1 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
3 * arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor
5 (ARM_ARCH_V8_2A): Likewise.
7 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
9 * aarch64.h (enum aarch64_opnd_qualifier): Add
10 AARCH64_OPND_QLF_V_2H.
12 2015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
14 * rx.h: Add new instructions.
16 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
18 * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
19 * aarch64-asm-2.c: Regenerate.
20 * aarch64-dis-2.c: Regenerate.
21 * aarch64-opc-2.c: Regenerate.
22 * aarch64-opc.c (aarch64_hint_options): Add "csync".
23 (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
24 * aarch64-tbl.h (aarch64_feature_stat_profile): New.
26 (aarch64_opcode_table): Add "psb".
27 (AARCH64_OPERANDS): Add "BARRIER_PSB".
29 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
31 * aarch64.h (aarch64_hint_options): Declare.
32 (aarch64_opnd_info): Add field hint_option.
34 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
36 * aarch64.h (AARCH64_FEATURE_PROFILE): New.
38 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
40 * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
42 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
44 * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
45 (aarch64_sys_ins_reg_has_xt): Declare.
47 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
49 * aarch64.h (AARCH64_FEATURE_RAS): New.
50 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
52 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
54 * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
56 (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
57 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
60 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
62 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
64 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
66 * aarch64.h (aarch64_op): Add OP_BFC.
68 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
70 * aarch64.h (AARCH64_FEATURE_F16): New.
71 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
74 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
76 * aarch64.h (AARCH64_FEATURE_V8_1): New.
77 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
79 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
81 * arm.h (ARM_EXT2_V8_2A): New.
82 (ARM_ARCH_V8_2A): New.
84 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
86 * aarch64.h (AARCH64_FEATURE_V8_2): New.
87 (AARCH64_ARCH_V8_2): New.
89 2015-11-11 Alan Modra <amodra@gmail.com>
90 Peter Bergner <bergner@vnet.ibm.com>
92 * ppc.h (PPC_OPCODE_POWER9): New define.
93 (PPC_OPCODE_VSX3): Likewise.
95 2015-11-02 Nick Clifton <nickc@redhat.com>
97 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
99 2015-11-02 Nick Clifton <nickc@redhat.com>
101 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
103 2015-10-28 Yao Qi <yao.qi@linaro.org>
105 * aarch64.h (aarch64_decode_insn): Update declaration.
107 2015-10-07 Yao Qi <yao.qi@linaro.org>
109 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
112 2015-10-07 Yao Qi <yao.qi@linaro.org>
114 * aarch64.h [__cplusplus]: Wrap in extern "C".
116 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
117 Cupertino Miranda <cmiranda@synopsys.com>
119 * arc-func.h: New file.
122 2015-10-02 Yao Qi <yao.qi@linaro.org>
124 * aarch64.h (aarch64_zero_register_p): Move the declaration
127 2015-10-02 Yao Qi <yao.qi@linaro.org>
129 * aarch64.h (aarch64_decode_insn): Declare it.
131 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
133 * s390.h (S390_INSTR_FLAG_HTM): New flag.
134 (S390_INSTR_FLAG_VX): New flag.
135 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
137 2015-09-23 Nick Clifton <nickc@redhat.com>
139 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
142 2015-09-22 Nick Clifton <nickc@redhat.com>
144 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
146 2015-09-09 Daniel Santos <daniel.santos@pobox.com>
148 * visium.h (gen_reg_table): Make static.
149 (fp_reg_table): Likewise.
150 (cc_table): Likewise.
152 2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
154 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
155 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
156 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
157 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
159 2015-07-03 Alan Modra <amodra@gmail.com>
161 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
163 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
164 Cesar Philippidis <cesar@codesourcery.com>
166 * nios2.h (enum iw_format_type): Add R2 formats.
167 (enum overflow_type): Add signed_immed12_overflow and
168 enumeration_overflow for R2.
169 (struct nios2_opcode): Document new argument letters for R2.
170 (REG_3BIT, REG_LDWM, REG_POP): Define.
171 (includes): Include nios2r2.h.
172 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
173 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
174 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
175 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
176 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
177 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
179 * nios2r2.h: New file.
181 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
183 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
184 (ppc_optional_operand_value): New inline function.
186 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
188 * aarch64.h (AARCH64_V8_1): New.
190 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
192 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
193 (ARM_ARCH_V8_1A): New.
194 (ARM_ARCH_V8_1A_FP): New.
195 (ARM_ARCH_V8_1A_SIMD): New.
196 (ARM_ARCH_V8_1A_CRYPTOV1): New.
197 (ARM_FEATURE_CORE): New.
199 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
201 * arm.h (ARM_EXT2_PAN): New.
202 (ARM_FEATURE_CORE_HIGH): New.
204 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
206 * arm.h (ARM_FEATURE_ALL): New.
208 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
210 * aarch64.h (AARCH64_FEATURE_RDMA): New.
212 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
214 * aarch64.h (AARCH64_FEATURE_LOR): New.
216 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
218 * aarch64.h (AARCH64_FEATURE_PAN): New.
219 (aarch64_sys_reg_supported_p): Declare.
220 (aarch64_pstatefield_supported_p): Declare.
222 2015-04-30 DJ Delorie <dj@redhat.com>
224 * rl78.h (RL78_Dis_Isa): New.
225 (rl78_decode_opcode): Add ISA parameter.
227 2015-03-24 Terry Guo <terry.guo@arm.com>
229 * arm.h (arm_feature_set): Extended to provide more available bits.
230 (ARM_ANY): Updated to follow above new definition.
231 (ARM_CPU_HAS_FEATURE): Likewise.
232 (ARM_CPU_IS_ANY): Likewise.
233 (ARM_MERGE_FEATURE_SETS): Likewise.
234 (ARM_CLEAR_FEATURE): Likewise.
235 (ARM_FEATURE): Likewise.
236 (ARM_FEATURE_COPY): New macro.
237 (ARM_FEATURE_EQUAL): Likewise.
238 (ARM_FEATURE_ZERO): Likewise.
239 (ARM_FEATURE_CORE_EQUAL): Likewise.
240 (ARM_FEATURE_LOW): Likewise.
241 (ARM_FEATURE_CORE_LOW): Likewise.
242 (ARM_FEATURE_CORE_COPROC): Likewise.
244 2015-02-19 Pedro Alves <palves@redhat.com>
246 * cgen.h [__cplusplus]: Wrap in extern "C".
247 * msp430-decode.h [__cplusplus]: Likewise.
248 * nios2.h [__cplusplus]: Likewise.
249 * rl78.h [__cplusplus]: Likewise.
250 * rx.h [__cplusplus]: Likewise.
251 * tilegx.h [__cplusplus]: Likewise.
253 2015-01-28 James Bowman <james.bowman@ftdichip.com>
257 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
259 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
261 2015-01-01 Alan Modra <amodra@gmail.com>
263 Update year range in copyright notice of all files.
265 2014-12-27 Anthony Green <green@moxielogic.com>
267 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
268 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
270 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
272 * visium.h: New file.
274 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
276 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
277 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
278 (NIOS2_INSN_OPTARG): Renumber.
280 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
282 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
283 declaration. Fix obsolete comment.
285 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
287 * nios2.h (enum iw_format_type): New.
288 (struct nios2_opcode): Update comments. Add size and format fields.
289 (NIOS2_INSN_OPTARG): New.
290 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
291 (struct nios2_reg): Add regtype field.
292 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
293 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
294 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
295 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
296 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
297 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
298 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
299 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
300 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
301 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
302 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
303 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
304 (OP_MASK_OP, OP_SH_OP): Delete.
305 (OP_MASK_IOP, OP_SH_IOP): Delete.
306 (OP_MASK_IRD, OP_SH_IRD): Delete.
307 (OP_MASK_IRT, OP_SH_IRT): Delete.
308 (OP_MASK_IRS, OP_SH_IRS): Delete.
309 (OP_MASK_ROP, OP_SH_ROP): Delete.
310 (OP_MASK_RRD, OP_SH_RRD): Delete.
311 (OP_MASK_RRT, OP_SH_RRT): Delete.
312 (OP_MASK_RRS, OP_SH_RRS): Delete.
313 (OP_MASK_JOP, OP_SH_JOP): Delete.
314 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
315 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
316 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
317 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
318 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
319 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
320 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
321 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
322 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
323 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
324 (OP_MASK_<insn>, OP_MASK): Delete.
325 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
326 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
327 Include nios2r1.h to define new instruction opcode constants
329 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
330 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
331 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
332 (NUMOPCODES, NUMREGISTERS): Delete.
333 * nios2r1.h: New file.
335 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
337 * sparc.h (HWCAP2_VIS3B): Documentation improved.
339 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
341 * sparc.h (sparc_opcode): new field `hwcaps2'.
342 (HWCAP2_FJATHPLUS): New define.
343 (HWCAP2_VIS3B): Likewise.
344 (HWCAP2_ADP): Likewise.
345 (HWCAP2_SPARC5): Likewise.
346 (HWCAP2_MWAIT): Likewise.
347 (HWCAP2_XMPMUL): Likewise.
348 (HWCAP2_XMONT): Likewise.
349 (HWCAP2_NSEC): Likewise.
350 (HWCAP2_FJATHHPC): Likewise.
351 (HWCAP2_FJDES): Likewise.
352 (HWCAP2_FJAES): Likewise.
353 Document the new operand kind `{', corresponding to the mcdper
354 ancillary state register.
355 Document the new operand kind }, which represents frsd floating
356 point registers (double precision) which must be the same than
357 frs1 in its containing instruction.
359 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
361 * nds32.h: Add new opcode declaration.
363 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
364 Matthew Fortune <matthew.fortune@imgtec.com>
366 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
367 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
368 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
369 +I, +O, +R, +:, +\, +", +;
370 (mips_check_prev_operand): New struct.
371 (INSN2_FORBIDDEN_SLOT): New define.
372 (INSN_ISA32R6): New define.
373 (INSN_ISA64R6): New define.
374 (INSN_UPTO32R6): New define.
375 (INSN_UPTO64R6): New define.
376 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
377 (ISA_MIPS32R6): New define.
378 (ISA_MIPS64R6): New define.
379 (CPU_MIPS32R6): New define.
380 (CPU_MIPS64R6): New define.
381 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
383 2014-09-03 Jiong Wang <jiong.wang@arm.com>
385 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
386 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
387 (aarch64_insn_class): Add lse_atomic.
388 (F_LSE_SZ): New field added.
389 (opcode_has_special_coder): Recognize F_LSE_SZ.
391 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
393 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
396 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
398 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
399 (INSN_LOAD_COPROC): New define.
400 (INSN_COPROC_MOVE_DELAY): Rename to...
401 (INSN_COPROC_MOVE): New define.
403 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
404 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
405 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
406 Soundararajan <Sounderarajan.D@atmel.com>
408 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
409 (AVR_ISA_2xxxa): Define ISA without LPM.
410 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
411 Add doc for contraint used in 16 bit lds/sts.
412 Adjust ISA group for icall, ijmp, pop and push.
413 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
415 2014-05-19 Nick Clifton <nickc@redhat.com>
417 * msp430.h (struct msp430_operand_s): Add vshift field.
419 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
421 * mips.h (INSN_ISA_MASK): Updated.
422 (INSN_ISA32R3): New define.
423 (INSN_ISA32R5): New define.
424 (INSN_ISA64R3): New define.
425 (INSN_ISA64R5): New define.
426 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
427 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
428 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
430 (INSN_UPTO32R3): New define.
431 (INSN_UPTO32R5): New define.
432 (INSN_UPTO64R3): New define.
433 (INSN_UPTO64R5): New define.
434 (ISA_MIPS32R3): New define.
435 (ISA_MIPS32R5): New define.
436 (ISA_MIPS64R3): New define.
437 (ISA_MIPS64R5): New define.
438 (CPU_MIPS32R3): New define.
439 (CPU_MIPS32R5): New define.
440 (CPU_MIPS64R3): New define.
441 (CPU_MIPS64R5): New define.
443 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
445 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
447 2014-04-22 Christian Svensson <blue@cmd.nu>
451 2014-03-05 Alan Modra <amodra@gmail.com>
453 Update copyright years.
455 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
457 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
460 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
461 Wei-Cheng Wang <cole945@gmail.com>
463 * nds32.h: New file for Andes NDS32.
465 2013-12-07 Mike Frysinger <vapier@gentoo.org>
467 * bfin.h: Remove +x file mode.
469 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
471 * aarch64.h (aarch64_pstatefields): Change element type to
474 2013-11-18 Renlin Li <Renlin.Li@arm.com>
476 * arm.h (ARM_AEXT_V7VE): New define.
477 (ARM_ARCH_V7VE): New define.
478 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
480 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
484 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
486 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
487 (aarch64_sys_reg_writeonly_p): Ditto.
489 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
491 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
492 (aarch64_sys_reg_writeonly_p): Ditto.
494 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
496 * aarch64.h (aarch64_sys_reg): New typedef.
497 (aarch64_sys_regs): Change to define with the new type.
498 (aarch64_sys_reg_deprecated_p): Declare.
500 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
502 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
503 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
505 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
507 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
508 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
509 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
510 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
511 For MIPS, update extension character sequences after +.
512 (ASE_MSA): New define.
513 (ASE_MSA64): New define.
514 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
515 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
516 For microMIPS, update extension character sequences after +.
518 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
523 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
525 * mips.h: Remove references to "+I" and imm2_expr.
527 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
529 * mips.h (M_DEXT, M_DINS): Delete.
531 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
533 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
534 (mips_optional_operand_p): New function.
536 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
537 Richard Sandiford <rdsandiford@googlemail.com>
539 * mips.h: Document new VU0 operand characters.
540 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
541 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
542 (OP_REG_R5900_ACC): New mips_reg_operand_types.
543 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
544 (mips_vu0_channel_mask): Declare.
546 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
548 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
549 (mips_int_operand_min, mips_int_operand_max): New functions.
550 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
552 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
554 * mips.h (mips_decode_reg_operand): New function.
555 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
556 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
557 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
559 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
560 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
561 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
562 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
563 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
564 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
565 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
566 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
567 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
568 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
569 macros to cover the gaps.
570 (INSN2_MOD_SP): Replace with...
571 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
572 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
573 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
574 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
575 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
578 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
580 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
581 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
582 (MIPS16_INSN_COND_BRANCH): Delete.
584 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
585 Kirill Yukhin <kirill.yukhin@intel.com>
586 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
588 * i386.h (BND_PREFIX_OPCODE): New.
590 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
592 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
593 OP_SAVE_RESTORE_LIST.
594 (decode_mips16_operand): Declare.
596 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
598 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
599 (mips_operand, mips_int_operand, mips_mapped_int_operand)
600 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
601 (mips_pcrel_operand): New structures.
602 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
603 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
604 (decode_mips_operand, decode_micromips_operand): Declare.
606 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
608 * mips.h: Document MIPS16 "I" opcode.
610 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
612 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
613 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
614 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
615 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
616 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
617 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
618 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
619 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
620 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
621 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
622 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
623 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
624 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
626 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
627 (M_USD_AB): ...these.
629 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
631 * mips.h: Remove documentation of "[" and "]". Update documentation
632 of "k" and the MDMX formats.
634 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
636 * mips.h: Update documentation of "+s" and "+S".
638 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
640 * mips.h: Document "+i".
642 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
644 * mips.h: Remove "mi" documentation. Update "mh" documentation.
645 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
647 (INSN2_WRITE_GPR_MHI): Rename to...
648 (INSN2_WRITE_GPR_MH): ...this.
650 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
652 * mips.h: Remove documentation of "+D" and "+T".
654 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
656 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
657 Use "source" rather than "destination" for microMIPS "G".
659 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
661 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
664 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
666 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
668 2013-06-17 Catherine Moore <clm@codesourcery.com>
669 Maciej W. Rozycki <macro@codesourcery.com>
670 Chao-Ying Fu <fu@mips.com>
672 * mips.h (OP_SH_EVAOFFSET): Define.
673 (OP_MASK_EVAOFFSET): Define.
674 (INSN_ASE_MASK): Delete.
676 (M_CACHEE_AB, M_CACHEE_OB): New.
677 (M_LBE_OB, M_LBE_AB): New.
678 (M_LBUE_OB, M_LBUE_AB): New.
679 (M_LHE_OB, M_LHE_AB): New.
680 (M_LHUE_OB, M_LHUE_AB): New.
681 (M_LLE_AB, M_LLE_OB): New.
682 (M_LWE_OB, M_LWE_AB): New.
683 (M_LWLE_AB, M_LWLE_OB): New.
684 (M_LWRE_AB, M_LWRE_OB): New.
685 (M_PREFE_AB, M_PREFE_OB): New.
686 (M_SCE_AB, M_SCE_OB): New.
687 (M_SBE_OB, M_SBE_AB): New.
688 (M_SHE_OB, M_SHE_AB): New.
689 (M_SWE_OB, M_SWE_AB): New.
690 (M_SWLE_AB, M_SWLE_OB): New.
691 (M_SWRE_AB, M_SWRE_OB): New.
692 (MICROMIPSOP_SH_EVAOFFSET): Define.
693 (MICROMIPSOP_MASK_EVAOFFSET): Define.
695 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
697 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
699 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
701 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
703 2013-05-09 Andrew Pinski <apinski@cavium.com>
705 * mips.h (OP_MASK_CODE10): Correct definition.
706 (OP_SH_CODE10): Likewise.
707 Add a comment that "+J" is used now for OP_*CODE10.
708 (INSN_ASE_MASK): Update.
709 (INSN_VIRT): New macro.
710 (INSN_VIRT64): New macro
712 2013-05-02 Nick Clifton <nickc@redhat.com>
714 * msp430.h: Add patterns for MSP430X instructions.
716 2013-04-06 David S. Miller <davem@davemloft.net>
718 * sparc.h (F_PREFERRED): Define.
719 (F_PREF_ALIAS): Define.
721 2013-04-03 Nick Clifton <nickc@redhat.com>
723 * v850.h (V850_INVERSE_PCREL): Define.
725 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
728 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
730 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
733 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
735 * tic6xc-opcode-table.h: Add 16-bit insns.
736 * tic6x.h: Add support for 16-bit insns.
738 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
740 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
741 and mov.b/w/l Rs,@(d:32,ERd).
743 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
746 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
747 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
748 tic6x_operand_xregpair operand coding type.
749 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
750 opcode field, usu ORXREGD1324 for the src2 operand and remove the
753 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
756 * tic6x.h (enum tic6x_coding_method): Add
757 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
758 separately the msb and lsb of a register pair. This is needed to
759 encode the opcodes in the same way as TI assembler does.
760 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
761 and rsqrdp opcodes to use the new field coding types.
763 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
765 * arm.h (CRC_EXT_ARMV8): New constant.
766 (ARCH_CRC_ARMV8): New macro.
768 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
770 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
772 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
773 Andrew Jenner <andrew@codesourcery.com>
775 Based on patches from Altera Corporation.
779 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
781 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
783 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
786 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
788 2013-01-24 Nick Clifton <nickc@redhat.com>
790 * v850.h: Add e3v5 support.
792 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
794 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
796 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
798 * ppc.h (PPC_OPCODE_POWER8): New define.
799 (PPC_OPCODE_HTM): Likewise.
801 2013-01-10 Will Newton <will.newton@imgtec.com>
805 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
807 * cr16.h (make_instruction): Rename to cr16_make_instruction.
808 (match_opcode): Rename to cr16_match_opcode.
810 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
812 * mips.h: Add support for r5900 instructions including lq and sq.
814 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
816 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
817 (make_instruction,match_opcode): Added function prototypes.
818 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
820 2012-11-23 Alan Modra <amodra@gmail.com>
822 * ppc.h (ppc_parse_cpu): Update prototype.
824 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
826 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
827 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
829 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
831 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
833 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
835 * ia64.h (ia64_opnd): Add new operand types.
837 2012-08-21 David S. Miller <davem@davemloft.net>
839 * sparc.h (F3F4): New macro.
841 2012-08-13 Ian Bolton <ian.bolton@arm.com>
842 Laurent Desnogues <laurent.desnogues@arm.com>
843 Jim MacArthur <jim.macarthur@arm.com>
844 Marcus Shawcroft <marcus.shawcroft@arm.com>
845 Nigel Stephens <nigel.stephens@arm.com>
846 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
847 Richard Earnshaw <rearnsha@arm.com>
848 Sofiane Naci <sofiane.naci@arm.com>
849 Tejas Belagod <tejas.belagod@arm.com>
850 Yufeng Zhang <yufeng.zhang@arm.com>
852 * aarch64.h: New file.
854 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
855 Maciej W. Rozycki <macro@codesourcery.com>
857 * mips.h (mips_opcode): Add the exclusions field.
858 (OPCODE_IS_MEMBER): Remove macro.
859 (cpu_is_member): New inline function.
860 (opcode_is_member): Likewise.
862 2012-07-31 Chao-Ying Fu <fu@mips.com>
863 Catherine Moore <clm@codesourcery.com>
864 Maciej W. Rozycki <macro@codesourcery.com>
866 * mips.h: Document microMIPS DSP ASE usage.
867 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
868 microMIPS DSP ASE support.
869 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
870 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
871 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
872 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
873 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
874 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
875 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
877 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
879 * mips.h: Fix a typo in description.
881 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
883 * avr.h: (AVR_ISA_XCH): New define.
884 (AVR_ISA_XMEGA): Use it.
885 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
887 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
889 * m68hc11.h: Add XGate definitions.
890 (struct m68hc11_opcode): Add xg_mask field.
892 2012-05-14 Catherine Moore <clm@codesourcery.com>
893 Maciej W. Rozycki <macro@codesourcery.com>
894 Rhonda Wittels <rhonda@codesourcery.com>
896 * ppc.h (PPC_OPCODE_VLE): New definition.
897 (PPC_OP_SA): New macro.
898 (PPC_OP_SE_VLE): New macro.
899 (PPC_OP): Use a variable shift amount.
900 (powerpc_operand): Update comments.
901 (PPC_OPSHIFT_INV): New macro.
902 (PPC_OPERAND_CR): Replace with...
903 (PPC_OPERAND_CR_BIT): ...this and
904 (PPC_OPERAND_CR_REG): ...this.
907 2012-05-03 Sean Keys <skeys@ipdatasys.com>
909 * xgate.h: Header file for XGATE assembler.
911 2012-04-27 David S. Miller <davem@davemloft.net>
913 * sparc.h: Document new arg code' )' for crypto RS3
916 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
917 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
918 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
919 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
920 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
921 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
922 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
923 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
924 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
925 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
926 HWCAP_CBCOND, HWCAP_CRC32): New defines.
928 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
930 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
932 2012-02-27 Alan Modra <amodra@gmail.com>
934 * crx.h (cst4_map): Update declaration.
936 2012-02-25 Walter Lee <walt@tilera.com>
938 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
940 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
941 TILEPRO_OPC_LW_TLS_SN.
943 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
945 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
946 (XRELEASE_PREFIX_OPCODE): Likewise.
948 2011-12-08 Andrew Pinski <apinski@cavium.com>
949 Adam Nemet <anemet@caviumnetworks.com>
951 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
952 (INSN_OCTEON2): New macro.
953 (CPU_OCTEON2): New macro.
954 (OPCODE_IS_MEMBER): Add Octeon2.
956 2011-11-29 Andrew Pinski <apinski@cavium.com>
958 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
959 (INSN_OCTEONP): New macro.
960 (CPU_OCTEONP): New macro.
961 (OPCODE_IS_MEMBER): Add Octeon+.
962 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
964 2011-11-01 DJ Delorie <dj@redhat.com>
968 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
970 * mips.h: Fix a typo in description.
972 2011-09-21 David S. Miller <davem@davemloft.net>
974 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
975 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
976 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
977 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
979 2011-08-09 Chao-ying Fu <fu@mips.com>
980 Maciej W. Rozycki <macro@codesourcery.com>
982 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
983 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
984 (INSN_ASE_MASK): Add the MCU bit.
985 (INSN_MCU): New macro.
986 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
987 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
989 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
991 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
992 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
993 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
994 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
995 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
996 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
997 (INSN2_READ_GPR_MMN): Likewise.
998 (INSN2_READ_FPR_D): Change the bit used.
999 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
1000 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
1001 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
1002 (INSN2_COND_BRANCH): Likewise.
1003 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
1004 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
1005 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
1006 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
1007 (INSN2_MOD_GPR_MN): Likewise.
1009 2011-08-05 David S. Miller <davem@davemloft.net>
1011 * sparc.h: Document new format codes '4', '5', and '('.
1012 (OPF_LOW4, RS3): New macros.
1014 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
1016 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
1017 order of flags documented.
1019 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
1021 * mips.h: Clarify the description of microMIPS instruction
1022 manipulation macros.
1023 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
1025 2011-07-24 Chao-ying Fu <fu@mips.com>
1026 Maciej W. Rozycki <macro@codesourcery.com>
1028 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
1029 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
1030 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
1031 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
1032 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
1033 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
1034 (OP_MASK_RS3, OP_SH_RS3): Likewise.
1035 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
1036 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
1037 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
1038 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
1039 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
1040 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
1041 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
1042 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
1043 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
1044 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
1045 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
1046 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
1047 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
1048 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
1049 (INSN_WRITE_GPR_S): New macro.
1050 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
1051 (INSN2_READ_FPR_D): Likewise.
1052 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
1053 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
1054 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
1055 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
1056 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
1057 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
1058 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1059 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1060 (CPU_MICROMIPS): New macro.
1061 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1062 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1063 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1064 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1065 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1066 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1067 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1068 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1069 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1070 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1071 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1072 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1073 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1074 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1075 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1076 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1077 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1078 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1079 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1080 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1081 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1082 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1083 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1084 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1085 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1086 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1087 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1088 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1089 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1090 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1091 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1092 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1093 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1094 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1095 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1096 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1097 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1098 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1099 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1100 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1101 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1102 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1103 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1104 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1105 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1106 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1107 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1108 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1109 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1110 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1111 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1112 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1113 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1114 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1115 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1116 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1117 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1118 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1119 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1120 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1121 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1122 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1123 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1124 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1125 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1126 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1127 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1128 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1129 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1130 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1131 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1132 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1133 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1134 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1135 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1136 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1137 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1138 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1139 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1140 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1141 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1142 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1143 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1144 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1145 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1146 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1147 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1148 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1149 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1150 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1151 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1152 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1153 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1154 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1155 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1156 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1157 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1158 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1159 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1160 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1161 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1162 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1163 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1164 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1165 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1166 (micromips_opcodes): New declaration.
1167 (bfd_micromips_num_opcodes): Likewise.
1169 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1171 * mips.h (INSN_TRAP): Rename to...
1172 (INSN_NO_DELAY_SLOT): ... this.
1173 (INSN_SYNC): Remove macro.
1175 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1177 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1178 a duplicate of AVR_ISA_SPM.
1180 2011-07-01 Nick Clifton <nickc@redhat.com>
1182 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1184 2011-06-18 Robin Getz <robin.getz@analog.com>
1186 * bfin.h (is_macmod_signed): New func
1188 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1190 * bfin.h (is_macmod_pmove): Add missing space before func args.
1191 (is_macmod_hmove): Likewise.
1193 2011-06-13 Walter Lee <walt@tilera.com>
1195 * tilegx.h: New file.
1196 * tilepro.h: New file.
1198 2011-05-31 Paul Brook <paul@codesourcery.com>
1200 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1202 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1204 * s390.h: Replace S390_OPERAND_REG_EVEN with
1205 S390_OPERAND_REG_PAIR.
1207 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1209 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1211 2011-04-18 Julian Brown <julian@codesourcery.com>
1213 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1215 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1218 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1220 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1222 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1223 New instruction set flags.
1224 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1226 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1228 * mips.h (M_PREF_AB): New enum value.
1230 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1232 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1234 (is_macmod_pmove, is_macmod_hmove): New functions.
1236 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1238 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1240 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1242 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1243 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1245 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1248 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1251 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1254 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1256 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1258 * mips.h: Update commentary after last commit.
1260 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1262 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1263 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1264 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1266 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1268 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1270 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1272 * mips.h: Fix previous commit.
1274 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1276 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1277 (INSN_LOONGSON_3A): Clear bit 31.
1279 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1282 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1283 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1284 (ARM_ARCH_V6M_ONLY): New define.
1286 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1288 * mips.h (INSN_LOONGSON_3A): Defined.
1289 (CPU_LOONGSON_3A): Defined.
1290 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1292 2010-10-09 Matt Rice <ratmice@gmail.com>
1294 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1295 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1297 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1299 * arm.h (ARM_EXT_VIRT): New define.
1300 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1301 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1304 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1306 * arm.h (ARM_AEXT_ADIV): New define.
1307 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1309 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1311 * arm.h (ARM_EXT_OS): New define.
1312 (ARM_AEXT_V6SM): Likewise.
1313 (ARM_ARCH_V6SM): Likewise.
1315 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1317 * arm.h (ARM_EXT_MP): Add.
1318 (ARM_ARCH_V7A_MP): Likewise.
1320 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1322 * bfin.h: Declare pseudoChr structs/defines.
1324 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1326 * bfin.h: Strip trailing whitespace.
1328 2010-07-29 DJ Delorie <dj@redhat.com>
1330 * rx.h (RX_Operand_Type): Add TwoReg.
1331 (RX_Opcode_ID): Remove ediv and ediv2.
1333 2010-07-27 DJ Delorie <dj@redhat.com>
1335 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1337 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1338 Ina Pandit <ina.pandit@kpitcummins.com>
1340 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1341 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1342 PROCESSOR_V850E2_ALL.
1343 Remove PROCESSOR_V850EA support.
1344 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1345 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1346 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1347 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1348 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1349 V850_OPERAND_PERCENT.
1350 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1352 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1355 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1357 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1358 (MIPS16_INSN_BRANCH): Rename to...
1359 (MIPS16_INSN_COND_BRANCH): ... this.
1361 2010-07-03 Alan Modra <amodra@gmail.com>
1363 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1364 Renumber other PPC_OPCODE defines.
1366 2010-07-03 Alan Modra <amodra@gmail.com>
1368 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1370 2010-06-29 Alan Modra <amodra@gmail.com>
1372 * maxq.h: Delete file.
1374 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1376 * ppc.h (PPC_OPCODE_E500): Define.
1378 2010-05-26 Catherine Moore <clm@codesourcery.com>
1380 * opcode/mips.h (INSN_MIPS16): Remove.
1382 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1384 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1386 2010-04-15 Nick Clifton <nickc@redhat.com>
1388 * alpha.h: Update copyright notice to use GPLv3.
1394 * convex.h: Likewise.
1401 * h8300.h: Likewise.
1408 * m68hc11.h: Likewise.
1414 * mn10200.h: Likewise.
1415 * mn10300.h: Likewise.
1416 * msp430.h: Likewise.
1418 * ns32k.h: Likewise.
1420 * pdp11.h: Likewise.
1427 * score-datadep.h: Likewise.
1428 * score-inst.h: Likewise.
1429 * sparc.h: Likewise.
1430 * spu-insns.h: Likewise.
1432 * tic30.h: Likewise.
1433 * tic4x.h: Likewise.
1434 * tic54x.h: Likewise.
1435 * tic80.h: Likewise.
1439 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1441 * tic6x-control-registers.h, tic6x-insn-formats.h,
1442 tic6x-opcode-table.h, tic6x.h: New.
1444 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1446 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1448 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1450 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1452 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1454 * ia64.h (ia64_find_opcode): Remove argument name.
1455 (ia64_find_next_opcode): Likewise.
1456 (ia64_dis_opcode): Likewise.
1457 (ia64_free_opcode): Likewise.
1458 (ia64_find_dependency): Likewise.
1460 2009-11-22 Doug Evans <dje@sebabeach.org>
1462 * cgen.h: Include bfd_stdint.h.
1463 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1465 2009-11-18 Paul Brook <paul@codesourcery.com>
1467 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1469 2009-11-17 Paul Brook <paul@codesourcery.com>
1470 Daniel Jacobowitz <dan@codesourcery.com>
1472 * arm.h (ARM_EXT_V6_DSP): Define.
1473 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1474 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1476 2009-11-04 DJ Delorie <dj@redhat.com>
1478 * rx.h (rx_decode_opcode) (mvtipl): Add.
1479 (mvtcp, mvfcp, opecp): Remove.
1481 2009-11-02 Paul Brook <paul@codesourcery.com>
1483 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1484 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1485 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1486 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1487 FPU_ARCH_NEON_VFP_V4): Define.
1489 2009-10-23 Doug Evans <dje@sebabeach.org>
1491 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1492 * cgen.h: Update. Improve multi-inclusion macro name.
1494 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1496 * ppc.h (PPC_OPCODE_476): Define.
1498 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1500 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1502 2009-09-29 DJ Delorie <dj@redhat.com>
1506 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1508 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1510 2009-09-21 Ben Elliston <bje@au.ibm.com>
1512 * ppc.h (PPC_OPCODE_PPCA2): New.
1514 2009-09-05 Martin Thuresson <martin@mtme.org>
1516 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1518 2009-08-29 Martin Thuresson <martin@mtme.org>
1520 * tic30.h (template): Rename type template to
1521 insn_template. Updated code to use new name.
1522 * tic54x.h (template): Rename type template to
1525 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1527 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1529 2009-06-11 Anthony Green <green@moxielogic.com>
1531 * moxie.h (MOXIE_F3_PCREL): Define.
1532 (moxie_form3_opc_info): Grow.
1534 2009-06-06 Anthony Green <green@moxielogic.com>
1536 * moxie.h (MOXIE_F1_M): Define.
1538 2009-04-15 Anthony Green <green@moxielogic.com>
1542 2009-04-06 DJ Delorie <dj@redhat.com>
1544 * h8300.h: Add relaxation attributes to MOVA opcodes.
1546 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1548 * ppc.h (ppc_parse_cpu): Declare.
1550 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1552 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1553 and _IMM11 for mbitclr and mbitset.
1554 * score-datadep.h: Update dependency information.
1556 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1558 * ppc.h (PPC_OPCODE_POWER7): New.
1560 2009-02-06 Doug Evans <dje@google.com>
1562 * i386.h: Add comment regarding sse* insns and prefixes.
1564 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1566 * mips.h (INSN_XLR): Define.
1567 (INSN_CHIP_MASK): Update.
1569 (OPCODE_IS_MEMBER): Update.
1570 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1572 2009-01-28 Doug Evans <dje@google.com>
1574 * opcode/i386.h: Add multiple inclusion protection.
1575 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1576 (EDI_REG_NUM): New macros.
1577 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1578 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1579 (REX_PREFIX_P): New macro.
1581 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1583 * ppc.h (struct powerpc_opcode): New field "deprecated".
1584 (PPC_OPCODE_NOPOWER4): Delete.
1586 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1588 * mips.h: Define CPU_R14000, CPU_R16000.
1589 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1591 2008-11-18 Catherine Moore <clm@codesourcery.com>
1593 * arm.h (FPU_NEON_FP16): New.
1594 (FPU_ARCH_NEON_FP16): New.
1596 2008-11-06 Chao-ying Fu <fu@mips.com>
1598 * mips.h: Doucument '1' for 5-bit sync type.
1600 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1602 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1605 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1607 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1609 2008-07-30 Michael J. Eager <eager@eagercon.com>
1611 * ppc.h (PPC_OPCODE_405): Define.
1612 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1614 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1616 * ppc.h (ppc_cpu_t): New typedef.
1617 (struct powerpc_opcode <flags>): Use it.
1618 (struct powerpc_operand <insert, extract>): Likewise.
1619 (struct powerpc_macro <flags>): Likewise.
1621 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1623 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1624 Update comment before MIPS16 field descriptors to mention MIPS16.
1625 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1627 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1628 New bit masks and shift counts for cins and exts.
1630 * mips.h: Document new field descriptors +Q.
1631 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1633 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1635 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1636 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1638 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1640 * ppc.h: (PPC_OPCODE_E500MC): New.
1642 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1644 * i386.h (MAX_OPERANDS): Set to 5.
1645 (MAX_MNEM_SIZE): Changed to 20.
1647 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1649 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1651 2008-03-09 Paul Brook <paul@codesourcery.com>
1653 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1655 2008-03-04 Paul Brook <paul@codesourcery.com>
1657 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1658 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1659 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1661 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1662 Nick Clifton <nickc@redhat.com>
1665 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1666 with a 32-bit displacement but without the top bit of the 4th byte
1669 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1671 * cr16.h (cr16_num_optab): Declared.
1673 2008-02-14 Hakan Ardo <hakan@debian.org>
1676 * avr.h (AVR_ISA_2xxe): Define.
1678 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1680 * mips.h: Update copyright.
1681 (INSN_CHIP_MASK): New macro.
1682 (INSN_OCTEON): New macro.
1683 (CPU_OCTEON): New macro.
1684 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1686 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1688 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1690 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1692 * avr.h (AVR_ISA_USB162): Add new opcode set.
1693 (AVR_ISA_AVR3): Likewise.
1695 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1697 * mips.h (INSN_LOONGSON_2E): New.
1698 (INSN_LOONGSON_2F): New.
1699 (CPU_LOONGSON_2E): New.
1700 (CPU_LOONGSON_2F): New.
1701 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1703 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1705 * mips.h (INSN_ISA*): Redefine certain values as an
1706 enumeration. Update comments.
1707 (mips_isa_table): New.
1708 (ISA_MIPS*): Redefine to match enumeration.
1709 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1712 2007-08-08 Ben Elliston <bje@au.ibm.com>
1714 * ppc.h (PPC_OPCODE_PPCPS): New.
1716 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1718 * m68k.h: Document j K & E.
1720 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1722 * cr16.h: New file for CR16 target.
1724 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1726 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1728 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1730 * m68k.h (mcfisa_c): New.
1731 (mcfusp, mcf_mask): Adjust.
1733 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1735 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1736 (num_powerpc_operands): Declare.
1737 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1738 (PPC_OPERAND_PLUS1): Define.
1740 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1742 * i386.h (REX_MODE64): Renamed to ...
1744 (REX_EXTX): Renamed to ...
1746 (REX_EXTY): Renamed to ...
1748 (REX_EXTZ): Renamed to ...
1751 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1753 * i386.h: Add entries from config/tc-i386.h and move tables
1754 to opcodes/i386-opc.h.
1756 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1758 * i386.h (FloatDR): Removed.
1759 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1761 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1763 * spu-insns.h: Add soma double-float insns.
1765 2007-02-20 Thiemo Seufer <ths@mips.com>
1766 Chao-Ying Fu <fu@mips.com>
1768 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1769 (INSN_DSPR2): Add flag for DSP R2 instructions.
1770 (M_BALIGN): New macro.
1772 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1774 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1775 and Seg3ShortFrom with Shortform.
1777 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1780 * i386.h (i386_optab): Put the real "test" before the pseudo
1783 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1785 * m68k.h (m68010up): OR fido_a.
1787 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1789 * m68k.h (fido_a): New.
1791 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1793 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1794 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1797 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1799 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1801 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1803 * score-inst.h (enum score_insn_type): Add Insn_internal.
1805 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1806 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1807 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1808 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1809 Alan Modra <amodra@bigpond.net.au>
1811 * spu-insns.h: New file.
1814 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1816 * ppc.h (PPC_OPCODE_CELL): Define.
1818 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1820 * i386.h : Modify opcode to support for the change in POPCNT opcode
1821 in amdfam10 architecture.
1823 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1825 * i386.h: Replace CpuMNI with CpuSSSE3.
1827 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1828 Joseph Myers <joseph@codesourcery.com>
1829 Ian Lance Taylor <ian@wasabisystems.com>
1830 Ben Elliston <bje@wasabisystems.com>
1832 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1834 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1836 * score-datadep.h: New file.
1837 * score-inst.h: New file.
1839 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1841 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1842 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1843 movdq2q and movq2dq.
1845 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1846 Michael Meissner <michael.meissner@amd.com>
1848 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1850 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1852 * i386.h (i386_optab): Add "nop" with memory reference.
1854 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1856 * i386.h (i386_optab): Update comment for 64bit NOP.
1858 2006-06-06 Ben Elliston <bje@au.ibm.com>
1859 Anton Blanchard <anton@samba.org>
1861 * ppc.h (PPC_OPCODE_POWER6): Define.
1864 2006-06-05 Thiemo Seufer <ths@mips.com>
1866 * mips.h: Improve description of MT flags.
1868 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1870 * m68k.h (mcf_mask): Define.
1872 2006-05-05 Thiemo Seufer <ths@mips.com>
1873 David Ung <davidu@mips.com>
1875 * mips.h (enum): Add macro M_CACHE_AB.
1877 2006-05-04 Thiemo Seufer <ths@mips.com>
1878 Nigel Stephens <nigel@mips.com>
1879 David Ung <davidu@mips.com>
1881 * mips.h: Add INSN_SMARTMIPS define.
1883 2006-04-30 Thiemo Seufer <ths@mips.com>
1884 David Ung <davidu@mips.com>
1886 * mips.h: Defines udi bits and masks. Add description of
1887 characters which may appear in the args field of udi
1890 2006-04-26 Thiemo Seufer <ths@networkno.de>
1892 * mips.h: Improve comments describing the bitfield instruction
1895 2006-04-26 Julian Brown <julian@codesourcery.com>
1897 * arm.h (FPU_VFP_EXT_V3): Define constant.
1898 (FPU_NEON_EXT_V1): Likewise.
1899 (FPU_VFP_HARD): Update.
1900 (FPU_VFP_V3): Define macro.
1901 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1903 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1905 * avr.h (AVR_ISA_PWMx): New.
1907 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1909 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1910 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1911 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1912 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1913 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1915 2006-03-10 Paul Brook <paul@codesourcery.com>
1917 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1919 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1921 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1922 first. Correct mask of bb "B" opcode.
1924 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1926 * i386.h (i386_optab): Support Intel Merom New Instructions.
1928 2006-02-24 Paul Brook <paul@codesourcery.com>
1930 * arm.h: Add V7 feature bits.
1932 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1934 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1936 2006-01-31 Paul Brook <paul@codesourcery.com>
1937 Richard Earnshaw <rearnsha@arm.com>
1939 * arm.h: Use ARM_CPU_FEATURE.
1940 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1941 (arm_feature_set): Change to a structure.
1942 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1943 ARM_FEATURE): New macros.
1945 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1947 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1948 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1949 (ADD_PC_INCR_OPCODE): Don't define.
1951 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1954 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1956 2005-11-14 David Ung <davidu@mips.com>
1958 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1959 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1960 save/restore encoding of the args field.
1962 2005-10-28 Dave Brolley <brolley@redhat.com>
1964 Contribute the following changes:
1965 2005-02-16 Dave Brolley <brolley@redhat.com>
1967 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1968 cgen_isa_mask_* to cgen_bitset_*.
1971 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1973 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1974 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1975 (CGEN_CPU_TABLE): Make isas a ponter.
1977 2003-09-29 Dave Brolley <brolley@redhat.com>
1979 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1980 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1981 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1983 2002-12-13 Dave Brolley <brolley@redhat.com>
1985 * cgen.h (symcat.h): #include it.
1986 (cgen-bitset.h): #include it.
1987 (CGEN_ATTR_VALUE_TYPE): Now a union.
1988 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1989 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1990 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1991 * cgen-bitset.h: New file.
1993 2005-09-30 Catherine Moore <clm@cm00re.com>
1997 2005-10-24 Jan Beulich <jbeulich@novell.com>
1999 * ia64.h (enum ia64_opnd): Move memory operand out of set of
2002 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2004 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
2005 Add FLAG_STRICT to pa10 ftest opcode.
2007 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2009 * hppa.h (pa_opcodes): Remove lha entries.
2011 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2013 * hppa.h (FLAG_STRICT): Revise comment.
2014 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
2015 before corresponding pa11 opcodes. Add strict pa10 register-immediate
2018 2005-09-30 Catherine Moore <clm@cm00re.com>
2022 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2024 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
2026 2005-09-06 Chao-ying Fu <fu@mips.com>
2028 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
2029 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
2031 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
2032 (INSN_ASE_MASK): Update to include INSN_MT.
2033 (INSN_MT): New define for MT ASE.
2035 2005-08-25 Chao-ying Fu <fu@mips.com>
2037 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
2038 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
2039 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
2040 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
2041 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
2042 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
2044 (INSN_DSP): New define for DSP ASE.
2046 2005-08-18 Alan Modra <amodra@bigpond.net.au>
2050 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
2052 * ppc.h (PPC_OPCODE_E300): Define.
2054 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
2056 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
2058 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2061 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2064 2005-07-27 Jan Beulich <jbeulich@novell.com>
2066 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2067 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2068 Add movq-s as 64-bit variants of movd-s.
2070 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2072 * hppa.h: Fix punctuation in comment.
2074 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2075 implicit space-register addressing. Set space-register bits on opcodes
2076 using implicit space-register addressing. Add various missing pa20
2077 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2078 space-register addressing. Use "fE" instead of "fe" in various
2081 2005-07-18 Jan Beulich <jbeulich@novell.com>
2083 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2085 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2087 * i386.h (i386_optab): Support Intel VMX Instructions.
2089 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2091 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2093 2005-07-05 Jan Beulich <jbeulich@novell.com>
2095 * i386.h (i386_optab): Add new insns.
2097 2005-07-01 Nick Clifton <nickc@redhat.com>
2099 * sparc.h: Add typedefs to structure declarations.
2101 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2104 * i386.h (i386_optab): Update comments for 64bit addressing on
2105 mov. Allow 64bit addressing for mov and movq.
2107 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2109 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2110 respectively, in various floating-point load and store patterns.
2112 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2114 * hppa.h (FLAG_STRICT): Correct comment.
2115 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2116 PA 2.0 mneumonics when equivalent. Entries with cache control
2117 completers now require PA 1.1. Adjust whitespace.
2119 2005-05-19 Anton Blanchard <anton@samba.org>
2121 * ppc.h (PPC_OPCODE_POWER5): Define.
2123 2005-05-10 Nick Clifton <nickc@redhat.com>
2125 * Update the address and phone number of the FSF organization in
2126 the GPL notices in the following files:
2127 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2128 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2129 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2130 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2131 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2132 tic54x.h, tic80.h, v850.h, vax.h
2134 2005-05-09 Jan Beulich <jbeulich@novell.com>
2136 * i386.h (i386_optab): Add ht and hnt.
2138 2005-04-18 Mark Kettenis <kettenis@gnu.org>
2140 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2141 Add xcrypt-ctr. Provide aliases without hyphens.
2143 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2145 Moved from ../ChangeLog
2147 2005-04-12 Paul Brook <paul@codesourcery.com>
2148 * m88k.h: Rename psr macros to avoid conflicts.
2150 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2151 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2152 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2153 and ARM_ARCH_V6ZKT2.
2155 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2156 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2157 Remove redundant instruction types.
2158 (struct argument): X_op - new field.
2159 (struct cst4_entry): Remove.
2160 (no_op_insn): Declare.
2162 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2163 * crx.h (enum argtype): Rename types, remove unused types.
2165 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2166 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2167 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2168 (enum operand_type): Rearrange operands, edit comments.
2169 replace us<N> with ui<N> for unsigned immediate.
2170 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2171 displacements (respectively).
2172 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2173 (instruction type): Add NO_TYPE_INS.
2174 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2175 (operand_entry): New field - 'flags'.
2176 (operand flags): New.
2178 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2179 * crx.h (operand_type): Remove redundant types i3, i4,
2181 Add new unsigned immediate types us3, us4, us5, us16.
2183 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2185 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2186 adjust them accordingly.
2188 2005-04-01 Jan Beulich <jbeulich@novell.com>
2190 * i386.h (i386_optab): Add rdtscp.
2192 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2194 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2195 between memory and segment register. Allow movq for moving between
2196 general-purpose register and segment register.
2198 2005-02-09 Jan Beulich <jbeulich@novell.com>
2201 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2202 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2205 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2207 * m68k.h (m68008, m68ec030, m68882): Remove.
2209 (cpu_m68k, cpu_cf): New.
2210 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2211 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2213 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2215 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2216 * cgen.h (enum cgen_parse_operand_type): Add
2217 CGEN_PARSE_OPERAND_SYMBOLIC.
2219 2005-01-21 Fred Fish <fnf@specifixinc.com>
2221 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2222 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2223 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2225 2005-01-19 Fred Fish <fnf@specifixinc.com>
2227 * mips.h (struct mips_opcode): Add new pinfo2 member.
2228 (INSN_ALIAS): New define for opcode table entries that are
2229 specific instances of another entry, such as 'move' for an 'or'
2230 with a zero operand.
2231 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2232 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2234 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2236 * mips.h (CPU_RM9000): Define.
2237 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2239 2004-11-25 Jan Beulich <jbeulich@novell.com>
2241 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2242 to/from test registers are illegal in 64-bit mode. Add missing
2243 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2244 (previously one had to explicitly encode a rex64 prefix). Re-enable
2245 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2246 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2248 2004-11-23 Jan Beulich <jbeulich@novell.com>
2250 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2251 available only with SSE2. Change the MMX additions introduced by SSE
2252 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2253 instructions by their now designated identifier (since combining i686
2254 and 3DNow! does not really imply 3DNow!A).
2256 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2258 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2259 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2261 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2262 Vineet Sharma <vineets@noida.hcltech.com>
2264 * maxq.h: New file: Disassembly information for the maxq port.
2266 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2268 * i386.h (i386_optab): Put back "movzb".
2270 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2272 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2273 comments. Remove member cris_ver_sim. Add members
2274 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2275 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2276 (struct cris_support_reg, struct cris_cond15): New types.
2277 (cris_conds15): Declare.
2278 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2279 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2280 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2281 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2282 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2283 SIZE_FIELD_UNSIGNED.
2285 2004-11-04 Jan Beulich <jbeulich@novell.com>
2287 * i386.h (sldx_Suf): Remove.
2288 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2289 (q_FP): Define, implying no REX64.
2290 (x_FP, sl_FP): Imply FloatMF.
2291 (i386_optab): Split reg and mem forms of moving from segment registers
2292 so that the memory forms can ignore the 16-/32-bit operand size
2293 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2294 all non-floating-point instructions. Unite 32- and 64-bit forms of
2295 movsx, movzx, and movd. Adjust floating point operations for the above
2296 changes to the *FP macros. Add DefaultSize to floating point control
2297 insns operating on larger memory ranges. Remove left over comments
2298 hinting at certain insns being Intel-syntax ones where the ones
2299 actually meant are already gone.
2301 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2303 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2306 2004-09-30 Paul Brook <paul@codesourcery.com>
2308 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2309 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2311 2004-09-11 Theodore A. Roth <troth@openavr.org>
2313 * avr.h: Add support for
2314 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2316 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2318 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2320 2004-08-24 Dmitry Diky <diwil@spec.ru>
2322 * msp430.h (msp430_opc): Add new instructions.
2323 (msp430_rcodes): Declare new instructions.
2324 (msp430_hcodes): Likewise..
2326 2004-08-13 Nick Clifton <nickc@redhat.com>
2329 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2332 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2334 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2336 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2338 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2340 2004-07-21 Jan Beulich <jbeulich@novell.com>
2342 * i386.h: Adjust instruction descriptions to better match the
2345 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2347 * arm.h: Remove all old content. Replace with architecture defines
2348 from gas/config/tc-arm.c.
2350 2004-07-09 Andreas Schwab <schwab@suse.de>
2352 * m68k.h: Fix comment.
2354 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2358 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2360 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2362 2004-05-24 Peter Barada <peter@the-baradas.com>
2364 * m68k.h: Add 'size' to m68k_opcode.
2366 2004-05-05 Peter Barada <peter@the-baradas.com>
2368 * m68k.h: Switch from ColdFire chip name to core variant.
2370 2004-04-22 Peter Barada <peter@the-baradas.com>
2372 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2373 descriptions for new EMAC cases.
2374 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2375 handle Motorola MAC syntax.
2376 Allow disassembly of ColdFire V4e object files.
2378 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2380 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2382 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2384 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2386 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2388 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2390 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2392 * i386.h (i386_optab): Added xstore/xcrypt insns.
2394 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2396 * h8300.h (32bit ldc/stc): Add relaxing support.
2398 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2400 * h8300.h (BITOP): Pass MEMRELAX flag.
2402 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2404 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2407 For older changes see ChangeLog-9103
2409 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2411 Copying and distribution of this file, with or without modification,
2412 are permitted in any medium without royalty provided the copyright
2413 notice and this notice are preserved.
2419 version-control: never
projects / external / binutils.git / blob