1 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
2 Matthew Fortune <matthew.fortune@imgtec.com>
4 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
5 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
6 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
7 +I, +O, +R, +:, +\, +", +;
8 (mips_check_prev_operand): New struct.
9 (INSN2_FORBIDDEN_SLOT): New define.
10 (INSN_ISA32R6): New define.
11 (INSN_ISA64R6): New define.
12 (INSN_UPTO32R6): New define.
13 (INSN_UPTO64R6): New define.
14 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
15 (ISA_MIPS32R6): New define.
16 (ISA_MIPS64R6): New define.
17 (CPU_MIPS32R6): New define.
18 (CPU_MIPS64R6): New define.
19 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
21 2014-09-03 Jiong Wang <jiong.wang@arm.com>
23 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
24 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
25 (aarch64_insn_class): Add lse_atomic.
26 (F_LSE_SZ): New field added.
27 (opcode_has_special_coder): Recognize F_LSE_SZ.
29 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
31 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
34 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
36 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
37 (INSN_LOAD_COPROC): New define.
38 (INSN_COPROC_MOVE_DELAY): Rename to...
39 (INSN_COPROC_MOVE): New define.
41 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
42 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
43 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
44 Soundararajan <Sounderarajan.D@atmel.com>
46 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
47 (AVR_ISA_2xxxa): Define ISA without LPM.
48 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
49 Add doc for contraint used in 16 bit lds/sts.
50 Adjust ISA group for icall, ijmp, pop and push.
51 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
53 2014-05-19 Nick Clifton <nickc@redhat.com>
55 * msp430.h (struct msp430_operand_s): Add vshift field.
57 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
59 * mips.h (INSN_ISA_MASK): Updated.
60 (INSN_ISA32R3): New define.
61 (INSN_ISA32R5): New define.
62 (INSN_ISA64R3): New define.
63 (INSN_ISA64R5): New define.
64 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
65 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
66 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
68 (INSN_UPTO32R3): New define.
69 (INSN_UPTO32R5): New define.
70 (INSN_UPTO64R3): New define.
71 (INSN_UPTO64R5): New define.
72 (ISA_MIPS32R3): New define.
73 (ISA_MIPS32R5): New define.
74 (ISA_MIPS64R3): New define.
75 (ISA_MIPS64R5): New define.
76 (CPU_MIPS32R3): New define.
77 (CPU_MIPS32R5): New define.
78 (CPU_MIPS64R3): New define.
79 (CPU_MIPS64R5): New define.
81 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
83 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
85 2014-04-22 Christian Svensson <blue@cmd.nu>
89 2014-03-05 Alan Modra <amodra@gmail.com>
91 Update copyright years.
93 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
95 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
98 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
99 Wei-Cheng Wang <cole945@gmail.com>
101 * nds32.h: New file for Andes NDS32.
103 2013-12-07 Mike Frysinger <vapier@gentoo.org>
105 * bfin.h: Remove +x file mode.
107 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
109 * aarch64.h (aarch64_pstatefields): Change element type to
112 2013-11-18 Renlin Li <Renlin.Li@arm.com>
114 * arm.h (ARM_AEXT_V7VE): New define.
115 (ARM_ARCH_V7VE): New define.
116 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
118 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
122 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
124 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
125 (aarch64_sys_reg_writeonly_p): Ditto.
127 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
129 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
130 (aarch64_sys_reg_writeonly_p): Ditto.
132 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
134 * aarch64.h (aarch64_sys_reg): New typedef.
135 (aarch64_sys_regs): Change to define with the new type.
136 (aarch64_sys_reg_deprecated_p): Declare.
138 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
140 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
141 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
143 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
145 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
146 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
147 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
148 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
149 For MIPS, update extension character sequences after +.
150 (ASE_MSA): New define.
151 (ASE_MSA64): New define.
152 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
153 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
154 For microMIPS, update extension character sequences after +.
156 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
161 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
163 * mips.h: Remove references to "+I" and imm2_expr.
165 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
167 * mips.h (M_DEXT, M_DINS): Delete.
169 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
171 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
172 (mips_optional_operand_p): New function.
174 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
175 Richard Sandiford <rdsandiford@googlemail.com>
177 * mips.h: Document new VU0 operand characters.
178 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
179 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
180 (OP_REG_R5900_ACC): New mips_reg_operand_types.
181 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
182 (mips_vu0_channel_mask): Declare.
184 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
186 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
187 (mips_int_operand_min, mips_int_operand_max): New functions.
188 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
190 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
192 * mips.h (mips_decode_reg_operand): New function.
193 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
194 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
195 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
197 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
198 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
199 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
200 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
201 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
202 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
203 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
204 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
205 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
206 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
207 macros to cover the gaps.
208 (INSN2_MOD_SP): Replace with...
209 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
210 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
211 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
212 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
213 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
216 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
218 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
219 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
220 (MIPS16_INSN_COND_BRANCH): Delete.
222 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
223 Kirill Yukhin <kirill.yukhin@intel.com>
224 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
226 * i386.h (BND_PREFIX_OPCODE): New.
228 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
230 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
231 OP_SAVE_RESTORE_LIST.
232 (decode_mips16_operand): Declare.
234 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
236 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
237 (mips_operand, mips_int_operand, mips_mapped_int_operand)
238 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
239 (mips_pcrel_operand): New structures.
240 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
241 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
242 (decode_mips_operand, decode_micromips_operand): Declare.
244 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
246 * mips.h: Document MIPS16 "I" opcode.
248 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
250 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
251 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
252 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
253 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
254 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
255 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
256 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
257 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
258 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
259 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
260 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
261 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
262 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
264 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
265 (M_USD_AB): ...these.
267 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
269 * mips.h: Remove documentation of "[" and "]". Update documentation
270 of "k" and the MDMX formats.
272 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
274 * mips.h: Update documentation of "+s" and "+S".
276 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
278 * mips.h: Document "+i".
280 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
282 * mips.h: Remove "mi" documentation. Update "mh" documentation.
283 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
285 (INSN2_WRITE_GPR_MHI): Rename to...
286 (INSN2_WRITE_GPR_MH): ...this.
288 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
290 * mips.h: Remove documentation of "+D" and "+T".
292 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
294 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
295 Use "source" rather than "destination" for microMIPS "G".
297 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
299 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
302 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
304 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
306 2013-06-17 Catherine Moore <clm@codesourcery.com>
307 Maciej W. Rozycki <macro@codesourcery.com>
308 Chao-Ying Fu <fu@mips.com>
310 * mips.h (OP_SH_EVAOFFSET): Define.
311 (OP_MASK_EVAOFFSET): Define.
312 (INSN_ASE_MASK): Delete.
314 (M_CACHEE_AB, M_CACHEE_OB): New.
315 (M_LBE_OB, M_LBE_AB): New.
316 (M_LBUE_OB, M_LBUE_AB): New.
317 (M_LHE_OB, M_LHE_AB): New.
318 (M_LHUE_OB, M_LHUE_AB): New.
319 (M_LLE_AB, M_LLE_OB): New.
320 (M_LWE_OB, M_LWE_AB): New.
321 (M_LWLE_AB, M_LWLE_OB): New.
322 (M_LWRE_AB, M_LWRE_OB): New.
323 (M_PREFE_AB, M_PREFE_OB): New.
324 (M_SCE_AB, M_SCE_OB): New.
325 (M_SBE_OB, M_SBE_AB): New.
326 (M_SHE_OB, M_SHE_AB): New.
327 (M_SWE_OB, M_SWE_AB): New.
328 (M_SWLE_AB, M_SWLE_OB): New.
329 (M_SWRE_AB, M_SWRE_OB): New.
330 (MICROMIPSOP_SH_EVAOFFSET): Define.
331 (MICROMIPSOP_MASK_EVAOFFSET): Define.
333 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
335 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
337 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
339 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
341 2013-05-09 Andrew Pinski <apinski@cavium.com>
343 * mips.h (OP_MASK_CODE10): Correct definition.
344 (OP_SH_CODE10): Likewise.
345 Add a comment that "+J" is used now for OP_*CODE10.
346 (INSN_ASE_MASK): Update.
347 (INSN_VIRT): New macro.
348 (INSN_VIRT64): New macro
350 2013-05-02 Nick Clifton <nickc@redhat.com>
352 * msp430.h: Add patterns for MSP430X instructions.
354 2013-04-06 David S. Miller <davem@davemloft.net>
356 * sparc.h (F_PREFERRED): Define.
357 (F_PREF_ALIAS): Define.
359 2013-04-03 Nick Clifton <nickc@redhat.com>
361 * v850.h (V850_INVERSE_PCREL): Define.
363 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
366 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
368 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
371 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
373 * tic6xc-opcode-table.h: Add 16-bit insns.
374 * tic6x.h: Add support for 16-bit insns.
376 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
378 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
379 and mov.b/w/l Rs,@(d:32,ERd).
381 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
384 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
385 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
386 tic6x_operand_xregpair operand coding type.
387 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
388 opcode field, usu ORXREGD1324 for the src2 operand and remove the
391 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
394 * tic6x.h (enum tic6x_coding_method): Add
395 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
396 separately the msb and lsb of a register pair. This is needed to
397 encode the opcodes in the same way as TI assembler does.
398 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
399 and rsqrdp opcodes to use the new field coding types.
401 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
403 * arm.h (CRC_EXT_ARMV8): New constant.
404 (ARCH_CRC_ARMV8): New macro.
406 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
408 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
410 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
411 Andrew Jenner <andrew@codesourcery.com>
413 Based on patches from Altera Corporation.
417 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
419 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
421 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
424 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
426 2013-01-24 Nick Clifton <nickc@redhat.com>
428 * v850.h: Add e3v5 support.
430 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
432 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
434 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
436 * ppc.h (PPC_OPCODE_POWER8): New define.
437 (PPC_OPCODE_HTM): Likewise.
439 2013-01-10 Will Newton <will.newton@imgtec.com>
443 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
445 * cr16.h (make_instruction): Rename to cr16_make_instruction.
446 (match_opcode): Rename to cr16_match_opcode.
448 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
450 * mips.h: Add support for r5900 instructions including lq and sq.
452 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
454 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
455 (make_instruction,match_opcode): Added function prototypes.
456 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
458 2012-11-23 Alan Modra <amodra@gmail.com>
460 * ppc.h (ppc_parse_cpu): Update prototype.
462 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
464 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
465 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
467 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
469 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
471 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
473 * ia64.h (ia64_opnd): Add new operand types.
475 2012-08-21 David S. Miller <davem@davemloft.net>
477 * sparc.h (F3F4): New macro.
479 2012-08-13 Ian Bolton <ian.bolton@arm.com>
480 Laurent Desnogues <laurent.desnogues@arm.com>
481 Jim MacArthur <jim.macarthur@arm.com>
482 Marcus Shawcroft <marcus.shawcroft@arm.com>
483 Nigel Stephens <nigel.stephens@arm.com>
484 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
485 Richard Earnshaw <rearnsha@arm.com>
486 Sofiane Naci <sofiane.naci@arm.com>
487 Tejas Belagod <tejas.belagod@arm.com>
488 Yufeng Zhang <yufeng.zhang@arm.com>
490 * aarch64.h: New file.
492 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
493 Maciej W. Rozycki <macro@codesourcery.com>
495 * mips.h (mips_opcode): Add the exclusions field.
496 (OPCODE_IS_MEMBER): Remove macro.
497 (cpu_is_member): New inline function.
498 (opcode_is_member): Likewise.
500 2012-07-31 Chao-Ying Fu <fu@mips.com>
501 Catherine Moore <clm@codesourcery.com>
502 Maciej W. Rozycki <macro@codesourcery.com>
504 * mips.h: Document microMIPS DSP ASE usage.
505 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
506 microMIPS DSP ASE support.
507 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
508 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
509 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
510 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
511 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
512 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
513 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
515 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
517 * mips.h: Fix a typo in description.
519 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
521 * avr.h: (AVR_ISA_XCH): New define.
522 (AVR_ISA_XMEGA): Use it.
523 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
525 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
527 * m68hc11.h: Add XGate definitions.
528 (struct m68hc11_opcode): Add xg_mask field.
530 2012-05-14 Catherine Moore <clm@codesourcery.com>
531 Maciej W. Rozycki <macro@codesourcery.com>
532 Rhonda Wittels <rhonda@codesourcery.com>
534 * ppc.h (PPC_OPCODE_VLE): New definition.
535 (PPC_OP_SA): New macro.
536 (PPC_OP_SE_VLE): New macro.
537 (PPC_OP): Use a variable shift amount.
538 (powerpc_operand): Update comments.
539 (PPC_OPSHIFT_INV): New macro.
540 (PPC_OPERAND_CR): Replace with...
541 (PPC_OPERAND_CR_BIT): ...this and
542 (PPC_OPERAND_CR_REG): ...this.
545 2012-05-03 Sean Keys <skeys@ipdatasys.com>
547 * xgate.h: Header file for XGATE assembler.
549 2012-04-27 David S. Miller <davem@davemloft.net>
551 * sparc.h: Document new arg code' )' for crypto RS3
554 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
555 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
556 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
557 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
558 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
559 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
560 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
561 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
562 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
563 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
564 HWCAP_CBCOND, HWCAP_CRC32): New defines.
566 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
568 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
570 2012-02-27 Alan Modra <amodra@gmail.com>
572 * crx.h (cst4_map): Update declaration.
574 2012-02-25 Walter Lee <walt@tilera.com>
576 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
578 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
579 TILEPRO_OPC_LW_TLS_SN.
581 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
583 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
584 (XRELEASE_PREFIX_OPCODE): Likewise.
586 2011-12-08 Andrew Pinski <apinski@cavium.com>
587 Adam Nemet <anemet@caviumnetworks.com>
589 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
590 (INSN_OCTEON2): New macro.
591 (CPU_OCTEON2): New macro.
592 (OPCODE_IS_MEMBER): Add Octeon2.
594 2011-11-29 Andrew Pinski <apinski@cavium.com>
596 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
597 (INSN_OCTEONP): New macro.
598 (CPU_OCTEONP): New macro.
599 (OPCODE_IS_MEMBER): Add Octeon+.
600 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
602 2011-11-01 DJ Delorie <dj@redhat.com>
606 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
608 * mips.h: Fix a typo in description.
610 2011-09-21 David S. Miller <davem@davemloft.net>
612 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
613 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
614 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
615 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
617 2011-08-09 Chao-ying Fu <fu@mips.com>
618 Maciej W. Rozycki <macro@codesourcery.com>
620 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
621 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
622 (INSN_ASE_MASK): Add the MCU bit.
623 (INSN_MCU): New macro.
624 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
625 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
627 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
629 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
630 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
631 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
632 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
633 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
634 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
635 (INSN2_READ_GPR_MMN): Likewise.
636 (INSN2_READ_FPR_D): Change the bit used.
637 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
638 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
639 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
640 (INSN2_COND_BRANCH): Likewise.
641 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
642 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
643 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
644 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
645 (INSN2_MOD_GPR_MN): Likewise.
647 2011-08-05 David S. Miller <davem@davemloft.net>
649 * sparc.h: Document new format codes '4', '5', and '('.
650 (OPF_LOW4, RS3): New macros.
652 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
654 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
655 order of flags documented.
657 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
659 * mips.h: Clarify the description of microMIPS instruction
661 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
663 2011-07-24 Chao-ying Fu <fu@mips.com>
664 Maciej W. Rozycki <macro@codesourcery.com>
666 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
667 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
668 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
669 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
670 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
671 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
672 (OP_MASK_RS3, OP_SH_RS3): Likewise.
673 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
674 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
675 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
676 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
677 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
678 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
679 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
680 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
681 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
682 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
683 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
684 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
685 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
686 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
687 (INSN_WRITE_GPR_S): New macro.
688 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
689 (INSN2_READ_FPR_D): Likewise.
690 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
691 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
692 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
693 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
694 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
695 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
696 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
697 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
698 (CPU_MICROMIPS): New macro.
699 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
700 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
701 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
702 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
703 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
704 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
705 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
706 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
707 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
708 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
709 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
710 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
711 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
712 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
713 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
714 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
715 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
716 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
717 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
718 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
719 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
720 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
721 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
722 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
723 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
724 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
725 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
726 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
727 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
728 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
729 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
730 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
731 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
732 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
733 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
734 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
735 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
736 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
737 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
738 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
739 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
740 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
741 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
742 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
743 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
744 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
745 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
746 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
747 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
748 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
749 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
750 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
751 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
752 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
753 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
754 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
755 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
756 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
757 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
758 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
759 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
760 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
761 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
762 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
763 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
764 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
765 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
766 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
767 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
768 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
769 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
770 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
771 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
772 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
773 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
774 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
775 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
776 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
777 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
778 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
779 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
780 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
781 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
782 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
783 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
784 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
785 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
786 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
787 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
788 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
789 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
790 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
791 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
792 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
793 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
794 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
795 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
796 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
797 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
798 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
799 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
800 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
801 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
802 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
803 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
804 (micromips_opcodes): New declaration.
805 (bfd_micromips_num_opcodes): Likewise.
807 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
809 * mips.h (INSN_TRAP): Rename to...
810 (INSN_NO_DELAY_SLOT): ... this.
811 (INSN_SYNC): Remove macro.
813 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
815 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
816 a duplicate of AVR_ISA_SPM.
818 2011-07-01 Nick Clifton <nickc@redhat.com>
820 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
822 2011-06-18 Robin Getz <robin.getz@analog.com>
824 * bfin.h (is_macmod_signed): New func
826 2011-06-18 Mike Frysinger <vapier@gentoo.org>
828 * bfin.h (is_macmod_pmove): Add missing space before func args.
829 (is_macmod_hmove): Likewise.
831 2011-06-13 Walter Lee <walt@tilera.com>
833 * tilegx.h: New file.
834 * tilepro.h: New file.
836 2011-05-31 Paul Brook <paul@codesourcery.com>
838 * arm.h (ARM_ARCH_V7R_IDIV): Define.
840 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
842 * s390.h: Replace S390_OPERAND_REG_EVEN with
843 S390_OPERAND_REG_PAIR.
845 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
847 * s390.h: Add S390_OPCODE_REG_EVEN flag.
849 2011-04-18 Julian Brown <julian@codesourcery.com>
851 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
853 2011-04-11 Dan McDonald <dan@wellkeeper.com>
856 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
858 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
860 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
861 New instruction set flags.
862 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
864 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
866 * mips.h (M_PREF_AB): New enum value.
868 2011-02-12 Mike Frysinger <vapier@gentoo.org>
870 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
872 (is_macmod_pmove, is_macmod_hmove): New functions.
874 2011-02-11 Mike Frysinger <vapier@gentoo.org>
876 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
878 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
880 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
881 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
883 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
886 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
889 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
892 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
894 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
896 * mips.h: Update commentary after last commit.
898 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
900 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
901 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
902 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
904 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
906 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
908 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
910 * mips.h: Fix previous commit.
912 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
914 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
915 (INSN_LOONGSON_3A): Clear bit 31.
917 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
920 * arm.h (ARM_AEXT_V6M_ONLY): New define.
921 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
922 (ARM_ARCH_V6M_ONLY): New define.
924 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
926 * mips.h (INSN_LOONGSON_3A): Defined.
927 (CPU_LOONGSON_3A): Defined.
928 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
930 2010-10-09 Matt Rice <ratmice@gmail.com>
932 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
933 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
935 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
937 * arm.h (ARM_EXT_VIRT): New define.
938 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
939 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
942 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
944 * arm.h (ARM_AEXT_ADIV): New define.
945 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
947 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
949 * arm.h (ARM_EXT_OS): New define.
950 (ARM_AEXT_V6SM): Likewise.
951 (ARM_ARCH_V6SM): Likewise.
953 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
955 * arm.h (ARM_EXT_MP): Add.
956 (ARM_ARCH_V7A_MP): Likewise.
958 2010-09-22 Mike Frysinger <vapier@gentoo.org>
960 * bfin.h: Declare pseudoChr structs/defines.
962 2010-09-21 Mike Frysinger <vapier@gentoo.org>
964 * bfin.h: Strip trailing whitespace.
966 2010-07-29 DJ Delorie <dj@redhat.com>
968 * rx.h (RX_Operand_Type): Add TwoReg.
969 (RX_Opcode_ID): Remove ediv and ediv2.
971 2010-07-27 DJ Delorie <dj@redhat.com>
973 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
975 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
976 Ina Pandit <ina.pandit@kpitcummins.com>
978 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
979 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
980 PROCESSOR_V850E2_ALL.
981 Remove PROCESSOR_V850EA support.
982 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
983 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
984 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
985 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
986 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
987 V850_OPERAND_PERCENT.
988 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
990 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
993 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
995 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
996 (MIPS16_INSN_BRANCH): Rename to...
997 (MIPS16_INSN_COND_BRANCH): ... this.
999 2010-07-03 Alan Modra <amodra@gmail.com>
1001 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1002 Renumber other PPC_OPCODE defines.
1004 2010-07-03 Alan Modra <amodra@gmail.com>
1006 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1008 2010-06-29 Alan Modra <amodra@gmail.com>
1010 * maxq.h: Delete file.
1012 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1014 * ppc.h (PPC_OPCODE_E500): Define.
1016 2010-05-26 Catherine Moore <clm@codesourcery.com>
1018 * opcode/mips.h (INSN_MIPS16): Remove.
1020 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1022 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1024 2010-04-15 Nick Clifton <nickc@redhat.com>
1026 * alpha.h: Update copyright notice to use GPLv3.
1032 * convex.h: Likewise.
1039 * h8300.h: Likewise.
1046 * m68hc11.h: Likewise.
1052 * mn10200.h: Likewise.
1053 * mn10300.h: Likewise.
1054 * msp430.h: Likewise.
1056 * ns32k.h: Likewise.
1058 * pdp11.h: Likewise.
1065 * score-datadep.h: Likewise.
1066 * score-inst.h: Likewise.
1067 * sparc.h: Likewise.
1068 * spu-insns.h: Likewise.
1070 * tic30.h: Likewise.
1071 * tic4x.h: Likewise.
1072 * tic54x.h: Likewise.
1073 * tic80.h: Likewise.
1077 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1079 * tic6x-control-registers.h, tic6x-insn-formats.h,
1080 tic6x-opcode-table.h, tic6x.h: New.
1082 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1084 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1086 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1088 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1090 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1092 * ia64.h (ia64_find_opcode): Remove argument name.
1093 (ia64_find_next_opcode): Likewise.
1094 (ia64_dis_opcode): Likewise.
1095 (ia64_free_opcode): Likewise.
1096 (ia64_find_dependency): Likewise.
1098 2009-11-22 Doug Evans <dje@sebabeach.org>
1100 * cgen.h: Include bfd_stdint.h.
1101 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1103 2009-11-18 Paul Brook <paul@codesourcery.com>
1105 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1107 2009-11-17 Paul Brook <paul@codesourcery.com>
1108 Daniel Jacobowitz <dan@codesourcery.com>
1110 * arm.h (ARM_EXT_V6_DSP): Define.
1111 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1112 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1114 2009-11-04 DJ Delorie <dj@redhat.com>
1116 * rx.h (rx_decode_opcode) (mvtipl): Add.
1117 (mvtcp, mvfcp, opecp): Remove.
1119 2009-11-02 Paul Brook <paul@codesourcery.com>
1121 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1122 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1123 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1124 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1125 FPU_ARCH_NEON_VFP_V4): Define.
1127 2009-10-23 Doug Evans <dje@sebabeach.org>
1129 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1130 * cgen.h: Update. Improve multi-inclusion macro name.
1132 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1134 * ppc.h (PPC_OPCODE_476): Define.
1136 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1138 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1140 2009-09-29 DJ Delorie <dj@redhat.com>
1144 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1146 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1148 2009-09-21 Ben Elliston <bje@au.ibm.com>
1150 * ppc.h (PPC_OPCODE_PPCA2): New.
1152 2009-09-05 Martin Thuresson <martin@mtme.org>
1154 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1156 2009-08-29 Martin Thuresson <martin@mtme.org>
1158 * tic30.h (template): Rename type template to
1159 insn_template. Updated code to use new name.
1160 * tic54x.h (template): Rename type template to
1163 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1165 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1167 2009-06-11 Anthony Green <green@moxielogic.com>
1169 * moxie.h (MOXIE_F3_PCREL): Define.
1170 (moxie_form3_opc_info): Grow.
1172 2009-06-06 Anthony Green <green@moxielogic.com>
1174 * moxie.h (MOXIE_F1_M): Define.
1176 2009-04-15 Anthony Green <green@moxielogic.com>
1180 2009-04-06 DJ Delorie <dj@redhat.com>
1182 * h8300.h: Add relaxation attributes to MOVA opcodes.
1184 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1186 * ppc.h (ppc_parse_cpu): Declare.
1188 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1190 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1191 and _IMM11 for mbitclr and mbitset.
1192 * score-datadep.h: Update dependency information.
1194 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1196 * ppc.h (PPC_OPCODE_POWER7): New.
1198 2009-02-06 Doug Evans <dje@google.com>
1200 * i386.h: Add comment regarding sse* insns and prefixes.
1202 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1204 * mips.h (INSN_XLR): Define.
1205 (INSN_CHIP_MASK): Update.
1207 (OPCODE_IS_MEMBER): Update.
1208 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1210 2009-01-28 Doug Evans <dje@google.com>
1212 * opcode/i386.h: Add multiple inclusion protection.
1213 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1214 (EDI_REG_NUM): New macros.
1215 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1216 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1217 (REX_PREFIX_P): New macro.
1219 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1221 * ppc.h (struct powerpc_opcode): New field "deprecated".
1222 (PPC_OPCODE_NOPOWER4): Delete.
1224 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1226 * mips.h: Define CPU_R14000, CPU_R16000.
1227 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1229 2008-11-18 Catherine Moore <clm@codesourcery.com>
1231 * arm.h (FPU_NEON_FP16): New.
1232 (FPU_ARCH_NEON_FP16): New.
1234 2008-11-06 Chao-ying Fu <fu@mips.com>
1236 * mips.h: Doucument '1' for 5-bit sync type.
1238 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1240 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1243 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1245 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1247 2008-07-30 Michael J. Eager <eager@eagercon.com>
1249 * ppc.h (PPC_OPCODE_405): Define.
1250 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1252 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1254 * ppc.h (ppc_cpu_t): New typedef.
1255 (struct powerpc_opcode <flags>): Use it.
1256 (struct powerpc_operand <insert, extract>): Likewise.
1257 (struct powerpc_macro <flags>): Likewise.
1259 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1261 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1262 Update comment before MIPS16 field descriptors to mention MIPS16.
1263 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1265 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1266 New bit masks and shift counts for cins and exts.
1268 * mips.h: Document new field descriptors +Q.
1269 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1271 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1273 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1274 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1276 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1278 * ppc.h: (PPC_OPCODE_E500MC): New.
1280 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1282 * i386.h (MAX_OPERANDS): Set to 5.
1283 (MAX_MNEM_SIZE): Changed to 20.
1285 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1287 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1289 2008-03-09 Paul Brook <paul@codesourcery.com>
1291 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1293 2008-03-04 Paul Brook <paul@codesourcery.com>
1295 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1296 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1297 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1299 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1300 Nick Clifton <nickc@redhat.com>
1303 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1304 with a 32-bit displacement but without the top bit of the 4th byte
1307 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1309 * cr16.h (cr16_num_optab): Declared.
1311 2008-02-14 Hakan Ardo <hakan@debian.org>
1314 * avr.h (AVR_ISA_2xxe): Define.
1316 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1318 * mips.h: Update copyright.
1319 (INSN_CHIP_MASK): New macro.
1320 (INSN_OCTEON): New macro.
1321 (CPU_OCTEON): New macro.
1322 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1324 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1326 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1328 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1330 * avr.h (AVR_ISA_USB162): Add new opcode set.
1331 (AVR_ISA_AVR3): Likewise.
1333 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1335 * mips.h (INSN_LOONGSON_2E): New.
1336 (INSN_LOONGSON_2F): New.
1337 (CPU_LOONGSON_2E): New.
1338 (CPU_LOONGSON_2F): New.
1339 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1341 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1343 * mips.h (INSN_ISA*): Redefine certain values as an
1344 enumeration. Update comments.
1345 (mips_isa_table): New.
1346 (ISA_MIPS*): Redefine to match enumeration.
1347 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1350 2007-08-08 Ben Elliston <bje@au.ibm.com>
1352 * ppc.h (PPC_OPCODE_PPCPS): New.
1354 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1356 * m68k.h: Document j K & E.
1358 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1360 * cr16.h: New file for CR16 target.
1362 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1364 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1366 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1368 * m68k.h (mcfisa_c): New.
1369 (mcfusp, mcf_mask): Adjust.
1371 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1373 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1374 (num_powerpc_operands): Declare.
1375 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1376 (PPC_OPERAND_PLUS1): Define.
1378 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1380 * i386.h (REX_MODE64): Renamed to ...
1382 (REX_EXTX): Renamed to ...
1384 (REX_EXTY): Renamed to ...
1386 (REX_EXTZ): Renamed to ...
1389 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1391 * i386.h: Add entries from config/tc-i386.h and move tables
1392 to opcodes/i386-opc.h.
1394 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1396 * i386.h (FloatDR): Removed.
1397 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1399 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1401 * spu-insns.h: Add soma double-float insns.
1403 2007-02-20 Thiemo Seufer <ths@mips.com>
1404 Chao-Ying Fu <fu@mips.com>
1406 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1407 (INSN_DSPR2): Add flag for DSP R2 instructions.
1408 (M_BALIGN): New macro.
1410 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1412 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1413 and Seg3ShortFrom with Shortform.
1415 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1418 * i386.h (i386_optab): Put the real "test" before the pseudo
1421 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1423 * m68k.h (m68010up): OR fido_a.
1425 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1427 * m68k.h (fido_a): New.
1429 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1431 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1432 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1435 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1437 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1439 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1441 * score-inst.h (enum score_insn_type): Add Insn_internal.
1443 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1444 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1445 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1446 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1447 Alan Modra <amodra@bigpond.net.au>
1449 * spu-insns.h: New file.
1452 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1454 * ppc.h (PPC_OPCODE_CELL): Define.
1456 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1458 * i386.h : Modify opcode to support for the change in POPCNT opcode
1459 in amdfam10 architecture.
1461 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1463 * i386.h: Replace CpuMNI with CpuSSSE3.
1465 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1466 Joseph Myers <joseph@codesourcery.com>
1467 Ian Lance Taylor <ian@wasabisystems.com>
1468 Ben Elliston <bje@wasabisystems.com>
1470 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1472 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1474 * score-datadep.h: New file.
1475 * score-inst.h: New file.
1477 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1479 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1480 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1481 movdq2q and movq2dq.
1483 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1484 Michael Meissner <michael.meissner@amd.com>
1486 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1488 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1490 * i386.h (i386_optab): Add "nop" with memory reference.
1492 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1494 * i386.h (i386_optab): Update comment for 64bit NOP.
1496 2006-06-06 Ben Elliston <bje@au.ibm.com>
1497 Anton Blanchard <anton@samba.org>
1499 * ppc.h (PPC_OPCODE_POWER6): Define.
1502 2006-06-05 Thiemo Seufer <ths@mips.com>
1504 * mips.h: Improve description of MT flags.
1506 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1508 * m68k.h (mcf_mask): Define.
1510 2006-05-05 Thiemo Seufer <ths@mips.com>
1511 David Ung <davidu@mips.com>
1513 * mips.h (enum): Add macro M_CACHE_AB.
1515 2006-05-04 Thiemo Seufer <ths@mips.com>
1516 Nigel Stephens <nigel@mips.com>
1517 David Ung <davidu@mips.com>
1519 * mips.h: Add INSN_SMARTMIPS define.
1521 2006-04-30 Thiemo Seufer <ths@mips.com>
1522 David Ung <davidu@mips.com>
1524 * mips.h: Defines udi bits and masks. Add description of
1525 characters which may appear in the args field of udi
1528 2006-04-26 Thiemo Seufer <ths@networkno.de>
1530 * mips.h: Improve comments describing the bitfield instruction
1533 2006-04-26 Julian Brown <julian@codesourcery.com>
1535 * arm.h (FPU_VFP_EXT_V3): Define constant.
1536 (FPU_NEON_EXT_V1): Likewise.
1537 (FPU_VFP_HARD): Update.
1538 (FPU_VFP_V3): Define macro.
1539 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1541 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1543 * avr.h (AVR_ISA_PWMx): New.
1545 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1547 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1548 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1549 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1550 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1551 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1553 2006-03-10 Paul Brook <paul@codesourcery.com>
1555 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1557 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1559 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1560 first. Correct mask of bb "B" opcode.
1562 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1564 * i386.h (i386_optab): Support Intel Merom New Instructions.
1566 2006-02-24 Paul Brook <paul@codesourcery.com>
1568 * arm.h: Add V7 feature bits.
1570 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1572 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1574 2006-01-31 Paul Brook <paul@codesourcery.com>
1575 Richard Earnshaw <rearnsha@arm.com>
1577 * arm.h: Use ARM_CPU_FEATURE.
1578 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1579 (arm_feature_set): Change to a structure.
1580 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1581 ARM_FEATURE): New macros.
1583 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1585 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1586 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1587 (ADD_PC_INCR_OPCODE): Don't define.
1589 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1592 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1594 2005-11-14 David Ung <davidu@mips.com>
1596 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1597 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1598 save/restore encoding of the args field.
1600 2005-10-28 Dave Brolley <brolley@redhat.com>
1602 Contribute the following changes:
1603 2005-02-16 Dave Brolley <brolley@redhat.com>
1605 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1606 cgen_isa_mask_* to cgen_bitset_*.
1609 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1611 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1612 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1613 (CGEN_CPU_TABLE): Make isas a ponter.
1615 2003-09-29 Dave Brolley <brolley@redhat.com>
1617 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1618 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1619 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1621 2002-12-13 Dave Brolley <brolley@redhat.com>
1623 * cgen.h (symcat.h): #include it.
1624 (cgen-bitset.h): #include it.
1625 (CGEN_ATTR_VALUE_TYPE): Now a union.
1626 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1627 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1628 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1629 * cgen-bitset.h: New file.
1631 2005-09-30 Catherine Moore <clm@cm00re.com>
1635 2005-10-24 Jan Beulich <jbeulich@novell.com>
1637 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1640 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1642 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1643 Add FLAG_STRICT to pa10 ftest opcode.
1645 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1647 * hppa.h (pa_opcodes): Remove lha entries.
1649 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1651 * hppa.h (FLAG_STRICT): Revise comment.
1652 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1653 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1656 2005-09-30 Catherine Moore <clm@cm00re.com>
1660 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1662 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1664 2005-09-06 Chao-ying Fu <fu@mips.com>
1666 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1667 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1669 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1670 (INSN_ASE_MASK): Update to include INSN_MT.
1671 (INSN_MT): New define for MT ASE.
1673 2005-08-25 Chao-ying Fu <fu@mips.com>
1675 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1676 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1677 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1678 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1679 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1680 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1682 (INSN_DSP): New define for DSP ASE.
1684 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1688 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1690 * ppc.h (PPC_OPCODE_E300): Define.
1692 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1694 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1696 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1699 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1702 2005-07-27 Jan Beulich <jbeulich@novell.com>
1704 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1705 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1706 Add movq-s as 64-bit variants of movd-s.
1708 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1710 * hppa.h: Fix punctuation in comment.
1712 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1713 implicit space-register addressing. Set space-register bits on opcodes
1714 using implicit space-register addressing. Add various missing pa20
1715 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1716 space-register addressing. Use "fE" instead of "fe" in various
1719 2005-07-18 Jan Beulich <jbeulich@novell.com>
1721 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1723 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1725 * i386.h (i386_optab): Support Intel VMX Instructions.
1727 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1729 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1731 2005-07-05 Jan Beulich <jbeulich@novell.com>
1733 * i386.h (i386_optab): Add new insns.
1735 2005-07-01 Nick Clifton <nickc@redhat.com>
1737 * sparc.h: Add typedefs to structure declarations.
1739 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1742 * i386.h (i386_optab): Update comments for 64bit addressing on
1743 mov. Allow 64bit addressing for mov and movq.
1745 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1747 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1748 respectively, in various floating-point load and store patterns.
1750 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1752 * hppa.h (FLAG_STRICT): Correct comment.
1753 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1754 PA 2.0 mneumonics when equivalent. Entries with cache control
1755 completers now require PA 1.1. Adjust whitespace.
1757 2005-05-19 Anton Blanchard <anton@samba.org>
1759 * ppc.h (PPC_OPCODE_POWER5): Define.
1761 2005-05-10 Nick Clifton <nickc@redhat.com>
1763 * Update the address and phone number of the FSF organization in
1764 the GPL notices in the following files:
1765 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1766 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1767 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1768 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1769 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1770 tic54x.h, tic80.h, v850.h, vax.h
1772 2005-05-09 Jan Beulich <jbeulich@novell.com>
1774 * i386.h (i386_optab): Add ht and hnt.
1776 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1778 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1779 Add xcrypt-ctr. Provide aliases without hyphens.
1781 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1783 Moved from ../ChangeLog
1785 2005-04-12 Paul Brook <paul@codesourcery.com>
1786 * m88k.h: Rename psr macros to avoid conflicts.
1788 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1789 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1790 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1791 and ARM_ARCH_V6ZKT2.
1793 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1794 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1795 Remove redundant instruction types.
1796 (struct argument): X_op - new field.
1797 (struct cst4_entry): Remove.
1798 (no_op_insn): Declare.
1800 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1801 * crx.h (enum argtype): Rename types, remove unused types.
1803 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1804 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1805 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1806 (enum operand_type): Rearrange operands, edit comments.
1807 replace us<N> with ui<N> for unsigned immediate.
1808 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1809 displacements (respectively).
1810 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1811 (instruction type): Add NO_TYPE_INS.
1812 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1813 (operand_entry): New field - 'flags'.
1814 (operand flags): New.
1816 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1817 * crx.h (operand_type): Remove redundant types i3, i4,
1819 Add new unsigned immediate types us3, us4, us5, us16.
1821 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1823 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1824 adjust them accordingly.
1826 2005-04-01 Jan Beulich <jbeulich@novell.com>
1828 * i386.h (i386_optab): Add rdtscp.
1830 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1832 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1833 between memory and segment register. Allow movq for moving between
1834 general-purpose register and segment register.
1836 2005-02-09 Jan Beulich <jbeulich@novell.com>
1839 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1840 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1843 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1845 * m68k.h (m68008, m68ec030, m68882): Remove.
1847 (cpu_m68k, cpu_cf): New.
1848 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1849 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1851 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1853 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1854 * cgen.h (enum cgen_parse_operand_type): Add
1855 CGEN_PARSE_OPERAND_SYMBOLIC.
1857 2005-01-21 Fred Fish <fnf@specifixinc.com>
1859 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1860 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1861 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1863 2005-01-19 Fred Fish <fnf@specifixinc.com>
1865 * mips.h (struct mips_opcode): Add new pinfo2 member.
1866 (INSN_ALIAS): New define for opcode table entries that are
1867 specific instances of another entry, such as 'move' for an 'or'
1868 with a zero operand.
1869 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1870 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1872 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1874 * mips.h (CPU_RM9000): Define.
1875 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1877 2004-11-25 Jan Beulich <jbeulich@novell.com>
1879 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1880 to/from test registers are illegal in 64-bit mode. Add missing
1881 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1882 (previously one had to explicitly encode a rex64 prefix). Re-enable
1883 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1884 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1886 2004-11-23 Jan Beulich <jbeulich@novell.com>
1888 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1889 available only with SSE2. Change the MMX additions introduced by SSE
1890 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1891 instructions by their now designated identifier (since combining i686
1892 and 3DNow! does not really imply 3DNow!A).
1894 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1896 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1897 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1899 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1900 Vineet Sharma <vineets@noida.hcltech.com>
1902 * maxq.h: New file: Disassembly information for the maxq port.
1904 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1906 * i386.h (i386_optab): Put back "movzb".
1908 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1910 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1911 comments. Remove member cris_ver_sim. Add members
1912 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1913 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1914 (struct cris_support_reg, struct cris_cond15): New types.
1915 (cris_conds15): Declare.
1916 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1917 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1918 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1919 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1920 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1921 SIZE_FIELD_UNSIGNED.
1923 2004-11-04 Jan Beulich <jbeulich@novell.com>
1925 * i386.h (sldx_Suf): Remove.
1926 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1927 (q_FP): Define, implying no REX64.
1928 (x_FP, sl_FP): Imply FloatMF.
1929 (i386_optab): Split reg and mem forms of moving from segment registers
1930 so that the memory forms can ignore the 16-/32-bit operand size
1931 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1932 all non-floating-point instructions. Unite 32- and 64-bit forms of
1933 movsx, movzx, and movd. Adjust floating point operations for the above
1934 changes to the *FP macros. Add DefaultSize to floating point control
1935 insns operating on larger memory ranges. Remove left over comments
1936 hinting at certain insns being Intel-syntax ones where the ones
1937 actually meant are already gone.
1939 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1941 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1944 2004-09-30 Paul Brook <paul@codesourcery.com>
1946 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1947 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1949 2004-09-11 Theodore A. Roth <troth@openavr.org>
1951 * avr.h: Add support for
1952 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1954 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1956 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1958 2004-08-24 Dmitry Diky <diwil@spec.ru>
1960 * msp430.h (msp430_opc): Add new instructions.
1961 (msp430_rcodes): Declare new instructions.
1962 (msp430_hcodes): Likewise..
1964 2004-08-13 Nick Clifton <nickc@redhat.com>
1967 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1970 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1972 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1974 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1976 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1978 2004-07-21 Jan Beulich <jbeulich@novell.com>
1980 * i386.h: Adjust instruction descriptions to better match the
1983 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1985 * arm.h: Remove all old content. Replace with architecture defines
1986 from gas/config/tc-arm.c.
1988 2004-07-09 Andreas Schwab <schwab@suse.de>
1990 * m68k.h: Fix comment.
1992 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1996 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1998 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2000 2004-05-24 Peter Barada <peter@the-baradas.com>
2002 * m68k.h: Add 'size' to m68k_opcode.
2004 2004-05-05 Peter Barada <peter@the-baradas.com>
2006 * m68k.h: Switch from ColdFire chip name to core variant.
2008 2004-04-22 Peter Barada <peter@the-baradas.com>
2010 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2011 descriptions for new EMAC cases.
2012 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2013 handle Motorola MAC syntax.
2014 Allow disassembly of ColdFire V4e object files.
2016 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2018 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2020 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2022 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2024 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2026 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2028 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2030 * i386.h (i386_optab): Added xstore/xcrypt insns.
2032 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2034 * h8300.h (32bit ldc/stc): Add relaxing support.
2036 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2038 * h8300.h (BITOP): Pass MEMRELAX flag.
2040 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2042 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2045 For older changes see ChangeLog-9103
2047 Copyright (C) 2004-2014 Free Software Foundation, Inc.
2049 Copying and distribution of this file, with or without modification,
2050 are permitted in any medium without royalty provided the copyright
2051 notice and this notice are preserved.
2057 version-control: never