1 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips.h (M_DEXT, M_DINS): Delete.
5 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
7 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
8 (mips_optional_operand_p): New function.
10 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
11 Richard Sandiford <rdsandiford@googlemail.com>
13 * mips.h: Document new VU0 operand characters.
14 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
15 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
16 (OP_REG_R5900_ACC): New mips_reg_operand_types.
17 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
18 (mips_vu0_channel_mask): Declare.
20 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
22 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
23 (mips_int_operand_min, mips_int_operand_max): New functions.
24 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
26 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
28 * mips.h (mips_decode_reg_operand): New function.
29 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
30 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
31 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
33 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
34 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
35 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
36 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
37 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
38 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
39 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
40 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
41 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
42 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
43 macros to cover the gaps.
44 (INSN2_MOD_SP): Replace with...
45 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
46 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
47 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
48 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
49 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
52 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
54 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
55 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
56 (MIPS16_INSN_COND_BRANCH): Delete.
58 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
59 Kirill Yukhin <kirill.yukhin@intel.com>
60 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
62 * i386.h (BND_PREFIX_OPCODE): New.
64 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
66 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
68 (decode_mips16_operand): Declare.
70 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
72 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
73 (mips_operand, mips_int_operand, mips_mapped_int_operand)
74 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
75 (mips_pcrel_operand): New structures.
76 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
77 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
78 (decode_mips_operand, decode_micromips_operand): Declare.
80 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
82 * mips.h: Document MIPS16 "I" opcode.
84 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
86 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
87 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
88 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
89 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
90 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
91 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
92 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
93 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
94 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
95 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
96 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
97 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
98 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
100 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
101 (M_USD_AB): ...these.
103 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
105 * mips.h: Remove documentation of "[" and "]". Update documentation
106 of "k" and the MDMX formats.
108 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
110 * mips.h: Update documentation of "+s" and "+S".
112 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
114 * mips.h: Document "+i".
116 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
118 * mips.h: Remove "mi" documentation. Update "mh" documentation.
119 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
121 (INSN2_WRITE_GPR_MHI): Rename to...
122 (INSN2_WRITE_GPR_MH): ...this.
124 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
126 * mips.h: Remove documentation of "+D" and "+T".
128 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
130 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
131 Use "source" rather than "destination" for microMIPS "G".
133 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
135 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
138 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
140 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
142 2013-06-17 Catherine Moore <clm@codesourcery.com>
143 Maciej W. Rozycki <macro@codesourcery.com>
144 Chao-Ying Fu <fu@mips.com>
146 * mips.h (OP_SH_EVAOFFSET): Define.
147 (OP_MASK_EVAOFFSET): Define.
148 (INSN_ASE_MASK): Delete.
150 (M_CACHEE_AB, M_CACHEE_OB): New.
151 (M_LBE_OB, M_LBE_AB): New.
152 (M_LBUE_OB, M_LBUE_AB): New.
153 (M_LHE_OB, M_LHE_AB): New.
154 (M_LHUE_OB, M_LHUE_AB): New.
155 (M_LLE_AB, M_LLE_OB): New.
156 (M_LWE_OB, M_LWE_AB): New.
157 (M_LWLE_AB, M_LWLE_OB): New.
158 (M_LWRE_AB, M_LWRE_OB): New.
159 (M_PREFE_AB, M_PREFE_OB): New.
160 (M_SCE_AB, M_SCE_OB): New.
161 (M_SBE_OB, M_SBE_AB): New.
162 (M_SHE_OB, M_SHE_AB): New.
163 (M_SWE_OB, M_SWE_AB): New.
164 (M_SWLE_AB, M_SWLE_OB): New.
165 (M_SWRE_AB, M_SWRE_OB): New.
166 (MICROMIPSOP_SH_EVAOFFSET): Define.
167 (MICROMIPSOP_MASK_EVAOFFSET): Define.
169 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
171 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
173 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
175 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
177 2013-05-09 Andrew Pinski <apinski@cavium.com>
179 * mips.h (OP_MASK_CODE10): Correct definition.
180 (OP_SH_CODE10): Likewise.
181 Add a comment that "+J" is used now for OP_*CODE10.
182 (INSN_ASE_MASK): Update.
183 (INSN_VIRT): New macro.
184 (INSN_VIRT64): New macro
186 2013-05-02 Nick Clifton <nickc@redhat.com>
188 * msp430.h: Add patterns for MSP430X instructions.
190 2013-04-06 David S. Miller <davem@davemloft.net>
192 * sparc.h (F_PREFERRED): Define.
193 (F_PREF_ALIAS): Define.
195 2013-04-03 Nick Clifton <nickc@redhat.com>
197 * v850.h (V850_INVERSE_PCREL): Define.
199 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
202 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
204 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
207 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
209 * tic6xc-opcode-table.h: Add 16-bit insns.
210 * tic6x.h: Add support for 16-bit insns.
212 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
214 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
215 and mov.b/w/l Rs,@(d:32,ERd).
217 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
220 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
221 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
222 tic6x_operand_xregpair operand coding type.
223 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
224 opcode field, usu ORXREGD1324 for the src2 operand and remove the
227 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
230 * tic6x.h (enum tic6x_coding_method): Add
231 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
232 separately the msb and lsb of a register pair. This is needed to
233 encode the opcodes in the same way as TI assembler does.
234 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
235 and rsqrdp opcodes to use the new field coding types.
237 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
239 * arm.h (CRC_EXT_ARMV8): New constant.
240 (ARCH_CRC_ARMV8): New macro.
242 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
244 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
246 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
247 Andrew Jenner <andrew@codesourcery.com>
249 Based on patches from Altera Corporation.
253 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
255 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
257 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
260 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
262 2013-01-24 Nick Clifton <nickc@redhat.com>
264 * v850.h: Add e3v5 support.
266 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
268 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
270 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
272 * ppc.h (PPC_OPCODE_POWER8): New define.
273 (PPC_OPCODE_HTM): Likewise.
275 2013-01-10 Will Newton <will.newton@imgtec.com>
279 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
281 * cr16.h (make_instruction): Rename to cr16_make_instruction.
282 (match_opcode): Rename to cr16_match_opcode.
284 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
286 * mips.h: Add support for r5900 instructions including lq and sq.
288 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
290 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
291 (make_instruction,match_opcode): Added function prototypes.
292 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
294 2012-11-23 Alan Modra <amodra@gmail.com>
296 * ppc.h (ppc_parse_cpu): Update prototype.
298 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
300 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
301 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
303 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
305 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
307 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
309 * ia64.h (ia64_opnd): Add new operand types.
311 2012-08-21 David S. Miller <davem@davemloft.net>
313 * sparc.h (F3F4): New macro.
315 2012-08-13 Ian Bolton <ian.bolton@arm.com>
316 Laurent Desnogues <laurent.desnogues@arm.com>
317 Jim MacArthur <jim.macarthur@arm.com>
318 Marcus Shawcroft <marcus.shawcroft@arm.com>
319 Nigel Stephens <nigel.stephens@arm.com>
320 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
321 Richard Earnshaw <rearnsha@arm.com>
322 Sofiane Naci <sofiane.naci@arm.com>
323 Tejas Belagod <tejas.belagod@arm.com>
324 Yufeng Zhang <yufeng.zhang@arm.com>
326 * aarch64.h: New file.
328 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
329 Maciej W. Rozycki <macro@codesourcery.com>
331 * mips.h (mips_opcode): Add the exclusions field.
332 (OPCODE_IS_MEMBER): Remove macro.
333 (cpu_is_member): New inline function.
334 (opcode_is_member): Likewise.
336 2012-07-31 Chao-Ying Fu <fu@mips.com>
337 Catherine Moore <clm@codesourcery.com>
338 Maciej W. Rozycki <macro@codesourcery.com>
340 * mips.h: Document microMIPS DSP ASE usage.
341 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
342 microMIPS DSP ASE support.
343 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
344 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
345 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
346 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
347 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
348 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
349 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
351 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
353 * mips.h: Fix a typo in description.
355 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
357 * avr.h: (AVR_ISA_XCH): New define.
358 (AVR_ISA_XMEGA): Use it.
359 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
361 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
363 * m68hc11.h: Add XGate definitions.
364 (struct m68hc11_opcode): Add xg_mask field.
366 2012-05-14 Catherine Moore <clm@codesourcery.com>
367 Maciej W. Rozycki <macro@codesourcery.com>
368 Rhonda Wittels <rhonda@codesourcery.com>
370 * ppc.h (PPC_OPCODE_VLE): New definition.
371 (PPC_OP_SA): New macro.
372 (PPC_OP_SE_VLE): New macro.
373 (PPC_OP): Use a variable shift amount.
374 (powerpc_operand): Update comments.
375 (PPC_OPSHIFT_INV): New macro.
376 (PPC_OPERAND_CR): Replace with...
377 (PPC_OPERAND_CR_BIT): ...this and
378 (PPC_OPERAND_CR_REG): ...this.
381 2012-05-03 Sean Keys <skeys@ipdatasys.com>
383 * xgate.h: Header file for XGATE assembler.
385 2012-04-27 David S. Miller <davem@davemloft.net>
387 * sparc.h: Document new arg code' )' for crypto RS3
390 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
391 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
392 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
393 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
394 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
395 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
396 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
397 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
398 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
399 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
400 HWCAP_CBCOND, HWCAP_CRC32): New defines.
402 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
404 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
406 2012-02-27 Alan Modra <amodra@gmail.com>
408 * crx.h (cst4_map): Update declaration.
410 2012-02-25 Walter Lee <walt@tilera.com>
412 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
414 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
415 TILEPRO_OPC_LW_TLS_SN.
417 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
419 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
420 (XRELEASE_PREFIX_OPCODE): Likewise.
422 2011-12-08 Andrew Pinski <apinski@cavium.com>
423 Adam Nemet <anemet@caviumnetworks.com>
425 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
426 (INSN_OCTEON2): New macro.
427 (CPU_OCTEON2): New macro.
428 (OPCODE_IS_MEMBER): Add Octeon2.
430 2011-11-29 Andrew Pinski <apinski@cavium.com>
432 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
433 (INSN_OCTEONP): New macro.
434 (CPU_OCTEONP): New macro.
435 (OPCODE_IS_MEMBER): Add Octeon+.
436 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
438 2011-11-01 DJ Delorie <dj@redhat.com>
442 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
444 * mips.h: Fix a typo in description.
446 2011-09-21 David S. Miller <davem@davemloft.net>
448 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
449 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
450 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
451 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
453 2011-08-09 Chao-ying Fu <fu@mips.com>
454 Maciej W. Rozycki <macro@codesourcery.com>
456 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
457 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
458 (INSN_ASE_MASK): Add the MCU bit.
459 (INSN_MCU): New macro.
460 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
461 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
463 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
465 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
466 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
467 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
468 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
469 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
470 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
471 (INSN2_READ_GPR_MMN): Likewise.
472 (INSN2_READ_FPR_D): Change the bit used.
473 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
474 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
475 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
476 (INSN2_COND_BRANCH): Likewise.
477 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
478 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
479 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
480 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
481 (INSN2_MOD_GPR_MN): Likewise.
483 2011-08-05 David S. Miller <davem@davemloft.net>
485 * sparc.h: Document new format codes '4', '5', and '('.
486 (OPF_LOW4, RS3): New macros.
488 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
490 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
491 order of flags documented.
493 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
495 * mips.h: Clarify the description of microMIPS instruction
497 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
499 2011-07-24 Chao-ying Fu <fu@mips.com>
500 Maciej W. Rozycki <macro@codesourcery.com>
502 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
503 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
504 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
505 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
506 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
507 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
508 (OP_MASK_RS3, OP_SH_RS3): Likewise.
509 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
510 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
511 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
512 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
513 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
514 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
515 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
516 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
517 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
518 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
519 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
520 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
521 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
522 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
523 (INSN_WRITE_GPR_S): New macro.
524 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
525 (INSN2_READ_FPR_D): Likewise.
526 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
527 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
528 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
529 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
530 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
531 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
532 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
533 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
534 (CPU_MICROMIPS): New macro.
535 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
536 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
537 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
538 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
539 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
540 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
541 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
542 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
543 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
544 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
545 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
546 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
547 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
548 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
549 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
550 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
551 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
552 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
553 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
554 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
555 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
556 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
557 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
558 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
559 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
560 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
561 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
562 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
563 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
564 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
565 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
566 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
567 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
568 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
569 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
570 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
571 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
572 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
573 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
574 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
575 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
576 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
577 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
578 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
579 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
580 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
581 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
582 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
583 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
584 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
585 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
586 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
587 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
588 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
589 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
590 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
591 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
592 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
593 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
594 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
595 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
596 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
597 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
598 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
599 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
600 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
601 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
602 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
603 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
604 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
605 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
606 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
607 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
608 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
609 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
610 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
611 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
612 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
613 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
614 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
615 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
616 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
617 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
618 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
619 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
620 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
621 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
622 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
623 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
624 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
625 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
626 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
627 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
628 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
629 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
630 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
631 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
632 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
633 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
634 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
635 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
636 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
637 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
638 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
639 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
640 (micromips_opcodes): New declaration.
641 (bfd_micromips_num_opcodes): Likewise.
643 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
645 * mips.h (INSN_TRAP): Rename to...
646 (INSN_NO_DELAY_SLOT): ... this.
647 (INSN_SYNC): Remove macro.
649 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
651 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
652 a duplicate of AVR_ISA_SPM.
654 2011-07-01 Nick Clifton <nickc@redhat.com>
656 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
658 2011-06-18 Robin Getz <robin.getz@analog.com>
660 * bfin.h (is_macmod_signed): New func
662 2011-06-18 Mike Frysinger <vapier@gentoo.org>
664 * bfin.h (is_macmod_pmove): Add missing space before func args.
665 (is_macmod_hmove): Likewise.
667 2011-06-13 Walter Lee <walt@tilera.com>
669 * tilegx.h: New file.
670 * tilepro.h: New file.
672 2011-05-31 Paul Brook <paul@codesourcery.com>
674 * arm.h (ARM_ARCH_V7R_IDIV): Define.
676 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
678 * s390.h: Replace S390_OPERAND_REG_EVEN with
679 S390_OPERAND_REG_PAIR.
681 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
683 * s390.h: Add S390_OPCODE_REG_EVEN flag.
685 2011-04-18 Julian Brown <julian@codesourcery.com>
687 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
689 2011-04-11 Dan McDonald <dan@wellkeeper.com>
692 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
694 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
696 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
697 New instruction set flags.
698 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
700 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
702 * mips.h (M_PREF_AB): New enum value.
704 2011-02-12 Mike Frysinger <vapier@gentoo.org>
706 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
708 (is_macmod_pmove, is_macmod_hmove): New functions.
710 2011-02-11 Mike Frysinger <vapier@gentoo.org>
712 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
714 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
716 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
717 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
719 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
722 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
725 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
728 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
730 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
732 * mips.h: Update commentary after last commit.
734 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
736 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
737 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
738 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
740 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
742 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
744 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
746 * mips.h: Fix previous commit.
748 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
750 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
751 (INSN_LOONGSON_3A): Clear bit 31.
753 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
756 * arm.h (ARM_AEXT_V6M_ONLY): New define.
757 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
758 (ARM_ARCH_V6M_ONLY): New define.
760 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
762 * mips.h (INSN_LOONGSON_3A): Defined.
763 (CPU_LOONGSON_3A): Defined.
764 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
766 2010-10-09 Matt Rice <ratmice@gmail.com>
768 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
769 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
771 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
773 * arm.h (ARM_EXT_VIRT): New define.
774 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
775 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
778 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
780 * arm.h (ARM_AEXT_ADIV): New define.
781 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
783 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
785 * arm.h (ARM_EXT_OS): New define.
786 (ARM_AEXT_V6SM): Likewise.
787 (ARM_ARCH_V6SM): Likewise.
789 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
791 * arm.h (ARM_EXT_MP): Add.
792 (ARM_ARCH_V7A_MP): Likewise.
794 2010-09-22 Mike Frysinger <vapier@gentoo.org>
796 * bfin.h: Declare pseudoChr structs/defines.
798 2010-09-21 Mike Frysinger <vapier@gentoo.org>
800 * bfin.h: Strip trailing whitespace.
802 2010-07-29 DJ Delorie <dj@redhat.com>
804 * rx.h (RX_Operand_Type): Add TwoReg.
805 (RX_Opcode_ID): Remove ediv and ediv2.
807 2010-07-27 DJ Delorie <dj@redhat.com>
809 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
811 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
812 Ina Pandit <ina.pandit@kpitcummins.com>
814 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
815 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
816 PROCESSOR_V850E2_ALL.
817 Remove PROCESSOR_V850EA support.
818 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
819 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
820 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
821 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
822 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
823 V850_OPERAND_PERCENT.
824 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
826 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
829 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
831 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
832 (MIPS16_INSN_BRANCH): Rename to...
833 (MIPS16_INSN_COND_BRANCH): ... this.
835 2010-07-03 Alan Modra <amodra@gmail.com>
837 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
838 Renumber other PPC_OPCODE defines.
840 2010-07-03 Alan Modra <amodra@gmail.com>
842 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
844 2010-06-29 Alan Modra <amodra@gmail.com>
846 * maxq.h: Delete file.
848 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
850 * ppc.h (PPC_OPCODE_E500): Define.
852 2010-05-26 Catherine Moore <clm@codesourcery.com>
854 * opcode/mips.h (INSN_MIPS16): Remove.
856 2010-04-21 Joseph Myers <joseph@codesourcery.com>
858 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
860 2010-04-15 Nick Clifton <nickc@redhat.com>
862 * alpha.h: Update copyright notice to use GPLv3.
868 * convex.h: Likewise.
882 * m68hc11.h: Likewise.
888 * mn10200.h: Likewise.
889 * mn10300.h: Likewise.
890 * msp430.h: Likewise.
901 * score-datadep.h: Likewise.
902 * score-inst.h: Likewise.
904 * spu-insns.h: Likewise.
908 * tic54x.h: Likewise.
913 2010-03-25 Joseph Myers <joseph@codesourcery.com>
915 * tic6x-control-registers.h, tic6x-insn-formats.h,
916 tic6x-opcode-table.h, tic6x.h: New.
918 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
920 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
922 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
924 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
926 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
928 * ia64.h (ia64_find_opcode): Remove argument name.
929 (ia64_find_next_opcode): Likewise.
930 (ia64_dis_opcode): Likewise.
931 (ia64_free_opcode): Likewise.
932 (ia64_find_dependency): Likewise.
934 2009-11-22 Doug Evans <dje@sebabeach.org>
936 * cgen.h: Include bfd_stdint.h.
937 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
939 2009-11-18 Paul Brook <paul@codesourcery.com>
941 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
943 2009-11-17 Paul Brook <paul@codesourcery.com>
944 Daniel Jacobowitz <dan@codesourcery.com>
946 * arm.h (ARM_EXT_V6_DSP): Define.
947 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
948 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
950 2009-11-04 DJ Delorie <dj@redhat.com>
952 * rx.h (rx_decode_opcode) (mvtipl): Add.
953 (mvtcp, mvfcp, opecp): Remove.
955 2009-11-02 Paul Brook <paul@codesourcery.com>
957 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
958 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
959 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
960 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
961 FPU_ARCH_NEON_VFP_V4): Define.
963 2009-10-23 Doug Evans <dje@sebabeach.org>
965 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
966 * cgen.h: Update. Improve multi-inclusion macro name.
968 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
970 * ppc.h (PPC_OPCODE_476): Define.
972 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
974 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
976 2009-09-29 DJ Delorie <dj@redhat.com>
980 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
982 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
984 2009-09-21 Ben Elliston <bje@au.ibm.com>
986 * ppc.h (PPC_OPCODE_PPCA2): New.
988 2009-09-05 Martin Thuresson <martin@mtme.org>
990 * ia64.h (struct ia64_operand): Renamed member class to op_class.
992 2009-08-29 Martin Thuresson <martin@mtme.org>
994 * tic30.h (template): Rename type template to
995 insn_template. Updated code to use new name.
996 * tic54x.h (template): Rename type template to
999 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1001 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1003 2009-06-11 Anthony Green <green@moxielogic.com>
1005 * moxie.h (MOXIE_F3_PCREL): Define.
1006 (moxie_form3_opc_info): Grow.
1008 2009-06-06 Anthony Green <green@moxielogic.com>
1010 * moxie.h (MOXIE_F1_M): Define.
1012 2009-04-15 Anthony Green <green@moxielogic.com>
1016 2009-04-06 DJ Delorie <dj@redhat.com>
1018 * h8300.h: Add relaxation attributes to MOVA opcodes.
1020 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1022 * ppc.h (ppc_parse_cpu): Declare.
1024 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1026 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1027 and _IMM11 for mbitclr and mbitset.
1028 * score-datadep.h: Update dependency information.
1030 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1032 * ppc.h (PPC_OPCODE_POWER7): New.
1034 2009-02-06 Doug Evans <dje@google.com>
1036 * i386.h: Add comment regarding sse* insns and prefixes.
1038 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1040 * mips.h (INSN_XLR): Define.
1041 (INSN_CHIP_MASK): Update.
1043 (OPCODE_IS_MEMBER): Update.
1044 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1046 2009-01-28 Doug Evans <dje@google.com>
1048 * opcode/i386.h: Add multiple inclusion protection.
1049 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1050 (EDI_REG_NUM): New macros.
1051 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1052 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1053 (REX_PREFIX_P): New macro.
1055 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1057 * ppc.h (struct powerpc_opcode): New field "deprecated".
1058 (PPC_OPCODE_NOPOWER4): Delete.
1060 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1062 * mips.h: Define CPU_R14000, CPU_R16000.
1063 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1065 2008-11-18 Catherine Moore <clm@codesourcery.com>
1067 * arm.h (FPU_NEON_FP16): New.
1068 (FPU_ARCH_NEON_FP16): New.
1070 2008-11-06 Chao-ying Fu <fu@mips.com>
1072 * mips.h: Doucument '1' for 5-bit sync type.
1074 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1076 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1079 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1081 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1083 2008-07-30 Michael J. Eager <eager@eagercon.com>
1085 * ppc.h (PPC_OPCODE_405): Define.
1086 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1088 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1090 * ppc.h (ppc_cpu_t): New typedef.
1091 (struct powerpc_opcode <flags>): Use it.
1092 (struct powerpc_operand <insert, extract>): Likewise.
1093 (struct powerpc_macro <flags>): Likewise.
1095 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1097 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1098 Update comment before MIPS16 field descriptors to mention MIPS16.
1099 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1101 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1102 New bit masks and shift counts for cins and exts.
1104 * mips.h: Document new field descriptors +Q.
1105 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1107 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1109 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1110 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1112 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1114 * ppc.h: (PPC_OPCODE_E500MC): New.
1116 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1118 * i386.h (MAX_OPERANDS): Set to 5.
1119 (MAX_MNEM_SIZE): Changed to 20.
1121 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1123 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1125 2008-03-09 Paul Brook <paul@codesourcery.com>
1127 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1129 2008-03-04 Paul Brook <paul@codesourcery.com>
1131 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1132 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1133 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1135 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1136 Nick Clifton <nickc@redhat.com>
1139 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1140 with a 32-bit displacement but without the top bit of the 4th byte
1143 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1145 * cr16.h (cr16_num_optab): Declared.
1147 2008-02-14 Hakan Ardo <hakan@debian.org>
1150 * avr.h (AVR_ISA_2xxe): Define.
1152 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1154 * mips.h: Update copyright.
1155 (INSN_CHIP_MASK): New macro.
1156 (INSN_OCTEON): New macro.
1157 (CPU_OCTEON): New macro.
1158 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1160 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1162 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1164 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1166 * avr.h (AVR_ISA_USB162): Add new opcode set.
1167 (AVR_ISA_AVR3): Likewise.
1169 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1171 * mips.h (INSN_LOONGSON_2E): New.
1172 (INSN_LOONGSON_2F): New.
1173 (CPU_LOONGSON_2E): New.
1174 (CPU_LOONGSON_2F): New.
1175 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1177 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1179 * mips.h (INSN_ISA*): Redefine certain values as an
1180 enumeration. Update comments.
1181 (mips_isa_table): New.
1182 (ISA_MIPS*): Redefine to match enumeration.
1183 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1186 2007-08-08 Ben Elliston <bje@au.ibm.com>
1188 * ppc.h (PPC_OPCODE_PPCPS): New.
1190 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1192 * m68k.h: Document j K & E.
1194 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1196 * cr16.h: New file for CR16 target.
1198 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1200 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1202 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1204 * m68k.h (mcfisa_c): New.
1205 (mcfusp, mcf_mask): Adjust.
1207 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1209 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1210 (num_powerpc_operands): Declare.
1211 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1212 (PPC_OPERAND_PLUS1): Define.
1214 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1216 * i386.h (REX_MODE64): Renamed to ...
1218 (REX_EXTX): Renamed to ...
1220 (REX_EXTY): Renamed to ...
1222 (REX_EXTZ): Renamed to ...
1225 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1227 * i386.h: Add entries from config/tc-i386.h and move tables
1228 to opcodes/i386-opc.h.
1230 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1232 * i386.h (FloatDR): Removed.
1233 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1235 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1237 * spu-insns.h: Add soma double-float insns.
1239 2007-02-20 Thiemo Seufer <ths@mips.com>
1240 Chao-Ying Fu <fu@mips.com>
1242 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1243 (INSN_DSPR2): Add flag for DSP R2 instructions.
1244 (M_BALIGN): New macro.
1246 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1248 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1249 and Seg3ShortFrom with Shortform.
1251 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1254 * i386.h (i386_optab): Put the real "test" before the pseudo
1257 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1259 * m68k.h (m68010up): OR fido_a.
1261 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1263 * m68k.h (fido_a): New.
1265 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1267 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1268 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1271 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1273 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1275 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1277 * score-inst.h (enum score_insn_type): Add Insn_internal.
1279 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1280 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1281 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1282 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1283 Alan Modra <amodra@bigpond.net.au>
1285 * spu-insns.h: New file.
1288 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1290 * ppc.h (PPC_OPCODE_CELL): Define.
1292 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1294 * i386.h : Modify opcode to support for the change in POPCNT opcode
1295 in amdfam10 architecture.
1297 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1299 * i386.h: Replace CpuMNI with CpuSSSE3.
1301 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1302 Joseph Myers <joseph@codesourcery.com>
1303 Ian Lance Taylor <ian@wasabisystems.com>
1304 Ben Elliston <bje@wasabisystems.com>
1306 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1308 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1310 * score-datadep.h: New file.
1311 * score-inst.h: New file.
1313 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1315 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1316 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1317 movdq2q and movq2dq.
1319 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1320 Michael Meissner <michael.meissner@amd.com>
1322 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1324 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1326 * i386.h (i386_optab): Add "nop" with memory reference.
1328 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1330 * i386.h (i386_optab): Update comment for 64bit NOP.
1332 2006-06-06 Ben Elliston <bje@au.ibm.com>
1333 Anton Blanchard <anton@samba.org>
1335 * ppc.h (PPC_OPCODE_POWER6): Define.
1338 2006-06-05 Thiemo Seufer <ths@mips.com>
1340 * mips.h: Improve description of MT flags.
1342 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1344 * m68k.h (mcf_mask): Define.
1346 2006-05-05 Thiemo Seufer <ths@mips.com>
1347 David Ung <davidu@mips.com>
1349 * mips.h (enum): Add macro M_CACHE_AB.
1351 2006-05-04 Thiemo Seufer <ths@mips.com>
1352 Nigel Stephens <nigel@mips.com>
1353 David Ung <davidu@mips.com>
1355 * mips.h: Add INSN_SMARTMIPS define.
1357 2006-04-30 Thiemo Seufer <ths@mips.com>
1358 David Ung <davidu@mips.com>
1360 * mips.h: Defines udi bits and masks. Add description of
1361 characters which may appear in the args field of udi
1364 2006-04-26 Thiemo Seufer <ths@networkno.de>
1366 * mips.h: Improve comments describing the bitfield instruction
1369 2006-04-26 Julian Brown <julian@codesourcery.com>
1371 * arm.h (FPU_VFP_EXT_V3): Define constant.
1372 (FPU_NEON_EXT_V1): Likewise.
1373 (FPU_VFP_HARD): Update.
1374 (FPU_VFP_V3): Define macro.
1375 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1377 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1379 * avr.h (AVR_ISA_PWMx): New.
1381 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1383 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1384 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1385 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1386 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1387 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1389 2006-03-10 Paul Brook <paul@codesourcery.com>
1391 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1393 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1395 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1396 first. Correct mask of bb "B" opcode.
1398 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1400 * i386.h (i386_optab): Support Intel Merom New Instructions.
1402 2006-02-24 Paul Brook <paul@codesourcery.com>
1404 * arm.h: Add V7 feature bits.
1406 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1408 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1410 2006-01-31 Paul Brook <paul@codesourcery.com>
1411 Richard Earnshaw <rearnsha@arm.com>
1413 * arm.h: Use ARM_CPU_FEATURE.
1414 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1415 (arm_feature_set): Change to a structure.
1416 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1417 ARM_FEATURE): New macros.
1419 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1421 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1422 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1423 (ADD_PC_INCR_OPCODE): Don't define.
1425 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1428 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1430 2005-11-14 David Ung <davidu@mips.com>
1432 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1433 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1434 save/restore encoding of the args field.
1436 2005-10-28 Dave Brolley <brolley@redhat.com>
1438 Contribute the following changes:
1439 2005-02-16 Dave Brolley <brolley@redhat.com>
1441 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1442 cgen_isa_mask_* to cgen_bitset_*.
1445 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1447 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1448 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1449 (CGEN_CPU_TABLE): Make isas a ponter.
1451 2003-09-29 Dave Brolley <brolley@redhat.com>
1453 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1454 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1455 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1457 2002-12-13 Dave Brolley <brolley@redhat.com>
1459 * cgen.h (symcat.h): #include it.
1460 (cgen-bitset.h): #include it.
1461 (CGEN_ATTR_VALUE_TYPE): Now a union.
1462 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1463 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1464 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1465 * cgen-bitset.h: New file.
1467 2005-09-30 Catherine Moore <clm@cm00re.com>
1471 2005-10-24 Jan Beulich <jbeulich@novell.com>
1473 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1476 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1478 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1479 Add FLAG_STRICT to pa10 ftest opcode.
1481 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1483 * hppa.h (pa_opcodes): Remove lha entries.
1485 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1487 * hppa.h (FLAG_STRICT): Revise comment.
1488 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1489 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1492 2005-09-30 Catherine Moore <clm@cm00re.com>
1496 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1498 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1500 2005-09-06 Chao-ying Fu <fu@mips.com>
1502 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1503 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1505 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1506 (INSN_ASE_MASK): Update to include INSN_MT.
1507 (INSN_MT): New define for MT ASE.
1509 2005-08-25 Chao-ying Fu <fu@mips.com>
1511 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1512 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1513 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1514 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1515 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1516 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1518 (INSN_DSP): New define for DSP ASE.
1520 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1524 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1526 * ppc.h (PPC_OPCODE_E300): Define.
1528 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1530 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1532 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1535 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1538 2005-07-27 Jan Beulich <jbeulich@novell.com>
1540 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1541 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1542 Add movq-s as 64-bit variants of movd-s.
1544 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1546 * hppa.h: Fix punctuation in comment.
1548 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1549 implicit space-register addressing. Set space-register bits on opcodes
1550 using implicit space-register addressing. Add various missing pa20
1551 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1552 space-register addressing. Use "fE" instead of "fe" in various
1555 2005-07-18 Jan Beulich <jbeulich@novell.com>
1557 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1559 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1561 * i386.h (i386_optab): Support Intel VMX Instructions.
1563 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1565 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1567 2005-07-05 Jan Beulich <jbeulich@novell.com>
1569 * i386.h (i386_optab): Add new insns.
1571 2005-07-01 Nick Clifton <nickc@redhat.com>
1573 * sparc.h: Add typedefs to structure declarations.
1575 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1578 * i386.h (i386_optab): Update comments for 64bit addressing on
1579 mov. Allow 64bit addressing for mov and movq.
1581 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1583 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1584 respectively, in various floating-point load and store patterns.
1586 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1588 * hppa.h (FLAG_STRICT): Correct comment.
1589 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1590 PA 2.0 mneumonics when equivalent. Entries with cache control
1591 completers now require PA 1.1. Adjust whitespace.
1593 2005-05-19 Anton Blanchard <anton@samba.org>
1595 * ppc.h (PPC_OPCODE_POWER5): Define.
1597 2005-05-10 Nick Clifton <nickc@redhat.com>
1599 * Update the address and phone number of the FSF organization in
1600 the GPL notices in the following files:
1601 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1602 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1603 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1604 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1605 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1606 tic54x.h, tic80.h, v850.h, vax.h
1608 2005-05-09 Jan Beulich <jbeulich@novell.com>
1610 * i386.h (i386_optab): Add ht and hnt.
1612 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1614 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1615 Add xcrypt-ctr. Provide aliases without hyphens.
1617 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1619 Moved from ../ChangeLog
1621 2005-04-12 Paul Brook <paul@codesourcery.com>
1622 * m88k.h: Rename psr macros to avoid conflicts.
1624 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1625 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1626 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1627 and ARM_ARCH_V6ZKT2.
1629 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1630 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1631 Remove redundant instruction types.
1632 (struct argument): X_op - new field.
1633 (struct cst4_entry): Remove.
1634 (no_op_insn): Declare.
1636 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1637 * crx.h (enum argtype): Rename types, remove unused types.
1639 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1640 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1641 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1642 (enum operand_type): Rearrange operands, edit comments.
1643 replace us<N> with ui<N> for unsigned immediate.
1644 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1645 displacements (respectively).
1646 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1647 (instruction type): Add NO_TYPE_INS.
1648 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1649 (operand_entry): New field - 'flags'.
1650 (operand flags): New.
1652 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1653 * crx.h (operand_type): Remove redundant types i3, i4,
1655 Add new unsigned immediate types us3, us4, us5, us16.
1657 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1659 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1660 adjust them accordingly.
1662 2005-04-01 Jan Beulich <jbeulich@novell.com>
1664 * i386.h (i386_optab): Add rdtscp.
1666 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1668 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1669 between memory and segment register. Allow movq for moving between
1670 general-purpose register and segment register.
1672 2005-02-09 Jan Beulich <jbeulich@novell.com>
1675 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1676 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1679 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1681 * m68k.h (m68008, m68ec030, m68882): Remove.
1683 (cpu_m68k, cpu_cf): New.
1684 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1685 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1687 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1689 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1690 * cgen.h (enum cgen_parse_operand_type): Add
1691 CGEN_PARSE_OPERAND_SYMBOLIC.
1693 2005-01-21 Fred Fish <fnf@specifixinc.com>
1695 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1696 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1697 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1699 2005-01-19 Fred Fish <fnf@specifixinc.com>
1701 * mips.h (struct mips_opcode): Add new pinfo2 member.
1702 (INSN_ALIAS): New define for opcode table entries that are
1703 specific instances of another entry, such as 'move' for an 'or'
1704 with a zero operand.
1705 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1706 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1708 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1710 * mips.h (CPU_RM9000): Define.
1711 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1713 2004-11-25 Jan Beulich <jbeulich@novell.com>
1715 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1716 to/from test registers are illegal in 64-bit mode. Add missing
1717 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1718 (previously one had to explicitly encode a rex64 prefix). Re-enable
1719 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1720 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1722 2004-11-23 Jan Beulich <jbeulich@novell.com>
1724 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1725 available only with SSE2. Change the MMX additions introduced by SSE
1726 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1727 instructions by their now designated identifier (since combining i686
1728 and 3DNow! does not really imply 3DNow!A).
1730 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1732 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1733 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1735 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1736 Vineet Sharma <vineets@noida.hcltech.com>
1738 * maxq.h: New file: Disassembly information for the maxq port.
1740 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1742 * i386.h (i386_optab): Put back "movzb".
1744 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1746 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1747 comments. Remove member cris_ver_sim. Add members
1748 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1749 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1750 (struct cris_support_reg, struct cris_cond15): New types.
1751 (cris_conds15): Declare.
1752 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1753 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1754 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1755 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1756 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1757 SIZE_FIELD_UNSIGNED.
1759 2004-11-04 Jan Beulich <jbeulich@novell.com>
1761 * i386.h (sldx_Suf): Remove.
1762 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1763 (q_FP): Define, implying no REX64.
1764 (x_FP, sl_FP): Imply FloatMF.
1765 (i386_optab): Split reg and mem forms of moving from segment registers
1766 so that the memory forms can ignore the 16-/32-bit operand size
1767 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1768 all non-floating-point instructions. Unite 32- and 64-bit forms of
1769 movsx, movzx, and movd. Adjust floating point operations for the above
1770 changes to the *FP macros. Add DefaultSize to floating point control
1771 insns operating on larger memory ranges. Remove left over comments
1772 hinting at certain insns being Intel-syntax ones where the ones
1773 actually meant are already gone.
1775 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1777 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1780 2004-09-30 Paul Brook <paul@codesourcery.com>
1782 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1783 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1785 2004-09-11 Theodore A. Roth <troth@openavr.org>
1787 * avr.h: Add support for
1788 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1790 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1792 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1794 2004-08-24 Dmitry Diky <diwil@spec.ru>
1796 * msp430.h (msp430_opc): Add new instructions.
1797 (msp430_rcodes): Declare new instructions.
1798 (msp430_hcodes): Likewise..
1800 2004-08-13 Nick Clifton <nickc@redhat.com>
1803 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1806 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1808 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1810 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1812 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1814 2004-07-21 Jan Beulich <jbeulich@novell.com>
1816 * i386.h: Adjust instruction descriptions to better match the
1819 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1821 * arm.h: Remove all old content. Replace with architecture defines
1822 from gas/config/tc-arm.c.
1824 2004-07-09 Andreas Schwab <schwab@suse.de>
1826 * m68k.h: Fix comment.
1828 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1832 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1834 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1836 2004-05-24 Peter Barada <peter@the-baradas.com>
1838 * m68k.h: Add 'size' to m68k_opcode.
1840 2004-05-05 Peter Barada <peter@the-baradas.com>
1842 * m68k.h: Switch from ColdFire chip name to core variant.
1844 2004-04-22 Peter Barada <peter@the-baradas.com>
1846 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1847 descriptions for new EMAC cases.
1848 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1849 handle Motorola MAC syntax.
1850 Allow disassembly of ColdFire V4e object files.
1852 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1854 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1856 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1858 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1860 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1862 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1864 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1866 * i386.h (i386_optab): Added xstore/xcrypt insns.
1868 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1870 * h8300.h (32bit ldc/stc): Add relaxing support.
1872 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1874 * h8300.h (BITOP): Pass MEMRELAX flag.
1876 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1878 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1881 For older changes see ChangeLog-9103
1883 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1885 Copying and distribution of this file, with or without modification,
1886 are permitted in any medium without royalty provided the copyright
1887 notice and this notice are preserved.
1893 version-control: never