1 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
3 * m68k.h: Document j K & E.
5 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
7 * cr16.h: New file for CR16 target.
9 2007-05-02 Alan Modra <amodra@bigpond.net.au>
11 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
13 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
15 * m68k.h (mcfisa_c): New.
16 (mcfusp, mcf_mask): Adjust.
18 2007-04-20 Alan Modra <amodra@bigpond.net.au>
20 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
21 (num_powerpc_operands): Declare.
22 (PPC_OPERAND_SIGNED et al): Redefine as hex.
23 (PPC_OPERAND_PLUS1): Define.
25 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
27 * i386.h (REX_MODE64): Renamed to ...
29 (REX_EXTX): Renamed to ...
31 (REX_EXTY): Renamed to ...
33 (REX_EXTZ): Renamed to ...
36 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
38 * i386.h: Add entries from config/tc-i386.h and move tables
39 to opcodes/i386-opc.h.
41 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
43 * i386.h (FloatDR): Removed.
44 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
46 2007-03-01 Alan Modra <amodra@bigpond.net.au>
48 * spu-insns.h: Add soma double-float insns.
50 2007-02-20 Thiemo Seufer <ths@mips.com>
51 Chao-Ying Fu <fu@mips.com>
53 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
54 (INSN_DSPR2): Add flag for DSP R2 instructions.
55 (M_BALIGN): New macro.
57 2007-02-14 Alan Modra <amodra@bigpond.net.au>
59 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
60 and Seg3ShortFrom with Shortform.
62 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
65 * i386.h (i386_optab): Put the real "test" before the pseudo
68 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
70 * m68k.h (m68010up): OR fido_a.
72 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
74 * m68k.h (fido_a): New.
76 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
78 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
79 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
82 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
84 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
86 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
88 * score-inst.h (enum score_insn_type): Add Insn_internal.
90 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
91 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
92 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
93 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
94 Alan Modra <amodra@bigpond.net.au>
96 * spu-insns.h: New file.
99 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
101 * ppc.h (PPC_OPCODE_CELL): Define.
103 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
105 * i386.h : Modify opcode to support for the change in POPCNT opcode
106 in amdfam10 architecture.
108 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
110 * i386.h: Replace CpuMNI with CpuSSSE3.
112 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
113 Joseph Myers <joseph@codesourcery.com>
114 Ian Lance Taylor <ian@wasabisystems.com>
115 Ben Elliston <bje@wasabisystems.com>
117 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
119 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
121 * score-datadep.h: New file.
122 * score-inst.h: New file.
124 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
126 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
127 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
130 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
131 Michael Meissner <michael.meissner@amd.com>
133 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
135 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
137 * i386.h (i386_optab): Add "nop" with memory reference.
139 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
141 * i386.h (i386_optab): Update comment for 64bit NOP.
143 2006-06-06 Ben Elliston <bje@au.ibm.com>
144 Anton Blanchard <anton@samba.org>
146 * ppc.h (PPC_OPCODE_POWER6): Define.
149 2006-06-05 Thiemo Seufer <ths@mips.com>
151 * mips.h: Improve description of MT flags.
153 2006-05-25 Richard Sandiford <richard@codesourcery.com>
155 * m68k.h (mcf_mask): Define.
157 2006-05-05 Thiemo Seufer <ths@mips.com>
158 David Ung <davidu@mips.com>
160 * mips.h (enum): Add macro M_CACHE_AB.
162 2006-05-04 Thiemo Seufer <ths@mips.com>
163 Nigel Stephens <nigel@mips.com>
164 David Ung <davidu@mips.com>
166 * mips.h: Add INSN_SMARTMIPS define.
168 2006-04-30 Thiemo Seufer <ths@mips.com>
169 David Ung <davidu@mips.com>
171 * mips.h: Defines udi bits and masks. Add description of
172 characters which may appear in the args field of udi
175 2006-04-26 Thiemo Seufer <ths@networkno.de>
177 * mips.h: Improve comments describing the bitfield instruction
180 2006-04-26 Julian Brown <julian@codesourcery.com>
182 * arm.h (FPU_VFP_EXT_V3): Define constant.
183 (FPU_NEON_EXT_V1): Likewise.
184 (FPU_VFP_HARD): Update.
185 (FPU_VFP_V3): Define macro.
186 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
188 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
190 * avr.h (AVR_ISA_PWMx): New.
192 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
194 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
195 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
196 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
197 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
198 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
200 2006-03-10 Paul Brook <paul@codesourcery.com>
202 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
204 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
206 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
207 first. Correct mask of bb "B" opcode.
209 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
211 * i386.h (i386_optab): Support Intel Merom New Instructions.
213 2006-02-24 Paul Brook <paul@codesourcery.com>
215 * arm.h: Add V7 feature bits.
217 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
219 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
221 2006-01-31 Paul Brook <paul@codesourcery.com>
222 Richard Earnshaw <rearnsha@arm.com>
224 * arm.h: Use ARM_CPU_FEATURE.
225 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
226 (arm_feature_set): Change to a structure.
227 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
228 ARM_FEATURE): New macros.
230 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
232 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
233 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
234 (ADD_PC_INCR_OPCODE): Don't define.
236 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
239 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
241 2005-11-14 David Ung <davidu@mips.com>
243 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
244 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
245 save/restore encoding of the args field.
247 2005-10-28 Dave Brolley <brolley@redhat.com>
249 Contribute the following changes:
250 2005-02-16 Dave Brolley <brolley@redhat.com>
252 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
253 cgen_isa_mask_* to cgen_bitset_*.
256 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
258 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
259 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
260 (CGEN_CPU_TABLE): Make isas a ponter.
262 2003-09-29 Dave Brolley <brolley@redhat.com>
264 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
265 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
266 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
268 2002-12-13 Dave Brolley <brolley@redhat.com>
270 * cgen.h (symcat.h): #include it.
271 (cgen-bitset.h): #include it.
272 (CGEN_ATTR_VALUE_TYPE): Now a union.
273 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
274 (CGEN_ATTR_ENTRY): 'value' now unsigned.
275 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
276 * cgen-bitset.h: New file.
278 2005-09-30 Catherine Moore <clm@cm00re.com>
282 2005-10-24 Jan Beulich <jbeulich@novell.com>
284 * ia64.h (enum ia64_opnd): Move memory operand out of set of
287 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
289 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
290 Add FLAG_STRICT to pa10 ftest opcode.
292 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
294 * hppa.h (pa_opcodes): Remove lha entries.
296 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
298 * hppa.h (FLAG_STRICT): Revise comment.
299 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
300 before corresponding pa11 opcodes. Add strict pa10 register-immediate
303 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
305 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
307 2005-09-06 Chao-ying Fu <fu@mips.com>
309 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
310 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
312 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
313 (INSN_ASE_MASK): Update to include INSN_MT.
314 (INSN_MT): New define for MT ASE.
316 2005-08-25 Chao-ying Fu <fu@mips.com>
318 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
319 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
320 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
321 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
322 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
323 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
325 (INSN_DSP): New define for DSP ASE.
327 2005-08-18 Alan Modra <amodra@bigpond.net.au>
331 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
333 * ppc.h (PPC_OPCODE_E300): Define.
335 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
337 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
339 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
342 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
345 2005-07-27 Jan Beulich <jbeulich@novell.com>
347 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
348 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
349 Add movq-s as 64-bit variants of movd-s.
351 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
353 * hppa.h: Fix punctuation in comment.
355 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
356 implicit space-register addressing. Set space-register bits on opcodes
357 using implicit space-register addressing. Add various missing pa20
358 long-immediate opcodes. Remove various opcodes using implicit 3-bit
359 space-register addressing. Use "fE" instead of "fe" in various
362 2005-07-18 Jan Beulich <jbeulich@novell.com>
364 * i386.h (i386_optab): Operands of aam and aad are unsigned.
366 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
368 * i386.h (i386_optab): Support Intel VMX Instructions.
370 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
372 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
374 2005-07-05 Jan Beulich <jbeulich@novell.com>
376 * i386.h (i386_optab): Add new insns.
378 2005-07-01 Nick Clifton <nickc@redhat.com>
380 * sparc.h: Add typedefs to structure declarations.
382 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
385 * i386.h (i386_optab): Update comments for 64bit addressing on
386 mov. Allow 64bit addressing for mov and movq.
388 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
390 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
391 respectively, in various floating-point load and store patterns.
393 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
395 * hppa.h (FLAG_STRICT): Correct comment.
396 (pa_opcodes): Update load and store entries to allow both PA 1.X and
397 PA 2.0 mneumonics when equivalent. Entries with cache control
398 completers now require PA 1.1. Adjust whitespace.
400 2005-05-19 Anton Blanchard <anton@samba.org>
402 * ppc.h (PPC_OPCODE_POWER5): Define.
404 2005-05-10 Nick Clifton <nickc@redhat.com>
406 * Update the address and phone number of the FSF organization in
407 the GPL notices in the following files:
408 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
409 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
410 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
411 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
412 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
413 tic54x.h, tic80.h, v850.h, vax.h
415 2005-05-09 Jan Beulich <jbeulich@novell.com>
417 * i386.h (i386_optab): Add ht and hnt.
419 2005-04-18 Mark Kettenis <kettenis@gnu.org>
421 * i386.h: Insert hyphens into selected VIA PadLock extensions.
422 Add xcrypt-ctr. Provide aliases without hyphens.
424 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
426 Moved from ../ChangeLog
428 2005-04-12 Paul Brook <paul@codesourcery.com>
429 * m88k.h: Rename psr macros to avoid conflicts.
431 2005-03-12 Zack Weinberg <zack@codesourcery.com>
432 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
433 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
436 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
437 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
438 Remove redundant instruction types.
439 (struct argument): X_op - new field.
440 (struct cst4_entry): Remove.
441 (no_op_insn): Declare.
443 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
444 * crx.h (enum argtype): Rename types, remove unused types.
446 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
447 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
448 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
449 (enum operand_type): Rearrange operands, edit comments.
450 replace us<N> with ui<N> for unsigned immediate.
451 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
452 displacements (respectively).
453 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
454 (instruction type): Add NO_TYPE_INS.
455 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
456 (operand_entry): New field - 'flags'.
457 (operand flags): New.
459 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
460 * crx.h (operand_type): Remove redundant types i3, i4,
462 Add new unsigned immediate types us3, us4, us5, us16.
464 2005-04-12 Mark Kettenis <kettenis@gnu.org>
466 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
467 adjust them accordingly.
469 2005-04-01 Jan Beulich <jbeulich@novell.com>
471 * i386.h (i386_optab): Add rdtscp.
473 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
475 * i386.h (i386_optab): Don't allow the `l' suffix for moving
476 between memory and segment register. Allow movq for moving between
477 general-purpose register and segment register.
479 2005-02-09 Jan Beulich <jbeulich@novell.com>
482 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
483 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
486 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
488 * m68k.h (m68008, m68ec030, m68882): Remove.
490 (cpu_m68k, cpu_cf): New.
491 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
492 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
494 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
496 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
497 * cgen.h (enum cgen_parse_operand_type): Add
498 CGEN_PARSE_OPERAND_SYMBOLIC.
500 2005-01-21 Fred Fish <fnf@specifixinc.com>
502 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
503 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
504 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
506 2005-01-19 Fred Fish <fnf@specifixinc.com>
508 * mips.h (struct mips_opcode): Add new pinfo2 member.
509 (INSN_ALIAS): New define for opcode table entries that are
510 specific instances of another entry, such as 'move' for an 'or'
512 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
513 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
515 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
517 * mips.h (CPU_RM9000): Define.
518 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
520 2004-11-25 Jan Beulich <jbeulich@novell.com>
522 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
523 to/from test registers are illegal in 64-bit mode. Add missing
524 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
525 (previously one had to explicitly encode a rex64 prefix). Re-enable
526 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
527 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
529 2004-11-23 Jan Beulich <jbeulich@novell.com>
531 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
532 available only with SSE2. Change the MMX additions introduced by SSE
533 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
534 instructions by their now designated identifier (since combining i686
535 and 3DNow! does not really imply 3DNow!A).
537 2004-11-19 Alan Modra <amodra@bigpond.net.au>
539 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
540 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
542 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
543 Vineet Sharma <vineets@noida.hcltech.com>
545 * maxq.h: New file: Disassembly information for the maxq port.
547 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
549 * i386.h (i386_optab): Put back "movzb".
551 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
553 * cris.h (enum cris_insn_version_usage): Tweak formatting and
554 comments. Remove member cris_ver_sim. Add members
555 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
556 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
557 (struct cris_support_reg, struct cris_cond15): New types.
558 (cris_conds15): Declare.
559 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
560 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
561 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
562 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
563 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
566 2004-11-04 Jan Beulich <jbeulich@novell.com>
568 * i386.h (sldx_Suf): Remove.
569 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
570 (q_FP): Define, implying no REX64.
571 (x_FP, sl_FP): Imply FloatMF.
572 (i386_optab): Split reg and mem forms of moving from segment registers
573 so that the memory forms can ignore the 16-/32-bit operand size
574 distinction. Adjust a few others for Intel mode. Remove *FP uses from
575 all non-floating-point instructions. Unite 32- and 64-bit forms of
576 movsx, movzx, and movd. Adjust floating point operations for the above
577 changes to the *FP macros. Add DefaultSize to floating point control
578 insns operating on larger memory ranges. Remove left over comments
579 hinting at certain insns being Intel-syntax ones where the ones
580 actually meant are already gone.
582 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
584 * crx.h: Add COPS_REG_INS - Coprocessor Special register
587 2004-09-30 Paul Brook <paul@codesourcery.com>
589 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
590 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
592 2004-09-11 Theodore A. Roth <troth@openavr.org>
594 * avr.h: Add support for
595 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
597 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
599 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
601 2004-08-24 Dmitry Diky <diwil@spec.ru>
603 * msp430.h (msp430_opc): Add new instructions.
604 (msp430_rcodes): Declare new instructions.
605 (msp430_hcodes): Likewise..
607 2004-08-13 Nick Clifton <nickc@redhat.com>
610 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
613 2004-08-30 Michal Ludvig <mludvig@suse.cz>
615 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
617 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
619 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
621 2004-07-21 Jan Beulich <jbeulich@novell.com>
623 * i386.h: Adjust instruction descriptions to better match the
626 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
628 * arm.h: Remove all old content. Replace with architecture defines
629 from gas/config/tc-arm.c.
631 2004-07-09 Andreas Schwab <schwab@suse.de>
633 * m68k.h: Fix comment.
635 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
639 2004-06-24 Alan Modra <amodra@bigpond.net.au>
641 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
643 2004-05-24 Peter Barada <peter@the-baradas.com>
645 * m68k.h: Add 'size' to m68k_opcode.
647 2004-05-05 Peter Barada <peter@the-baradas.com>
649 * m68k.h: Switch from ColdFire chip name to core variant.
651 2004-04-22 Peter Barada <peter@the-baradas.com>
653 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
654 descriptions for new EMAC cases.
655 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
656 handle Motorola MAC syntax.
657 Allow disassembly of ColdFire V4e object files.
659 2004-03-16 Alan Modra <amodra@bigpond.net.au>
661 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
663 2004-03-12 Jakub Jelinek <jakub@redhat.com>
665 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
667 2004-03-12 Michal Ludvig <mludvig@suse.cz>
669 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
671 2004-03-12 Michal Ludvig <mludvig@suse.cz>
673 * i386.h (i386_optab): Added xstore/xcrypt insns.
675 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
677 * h8300.h (32bit ldc/stc): Add relaxing support.
679 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
681 * h8300.h (BITOP): Pass MEMRELAX flag.
683 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
685 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
688 For older changes see ChangeLog-9103
694 version-control: never