1 2015-10-28 Yao Qi <yao.qi@linaro.org>
3 * aarch64.h (aarch64_decode_insn): Update declaration.
5 2015-10-07 Yao Qi <yao.qi@linaro.org>
7 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
10 2015-10-07 Yao Qi <yao.qi@linaro.org>
12 * aarch64.h [__cplusplus]: Wrap in extern "C".
14 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
15 Cupertino Miranda <cmiranda@synopsys.com>
17 * arc-func.h: New file.
20 2015-10-02 Yao Qi <yao.qi@linaro.org>
22 * aarch64.h (aarch64_zero_register_p): Move the declaration
25 2015-10-02 Yao Qi <yao.qi@linaro.org>
27 * aarch64.h (aarch64_decode_insn): Declare it.
29 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
31 * s390.h (S390_INSTR_FLAG_HTM): New flag.
32 (S390_INSTR_FLAG_VX): New flag.
33 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
35 2015-09-23 Nick Clifton <nickc@redhat.com>
37 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
40 2015-09-22 Nick Clifton <nickc@redhat.com>
42 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
44 2015-09-09 Daniel Santos <daniel.santos@pobox.com>
46 * visium.h (gen_reg_table): Make static.
47 (fp_reg_table): Likewise.
50 2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
52 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
53 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
54 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
55 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
57 2015-07-03 Alan Modra <amodra@gmail.com>
59 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
61 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
62 Cesar Philippidis <cesar@codesourcery.com>
64 * nios2.h (enum iw_format_type): Add R2 formats.
65 (enum overflow_type): Add signed_immed12_overflow and
66 enumeration_overflow for R2.
67 (struct nios2_opcode): Document new argument letters for R2.
68 (REG_3BIT, REG_LDWM, REG_POP): Define.
69 (includes): Include nios2r2.h.
70 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
71 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
72 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
73 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
74 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
75 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
77 * nios2r2.h: New file.
79 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
81 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
82 (ppc_optional_operand_value): New inline function.
84 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
86 * aarch64.h (AARCH64_V8_1): New.
88 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
90 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
91 (ARM_ARCH_V8_1A): New.
92 (ARM_ARCH_V8_1A_FP): New.
93 (ARM_ARCH_V8_1A_SIMD): New.
94 (ARM_ARCH_V8_1A_CRYPTOV1): New.
95 (ARM_FEATURE_CORE): New.
97 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
99 * arm.h (ARM_EXT2_PAN): New.
100 (ARM_FEATURE_CORE_HIGH): New.
102 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
104 * arm.h (ARM_FEATURE_ALL): New.
106 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
108 * aarch64.h (AARCH64_FEATURE_RDMA): New.
110 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
112 * aarch64.h (AARCH64_FEATURE_LOR): New.
114 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
116 * aarch64.h (AARCH64_FEATURE_PAN): New.
117 (aarch64_sys_reg_supported_p): Declare.
118 (aarch64_pstatefield_supported_p): Declare.
120 2015-04-30 DJ Delorie <dj@redhat.com>
122 * rl78.h (RL78_Dis_Isa): New.
123 (rl78_decode_opcode): Add ISA parameter.
125 2015-03-24 Terry Guo <terry.guo@arm.com>
127 * arm.h (arm_feature_set): Extended to provide more available bits.
128 (ARM_ANY): Updated to follow above new definition.
129 (ARM_CPU_HAS_FEATURE): Likewise.
130 (ARM_CPU_IS_ANY): Likewise.
131 (ARM_MERGE_FEATURE_SETS): Likewise.
132 (ARM_CLEAR_FEATURE): Likewise.
133 (ARM_FEATURE): Likewise.
134 (ARM_FEATURE_COPY): New macro.
135 (ARM_FEATURE_EQUAL): Likewise.
136 (ARM_FEATURE_ZERO): Likewise.
137 (ARM_FEATURE_CORE_EQUAL): Likewise.
138 (ARM_FEATURE_LOW): Likewise.
139 (ARM_FEATURE_CORE_LOW): Likewise.
140 (ARM_FEATURE_CORE_COPROC): Likewise.
142 2015-02-19 Pedro Alves <palves@redhat.com>
144 * cgen.h [__cplusplus]: Wrap in extern "C".
145 * msp430-decode.h [__cplusplus]: Likewise.
146 * nios2.h [__cplusplus]: Likewise.
147 * rl78.h [__cplusplus]: Likewise.
148 * rx.h [__cplusplus]: Likewise.
149 * tilegx.h [__cplusplus]: Likewise.
151 2015-01-28 James Bowman <james.bowman@ftdichip.com>
155 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
157 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
159 2015-01-01 Alan Modra <amodra@gmail.com>
161 Update year range in copyright notice of all files.
163 2014-12-27 Anthony Green <green@moxielogic.com>
165 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
166 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
168 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
170 * visium.h: New file.
172 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
174 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
175 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
176 (NIOS2_INSN_OPTARG): Renumber.
178 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
180 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
181 declaration. Fix obsolete comment.
183 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
185 * nios2.h (enum iw_format_type): New.
186 (struct nios2_opcode): Update comments. Add size and format fields.
187 (NIOS2_INSN_OPTARG): New.
188 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
189 (struct nios2_reg): Add regtype field.
190 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
191 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
192 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
193 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
194 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
195 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
196 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
197 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
198 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
199 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
200 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
201 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
202 (OP_MASK_OP, OP_SH_OP): Delete.
203 (OP_MASK_IOP, OP_SH_IOP): Delete.
204 (OP_MASK_IRD, OP_SH_IRD): Delete.
205 (OP_MASK_IRT, OP_SH_IRT): Delete.
206 (OP_MASK_IRS, OP_SH_IRS): Delete.
207 (OP_MASK_ROP, OP_SH_ROP): Delete.
208 (OP_MASK_RRD, OP_SH_RRD): Delete.
209 (OP_MASK_RRT, OP_SH_RRT): Delete.
210 (OP_MASK_RRS, OP_SH_RRS): Delete.
211 (OP_MASK_JOP, OP_SH_JOP): Delete.
212 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
213 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
214 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
215 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
216 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
217 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
218 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
219 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
220 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
221 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
222 (OP_MASK_<insn>, OP_MASK): Delete.
223 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
224 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
225 Include nios2r1.h to define new instruction opcode constants
227 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
228 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
229 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
230 (NUMOPCODES, NUMREGISTERS): Delete.
231 * nios2r1.h: New file.
233 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
235 * sparc.h (HWCAP2_VIS3B): Documentation improved.
237 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
239 * sparc.h (sparc_opcode): new field `hwcaps2'.
240 (HWCAP2_FJATHPLUS): New define.
241 (HWCAP2_VIS3B): Likewise.
242 (HWCAP2_ADP): Likewise.
243 (HWCAP2_SPARC5): Likewise.
244 (HWCAP2_MWAIT): Likewise.
245 (HWCAP2_XMPMUL): Likewise.
246 (HWCAP2_XMONT): Likewise.
247 (HWCAP2_NSEC): Likewise.
248 (HWCAP2_FJATHHPC): Likewise.
249 (HWCAP2_FJDES): Likewise.
250 (HWCAP2_FJAES): Likewise.
251 Document the new operand kind `{', corresponding to the mcdper
252 ancillary state register.
253 Document the new operand kind }, which represents frsd floating
254 point registers (double precision) which must be the same than
255 frs1 in its containing instruction.
257 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
259 * nds32.h: Add new opcode declaration.
261 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
262 Matthew Fortune <matthew.fortune@imgtec.com>
264 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
265 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
266 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
267 +I, +O, +R, +:, +\, +", +;
268 (mips_check_prev_operand): New struct.
269 (INSN2_FORBIDDEN_SLOT): New define.
270 (INSN_ISA32R6): New define.
271 (INSN_ISA64R6): New define.
272 (INSN_UPTO32R6): New define.
273 (INSN_UPTO64R6): New define.
274 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
275 (ISA_MIPS32R6): New define.
276 (ISA_MIPS64R6): New define.
277 (CPU_MIPS32R6): New define.
278 (CPU_MIPS64R6): New define.
279 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
281 2014-09-03 Jiong Wang <jiong.wang@arm.com>
283 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
284 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
285 (aarch64_insn_class): Add lse_atomic.
286 (F_LSE_SZ): New field added.
287 (opcode_has_special_coder): Recognize F_LSE_SZ.
289 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
291 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
294 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
296 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
297 (INSN_LOAD_COPROC): New define.
298 (INSN_COPROC_MOVE_DELAY): Rename to...
299 (INSN_COPROC_MOVE): New define.
301 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
302 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
303 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
304 Soundararajan <Sounderarajan.D@atmel.com>
306 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
307 (AVR_ISA_2xxxa): Define ISA without LPM.
308 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
309 Add doc for contraint used in 16 bit lds/sts.
310 Adjust ISA group for icall, ijmp, pop and push.
311 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
313 2014-05-19 Nick Clifton <nickc@redhat.com>
315 * msp430.h (struct msp430_operand_s): Add vshift field.
317 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
319 * mips.h (INSN_ISA_MASK): Updated.
320 (INSN_ISA32R3): New define.
321 (INSN_ISA32R5): New define.
322 (INSN_ISA64R3): New define.
323 (INSN_ISA64R5): New define.
324 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
325 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
326 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
328 (INSN_UPTO32R3): New define.
329 (INSN_UPTO32R5): New define.
330 (INSN_UPTO64R3): New define.
331 (INSN_UPTO64R5): New define.
332 (ISA_MIPS32R3): New define.
333 (ISA_MIPS32R5): New define.
334 (ISA_MIPS64R3): New define.
335 (ISA_MIPS64R5): New define.
336 (CPU_MIPS32R3): New define.
337 (CPU_MIPS32R5): New define.
338 (CPU_MIPS64R3): New define.
339 (CPU_MIPS64R5): New define.
341 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
343 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
345 2014-04-22 Christian Svensson <blue@cmd.nu>
349 2014-03-05 Alan Modra <amodra@gmail.com>
351 Update copyright years.
353 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
355 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
358 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
359 Wei-Cheng Wang <cole945@gmail.com>
361 * nds32.h: New file for Andes NDS32.
363 2013-12-07 Mike Frysinger <vapier@gentoo.org>
365 * bfin.h: Remove +x file mode.
367 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
369 * aarch64.h (aarch64_pstatefields): Change element type to
372 2013-11-18 Renlin Li <Renlin.Li@arm.com>
374 * arm.h (ARM_AEXT_V7VE): New define.
375 (ARM_ARCH_V7VE): New define.
376 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
378 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
382 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
384 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
385 (aarch64_sys_reg_writeonly_p): Ditto.
387 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
389 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
390 (aarch64_sys_reg_writeonly_p): Ditto.
392 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
394 * aarch64.h (aarch64_sys_reg): New typedef.
395 (aarch64_sys_regs): Change to define with the new type.
396 (aarch64_sys_reg_deprecated_p): Declare.
398 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
400 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
401 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
403 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
405 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
406 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
407 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
408 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
409 For MIPS, update extension character sequences after +.
410 (ASE_MSA): New define.
411 (ASE_MSA64): New define.
412 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
413 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
414 For microMIPS, update extension character sequences after +.
416 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
421 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
423 * mips.h: Remove references to "+I" and imm2_expr.
425 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
427 * mips.h (M_DEXT, M_DINS): Delete.
429 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
431 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
432 (mips_optional_operand_p): New function.
434 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
435 Richard Sandiford <rdsandiford@googlemail.com>
437 * mips.h: Document new VU0 operand characters.
438 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
439 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
440 (OP_REG_R5900_ACC): New mips_reg_operand_types.
441 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
442 (mips_vu0_channel_mask): Declare.
444 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
446 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
447 (mips_int_operand_min, mips_int_operand_max): New functions.
448 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
450 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
452 * mips.h (mips_decode_reg_operand): New function.
453 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
454 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
455 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
457 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
458 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
459 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
460 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
461 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
462 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
463 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
464 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
465 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
466 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
467 macros to cover the gaps.
468 (INSN2_MOD_SP): Replace with...
469 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
470 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
471 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
472 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
473 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
476 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
478 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
479 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
480 (MIPS16_INSN_COND_BRANCH): Delete.
482 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
483 Kirill Yukhin <kirill.yukhin@intel.com>
484 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
486 * i386.h (BND_PREFIX_OPCODE): New.
488 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
490 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
491 OP_SAVE_RESTORE_LIST.
492 (decode_mips16_operand): Declare.
494 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
496 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
497 (mips_operand, mips_int_operand, mips_mapped_int_operand)
498 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
499 (mips_pcrel_operand): New structures.
500 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
501 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
502 (decode_mips_operand, decode_micromips_operand): Declare.
504 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
506 * mips.h: Document MIPS16 "I" opcode.
508 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
510 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
511 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
512 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
513 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
514 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
515 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
516 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
517 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
518 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
519 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
520 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
521 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
522 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
524 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
525 (M_USD_AB): ...these.
527 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
529 * mips.h: Remove documentation of "[" and "]". Update documentation
530 of "k" and the MDMX formats.
532 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
534 * mips.h: Update documentation of "+s" and "+S".
536 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
538 * mips.h: Document "+i".
540 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
542 * mips.h: Remove "mi" documentation. Update "mh" documentation.
543 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
545 (INSN2_WRITE_GPR_MHI): Rename to...
546 (INSN2_WRITE_GPR_MH): ...this.
548 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
550 * mips.h: Remove documentation of "+D" and "+T".
552 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
554 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
555 Use "source" rather than "destination" for microMIPS "G".
557 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
559 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
562 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
564 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
566 2013-06-17 Catherine Moore <clm@codesourcery.com>
567 Maciej W. Rozycki <macro@codesourcery.com>
568 Chao-Ying Fu <fu@mips.com>
570 * mips.h (OP_SH_EVAOFFSET): Define.
571 (OP_MASK_EVAOFFSET): Define.
572 (INSN_ASE_MASK): Delete.
574 (M_CACHEE_AB, M_CACHEE_OB): New.
575 (M_LBE_OB, M_LBE_AB): New.
576 (M_LBUE_OB, M_LBUE_AB): New.
577 (M_LHE_OB, M_LHE_AB): New.
578 (M_LHUE_OB, M_LHUE_AB): New.
579 (M_LLE_AB, M_LLE_OB): New.
580 (M_LWE_OB, M_LWE_AB): New.
581 (M_LWLE_AB, M_LWLE_OB): New.
582 (M_LWRE_AB, M_LWRE_OB): New.
583 (M_PREFE_AB, M_PREFE_OB): New.
584 (M_SCE_AB, M_SCE_OB): New.
585 (M_SBE_OB, M_SBE_AB): New.
586 (M_SHE_OB, M_SHE_AB): New.
587 (M_SWE_OB, M_SWE_AB): New.
588 (M_SWLE_AB, M_SWLE_OB): New.
589 (M_SWRE_AB, M_SWRE_OB): New.
590 (MICROMIPSOP_SH_EVAOFFSET): Define.
591 (MICROMIPSOP_MASK_EVAOFFSET): Define.
593 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
595 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
597 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
599 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
601 2013-05-09 Andrew Pinski <apinski@cavium.com>
603 * mips.h (OP_MASK_CODE10): Correct definition.
604 (OP_SH_CODE10): Likewise.
605 Add a comment that "+J" is used now for OP_*CODE10.
606 (INSN_ASE_MASK): Update.
607 (INSN_VIRT): New macro.
608 (INSN_VIRT64): New macro
610 2013-05-02 Nick Clifton <nickc@redhat.com>
612 * msp430.h: Add patterns for MSP430X instructions.
614 2013-04-06 David S. Miller <davem@davemloft.net>
616 * sparc.h (F_PREFERRED): Define.
617 (F_PREF_ALIAS): Define.
619 2013-04-03 Nick Clifton <nickc@redhat.com>
621 * v850.h (V850_INVERSE_PCREL): Define.
623 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
626 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
628 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
631 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
633 * tic6xc-opcode-table.h: Add 16-bit insns.
634 * tic6x.h: Add support for 16-bit insns.
636 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
638 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
639 and mov.b/w/l Rs,@(d:32,ERd).
641 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
644 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
645 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
646 tic6x_operand_xregpair operand coding type.
647 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
648 opcode field, usu ORXREGD1324 for the src2 operand and remove the
651 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
654 * tic6x.h (enum tic6x_coding_method): Add
655 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
656 separately the msb and lsb of a register pair. This is needed to
657 encode the opcodes in the same way as TI assembler does.
658 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
659 and rsqrdp opcodes to use the new field coding types.
661 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
663 * arm.h (CRC_EXT_ARMV8): New constant.
664 (ARCH_CRC_ARMV8): New macro.
666 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
668 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
670 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
671 Andrew Jenner <andrew@codesourcery.com>
673 Based on patches from Altera Corporation.
677 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
679 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
681 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
684 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
686 2013-01-24 Nick Clifton <nickc@redhat.com>
688 * v850.h: Add e3v5 support.
690 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
692 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
694 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
696 * ppc.h (PPC_OPCODE_POWER8): New define.
697 (PPC_OPCODE_HTM): Likewise.
699 2013-01-10 Will Newton <will.newton@imgtec.com>
703 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
705 * cr16.h (make_instruction): Rename to cr16_make_instruction.
706 (match_opcode): Rename to cr16_match_opcode.
708 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
710 * mips.h: Add support for r5900 instructions including lq and sq.
712 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
714 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
715 (make_instruction,match_opcode): Added function prototypes.
716 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
718 2012-11-23 Alan Modra <amodra@gmail.com>
720 * ppc.h (ppc_parse_cpu): Update prototype.
722 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
724 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
725 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
727 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
729 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
731 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
733 * ia64.h (ia64_opnd): Add new operand types.
735 2012-08-21 David S. Miller <davem@davemloft.net>
737 * sparc.h (F3F4): New macro.
739 2012-08-13 Ian Bolton <ian.bolton@arm.com>
740 Laurent Desnogues <laurent.desnogues@arm.com>
741 Jim MacArthur <jim.macarthur@arm.com>
742 Marcus Shawcroft <marcus.shawcroft@arm.com>
743 Nigel Stephens <nigel.stephens@arm.com>
744 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
745 Richard Earnshaw <rearnsha@arm.com>
746 Sofiane Naci <sofiane.naci@arm.com>
747 Tejas Belagod <tejas.belagod@arm.com>
748 Yufeng Zhang <yufeng.zhang@arm.com>
750 * aarch64.h: New file.
752 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
753 Maciej W. Rozycki <macro@codesourcery.com>
755 * mips.h (mips_opcode): Add the exclusions field.
756 (OPCODE_IS_MEMBER): Remove macro.
757 (cpu_is_member): New inline function.
758 (opcode_is_member): Likewise.
760 2012-07-31 Chao-Ying Fu <fu@mips.com>
761 Catherine Moore <clm@codesourcery.com>
762 Maciej W. Rozycki <macro@codesourcery.com>
764 * mips.h: Document microMIPS DSP ASE usage.
765 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
766 microMIPS DSP ASE support.
767 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
768 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
769 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
770 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
771 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
772 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
773 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
775 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
777 * mips.h: Fix a typo in description.
779 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
781 * avr.h: (AVR_ISA_XCH): New define.
782 (AVR_ISA_XMEGA): Use it.
783 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
785 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
787 * m68hc11.h: Add XGate definitions.
788 (struct m68hc11_opcode): Add xg_mask field.
790 2012-05-14 Catherine Moore <clm@codesourcery.com>
791 Maciej W. Rozycki <macro@codesourcery.com>
792 Rhonda Wittels <rhonda@codesourcery.com>
794 * ppc.h (PPC_OPCODE_VLE): New definition.
795 (PPC_OP_SA): New macro.
796 (PPC_OP_SE_VLE): New macro.
797 (PPC_OP): Use a variable shift amount.
798 (powerpc_operand): Update comments.
799 (PPC_OPSHIFT_INV): New macro.
800 (PPC_OPERAND_CR): Replace with...
801 (PPC_OPERAND_CR_BIT): ...this and
802 (PPC_OPERAND_CR_REG): ...this.
805 2012-05-03 Sean Keys <skeys@ipdatasys.com>
807 * xgate.h: Header file for XGATE assembler.
809 2012-04-27 David S. Miller <davem@davemloft.net>
811 * sparc.h: Document new arg code' )' for crypto RS3
814 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
815 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
816 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
817 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
818 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
819 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
820 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
821 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
822 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
823 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
824 HWCAP_CBCOND, HWCAP_CRC32): New defines.
826 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
828 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
830 2012-02-27 Alan Modra <amodra@gmail.com>
832 * crx.h (cst4_map): Update declaration.
834 2012-02-25 Walter Lee <walt@tilera.com>
836 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
838 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
839 TILEPRO_OPC_LW_TLS_SN.
841 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
843 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
844 (XRELEASE_PREFIX_OPCODE): Likewise.
846 2011-12-08 Andrew Pinski <apinski@cavium.com>
847 Adam Nemet <anemet@caviumnetworks.com>
849 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
850 (INSN_OCTEON2): New macro.
851 (CPU_OCTEON2): New macro.
852 (OPCODE_IS_MEMBER): Add Octeon2.
854 2011-11-29 Andrew Pinski <apinski@cavium.com>
856 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
857 (INSN_OCTEONP): New macro.
858 (CPU_OCTEONP): New macro.
859 (OPCODE_IS_MEMBER): Add Octeon+.
860 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
862 2011-11-01 DJ Delorie <dj@redhat.com>
866 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
868 * mips.h: Fix a typo in description.
870 2011-09-21 David S. Miller <davem@davemloft.net>
872 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
873 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
874 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
875 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
877 2011-08-09 Chao-ying Fu <fu@mips.com>
878 Maciej W. Rozycki <macro@codesourcery.com>
880 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
881 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
882 (INSN_ASE_MASK): Add the MCU bit.
883 (INSN_MCU): New macro.
884 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
885 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
887 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
889 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
890 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
891 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
892 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
893 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
894 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
895 (INSN2_READ_GPR_MMN): Likewise.
896 (INSN2_READ_FPR_D): Change the bit used.
897 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
898 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
899 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
900 (INSN2_COND_BRANCH): Likewise.
901 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
902 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
903 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
904 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
905 (INSN2_MOD_GPR_MN): Likewise.
907 2011-08-05 David S. Miller <davem@davemloft.net>
909 * sparc.h: Document new format codes '4', '5', and '('.
910 (OPF_LOW4, RS3): New macros.
912 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
914 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
915 order of flags documented.
917 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
919 * mips.h: Clarify the description of microMIPS instruction
921 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
923 2011-07-24 Chao-ying Fu <fu@mips.com>
924 Maciej W. Rozycki <macro@codesourcery.com>
926 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
927 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
928 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
929 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
930 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
931 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
932 (OP_MASK_RS3, OP_SH_RS3): Likewise.
933 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
934 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
935 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
936 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
937 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
938 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
939 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
940 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
941 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
942 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
943 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
944 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
945 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
946 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
947 (INSN_WRITE_GPR_S): New macro.
948 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
949 (INSN2_READ_FPR_D): Likewise.
950 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
951 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
952 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
953 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
954 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
955 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
956 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
957 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
958 (CPU_MICROMIPS): New macro.
959 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
960 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
961 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
962 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
963 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
964 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
965 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
966 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
967 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
968 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
969 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
970 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
971 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
972 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
973 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
974 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
975 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
976 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
977 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
978 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
979 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
980 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
981 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
982 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
983 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
984 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
985 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
986 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
987 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
988 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
989 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
990 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
991 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
992 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
993 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
994 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
995 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
996 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
997 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
998 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
999 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1000 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1001 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1002 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1003 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1004 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1005 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1006 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1007 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1008 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1009 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1010 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1011 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1012 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1013 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1014 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1015 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1016 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1017 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1018 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1019 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1020 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1021 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1022 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1023 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1024 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1025 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1026 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1027 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1028 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1029 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1030 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1031 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1032 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1033 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1034 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1035 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1036 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1037 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1038 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1039 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1040 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1041 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1042 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1043 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1044 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1045 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1046 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1047 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1048 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1049 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1050 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1051 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1052 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1053 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1054 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1055 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1056 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1057 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1058 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1059 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1060 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1061 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1062 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1063 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1064 (micromips_opcodes): New declaration.
1065 (bfd_micromips_num_opcodes): Likewise.
1067 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1069 * mips.h (INSN_TRAP): Rename to...
1070 (INSN_NO_DELAY_SLOT): ... this.
1071 (INSN_SYNC): Remove macro.
1073 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1075 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1076 a duplicate of AVR_ISA_SPM.
1078 2011-07-01 Nick Clifton <nickc@redhat.com>
1080 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1082 2011-06-18 Robin Getz <robin.getz@analog.com>
1084 * bfin.h (is_macmod_signed): New func
1086 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1088 * bfin.h (is_macmod_pmove): Add missing space before func args.
1089 (is_macmod_hmove): Likewise.
1091 2011-06-13 Walter Lee <walt@tilera.com>
1093 * tilegx.h: New file.
1094 * tilepro.h: New file.
1096 2011-05-31 Paul Brook <paul@codesourcery.com>
1098 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1100 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1102 * s390.h: Replace S390_OPERAND_REG_EVEN with
1103 S390_OPERAND_REG_PAIR.
1105 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1107 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1109 2011-04-18 Julian Brown <julian@codesourcery.com>
1111 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1113 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1116 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1118 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1120 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1121 New instruction set flags.
1122 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1124 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1126 * mips.h (M_PREF_AB): New enum value.
1128 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1130 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1132 (is_macmod_pmove, is_macmod_hmove): New functions.
1134 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1136 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1138 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1140 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1141 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1143 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1146 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1149 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1152 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1154 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1156 * mips.h: Update commentary after last commit.
1158 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1160 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1161 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1162 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1164 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1166 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1168 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1170 * mips.h: Fix previous commit.
1172 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1174 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1175 (INSN_LOONGSON_3A): Clear bit 31.
1177 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1180 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1181 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1182 (ARM_ARCH_V6M_ONLY): New define.
1184 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1186 * mips.h (INSN_LOONGSON_3A): Defined.
1187 (CPU_LOONGSON_3A): Defined.
1188 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1190 2010-10-09 Matt Rice <ratmice@gmail.com>
1192 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1193 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1195 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1197 * arm.h (ARM_EXT_VIRT): New define.
1198 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1199 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1202 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1204 * arm.h (ARM_AEXT_ADIV): New define.
1205 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1207 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1209 * arm.h (ARM_EXT_OS): New define.
1210 (ARM_AEXT_V6SM): Likewise.
1211 (ARM_ARCH_V6SM): Likewise.
1213 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1215 * arm.h (ARM_EXT_MP): Add.
1216 (ARM_ARCH_V7A_MP): Likewise.
1218 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1220 * bfin.h: Declare pseudoChr structs/defines.
1222 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1224 * bfin.h: Strip trailing whitespace.
1226 2010-07-29 DJ Delorie <dj@redhat.com>
1228 * rx.h (RX_Operand_Type): Add TwoReg.
1229 (RX_Opcode_ID): Remove ediv and ediv2.
1231 2010-07-27 DJ Delorie <dj@redhat.com>
1233 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1235 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1236 Ina Pandit <ina.pandit@kpitcummins.com>
1238 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1239 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1240 PROCESSOR_V850E2_ALL.
1241 Remove PROCESSOR_V850EA support.
1242 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1243 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1244 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1245 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1246 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1247 V850_OPERAND_PERCENT.
1248 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1250 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1253 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1255 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1256 (MIPS16_INSN_BRANCH): Rename to...
1257 (MIPS16_INSN_COND_BRANCH): ... this.
1259 2010-07-03 Alan Modra <amodra@gmail.com>
1261 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1262 Renumber other PPC_OPCODE defines.
1264 2010-07-03 Alan Modra <amodra@gmail.com>
1266 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1268 2010-06-29 Alan Modra <amodra@gmail.com>
1270 * maxq.h: Delete file.
1272 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1274 * ppc.h (PPC_OPCODE_E500): Define.
1276 2010-05-26 Catherine Moore <clm@codesourcery.com>
1278 * opcode/mips.h (INSN_MIPS16): Remove.
1280 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1282 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1284 2010-04-15 Nick Clifton <nickc@redhat.com>
1286 * alpha.h: Update copyright notice to use GPLv3.
1292 * convex.h: Likewise.
1299 * h8300.h: Likewise.
1306 * m68hc11.h: Likewise.
1312 * mn10200.h: Likewise.
1313 * mn10300.h: Likewise.
1314 * msp430.h: Likewise.
1316 * ns32k.h: Likewise.
1318 * pdp11.h: Likewise.
1325 * score-datadep.h: Likewise.
1326 * score-inst.h: Likewise.
1327 * sparc.h: Likewise.
1328 * spu-insns.h: Likewise.
1330 * tic30.h: Likewise.
1331 * tic4x.h: Likewise.
1332 * tic54x.h: Likewise.
1333 * tic80.h: Likewise.
1337 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1339 * tic6x-control-registers.h, tic6x-insn-formats.h,
1340 tic6x-opcode-table.h, tic6x.h: New.
1342 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1344 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1346 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1348 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1350 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1352 * ia64.h (ia64_find_opcode): Remove argument name.
1353 (ia64_find_next_opcode): Likewise.
1354 (ia64_dis_opcode): Likewise.
1355 (ia64_free_opcode): Likewise.
1356 (ia64_find_dependency): Likewise.
1358 2009-11-22 Doug Evans <dje@sebabeach.org>
1360 * cgen.h: Include bfd_stdint.h.
1361 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1363 2009-11-18 Paul Brook <paul@codesourcery.com>
1365 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1367 2009-11-17 Paul Brook <paul@codesourcery.com>
1368 Daniel Jacobowitz <dan@codesourcery.com>
1370 * arm.h (ARM_EXT_V6_DSP): Define.
1371 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1372 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1374 2009-11-04 DJ Delorie <dj@redhat.com>
1376 * rx.h (rx_decode_opcode) (mvtipl): Add.
1377 (mvtcp, mvfcp, opecp): Remove.
1379 2009-11-02 Paul Brook <paul@codesourcery.com>
1381 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1382 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1383 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1384 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1385 FPU_ARCH_NEON_VFP_V4): Define.
1387 2009-10-23 Doug Evans <dje@sebabeach.org>
1389 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1390 * cgen.h: Update. Improve multi-inclusion macro name.
1392 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1394 * ppc.h (PPC_OPCODE_476): Define.
1396 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1398 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1400 2009-09-29 DJ Delorie <dj@redhat.com>
1404 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1406 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1408 2009-09-21 Ben Elliston <bje@au.ibm.com>
1410 * ppc.h (PPC_OPCODE_PPCA2): New.
1412 2009-09-05 Martin Thuresson <martin@mtme.org>
1414 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1416 2009-08-29 Martin Thuresson <martin@mtme.org>
1418 * tic30.h (template): Rename type template to
1419 insn_template. Updated code to use new name.
1420 * tic54x.h (template): Rename type template to
1423 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1425 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1427 2009-06-11 Anthony Green <green@moxielogic.com>
1429 * moxie.h (MOXIE_F3_PCREL): Define.
1430 (moxie_form3_opc_info): Grow.
1432 2009-06-06 Anthony Green <green@moxielogic.com>
1434 * moxie.h (MOXIE_F1_M): Define.
1436 2009-04-15 Anthony Green <green@moxielogic.com>
1440 2009-04-06 DJ Delorie <dj@redhat.com>
1442 * h8300.h: Add relaxation attributes to MOVA opcodes.
1444 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1446 * ppc.h (ppc_parse_cpu): Declare.
1448 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1450 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1451 and _IMM11 for mbitclr and mbitset.
1452 * score-datadep.h: Update dependency information.
1454 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1456 * ppc.h (PPC_OPCODE_POWER7): New.
1458 2009-02-06 Doug Evans <dje@google.com>
1460 * i386.h: Add comment regarding sse* insns and prefixes.
1462 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1464 * mips.h (INSN_XLR): Define.
1465 (INSN_CHIP_MASK): Update.
1467 (OPCODE_IS_MEMBER): Update.
1468 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1470 2009-01-28 Doug Evans <dje@google.com>
1472 * opcode/i386.h: Add multiple inclusion protection.
1473 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1474 (EDI_REG_NUM): New macros.
1475 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1476 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1477 (REX_PREFIX_P): New macro.
1479 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1481 * ppc.h (struct powerpc_opcode): New field "deprecated".
1482 (PPC_OPCODE_NOPOWER4): Delete.
1484 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1486 * mips.h: Define CPU_R14000, CPU_R16000.
1487 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1489 2008-11-18 Catherine Moore <clm@codesourcery.com>
1491 * arm.h (FPU_NEON_FP16): New.
1492 (FPU_ARCH_NEON_FP16): New.
1494 2008-11-06 Chao-ying Fu <fu@mips.com>
1496 * mips.h: Doucument '1' for 5-bit sync type.
1498 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1500 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1503 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1505 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1507 2008-07-30 Michael J. Eager <eager@eagercon.com>
1509 * ppc.h (PPC_OPCODE_405): Define.
1510 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1512 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1514 * ppc.h (ppc_cpu_t): New typedef.
1515 (struct powerpc_opcode <flags>): Use it.
1516 (struct powerpc_operand <insert, extract>): Likewise.
1517 (struct powerpc_macro <flags>): Likewise.
1519 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1521 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1522 Update comment before MIPS16 field descriptors to mention MIPS16.
1523 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1525 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1526 New bit masks and shift counts for cins and exts.
1528 * mips.h: Document new field descriptors +Q.
1529 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1531 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1533 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1534 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1536 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1538 * ppc.h: (PPC_OPCODE_E500MC): New.
1540 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1542 * i386.h (MAX_OPERANDS): Set to 5.
1543 (MAX_MNEM_SIZE): Changed to 20.
1545 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1547 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1549 2008-03-09 Paul Brook <paul@codesourcery.com>
1551 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1553 2008-03-04 Paul Brook <paul@codesourcery.com>
1555 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1556 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1557 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1559 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1560 Nick Clifton <nickc@redhat.com>
1563 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1564 with a 32-bit displacement but without the top bit of the 4th byte
1567 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1569 * cr16.h (cr16_num_optab): Declared.
1571 2008-02-14 Hakan Ardo <hakan@debian.org>
1574 * avr.h (AVR_ISA_2xxe): Define.
1576 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1578 * mips.h: Update copyright.
1579 (INSN_CHIP_MASK): New macro.
1580 (INSN_OCTEON): New macro.
1581 (CPU_OCTEON): New macro.
1582 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1584 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1586 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1588 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1590 * avr.h (AVR_ISA_USB162): Add new opcode set.
1591 (AVR_ISA_AVR3): Likewise.
1593 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1595 * mips.h (INSN_LOONGSON_2E): New.
1596 (INSN_LOONGSON_2F): New.
1597 (CPU_LOONGSON_2E): New.
1598 (CPU_LOONGSON_2F): New.
1599 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1601 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1603 * mips.h (INSN_ISA*): Redefine certain values as an
1604 enumeration. Update comments.
1605 (mips_isa_table): New.
1606 (ISA_MIPS*): Redefine to match enumeration.
1607 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1610 2007-08-08 Ben Elliston <bje@au.ibm.com>
1612 * ppc.h (PPC_OPCODE_PPCPS): New.
1614 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1616 * m68k.h: Document j K & E.
1618 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1620 * cr16.h: New file for CR16 target.
1622 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1624 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1626 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1628 * m68k.h (mcfisa_c): New.
1629 (mcfusp, mcf_mask): Adjust.
1631 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1633 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1634 (num_powerpc_operands): Declare.
1635 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1636 (PPC_OPERAND_PLUS1): Define.
1638 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1640 * i386.h (REX_MODE64): Renamed to ...
1642 (REX_EXTX): Renamed to ...
1644 (REX_EXTY): Renamed to ...
1646 (REX_EXTZ): Renamed to ...
1649 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1651 * i386.h: Add entries from config/tc-i386.h and move tables
1652 to opcodes/i386-opc.h.
1654 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1656 * i386.h (FloatDR): Removed.
1657 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1659 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1661 * spu-insns.h: Add soma double-float insns.
1663 2007-02-20 Thiemo Seufer <ths@mips.com>
1664 Chao-Ying Fu <fu@mips.com>
1666 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1667 (INSN_DSPR2): Add flag for DSP R2 instructions.
1668 (M_BALIGN): New macro.
1670 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1672 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1673 and Seg3ShortFrom with Shortform.
1675 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1678 * i386.h (i386_optab): Put the real "test" before the pseudo
1681 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1683 * m68k.h (m68010up): OR fido_a.
1685 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1687 * m68k.h (fido_a): New.
1689 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1691 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1692 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1695 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1697 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1699 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1701 * score-inst.h (enum score_insn_type): Add Insn_internal.
1703 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1704 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1705 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1706 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1707 Alan Modra <amodra@bigpond.net.au>
1709 * spu-insns.h: New file.
1712 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1714 * ppc.h (PPC_OPCODE_CELL): Define.
1716 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1718 * i386.h : Modify opcode to support for the change in POPCNT opcode
1719 in amdfam10 architecture.
1721 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1723 * i386.h: Replace CpuMNI with CpuSSSE3.
1725 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1726 Joseph Myers <joseph@codesourcery.com>
1727 Ian Lance Taylor <ian@wasabisystems.com>
1728 Ben Elliston <bje@wasabisystems.com>
1730 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1732 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1734 * score-datadep.h: New file.
1735 * score-inst.h: New file.
1737 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1739 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1740 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1741 movdq2q and movq2dq.
1743 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1744 Michael Meissner <michael.meissner@amd.com>
1746 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1748 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1750 * i386.h (i386_optab): Add "nop" with memory reference.
1752 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1754 * i386.h (i386_optab): Update comment for 64bit NOP.
1756 2006-06-06 Ben Elliston <bje@au.ibm.com>
1757 Anton Blanchard <anton@samba.org>
1759 * ppc.h (PPC_OPCODE_POWER6): Define.
1762 2006-06-05 Thiemo Seufer <ths@mips.com>
1764 * mips.h: Improve description of MT flags.
1766 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1768 * m68k.h (mcf_mask): Define.
1770 2006-05-05 Thiemo Seufer <ths@mips.com>
1771 David Ung <davidu@mips.com>
1773 * mips.h (enum): Add macro M_CACHE_AB.
1775 2006-05-04 Thiemo Seufer <ths@mips.com>
1776 Nigel Stephens <nigel@mips.com>
1777 David Ung <davidu@mips.com>
1779 * mips.h: Add INSN_SMARTMIPS define.
1781 2006-04-30 Thiemo Seufer <ths@mips.com>
1782 David Ung <davidu@mips.com>
1784 * mips.h: Defines udi bits and masks. Add description of
1785 characters which may appear in the args field of udi
1788 2006-04-26 Thiemo Seufer <ths@networkno.de>
1790 * mips.h: Improve comments describing the bitfield instruction
1793 2006-04-26 Julian Brown <julian@codesourcery.com>
1795 * arm.h (FPU_VFP_EXT_V3): Define constant.
1796 (FPU_NEON_EXT_V1): Likewise.
1797 (FPU_VFP_HARD): Update.
1798 (FPU_VFP_V3): Define macro.
1799 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1801 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1803 * avr.h (AVR_ISA_PWMx): New.
1805 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1807 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1808 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1809 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1810 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1811 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1813 2006-03-10 Paul Brook <paul@codesourcery.com>
1815 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1817 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1819 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1820 first. Correct mask of bb "B" opcode.
1822 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1824 * i386.h (i386_optab): Support Intel Merom New Instructions.
1826 2006-02-24 Paul Brook <paul@codesourcery.com>
1828 * arm.h: Add V7 feature bits.
1830 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1832 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1834 2006-01-31 Paul Brook <paul@codesourcery.com>
1835 Richard Earnshaw <rearnsha@arm.com>
1837 * arm.h: Use ARM_CPU_FEATURE.
1838 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1839 (arm_feature_set): Change to a structure.
1840 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1841 ARM_FEATURE): New macros.
1843 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1845 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1846 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1847 (ADD_PC_INCR_OPCODE): Don't define.
1849 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1852 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1854 2005-11-14 David Ung <davidu@mips.com>
1856 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1857 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1858 save/restore encoding of the args field.
1860 2005-10-28 Dave Brolley <brolley@redhat.com>
1862 Contribute the following changes:
1863 2005-02-16 Dave Brolley <brolley@redhat.com>
1865 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1866 cgen_isa_mask_* to cgen_bitset_*.
1869 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1871 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1872 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1873 (CGEN_CPU_TABLE): Make isas a ponter.
1875 2003-09-29 Dave Brolley <brolley@redhat.com>
1877 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1878 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1879 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1881 2002-12-13 Dave Brolley <brolley@redhat.com>
1883 * cgen.h (symcat.h): #include it.
1884 (cgen-bitset.h): #include it.
1885 (CGEN_ATTR_VALUE_TYPE): Now a union.
1886 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1887 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1888 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1889 * cgen-bitset.h: New file.
1891 2005-09-30 Catherine Moore <clm@cm00re.com>
1895 2005-10-24 Jan Beulich <jbeulich@novell.com>
1897 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1900 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1902 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1903 Add FLAG_STRICT to pa10 ftest opcode.
1905 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1907 * hppa.h (pa_opcodes): Remove lha entries.
1909 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1911 * hppa.h (FLAG_STRICT): Revise comment.
1912 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1913 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1916 2005-09-30 Catherine Moore <clm@cm00re.com>
1920 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1922 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1924 2005-09-06 Chao-ying Fu <fu@mips.com>
1926 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1927 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1929 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1930 (INSN_ASE_MASK): Update to include INSN_MT.
1931 (INSN_MT): New define for MT ASE.
1933 2005-08-25 Chao-ying Fu <fu@mips.com>
1935 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1936 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1937 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1938 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1939 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1940 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1942 (INSN_DSP): New define for DSP ASE.
1944 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1948 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1950 * ppc.h (PPC_OPCODE_E300): Define.
1952 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1954 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1956 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1959 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1962 2005-07-27 Jan Beulich <jbeulich@novell.com>
1964 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1965 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1966 Add movq-s as 64-bit variants of movd-s.
1968 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1970 * hppa.h: Fix punctuation in comment.
1972 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1973 implicit space-register addressing. Set space-register bits on opcodes
1974 using implicit space-register addressing. Add various missing pa20
1975 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1976 space-register addressing. Use "fE" instead of "fe" in various
1979 2005-07-18 Jan Beulich <jbeulich@novell.com>
1981 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1983 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1985 * i386.h (i386_optab): Support Intel VMX Instructions.
1987 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1989 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1991 2005-07-05 Jan Beulich <jbeulich@novell.com>
1993 * i386.h (i386_optab): Add new insns.
1995 2005-07-01 Nick Clifton <nickc@redhat.com>
1997 * sparc.h: Add typedefs to structure declarations.
1999 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2002 * i386.h (i386_optab): Update comments for 64bit addressing on
2003 mov. Allow 64bit addressing for mov and movq.
2005 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2007 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2008 respectively, in various floating-point load and store patterns.
2010 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2012 * hppa.h (FLAG_STRICT): Correct comment.
2013 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2014 PA 2.0 mneumonics when equivalent. Entries with cache control
2015 completers now require PA 1.1. Adjust whitespace.
2017 2005-05-19 Anton Blanchard <anton@samba.org>
2019 * ppc.h (PPC_OPCODE_POWER5): Define.
2021 2005-05-10 Nick Clifton <nickc@redhat.com>
2023 * Update the address and phone number of the FSF organization in
2024 the GPL notices in the following files:
2025 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2026 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2027 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2028 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2029 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2030 tic54x.h, tic80.h, v850.h, vax.h
2032 2005-05-09 Jan Beulich <jbeulich@novell.com>
2034 * i386.h (i386_optab): Add ht and hnt.
2036 2005-04-18 Mark Kettenis <kettenis@gnu.org>
2038 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2039 Add xcrypt-ctr. Provide aliases without hyphens.
2041 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2043 Moved from ../ChangeLog
2045 2005-04-12 Paul Brook <paul@codesourcery.com>
2046 * m88k.h: Rename psr macros to avoid conflicts.
2048 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2049 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2050 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2051 and ARM_ARCH_V6ZKT2.
2053 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2054 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2055 Remove redundant instruction types.
2056 (struct argument): X_op - new field.
2057 (struct cst4_entry): Remove.
2058 (no_op_insn): Declare.
2060 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2061 * crx.h (enum argtype): Rename types, remove unused types.
2063 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2064 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2065 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2066 (enum operand_type): Rearrange operands, edit comments.
2067 replace us<N> with ui<N> for unsigned immediate.
2068 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2069 displacements (respectively).
2070 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2071 (instruction type): Add NO_TYPE_INS.
2072 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2073 (operand_entry): New field - 'flags'.
2074 (operand flags): New.
2076 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2077 * crx.h (operand_type): Remove redundant types i3, i4,
2079 Add new unsigned immediate types us3, us4, us5, us16.
2081 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2083 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2084 adjust them accordingly.
2086 2005-04-01 Jan Beulich <jbeulich@novell.com>
2088 * i386.h (i386_optab): Add rdtscp.
2090 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2092 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2093 between memory and segment register. Allow movq for moving between
2094 general-purpose register and segment register.
2096 2005-02-09 Jan Beulich <jbeulich@novell.com>
2099 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2100 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2103 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2105 * m68k.h (m68008, m68ec030, m68882): Remove.
2107 (cpu_m68k, cpu_cf): New.
2108 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2109 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2111 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2113 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2114 * cgen.h (enum cgen_parse_operand_type): Add
2115 CGEN_PARSE_OPERAND_SYMBOLIC.
2117 2005-01-21 Fred Fish <fnf@specifixinc.com>
2119 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2120 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2121 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2123 2005-01-19 Fred Fish <fnf@specifixinc.com>
2125 * mips.h (struct mips_opcode): Add new pinfo2 member.
2126 (INSN_ALIAS): New define for opcode table entries that are
2127 specific instances of another entry, such as 'move' for an 'or'
2128 with a zero operand.
2129 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2130 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2132 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2134 * mips.h (CPU_RM9000): Define.
2135 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2137 2004-11-25 Jan Beulich <jbeulich@novell.com>
2139 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2140 to/from test registers are illegal in 64-bit mode. Add missing
2141 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2142 (previously one had to explicitly encode a rex64 prefix). Re-enable
2143 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2144 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2146 2004-11-23 Jan Beulich <jbeulich@novell.com>
2148 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2149 available only with SSE2. Change the MMX additions introduced by SSE
2150 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2151 instructions by their now designated identifier (since combining i686
2152 and 3DNow! does not really imply 3DNow!A).
2154 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2156 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2157 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2159 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2160 Vineet Sharma <vineets@noida.hcltech.com>
2162 * maxq.h: New file: Disassembly information for the maxq port.
2164 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2166 * i386.h (i386_optab): Put back "movzb".
2168 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2170 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2171 comments. Remove member cris_ver_sim. Add members
2172 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2173 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2174 (struct cris_support_reg, struct cris_cond15): New types.
2175 (cris_conds15): Declare.
2176 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2177 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2178 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2179 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2180 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2181 SIZE_FIELD_UNSIGNED.
2183 2004-11-04 Jan Beulich <jbeulich@novell.com>
2185 * i386.h (sldx_Suf): Remove.
2186 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2187 (q_FP): Define, implying no REX64.
2188 (x_FP, sl_FP): Imply FloatMF.
2189 (i386_optab): Split reg and mem forms of moving from segment registers
2190 so that the memory forms can ignore the 16-/32-bit operand size
2191 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2192 all non-floating-point instructions. Unite 32- and 64-bit forms of
2193 movsx, movzx, and movd. Adjust floating point operations for the above
2194 changes to the *FP macros. Add DefaultSize to floating point control
2195 insns operating on larger memory ranges. Remove left over comments
2196 hinting at certain insns being Intel-syntax ones where the ones
2197 actually meant are already gone.
2199 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2201 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2204 2004-09-30 Paul Brook <paul@codesourcery.com>
2206 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2207 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2209 2004-09-11 Theodore A. Roth <troth@openavr.org>
2211 * avr.h: Add support for
2212 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2214 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2216 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2218 2004-08-24 Dmitry Diky <diwil@spec.ru>
2220 * msp430.h (msp430_opc): Add new instructions.
2221 (msp430_rcodes): Declare new instructions.
2222 (msp430_hcodes): Likewise..
2224 2004-08-13 Nick Clifton <nickc@redhat.com>
2227 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2230 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2232 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2234 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2236 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2238 2004-07-21 Jan Beulich <jbeulich@novell.com>
2240 * i386.h: Adjust instruction descriptions to better match the
2243 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2245 * arm.h: Remove all old content. Replace with architecture defines
2246 from gas/config/tc-arm.c.
2248 2004-07-09 Andreas Schwab <schwab@suse.de>
2250 * m68k.h: Fix comment.
2252 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2256 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2258 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2260 2004-05-24 Peter Barada <peter@the-baradas.com>
2262 * m68k.h: Add 'size' to m68k_opcode.
2264 2004-05-05 Peter Barada <peter@the-baradas.com>
2266 * m68k.h: Switch from ColdFire chip name to core variant.
2268 2004-04-22 Peter Barada <peter@the-baradas.com>
2270 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2271 descriptions for new EMAC cases.
2272 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2273 handle Motorola MAC syntax.
2274 Allow disassembly of ColdFire V4e object files.
2276 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2278 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2280 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2282 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2284 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2286 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2288 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2290 * i386.h (i386_optab): Added xstore/xcrypt insns.
2292 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2294 * h8300.h (32bit ldc/stc): Add relaxing support.
2296 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2298 * h8300.h (BITOP): Pass MEMRELAX flag.
2300 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2302 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2305 For older changes see ChangeLog-9103
2307 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2309 Copying and distribution of this file, with or without modification,
2310 are permitted in any medium without royalty provided the copyright
2311 notice and this notice are preserved.
2317 version-control: never
projects / external / binutils.git / blob