1 2015-01-01 Alan Modra <amodra@gmail.com>
3 Update year range in copyright notice of all files.
5 2014-12-27 Anthony Green <green@moxielogic.com>
7 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
8 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
10 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
14 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
16 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
17 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
18 (NIOS2_INSN_OPTARG): Renumber.
20 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
22 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
23 declaration. Fix obsolete comment.
25 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
27 * nios2.h (enum iw_format_type): New.
28 (struct nios2_opcode): Update comments. Add size and format fields.
29 (NIOS2_INSN_OPTARG): New.
30 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
31 (struct nios2_reg): Add regtype field.
32 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
33 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
34 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
35 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
36 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
37 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
38 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
39 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
40 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
41 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
42 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
43 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
44 (OP_MASK_OP, OP_SH_OP): Delete.
45 (OP_MASK_IOP, OP_SH_IOP): Delete.
46 (OP_MASK_IRD, OP_SH_IRD): Delete.
47 (OP_MASK_IRT, OP_SH_IRT): Delete.
48 (OP_MASK_IRS, OP_SH_IRS): Delete.
49 (OP_MASK_ROP, OP_SH_ROP): Delete.
50 (OP_MASK_RRD, OP_SH_RRD): Delete.
51 (OP_MASK_RRT, OP_SH_RRT): Delete.
52 (OP_MASK_RRS, OP_SH_RRS): Delete.
53 (OP_MASK_JOP, OP_SH_JOP): Delete.
54 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
55 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
56 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
57 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
58 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
59 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
60 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
61 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
62 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
63 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
64 (OP_MASK_<insn>, OP_MASK): Delete.
65 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
66 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
67 Include nios2r1.h to define new instruction opcode constants
69 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
70 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
71 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
72 (NUMOPCODES, NUMREGISTERS): Delete.
73 * nios2r1.h: New file.
75 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
77 * sparc.h (HWCAP2_VIS3B): Documentation improved.
79 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
81 * sparc.h (sparc_opcode): new field `hwcaps2'.
82 (HWCAP2_FJATHPLUS): New define.
83 (HWCAP2_VIS3B): Likewise.
84 (HWCAP2_ADP): Likewise.
85 (HWCAP2_SPARC5): Likewise.
86 (HWCAP2_MWAIT): Likewise.
87 (HWCAP2_XMPMUL): Likewise.
88 (HWCAP2_XMONT): Likewise.
89 (HWCAP2_NSEC): Likewise.
90 (HWCAP2_FJATHHPC): Likewise.
91 (HWCAP2_FJDES): Likewise.
92 (HWCAP2_FJAES): Likewise.
93 Document the new operand kind `{', corresponding to the mcdper
94 ancillary state register.
95 Document the new operand kind }, which represents frsd floating
96 point registers (double precision) which must be the same than
97 frs1 in its containing instruction.
99 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
101 * nds32.h: Add new opcode declaration.
103 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
104 Matthew Fortune <matthew.fortune@imgtec.com>
106 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
107 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
108 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
109 +I, +O, +R, +:, +\, +", +;
110 (mips_check_prev_operand): New struct.
111 (INSN2_FORBIDDEN_SLOT): New define.
112 (INSN_ISA32R6): New define.
113 (INSN_ISA64R6): New define.
114 (INSN_UPTO32R6): New define.
115 (INSN_UPTO64R6): New define.
116 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
117 (ISA_MIPS32R6): New define.
118 (ISA_MIPS64R6): New define.
119 (CPU_MIPS32R6): New define.
120 (CPU_MIPS64R6): New define.
121 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
123 2014-09-03 Jiong Wang <jiong.wang@arm.com>
125 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
126 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
127 (aarch64_insn_class): Add lse_atomic.
128 (F_LSE_SZ): New field added.
129 (opcode_has_special_coder): Recognize F_LSE_SZ.
131 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
133 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
136 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
138 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
139 (INSN_LOAD_COPROC): New define.
140 (INSN_COPROC_MOVE_DELAY): Rename to...
141 (INSN_COPROC_MOVE): New define.
143 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
144 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
145 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
146 Soundararajan <Sounderarajan.D@atmel.com>
148 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
149 (AVR_ISA_2xxxa): Define ISA without LPM.
150 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
151 Add doc for contraint used in 16 bit lds/sts.
152 Adjust ISA group for icall, ijmp, pop and push.
153 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
155 2014-05-19 Nick Clifton <nickc@redhat.com>
157 * msp430.h (struct msp430_operand_s): Add vshift field.
159 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
161 * mips.h (INSN_ISA_MASK): Updated.
162 (INSN_ISA32R3): New define.
163 (INSN_ISA32R5): New define.
164 (INSN_ISA64R3): New define.
165 (INSN_ISA64R5): New define.
166 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
167 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
168 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
170 (INSN_UPTO32R3): New define.
171 (INSN_UPTO32R5): New define.
172 (INSN_UPTO64R3): New define.
173 (INSN_UPTO64R5): New define.
174 (ISA_MIPS32R3): New define.
175 (ISA_MIPS32R5): New define.
176 (ISA_MIPS64R3): New define.
177 (ISA_MIPS64R5): New define.
178 (CPU_MIPS32R3): New define.
179 (CPU_MIPS32R5): New define.
180 (CPU_MIPS64R3): New define.
181 (CPU_MIPS64R5): New define.
183 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
185 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
187 2014-04-22 Christian Svensson <blue@cmd.nu>
191 2014-03-05 Alan Modra <amodra@gmail.com>
193 Update copyright years.
195 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
197 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
200 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
201 Wei-Cheng Wang <cole945@gmail.com>
203 * nds32.h: New file for Andes NDS32.
205 2013-12-07 Mike Frysinger <vapier@gentoo.org>
207 * bfin.h: Remove +x file mode.
209 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
211 * aarch64.h (aarch64_pstatefields): Change element type to
214 2013-11-18 Renlin Li <Renlin.Li@arm.com>
216 * arm.h (ARM_AEXT_V7VE): New define.
217 (ARM_ARCH_V7VE): New define.
218 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
220 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
224 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
226 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
227 (aarch64_sys_reg_writeonly_p): Ditto.
229 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
231 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
232 (aarch64_sys_reg_writeonly_p): Ditto.
234 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
236 * aarch64.h (aarch64_sys_reg): New typedef.
237 (aarch64_sys_regs): Change to define with the new type.
238 (aarch64_sys_reg_deprecated_p): Declare.
240 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
242 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
243 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
245 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
247 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
248 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
249 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
250 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
251 For MIPS, update extension character sequences after +.
252 (ASE_MSA): New define.
253 (ASE_MSA64): New define.
254 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
255 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
256 For microMIPS, update extension character sequences after +.
258 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
263 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
265 * mips.h: Remove references to "+I" and imm2_expr.
267 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
269 * mips.h (M_DEXT, M_DINS): Delete.
271 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
273 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
274 (mips_optional_operand_p): New function.
276 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
277 Richard Sandiford <rdsandiford@googlemail.com>
279 * mips.h: Document new VU0 operand characters.
280 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
281 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
282 (OP_REG_R5900_ACC): New mips_reg_operand_types.
283 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
284 (mips_vu0_channel_mask): Declare.
286 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
288 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
289 (mips_int_operand_min, mips_int_operand_max): New functions.
290 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
292 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
294 * mips.h (mips_decode_reg_operand): New function.
295 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
296 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
297 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
299 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
300 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
301 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
302 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
303 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
304 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
305 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
306 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
307 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
308 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
309 macros to cover the gaps.
310 (INSN2_MOD_SP): Replace with...
311 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
312 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
313 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
314 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
315 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
318 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
320 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
321 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
322 (MIPS16_INSN_COND_BRANCH): Delete.
324 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
325 Kirill Yukhin <kirill.yukhin@intel.com>
326 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
328 * i386.h (BND_PREFIX_OPCODE): New.
330 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
332 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
333 OP_SAVE_RESTORE_LIST.
334 (decode_mips16_operand): Declare.
336 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
338 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
339 (mips_operand, mips_int_operand, mips_mapped_int_operand)
340 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
341 (mips_pcrel_operand): New structures.
342 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
343 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
344 (decode_mips_operand, decode_micromips_operand): Declare.
346 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
348 * mips.h: Document MIPS16 "I" opcode.
350 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
352 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
353 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
354 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
355 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
356 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
357 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
358 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
359 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
360 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
361 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
362 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
363 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
364 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
366 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
367 (M_USD_AB): ...these.
369 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
371 * mips.h: Remove documentation of "[" and "]". Update documentation
372 of "k" and the MDMX formats.
374 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
376 * mips.h: Update documentation of "+s" and "+S".
378 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
380 * mips.h: Document "+i".
382 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
384 * mips.h: Remove "mi" documentation. Update "mh" documentation.
385 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
387 (INSN2_WRITE_GPR_MHI): Rename to...
388 (INSN2_WRITE_GPR_MH): ...this.
390 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
392 * mips.h: Remove documentation of "+D" and "+T".
394 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
396 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
397 Use "source" rather than "destination" for microMIPS "G".
399 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
401 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
404 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
406 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
408 2013-06-17 Catherine Moore <clm@codesourcery.com>
409 Maciej W. Rozycki <macro@codesourcery.com>
410 Chao-Ying Fu <fu@mips.com>
412 * mips.h (OP_SH_EVAOFFSET): Define.
413 (OP_MASK_EVAOFFSET): Define.
414 (INSN_ASE_MASK): Delete.
416 (M_CACHEE_AB, M_CACHEE_OB): New.
417 (M_LBE_OB, M_LBE_AB): New.
418 (M_LBUE_OB, M_LBUE_AB): New.
419 (M_LHE_OB, M_LHE_AB): New.
420 (M_LHUE_OB, M_LHUE_AB): New.
421 (M_LLE_AB, M_LLE_OB): New.
422 (M_LWE_OB, M_LWE_AB): New.
423 (M_LWLE_AB, M_LWLE_OB): New.
424 (M_LWRE_AB, M_LWRE_OB): New.
425 (M_PREFE_AB, M_PREFE_OB): New.
426 (M_SCE_AB, M_SCE_OB): New.
427 (M_SBE_OB, M_SBE_AB): New.
428 (M_SHE_OB, M_SHE_AB): New.
429 (M_SWE_OB, M_SWE_AB): New.
430 (M_SWLE_AB, M_SWLE_OB): New.
431 (M_SWRE_AB, M_SWRE_OB): New.
432 (MICROMIPSOP_SH_EVAOFFSET): Define.
433 (MICROMIPSOP_MASK_EVAOFFSET): Define.
435 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
437 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
439 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
441 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
443 2013-05-09 Andrew Pinski <apinski@cavium.com>
445 * mips.h (OP_MASK_CODE10): Correct definition.
446 (OP_SH_CODE10): Likewise.
447 Add a comment that "+J" is used now for OP_*CODE10.
448 (INSN_ASE_MASK): Update.
449 (INSN_VIRT): New macro.
450 (INSN_VIRT64): New macro
452 2013-05-02 Nick Clifton <nickc@redhat.com>
454 * msp430.h: Add patterns for MSP430X instructions.
456 2013-04-06 David S. Miller <davem@davemloft.net>
458 * sparc.h (F_PREFERRED): Define.
459 (F_PREF_ALIAS): Define.
461 2013-04-03 Nick Clifton <nickc@redhat.com>
463 * v850.h (V850_INVERSE_PCREL): Define.
465 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
468 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
470 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
473 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
475 * tic6xc-opcode-table.h: Add 16-bit insns.
476 * tic6x.h: Add support for 16-bit insns.
478 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
480 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
481 and mov.b/w/l Rs,@(d:32,ERd).
483 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
486 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
487 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
488 tic6x_operand_xregpair operand coding type.
489 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
490 opcode field, usu ORXREGD1324 for the src2 operand and remove the
493 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
496 * tic6x.h (enum tic6x_coding_method): Add
497 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
498 separately the msb and lsb of a register pair. This is needed to
499 encode the opcodes in the same way as TI assembler does.
500 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
501 and rsqrdp opcodes to use the new field coding types.
503 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
505 * arm.h (CRC_EXT_ARMV8): New constant.
506 (ARCH_CRC_ARMV8): New macro.
508 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
510 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
512 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
513 Andrew Jenner <andrew@codesourcery.com>
515 Based on patches from Altera Corporation.
519 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
521 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
523 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
526 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
528 2013-01-24 Nick Clifton <nickc@redhat.com>
530 * v850.h: Add e3v5 support.
532 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
534 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
536 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
538 * ppc.h (PPC_OPCODE_POWER8): New define.
539 (PPC_OPCODE_HTM): Likewise.
541 2013-01-10 Will Newton <will.newton@imgtec.com>
545 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
547 * cr16.h (make_instruction): Rename to cr16_make_instruction.
548 (match_opcode): Rename to cr16_match_opcode.
550 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
552 * mips.h: Add support for r5900 instructions including lq and sq.
554 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
556 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
557 (make_instruction,match_opcode): Added function prototypes.
558 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
560 2012-11-23 Alan Modra <amodra@gmail.com>
562 * ppc.h (ppc_parse_cpu): Update prototype.
564 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
566 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
567 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
569 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
571 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
573 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
575 * ia64.h (ia64_opnd): Add new operand types.
577 2012-08-21 David S. Miller <davem@davemloft.net>
579 * sparc.h (F3F4): New macro.
581 2012-08-13 Ian Bolton <ian.bolton@arm.com>
582 Laurent Desnogues <laurent.desnogues@arm.com>
583 Jim MacArthur <jim.macarthur@arm.com>
584 Marcus Shawcroft <marcus.shawcroft@arm.com>
585 Nigel Stephens <nigel.stephens@arm.com>
586 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
587 Richard Earnshaw <rearnsha@arm.com>
588 Sofiane Naci <sofiane.naci@arm.com>
589 Tejas Belagod <tejas.belagod@arm.com>
590 Yufeng Zhang <yufeng.zhang@arm.com>
592 * aarch64.h: New file.
594 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
595 Maciej W. Rozycki <macro@codesourcery.com>
597 * mips.h (mips_opcode): Add the exclusions field.
598 (OPCODE_IS_MEMBER): Remove macro.
599 (cpu_is_member): New inline function.
600 (opcode_is_member): Likewise.
602 2012-07-31 Chao-Ying Fu <fu@mips.com>
603 Catherine Moore <clm@codesourcery.com>
604 Maciej W. Rozycki <macro@codesourcery.com>
606 * mips.h: Document microMIPS DSP ASE usage.
607 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
608 microMIPS DSP ASE support.
609 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
610 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
611 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
612 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
613 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
614 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
615 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
617 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
619 * mips.h: Fix a typo in description.
621 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
623 * avr.h: (AVR_ISA_XCH): New define.
624 (AVR_ISA_XMEGA): Use it.
625 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
627 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
629 * m68hc11.h: Add XGate definitions.
630 (struct m68hc11_opcode): Add xg_mask field.
632 2012-05-14 Catherine Moore <clm@codesourcery.com>
633 Maciej W. Rozycki <macro@codesourcery.com>
634 Rhonda Wittels <rhonda@codesourcery.com>
636 * ppc.h (PPC_OPCODE_VLE): New definition.
637 (PPC_OP_SA): New macro.
638 (PPC_OP_SE_VLE): New macro.
639 (PPC_OP): Use a variable shift amount.
640 (powerpc_operand): Update comments.
641 (PPC_OPSHIFT_INV): New macro.
642 (PPC_OPERAND_CR): Replace with...
643 (PPC_OPERAND_CR_BIT): ...this and
644 (PPC_OPERAND_CR_REG): ...this.
647 2012-05-03 Sean Keys <skeys@ipdatasys.com>
649 * xgate.h: Header file for XGATE assembler.
651 2012-04-27 David S. Miller <davem@davemloft.net>
653 * sparc.h: Document new arg code' )' for crypto RS3
656 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
657 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
658 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
659 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
660 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
661 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
662 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
663 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
664 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
665 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
666 HWCAP_CBCOND, HWCAP_CRC32): New defines.
668 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
670 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
672 2012-02-27 Alan Modra <amodra@gmail.com>
674 * crx.h (cst4_map): Update declaration.
676 2012-02-25 Walter Lee <walt@tilera.com>
678 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
680 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
681 TILEPRO_OPC_LW_TLS_SN.
683 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
685 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
686 (XRELEASE_PREFIX_OPCODE): Likewise.
688 2011-12-08 Andrew Pinski <apinski@cavium.com>
689 Adam Nemet <anemet@caviumnetworks.com>
691 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
692 (INSN_OCTEON2): New macro.
693 (CPU_OCTEON2): New macro.
694 (OPCODE_IS_MEMBER): Add Octeon2.
696 2011-11-29 Andrew Pinski <apinski@cavium.com>
698 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
699 (INSN_OCTEONP): New macro.
700 (CPU_OCTEONP): New macro.
701 (OPCODE_IS_MEMBER): Add Octeon+.
702 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
704 2011-11-01 DJ Delorie <dj@redhat.com>
708 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
710 * mips.h: Fix a typo in description.
712 2011-09-21 David S. Miller <davem@davemloft.net>
714 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
715 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
716 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
717 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
719 2011-08-09 Chao-ying Fu <fu@mips.com>
720 Maciej W. Rozycki <macro@codesourcery.com>
722 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
723 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
724 (INSN_ASE_MASK): Add the MCU bit.
725 (INSN_MCU): New macro.
726 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
727 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
729 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
731 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
732 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
733 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
734 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
735 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
736 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
737 (INSN2_READ_GPR_MMN): Likewise.
738 (INSN2_READ_FPR_D): Change the bit used.
739 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
740 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
741 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
742 (INSN2_COND_BRANCH): Likewise.
743 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
744 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
745 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
746 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
747 (INSN2_MOD_GPR_MN): Likewise.
749 2011-08-05 David S. Miller <davem@davemloft.net>
751 * sparc.h: Document new format codes '4', '5', and '('.
752 (OPF_LOW4, RS3): New macros.
754 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
756 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
757 order of flags documented.
759 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
761 * mips.h: Clarify the description of microMIPS instruction
763 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
765 2011-07-24 Chao-ying Fu <fu@mips.com>
766 Maciej W. Rozycki <macro@codesourcery.com>
768 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
769 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
770 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
771 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
772 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
773 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
774 (OP_MASK_RS3, OP_SH_RS3): Likewise.
775 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
776 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
777 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
778 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
779 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
780 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
781 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
782 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
783 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
784 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
785 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
786 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
787 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
788 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
789 (INSN_WRITE_GPR_S): New macro.
790 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
791 (INSN2_READ_FPR_D): Likewise.
792 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
793 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
794 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
795 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
796 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
797 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
798 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
799 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
800 (CPU_MICROMIPS): New macro.
801 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
802 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
803 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
804 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
805 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
806 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
807 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
808 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
809 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
810 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
811 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
812 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
813 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
814 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
815 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
816 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
817 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
818 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
819 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
820 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
821 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
822 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
823 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
824 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
825 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
826 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
827 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
828 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
829 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
830 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
831 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
832 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
833 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
834 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
835 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
836 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
837 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
838 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
839 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
840 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
841 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
842 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
843 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
844 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
845 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
846 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
847 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
848 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
849 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
850 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
851 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
852 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
853 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
854 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
855 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
856 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
857 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
858 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
859 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
860 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
861 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
862 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
863 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
864 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
865 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
866 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
867 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
868 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
869 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
870 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
871 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
872 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
873 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
874 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
875 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
876 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
877 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
878 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
879 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
880 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
881 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
882 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
883 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
884 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
885 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
886 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
887 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
888 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
889 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
890 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
891 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
892 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
893 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
894 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
895 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
896 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
897 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
898 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
899 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
900 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
901 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
902 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
903 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
904 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
905 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
906 (micromips_opcodes): New declaration.
907 (bfd_micromips_num_opcodes): Likewise.
909 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
911 * mips.h (INSN_TRAP): Rename to...
912 (INSN_NO_DELAY_SLOT): ... this.
913 (INSN_SYNC): Remove macro.
915 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
917 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
918 a duplicate of AVR_ISA_SPM.
920 2011-07-01 Nick Clifton <nickc@redhat.com>
922 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
924 2011-06-18 Robin Getz <robin.getz@analog.com>
926 * bfin.h (is_macmod_signed): New func
928 2011-06-18 Mike Frysinger <vapier@gentoo.org>
930 * bfin.h (is_macmod_pmove): Add missing space before func args.
931 (is_macmod_hmove): Likewise.
933 2011-06-13 Walter Lee <walt@tilera.com>
935 * tilegx.h: New file.
936 * tilepro.h: New file.
938 2011-05-31 Paul Brook <paul@codesourcery.com>
940 * arm.h (ARM_ARCH_V7R_IDIV): Define.
942 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
944 * s390.h: Replace S390_OPERAND_REG_EVEN with
945 S390_OPERAND_REG_PAIR.
947 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
949 * s390.h: Add S390_OPCODE_REG_EVEN flag.
951 2011-04-18 Julian Brown <julian@codesourcery.com>
953 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
955 2011-04-11 Dan McDonald <dan@wellkeeper.com>
958 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
960 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
962 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
963 New instruction set flags.
964 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
966 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
968 * mips.h (M_PREF_AB): New enum value.
970 2011-02-12 Mike Frysinger <vapier@gentoo.org>
972 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
974 (is_macmod_pmove, is_macmod_hmove): New functions.
976 2011-02-11 Mike Frysinger <vapier@gentoo.org>
978 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
980 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
982 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
983 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
985 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
988 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
991 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
994 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
996 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
998 * mips.h: Update commentary after last commit.
1000 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1002 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1003 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1004 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1006 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1008 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1010 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1012 * mips.h: Fix previous commit.
1014 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1016 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1017 (INSN_LOONGSON_3A): Clear bit 31.
1019 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1022 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1023 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1024 (ARM_ARCH_V6M_ONLY): New define.
1026 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1028 * mips.h (INSN_LOONGSON_3A): Defined.
1029 (CPU_LOONGSON_3A): Defined.
1030 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1032 2010-10-09 Matt Rice <ratmice@gmail.com>
1034 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1035 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1037 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1039 * arm.h (ARM_EXT_VIRT): New define.
1040 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1041 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1044 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1046 * arm.h (ARM_AEXT_ADIV): New define.
1047 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1049 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1051 * arm.h (ARM_EXT_OS): New define.
1052 (ARM_AEXT_V6SM): Likewise.
1053 (ARM_ARCH_V6SM): Likewise.
1055 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1057 * arm.h (ARM_EXT_MP): Add.
1058 (ARM_ARCH_V7A_MP): Likewise.
1060 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1062 * bfin.h: Declare pseudoChr structs/defines.
1064 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1066 * bfin.h: Strip trailing whitespace.
1068 2010-07-29 DJ Delorie <dj@redhat.com>
1070 * rx.h (RX_Operand_Type): Add TwoReg.
1071 (RX_Opcode_ID): Remove ediv and ediv2.
1073 2010-07-27 DJ Delorie <dj@redhat.com>
1075 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1077 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1078 Ina Pandit <ina.pandit@kpitcummins.com>
1080 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1081 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1082 PROCESSOR_V850E2_ALL.
1083 Remove PROCESSOR_V850EA support.
1084 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1085 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1086 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1087 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1088 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1089 V850_OPERAND_PERCENT.
1090 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1092 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1095 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1097 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1098 (MIPS16_INSN_BRANCH): Rename to...
1099 (MIPS16_INSN_COND_BRANCH): ... this.
1101 2010-07-03 Alan Modra <amodra@gmail.com>
1103 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1104 Renumber other PPC_OPCODE defines.
1106 2010-07-03 Alan Modra <amodra@gmail.com>
1108 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1110 2010-06-29 Alan Modra <amodra@gmail.com>
1112 * maxq.h: Delete file.
1114 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1116 * ppc.h (PPC_OPCODE_E500): Define.
1118 2010-05-26 Catherine Moore <clm@codesourcery.com>
1120 * opcode/mips.h (INSN_MIPS16): Remove.
1122 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1124 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1126 2010-04-15 Nick Clifton <nickc@redhat.com>
1128 * alpha.h: Update copyright notice to use GPLv3.
1134 * convex.h: Likewise.
1141 * h8300.h: Likewise.
1148 * m68hc11.h: Likewise.
1154 * mn10200.h: Likewise.
1155 * mn10300.h: Likewise.
1156 * msp430.h: Likewise.
1158 * ns32k.h: Likewise.
1160 * pdp11.h: Likewise.
1167 * score-datadep.h: Likewise.
1168 * score-inst.h: Likewise.
1169 * sparc.h: Likewise.
1170 * spu-insns.h: Likewise.
1172 * tic30.h: Likewise.
1173 * tic4x.h: Likewise.
1174 * tic54x.h: Likewise.
1175 * tic80.h: Likewise.
1179 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1181 * tic6x-control-registers.h, tic6x-insn-formats.h,
1182 tic6x-opcode-table.h, tic6x.h: New.
1184 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1186 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1188 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1190 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1192 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1194 * ia64.h (ia64_find_opcode): Remove argument name.
1195 (ia64_find_next_opcode): Likewise.
1196 (ia64_dis_opcode): Likewise.
1197 (ia64_free_opcode): Likewise.
1198 (ia64_find_dependency): Likewise.
1200 2009-11-22 Doug Evans <dje@sebabeach.org>
1202 * cgen.h: Include bfd_stdint.h.
1203 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1205 2009-11-18 Paul Brook <paul@codesourcery.com>
1207 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1209 2009-11-17 Paul Brook <paul@codesourcery.com>
1210 Daniel Jacobowitz <dan@codesourcery.com>
1212 * arm.h (ARM_EXT_V6_DSP): Define.
1213 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1214 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1216 2009-11-04 DJ Delorie <dj@redhat.com>
1218 * rx.h (rx_decode_opcode) (mvtipl): Add.
1219 (mvtcp, mvfcp, opecp): Remove.
1221 2009-11-02 Paul Brook <paul@codesourcery.com>
1223 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1224 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1225 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1226 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1227 FPU_ARCH_NEON_VFP_V4): Define.
1229 2009-10-23 Doug Evans <dje@sebabeach.org>
1231 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1232 * cgen.h: Update. Improve multi-inclusion macro name.
1234 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1236 * ppc.h (PPC_OPCODE_476): Define.
1238 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1240 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1242 2009-09-29 DJ Delorie <dj@redhat.com>
1246 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1248 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1250 2009-09-21 Ben Elliston <bje@au.ibm.com>
1252 * ppc.h (PPC_OPCODE_PPCA2): New.
1254 2009-09-05 Martin Thuresson <martin@mtme.org>
1256 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1258 2009-08-29 Martin Thuresson <martin@mtme.org>
1260 * tic30.h (template): Rename type template to
1261 insn_template. Updated code to use new name.
1262 * tic54x.h (template): Rename type template to
1265 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1267 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1269 2009-06-11 Anthony Green <green@moxielogic.com>
1271 * moxie.h (MOXIE_F3_PCREL): Define.
1272 (moxie_form3_opc_info): Grow.
1274 2009-06-06 Anthony Green <green@moxielogic.com>
1276 * moxie.h (MOXIE_F1_M): Define.
1278 2009-04-15 Anthony Green <green@moxielogic.com>
1282 2009-04-06 DJ Delorie <dj@redhat.com>
1284 * h8300.h: Add relaxation attributes to MOVA opcodes.
1286 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1288 * ppc.h (ppc_parse_cpu): Declare.
1290 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1292 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1293 and _IMM11 for mbitclr and mbitset.
1294 * score-datadep.h: Update dependency information.
1296 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1298 * ppc.h (PPC_OPCODE_POWER7): New.
1300 2009-02-06 Doug Evans <dje@google.com>
1302 * i386.h: Add comment regarding sse* insns and prefixes.
1304 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1306 * mips.h (INSN_XLR): Define.
1307 (INSN_CHIP_MASK): Update.
1309 (OPCODE_IS_MEMBER): Update.
1310 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1312 2009-01-28 Doug Evans <dje@google.com>
1314 * opcode/i386.h: Add multiple inclusion protection.
1315 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1316 (EDI_REG_NUM): New macros.
1317 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1318 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1319 (REX_PREFIX_P): New macro.
1321 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1323 * ppc.h (struct powerpc_opcode): New field "deprecated".
1324 (PPC_OPCODE_NOPOWER4): Delete.
1326 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1328 * mips.h: Define CPU_R14000, CPU_R16000.
1329 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1331 2008-11-18 Catherine Moore <clm@codesourcery.com>
1333 * arm.h (FPU_NEON_FP16): New.
1334 (FPU_ARCH_NEON_FP16): New.
1336 2008-11-06 Chao-ying Fu <fu@mips.com>
1338 * mips.h: Doucument '1' for 5-bit sync type.
1340 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1342 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1345 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1347 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1349 2008-07-30 Michael J. Eager <eager@eagercon.com>
1351 * ppc.h (PPC_OPCODE_405): Define.
1352 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1354 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1356 * ppc.h (ppc_cpu_t): New typedef.
1357 (struct powerpc_opcode <flags>): Use it.
1358 (struct powerpc_operand <insert, extract>): Likewise.
1359 (struct powerpc_macro <flags>): Likewise.
1361 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1363 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1364 Update comment before MIPS16 field descriptors to mention MIPS16.
1365 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1367 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1368 New bit masks and shift counts for cins and exts.
1370 * mips.h: Document new field descriptors +Q.
1371 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1373 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1375 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1376 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1378 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1380 * ppc.h: (PPC_OPCODE_E500MC): New.
1382 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1384 * i386.h (MAX_OPERANDS): Set to 5.
1385 (MAX_MNEM_SIZE): Changed to 20.
1387 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1389 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1391 2008-03-09 Paul Brook <paul@codesourcery.com>
1393 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1395 2008-03-04 Paul Brook <paul@codesourcery.com>
1397 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1398 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1399 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1401 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1402 Nick Clifton <nickc@redhat.com>
1405 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1406 with a 32-bit displacement but without the top bit of the 4th byte
1409 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1411 * cr16.h (cr16_num_optab): Declared.
1413 2008-02-14 Hakan Ardo <hakan@debian.org>
1416 * avr.h (AVR_ISA_2xxe): Define.
1418 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1420 * mips.h: Update copyright.
1421 (INSN_CHIP_MASK): New macro.
1422 (INSN_OCTEON): New macro.
1423 (CPU_OCTEON): New macro.
1424 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1426 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1428 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1430 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1432 * avr.h (AVR_ISA_USB162): Add new opcode set.
1433 (AVR_ISA_AVR3): Likewise.
1435 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1437 * mips.h (INSN_LOONGSON_2E): New.
1438 (INSN_LOONGSON_2F): New.
1439 (CPU_LOONGSON_2E): New.
1440 (CPU_LOONGSON_2F): New.
1441 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1443 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1445 * mips.h (INSN_ISA*): Redefine certain values as an
1446 enumeration. Update comments.
1447 (mips_isa_table): New.
1448 (ISA_MIPS*): Redefine to match enumeration.
1449 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1452 2007-08-08 Ben Elliston <bje@au.ibm.com>
1454 * ppc.h (PPC_OPCODE_PPCPS): New.
1456 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1458 * m68k.h: Document j K & E.
1460 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1462 * cr16.h: New file for CR16 target.
1464 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1466 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1468 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1470 * m68k.h (mcfisa_c): New.
1471 (mcfusp, mcf_mask): Adjust.
1473 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1475 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1476 (num_powerpc_operands): Declare.
1477 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1478 (PPC_OPERAND_PLUS1): Define.
1480 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1482 * i386.h (REX_MODE64): Renamed to ...
1484 (REX_EXTX): Renamed to ...
1486 (REX_EXTY): Renamed to ...
1488 (REX_EXTZ): Renamed to ...
1491 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1493 * i386.h: Add entries from config/tc-i386.h and move tables
1494 to opcodes/i386-opc.h.
1496 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1498 * i386.h (FloatDR): Removed.
1499 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1501 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1503 * spu-insns.h: Add soma double-float insns.
1505 2007-02-20 Thiemo Seufer <ths@mips.com>
1506 Chao-Ying Fu <fu@mips.com>
1508 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1509 (INSN_DSPR2): Add flag for DSP R2 instructions.
1510 (M_BALIGN): New macro.
1512 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1514 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1515 and Seg3ShortFrom with Shortform.
1517 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1520 * i386.h (i386_optab): Put the real "test" before the pseudo
1523 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1525 * m68k.h (m68010up): OR fido_a.
1527 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1529 * m68k.h (fido_a): New.
1531 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1533 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1534 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1537 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1539 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1541 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1543 * score-inst.h (enum score_insn_type): Add Insn_internal.
1545 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1546 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1547 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1548 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1549 Alan Modra <amodra@bigpond.net.au>
1551 * spu-insns.h: New file.
1554 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1556 * ppc.h (PPC_OPCODE_CELL): Define.
1558 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1560 * i386.h : Modify opcode to support for the change in POPCNT opcode
1561 in amdfam10 architecture.
1563 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1565 * i386.h: Replace CpuMNI with CpuSSSE3.
1567 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1568 Joseph Myers <joseph@codesourcery.com>
1569 Ian Lance Taylor <ian@wasabisystems.com>
1570 Ben Elliston <bje@wasabisystems.com>
1572 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1574 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1576 * score-datadep.h: New file.
1577 * score-inst.h: New file.
1579 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1581 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1582 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1583 movdq2q and movq2dq.
1585 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1586 Michael Meissner <michael.meissner@amd.com>
1588 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1590 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1592 * i386.h (i386_optab): Add "nop" with memory reference.
1594 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1596 * i386.h (i386_optab): Update comment for 64bit NOP.
1598 2006-06-06 Ben Elliston <bje@au.ibm.com>
1599 Anton Blanchard <anton@samba.org>
1601 * ppc.h (PPC_OPCODE_POWER6): Define.
1604 2006-06-05 Thiemo Seufer <ths@mips.com>
1606 * mips.h: Improve description of MT flags.
1608 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1610 * m68k.h (mcf_mask): Define.
1612 2006-05-05 Thiemo Seufer <ths@mips.com>
1613 David Ung <davidu@mips.com>
1615 * mips.h (enum): Add macro M_CACHE_AB.
1617 2006-05-04 Thiemo Seufer <ths@mips.com>
1618 Nigel Stephens <nigel@mips.com>
1619 David Ung <davidu@mips.com>
1621 * mips.h: Add INSN_SMARTMIPS define.
1623 2006-04-30 Thiemo Seufer <ths@mips.com>
1624 David Ung <davidu@mips.com>
1626 * mips.h: Defines udi bits and masks. Add description of
1627 characters which may appear in the args field of udi
1630 2006-04-26 Thiemo Seufer <ths@networkno.de>
1632 * mips.h: Improve comments describing the bitfield instruction
1635 2006-04-26 Julian Brown <julian@codesourcery.com>
1637 * arm.h (FPU_VFP_EXT_V3): Define constant.
1638 (FPU_NEON_EXT_V1): Likewise.
1639 (FPU_VFP_HARD): Update.
1640 (FPU_VFP_V3): Define macro.
1641 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1643 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1645 * avr.h (AVR_ISA_PWMx): New.
1647 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1649 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1650 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1651 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1652 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1653 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1655 2006-03-10 Paul Brook <paul@codesourcery.com>
1657 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1659 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1661 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1662 first. Correct mask of bb "B" opcode.
1664 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1666 * i386.h (i386_optab): Support Intel Merom New Instructions.
1668 2006-02-24 Paul Brook <paul@codesourcery.com>
1670 * arm.h: Add V7 feature bits.
1672 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1674 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1676 2006-01-31 Paul Brook <paul@codesourcery.com>
1677 Richard Earnshaw <rearnsha@arm.com>
1679 * arm.h: Use ARM_CPU_FEATURE.
1680 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1681 (arm_feature_set): Change to a structure.
1682 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1683 ARM_FEATURE): New macros.
1685 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1687 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1688 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1689 (ADD_PC_INCR_OPCODE): Don't define.
1691 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1694 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1696 2005-11-14 David Ung <davidu@mips.com>
1698 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1699 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1700 save/restore encoding of the args field.
1702 2005-10-28 Dave Brolley <brolley@redhat.com>
1704 Contribute the following changes:
1705 2005-02-16 Dave Brolley <brolley@redhat.com>
1707 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1708 cgen_isa_mask_* to cgen_bitset_*.
1711 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1713 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1714 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1715 (CGEN_CPU_TABLE): Make isas a ponter.
1717 2003-09-29 Dave Brolley <brolley@redhat.com>
1719 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1720 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1721 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1723 2002-12-13 Dave Brolley <brolley@redhat.com>
1725 * cgen.h (symcat.h): #include it.
1726 (cgen-bitset.h): #include it.
1727 (CGEN_ATTR_VALUE_TYPE): Now a union.
1728 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1729 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1730 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1731 * cgen-bitset.h: New file.
1733 2005-09-30 Catherine Moore <clm@cm00re.com>
1737 2005-10-24 Jan Beulich <jbeulich@novell.com>
1739 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1742 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1744 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1745 Add FLAG_STRICT to pa10 ftest opcode.
1747 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1749 * hppa.h (pa_opcodes): Remove lha entries.
1751 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1753 * hppa.h (FLAG_STRICT): Revise comment.
1754 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1755 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1758 2005-09-30 Catherine Moore <clm@cm00re.com>
1762 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1764 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1766 2005-09-06 Chao-ying Fu <fu@mips.com>
1768 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1769 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1771 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1772 (INSN_ASE_MASK): Update to include INSN_MT.
1773 (INSN_MT): New define for MT ASE.
1775 2005-08-25 Chao-ying Fu <fu@mips.com>
1777 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1778 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1779 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1780 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1781 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1782 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1784 (INSN_DSP): New define for DSP ASE.
1786 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1790 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1792 * ppc.h (PPC_OPCODE_E300): Define.
1794 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1796 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1798 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1801 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1804 2005-07-27 Jan Beulich <jbeulich@novell.com>
1806 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1807 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1808 Add movq-s as 64-bit variants of movd-s.
1810 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1812 * hppa.h: Fix punctuation in comment.
1814 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1815 implicit space-register addressing. Set space-register bits on opcodes
1816 using implicit space-register addressing. Add various missing pa20
1817 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1818 space-register addressing. Use "fE" instead of "fe" in various
1821 2005-07-18 Jan Beulich <jbeulich@novell.com>
1823 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1825 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1827 * i386.h (i386_optab): Support Intel VMX Instructions.
1829 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1831 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1833 2005-07-05 Jan Beulich <jbeulich@novell.com>
1835 * i386.h (i386_optab): Add new insns.
1837 2005-07-01 Nick Clifton <nickc@redhat.com>
1839 * sparc.h: Add typedefs to structure declarations.
1841 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1844 * i386.h (i386_optab): Update comments for 64bit addressing on
1845 mov. Allow 64bit addressing for mov and movq.
1847 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1849 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1850 respectively, in various floating-point load and store patterns.
1852 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1854 * hppa.h (FLAG_STRICT): Correct comment.
1855 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1856 PA 2.0 mneumonics when equivalent. Entries with cache control
1857 completers now require PA 1.1. Adjust whitespace.
1859 2005-05-19 Anton Blanchard <anton@samba.org>
1861 * ppc.h (PPC_OPCODE_POWER5): Define.
1863 2005-05-10 Nick Clifton <nickc@redhat.com>
1865 * Update the address and phone number of the FSF organization in
1866 the GPL notices in the following files:
1867 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1868 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1869 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1870 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1871 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1872 tic54x.h, tic80.h, v850.h, vax.h
1874 2005-05-09 Jan Beulich <jbeulich@novell.com>
1876 * i386.h (i386_optab): Add ht and hnt.
1878 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1880 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1881 Add xcrypt-ctr. Provide aliases without hyphens.
1883 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1885 Moved from ../ChangeLog
1887 2005-04-12 Paul Brook <paul@codesourcery.com>
1888 * m88k.h: Rename psr macros to avoid conflicts.
1890 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1891 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1892 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1893 and ARM_ARCH_V6ZKT2.
1895 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1896 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1897 Remove redundant instruction types.
1898 (struct argument): X_op - new field.
1899 (struct cst4_entry): Remove.
1900 (no_op_insn): Declare.
1902 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1903 * crx.h (enum argtype): Rename types, remove unused types.
1905 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1906 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1907 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1908 (enum operand_type): Rearrange operands, edit comments.
1909 replace us<N> with ui<N> for unsigned immediate.
1910 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1911 displacements (respectively).
1912 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1913 (instruction type): Add NO_TYPE_INS.
1914 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1915 (operand_entry): New field - 'flags'.
1916 (operand flags): New.
1918 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1919 * crx.h (operand_type): Remove redundant types i3, i4,
1921 Add new unsigned immediate types us3, us4, us5, us16.
1923 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1925 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1926 adjust them accordingly.
1928 2005-04-01 Jan Beulich <jbeulich@novell.com>
1930 * i386.h (i386_optab): Add rdtscp.
1932 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1934 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1935 between memory and segment register. Allow movq for moving between
1936 general-purpose register and segment register.
1938 2005-02-09 Jan Beulich <jbeulich@novell.com>
1941 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1942 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1945 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1947 * m68k.h (m68008, m68ec030, m68882): Remove.
1949 (cpu_m68k, cpu_cf): New.
1950 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1951 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1953 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1955 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1956 * cgen.h (enum cgen_parse_operand_type): Add
1957 CGEN_PARSE_OPERAND_SYMBOLIC.
1959 2005-01-21 Fred Fish <fnf@specifixinc.com>
1961 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1962 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1963 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1965 2005-01-19 Fred Fish <fnf@specifixinc.com>
1967 * mips.h (struct mips_opcode): Add new pinfo2 member.
1968 (INSN_ALIAS): New define for opcode table entries that are
1969 specific instances of another entry, such as 'move' for an 'or'
1970 with a zero operand.
1971 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1972 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1974 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1976 * mips.h (CPU_RM9000): Define.
1977 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1979 2004-11-25 Jan Beulich <jbeulich@novell.com>
1981 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1982 to/from test registers are illegal in 64-bit mode. Add missing
1983 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1984 (previously one had to explicitly encode a rex64 prefix). Re-enable
1985 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1986 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1988 2004-11-23 Jan Beulich <jbeulich@novell.com>
1990 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1991 available only with SSE2. Change the MMX additions introduced by SSE
1992 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1993 instructions by their now designated identifier (since combining i686
1994 and 3DNow! does not really imply 3DNow!A).
1996 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1998 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1999 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2001 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2002 Vineet Sharma <vineets@noida.hcltech.com>
2004 * maxq.h: New file: Disassembly information for the maxq port.
2006 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2008 * i386.h (i386_optab): Put back "movzb".
2010 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2012 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2013 comments. Remove member cris_ver_sim. Add members
2014 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2015 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2016 (struct cris_support_reg, struct cris_cond15): New types.
2017 (cris_conds15): Declare.
2018 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2019 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2020 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2021 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2022 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2023 SIZE_FIELD_UNSIGNED.
2025 2004-11-04 Jan Beulich <jbeulich@novell.com>
2027 * i386.h (sldx_Suf): Remove.
2028 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2029 (q_FP): Define, implying no REX64.
2030 (x_FP, sl_FP): Imply FloatMF.
2031 (i386_optab): Split reg and mem forms of moving from segment registers
2032 so that the memory forms can ignore the 16-/32-bit operand size
2033 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2034 all non-floating-point instructions. Unite 32- and 64-bit forms of
2035 movsx, movzx, and movd. Adjust floating point operations for the above
2036 changes to the *FP macros. Add DefaultSize to floating point control
2037 insns operating on larger memory ranges. Remove left over comments
2038 hinting at certain insns being Intel-syntax ones where the ones
2039 actually meant are already gone.
2041 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2043 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2046 2004-09-30 Paul Brook <paul@codesourcery.com>
2048 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2049 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2051 2004-09-11 Theodore A. Roth <troth@openavr.org>
2053 * avr.h: Add support for
2054 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2056 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2058 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2060 2004-08-24 Dmitry Diky <diwil@spec.ru>
2062 * msp430.h (msp430_opc): Add new instructions.
2063 (msp430_rcodes): Declare new instructions.
2064 (msp430_hcodes): Likewise..
2066 2004-08-13 Nick Clifton <nickc@redhat.com>
2069 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2072 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2074 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2076 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2078 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2080 2004-07-21 Jan Beulich <jbeulich@novell.com>
2082 * i386.h: Adjust instruction descriptions to better match the
2085 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2087 * arm.h: Remove all old content. Replace with architecture defines
2088 from gas/config/tc-arm.c.
2090 2004-07-09 Andreas Schwab <schwab@suse.de>
2092 * m68k.h: Fix comment.
2094 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2098 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2100 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2102 2004-05-24 Peter Barada <peter@the-baradas.com>
2104 * m68k.h: Add 'size' to m68k_opcode.
2106 2004-05-05 Peter Barada <peter@the-baradas.com>
2108 * m68k.h: Switch from ColdFire chip name to core variant.
2110 2004-04-22 Peter Barada <peter@the-baradas.com>
2112 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2113 descriptions for new EMAC cases.
2114 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2115 handle Motorola MAC syntax.
2116 Allow disassembly of ColdFire V4e object files.
2118 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2120 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2122 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2124 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2126 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2128 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2130 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2132 * i386.h (i386_optab): Added xstore/xcrypt insns.
2134 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2136 * h8300.h (32bit ldc/stc): Add relaxing support.
2138 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2140 * h8300.h (BITOP): Pass MEMRELAX flag.
2142 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2144 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2147 For older changes see ChangeLog-9103
2149 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2151 Copying and distribution of this file, with or without modification,
2152 are permitted in any medium without royalty provided the copyright
2153 notice and this notice are preserved.
2159 version-control: never