1 2015-11-11 Alan Modra <amodra@gmail.com>
2 Peter Bergner <bergner@vnet.ibm.com>
4 * ppc.h (PPC_OPCODE_POWER9): New define.
5 (PPC_OPCODE_VSX3): Likewise.
7 2015-11-02 Nick Clifton <nickc@redhat.com>
9 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
11 2015-11-02 Nick Clifton <nickc@redhat.com>
13 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
15 2015-10-28 Yao Qi <yao.qi@linaro.org>
17 * aarch64.h (aarch64_decode_insn): Update declaration.
19 2015-10-07 Yao Qi <yao.qi@linaro.org>
21 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
24 2015-10-07 Yao Qi <yao.qi@linaro.org>
26 * aarch64.h [__cplusplus]: Wrap in extern "C".
28 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
29 Cupertino Miranda <cmiranda@synopsys.com>
31 * arc-func.h: New file.
34 2015-10-02 Yao Qi <yao.qi@linaro.org>
36 * aarch64.h (aarch64_zero_register_p): Move the declaration
39 2015-10-02 Yao Qi <yao.qi@linaro.org>
41 * aarch64.h (aarch64_decode_insn): Declare it.
43 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
45 * s390.h (S390_INSTR_FLAG_HTM): New flag.
46 (S390_INSTR_FLAG_VX): New flag.
47 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
49 2015-09-23 Nick Clifton <nickc@redhat.com>
51 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
54 2015-09-22 Nick Clifton <nickc@redhat.com>
56 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
58 2015-09-09 Daniel Santos <daniel.santos@pobox.com>
60 * visium.h (gen_reg_table): Make static.
61 (fp_reg_table): Likewise.
64 2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
66 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
67 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
68 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
69 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
71 2015-07-03 Alan Modra <amodra@gmail.com>
73 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
75 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
76 Cesar Philippidis <cesar@codesourcery.com>
78 * nios2.h (enum iw_format_type): Add R2 formats.
79 (enum overflow_type): Add signed_immed12_overflow and
80 enumeration_overflow for R2.
81 (struct nios2_opcode): Document new argument letters for R2.
82 (REG_3BIT, REG_LDWM, REG_POP): Define.
83 (includes): Include nios2r2.h.
84 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
85 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
86 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
87 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
88 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
89 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
91 * nios2r2.h: New file.
93 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
95 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
96 (ppc_optional_operand_value): New inline function.
98 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
100 * aarch64.h (AARCH64_V8_1): New.
102 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
104 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
105 (ARM_ARCH_V8_1A): New.
106 (ARM_ARCH_V8_1A_FP): New.
107 (ARM_ARCH_V8_1A_SIMD): New.
108 (ARM_ARCH_V8_1A_CRYPTOV1): New.
109 (ARM_FEATURE_CORE): New.
111 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
113 * arm.h (ARM_EXT2_PAN): New.
114 (ARM_FEATURE_CORE_HIGH): New.
116 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
118 * arm.h (ARM_FEATURE_ALL): New.
120 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
122 * aarch64.h (AARCH64_FEATURE_RDMA): New.
124 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
126 * aarch64.h (AARCH64_FEATURE_LOR): New.
128 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
130 * aarch64.h (AARCH64_FEATURE_PAN): New.
131 (aarch64_sys_reg_supported_p): Declare.
132 (aarch64_pstatefield_supported_p): Declare.
134 2015-04-30 DJ Delorie <dj@redhat.com>
136 * rl78.h (RL78_Dis_Isa): New.
137 (rl78_decode_opcode): Add ISA parameter.
139 2015-03-24 Terry Guo <terry.guo@arm.com>
141 * arm.h (arm_feature_set): Extended to provide more available bits.
142 (ARM_ANY): Updated to follow above new definition.
143 (ARM_CPU_HAS_FEATURE): Likewise.
144 (ARM_CPU_IS_ANY): Likewise.
145 (ARM_MERGE_FEATURE_SETS): Likewise.
146 (ARM_CLEAR_FEATURE): Likewise.
147 (ARM_FEATURE): Likewise.
148 (ARM_FEATURE_COPY): New macro.
149 (ARM_FEATURE_EQUAL): Likewise.
150 (ARM_FEATURE_ZERO): Likewise.
151 (ARM_FEATURE_CORE_EQUAL): Likewise.
152 (ARM_FEATURE_LOW): Likewise.
153 (ARM_FEATURE_CORE_LOW): Likewise.
154 (ARM_FEATURE_CORE_COPROC): Likewise.
156 2015-02-19 Pedro Alves <palves@redhat.com>
158 * cgen.h [__cplusplus]: Wrap in extern "C".
159 * msp430-decode.h [__cplusplus]: Likewise.
160 * nios2.h [__cplusplus]: Likewise.
161 * rl78.h [__cplusplus]: Likewise.
162 * rx.h [__cplusplus]: Likewise.
163 * tilegx.h [__cplusplus]: Likewise.
165 2015-01-28 James Bowman <james.bowman@ftdichip.com>
169 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
171 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
173 2015-01-01 Alan Modra <amodra@gmail.com>
175 Update year range in copyright notice of all files.
177 2014-12-27 Anthony Green <green@moxielogic.com>
179 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
180 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
182 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
184 * visium.h: New file.
186 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
188 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
189 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
190 (NIOS2_INSN_OPTARG): Renumber.
192 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
194 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
195 declaration. Fix obsolete comment.
197 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
199 * nios2.h (enum iw_format_type): New.
200 (struct nios2_opcode): Update comments. Add size and format fields.
201 (NIOS2_INSN_OPTARG): New.
202 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
203 (struct nios2_reg): Add regtype field.
204 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
205 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
206 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
207 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
208 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
209 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
210 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
211 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
212 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
213 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
214 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
215 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
216 (OP_MASK_OP, OP_SH_OP): Delete.
217 (OP_MASK_IOP, OP_SH_IOP): Delete.
218 (OP_MASK_IRD, OP_SH_IRD): Delete.
219 (OP_MASK_IRT, OP_SH_IRT): Delete.
220 (OP_MASK_IRS, OP_SH_IRS): Delete.
221 (OP_MASK_ROP, OP_SH_ROP): Delete.
222 (OP_MASK_RRD, OP_SH_RRD): Delete.
223 (OP_MASK_RRT, OP_SH_RRT): Delete.
224 (OP_MASK_RRS, OP_SH_RRS): Delete.
225 (OP_MASK_JOP, OP_SH_JOP): Delete.
226 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
227 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
228 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
229 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
230 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
231 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
232 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
233 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
234 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
235 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
236 (OP_MASK_<insn>, OP_MASK): Delete.
237 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
238 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
239 Include nios2r1.h to define new instruction opcode constants
241 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
242 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
243 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
244 (NUMOPCODES, NUMREGISTERS): Delete.
245 * nios2r1.h: New file.
247 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
249 * sparc.h (HWCAP2_VIS3B): Documentation improved.
251 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
253 * sparc.h (sparc_opcode): new field `hwcaps2'.
254 (HWCAP2_FJATHPLUS): New define.
255 (HWCAP2_VIS3B): Likewise.
256 (HWCAP2_ADP): Likewise.
257 (HWCAP2_SPARC5): Likewise.
258 (HWCAP2_MWAIT): Likewise.
259 (HWCAP2_XMPMUL): Likewise.
260 (HWCAP2_XMONT): Likewise.
261 (HWCAP2_NSEC): Likewise.
262 (HWCAP2_FJATHHPC): Likewise.
263 (HWCAP2_FJDES): Likewise.
264 (HWCAP2_FJAES): Likewise.
265 Document the new operand kind `{', corresponding to the mcdper
266 ancillary state register.
267 Document the new operand kind }, which represents frsd floating
268 point registers (double precision) which must be the same than
269 frs1 in its containing instruction.
271 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
273 * nds32.h: Add new opcode declaration.
275 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
276 Matthew Fortune <matthew.fortune@imgtec.com>
278 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
279 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
280 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
281 +I, +O, +R, +:, +\, +", +;
282 (mips_check_prev_operand): New struct.
283 (INSN2_FORBIDDEN_SLOT): New define.
284 (INSN_ISA32R6): New define.
285 (INSN_ISA64R6): New define.
286 (INSN_UPTO32R6): New define.
287 (INSN_UPTO64R6): New define.
288 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
289 (ISA_MIPS32R6): New define.
290 (ISA_MIPS64R6): New define.
291 (CPU_MIPS32R6): New define.
292 (CPU_MIPS64R6): New define.
293 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
295 2014-09-03 Jiong Wang <jiong.wang@arm.com>
297 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
298 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
299 (aarch64_insn_class): Add lse_atomic.
300 (F_LSE_SZ): New field added.
301 (opcode_has_special_coder): Recognize F_LSE_SZ.
303 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
305 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
308 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
310 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
311 (INSN_LOAD_COPROC): New define.
312 (INSN_COPROC_MOVE_DELAY): Rename to...
313 (INSN_COPROC_MOVE): New define.
315 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
316 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
317 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
318 Soundararajan <Sounderarajan.D@atmel.com>
320 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
321 (AVR_ISA_2xxxa): Define ISA without LPM.
322 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
323 Add doc for contraint used in 16 bit lds/sts.
324 Adjust ISA group for icall, ijmp, pop and push.
325 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
327 2014-05-19 Nick Clifton <nickc@redhat.com>
329 * msp430.h (struct msp430_operand_s): Add vshift field.
331 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
333 * mips.h (INSN_ISA_MASK): Updated.
334 (INSN_ISA32R3): New define.
335 (INSN_ISA32R5): New define.
336 (INSN_ISA64R3): New define.
337 (INSN_ISA64R5): New define.
338 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
339 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
340 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
342 (INSN_UPTO32R3): New define.
343 (INSN_UPTO32R5): New define.
344 (INSN_UPTO64R3): New define.
345 (INSN_UPTO64R5): New define.
346 (ISA_MIPS32R3): New define.
347 (ISA_MIPS32R5): New define.
348 (ISA_MIPS64R3): New define.
349 (ISA_MIPS64R5): New define.
350 (CPU_MIPS32R3): New define.
351 (CPU_MIPS32R5): New define.
352 (CPU_MIPS64R3): New define.
353 (CPU_MIPS64R5): New define.
355 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
357 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
359 2014-04-22 Christian Svensson <blue@cmd.nu>
363 2014-03-05 Alan Modra <amodra@gmail.com>
365 Update copyright years.
367 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
369 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
372 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
373 Wei-Cheng Wang <cole945@gmail.com>
375 * nds32.h: New file for Andes NDS32.
377 2013-12-07 Mike Frysinger <vapier@gentoo.org>
379 * bfin.h: Remove +x file mode.
381 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
383 * aarch64.h (aarch64_pstatefields): Change element type to
386 2013-11-18 Renlin Li <Renlin.Li@arm.com>
388 * arm.h (ARM_AEXT_V7VE): New define.
389 (ARM_ARCH_V7VE): New define.
390 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
392 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
396 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
398 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
399 (aarch64_sys_reg_writeonly_p): Ditto.
401 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
403 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
404 (aarch64_sys_reg_writeonly_p): Ditto.
406 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
408 * aarch64.h (aarch64_sys_reg): New typedef.
409 (aarch64_sys_regs): Change to define with the new type.
410 (aarch64_sys_reg_deprecated_p): Declare.
412 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
414 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
415 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
417 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
419 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
420 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
421 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
422 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
423 For MIPS, update extension character sequences after +.
424 (ASE_MSA): New define.
425 (ASE_MSA64): New define.
426 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
427 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
428 For microMIPS, update extension character sequences after +.
430 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
435 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
437 * mips.h: Remove references to "+I" and imm2_expr.
439 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
441 * mips.h (M_DEXT, M_DINS): Delete.
443 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
445 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
446 (mips_optional_operand_p): New function.
448 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
449 Richard Sandiford <rdsandiford@googlemail.com>
451 * mips.h: Document new VU0 operand characters.
452 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
453 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
454 (OP_REG_R5900_ACC): New mips_reg_operand_types.
455 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
456 (mips_vu0_channel_mask): Declare.
458 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
460 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
461 (mips_int_operand_min, mips_int_operand_max): New functions.
462 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
464 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
466 * mips.h (mips_decode_reg_operand): New function.
467 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
468 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
469 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
471 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
472 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
473 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
474 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
475 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
476 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
477 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
478 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
479 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
480 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
481 macros to cover the gaps.
482 (INSN2_MOD_SP): Replace with...
483 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
484 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
485 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
486 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
487 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
490 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
492 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
493 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
494 (MIPS16_INSN_COND_BRANCH): Delete.
496 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
497 Kirill Yukhin <kirill.yukhin@intel.com>
498 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
500 * i386.h (BND_PREFIX_OPCODE): New.
502 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
504 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
505 OP_SAVE_RESTORE_LIST.
506 (decode_mips16_operand): Declare.
508 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
510 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
511 (mips_operand, mips_int_operand, mips_mapped_int_operand)
512 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
513 (mips_pcrel_operand): New structures.
514 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
515 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
516 (decode_mips_operand, decode_micromips_operand): Declare.
518 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
520 * mips.h: Document MIPS16 "I" opcode.
522 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
524 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
525 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
526 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
527 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
528 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
529 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
530 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
531 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
532 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
533 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
534 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
535 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
536 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
538 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
539 (M_USD_AB): ...these.
541 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
543 * mips.h: Remove documentation of "[" and "]". Update documentation
544 of "k" and the MDMX formats.
546 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
548 * mips.h: Update documentation of "+s" and "+S".
550 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
552 * mips.h: Document "+i".
554 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
556 * mips.h: Remove "mi" documentation. Update "mh" documentation.
557 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
559 (INSN2_WRITE_GPR_MHI): Rename to...
560 (INSN2_WRITE_GPR_MH): ...this.
562 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
564 * mips.h: Remove documentation of "+D" and "+T".
566 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
568 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
569 Use "source" rather than "destination" for microMIPS "G".
571 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
573 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
576 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
578 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
580 2013-06-17 Catherine Moore <clm@codesourcery.com>
581 Maciej W. Rozycki <macro@codesourcery.com>
582 Chao-Ying Fu <fu@mips.com>
584 * mips.h (OP_SH_EVAOFFSET): Define.
585 (OP_MASK_EVAOFFSET): Define.
586 (INSN_ASE_MASK): Delete.
588 (M_CACHEE_AB, M_CACHEE_OB): New.
589 (M_LBE_OB, M_LBE_AB): New.
590 (M_LBUE_OB, M_LBUE_AB): New.
591 (M_LHE_OB, M_LHE_AB): New.
592 (M_LHUE_OB, M_LHUE_AB): New.
593 (M_LLE_AB, M_LLE_OB): New.
594 (M_LWE_OB, M_LWE_AB): New.
595 (M_LWLE_AB, M_LWLE_OB): New.
596 (M_LWRE_AB, M_LWRE_OB): New.
597 (M_PREFE_AB, M_PREFE_OB): New.
598 (M_SCE_AB, M_SCE_OB): New.
599 (M_SBE_OB, M_SBE_AB): New.
600 (M_SHE_OB, M_SHE_AB): New.
601 (M_SWE_OB, M_SWE_AB): New.
602 (M_SWLE_AB, M_SWLE_OB): New.
603 (M_SWRE_AB, M_SWRE_OB): New.
604 (MICROMIPSOP_SH_EVAOFFSET): Define.
605 (MICROMIPSOP_MASK_EVAOFFSET): Define.
607 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
609 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
611 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
613 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
615 2013-05-09 Andrew Pinski <apinski@cavium.com>
617 * mips.h (OP_MASK_CODE10): Correct definition.
618 (OP_SH_CODE10): Likewise.
619 Add a comment that "+J" is used now for OP_*CODE10.
620 (INSN_ASE_MASK): Update.
621 (INSN_VIRT): New macro.
622 (INSN_VIRT64): New macro
624 2013-05-02 Nick Clifton <nickc@redhat.com>
626 * msp430.h: Add patterns for MSP430X instructions.
628 2013-04-06 David S. Miller <davem@davemloft.net>
630 * sparc.h (F_PREFERRED): Define.
631 (F_PREF_ALIAS): Define.
633 2013-04-03 Nick Clifton <nickc@redhat.com>
635 * v850.h (V850_INVERSE_PCREL): Define.
637 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
640 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
642 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
645 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
647 * tic6xc-opcode-table.h: Add 16-bit insns.
648 * tic6x.h: Add support for 16-bit insns.
650 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
652 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
653 and mov.b/w/l Rs,@(d:32,ERd).
655 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
658 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
659 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
660 tic6x_operand_xregpair operand coding type.
661 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
662 opcode field, usu ORXREGD1324 for the src2 operand and remove the
665 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
668 * tic6x.h (enum tic6x_coding_method): Add
669 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
670 separately the msb and lsb of a register pair. This is needed to
671 encode the opcodes in the same way as TI assembler does.
672 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
673 and rsqrdp opcodes to use the new field coding types.
675 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
677 * arm.h (CRC_EXT_ARMV8): New constant.
678 (ARCH_CRC_ARMV8): New macro.
680 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
682 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
684 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
685 Andrew Jenner <andrew@codesourcery.com>
687 Based on patches from Altera Corporation.
691 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
693 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
695 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
698 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
700 2013-01-24 Nick Clifton <nickc@redhat.com>
702 * v850.h: Add e3v5 support.
704 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
706 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
708 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
710 * ppc.h (PPC_OPCODE_POWER8): New define.
711 (PPC_OPCODE_HTM): Likewise.
713 2013-01-10 Will Newton <will.newton@imgtec.com>
717 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
719 * cr16.h (make_instruction): Rename to cr16_make_instruction.
720 (match_opcode): Rename to cr16_match_opcode.
722 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
724 * mips.h: Add support for r5900 instructions including lq and sq.
726 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
728 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
729 (make_instruction,match_opcode): Added function prototypes.
730 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
732 2012-11-23 Alan Modra <amodra@gmail.com>
734 * ppc.h (ppc_parse_cpu): Update prototype.
736 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
738 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
739 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
741 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
743 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
745 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
747 * ia64.h (ia64_opnd): Add new operand types.
749 2012-08-21 David S. Miller <davem@davemloft.net>
751 * sparc.h (F3F4): New macro.
753 2012-08-13 Ian Bolton <ian.bolton@arm.com>
754 Laurent Desnogues <laurent.desnogues@arm.com>
755 Jim MacArthur <jim.macarthur@arm.com>
756 Marcus Shawcroft <marcus.shawcroft@arm.com>
757 Nigel Stephens <nigel.stephens@arm.com>
758 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
759 Richard Earnshaw <rearnsha@arm.com>
760 Sofiane Naci <sofiane.naci@arm.com>
761 Tejas Belagod <tejas.belagod@arm.com>
762 Yufeng Zhang <yufeng.zhang@arm.com>
764 * aarch64.h: New file.
766 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
767 Maciej W. Rozycki <macro@codesourcery.com>
769 * mips.h (mips_opcode): Add the exclusions field.
770 (OPCODE_IS_MEMBER): Remove macro.
771 (cpu_is_member): New inline function.
772 (opcode_is_member): Likewise.
774 2012-07-31 Chao-Ying Fu <fu@mips.com>
775 Catherine Moore <clm@codesourcery.com>
776 Maciej W. Rozycki <macro@codesourcery.com>
778 * mips.h: Document microMIPS DSP ASE usage.
779 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
780 microMIPS DSP ASE support.
781 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
782 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
783 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
784 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
785 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
786 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
787 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
789 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
791 * mips.h: Fix a typo in description.
793 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
795 * avr.h: (AVR_ISA_XCH): New define.
796 (AVR_ISA_XMEGA): Use it.
797 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
799 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
801 * m68hc11.h: Add XGate definitions.
802 (struct m68hc11_opcode): Add xg_mask field.
804 2012-05-14 Catherine Moore <clm@codesourcery.com>
805 Maciej W. Rozycki <macro@codesourcery.com>
806 Rhonda Wittels <rhonda@codesourcery.com>
808 * ppc.h (PPC_OPCODE_VLE): New definition.
809 (PPC_OP_SA): New macro.
810 (PPC_OP_SE_VLE): New macro.
811 (PPC_OP): Use a variable shift amount.
812 (powerpc_operand): Update comments.
813 (PPC_OPSHIFT_INV): New macro.
814 (PPC_OPERAND_CR): Replace with...
815 (PPC_OPERAND_CR_BIT): ...this and
816 (PPC_OPERAND_CR_REG): ...this.
819 2012-05-03 Sean Keys <skeys@ipdatasys.com>
821 * xgate.h: Header file for XGATE assembler.
823 2012-04-27 David S. Miller <davem@davemloft.net>
825 * sparc.h: Document new arg code' )' for crypto RS3
828 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
829 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
830 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
831 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
832 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
833 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
834 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
835 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
836 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
837 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
838 HWCAP_CBCOND, HWCAP_CRC32): New defines.
840 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
842 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
844 2012-02-27 Alan Modra <amodra@gmail.com>
846 * crx.h (cst4_map): Update declaration.
848 2012-02-25 Walter Lee <walt@tilera.com>
850 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
852 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
853 TILEPRO_OPC_LW_TLS_SN.
855 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
857 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
858 (XRELEASE_PREFIX_OPCODE): Likewise.
860 2011-12-08 Andrew Pinski <apinski@cavium.com>
861 Adam Nemet <anemet@caviumnetworks.com>
863 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
864 (INSN_OCTEON2): New macro.
865 (CPU_OCTEON2): New macro.
866 (OPCODE_IS_MEMBER): Add Octeon2.
868 2011-11-29 Andrew Pinski <apinski@cavium.com>
870 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
871 (INSN_OCTEONP): New macro.
872 (CPU_OCTEONP): New macro.
873 (OPCODE_IS_MEMBER): Add Octeon+.
874 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
876 2011-11-01 DJ Delorie <dj@redhat.com>
880 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
882 * mips.h: Fix a typo in description.
884 2011-09-21 David S. Miller <davem@davemloft.net>
886 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
887 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
888 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
889 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
891 2011-08-09 Chao-ying Fu <fu@mips.com>
892 Maciej W. Rozycki <macro@codesourcery.com>
894 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
895 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
896 (INSN_ASE_MASK): Add the MCU bit.
897 (INSN_MCU): New macro.
898 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
899 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
901 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
903 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
904 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
905 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
906 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
907 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
908 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
909 (INSN2_READ_GPR_MMN): Likewise.
910 (INSN2_READ_FPR_D): Change the bit used.
911 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
912 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
913 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
914 (INSN2_COND_BRANCH): Likewise.
915 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
916 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
917 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
918 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
919 (INSN2_MOD_GPR_MN): Likewise.
921 2011-08-05 David S. Miller <davem@davemloft.net>
923 * sparc.h: Document new format codes '4', '5', and '('.
924 (OPF_LOW4, RS3): New macros.
926 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
928 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
929 order of flags documented.
931 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
933 * mips.h: Clarify the description of microMIPS instruction
935 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
937 2011-07-24 Chao-ying Fu <fu@mips.com>
938 Maciej W. Rozycki <macro@codesourcery.com>
940 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
941 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
942 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
943 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
944 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
945 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
946 (OP_MASK_RS3, OP_SH_RS3): Likewise.
947 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
948 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
949 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
950 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
951 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
952 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
953 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
954 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
955 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
956 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
957 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
958 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
959 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
960 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
961 (INSN_WRITE_GPR_S): New macro.
962 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
963 (INSN2_READ_FPR_D): Likewise.
964 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
965 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
966 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
967 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
968 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
969 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
970 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
971 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
972 (CPU_MICROMIPS): New macro.
973 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
974 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
975 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
976 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
977 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
978 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
979 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
980 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
981 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
982 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
983 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
984 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
985 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
986 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
987 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
988 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
989 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
990 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
991 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
992 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
993 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
994 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
995 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
996 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
997 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
998 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
999 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1000 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1001 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1002 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1003 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1004 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1005 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1006 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1007 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1008 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1009 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1010 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1011 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1012 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1013 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1014 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1015 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1016 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1017 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1018 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1019 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1020 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1021 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1022 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1023 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1024 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1025 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1026 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1027 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1028 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1029 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1030 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1031 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1032 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1033 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1034 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1035 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1036 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1037 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1038 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1039 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1040 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1041 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1042 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1043 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1044 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1045 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1046 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1047 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1048 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1049 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1050 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1051 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1052 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1053 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1054 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1055 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1056 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1057 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1058 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1059 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1060 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1061 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1062 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1063 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1064 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1065 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1066 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1067 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1068 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1069 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1070 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1071 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1072 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1073 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1074 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1075 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1076 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1077 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1078 (micromips_opcodes): New declaration.
1079 (bfd_micromips_num_opcodes): Likewise.
1081 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1083 * mips.h (INSN_TRAP): Rename to...
1084 (INSN_NO_DELAY_SLOT): ... this.
1085 (INSN_SYNC): Remove macro.
1087 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1089 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1090 a duplicate of AVR_ISA_SPM.
1092 2011-07-01 Nick Clifton <nickc@redhat.com>
1094 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1096 2011-06-18 Robin Getz <robin.getz@analog.com>
1098 * bfin.h (is_macmod_signed): New func
1100 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1102 * bfin.h (is_macmod_pmove): Add missing space before func args.
1103 (is_macmod_hmove): Likewise.
1105 2011-06-13 Walter Lee <walt@tilera.com>
1107 * tilegx.h: New file.
1108 * tilepro.h: New file.
1110 2011-05-31 Paul Brook <paul@codesourcery.com>
1112 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1114 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1116 * s390.h: Replace S390_OPERAND_REG_EVEN with
1117 S390_OPERAND_REG_PAIR.
1119 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1121 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1123 2011-04-18 Julian Brown <julian@codesourcery.com>
1125 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1127 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1130 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1132 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1134 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1135 New instruction set flags.
1136 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1138 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1140 * mips.h (M_PREF_AB): New enum value.
1142 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1144 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1146 (is_macmod_pmove, is_macmod_hmove): New functions.
1148 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1150 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1152 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1154 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1155 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1157 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1160 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1163 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1166 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1168 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1170 * mips.h: Update commentary after last commit.
1172 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1174 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1175 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1176 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1178 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1180 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1182 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1184 * mips.h: Fix previous commit.
1186 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1188 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1189 (INSN_LOONGSON_3A): Clear bit 31.
1191 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1194 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1195 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1196 (ARM_ARCH_V6M_ONLY): New define.
1198 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1200 * mips.h (INSN_LOONGSON_3A): Defined.
1201 (CPU_LOONGSON_3A): Defined.
1202 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1204 2010-10-09 Matt Rice <ratmice@gmail.com>
1206 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1207 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1209 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1211 * arm.h (ARM_EXT_VIRT): New define.
1212 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1213 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1216 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1218 * arm.h (ARM_AEXT_ADIV): New define.
1219 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1221 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1223 * arm.h (ARM_EXT_OS): New define.
1224 (ARM_AEXT_V6SM): Likewise.
1225 (ARM_ARCH_V6SM): Likewise.
1227 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1229 * arm.h (ARM_EXT_MP): Add.
1230 (ARM_ARCH_V7A_MP): Likewise.
1232 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1234 * bfin.h: Declare pseudoChr structs/defines.
1236 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1238 * bfin.h: Strip trailing whitespace.
1240 2010-07-29 DJ Delorie <dj@redhat.com>
1242 * rx.h (RX_Operand_Type): Add TwoReg.
1243 (RX_Opcode_ID): Remove ediv and ediv2.
1245 2010-07-27 DJ Delorie <dj@redhat.com>
1247 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1249 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1250 Ina Pandit <ina.pandit@kpitcummins.com>
1252 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1253 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1254 PROCESSOR_V850E2_ALL.
1255 Remove PROCESSOR_V850EA support.
1256 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1257 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1258 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1259 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1260 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1261 V850_OPERAND_PERCENT.
1262 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1264 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1267 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1269 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1270 (MIPS16_INSN_BRANCH): Rename to...
1271 (MIPS16_INSN_COND_BRANCH): ... this.
1273 2010-07-03 Alan Modra <amodra@gmail.com>
1275 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1276 Renumber other PPC_OPCODE defines.
1278 2010-07-03 Alan Modra <amodra@gmail.com>
1280 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1282 2010-06-29 Alan Modra <amodra@gmail.com>
1284 * maxq.h: Delete file.
1286 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1288 * ppc.h (PPC_OPCODE_E500): Define.
1290 2010-05-26 Catherine Moore <clm@codesourcery.com>
1292 * opcode/mips.h (INSN_MIPS16): Remove.
1294 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1296 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1298 2010-04-15 Nick Clifton <nickc@redhat.com>
1300 * alpha.h: Update copyright notice to use GPLv3.
1306 * convex.h: Likewise.
1313 * h8300.h: Likewise.
1320 * m68hc11.h: Likewise.
1326 * mn10200.h: Likewise.
1327 * mn10300.h: Likewise.
1328 * msp430.h: Likewise.
1330 * ns32k.h: Likewise.
1332 * pdp11.h: Likewise.
1339 * score-datadep.h: Likewise.
1340 * score-inst.h: Likewise.
1341 * sparc.h: Likewise.
1342 * spu-insns.h: Likewise.
1344 * tic30.h: Likewise.
1345 * tic4x.h: Likewise.
1346 * tic54x.h: Likewise.
1347 * tic80.h: Likewise.
1351 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1353 * tic6x-control-registers.h, tic6x-insn-formats.h,
1354 tic6x-opcode-table.h, tic6x.h: New.
1356 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1358 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1360 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1362 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1364 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1366 * ia64.h (ia64_find_opcode): Remove argument name.
1367 (ia64_find_next_opcode): Likewise.
1368 (ia64_dis_opcode): Likewise.
1369 (ia64_free_opcode): Likewise.
1370 (ia64_find_dependency): Likewise.
1372 2009-11-22 Doug Evans <dje@sebabeach.org>
1374 * cgen.h: Include bfd_stdint.h.
1375 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1377 2009-11-18 Paul Brook <paul@codesourcery.com>
1379 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1381 2009-11-17 Paul Brook <paul@codesourcery.com>
1382 Daniel Jacobowitz <dan@codesourcery.com>
1384 * arm.h (ARM_EXT_V6_DSP): Define.
1385 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1386 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1388 2009-11-04 DJ Delorie <dj@redhat.com>
1390 * rx.h (rx_decode_opcode) (mvtipl): Add.
1391 (mvtcp, mvfcp, opecp): Remove.
1393 2009-11-02 Paul Brook <paul@codesourcery.com>
1395 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1396 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1397 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1398 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1399 FPU_ARCH_NEON_VFP_V4): Define.
1401 2009-10-23 Doug Evans <dje@sebabeach.org>
1403 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1404 * cgen.h: Update. Improve multi-inclusion macro name.
1406 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1408 * ppc.h (PPC_OPCODE_476): Define.
1410 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1412 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1414 2009-09-29 DJ Delorie <dj@redhat.com>
1418 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1420 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1422 2009-09-21 Ben Elliston <bje@au.ibm.com>
1424 * ppc.h (PPC_OPCODE_PPCA2): New.
1426 2009-09-05 Martin Thuresson <martin@mtme.org>
1428 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1430 2009-08-29 Martin Thuresson <martin@mtme.org>
1432 * tic30.h (template): Rename type template to
1433 insn_template. Updated code to use new name.
1434 * tic54x.h (template): Rename type template to
1437 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1439 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1441 2009-06-11 Anthony Green <green@moxielogic.com>
1443 * moxie.h (MOXIE_F3_PCREL): Define.
1444 (moxie_form3_opc_info): Grow.
1446 2009-06-06 Anthony Green <green@moxielogic.com>
1448 * moxie.h (MOXIE_F1_M): Define.
1450 2009-04-15 Anthony Green <green@moxielogic.com>
1454 2009-04-06 DJ Delorie <dj@redhat.com>
1456 * h8300.h: Add relaxation attributes to MOVA opcodes.
1458 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1460 * ppc.h (ppc_parse_cpu): Declare.
1462 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1464 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1465 and _IMM11 for mbitclr and mbitset.
1466 * score-datadep.h: Update dependency information.
1468 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1470 * ppc.h (PPC_OPCODE_POWER7): New.
1472 2009-02-06 Doug Evans <dje@google.com>
1474 * i386.h: Add comment regarding sse* insns and prefixes.
1476 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1478 * mips.h (INSN_XLR): Define.
1479 (INSN_CHIP_MASK): Update.
1481 (OPCODE_IS_MEMBER): Update.
1482 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1484 2009-01-28 Doug Evans <dje@google.com>
1486 * opcode/i386.h: Add multiple inclusion protection.
1487 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1488 (EDI_REG_NUM): New macros.
1489 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1490 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1491 (REX_PREFIX_P): New macro.
1493 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1495 * ppc.h (struct powerpc_opcode): New field "deprecated".
1496 (PPC_OPCODE_NOPOWER4): Delete.
1498 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1500 * mips.h: Define CPU_R14000, CPU_R16000.
1501 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1503 2008-11-18 Catherine Moore <clm@codesourcery.com>
1505 * arm.h (FPU_NEON_FP16): New.
1506 (FPU_ARCH_NEON_FP16): New.
1508 2008-11-06 Chao-ying Fu <fu@mips.com>
1510 * mips.h: Doucument '1' for 5-bit sync type.
1512 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1514 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1517 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1519 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1521 2008-07-30 Michael J. Eager <eager@eagercon.com>
1523 * ppc.h (PPC_OPCODE_405): Define.
1524 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1526 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1528 * ppc.h (ppc_cpu_t): New typedef.
1529 (struct powerpc_opcode <flags>): Use it.
1530 (struct powerpc_operand <insert, extract>): Likewise.
1531 (struct powerpc_macro <flags>): Likewise.
1533 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1535 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1536 Update comment before MIPS16 field descriptors to mention MIPS16.
1537 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1539 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1540 New bit masks and shift counts for cins and exts.
1542 * mips.h: Document new field descriptors +Q.
1543 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1545 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1547 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1548 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1550 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1552 * ppc.h: (PPC_OPCODE_E500MC): New.
1554 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1556 * i386.h (MAX_OPERANDS): Set to 5.
1557 (MAX_MNEM_SIZE): Changed to 20.
1559 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1561 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1563 2008-03-09 Paul Brook <paul@codesourcery.com>
1565 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1567 2008-03-04 Paul Brook <paul@codesourcery.com>
1569 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1570 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1571 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1573 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1574 Nick Clifton <nickc@redhat.com>
1577 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1578 with a 32-bit displacement but without the top bit of the 4th byte
1581 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1583 * cr16.h (cr16_num_optab): Declared.
1585 2008-02-14 Hakan Ardo <hakan@debian.org>
1588 * avr.h (AVR_ISA_2xxe): Define.
1590 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1592 * mips.h: Update copyright.
1593 (INSN_CHIP_MASK): New macro.
1594 (INSN_OCTEON): New macro.
1595 (CPU_OCTEON): New macro.
1596 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1598 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1600 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1602 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1604 * avr.h (AVR_ISA_USB162): Add new opcode set.
1605 (AVR_ISA_AVR3): Likewise.
1607 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1609 * mips.h (INSN_LOONGSON_2E): New.
1610 (INSN_LOONGSON_2F): New.
1611 (CPU_LOONGSON_2E): New.
1612 (CPU_LOONGSON_2F): New.
1613 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1615 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1617 * mips.h (INSN_ISA*): Redefine certain values as an
1618 enumeration. Update comments.
1619 (mips_isa_table): New.
1620 (ISA_MIPS*): Redefine to match enumeration.
1621 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1624 2007-08-08 Ben Elliston <bje@au.ibm.com>
1626 * ppc.h (PPC_OPCODE_PPCPS): New.
1628 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1630 * m68k.h: Document j K & E.
1632 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1634 * cr16.h: New file for CR16 target.
1636 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1638 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1640 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1642 * m68k.h (mcfisa_c): New.
1643 (mcfusp, mcf_mask): Adjust.
1645 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1647 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1648 (num_powerpc_operands): Declare.
1649 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1650 (PPC_OPERAND_PLUS1): Define.
1652 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1654 * i386.h (REX_MODE64): Renamed to ...
1656 (REX_EXTX): Renamed to ...
1658 (REX_EXTY): Renamed to ...
1660 (REX_EXTZ): Renamed to ...
1663 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1665 * i386.h: Add entries from config/tc-i386.h and move tables
1666 to opcodes/i386-opc.h.
1668 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1670 * i386.h (FloatDR): Removed.
1671 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1673 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1675 * spu-insns.h: Add soma double-float insns.
1677 2007-02-20 Thiemo Seufer <ths@mips.com>
1678 Chao-Ying Fu <fu@mips.com>
1680 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1681 (INSN_DSPR2): Add flag for DSP R2 instructions.
1682 (M_BALIGN): New macro.
1684 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1686 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1687 and Seg3ShortFrom with Shortform.
1689 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1692 * i386.h (i386_optab): Put the real "test" before the pseudo
1695 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1697 * m68k.h (m68010up): OR fido_a.
1699 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1701 * m68k.h (fido_a): New.
1703 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1705 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1706 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1709 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1711 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1713 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1715 * score-inst.h (enum score_insn_type): Add Insn_internal.
1717 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1718 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1719 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1720 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1721 Alan Modra <amodra@bigpond.net.au>
1723 * spu-insns.h: New file.
1726 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1728 * ppc.h (PPC_OPCODE_CELL): Define.
1730 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1732 * i386.h : Modify opcode to support for the change in POPCNT opcode
1733 in amdfam10 architecture.
1735 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1737 * i386.h: Replace CpuMNI with CpuSSSE3.
1739 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1740 Joseph Myers <joseph@codesourcery.com>
1741 Ian Lance Taylor <ian@wasabisystems.com>
1742 Ben Elliston <bje@wasabisystems.com>
1744 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1746 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1748 * score-datadep.h: New file.
1749 * score-inst.h: New file.
1751 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1753 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1754 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1755 movdq2q and movq2dq.
1757 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1758 Michael Meissner <michael.meissner@amd.com>
1760 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1762 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1764 * i386.h (i386_optab): Add "nop" with memory reference.
1766 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1768 * i386.h (i386_optab): Update comment for 64bit NOP.
1770 2006-06-06 Ben Elliston <bje@au.ibm.com>
1771 Anton Blanchard <anton@samba.org>
1773 * ppc.h (PPC_OPCODE_POWER6): Define.
1776 2006-06-05 Thiemo Seufer <ths@mips.com>
1778 * mips.h: Improve description of MT flags.
1780 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1782 * m68k.h (mcf_mask): Define.
1784 2006-05-05 Thiemo Seufer <ths@mips.com>
1785 David Ung <davidu@mips.com>
1787 * mips.h (enum): Add macro M_CACHE_AB.
1789 2006-05-04 Thiemo Seufer <ths@mips.com>
1790 Nigel Stephens <nigel@mips.com>
1791 David Ung <davidu@mips.com>
1793 * mips.h: Add INSN_SMARTMIPS define.
1795 2006-04-30 Thiemo Seufer <ths@mips.com>
1796 David Ung <davidu@mips.com>
1798 * mips.h: Defines udi bits and masks. Add description of
1799 characters which may appear in the args field of udi
1802 2006-04-26 Thiemo Seufer <ths@networkno.de>
1804 * mips.h: Improve comments describing the bitfield instruction
1807 2006-04-26 Julian Brown <julian@codesourcery.com>
1809 * arm.h (FPU_VFP_EXT_V3): Define constant.
1810 (FPU_NEON_EXT_V1): Likewise.
1811 (FPU_VFP_HARD): Update.
1812 (FPU_VFP_V3): Define macro.
1813 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1815 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1817 * avr.h (AVR_ISA_PWMx): New.
1819 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1821 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1822 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1823 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1824 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1825 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1827 2006-03-10 Paul Brook <paul@codesourcery.com>
1829 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1831 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1833 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1834 first. Correct mask of bb "B" opcode.
1836 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1838 * i386.h (i386_optab): Support Intel Merom New Instructions.
1840 2006-02-24 Paul Brook <paul@codesourcery.com>
1842 * arm.h: Add V7 feature bits.
1844 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1846 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1848 2006-01-31 Paul Brook <paul@codesourcery.com>
1849 Richard Earnshaw <rearnsha@arm.com>
1851 * arm.h: Use ARM_CPU_FEATURE.
1852 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1853 (arm_feature_set): Change to a structure.
1854 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1855 ARM_FEATURE): New macros.
1857 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1859 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1860 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1861 (ADD_PC_INCR_OPCODE): Don't define.
1863 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1866 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1868 2005-11-14 David Ung <davidu@mips.com>
1870 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1871 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1872 save/restore encoding of the args field.
1874 2005-10-28 Dave Brolley <brolley@redhat.com>
1876 Contribute the following changes:
1877 2005-02-16 Dave Brolley <brolley@redhat.com>
1879 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1880 cgen_isa_mask_* to cgen_bitset_*.
1883 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1885 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1886 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1887 (CGEN_CPU_TABLE): Make isas a ponter.
1889 2003-09-29 Dave Brolley <brolley@redhat.com>
1891 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1892 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1893 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1895 2002-12-13 Dave Brolley <brolley@redhat.com>
1897 * cgen.h (symcat.h): #include it.
1898 (cgen-bitset.h): #include it.
1899 (CGEN_ATTR_VALUE_TYPE): Now a union.
1900 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1901 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1902 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1903 * cgen-bitset.h: New file.
1905 2005-09-30 Catherine Moore <clm@cm00re.com>
1909 2005-10-24 Jan Beulich <jbeulich@novell.com>
1911 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1914 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1916 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1917 Add FLAG_STRICT to pa10 ftest opcode.
1919 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1921 * hppa.h (pa_opcodes): Remove lha entries.
1923 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1925 * hppa.h (FLAG_STRICT): Revise comment.
1926 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1927 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1930 2005-09-30 Catherine Moore <clm@cm00re.com>
1934 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1936 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1938 2005-09-06 Chao-ying Fu <fu@mips.com>
1940 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1941 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1943 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1944 (INSN_ASE_MASK): Update to include INSN_MT.
1945 (INSN_MT): New define for MT ASE.
1947 2005-08-25 Chao-ying Fu <fu@mips.com>
1949 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1950 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1951 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1952 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1953 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1954 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1956 (INSN_DSP): New define for DSP ASE.
1958 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1962 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1964 * ppc.h (PPC_OPCODE_E300): Define.
1966 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1968 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1970 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1973 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1976 2005-07-27 Jan Beulich <jbeulich@novell.com>
1978 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1979 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1980 Add movq-s as 64-bit variants of movd-s.
1982 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1984 * hppa.h: Fix punctuation in comment.
1986 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1987 implicit space-register addressing. Set space-register bits on opcodes
1988 using implicit space-register addressing. Add various missing pa20
1989 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1990 space-register addressing. Use "fE" instead of "fe" in various
1993 2005-07-18 Jan Beulich <jbeulich@novell.com>
1995 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1997 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1999 * i386.h (i386_optab): Support Intel VMX Instructions.
2001 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2003 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2005 2005-07-05 Jan Beulich <jbeulich@novell.com>
2007 * i386.h (i386_optab): Add new insns.
2009 2005-07-01 Nick Clifton <nickc@redhat.com>
2011 * sparc.h: Add typedefs to structure declarations.
2013 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2016 * i386.h (i386_optab): Update comments for 64bit addressing on
2017 mov. Allow 64bit addressing for mov and movq.
2019 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2021 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2022 respectively, in various floating-point load and store patterns.
2024 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2026 * hppa.h (FLAG_STRICT): Correct comment.
2027 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2028 PA 2.0 mneumonics when equivalent. Entries with cache control
2029 completers now require PA 1.1. Adjust whitespace.
2031 2005-05-19 Anton Blanchard <anton@samba.org>
2033 * ppc.h (PPC_OPCODE_POWER5): Define.
2035 2005-05-10 Nick Clifton <nickc@redhat.com>
2037 * Update the address and phone number of the FSF organization in
2038 the GPL notices in the following files:
2039 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2040 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2041 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2042 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2043 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2044 tic54x.h, tic80.h, v850.h, vax.h
2046 2005-05-09 Jan Beulich <jbeulich@novell.com>
2048 * i386.h (i386_optab): Add ht and hnt.
2050 2005-04-18 Mark Kettenis <kettenis@gnu.org>
2052 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2053 Add xcrypt-ctr. Provide aliases without hyphens.
2055 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2057 Moved from ../ChangeLog
2059 2005-04-12 Paul Brook <paul@codesourcery.com>
2060 * m88k.h: Rename psr macros to avoid conflicts.
2062 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2063 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2064 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2065 and ARM_ARCH_V6ZKT2.
2067 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2068 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2069 Remove redundant instruction types.
2070 (struct argument): X_op - new field.
2071 (struct cst4_entry): Remove.
2072 (no_op_insn): Declare.
2074 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2075 * crx.h (enum argtype): Rename types, remove unused types.
2077 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2078 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2079 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2080 (enum operand_type): Rearrange operands, edit comments.
2081 replace us<N> with ui<N> for unsigned immediate.
2082 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2083 displacements (respectively).
2084 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2085 (instruction type): Add NO_TYPE_INS.
2086 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2087 (operand_entry): New field - 'flags'.
2088 (operand flags): New.
2090 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2091 * crx.h (operand_type): Remove redundant types i3, i4,
2093 Add new unsigned immediate types us3, us4, us5, us16.
2095 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2097 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2098 adjust them accordingly.
2100 2005-04-01 Jan Beulich <jbeulich@novell.com>
2102 * i386.h (i386_optab): Add rdtscp.
2104 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2106 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2107 between memory and segment register. Allow movq for moving between
2108 general-purpose register and segment register.
2110 2005-02-09 Jan Beulich <jbeulich@novell.com>
2113 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2114 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2117 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2119 * m68k.h (m68008, m68ec030, m68882): Remove.
2121 (cpu_m68k, cpu_cf): New.
2122 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2123 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2125 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2127 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2128 * cgen.h (enum cgen_parse_operand_type): Add
2129 CGEN_PARSE_OPERAND_SYMBOLIC.
2131 2005-01-21 Fred Fish <fnf@specifixinc.com>
2133 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2134 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2135 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2137 2005-01-19 Fred Fish <fnf@specifixinc.com>
2139 * mips.h (struct mips_opcode): Add new pinfo2 member.
2140 (INSN_ALIAS): New define for opcode table entries that are
2141 specific instances of another entry, such as 'move' for an 'or'
2142 with a zero operand.
2143 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2144 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2146 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2148 * mips.h (CPU_RM9000): Define.
2149 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2151 2004-11-25 Jan Beulich <jbeulich@novell.com>
2153 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2154 to/from test registers are illegal in 64-bit mode. Add missing
2155 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2156 (previously one had to explicitly encode a rex64 prefix). Re-enable
2157 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2158 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2160 2004-11-23 Jan Beulich <jbeulich@novell.com>
2162 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2163 available only with SSE2. Change the MMX additions introduced by SSE
2164 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2165 instructions by their now designated identifier (since combining i686
2166 and 3DNow! does not really imply 3DNow!A).
2168 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2170 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2171 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2173 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2174 Vineet Sharma <vineets@noida.hcltech.com>
2176 * maxq.h: New file: Disassembly information for the maxq port.
2178 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2180 * i386.h (i386_optab): Put back "movzb".
2182 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2184 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2185 comments. Remove member cris_ver_sim. Add members
2186 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2187 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2188 (struct cris_support_reg, struct cris_cond15): New types.
2189 (cris_conds15): Declare.
2190 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2191 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2192 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2193 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2194 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2195 SIZE_FIELD_UNSIGNED.
2197 2004-11-04 Jan Beulich <jbeulich@novell.com>
2199 * i386.h (sldx_Suf): Remove.
2200 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2201 (q_FP): Define, implying no REX64.
2202 (x_FP, sl_FP): Imply FloatMF.
2203 (i386_optab): Split reg and mem forms of moving from segment registers
2204 so that the memory forms can ignore the 16-/32-bit operand size
2205 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2206 all non-floating-point instructions. Unite 32- and 64-bit forms of
2207 movsx, movzx, and movd. Adjust floating point operations for the above
2208 changes to the *FP macros. Add DefaultSize to floating point control
2209 insns operating on larger memory ranges. Remove left over comments
2210 hinting at certain insns being Intel-syntax ones where the ones
2211 actually meant are already gone.
2213 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2215 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2218 2004-09-30 Paul Brook <paul@codesourcery.com>
2220 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2221 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2223 2004-09-11 Theodore A. Roth <troth@openavr.org>
2225 * avr.h: Add support for
2226 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2228 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2230 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2232 2004-08-24 Dmitry Diky <diwil@spec.ru>
2234 * msp430.h (msp430_opc): Add new instructions.
2235 (msp430_rcodes): Declare new instructions.
2236 (msp430_hcodes): Likewise..
2238 2004-08-13 Nick Clifton <nickc@redhat.com>
2241 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2244 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2246 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2248 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2250 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2252 2004-07-21 Jan Beulich <jbeulich@novell.com>
2254 * i386.h: Adjust instruction descriptions to better match the
2257 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2259 * arm.h: Remove all old content. Replace with architecture defines
2260 from gas/config/tc-arm.c.
2262 2004-07-09 Andreas Schwab <schwab@suse.de>
2264 * m68k.h: Fix comment.
2266 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2270 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2272 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2274 2004-05-24 Peter Barada <peter@the-baradas.com>
2276 * m68k.h: Add 'size' to m68k_opcode.
2278 2004-05-05 Peter Barada <peter@the-baradas.com>
2280 * m68k.h: Switch from ColdFire chip name to core variant.
2282 2004-04-22 Peter Barada <peter@the-baradas.com>
2284 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2285 descriptions for new EMAC cases.
2286 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2287 handle Motorola MAC syntax.
2288 Allow disassembly of ColdFire V4e object files.
2290 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2292 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2294 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2296 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2298 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2300 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2302 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2304 * i386.h (i386_optab): Added xstore/xcrypt insns.
2306 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2308 * h8300.h (32bit ldc/stc): Add relaxing support.
2310 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2312 * h8300.h (BITOP): Pass MEMRELAX flag.
2314 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2316 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2319 For older changes see ChangeLog-9103
2321 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2323 Copying and distribution of this file, with or without modification,
2324 are permitted in any medium without royalty provided the copyright
2325 notice and this notice are preserved.
2331 version-control: never
projects / external / binutils.git / blob