1 2006-02-24 Paul Brook <paul@codesourcery.com>
3 * arm.h: Add V7 feature bits.
5 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
7 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
9 2006-01-31 Paul Brook <paul@codesourcery.com>
10 Richard Earnshaw <rearnsha@arm.com>
12 * arm.h: Use ARM_CPU_FEATURE.
13 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
14 (arm_feature_set): Change to a structure.
15 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
16 ARM_FEATURE): New macros.
18 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
20 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
21 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
22 (ADD_PC_INCR_OPCODE): Don't define.
24 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
27 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
29 2005-11-14 David Ung <davidu@mips.com>
31 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
32 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
33 save/restore encoding of the args field.
35 2005-10-28 Dave Brolley <brolley@redhat.com>
37 Contribute the following changes:
38 2005-02-16 Dave Brolley <brolley@redhat.com>
40 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
41 cgen_isa_mask_* to cgen_bitset_*.
44 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
46 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
47 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
48 (CGEN_CPU_TABLE): Make isas a ponter.
50 2003-09-29 Dave Brolley <brolley@redhat.com>
52 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
53 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
54 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
56 2002-12-13 Dave Brolley <brolley@redhat.com>
58 * cgen.h (symcat.h): #include it.
59 (cgen-bitset.h): #include it.
60 (CGEN_ATTR_VALUE_TYPE): Now a union.
61 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
62 (CGEN_ATTR_ENTRY): 'value' now unsigned.
63 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
64 * cgen-bitset.h: New file.
66 2005-09-30 Catherine Moore <clm@cm00re.com>
70 2005-10-24 Jan Beulich <jbeulich@novell.com>
72 * ia64.h (enum ia64_opnd): Move memory operand out of set of
75 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
77 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
78 Add FLAG_STRICT to pa10 ftest opcode.
80 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
82 * hppa.h (pa_opcodes): Remove lha entries.
84 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
86 * hppa.h (FLAG_STRICT): Revise comment.
87 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
88 before corresponding pa11 opcodes. Add strict pa10 register-immediate
91 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
93 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
95 2005-09-06 Chao-ying Fu <fu@mips.com>
97 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
98 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
100 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
101 (INSN_ASE_MASK): Update to include INSN_MT.
102 (INSN_MT): New define for MT ASE.
104 2005-08-25 Chao-ying Fu <fu@mips.com>
106 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
107 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
108 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
109 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
110 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
111 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
113 (INSN_DSP): New define for DSP ASE.
115 2005-08-18 Alan Modra <amodra@bigpond.net.au>
119 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
121 * ppc.h (PPC_OPCODE_E300): Define.
123 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
125 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
127 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
130 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
133 2005-07-27 Jan Beulich <jbeulich@novell.com>
135 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
136 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
137 Add movq-s as 64-bit variants of movd-s.
139 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
141 * hppa.h: Fix punctuation in comment.
143 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
144 implicit space-register addressing. Set space-register bits on opcodes
145 using implicit space-register addressing. Add various missing pa20
146 long-immediate opcodes. Remove various opcodes using implicit 3-bit
147 space-register addressing. Use "fE" instead of "fe" in various
150 2005-07-18 Jan Beulich <jbeulich@novell.com>
152 * i386.h (i386_optab): Operands of aam and aad are unsigned.
154 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
156 * i386.h (i386_optab): Support Intel VMX Instructions.
158 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
160 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
162 2005-07-05 Jan Beulich <jbeulich@novell.com>
164 * i386.h (i386_optab): Add new insns.
166 2005-07-01 Nick Clifton <nickc@redhat.com>
168 * sparc.h: Add typedefs to structure declarations.
170 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
173 * i386.h (i386_optab): Update comments for 64bit addressing on
174 mov. Allow 64bit addressing for mov and movq.
176 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
178 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
179 respectively, in various floating-point load and store patterns.
181 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
183 * hppa.h (FLAG_STRICT): Correct comment.
184 (pa_opcodes): Update load and store entries to allow both PA 1.X and
185 PA 2.0 mneumonics when equivalent. Entries with cache control
186 completers now require PA 1.1. Adjust whitespace.
188 2005-05-19 Anton Blanchard <anton@samba.org>
190 * ppc.h (PPC_OPCODE_POWER5): Define.
192 2005-05-10 Nick Clifton <nickc@redhat.com>
194 * Update the address and phone number of the FSF organization in
195 the GPL notices in the following files:
196 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
197 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
198 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
199 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
200 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
201 tic54x.h, tic80.h, v850.h, vax.h
203 2005-05-09 Jan Beulich <jbeulich@novell.com>
205 * i386.h (i386_optab): Add ht and hnt.
207 2005-04-18 Mark Kettenis <kettenis@gnu.org>
209 * i386.h: Insert hyphens into selected VIA PadLock extensions.
210 Add xcrypt-ctr. Provide aliases without hyphens.
212 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
214 Moved from ../ChangeLog
216 2005-04-12 Paul Brook <paul@codesourcery.com>
217 * m88k.h: Rename psr macros to avoid conflicts.
219 2005-03-12 Zack Weinberg <zack@codesourcery.com>
220 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
221 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
224 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
225 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
226 Remove redundant instruction types.
227 (struct argument): X_op - new field.
228 (struct cst4_entry): Remove.
229 (no_op_insn): Declare.
231 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
232 * crx.h (enum argtype): Rename types, remove unused types.
234 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
235 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
236 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
237 (enum operand_type): Rearrange operands, edit comments.
238 replace us<N> with ui<N> for unsigned immediate.
239 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
240 displacements (respectively).
241 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
242 (instruction type): Add NO_TYPE_INS.
243 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
244 (operand_entry): New field - 'flags'.
245 (operand flags): New.
247 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
248 * crx.h (operand_type): Remove redundant types i3, i4,
250 Add new unsigned immediate types us3, us4, us5, us16.
252 2005-04-12 Mark Kettenis <kettenis@gnu.org>
254 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
255 adjust them accordingly.
257 2005-04-01 Jan Beulich <jbeulich@novell.com>
259 * i386.h (i386_optab): Add rdtscp.
261 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
263 * i386.h (i386_optab): Don't allow the `l' suffix for moving
264 between memory and segment register. Allow movq for moving between
265 general-purpose register and segment register.
267 2005-02-09 Jan Beulich <jbeulich@novell.com>
270 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
271 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
274 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
276 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
277 * cgen.h (enum cgen_parse_operand_type): Add
278 CGEN_PARSE_OPERAND_SYMBOLIC.
280 2005-01-21 Fred Fish <fnf@specifixinc.com>
282 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
283 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
284 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
286 2005-01-19 Fred Fish <fnf@specifixinc.com>
288 * mips.h (struct mips_opcode): Add new pinfo2 member.
289 (INSN_ALIAS): New define for opcode table entries that are
290 specific instances of another entry, such as 'move' for an 'or'
292 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
293 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
295 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
297 * mips.h (CPU_RM9000): Define.
298 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
300 2004-11-25 Jan Beulich <jbeulich@novell.com>
302 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
303 to/from test registers are illegal in 64-bit mode. Add missing
304 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
305 (previously one had to explicitly encode a rex64 prefix). Re-enable
306 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
307 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
309 2004-11-23 Jan Beulich <jbeulich@novell.com>
311 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
312 available only with SSE2. Change the MMX additions introduced by SSE
313 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
314 instructions by their now designated identifier (since combining i686
315 and 3DNow! does not really imply 3DNow!A).
317 2004-11-19 Alan Modra <amodra@bigpond.net.au>
319 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
320 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
322 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
323 Vineet Sharma <vineets@noida.hcltech.com>
325 * maxq.h: New file: Disassembly information for the maxq port.
327 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
329 * i386.h (i386_optab): Put back "movzb".
331 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
333 * cris.h (enum cris_insn_version_usage): Tweak formatting and
334 comments. Remove member cris_ver_sim. Add members
335 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
336 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
337 (struct cris_support_reg, struct cris_cond15): New types.
338 (cris_conds15): Declare.
339 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
340 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
341 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
342 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
343 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
346 2004-11-04 Jan Beulich <jbeulich@novell.com>
348 * i386.h (sldx_Suf): Remove.
349 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
350 (q_FP): Define, implying no REX64.
351 (x_FP, sl_FP): Imply FloatMF.
352 (i386_optab): Split reg and mem forms of moving from segment registers
353 so that the memory forms can ignore the 16-/32-bit operand size
354 distinction. Adjust a few others for Intel mode. Remove *FP uses from
355 all non-floating-point instructions. Unite 32- and 64-bit forms of
356 movsx, movzx, and movd. Adjust floating point operations for the above
357 changes to the *FP macros. Add DefaultSize to floating point control
358 insns operating on larger memory ranges. Remove left over comments
359 hinting at certain insns being Intel-syntax ones where the ones
360 actually meant are already gone.
362 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
364 * crx.h: Add COPS_REG_INS - Coprocessor Special register
367 2004-09-30 Paul Brook <paul@codesourcery.com>
369 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
370 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
372 2004-09-11 Theodore A. Roth <troth@openavr.org>
374 * avr.h: Add support for
375 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
377 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
379 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
381 2004-08-24 Dmitry Diky <diwil@spec.ru>
383 * msp430.h (msp430_opc): Add new instructions.
384 (msp430_rcodes): Declare new instructions.
385 (msp430_hcodes): Likewise..
387 2004-08-13 Nick Clifton <nickc@redhat.com>
390 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
393 2004-08-30 Michal Ludvig <mludvig@suse.cz>
395 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
397 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
399 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
401 2004-07-21 Jan Beulich <jbeulich@novell.com>
403 * i386.h: Adjust instruction descriptions to better match the
406 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
408 * arm.h: Remove all old content. Replace with architecture defines
409 from gas/config/tc-arm.c.
411 2004-07-09 Andreas Schwab <schwab@suse.de>
413 * m68k.h: Fix comment.
415 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
419 2004-06-24 Alan Modra <amodra@bigpond.net.au>
421 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
423 2004-05-24 Peter Barada <peter@the-baradas.com>
425 * m68k.h: Add 'size' to m68k_opcode.
427 2004-05-05 Peter Barada <peter@the-baradas.com>
429 * m68k.h: Switch from ColdFire chip name to core variant.
431 2004-04-22 Peter Barada <peter@the-baradas.com>
433 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
434 descriptions for new EMAC cases.
435 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
436 handle Motorola MAC syntax.
437 Allow disassembly of ColdFire V4e object files.
439 2004-03-16 Alan Modra <amodra@bigpond.net.au>
441 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
443 2004-03-12 Jakub Jelinek <jakub@redhat.com>
445 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
447 2004-03-12 Michal Ludvig <mludvig@suse.cz>
449 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
451 2004-03-12 Michal Ludvig <mludvig@suse.cz>
453 * i386.h (i386_optab): Added xstore/xcrypt insns.
455 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
457 * h8300.h (32bit ldc/stc): Add relaxing support.
459 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
461 * h8300.h (BITOP): Pass MEMRELAX flag.
463 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
465 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
468 For older changes see ChangeLog-9103
474 version-control: never