1 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64.h (AARCH64_FEATURE_PAN): New.
4 (aarch64_sys_reg_supported_p): Declare.
5 (aarch64_pstatefield_supported_p): Declare.
7 2015-04-30 DJ Delorie <dj@redhat.com>
9 * rl78.h (RL78_Dis_Isa): New.
10 (rl78_decode_opcode): Add ISA parameter.
12 2015-03-24 Terry Guo <terry.guo@arm.com>
14 * arm.h (arm_feature_set): Extended to provide more available bits.
15 (ARM_ANY): Updated to follow above new definition.
16 (ARM_CPU_HAS_FEATURE): Likewise.
17 (ARM_CPU_IS_ANY): Likewise.
18 (ARM_MERGE_FEATURE_SETS): Likewise.
19 (ARM_CLEAR_FEATURE): Likewise.
20 (ARM_FEATURE): Likewise.
21 (ARM_FEATURE_COPY): New macro.
22 (ARM_FEATURE_EQUAL): Likewise.
23 (ARM_FEATURE_ZERO): Likewise.
24 (ARM_FEATURE_CORE_EQUAL): Likewise.
25 (ARM_FEATURE_LOW): Likewise.
26 (ARM_FEATURE_CORE_LOW): Likewise.
27 (ARM_FEATURE_CORE_COPROC): Likewise.
29 2015-02-19 Pedro Alves <palves@redhat.com>
31 * cgen.h [__cplusplus]: Wrap in extern "C".
32 * msp430-decode.h [__cplusplus]: Likewise.
33 * nios2.h [__cplusplus]: Likewise.
34 * rl78.h [__cplusplus]: Likewise.
35 * rx.h [__cplusplus]: Likewise.
36 * tilegx.h [__cplusplus]: Likewise.
38 2015-01-28 James Bowman <james.bowman@ftdichip.com>
42 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
44 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
46 2015-01-01 Alan Modra <amodra@gmail.com>
48 Update year range in copyright notice of all files.
50 2014-12-27 Anthony Green <green@moxielogic.com>
52 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
53 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
55 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
59 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
61 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
62 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
63 (NIOS2_INSN_OPTARG): Renumber.
65 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
67 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
68 declaration. Fix obsolete comment.
70 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
72 * nios2.h (enum iw_format_type): New.
73 (struct nios2_opcode): Update comments. Add size and format fields.
74 (NIOS2_INSN_OPTARG): New.
75 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
76 (struct nios2_reg): Add regtype field.
77 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
78 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
79 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
80 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
81 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
82 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
83 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
84 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
85 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
86 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
87 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
88 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
89 (OP_MASK_OP, OP_SH_OP): Delete.
90 (OP_MASK_IOP, OP_SH_IOP): Delete.
91 (OP_MASK_IRD, OP_SH_IRD): Delete.
92 (OP_MASK_IRT, OP_SH_IRT): Delete.
93 (OP_MASK_IRS, OP_SH_IRS): Delete.
94 (OP_MASK_ROP, OP_SH_ROP): Delete.
95 (OP_MASK_RRD, OP_SH_RRD): Delete.
96 (OP_MASK_RRT, OP_SH_RRT): Delete.
97 (OP_MASK_RRS, OP_SH_RRS): Delete.
98 (OP_MASK_JOP, OP_SH_JOP): Delete.
99 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
100 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
101 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
102 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
103 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
104 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
105 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
106 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
107 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
108 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
109 (OP_MASK_<insn>, OP_MASK): Delete.
110 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
111 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
112 Include nios2r1.h to define new instruction opcode constants
114 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
115 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
116 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
117 (NUMOPCODES, NUMREGISTERS): Delete.
118 * nios2r1.h: New file.
120 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
122 * sparc.h (HWCAP2_VIS3B): Documentation improved.
124 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
126 * sparc.h (sparc_opcode): new field `hwcaps2'.
127 (HWCAP2_FJATHPLUS): New define.
128 (HWCAP2_VIS3B): Likewise.
129 (HWCAP2_ADP): Likewise.
130 (HWCAP2_SPARC5): Likewise.
131 (HWCAP2_MWAIT): Likewise.
132 (HWCAP2_XMPMUL): Likewise.
133 (HWCAP2_XMONT): Likewise.
134 (HWCAP2_NSEC): Likewise.
135 (HWCAP2_FJATHHPC): Likewise.
136 (HWCAP2_FJDES): Likewise.
137 (HWCAP2_FJAES): Likewise.
138 Document the new operand kind `{', corresponding to the mcdper
139 ancillary state register.
140 Document the new operand kind }, which represents frsd floating
141 point registers (double precision) which must be the same than
142 frs1 in its containing instruction.
144 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
146 * nds32.h: Add new opcode declaration.
148 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
149 Matthew Fortune <matthew.fortune@imgtec.com>
151 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
152 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
153 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
154 +I, +O, +R, +:, +\, +", +;
155 (mips_check_prev_operand): New struct.
156 (INSN2_FORBIDDEN_SLOT): New define.
157 (INSN_ISA32R6): New define.
158 (INSN_ISA64R6): New define.
159 (INSN_UPTO32R6): New define.
160 (INSN_UPTO64R6): New define.
161 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
162 (ISA_MIPS32R6): New define.
163 (ISA_MIPS64R6): New define.
164 (CPU_MIPS32R6): New define.
165 (CPU_MIPS64R6): New define.
166 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
168 2014-09-03 Jiong Wang <jiong.wang@arm.com>
170 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
171 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
172 (aarch64_insn_class): Add lse_atomic.
173 (F_LSE_SZ): New field added.
174 (opcode_has_special_coder): Recognize F_LSE_SZ.
176 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
178 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
181 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
183 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
184 (INSN_LOAD_COPROC): New define.
185 (INSN_COPROC_MOVE_DELAY): Rename to...
186 (INSN_COPROC_MOVE): New define.
188 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
189 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
190 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
191 Soundararajan <Sounderarajan.D@atmel.com>
193 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
194 (AVR_ISA_2xxxa): Define ISA without LPM.
195 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
196 Add doc for contraint used in 16 bit lds/sts.
197 Adjust ISA group for icall, ijmp, pop and push.
198 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
200 2014-05-19 Nick Clifton <nickc@redhat.com>
202 * msp430.h (struct msp430_operand_s): Add vshift field.
204 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
206 * mips.h (INSN_ISA_MASK): Updated.
207 (INSN_ISA32R3): New define.
208 (INSN_ISA32R5): New define.
209 (INSN_ISA64R3): New define.
210 (INSN_ISA64R5): New define.
211 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
212 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
213 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
215 (INSN_UPTO32R3): New define.
216 (INSN_UPTO32R5): New define.
217 (INSN_UPTO64R3): New define.
218 (INSN_UPTO64R5): New define.
219 (ISA_MIPS32R3): New define.
220 (ISA_MIPS32R5): New define.
221 (ISA_MIPS64R3): New define.
222 (ISA_MIPS64R5): New define.
223 (CPU_MIPS32R3): New define.
224 (CPU_MIPS32R5): New define.
225 (CPU_MIPS64R3): New define.
226 (CPU_MIPS64R5): New define.
228 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
230 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
232 2014-04-22 Christian Svensson <blue@cmd.nu>
236 2014-03-05 Alan Modra <amodra@gmail.com>
238 Update copyright years.
240 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
242 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
245 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
246 Wei-Cheng Wang <cole945@gmail.com>
248 * nds32.h: New file for Andes NDS32.
250 2013-12-07 Mike Frysinger <vapier@gentoo.org>
252 * bfin.h: Remove +x file mode.
254 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
256 * aarch64.h (aarch64_pstatefields): Change element type to
259 2013-11-18 Renlin Li <Renlin.Li@arm.com>
261 * arm.h (ARM_AEXT_V7VE): New define.
262 (ARM_ARCH_V7VE): New define.
263 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
265 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
269 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
271 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
272 (aarch64_sys_reg_writeonly_p): Ditto.
274 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
276 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
277 (aarch64_sys_reg_writeonly_p): Ditto.
279 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
281 * aarch64.h (aarch64_sys_reg): New typedef.
282 (aarch64_sys_regs): Change to define with the new type.
283 (aarch64_sys_reg_deprecated_p): Declare.
285 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
287 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
288 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
290 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
292 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
293 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
294 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
295 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
296 For MIPS, update extension character sequences after +.
297 (ASE_MSA): New define.
298 (ASE_MSA64): New define.
299 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
300 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
301 For microMIPS, update extension character sequences after +.
303 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
308 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
310 * mips.h: Remove references to "+I" and imm2_expr.
312 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
314 * mips.h (M_DEXT, M_DINS): Delete.
316 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
318 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
319 (mips_optional_operand_p): New function.
321 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
322 Richard Sandiford <rdsandiford@googlemail.com>
324 * mips.h: Document new VU0 operand characters.
325 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
326 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
327 (OP_REG_R5900_ACC): New mips_reg_operand_types.
328 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
329 (mips_vu0_channel_mask): Declare.
331 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
333 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
334 (mips_int_operand_min, mips_int_operand_max): New functions.
335 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
337 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
339 * mips.h (mips_decode_reg_operand): New function.
340 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
341 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
342 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
344 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
345 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
346 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
347 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
348 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
349 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
350 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
351 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
352 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
353 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
354 macros to cover the gaps.
355 (INSN2_MOD_SP): Replace with...
356 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
357 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
358 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
359 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
360 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
363 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
365 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
366 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
367 (MIPS16_INSN_COND_BRANCH): Delete.
369 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
370 Kirill Yukhin <kirill.yukhin@intel.com>
371 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
373 * i386.h (BND_PREFIX_OPCODE): New.
375 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
377 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
378 OP_SAVE_RESTORE_LIST.
379 (decode_mips16_operand): Declare.
381 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
383 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
384 (mips_operand, mips_int_operand, mips_mapped_int_operand)
385 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
386 (mips_pcrel_operand): New structures.
387 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
388 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
389 (decode_mips_operand, decode_micromips_operand): Declare.
391 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
393 * mips.h: Document MIPS16 "I" opcode.
395 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
397 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
398 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
399 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
400 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
401 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
402 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
403 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
404 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
405 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
406 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
407 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
408 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
409 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
411 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
412 (M_USD_AB): ...these.
414 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
416 * mips.h: Remove documentation of "[" and "]". Update documentation
417 of "k" and the MDMX formats.
419 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
421 * mips.h: Update documentation of "+s" and "+S".
423 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
425 * mips.h: Document "+i".
427 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
429 * mips.h: Remove "mi" documentation. Update "mh" documentation.
430 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
432 (INSN2_WRITE_GPR_MHI): Rename to...
433 (INSN2_WRITE_GPR_MH): ...this.
435 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
437 * mips.h: Remove documentation of "+D" and "+T".
439 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
441 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
442 Use "source" rather than "destination" for microMIPS "G".
444 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
446 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
449 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
451 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
453 2013-06-17 Catherine Moore <clm@codesourcery.com>
454 Maciej W. Rozycki <macro@codesourcery.com>
455 Chao-Ying Fu <fu@mips.com>
457 * mips.h (OP_SH_EVAOFFSET): Define.
458 (OP_MASK_EVAOFFSET): Define.
459 (INSN_ASE_MASK): Delete.
461 (M_CACHEE_AB, M_CACHEE_OB): New.
462 (M_LBE_OB, M_LBE_AB): New.
463 (M_LBUE_OB, M_LBUE_AB): New.
464 (M_LHE_OB, M_LHE_AB): New.
465 (M_LHUE_OB, M_LHUE_AB): New.
466 (M_LLE_AB, M_LLE_OB): New.
467 (M_LWE_OB, M_LWE_AB): New.
468 (M_LWLE_AB, M_LWLE_OB): New.
469 (M_LWRE_AB, M_LWRE_OB): New.
470 (M_PREFE_AB, M_PREFE_OB): New.
471 (M_SCE_AB, M_SCE_OB): New.
472 (M_SBE_OB, M_SBE_AB): New.
473 (M_SHE_OB, M_SHE_AB): New.
474 (M_SWE_OB, M_SWE_AB): New.
475 (M_SWLE_AB, M_SWLE_OB): New.
476 (M_SWRE_AB, M_SWRE_OB): New.
477 (MICROMIPSOP_SH_EVAOFFSET): Define.
478 (MICROMIPSOP_MASK_EVAOFFSET): Define.
480 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
482 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
484 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
486 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
488 2013-05-09 Andrew Pinski <apinski@cavium.com>
490 * mips.h (OP_MASK_CODE10): Correct definition.
491 (OP_SH_CODE10): Likewise.
492 Add a comment that "+J" is used now for OP_*CODE10.
493 (INSN_ASE_MASK): Update.
494 (INSN_VIRT): New macro.
495 (INSN_VIRT64): New macro
497 2013-05-02 Nick Clifton <nickc@redhat.com>
499 * msp430.h: Add patterns for MSP430X instructions.
501 2013-04-06 David S. Miller <davem@davemloft.net>
503 * sparc.h (F_PREFERRED): Define.
504 (F_PREF_ALIAS): Define.
506 2013-04-03 Nick Clifton <nickc@redhat.com>
508 * v850.h (V850_INVERSE_PCREL): Define.
510 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
513 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
515 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
518 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
520 * tic6xc-opcode-table.h: Add 16-bit insns.
521 * tic6x.h: Add support for 16-bit insns.
523 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
525 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
526 and mov.b/w/l Rs,@(d:32,ERd).
528 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
531 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
532 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
533 tic6x_operand_xregpair operand coding type.
534 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
535 opcode field, usu ORXREGD1324 for the src2 operand and remove the
538 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
541 * tic6x.h (enum tic6x_coding_method): Add
542 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
543 separately the msb and lsb of a register pair. This is needed to
544 encode the opcodes in the same way as TI assembler does.
545 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
546 and rsqrdp opcodes to use the new field coding types.
548 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
550 * arm.h (CRC_EXT_ARMV8): New constant.
551 (ARCH_CRC_ARMV8): New macro.
553 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
555 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
557 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
558 Andrew Jenner <andrew@codesourcery.com>
560 Based on patches from Altera Corporation.
564 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
566 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
568 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
571 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
573 2013-01-24 Nick Clifton <nickc@redhat.com>
575 * v850.h: Add e3v5 support.
577 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
579 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
581 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
583 * ppc.h (PPC_OPCODE_POWER8): New define.
584 (PPC_OPCODE_HTM): Likewise.
586 2013-01-10 Will Newton <will.newton@imgtec.com>
590 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
592 * cr16.h (make_instruction): Rename to cr16_make_instruction.
593 (match_opcode): Rename to cr16_match_opcode.
595 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
597 * mips.h: Add support for r5900 instructions including lq and sq.
599 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
601 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
602 (make_instruction,match_opcode): Added function prototypes.
603 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
605 2012-11-23 Alan Modra <amodra@gmail.com>
607 * ppc.h (ppc_parse_cpu): Update prototype.
609 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
611 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
612 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
614 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
616 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
618 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
620 * ia64.h (ia64_opnd): Add new operand types.
622 2012-08-21 David S. Miller <davem@davemloft.net>
624 * sparc.h (F3F4): New macro.
626 2012-08-13 Ian Bolton <ian.bolton@arm.com>
627 Laurent Desnogues <laurent.desnogues@arm.com>
628 Jim MacArthur <jim.macarthur@arm.com>
629 Marcus Shawcroft <marcus.shawcroft@arm.com>
630 Nigel Stephens <nigel.stephens@arm.com>
631 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
632 Richard Earnshaw <rearnsha@arm.com>
633 Sofiane Naci <sofiane.naci@arm.com>
634 Tejas Belagod <tejas.belagod@arm.com>
635 Yufeng Zhang <yufeng.zhang@arm.com>
637 * aarch64.h: New file.
639 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
640 Maciej W. Rozycki <macro@codesourcery.com>
642 * mips.h (mips_opcode): Add the exclusions field.
643 (OPCODE_IS_MEMBER): Remove macro.
644 (cpu_is_member): New inline function.
645 (opcode_is_member): Likewise.
647 2012-07-31 Chao-Ying Fu <fu@mips.com>
648 Catherine Moore <clm@codesourcery.com>
649 Maciej W. Rozycki <macro@codesourcery.com>
651 * mips.h: Document microMIPS DSP ASE usage.
652 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
653 microMIPS DSP ASE support.
654 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
655 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
656 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
657 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
658 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
659 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
660 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
662 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
664 * mips.h: Fix a typo in description.
666 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
668 * avr.h: (AVR_ISA_XCH): New define.
669 (AVR_ISA_XMEGA): Use it.
670 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
672 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
674 * m68hc11.h: Add XGate definitions.
675 (struct m68hc11_opcode): Add xg_mask field.
677 2012-05-14 Catherine Moore <clm@codesourcery.com>
678 Maciej W. Rozycki <macro@codesourcery.com>
679 Rhonda Wittels <rhonda@codesourcery.com>
681 * ppc.h (PPC_OPCODE_VLE): New definition.
682 (PPC_OP_SA): New macro.
683 (PPC_OP_SE_VLE): New macro.
684 (PPC_OP): Use a variable shift amount.
685 (powerpc_operand): Update comments.
686 (PPC_OPSHIFT_INV): New macro.
687 (PPC_OPERAND_CR): Replace with...
688 (PPC_OPERAND_CR_BIT): ...this and
689 (PPC_OPERAND_CR_REG): ...this.
692 2012-05-03 Sean Keys <skeys@ipdatasys.com>
694 * xgate.h: Header file for XGATE assembler.
696 2012-04-27 David S. Miller <davem@davemloft.net>
698 * sparc.h: Document new arg code' )' for crypto RS3
701 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
702 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
703 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
704 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
705 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
706 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
707 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
708 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
709 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
710 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
711 HWCAP_CBCOND, HWCAP_CRC32): New defines.
713 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
715 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
717 2012-02-27 Alan Modra <amodra@gmail.com>
719 * crx.h (cst4_map): Update declaration.
721 2012-02-25 Walter Lee <walt@tilera.com>
723 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
725 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
726 TILEPRO_OPC_LW_TLS_SN.
728 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
730 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
731 (XRELEASE_PREFIX_OPCODE): Likewise.
733 2011-12-08 Andrew Pinski <apinski@cavium.com>
734 Adam Nemet <anemet@caviumnetworks.com>
736 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
737 (INSN_OCTEON2): New macro.
738 (CPU_OCTEON2): New macro.
739 (OPCODE_IS_MEMBER): Add Octeon2.
741 2011-11-29 Andrew Pinski <apinski@cavium.com>
743 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
744 (INSN_OCTEONP): New macro.
745 (CPU_OCTEONP): New macro.
746 (OPCODE_IS_MEMBER): Add Octeon+.
747 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
749 2011-11-01 DJ Delorie <dj@redhat.com>
753 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
755 * mips.h: Fix a typo in description.
757 2011-09-21 David S. Miller <davem@davemloft.net>
759 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
760 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
761 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
762 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
764 2011-08-09 Chao-ying Fu <fu@mips.com>
765 Maciej W. Rozycki <macro@codesourcery.com>
767 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
768 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
769 (INSN_ASE_MASK): Add the MCU bit.
770 (INSN_MCU): New macro.
771 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
772 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
774 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
776 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
777 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
778 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
779 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
780 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
781 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
782 (INSN2_READ_GPR_MMN): Likewise.
783 (INSN2_READ_FPR_D): Change the bit used.
784 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
785 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
786 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
787 (INSN2_COND_BRANCH): Likewise.
788 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
789 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
790 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
791 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
792 (INSN2_MOD_GPR_MN): Likewise.
794 2011-08-05 David S. Miller <davem@davemloft.net>
796 * sparc.h: Document new format codes '4', '5', and '('.
797 (OPF_LOW4, RS3): New macros.
799 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
801 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
802 order of flags documented.
804 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
806 * mips.h: Clarify the description of microMIPS instruction
808 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
810 2011-07-24 Chao-ying Fu <fu@mips.com>
811 Maciej W. Rozycki <macro@codesourcery.com>
813 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
814 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
815 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
816 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
817 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
818 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
819 (OP_MASK_RS3, OP_SH_RS3): Likewise.
820 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
821 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
822 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
823 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
824 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
825 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
826 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
827 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
828 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
829 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
830 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
831 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
832 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
833 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
834 (INSN_WRITE_GPR_S): New macro.
835 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
836 (INSN2_READ_FPR_D): Likewise.
837 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
838 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
839 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
840 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
841 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
842 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
843 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
844 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
845 (CPU_MICROMIPS): New macro.
846 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
847 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
848 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
849 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
850 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
851 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
852 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
853 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
854 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
855 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
856 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
857 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
858 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
859 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
860 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
861 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
862 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
863 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
864 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
865 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
866 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
867 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
868 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
869 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
870 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
871 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
872 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
873 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
874 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
875 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
876 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
877 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
878 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
879 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
880 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
881 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
882 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
883 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
884 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
885 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
886 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
887 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
888 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
889 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
890 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
891 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
892 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
893 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
894 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
895 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
896 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
897 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
898 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
899 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
900 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
901 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
902 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
903 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
904 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
905 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
906 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
907 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
908 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
909 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
910 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
911 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
912 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
913 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
914 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
915 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
916 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
917 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
918 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
919 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
920 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
921 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
922 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
923 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
924 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
925 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
926 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
927 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
928 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
929 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
930 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
931 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
932 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
933 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
934 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
935 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
936 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
937 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
938 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
939 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
940 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
941 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
942 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
943 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
944 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
945 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
946 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
947 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
948 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
949 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
950 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
951 (micromips_opcodes): New declaration.
952 (bfd_micromips_num_opcodes): Likewise.
954 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
956 * mips.h (INSN_TRAP): Rename to...
957 (INSN_NO_DELAY_SLOT): ... this.
958 (INSN_SYNC): Remove macro.
960 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
962 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
963 a duplicate of AVR_ISA_SPM.
965 2011-07-01 Nick Clifton <nickc@redhat.com>
967 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
969 2011-06-18 Robin Getz <robin.getz@analog.com>
971 * bfin.h (is_macmod_signed): New func
973 2011-06-18 Mike Frysinger <vapier@gentoo.org>
975 * bfin.h (is_macmod_pmove): Add missing space before func args.
976 (is_macmod_hmove): Likewise.
978 2011-06-13 Walter Lee <walt@tilera.com>
980 * tilegx.h: New file.
981 * tilepro.h: New file.
983 2011-05-31 Paul Brook <paul@codesourcery.com>
985 * arm.h (ARM_ARCH_V7R_IDIV): Define.
987 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
989 * s390.h: Replace S390_OPERAND_REG_EVEN with
990 S390_OPERAND_REG_PAIR.
992 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
994 * s390.h: Add S390_OPCODE_REG_EVEN flag.
996 2011-04-18 Julian Brown <julian@codesourcery.com>
998 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1000 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1003 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1005 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1007 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1008 New instruction set flags.
1009 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1011 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1013 * mips.h (M_PREF_AB): New enum value.
1015 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1017 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1019 (is_macmod_pmove, is_macmod_hmove): New functions.
1021 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1023 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1025 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1027 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1028 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1030 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1033 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1036 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1039 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1041 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1043 * mips.h: Update commentary after last commit.
1045 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1047 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1048 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1049 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1051 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1053 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1055 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1057 * mips.h: Fix previous commit.
1059 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1061 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1062 (INSN_LOONGSON_3A): Clear bit 31.
1064 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1067 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1068 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1069 (ARM_ARCH_V6M_ONLY): New define.
1071 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1073 * mips.h (INSN_LOONGSON_3A): Defined.
1074 (CPU_LOONGSON_3A): Defined.
1075 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1077 2010-10-09 Matt Rice <ratmice@gmail.com>
1079 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1080 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1082 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1084 * arm.h (ARM_EXT_VIRT): New define.
1085 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1086 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1089 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1091 * arm.h (ARM_AEXT_ADIV): New define.
1092 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1094 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1096 * arm.h (ARM_EXT_OS): New define.
1097 (ARM_AEXT_V6SM): Likewise.
1098 (ARM_ARCH_V6SM): Likewise.
1100 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1102 * arm.h (ARM_EXT_MP): Add.
1103 (ARM_ARCH_V7A_MP): Likewise.
1105 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1107 * bfin.h: Declare pseudoChr structs/defines.
1109 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1111 * bfin.h: Strip trailing whitespace.
1113 2010-07-29 DJ Delorie <dj@redhat.com>
1115 * rx.h (RX_Operand_Type): Add TwoReg.
1116 (RX_Opcode_ID): Remove ediv and ediv2.
1118 2010-07-27 DJ Delorie <dj@redhat.com>
1120 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1122 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1123 Ina Pandit <ina.pandit@kpitcummins.com>
1125 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1126 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1127 PROCESSOR_V850E2_ALL.
1128 Remove PROCESSOR_V850EA support.
1129 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1130 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1131 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1132 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1133 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1134 V850_OPERAND_PERCENT.
1135 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1137 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1140 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1142 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1143 (MIPS16_INSN_BRANCH): Rename to...
1144 (MIPS16_INSN_COND_BRANCH): ... this.
1146 2010-07-03 Alan Modra <amodra@gmail.com>
1148 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1149 Renumber other PPC_OPCODE defines.
1151 2010-07-03 Alan Modra <amodra@gmail.com>
1153 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1155 2010-06-29 Alan Modra <amodra@gmail.com>
1157 * maxq.h: Delete file.
1159 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1161 * ppc.h (PPC_OPCODE_E500): Define.
1163 2010-05-26 Catherine Moore <clm@codesourcery.com>
1165 * opcode/mips.h (INSN_MIPS16): Remove.
1167 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1169 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1171 2010-04-15 Nick Clifton <nickc@redhat.com>
1173 * alpha.h: Update copyright notice to use GPLv3.
1179 * convex.h: Likewise.
1186 * h8300.h: Likewise.
1193 * m68hc11.h: Likewise.
1199 * mn10200.h: Likewise.
1200 * mn10300.h: Likewise.
1201 * msp430.h: Likewise.
1203 * ns32k.h: Likewise.
1205 * pdp11.h: Likewise.
1212 * score-datadep.h: Likewise.
1213 * score-inst.h: Likewise.
1214 * sparc.h: Likewise.
1215 * spu-insns.h: Likewise.
1217 * tic30.h: Likewise.
1218 * tic4x.h: Likewise.
1219 * tic54x.h: Likewise.
1220 * tic80.h: Likewise.
1224 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1226 * tic6x-control-registers.h, tic6x-insn-formats.h,
1227 tic6x-opcode-table.h, tic6x.h: New.
1229 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1231 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1233 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1235 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1237 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1239 * ia64.h (ia64_find_opcode): Remove argument name.
1240 (ia64_find_next_opcode): Likewise.
1241 (ia64_dis_opcode): Likewise.
1242 (ia64_free_opcode): Likewise.
1243 (ia64_find_dependency): Likewise.
1245 2009-11-22 Doug Evans <dje@sebabeach.org>
1247 * cgen.h: Include bfd_stdint.h.
1248 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1250 2009-11-18 Paul Brook <paul@codesourcery.com>
1252 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1254 2009-11-17 Paul Brook <paul@codesourcery.com>
1255 Daniel Jacobowitz <dan@codesourcery.com>
1257 * arm.h (ARM_EXT_V6_DSP): Define.
1258 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1259 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1261 2009-11-04 DJ Delorie <dj@redhat.com>
1263 * rx.h (rx_decode_opcode) (mvtipl): Add.
1264 (mvtcp, mvfcp, opecp): Remove.
1266 2009-11-02 Paul Brook <paul@codesourcery.com>
1268 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1269 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1270 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1271 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1272 FPU_ARCH_NEON_VFP_V4): Define.
1274 2009-10-23 Doug Evans <dje@sebabeach.org>
1276 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1277 * cgen.h: Update. Improve multi-inclusion macro name.
1279 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1281 * ppc.h (PPC_OPCODE_476): Define.
1283 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1285 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1287 2009-09-29 DJ Delorie <dj@redhat.com>
1291 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1293 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1295 2009-09-21 Ben Elliston <bje@au.ibm.com>
1297 * ppc.h (PPC_OPCODE_PPCA2): New.
1299 2009-09-05 Martin Thuresson <martin@mtme.org>
1301 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1303 2009-08-29 Martin Thuresson <martin@mtme.org>
1305 * tic30.h (template): Rename type template to
1306 insn_template. Updated code to use new name.
1307 * tic54x.h (template): Rename type template to
1310 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1312 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1314 2009-06-11 Anthony Green <green@moxielogic.com>
1316 * moxie.h (MOXIE_F3_PCREL): Define.
1317 (moxie_form3_opc_info): Grow.
1319 2009-06-06 Anthony Green <green@moxielogic.com>
1321 * moxie.h (MOXIE_F1_M): Define.
1323 2009-04-15 Anthony Green <green@moxielogic.com>
1327 2009-04-06 DJ Delorie <dj@redhat.com>
1329 * h8300.h: Add relaxation attributes to MOVA opcodes.
1331 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1333 * ppc.h (ppc_parse_cpu): Declare.
1335 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1337 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1338 and _IMM11 for mbitclr and mbitset.
1339 * score-datadep.h: Update dependency information.
1341 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1343 * ppc.h (PPC_OPCODE_POWER7): New.
1345 2009-02-06 Doug Evans <dje@google.com>
1347 * i386.h: Add comment regarding sse* insns and prefixes.
1349 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1351 * mips.h (INSN_XLR): Define.
1352 (INSN_CHIP_MASK): Update.
1354 (OPCODE_IS_MEMBER): Update.
1355 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1357 2009-01-28 Doug Evans <dje@google.com>
1359 * opcode/i386.h: Add multiple inclusion protection.
1360 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1361 (EDI_REG_NUM): New macros.
1362 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1363 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1364 (REX_PREFIX_P): New macro.
1366 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1368 * ppc.h (struct powerpc_opcode): New field "deprecated".
1369 (PPC_OPCODE_NOPOWER4): Delete.
1371 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1373 * mips.h: Define CPU_R14000, CPU_R16000.
1374 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1376 2008-11-18 Catherine Moore <clm@codesourcery.com>
1378 * arm.h (FPU_NEON_FP16): New.
1379 (FPU_ARCH_NEON_FP16): New.
1381 2008-11-06 Chao-ying Fu <fu@mips.com>
1383 * mips.h: Doucument '1' for 5-bit sync type.
1385 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1387 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1390 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1392 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1394 2008-07-30 Michael J. Eager <eager@eagercon.com>
1396 * ppc.h (PPC_OPCODE_405): Define.
1397 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1399 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1401 * ppc.h (ppc_cpu_t): New typedef.
1402 (struct powerpc_opcode <flags>): Use it.
1403 (struct powerpc_operand <insert, extract>): Likewise.
1404 (struct powerpc_macro <flags>): Likewise.
1406 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1408 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1409 Update comment before MIPS16 field descriptors to mention MIPS16.
1410 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1412 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1413 New bit masks and shift counts for cins and exts.
1415 * mips.h: Document new field descriptors +Q.
1416 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1418 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1420 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1421 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1423 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1425 * ppc.h: (PPC_OPCODE_E500MC): New.
1427 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1429 * i386.h (MAX_OPERANDS): Set to 5.
1430 (MAX_MNEM_SIZE): Changed to 20.
1432 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1434 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1436 2008-03-09 Paul Brook <paul@codesourcery.com>
1438 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1440 2008-03-04 Paul Brook <paul@codesourcery.com>
1442 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1443 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1444 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1446 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1447 Nick Clifton <nickc@redhat.com>
1450 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1451 with a 32-bit displacement but without the top bit of the 4th byte
1454 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1456 * cr16.h (cr16_num_optab): Declared.
1458 2008-02-14 Hakan Ardo <hakan@debian.org>
1461 * avr.h (AVR_ISA_2xxe): Define.
1463 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1465 * mips.h: Update copyright.
1466 (INSN_CHIP_MASK): New macro.
1467 (INSN_OCTEON): New macro.
1468 (CPU_OCTEON): New macro.
1469 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1471 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1473 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1475 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1477 * avr.h (AVR_ISA_USB162): Add new opcode set.
1478 (AVR_ISA_AVR3): Likewise.
1480 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1482 * mips.h (INSN_LOONGSON_2E): New.
1483 (INSN_LOONGSON_2F): New.
1484 (CPU_LOONGSON_2E): New.
1485 (CPU_LOONGSON_2F): New.
1486 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1488 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1490 * mips.h (INSN_ISA*): Redefine certain values as an
1491 enumeration. Update comments.
1492 (mips_isa_table): New.
1493 (ISA_MIPS*): Redefine to match enumeration.
1494 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1497 2007-08-08 Ben Elliston <bje@au.ibm.com>
1499 * ppc.h (PPC_OPCODE_PPCPS): New.
1501 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1503 * m68k.h: Document j K & E.
1505 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1507 * cr16.h: New file for CR16 target.
1509 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1511 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1513 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1515 * m68k.h (mcfisa_c): New.
1516 (mcfusp, mcf_mask): Adjust.
1518 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1520 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1521 (num_powerpc_operands): Declare.
1522 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1523 (PPC_OPERAND_PLUS1): Define.
1525 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1527 * i386.h (REX_MODE64): Renamed to ...
1529 (REX_EXTX): Renamed to ...
1531 (REX_EXTY): Renamed to ...
1533 (REX_EXTZ): Renamed to ...
1536 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1538 * i386.h: Add entries from config/tc-i386.h and move tables
1539 to opcodes/i386-opc.h.
1541 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1543 * i386.h (FloatDR): Removed.
1544 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1546 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1548 * spu-insns.h: Add soma double-float insns.
1550 2007-02-20 Thiemo Seufer <ths@mips.com>
1551 Chao-Ying Fu <fu@mips.com>
1553 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1554 (INSN_DSPR2): Add flag for DSP R2 instructions.
1555 (M_BALIGN): New macro.
1557 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1559 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1560 and Seg3ShortFrom with Shortform.
1562 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1565 * i386.h (i386_optab): Put the real "test" before the pseudo
1568 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1570 * m68k.h (m68010up): OR fido_a.
1572 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1574 * m68k.h (fido_a): New.
1576 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1578 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1579 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1582 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1584 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1586 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1588 * score-inst.h (enum score_insn_type): Add Insn_internal.
1590 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1591 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1592 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1593 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1594 Alan Modra <amodra@bigpond.net.au>
1596 * spu-insns.h: New file.
1599 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1601 * ppc.h (PPC_OPCODE_CELL): Define.
1603 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1605 * i386.h : Modify opcode to support for the change in POPCNT opcode
1606 in amdfam10 architecture.
1608 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1610 * i386.h: Replace CpuMNI with CpuSSSE3.
1612 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1613 Joseph Myers <joseph@codesourcery.com>
1614 Ian Lance Taylor <ian@wasabisystems.com>
1615 Ben Elliston <bje@wasabisystems.com>
1617 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1619 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1621 * score-datadep.h: New file.
1622 * score-inst.h: New file.
1624 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1626 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1627 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1628 movdq2q and movq2dq.
1630 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1631 Michael Meissner <michael.meissner@amd.com>
1633 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1635 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1637 * i386.h (i386_optab): Add "nop" with memory reference.
1639 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1641 * i386.h (i386_optab): Update comment for 64bit NOP.
1643 2006-06-06 Ben Elliston <bje@au.ibm.com>
1644 Anton Blanchard <anton@samba.org>
1646 * ppc.h (PPC_OPCODE_POWER6): Define.
1649 2006-06-05 Thiemo Seufer <ths@mips.com>
1651 * mips.h: Improve description of MT flags.
1653 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1655 * m68k.h (mcf_mask): Define.
1657 2006-05-05 Thiemo Seufer <ths@mips.com>
1658 David Ung <davidu@mips.com>
1660 * mips.h (enum): Add macro M_CACHE_AB.
1662 2006-05-04 Thiemo Seufer <ths@mips.com>
1663 Nigel Stephens <nigel@mips.com>
1664 David Ung <davidu@mips.com>
1666 * mips.h: Add INSN_SMARTMIPS define.
1668 2006-04-30 Thiemo Seufer <ths@mips.com>
1669 David Ung <davidu@mips.com>
1671 * mips.h: Defines udi bits and masks. Add description of
1672 characters which may appear in the args field of udi
1675 2006-04-26 Thiemo Seufer <ths@networkno.de>
1677 * mips.h: Improve comments describing the bitfield instruction
1680 2006-04-26 Julian Brown <julian@codesourcery.com>
1682 * arm.h (FPU_VFP_EXT_V3): Define constant.
1683 (FPU_NEON_EXT_V1): Likewise.
1684 (FPU_VFP_HARD): Update.
1685 (FPU_VFP_V3): Define macro.
1686 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1688 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1690 * avr.h (AVR_ISA_PWMx): New.
1692 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1694 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1695 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1696 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1697 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1698 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1700 2006-03-10 Paul Brook <paul@codesourcery.com>
1702 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1704 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1706 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1707 first. Correct mask of bb "B" opcode.
1709 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1711 * i386.h (i386_optab): Support Intel Merom New Instructions.
1713 2006-02-24 Paul Brook <paul@codesourcery.com>
1715 * arm.h: Add V7 feature bits.
1717 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1719 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1721 2006-01-31 Paul Brook <paul@codesourcery.com>
1722 Richard Earnshaw <rearnsha@arm.com>
1724 * arm.h: Use ARM_CPU_FEATURE.
1725 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1726 (arm_feature_set): Change to a structure.
1727 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1728 ARM_FEATURE): New macros.
1730 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1732 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1733 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1734 (ADD_PC_INCR_OPCODE): Don't define.
1736 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1739 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1741 2005-11-14 David Ung <davidu@mips.com>
1743 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1744 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1745 save/restore encoding of the args field.
1747 2005-10-28 Dave Brolley <brolley@redhat.com>
1749 Contribute the following changes:
1750 2005-02-16 Dave Brolley <brolley@redhat.com>
1752 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1753 cgen_isa_mask_* to cgen_bitset_*.
1756 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1758 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1759 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1760 (CGEN_CPU_TABLE): Make isas a ponter.
1762 2003-09-29 Dave Brolley <brolley@redhat.com>
1764 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1765 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1766 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1768 2002-12-13 Dave Brolley <brolley@redhat.com>
1770 * cgen.h (symcat.h): #include it.
1771 (cgen-bitset.h): #include it.
1772 (CGEN_ATTR_VALUE_TYPE): Now a union.
1773 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1774 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1775 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1776 * cgen-bitset.h: New file.
1778 2005-09-30 Catherine Moore <clm@cm00re.com>
1782 2005-10-24 Jan Beulich <jbeulich@novell.com>
1784 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1787 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1789 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1790 Add FLAG_STRICT to pa10 ftest opcode.
1792 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1794 * hppa.h (pa_opcodes): Remove lha entries.
1796 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1798 * hppa.h (FLAG_STRICT): Revise comment.
1799 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1800 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1803 2005-09-30 Catherine Moore <clm@cm00re.com>
1807 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1809 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1811 2005-09-06 Chao-ying Fu <fu@mips.com>
1813 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1814 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1816 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1817 (INSN_ASE_MASK): Update to include INSN_MT.
1818 (INSN_MT): New define for MT ASE.
1820 2005-08-25 Chao-ying Fu <fu@mips.com>
1822 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1823 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1824 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1825 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1826 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1827 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1829 (INSN_DSP): New define for DSP ASE.
1831 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1835 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1837 * ppc.h (PPC_OPCODE_E300): Define.
1839 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1841 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1843 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1846 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1849 2005-07-27 Jan Beulich <jbeulich@novell.com>
1851 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1852 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1853 Add movq-s as 64-bit variants of movd-s.
1855 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1857 * hppa.h: Fix punctuation in comment.
1859 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1860 implicit space-register addressing. Set space-register bits on opcodes
1861 using implicit space-register addressing. Add various missing pa20
1862 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1863 space-register addressing. Use "fE" instead of "fe" in various
1866 2005-07-18 Jan Beulich <jbeulich@novell.com>
1868 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1870 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1872 * i386.h (i386_optab): Support Intel VMX Instructions.
1874 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1876 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1878 2005-07-05 Jan Beulich <jbeulich@novell.com>
1880 * i386.h (i386_optab): Add new insns.
1882 2005-07-01 Nick Clifton <nickc@redhat.com>
1884 * sparc.h: Add typedefs to structure declarations.
1886 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1889 * i386.h (i386_optab): Update comments for 64bit addressing on
1890 mov. Allow 64bit addressing for mov and movq.
1892 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1894 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1895 respectively, in various floating-point load and store patterns.
1897 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1899 * hppa.h (FLAG_STRICT): Correct comment.
1900 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1901 PA 2.0 mneumonics when equivalent. Entries with cache control
1902 completers now require PA 1.1. Adjust whitespace.
1904 2005-05-19 Anton Blanchard <anton@samba.org>
1906 * ppc.h (PPC_OPCODE_POWER5): Define.
1908 2005-05-10 Nick Clifton <nickc@redhat.com>
1910 * Update the address and phone number of the FSF organization in
1911 the GPL notices in the following files:
1912 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1913 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1914 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1915 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1916 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1917 tic54x.h, tic80.h, v850.h, vax.h
1919 2005-05-09 Jan Beulich <jbeulich@novell.com>
1921 * i386.h (i386_optab): Add ht and hnt.
1923 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1925 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1926 Add xcrypt-ctr. Provide aliases without hyphens.
1928 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1930 Moved from ../ChangeLog
1932 2005-04-12 Paul Brook <paul@codesourcery.com>
1933 * m88k.h: Rename psr macros to avoid conflicts.
1935 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1936 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1937 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1938 and ARM_ARCH_V6ZKT2.
1940 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1941 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1942 Remove redundant instruction types.
1943 (struct argument): X_op - new field.
1944 (struct cst4_entry): Remove.
1945 (no_op_insn): Declare.
1947 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1948 * crx.h (enum argtype): Rename types, remove unused types.
1950 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1951 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1952 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1953 (enum operand_type): Rearrange operands, edit comments.
1954 replace us<N> with ui<N> for unsigned immediate.
1955 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1956 displacements (respectively).
1957 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1958 (instruction type): Add NO_TYPE_INS.
1959 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1960 (operand_entry): New field - 'flags'.
1961 (operand flags): New.
1963 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1964 * crx.h (operand_type): Remove redundant types i3, i4,
1966 Add new unsigned immediate types us3, us4, us5, us16.
1968 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1970 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1971 adjust them accordingly.
1973 2005-04-01 Jan Beulich <jbeulich@novell.com>
1975 * i386.h (i386_optab): Add rdtscp.
1977 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1979 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1980 between memory and segment register. Allow movq for moving between
1981 general-purpose register and segment register.
1983 2005-02-09 Jan Beulich <jbeulich@novell.com>
1986 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1987 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1990 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1992 * m68k.h (m68008, m68ec030, m68882): Remove.
1994 (cpu_m68k, cpu_cf): New.
1995 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1996 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1998 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2000 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2001 * cgen.h (enum cgen_parse_operand_type): Add
2002 CGEN_PARSE_OPERAND_SYMBOLIC.
2004 2005-01-21 Fred Fish <fnf@specifixinc.com>
2006 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2007 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2008 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2010 2005-01-19 Fred Fish <fnf@specifixinc.com>
2012 * mips.h (struct mips_opcode): Add new pinfo2 member.
2013 (INSN_ALIAS): New define for opcode table entries that are
2014 specific instances of another entry, such as 'move' for an 'or'
2015 with a zero operand.
2016 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2017 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2019 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2021 * mips.h (CPU_RM9000): Define.
2022 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2024 2004-11-25 Jan Beulich <jbeulich@novell.com>
2026 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2027 to/from test registers are illegal in 64-bit mode. Add missing
2028 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2029 (previously one had to explicitly encode a rex64 prefix). Re-enable
2030 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2031 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2033 2004-11-23 Jan Beulich <jbeulich@novell.com>
2035 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2036 available only with SSE2. Change the MMX additions introduced by SSE
2037 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2038 instructions by their now designated identifier (since combining i686
2039 and 3DNow! does not really imply 3DNow!A).
2041 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2043 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2044 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2046 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2047 Vineet Sharma <vineets@noida.hcltech.com>
2049 * maxq.h: New file: Disassembly information for the maxq port.
2051 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2053 * i386.h (i386_optab): Put back "movzb".
2055 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2057 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2058 comments. Remove member cris_ver_sim. Add members
2059 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2060 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2061 (struct cris_support_reg, struct cris_cond15): New types.
2062 (cris_conds15): Declare.
2063 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2064 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2065 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2066 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2067 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2068 SIZE_FIELD_UNSIGNED.
2070 2004-11-04 Jan Beulich <jbeulich@novell.com>
2072 * i386.h (sldx_Suf): Remove.
2073 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2074 (q_FP): Define, implying no REX64.
2075 (x_FP, sl_FP): Imply FloatMF.
2076 (i386_optab): Split reg and mem forms of moving from segment registers
2077 so that the memory forms can ignore the 16-/32-bit operand size
2078 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2079 all non-floating-point instructions. Unite 32- and 64-bit forms of
2080 movsx, movzx, and movd. Adjust floating point operations for the above
2081 changes to the *FP macros. Add DefaultSize to floating point control
2082 insns operating on larger memory ranges. Remove left over comments
2083 hinting at certain insns being Intel-syntax ones where the ones
2084 actually meant are already gone.
2086 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2088 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2091 2004-09-30 Paul Brook <paul@codesourcery.com>
2093 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2094 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2096 2004-09-11 Theodore A. Roth <troth@openavr.org>
2098 * avr.h: Add support for
2099 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2101 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2103 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2105 2004-08-24 Dmitry Diky <diwil@spec.ru>
2107 * msp430.h (msp430_opc): Add new instructions.
2108 (msp430_rcodes): Declare new instructions.
2109 (msp430_hcodes): Likewise..
2111 2004-08-13 Nick Clifton <nickc@redhat.com>
2114 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2117 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2119 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2121 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2123 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2125 2004-07-21 Jan Beulich <jbeulich@novell.com>
2127 * i386.h: Adjust instruction descriptions to better match the
2130 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2132 * arm.h: Remove all old content. Replace with architecture defines
2133 from gas/config/tc-arm.c.
2135 2004-07-09 Andreas Schwab <schwab@suse.de>
2137 * m68k.h: Fix comment.
2139 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2143 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2145 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2147 2004-05-24 Peter Barada <peter@the-baradas.com>
2149 * m68k.h: Add 'size' to m68k_opcode.
2151 2004-05-05 Peter Barada <peter@the-baradas.com>
2153 * m68k.h: Switch from ColdFire chip name to core variant.
2155 2004-04-22 Peter Barada <peter@the-baradas.com>
2157 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2158 descriptions for new EMAC cases.
2159 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2160 handle Motorola MAC syntax.
2161 Allow disassembly of ColdFire V4e object files.
2163 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2165 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2167 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2169 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2171 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2173 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2175 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2177 * i386.h (i386_optab): Added xstore/xcrypt insns.
2179 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2181 * h8300.h (32bit ldc/stc): Add relaxing support.
2183 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2185 * h8300.h (BITOP): Pass MEMRELAX flag.
2187 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2189 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2192 For older changes see ChangeLog-9103
2194 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2196 Copying and distribution of this file, with or without modification,
2197 are permitted in any medium without royalty provided the copyright
2198 notice and this notice are preserved.
2204 version-control: never
projects / external / binutils.git / blob