1 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
4 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
6 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
8 * mips.h: Update commentary after last commit.
10 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
12 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
13 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
14 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
16 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
18 * mips.h: Fix previous commit.
20 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
22 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
23 (INSN_LOONGSON_3A): Clear bit 31.
25 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
28 * arm.h (ARM_AEXT_V6M_ONLY): New define.
29 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
30 (ARM_ARCH_V6M_ONLY): New define.
32 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
34 * mips.h (INSN_LOONGSON_3A): Defined.
35 (CPU_LOONGSON_3A): Defined.
36 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
38 2010-10-09 Matt Rice <ratmice@gmail.com>
40 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
41 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
43 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
45 * arm.h (ARM_EXT_VIRT): New define.
46 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
47 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
50 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
52 * arm.h (ARM_AEXT_ADIV): New define.
53 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
55 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
57 * arm.h (ARM_EXT_OS): New define.
58 (ARM_AEXT_V6SM): Likewise.
59 (ARM_ARCH_V6SM): Likewise.
61 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
63 * arm.h (ARM_EXT_MP): Add.
64 (ARM_ARCH_V7A_MP): Likewise.
66 2010-09-22 Mike Frysinger <vapier@gentoo.org>
68 * bfin.h: Declare pseudoChr structs/defines.
70 2010-09-21 Mike Frysinger <vapier@gentoo.org>
72 * bfin.h: Strip trailing whitespace.
74 2010-07-29 DJ Delorie <dj@redhat.com>
76 * rx.h (RX_Operand_Type): Add TwoReg.
77 (RX_Opcode_ID): Remove ediv and ediv2.
79 2010-07-27 DJ Delorie <dj@redhat.com>
81 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
83 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
84 Ina Pandit <ina.pandit@kpitcummins.com>
86 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
87 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
89 Remove PROCESSOR_V850EA support.
90 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
91 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
92 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
93 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
94 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
96 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
98 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
101 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
103 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
104 (MIPS16_INSN_BRANCH): Rename to...
105 (MIPS16_INSN_COND_BRANCH): ... this.
107 2010-07-03 Alan Modra <amodra@gmail.com>
109 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
110 Renumber other PPC_OPCODE defines.
112 2010-07-03 Alan Modra <amodra@gmail.com>
114 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
116 2010-06-29 Alan Modra <amodra@gmail.com>
118 * maxq.h: Delete file.
120 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
122 * ppc.h (PPC_OPCODE_E500): Define.
124 2010-05-26 Catherine Moore <clm@codesourcery.com>
126 * opcode/mips.h (INSN_MIPS16): Remove.
128 2010-04-21 Joseph Myers <joseph@codesourcery.com>
130 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
132 2010-04-15 Nick Clifton <nickc@redhat.com>
134 * alpha.h: Update copyright notice to use GPLv3.
140 * convex.h: Likewise.
154 * m68hc11.h: Likewise.
160 * mn10200.h: Likewise.
161 * mn10300.h: Likewise.
162 * msp430.h: Likewise.
173 * score-datadep.h: Likewise.
174 * score-inst.h: Likewise.
176 * spu-insns.h: Likewise.
180 * tic54x.h: Likewise.
185 2010-03-25 Joseph Myers <joseph@codesourcery.com>
187 * tic6x-control-registers.h, tic6x-insn-formats.h,
188 tic6x-opcode-table.h, tic6x.h: New.
190 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
192 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
194 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
196 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
198 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
200 * ia64.h (ia64_find_opcode): Remove argument name.
201 (ia64_find_next_opcode): Likewise.
202 (ia64_dis_opcode): Likewise.
203 (ia64_free_opcode): Likewise.
204 (ia64_find_dependency): Likewise.
206 2009-11-22 Doug Evans <dje@sebabeach.org>
208 * cgen.h: Include bfd_stdint.h.
209 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
211 2009-11-18 Paul Brook <paul@codesourcery.com>
213 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
215 2009-11-17 Paul Brook <paul@codesourcery.com>
216 Daniel Jacobowitz <dan@codesourcery.com>
218 * arm.h (ARM_EXT_V6_DSP): Define.
219 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
220 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
222 2009-11-04 DJ Delorie <dj@redhat.com>
224 * rx.h (rx_decode_opcode) (mvtipl): Add.
225 (mvtcp, mvfcp, opecp): Remove.
227 2009-11-02 Paul Brook <paul@codesourcery.com>
229 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
230 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
231 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
232 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
233 FPU_ARCH_NEON_VFP_V4): Define.
235 2009-10-23 Doug Evans <dje@sebabeach.org>
237 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
238 * cgen.h: Update. Improve multi-inclusion macro name.
240 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
242 * ppc.h (PPC_OPCODE_476): Define.
244 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
246 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
248 2009-09-29 DJ Delorie <dj@redhat.com>
252 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
254 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
256 2009-09-21 Ben Elliston <bje@au.ibm.com>
258 * ppc.h (PPC_OPCODE_PPCA2): New.
260 2009-09-05 Martin Thuresson <martin@mtme.org>
262 * ia64.h (struct ia64_operand): Renamed member class to op_class.
264 2009-08-29 Martin Thuresson <martin@mtme.org>
266 * tic30.h (template): Rename type template to
267 insn_template. Updated code to use new name.
268 * tic54x.h (template): Rename type template to
271 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
273 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
275 2009-06-11 Anthony Green <green@moxielogic.com>
277 * moxie.h (MOXIE_F3_PCREL): Define.
278 (moxie_form3_opc_info): Grow.
280 2009-06-06 Anthony Green <green@moxielogic.com>
282 * moxie.h (MOXIE_F1_M): Define.
284 2009-04-15 Anthony Green <green@moxielogic.com>
288 2009-04-06 DJ Delorie <dj@redhat.com>
290 * h8300.h: Add relaxation attributes to MOVA opcodes.
292 2009-03-10 Alan Modra <amodra@bigpond.net.au>
294 * ppc.h (ppc_parse_cpu): Declare.
296 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
298 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
299 and _IMM11 for mbitclr and mbitset.
300 * score-datadep.h: Update dependency information.
302 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
304 * ppc.h (PPC_OPCODE_POWER7): New.
306 2009-02-06 Doug Evans <dje@google.com>
308 * i386.h: Add comment regarding sse* insns and prefixes.
310 2009-02-03 Sandip Matte <sandip@rmicorp.com>
312 * mips.h (INSN_XLR): Define.
313 (INSN_CHIP_MASK): Update.
315 (OPCODE_IS_MEMBER): Update.
316 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
318 2009-01-28 Doug Evans <dje@google.com>
320 * opcode/i386.h: Add multiple inclusion protection.
321 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
322 (EDI_REG_NUM): New macros.
323 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
324 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
325 (REX_PREFIX_P): New macro.
327 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
329 * ppc.h (struct powerpc_opcode): New field "deprecated".
330 (PPC_OPCODE_NOPOWER4): Delete.
332 2008-11-28 Joshua Kinard <kumba@gentoo.org>
334 * mips.h: Define CPU_R14000, CPU_R16000.
335 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
337 2008-11-18 Catherine Moore <clm@codesourcery.com>
339 * arm.h (FPU_NEON_FP16): New.
340 (FPU_ARCH_NEON_FP16): New.
342 2008-11-06 Chao-ying Fu <fu@mips.com>
344 * mips.h: Doucument '1' for 5-bit sync type.
346 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
348 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
351 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
353 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
355 2008-07-30 Michael J. Eager <eager@eagercon.com>
357 * ppc.h (PPC_OPCODE_405): Define.
358 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
360 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
362 * ppc.h (ppc_cpu_t): New typedef.
363 (struct powerpc_opcode <flags>): Use it.
364 (struct powerpc_operand <insert, extract>): Likewise.
365 (struct powerpc_macro <flags>): Likewise.
367 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
369 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
370 Update comment before MIPS16 field descriptors to mention MIPS16.
371 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
373 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
374 New bit masks and shift counts for cins and exts.
376 * mips.h: Document new field descriptors +Q.
377 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
379 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
381 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
382 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
384 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
386 * ppc.h: (PPC_OPCODE_E500MC): New.
388 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
390 * i386.h (MAX_OPERANDS): Set to 5.
391 (MAX_MNEM_SIZE): Changed to 20.
393 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
395 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
397 2008-03-09 Paul Brook <paul@codesourcery.com>
399 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
401 2008-03-04 Paul Brook <paul@codesourcery.com>
403 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
404 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
405 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
407 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
408 Nick Clifton <nickc@redhat.com>
411 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
412 with a 32-bit displacement but without the top bit of the 4th byte
415 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
417 * cr16.h (cr16_num_optab): Declared.
419 2008-02-14 Hakan Ardo <hakan@debian.org>
422 * avr.h (AVR_ISA_2xxe): Define.
424 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
426 * mips.h: Update copyright.
427 (INSN_CHIP_MASK): New macro.
428 (INSN_OCTEON): New macro.
429 (CPU_OCTEON): New macro.
430 (OPCODE_IS_MEMBER): Handle Octeon instructions.
432 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
434 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
436 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
438 * avr.h (AVR_ISA_USB162): Add new opcode set.
439 (AVR_ISA_AVR3): Likewise.
441 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
443 * mips.h (INSN_LOONGSON_2E): New.
444 (INSN_LOONGSON_2F): New.
445 (CPU_LOONGSON_2E): New.
446 (CPU_LOONGSON_2F): New.
447 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
449 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
451 * mips.h (INSN_ISA*): Redefine certain values as an
452 enumeration. Update comments.
453 (mips_isa_table): New.
454 (ISA_MIPS*): Redefine to match enumeration.
455 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
458 2007-08-08 Ben Elliston <bje@au.ibm.com>
460 * ppc.h (PPC_OPCODE_PPCPS): New.
462 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
464 * m68k.h: Document j K & E.
466 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
468 * cr16.h: New file for CR16 target.
470 2007-05-02 Alan Modra <amodra@bigpond.net.au>
472 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
474 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
476 * m68k.h (mcfisa_c): New.
477 (mcfusp, mcf_mask): Adjust.
479 2007-04-20 Alan Modra <amodra@bigpond.net.au>
481 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
482 (num_powerpc_operands): Declare.
483 (PPC_OPERAND_SIGNED et al): Redefine as hex.
484 (PPC_OPERAND_PLUS1): Define.
486 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
488 * i386.h (REX_MODE64): Renamed to ...
490 (REX_EXTX): Renamed to ...
492 (REX_EXTY): Renamed to ...
494 (REX_EXTZ): Renamed to ...
497 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
499 * i386.h: Add entries from config/tc-i386.h and move tables
500 to opcodes/i386-opc.h.
502 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
504 * i386.h (FloatDR): Removed.
505 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
507 2007-03-01 Alan Modra <amodra@bigpond.net.au>
509 * spu-insns.h: Add soma double-float insns.
511 2007-02-20 Thiemo Seufer <ths@mips.com>
512 Chao-Ying Fu <fu@mips.com>
514 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
515 (INSN_DSPR2): Add flag for DSP R2 instructions.
516 (M_BALIGN): New macro.
518 2007-02-14 Alan Modra <amodra@bigpond.net.au>
520 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
521 and Seg3ShortFrom with Shortform.
523 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
526 * i386.h (i386_optab): Put the real "test" before the pseudo
529 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
531 * m68k.h (m68010up): OR fido_a.
533 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
535 * m68k.h (fido_a): New.
537 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
539 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
540 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
543 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
545 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
547 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
549 * score-inst.h (enum score_insn_type): Add Insn_internal.
551 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
552 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
553 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
554 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
555 Alan Modra <amodra@bigpond.net.au>
557 * spu-insns.h: New file.
560 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
562 * ppc.h (PPC_OPCODE_CELL): Define.
564 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
566 * i386.h : Modify opcode to support for the change in POPCNT opcode
567 in amdfam10 architecture.
569 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
571 * i386.h: Replace CpuMNI with CpuSSSE3.
573 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
574 Joseph Myers <joseph@codesourcery.com>
575 Ian Lance Taylor <ian@wasabisystems.com>
576 Ben Elliston <bje@wasabisystems.com>
578 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
580 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
582 * score-datadep.h: New file.
583 * score-inst.h: New file.
585 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
587 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
588 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
591 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
592 Michael Meissner <michael.meissner@amd.com>
594 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
596 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
598 * i386.h (i386_optab): Add "nop" with memory reference.
600 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
602 * i386.h (i386_optab): Update comment for 64bit NOP.
604 2006-06-06 Ben Elliston <bje@au.ibm.com>
605 Anton Blanchard <anton@samba.org>
607 * ppc.h (PPC_OPCODE_POWER6): Define.
610 2006-06-05 Thiemo Seufer <ths@mips.com>
612 * mips.h: Improve description of MT flags.
614 2006-05-25 Richard Sandiford <richard@codesourcery.com>
616 * m68k.h (mcf_mask): Define.
618 2006-05-05 Thiemo Seufer <ths@mips.com>
619 David Ung <davidu@mips.com>
621 * mips.h (enum): Add macro M_CACHE_AB.
623 2006-05-04 Thiemo Seufer <ths@mips.com>
624 Nigel Stephens <nigel@mips.com>
625 David Ung <davidu@mips.com>
627 * mips.h: Add INSN_SMARTMIPS define.
629 2006-04-30 Thiemo Seufer <ths@mips.com>
630 David Ung <davidu@mips.com>
632 * mips.h: Defines udi bits and masks. Add description of
633 characters which may appear in the args field of udi
636 2006-04-26 Thiemo Seufer <ths@networkno.de>
638 * mips.h: Improve comments describing the bitfield instruction
641 2006-04-26 Julian Brown <julian@codesourcery.com>
643 * arm.h (FPU_VFP_EXT_V3): Define constant.
644 (FPU_NEON_EXT_V1): Likewise.
645 (FPU_VFP_HARD): Update.
646 (FPU_VFP_V3): Define macro.
647 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
649 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
651 * avr.h (AVR_ISA_PWMx): New.
653 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
655 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
656 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
657 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
658 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
659 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
661 2006-03-10 Paul Brook <paul@codesourcery.com>
663 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
665 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
667 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
668 first. Correct mask of bb "B" opcode.
670 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
672 * i386.h (i386_optab): Support Intel Merom New Instructions.
674 2006-02-24 Paul Brook <paul@codesourcery.com>
676 * arm.h: Add V7 feature bits.
678 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
680 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
682 2006-01-31 Paul Brook <paul@codesourcery.com>
683 Richard Earnshaw <rearnsha@arm.com>
685 * arm.h: Use ARM_CPU_FEATURE.
686 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
687 (arm_feature_set): Change to a structure.
688 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
689 ARM_FEATURE): New macros.
691 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
693 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
694 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
695 (ADD_PC_INCR_OPCODE): Don't define.
697 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
700 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
702 2005-11-14 David Ung <davidu@mips.com>
704 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
705 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
706 save/restore encoding of the args field.
708 2005-10-28 Dave Brolley <brolley@redhat.com>
710 Contribute the following changes:
711 2005-02-16 Dave Brolley <brolley@redhat.com>
713 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
714 cgen_isa_mask_* to cgen_bitset_*.
717 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
719 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
720 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
721 (CGEN_CPU_TABLE): Make isas a ponter.
723 2003-09-29 Dave Brolley <brolley@redhat.com>
725 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
726 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
727 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
729 2002-12-13 Dave Brolley <brolley@redhat.com>
731 * cgen.h (symcat.h): #include it.
732 (cgen-bitset.h): #include it.
733 (CGEN_ATTR_VALUE_TYPE): Now a union.
734 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
735 (CGEN_ATTR_ENTRY): 'value' now unsigned.
736 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
737 * cgen-bitset.h: New file.
739 2005-09-30 Catherine Moore <clm@cm00re.com>
743 2005-10-24 Jan Beulich <jbeulich@novell.com>
745 * ia64.h (enum ia64_opnd): Move memory operand out of set of
748 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
750 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
751 Add FLAG_STRICT to pa10 ftest opcode.
753 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
755 * hppa.h (pa_opcodes): Remove lha entries.
757 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
759 * hppa.h (FLAG_STRICT): Revise comment.
760 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
761 before corresponding pa11 opcodes. Add strict pa10 register-immediate
764 2005-09-30 Catherine Moore <clm@cm00re.com>
768 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
770 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
772 2005-09-06 Chao-ying Fu <fu@mips.com>
774 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
775 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
777 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
778 (INSN_ASE_MASK): Update to include INSN_MT.
779 (INSN_MT): New define for MT ASE.
781 2005-08-25 Chao-ying Fu <fu@mips.com>
783 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
784 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
785 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
786 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
787 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
788 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
790 (INSN_DSP): New define for DSP ASE.
792 2005-08-18 Alan Modra <amodra@bigpond.net.au>
796 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
798 * ppc.h (PPC_OPCODE_E300): Define.
800 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
802 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
804 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
807 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
810 2005-07-27 Jan Beulich <jbeulich@novell.com>
812 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
813 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
814 Add movq-s as 64-bit variants of movd-s.
816 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
818 * hppa.h: Fix punctuation in comment.
820 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
821 implicit space-register addressing. Set space-register bits on opcodes
822 using implicit space-register addressing. Add various missing pa20
823 long-immediate opcodes. Remove various opcodes using implicit 3-bit
824 space-register addressing. Use "fE" instead of "fe" in various
827 2005-07-18 Jan Beulich <jbeulich@novell.com>
829 * i386.h (i386_optab): Operands of aam and aad are unsigned.
831 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
833 * i386.h (i386_optab): Support Intel VMX Instructions.
835 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
837 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
839 2005-07-05 Jan Beulich <jbeulich@novell.com>
841 * i386.h (i386_optab): Add new insns.
843 2005-07-01 Nick Clifton <nickc@redhat.com>
845 * sparc.h: Add typedefs to structure declarations.
847 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
850 * i386.h (i386_optab): Update comments for 64bit addressing on
851 mov. Allow 64bit addressing for mov and movq.
853 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
855 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
856 respectively, in various floating-point load and store patterns.
858 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
860 * hppa.h (FLAG_STRICT): Correct comment.
861 (pa_opcodes): Update load and store entries to allow both PA 1.X and
862 PA 2.0 mneumonics when equivalent. Entries with cache control
863 completers now require PA 1.1. Adjust whitespace.
865 2005-05-19 Anton Blanchard <anton@samba.org>
867 * ppc.h (PPC_OPCODE_POWER5): Define.
869 2005-05-10 Nick Clifton <nickc@redhat.com>
871 * Update the address and phone number of the FSF organization in
872 the GPL notices in the following files:
873 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
874 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
875 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
876 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
877 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
878 tic54x.h, tic80.h, v850.h, vax.h
880 2005-05-09 Jan Beulich <jbeulich@novell.com>
882 * i386.h (i386_optab): Add ht and hnt.
884 2005-04-18 Mark Kettenis <kettenis@gnu.org>
886 * i386.h: Insert hyphens into selected VIA PadLock extensions.
887 Add xcrypt-ctr. Provide aliases without hyphens.
889 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
891 Moved from ../ChangeLog
893 2005-04-12 Paul Brook <paul@codesourcery.com>
894 * m88k.h: Rename psr macros to avoid conflicts.
896 2005-03-12 Zack Weinberg <zack@codesourcery.com>
897 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
898 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
901 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
902 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
903 Remove redundant instruction types.
904 (struct argument): X_op - new field.
905 (struct cst4_entry): Remove.
906 (no_op_insn): Declare.
908 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
909 * crx.h (enum argtype): Rename types, remove unused types.
911 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
912 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
913 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
914 (enum operand_type): Rearrange operands, edit comments.
915 replace us<N> with ui<N> for unsigned immediate.
916 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
917 displacements (respectively).
918 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
919 (instruction type): Add NO_TYPE_INS.
920 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
921 (operand_entry): New field - 'flags'.
922 (operand flags): New.
924 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
925 * crx.h (operand_type): Remove redundant types i3, i4,
927 Add new unsigned immediate types us3, us4, us5, us16.
929 2005-04-12 Mark Kettenis <kettenis@gnu.org>
931 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
932 adjust them accordingly.
934 2005-04-01 Jan Beulich <jbeulich@novell.com>
936 * i386.h (i386_optab): Add rdtscp.
938 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
940 * i386.h (i386_optab): Don't allow the `l' suffix for moving
941 between memory and segment register. Allow movq for moving between
942 general-purpose register and segment register.
944 2005-02-09 Jan Beulich <jbeulich@novell.com>
947 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
948 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
951 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
953 * m68k.h (m68008, m68ec030, m68882): Remove.
955 (cpu_m68k, cpu_cf): New.
956 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
957 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
959 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
961 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
962 * cgen.h (enum cgen_parse_operand_type): Add
963 CGEN_PARSE_OPERAND_SYMBOLIC.
965 2005-01-21 Fred Fish <fnf@specifixinc.com>
967 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
968 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
969 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
971 2005-01-19 Fred Fish <fnf@specifixinc.com>
973 * mips.h (struct mips_opcode): Add new pinfo2 member.
974 (INSN_ALIAS): New define for opcode table entries that are
975 specific instances of another entry, such as 'move' for an 'or'
977 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
978 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
980 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
982 * mips.h (CPU_RM9000): Define.
983 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
985 2004-11-25 Jan Beulich <jbeulich@novell.com>
987 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
988 to/from test registers are illegal in 64-bit mode. Add missing
989 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
990 (previously one had to explicitly encode a rex64 prefix). Re-enable
991 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
992 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
994 2004-11-23 Jan Beulich <jbeulich@novell.com>
996 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
997 available only with SSE2. Change the MMX additions introduced by SSE
998 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
999 instructions by their now designated identifier (since combining i686
1000 and 3DNow! does not really imply 3DNow!A).
1002 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1004 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1005 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1007 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1008 Vineet Sharma <vineets@noida.hcltech.com>
1010 * maxq.h: New file: Disassembly information for the maxq port.
1012 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1014 * i386.h (i386_optab): Put back "movzb".
1016 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1018 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1019 comments. Remove member cris_ver_sim. Add members
1020 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1021 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1022 (struct cris_support_reg, struct cris_cond15): New types.
1023 (cris_conds15): Declare.
1024 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1025 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1026 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1027 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1028 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1029 SIZE_FIELD_UNSIGNED.
1031 2004-11-04 Jan Beulich <jbeulich@novell.com>
1033 * i386.h (sldx_Suf): Remove.
1034 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1035 (q_FP): Define, implying no REX64.
1036 (x_FP, sl_FP): Imply FloatMF.
1037 (i386_optab): Split reg and mem forms of moving from segment registers
1038 so that the memory forms can ignore the 16-/32-bit operand size
1039 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1040 all non-floating-point instructions. Unite 32- and 64-bit forms of
1041 movsx, movzx, and movd. Adjust floating point operations for the above
1042 changes to the *FP macros. Add DefaultSize to floating point control
1043 insns operating on larger memory ranges. Remove left over comments
1044 hinting at certain insns being Intel-syntax ones where the ones
1045 actually meant are already gone.
1047 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1049 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1052 2004-09-30 Paul Brook <paul@codesourcery.com>
1054 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1055 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1057 2004-09-11 Theodore A. Roth <troth@openavr.org>
1059 * avr.h: Add support for
1060 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1062 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1064 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1066 2004-08-24 Dmitry Diky <diwil@spec.ru>
1068 * msp430.h (msp430_opc): Add new instructions.
1069 (msp430_rcodes): Declare new instructions.
1070 (msp430_hcodes): Likewise..
1072 2004-08-13 Nick Clifton <nickc@redhat.com>
1075 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1078 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1080 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1082 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1084 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1086 2004-07-21 Jan Beulich <jbeulich@novell.com>
1088 * i386.h: Adjust instruction descriptions to better match the
1091 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1093 * arm.h: Remove all old content. Replace with architecture defines
1094 from gas/config/tc-arm.c.
1096 2004-07-09 Andreas Schwab <schwab@suse.de>
1098 * m68k.h: Fix comment.
1100 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1104 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1106 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1108 2004-05-24 Peter Barada <peter@the-baradas.com>
1110 * m68k.h: Add 'size' to m68k_opcode.
1112 2004-05-05 Peter Barada <peter@the-baradas.com>
1114 * m68k.h: Switch from ColdFire chip name to core variant.
1116 2004-04-22 Peter Barada <peter@the-baradas.com>
1118 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1119 descriptions for new EMAC cases.
1120 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1121 handle Motorola MAC syntax.
1122 Allow disassembly of ColdFire V4e object files.
1124 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1126 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1128 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1130 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1132 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1134 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1136 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1138 * i386.h (i386_optab): Added xstore/xcrypt insns.
1140 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1142 * h8300.h (32bit ldc/stc): Add relaxing support.
1144 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1146 * h8300.h (BITOP): Pass MEMRELAX flag.
1148 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1150 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1153 For older changes see ChangeLog-9103
1159 version-control: never