1 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
3 * aarch64.h (aarch64_sys_reg): New typedef.
4 (aarch64_sys_regs): Change to define with the new type.
5 (aarch64_sys_reg_deprecated_p): Declare.
7 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
9 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
10 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
12 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
14 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
15 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
16 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
17 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
18 For MIPS, update extension character sequences after +.
19 (ASE_MSA): New define.
20 (ASE_MSA64): New define.
21 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
22 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
23 For microMIPS, update extension character sequences after +.
25 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
30 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
32 * mips.h: Remove references to "+I" and imm2_expr.
34 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
36 * mips.h (M_DEXT, M_DINS): Delete.
38 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
40 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
41 (mips_optional_operand_p): New function.
43 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
44 Richard Sandiford <rdsandiford@googlemail.com>
46 * mips.h: Document new VU0 operand characters.
47 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
48 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
49 (OP_REG_R5900_ACC): New mips_reg_operand_types.
50 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
51 (mips_vu0_channel_mask): Declare.
53 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
55 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
56 (mips_int_operand_min, mips_int_operand_max): New functions.
57 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
59 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
61 * mips.h (mips_decode_reg_operand): New function.
62 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
63 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
64 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
66 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
67 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
68 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
69 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
70 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
71 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
72 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
73 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
74 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
75 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
76 macros to cover the gaps.
77 (INSN2_MOD_SP): Replace with...
78 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
79 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
80 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
81 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
82 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
85 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
87 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
88 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
89 (MIPS16_INSN_COND_BRANCH): Delete.
91 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
92 Kirill Yukhin <kirill.yukhin@intel.com>
93 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
95 * i386.h (BND_PREFIX_OPCODE): New.
97 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
99 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
100 OP_SAVE_RESTORE_LIST.
101 (decode_mips16_operand): Declare.
103 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
105 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
106 (mips_operand, mips_int_operand, mips_mapped_int_operand)
107 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
108 (mips_pcrel_operand): New structures.
109 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
110 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
111 (decode_mips_operand, decode_micromips_operand): Declare.
113 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
115 * mips.h: Document MIPS16 "I" opcode.
117 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
119 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
120 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
121 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
122 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
123 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
124 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
125 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
126 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
127 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
128 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
129 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
130 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
131 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
133 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
134 (M_USD_AB): ...these.
136 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
138 * mips.h: Remove documentation of "[" and "]". Update documentation
139 of "k" and the MDMX formats.
141 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
143 * mips.h: Update documentation of "+s" and "+S".
145 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
147 * mips.h: Document "+i".
149 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
151 * mips.h: Remove "mi" documentation. Update "mh" documentation.
152 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
154 (INSN2_WRITE_GPR_MHI): Rename to...
155 (INSN2_WRITE_GPR_MH): ...this.
157 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
159 * mips.h: Remove documentation of "+D" and "+T".
161 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
163 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
164 Use "source" rather than "destination" for microMIPS "G".
166 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
168 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
171 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
173 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
175 2013-06-17 Catherine Moore <clm@codesourcery.com>
176 Maciej W. Rozycki <macro@codesourcery.com>
177 Chao-Ying Fu <fu@mips.com>
179 * mips.h (OP_SH_EVAOFFSET): Define.
180 (OP_MASK_EVAOFFSET): Define.
181 (INSN_ASE_MASK): Delete.
183 (M_CACHEE_AB, M_CACHEE_OB): New.
184 (M_LBE_OB, M_LBE_AB): New.
185 (M_LBUE_OB, M_LBUE_AB): New.
186 (M_LHE_OB, M_LHE_AB): New.
187 (M_LHUE_OB, M_LHUE_AB): New.
188 (M_LLE_AB, M_LLE_OB): New.
189 (M_LWE_OB, M_LWE_AB): New.
190 (M_LWLE_AB, M_LWLE_OB): New.
191 (M_LWRE_AB, M_LWRE_OB): New.
192 (M_PREFE_AB, M_PREFE_OB): New.
193 (M_SCE_AB, M_SCE_OB): New.
194 (M_SBE_OB, M_SBE_AB): New.
195 (M_SHE_OB, M_SHE_AB): New.
196 (M_SWE_OB, M_SWE_AB): New.
197 (M_SWLE_AB, M_SWLE_OB): New.
198 (M_SWRE_AB, M_SWRE_OB): New.
199 (MICROMIPSOP_SH_EVAOFFSET): Define.
200 (MICROMIPSOP_MASK_EVAOFFSET): Define.
202 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
204 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
206 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
208 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
210 2013-05-09 Andrew Pinski <apinski@cavium.com>
212 * mips.h (OP_MASK_CODE10): Correct definition.
213 (OP_SH_CODE10): Likewise.
214 Add a comment that "+J" is used now for OP_*CODE10.
215 (INSN_ASE_MASK): Update.
216 (INSN_VIRT): New macro.
217 (INSN_VIRT64): New macro
219 2013-05-02 Nick Clifton <nickc@redhat.com>
221 * msp430.h: Add patterns for MSP430X instructions.
223 2013-04-06 David S. Miller <davem@davemloft.net>
225 * sparc.h (F_PREFERRED): Define.
226 (F_PREF_ALIAS): Define.
228 2013-04-03 Nick Clifton <nickc@redhat.com>
230 * v850.h (V850_INVERSE_PCREL): Define.
232 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
235 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
237 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
240 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
242 * tic6xc-opcode-table.h: Add 16-bit insns.
243 * tic6x.h: Add support for 16-bit insns.
245 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
247 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
248 and mov.b/w/l Rs,@(d:32,ERd).
250 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
253 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
254 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
255 tic6x_operand_xregpair operand coding type.
256 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
257 opcode field, usu ORXREGD1324 for the src2 operand and remove the
260 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
263 * tic6x.h (enum tic6x_coding_method): Add
264 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
265 separately the msb and lsb of a register pair. This is needed to
266 encode the opcodes in the same way as TI assembler does.
267 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
268 and rsqrdp opcodes to use the new field coding types.
270 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
272 * arm.h (CRC_EXT_ARMV8): New constant.
273 (ARCH_CRC_ARMV8): New macro.
275 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
277 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
279 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
280 Andrew Jenner <andrew@codesourcery.com>
282 Based on patches from Altera Corporation.
286 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
288 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
290 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
293 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
295 2013-01-24 Nick Clifton <nickc@redhat.com>
297 * v850.h: Add e3v5 support.
299 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
301 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
303 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
305 * ppc.h (PPC_OPCODE_POWER8): New define.
306 (PPC_OPCODE_HTM): Likewise.
308 2013-01-10 Will Newton <will.newton@imgtec.com>
312 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
314 * cr16.h (make_instruction): Rename to cr16_make_instruction.
315 (match_opcode): Rename to cr16_match_opcode.
317 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
319 * mips.h: Add support for r5900 instructions including lq and sq.
321 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
323 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
324 (make_instruction,match_opcode): Added function prototypes.
325 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
327 2012-11-23 Alan Modra <amodra@gmail.com>
329 * ppc.h (ppc_parse_cpu): Update prototype.
331 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
333 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
334 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
336 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
338 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
340 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
342 * ia64.h (ia64_opnd): Add new operand types.
344 2012-08-21 David S. Miller <davem@davemloft.net>
346 * sparc.h (F3F4): New macro.
348 2012-08-13 Ian Bolton <ian.bolton@arm.com>
349 Laurent Desnogues <laurent.desnogues@arm.com>
350 Jim MacArthur <jim.macarthur@arm.com>
351 Marcus Shawcroft <marcus.shawcroft@arm.com>
352 Nigel Stephens <nigel.stephens@arm.com>
353 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
354 Richard Earnshaw <rearnsha@arm.com>
355 Sofiane Naci <sofiane.naci@arm.com>
356 Tejas Belagod <tejas.belagod@arm.com>
357 Yufeng Zhang <yufeng.zhang@arm.com>
359 * aarch64.h: New file.
361 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
362 Maciej W. Rozycki <macro@codesourcery.com>
364 * mips.h (mips_opcode): Add the exclusions field.
365 (OPCODE_IS_MEMBER): Remove macro.
366 (cpu_is_member): New inline function.
367 (opcode_is_member): Likewise.
369 2012-07-31 Chao-Ying Fu <fu@mips.com>
370 Catherine Moore <clm@codesourcery.com>
371 Maciej W. Rozycki <macro@codesourcery.com>
373 * mips.h: Document microMIPS DSP ASE usage.
374 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
375 microMIPS DSP ASE support.
376 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
377 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
378 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
379 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
380 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
381 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
382 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
384 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
386 * mips.h: Fix a typo in description.
388 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
390 * avr.h: (AVR_ISA_XCH): New define.
391 (AVR_ISA_XMEGA): Use it.
392 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
394 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
396 * m68hc11.h: Add XGate definitions.
397 (struct m68hc11_opcode): Add xg_mask field.
399 2012-05-14 Catherine Moore <clm@codesourcery.com>
400 Maciej W. Rozycki <macro@codesourcery.com>
401 Rhonda Wittels <rhonda@codesourcery.com>
403 * ppc.h (PPC_OPCODE_VLE): New definition.
404 (PPC_OP_SA): New macro.
405 (PPC_OP_SE_VLE): New macro.
406 (PPC_OP): Use a variable shift amount.
407 (powerpc_operand): Update comments.
408 (PPC_OPSHIFT_INV): New macro.
409 (PPC_OPERAND_CR): Replace with...
410 (PPC_OPERAND_CR_BIT): ...this and
411 (PPC_OPERAND_CR_REG): ...this.
414 2012-05-03 Sean Keys <skeys@ipdatasys.com>
416 * xgate.h: Header file for XGATE assembler.
418 2012-04-27 David S. Miller <davem@davemloft.net>
420 * sparc.h: Document new arg code' )' for crypto RS3
423 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
424 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
425 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
426 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
427 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
428 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
429 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
430 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
431 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
432 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
433 HWCAP_CBCOND, HWCAP_CRC32): New defines.
435 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
437 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
439 2012-02-27 Alan Modra <amodra@gmail.com>
441 * crx.h (cst4_map): Update declaration.
443 2012-02-25 Walter Lee <walt@tilera.com>
445 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
447 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
448 TILEPRO_OPC_LW_TLS_SN.
450 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
452 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
453 (XRELEASE_PREFIX_OPCODE): Likewise.
455 2011-12-08 Andrew Pinski <apinski@cavium.com>
456 Adam Nemet <anemet@caviumnetworks.com>
458 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
459 (INSN_OCTEON2): New macro.
460 (CPU_OCTEON2): New macro.
461 (OPCODE_IS_MEMBER): Add Octeon2.
463 2011-11-29 Andrew Pinski <apinski@cavium.com>
465 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
466 (INSN_OCTEONP): New macro.
467 (CPU_OCTEONP): New macro.
468 (OPCODE_IS_MEMBER): Add Octeon+.
469 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
471 2011-11-01 DJ Delorie <dj@redhat.com>
475 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
477 * mips.h: Fix a typo in description.
479 2011-09-21 David S. Miller <davem@davemloft.net>
481 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
482 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
483 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
484 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
486 2011-08-09 Chao-ying Fu <fu@mips.com>
487 Maciej W. Rozycki <macro@codesourcery.com>
489 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
490 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
491 (INSN_ASE_MASK): Add the MCU bit.
492 (INSN_MCU): New macro.
493 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
494 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
496 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
498 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
499 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
500 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
501 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
502 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
503 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
504 (INSN2_READ_GPR_MMN): Likewise.
505 (INSN2_READ_FPR_D): Change the bit used.
506 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
507 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
508 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
509 (INSN2_COND_BRANCH): Likewise.
510 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
511 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
512 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
513 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
514 (INSN2_MOD_GPR_MN): Likewise.
516 2011-08-05 David S. Miller <davem@davemloft.net>
518 * sparc.h: Document new format codes '4', '5', and '('.
519 (OPF_LOW4, RS3): New macros.
521 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
523 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
524 order of flags documented.
526 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
528 * mips.h: Clarify the description of microMIPS instruction
530 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
532 2011-07-24 Chao-ying Fu <fu@mips.com>
533 Maciej W. Rozycki <macro@codesourcery.com>
535 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
536 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
537 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
538 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
539 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
540 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
541 (OP_MASK_RS3, OP_SH_RS3): Likewise.
542 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
543 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
544 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
545 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
546 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
547 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
548 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
549 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
550 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
551 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
552 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
553 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
554 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
555 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
556 (INSN_WRITE_GPR_S): New macro.
557 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
558 (INSN2_READ_FPR_D): Likewise.
559 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
560 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
561 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
562 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
563 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
564 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
565 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
566 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
567 (CPU_MICROMIPS): New macro.
568 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
569 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
570 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
571 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
572 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
573 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
574 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
575 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
576 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
577 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
578 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
579 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
580 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
581 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
582 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
583 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
584 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
585 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
586 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
587 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
588 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
589 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
590 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
591 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
592 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
593 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
594 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
595 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
596 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
597 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
598 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
599 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
600 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
601 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
602 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
603 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
604 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
605 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
606 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
607 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
608 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
609 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
610 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
611 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
612 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
613 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
614 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
615 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
616 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
617 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
618 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
619 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
620 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
621 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
622 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
623 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
624 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
625 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
626 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
627 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
628 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
629 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
630 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
631 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
632 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
633 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
634 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
635 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
636 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
637 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
638 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
639 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
640 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
641 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
642 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
643 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
644 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
645 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
646 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
647 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
648 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
649 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
650 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
651 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
652 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
653 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
654 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
655 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
656 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
657 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
658 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
659 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
660 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
661 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
662 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
663 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
664 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
665 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
666 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
667 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
668 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
669 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
670 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
671 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
672 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
673 (micromips_opcodes): New declaration.
674 (bfd_micromips_num_opcodes): Likewise.
676 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
678 * mips.h (INSN_TRAP): Rename to...
679 (INSN_NO_DELAY_SLOT): ... this.
680 (INSN_SYNC): Remove macro.
682 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
684 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
685 a duplicate of AVR_ISA_SPM.
687 2011-07-01 Nick Clifton <nickc@redhat.com>
689 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
691 2011-06-18 Robin Getz <robin.getz@analog.com>
693 * bfin.h (is_macmod_signed): New func
695 2011-06-18 Mike Frysinger <vapier@gentoo.org>
697 * bfin.h (is_macmod_pmove): Add missing space before func args.
698 (is_macmod_hmove): Likewise.
700 2011-06-13 Walter Lee <walt@tilera.com>
702 * tilegx.h: New file.
703 * tilepro.h: New file.
705 2011-05-31 Paul Brook <paul@codesourcery.com>
707 * arm.h (ARM_ARCH_V7R_IDIV): Define.
709 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
711 * s390.h: Replace S390_OPERAND_REG_EVEN with
712 S390_OPERAND_REG_PAIR.
714 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
716 * s390.h: Add S390_OPCODE_REG_EVEN flag.
718 2011-04-18 Julian Brown <julian@codesourcery.com>
720 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
722 2011-04-11 Dan McDonald <dan@wellkeeper.com>
725 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
727 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
729 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
730 New instruction set flags.
731 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
733 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
735 * mips.h (M_PREF_AB): New enum value.
737 2011-02-12 Mike Frysinger <vapier@gentoo.org>
739 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
741 (is_macmod_pmove, is_macmod_hmove): New functions.
743 2011-02-11 Mike Frysinger <vapier@gentoo.org>
745 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
747 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
749 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
750 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
752 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
755 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
758 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
761 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
763 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
765 * mips.h: Update commentary after last commit.
767 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
769 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
770 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
771 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
773 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
775 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
777 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
779 * mips.h: Fix previous commit.
781 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
783 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
784 (INSN_LOONGSON_3A): Clear bit 31.
786 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
789 * arm.h (ARM_AEXT_V6M_ONLY): New define.
790 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
791 (ARM_ARCH_V6M_ONLY): New define.
793 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
795 * mips.h (INSN_LOONGSON_3A): Defined.
796 (CPU_LOONGSON_3A): Defined.
797 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
799 2010-10-09 Matt Rice <ratmice@gmail.com>
801 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
802 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
804 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
806 * arm.h (ARM_EXT_VIRT): New define.
807 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
808 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
811 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
813 * arm.h (ARM_AEXT_ADIV): New define.
814 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
816 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
818 * arm.h (ARM_EXT_OS): New define.
819 (ARM_AEXT_V6SM): Likewise.
820 (ARM_ARCH_V6SM): Likewise.
822 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
824 * arm.h (ARM_EXT_MP): Add.
825 (ARM_ARCH_V7A_MP): Likewise.
827 2010-09-22 Mike Frysinger <vapier@gentoo.org>
829 * bfin.h: Declare pseudoChr structs/defines.
831 2010-09-21 Mike Frysinger <vapier@gentoo.org>
833 * bfin.h: Strip trailing whitespace.
835 2010-07-29 DJ Delorie <dj@redhat.com>
837 * rx.h (RX_Operand_Type): Add TwoReg.
838 (RX_Opcode_ID): Remove ediv and ediv2.
840 2010-07-27 DJ Delorie <dj@redhat.com>
842 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
844 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
845 Ina Pandit <ina.pandit@kpitcummins.com>
847 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
848 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
849 PROCESSOR_V850E2_ALL.
850 Remove PROCESSOR_V850EA support.
851 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
852 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
853 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
854 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
855 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
856 V850_OPERAND_PERCENT.
857 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
859 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
862 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
864 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
865 (MIPS16_INSN_BRANCH): Rename to...
866 (MIPS16_INSN_COND_BRANCH): ... this.
868 2010-07-03 Alan Modra <amodra@gmail.com>
870 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
871 Renumber other PPC_OPCODE defines.
873 2010-07-03 Alan Modra <amodra@gmail.com>
875 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
877 2010-06-29 Alan Modra <amodra@gmail.com>
879 * maxq.h: Delete file.
881 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
883 * ppc.h (PPC_OPCODE_E500): Define.
885 2010-05-26 Catherine Moore <clm@codesourcery.com>
887 * opcode/mips.h (INSN_MIPS16): Remove.
889 2010-04-21 Joseph Myers <joseph@codesourcery.com>
891 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
893 2010-04-15 Nick Clifton <nickc@redhat.com>
895 * alpha.h: Update copyright notice to use GPLv3.
901 * convex.h: Likewise.
915 * m68hc11.h: Likewise.
921 * mn10200.h: Likewise.
922 * mn10300.h: Likewise.
923 * msp430.h: Likewise.
934 * score-datadep.h: Likewise.
935 * score-inst.h: Likewise.
937 * spu-insns.h: Likewise.
941 * tic54x.h: Likewise.
946 2010-03-25 Joseph Myers <joseph@codesourcery.com>
948 * tic6x-control-registers.h, tic6x-insn-formats.h,
949 tic6x-opcode-table.h, tic6x.h: New.
951 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
953 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
955 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
957 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
959 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
961 * ia64.h (ia64_find_opcode): Remove argument name.
962 (ia64_find_next_opcode): Likewise.
963 (ia64_dis_opcode): Likewise.
964 (ia64_free_opcode): Likewise.
965 (ia64_find_dependency): Likewise.
967 2009-11-22 Doug Evans <dje@sebabeach.org>
969 * cgen.h: Include bfd_stdint.h.
970 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
972 2009-11-18 Paul Brook <paul@codesourcery.com>
974 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
976 2009-11-17 Paul Brook <paul@codesourcery.com>
977 Daniel Jacobowitz <dan@codesourcery.com>
979 * arm.h (ARM_EXT_V6_DSP): Define.
980 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
981 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
983 2009-11-04 DJ Delorie <dj@redhat.com>
985 * rx.h (rx_decode_opcode) (mvtipl): Add.
986 (mvtcp, mvfcp, opecp): Remove.
988 2009-11-02 Paul Brook <paul@codesourcery.com>
990 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
991 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
992 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
993 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
994 FPU_ARCH_NEON_VFP_V4): Define.
996 2009-10-23 Doug Evans <dje@sebabeach.org>
998 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
999 * cgen.h: Update. Improve multi-inclusion macro name.
1001 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1003 * ppc.h (PPC_OPCODE_476): Define.
1005 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1007 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1009 2009-09-29 DJ Delorie <dj@redhat.com>
1013 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1015 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1017 2009-09-21 Ben Elliston <bje@au.ibm.com>
1019 * ppc.h (PPC_OPCODE_PPCA2): New.
1021 2009-09-05 Martin Thuresson <martin@mtme.org>
1023 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1025 2009-08-29 Martin Thuresson <martin@mtme.org>
1027 * tic30.h (template): Rename type template to
1028 insn_template. Updated code to use new name.
1029 * tic54x.h (template): Rename type template to
1032 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1034 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1036 2009-06-11 Anthony Green <green@moxielogic.com>
1038 * moxie.h (MOXIE_F3_PCREL): Define.
1039 (moxie_form3_opc_info): Grow.
1041 2009-06-06 Anthony Green <green@moxielogic.com>
1043 * moxie.h (MOXIE_F1_M): Define.
1045 2009-04-15 Anthony Green <green@moxielogic.com>
1049 2009-04-06 DJ Delorie <dj@redhat.com>
1051 * h8300.h: Add relaxation attributes to MOVA opcodes.
1053 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1055 * ppc.h (ppc_parse_cpu): Declare.
1057 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1059 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1060 and _IMM11 for mbitclr and mbitset.
1061 * score-datadep.h: Update dependency information.
1063 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1065 * ppc.h (PPC_OPCODE_POWER7): New.
1067 2009-02-06 Doug Evans <dje@google.com>
1069 * i386.h: Add comment regarding sse* insns and prefixes.
1071 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1073 * mips.h (INSN_XLR): Define.
1074 (INSN_CHIP_MASK): Update.
1076 (OPCODE_IS_MEMBER): Update.
1077 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1079 2009-01-28 Doug Evans <dje@google.com>
1081 * opcode/i386.h: Add multiple inclusion protection.
1082 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1083 (EDI_REG_NUM): New macros.
1084 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1085 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1086 (REX_PREFIX_P): New macro.
1088 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1090 * ppc.h (struct powerpc_opcode): New field "deprecated".
1091 (PPC_OPCODE_NOPOWER4): Delete.
1093 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1095 * mips.h: Define CPU_R14000, CPU_R16000.
1096 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1098 2008-11-18 Catherine Moore <clm@codesourcery.com>
1100 * arm.h (FPU_NEON_FP16): New.
1101 (FPU_ARCH_NEON_FP16): New.
1103 2008-11-06 Chao-ying Fu <fu@mips.com>
1105 * mips.h: Doucument '1' for 5-bit sync type.
1107 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1109 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1112 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1114 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1116 2008-07-30 Michael J. Eager <eager@eagercon.com>
1118 * ppc.h (PPC_OPCODE_405): Define.
1119 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1121 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1123 * ppc.h (ppc_cpu_t): New typedef.
1124 (struct powerpc_opcode <flags>): Use it.
1125 (struct powerpc_operand <insert, extract>): Likewise.
1126 (struct powerpc_macro <flags>): Likewise.
1128 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1130 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1131 Update comment before MIPS16 field descriptors to mention MIPS16.
1132 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1134 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1135 New bit masks and shift counts for cins and exts.
1137 * mips.h: Document new field descriptors +Q.
1138 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1140 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1142 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1143 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1145 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1147 * ppc.h: (PPC_OPCODE_E500MC): New.
1149 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1151 * i386.h (MAX_OPERANDS): Set to 5.
1152 (MAX_MNEM_SIZE): Changed to 20.
1154 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1156 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1158 2008-03-09 Paul Brook <paul@codesourcery.com>
1160 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1162 2008-03-04 Paul Brook <paul@codesourcery.com>
1164 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1165 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1166 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1168 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1169 Nick Clifton <nickc@redhat.com>
1172 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1173 with a 32-bit displacement but without the top bit of the 4th byte
1176 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1178 * cr16.h (cr16_num_optab): Declared.
1180 2008-02-14 Hakan Ardo <hakan@debian.org>
1183 * avr.h (AVR_ISA_2xxe): Define.
1185 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1187 * mips.h: Update copyright.
1188 (INSN_CHIP_MASK): New macro.
1189 (INSN_OCTEON): New macro.
1190 (CPU_OCTEON): New macro.
1191 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1193 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1195 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1197 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1199 * avr.h (AVR_ISA_USB162): Add new opcode set.
1200 (AVR_ISA_AVR3): Likewise.
1202 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1204 * mips.h (INSN_LOONGSON_2E): New.
1205 (INSN_LOONGSON_2F): New.
1206 (CPU_LOONGSON_2E): New.
1207 (CPU_LOONGSON_2F): New.
1208 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1210 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1212 * mips.h (INSN_ISA*): Redefine certain values as an
1213 enumeration. Update comments.
1214 (mips_isa_table): New.
1215 (ISA_MIPS*): Redefine to match enumeration.
1216 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1219 2007-08-08 Ben Elliston <bje@au.ibm.com>
1221 * ppc.h (PPC_OPCODE_PPCPS): New.
1223 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1225 * m68k.h: Document j K & E.
1227 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1229 * cr16.h: New file for CR16 target.
1231 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1233 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1235 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1237 * m68k.h (mcfisa_c): New.
1238 (mcfusp, mcf_mask): Adjust.
1240 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1242 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1243 (num_powerpc_operands): Declare.
1244 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1245 (PPC_OPERAND_PLUS1): Define.
1247 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1249 * i386.h (REX_MODE64): Renamed to ...
1251 (REX_EXTX): Renamed to ...
1253 (REX_EXTY): Renamed to ...
1255 (REX_EXTZ): Renamed to ...
1258 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1260 * i386.h: Add entries from config/tc-i386.h and move tables
1261 to opcodes/i386-opc.h.
1263 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1265 * i386.h (FloatDR): Removed.
1266 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1268 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1270 * spu-insns.h: Add soma double-float insns.
1272 2007-02-20 Thiemo Seufer <ths@mips.com>
1273 Chao-Ying Fu <fu@mips.com>
1275 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1276 (INSN_DSPR2): Add flag for DSP R2 instructions.
1277 (M_BALIGN): New macro.
1279 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1281 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1282 and Seg3ShortFrom with Shortform.
1284 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1287 * i386.h (i386_optab): Put the real "test" before the pseudo
1290 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1292 * m68k.h (m68010up): OR fido_a.
1294 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1296 * m68k.h (fido_a): New.
1298 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1300 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1301 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1304 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1306 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1308 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1310 * score-inst.h (enum score_insn_type): Add Insn_internal.
1312 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1313 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1314 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1315 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1316 Alan Modra <amodra@bigpond.net.au>
1318 * spu-insns.h: New file.
1321 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1323 * ppc.h (PPC_OPCODE_CELL): Define.
1325 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1327 * i386.h : Modify opcode to support for the change in POPCNT opcode
1328 in amdfam10 architecture.
1330 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1332 * i386.h: Replace CpuMNI with CpuSSSE3.
1334 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1335 Joseph Myers <joseph@codesourcery.com>
1336 Ian Lance Taylor <ian@wasabisystems.com>
1337 Ben Elliston <bje@wasabisystems.com>
1339 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1341 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1343 * score-datadep.h: New file.
1344 * score-inst.h: New file.
1346 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1348 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1349 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1350 movdq2q and movq2dq.
1352 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1353 Michael Meissner <michael.meissner@amd.com>
1355 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1357 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1359 * i386.h (i386_optab): Add "nop" with memory reference.
1361 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1363 * i386.h (i386_optab): Update comment for 64bit NOP.
1365 2006-06-06 Ben Elliston <bje@au.ibm.com>
1366 Anton Blanchard <anton@samba.org>
1368 * ppc.h (PPC_OPCODE_POWER6): Define.
1371 2006-06-05 Thiemo Seufer <ths@mips.com>
1373 * mips.h: Improve description of MT flags.
1375 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1377 * m68k.h (mcf_mask): Define.
1379 2006-05-05 Thiemo Seufer <ths@mips.com>
1380 David Ung <davidu@mips.com>
1382 * mips.h (enum): Add macro M_CACHE_AB.
1384 2006-05-04 Thiemo Seufer <ths@mips.com>
1385 Nigel Stephens <nigel@mips.com>
1386 David Ung <davidu@mips.com>
1388 * mips.h: Add INSN_SMARTMIPS define.
1390 2006-04-30 Thiemo Seufer <ths@mips.com>
1391 David Ung <davidu@mips.com>
1393 * mips.h: Defines udi bits and masks. Add description of
1394 characters which may appear in the args field of udi
1397 2006-04-26 Thiemo Seufer <ths@networkno.de>
1399 * mips.h: Improve comments describing the bitfield instruction
1402 2006-04-26 Julian Brown <julian@codesourcery.com>
1404 * arm.h (FPU_VFP_EXT_V3): Define constant.
1405 (FPU_NEON_EXT_V1): Likewise.
1406 (FPU_VFP_HARD): Update.
1407 (FPU_VFP_V3): Define macro.
1408 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1410 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1412 * avr.h (AVR_ISA_PWMx): New.
1414 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1416 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1417 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1418 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1419 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1420 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1422 2006-03-10 Paul Brook <paul@codesourcery.com>
1424 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1426 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1428 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1429 first. Correct mask of bb "B" opcode.
1431 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1433 * i386.h (i386_optab): Support Intel Merom New Instructions.
1435 2006-02-24 Paul Brook <paul@codesourcery.com>
1437 * arm.h: Add V7 feature bits.
1439 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1441 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1443 2006-01-31 Paul Brook <paul@codesourcery.com>
1444 Richard Earnshaw <rearnsha@arm.com>
1446 * arm.h: Use ARM_CPU_FEATURE.
1447 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1448 (arm_feature_set): Change to a structure.
1449 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1450 ARM_FEATURE): New macros.
1452 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1454 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1455 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1456 (ADD_PC_INCR_OPCODE): Don't define.
1458 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1461 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1463 2005-11-14 David Ung <davidu@mips.com>
1465 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1466 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1467 save/restore encoding of the args field.
1469 2005-10-28 Dave Brolley <brolley@redhat.com>
1471 Contribute the following changes:
1472 2005-02-16 Dave Brolley <brolley@redhat.com>
1474 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1475 cgen_isa_mask_* to cgen_bitset_*.
1478 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1480 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1481 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1482 (CGEN_CPU_TABLE): Make isas a ponter.
1484 2003-09-29 Dave Brolley <brolley@redhat.com>
1486 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1487 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1488 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1490 2002-12-13 Dave Brolley <brolley@redhat.com>
1492 * cgen.h (symcat.h): #include it.
1493 (cgen-bitset.h): #include it.
1494 (CGEN_ATTR_VALUE_TYPE): Now a union.
1495 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1496 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1497 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1498 * cgen-bitset.h: New file.
1500 2005-09-30 Catherine Moore <clm@cm00re.com>
1504 2005-10-24 Jan Beulich <jbeulich@novell.com>
1506 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1509 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1511 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1512 Add FLAG_STRICT to pa10 ftest opcode.
1514 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1516 * hppa.h (pa_opcodes): Remove lha entries.
1518 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1520 * hppa.h (FLAG_STRICT): Revise comment.
1521 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1522 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1525 2005-09-30 Catherine Moore <clm@cm00re.com>
1529 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1531 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1533 2005-09-06 Chao-ying Fu <fu@mips.com>
1535 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1536 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1538 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1539 (INSN_ASE_MASK): Update to include INSN_MT.
1540 (INSN_MT): New define for MT ASE.
1542 2005-08-25 Chao-ying Fu <fu@mips.com>
1544 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1545 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1546 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1547 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1548 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1549 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1551 (INSN_DSP): New define for DSP ASE.
1553 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1557 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1559 * ppc.h (PPC_OPCODE_E300): Define.
1561 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1563 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1565 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1568 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1571 2005-07-27 Jan Beulich <jbeulich@novell.com>
1573 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1574 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1575 Add movq-s as 64-bit variants of movd-s.
1577 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1579 * hppa.h: Fix punctuation in comment.
1581 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1582 implicit space-register addressing. Set space-register bits on opcodes
1583 using implicit space-register addressing. Add various missing pa20
1584 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1585 space-register addressing. Use "fE" instead of "fe" in various
1588 2005-07-18 Jan Beulich <jbeulich@novell.com>
1590 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1592 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1594 * i386.h (i386_optab): Support Intel VMX Instructions.
1596 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1598 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1600 2005-07-05 Jan Beulich <jbeulich@novell.com>
1602 * i386.h (i386_optab): Add new insns.
1604 2005-07-01 Nick Clifton <nickc@redhat.com>
1606 * sparc.h: Add typedefs to structure declarations.
1608 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1611 * i386.h (i386_optab): Update comments for 64bit addressing on
1612 mov. Allow 64bit addressing for mov and movq.
1614 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1616 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1617 respectively, in various floating-point load and store patterns.
1619 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1621 * hppa.h (FLAG_STRICT): Correct comment.
1622 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1623 PA 2.0 mneumonics when equivalent. Entries with cache control
1624 completers now require PA 1.1. Adjust whitespace.
1626 2005-05-19 Anton Blanchard <anton@samba.org>
1628 * ppc.h (PPC_OPCODE_POWER5): Define.
1630 2005-05-10 Nick Clifton <nickc@redhat.com>
1632 * Update the address and phone number of the FSF organization in
1633 the GPL notices in the following files:
1634 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1635 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1636 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1637 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1638 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1639 tic54x.h, tic80.h, v850.h, vax.h
1641 2005-05-09 Jan Beulich <jbeulich@novell.com>
1643 * i386.h (i386_optab): Add ht and hnt.
1645 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1647 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1648 Add xcrypt-ctr. Provide aliases without hyphens.
1650 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1652 Moved from ../ChangeLog
1654 2005-04-12 Paul Brook <paul@codesourcery.com>
1655 * m88k.h: Rename psr macros to avoid conflicts.
1657 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1658 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1659 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1660 and ARM_ARCH_V6ZKT2.
1662 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1663 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1664 Remove redundant instruction types.
1665 (struct argument): X_op - new field.
1666 (struct cst4_entry): Remove.
1667 (no_op_insn): Declare.
1669 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1670 * crx.h (enum argtype): Rename types, remove unused types.
1672 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1673 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1674 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1675 (enum operand_type): Rearrange operands, edit comments.
1676 replace us<N> with ui<N> for unsigned immediate.
1677 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1678 displacements (respectively).
1679 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1680 (instruction type): Add NO_TYPE_INS.
1681 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1682 (operand_entry): New field - 'flags'.
1683 (operand flags): New.
1685 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1686 * crx.h (operand_type): Remove redundant types i3, i4,
1688 Add new unsigned immediate types us3, us4, us5, us16.
1690 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1692 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1693 adjust them accordingly.
1695 2005-04-01 Jan Beulich <jbeulich@novell.com>
1697 * i386.h (i386_optab): Add rdtscp.
1699 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1701 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1702 between memory and segment register. Allow movq for moving between
1703 general-purpose register and segment register.
1705 2005-02-09 Jan Beulich <jbeulich@novell.com>
1708 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1709 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1712 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1714 * m68k.h (m68008, m68ec030, m68882): Remove.
1716 (cpu_m68k, cpu_cf): New.
1717 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1718 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1720 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1722 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1723 * cgen.h (enum cgen_parse_operand_type): Add
1724 CGEN_PARSE_OPERAND_SYMBOLIC.
1726 2005-01-21 Fred Fish <fnf@specifixinc.com>
1728 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1729 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1730 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1732 2005-01-19 Fred Fish <fnf@specifixinc.com>
1734 * mips.h (struct mips_opcode): Add new pinfo2 member.
1735 (INSN_ALIAS): New define for opcode table entries that are
1736 specific instances of another entry, such as 'move' for an 'or'
1737 with a zero operand.
1738 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1739 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1741 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1743 * mips.h (CPU_RM9000): Define.
1744 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1746 2004-11-25 Jan Beulich <jbeulich@novell.com>
1748 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1749 to/from test registers are illegal in 64-bit mode. Add missing
1750 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1751 (previously one had to explicitly encode a rex64 prefix). Re-enable
1752 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1753 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1755 2004-11-23 Jan Beulich <jbeulich@novell.com>
1757 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1758 available only with SSE2. Change the MMX additions introduced by SSE
1759 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1760 instructions by their now designated identifier (since combining i686
1761 and 3DNow! does not really imply 3DNow!A).
1763 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1765 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1766 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1768 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1769 Vineet Sharma <vineets@noida.hcltech.com>
1771 * maxq.h: New file: Disassembly information for the maxq port.
1773 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1775 * i386.h (i386_optab): Put back "movzb".
1777 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1779 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1780 comments. Remove member cris_ver_sim. Add members
1781 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1782 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1783 (struct cris_support_reg, struct cris_cond15): New types.
1784 (cris_conds15): Declare.
1785 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1786 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1787 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1788 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1789 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1790 SIZE_FIELD_UNSIGNED.
1792 2004-11-04 Jan Beulich <jbeulich@novell.com>
1794 * i386.h (sldx_Suf): Remove.
1795 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1796 (q_FP): Define, implying no REX64.
1797 (x_FP, sl_FP): Imply FloatMF.
1798 (i386_optab): Split reg and mem forms of moving from segment registers
1799 so that the memory forms can ignore the 16-/32-bit operand size
1800 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1801 all non-floating-point instructions. Unite 32- and 64-bit forms of
1802 movsx, movzx, and movd. Adjust floating point operations for the above
1803 changes to the *FP macros. Add DefaultSize to floating point control
1804 insns operating on larger memory ranges. Remove left over comments
1805 hinting at certain insns being Intel-syntax ones where the ones
1806 actually meant are already gone.
1808 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1810 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1813 2004-09-30 Paul Brook <paul@codesourcery.com>
1815 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1816 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1818 2004-09-11 Theodore A. Roth <troth@openavr.org>
1820 * avr.h: Add support for
1821 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1823 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1825 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1827 2004-08-24 Dmitry Diky <diwil@spec.ru>
1829 * msp430.h (msp430_opc): Add new instructions.
1830 (msp430_rcodes): Declare new instructions.
1831 (msp430_hcodes): Likewise..
1833 2004-08-13 Nick Clifton <nickc@redhat.com>
1836 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1839 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1841 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1843 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1845 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1847 2004-07-21 Jan Beulich <jbeulich@novell.com>
1849 * i386.h: Adjust instruction descriptions to better match the
1852 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1854 * arm.h: Remove all old content. Replace with architecture defines
1855 from gas/config/tc-arm.c.
1857 2004-07-09 Andreas Schwab <schwab@suse.de>
1859 * m68k.h: Fix comment.
1861 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1865 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1867 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1869 2004-05-24 Peter Barada <peter@the-baradas.com>
1871 * m68k.h: Add 'size' to m68k_opcode.
1873 2004-05-05 Peter Barada <peter@the-baradas.com>
1875 * m68k.h: Switch from ColdFire chip name to core variant.
1877 2004-04-22 Peter Barada <peter@the-baradas.com>
1879 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1880 descriptions for new EMAC cases.
1881 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1882 handle Motorola MAC syntax.
1883 Allow disassembly of ColdFire V4e object files.
1885 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1887 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1889 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1891 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1893 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1895 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1897 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1899 * i386.h (i386_optab): Added xstore/xcrypt insns.
1901 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1903 * h8300.h (32bit ldc/stc): Add relaxing support.
1905 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1907 * h8300.h (BITOP): Pass MEMRELAX flag.
1909 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1911 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1914 For older changes see ChangeLog-9103
1916 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1918 Copying and distribution of this file, with or without modification,
1919 are permitted in any medium without royalty provided the copyright
1920 notice and this notice are preserved.
1926 version-control: never