1 2010-05-26 Catherine Moore <clm@codesourcery.com>
3 * opcode/mips.h (INSN_MIPS16): Remove.
5 2010-04-21 Joseph Myers <joseph@codesourcery.com>
7 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
9 2010-04-15 Nick Clifton <nickc@redhat.com>
11 * alpha.h: Update copyright notice to use GPLv3.
31 * m68hc11.h: Likewise.
37 * mn10200.h: Likewise.
38 * mn10300.h: Likewise.
50 * score-datadep.h: Likewise.
51 * score-inst.h: Likewise.
53 * spu-insns.h: Likewise.
62 2010-03-25 Joseph Myers <joseph@codesourcery.com>
64 * tic6x-control-registers.h, tic6x-insn-formats.h,
65 tic6x-opcode-table.h, tic6x.h: New.
67 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
69 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
71 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
73 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
75 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
77 * ia64.h (ia64_find_opcode): Remove argument name.
78 (ia64_find_next_opcode): Likewise.
79 (ia64_dis_opcode): Likewise.
80 (ia64_free_opcode): Likewise.
81 (ia64_find_dependency): Likewise.
83 2009-11-22 Doug Evans <dje@sebabeach.org>
85 * cgen.h: Include bfd_stdint.h.
86 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
88 2009-11-18 Paul Brook <paul@codesourcery.com>
90 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
92 2009-11-17 Paul Brook <paul@codesourcery.com>
93 Daniel Jacobowitz <dan@codesourcery.com>
95 * arm.h (ARM_EXT_V6_DSP): Define.
96 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
97 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
99 2009-11-04 DJ Delorie <dj@redhat.com>
101 * rx.h (rx_decode_opcode) (mvtipl): Add.
102 (mvtcp, mvfcp, opecp): Remove.
104 2009-11-02 Paul Brook <paul@codesourcery.com>
106 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
107 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
108 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
109 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
110 FPU_ARCH_NEON_VFP_V4): Define.
112 2009-10-23 Doug Evans <dje@sebabeach.org>
114 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
115 * cgen.h: Update. Improve multi-inclusion macro name.
117 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
119 * ppc.h (PPC_OPCODE_476): Define.
121 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
123 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
125 2009-09-29 DJ Delorie <dj@redhat.com>
129 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
131 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
133 2009-09-21 Ben Elliston <bje@au.ibm.com>
135 * ppc.h (PPC_OPCODE_PPCA2): New.
137 2009-09-05 Martin Thuresson <martin@mtme.org>
139 * ia64.h (struct ia64_operand): Renamed member class to op_class.
141 2009-08-29 Martin Thuresson <martin@mtme.org>
143 * tic30.h (template): Rename type template to
144 insn_template. Updated code to use new name.
145 * tic54x.h (template): Rename type template to
148 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
150 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
152 2009-06-11 Anthony Green <green@moxielogic.com>
154 * moxie.h (MOXIE_F3_PCREL): Define.
155 (moxie_form3_opc_info): Grow.
157 2009-06-06 Anthony Green <green@moxielogic.com>
159 * moxie.h (MOXIE_F1_M): Define.
161 2009-04-15 Anthony Green <green@moxielogic.com>
165 2009-04-06 DJ Delorie <dj@redhat.com>
167 * h8300.h: Add relaxation attributes to MOVA opcodes.
169 2009-03-10 Alan Modra <amodra@bigpond.net.au>
171 * ppc.h (ppc_parse_cpu): Declare.
173 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
175 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
176 and _IMM11 for mbitclr and mbitset.
177 * score-datadep.h: Update dependency information.
179 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
181 * ppc.h (PPC_OPCODE_POWER7): New.
183 2009-02-06 Doug Evans <dje@google.com>
185 * i386.h: Add comment regarding sse* insns and prefixes.
187 2009-02-03 Sandip Matte <sandip@rmicorp.com>
189 * mips.h (INSN_XLR): Define.
190 (INSN_CHIP_MASK): Update.
192 (OPCODE_IS_MEMBER): Update.
193 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
195 2009-01-28 Doug Evans <dje@google.com>
197 * opcode/i386.h: Add multiple inclusion protection.
198 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
199 (EDI_REG_NUM): New macros.
200 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
201 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
202 (REX_PREFIX_P): New macro.
204 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
206 * ppc.h (struct powerpc_opcode): New field "deprecated".
207 (PPC_OPCODE_NOPOWER4): Delete.
209 2008-11-28 Joshua Kinard <kumba@gentoo.org>
211 * mips.h: Define CPU_R14000, CPU_R16000.
212 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
214 2008-11-18 Catherine Moore <clm@codesourcery.com>
216 * arm.h (FPU_NEON_FP16): New.
217 (FPU_ARCH_NEON_FP16): New.
219 2008-11-06 Chao-ying Fu <fu@mips.com>
221 * mips.h: Doucument '1' for 5-bit sync type.
223 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
225 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
228 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
230 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
232 2008-07-30 Michael J. Eager <eager@eagercon.com>
234 * ppc.h (PPC_OPCODE_405): Define.
235 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
237 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
239 * ppc.h (ppc_cpu_t): New typedef.
240 (struct powerpc_opcode <flags>): Use it.
241 (struct powerpc_operand <insert, extract>): Likewise.
242 (struct powerpc_macro <flags>): Likewise.
244 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
246 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
247 Update comment before MIPS16 field descriptors to mention MIPS16.
248 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
250 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
251 New bit masks and shift counts for cins and exts.
253 * mips.h: Document new field descriptors +Q.
254 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
256 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
258 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
259 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
261 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
263 * ppc.h: (PPC_OPCODE_E500MC): New.
265 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
267 * i386.h (MAX_OPERANDS): Set to 5.
268 (MAX_MNEM_SIZE): Changed to 20.
270 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
272 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
274 2008-03-09 Paul Brook <paul@codesourcery.com>
276 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
278 2008-03-04 Paul Brook <paul@codesourcery.com>
280 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
281 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
282 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
284 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
285 Nick Clifton <nickc@redhat.com>
288 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
289 with a 32-bit displacement but without the top bit of the 4th byte
292 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
294 * cr16.h (cr16_num_optab): Declared.
296 2008-02-14 Hakan Ardo <hakan@debian.org>
299 * avr.h (AVR_ISA_2xxe): Define.
301 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
303 * mips.h: Update copyright.
304 (INSN_CHIP_MASK): New macro.
305 (INSN_OCTEON): New macro.
306 (CPU_OCTEON): New macro.
307 (OPCODE_IS_MEMBER): Handle Octeon instructions.
309 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
311 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
313 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
315 * avr.h (AVR_ISA_USB162): Add new opcode set.
316 (AVR_ISA_AVR3): Likewise.
318 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
320 * mips.h (INSN_LOONGSON_2E): New.
321 (INSN_LOONGSON_2F): New.
322 (CPU_LOONGSON_2E): New.
323 (CPU_LOONGSON_2F): New.
324 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
326 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
328 * mips.h (INSN_ISA*): Redefine certain values as an
329 enumeration. Update comments.
330 (mips_isa_table): New.
331 (ISA_MIPS*): Redefine to match enumeration.
332 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
335 2007-08-08 Ben Elliston <bje@au.ibm.com>
337 * ppc.h (PPC_OPCODE_PPCPS): New.
339 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
341 * m68k.h: Document j K & E.
343 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
345 * cr16.h: New file for CR16 target.
347 2007-05-02 Alan Modra <amodra@bigpond.net.au>
349 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
351 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
353 * m68k.h (mcfisa_c): New.
354 (mcfusp, mcf_mask): Adjust.
356 2007-04-20 Alan Modra <amodra@bigpond.net.au>
358 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
359 (num_powerpc_operands): Declare.
360 (PPC_OPERAND_SIGNED et al): Redefine as hex.
361 (PPC_OPERAND_PLUS1): Define.
363 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
365 * i386.h (REX_MODE64): Renamed to ...
367 (REX_EXTX): Renamed to ...
369 (REX_EXTY): Renamed to ...
371 (REX_EXTZ): Renamed to ...
374 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
376 * i386.h: Add entries from config/tc-i386.h and move tables
377 to opcodes/i386-opc.h.
379 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
381 * i386.h (FloatDR): Removed.
382 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
384 2007-03-01 Alan Modra <amodra@bigpond.net.au>
386 * spu-insns.h: Add soma double-float insns.
388 2007-02-20 Thiemo Seufer <ths@mips.com>
389 Chao-Ying Fu <fu@mips.com>
391 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
392 (INSN_DSPR2): Add flag for DSP R2 instructions.
393 (M_BALIGN): New macro.
395 2007-02-14 Alan Modra <amodra@bigpond.net.au>
397 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
398 and Seg3ShortFrom with Shortform.
400 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
403 * i386.h (i386_optab): Put the real "test" before the pseudo
406 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
408 * m68k.h (m68010up): OR fido_a.
410 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
412 * m68k.h (fido_a): New.
414 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
416 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
417 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
420 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
422 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
424 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
426 * score-inst.h (enum score_insn_type): Add Insn_internal.
428 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
429 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
430 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
431 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
432 Alan Modra <amodra@bigpond.net.au>
434 * spu-insns.h: New file.
437 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
439 * ppc.h (PPC_OPCODE_CELL): Define.
441 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
443 * i386.h : Modify opcode to support for the change in POPCNT opcode
444 in amdfam10 architecture.
446 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
448 * i386.h: Replace CpuMNI with CpuSSSE3.
450 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
451 Joseph Myers <joseph@codesourcery.com>
452 Ian Lance Taylor <ian@wasabisystems.com>
453 Ben Elliston <bje@wasabisystems.com>
455 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
457 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
459 * score-datadep.h: New file.
460 * score-inst.h: New file.
462 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
464 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
465 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
468 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
469 Michael Meissner <michael.meissner@amd.com>
471 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
473 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
475 * i386.h (i386_optab): Add "nop" with memory reference.
477 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
479 * i386.h (i386_optab): Update comment for 64bit NOP.
481 2006-06-06 Ben Elliston <bje@au.ibm.com>
482 Anton Blanchard <anton@samba.org>
484 * ppc.h (PPC_OPCODE_POWER6): Define.
487 2006-06-05 Thiemo Seufer <ths@mips.com>
489 * mips.h: Improve description of MT flags.
491 2006-05-25 Richard Sandiford <richard@codesourcery.com>
493 * m68k.h (mcf_mask): Define.
495 2006-05-05 Thiemo Seufer <ths@mips.com>
496 David Ung <davidu@mips.com>
498 * mips.h (enum): Add macro M_CACHE_AB.
500 2006-05-04 Thiemo Seufer <ths@mips.com>
501 Nigel Stephens <nigel@mips.com>
502 David Ung <davidu@mips.com>
504 * mips.h: Add INSN_SMARTMIPS define.
506 2006-04-30 Thiemo Seufer <ths@mips.com>
507 David Ung <davidu@mips.com>
509 * mips.h: Defines udi bits and masks. Add description of
510 characters which may appear in the args field of udi
513 2006-04-26 Thiemo Seufer <ths@networkno.de>
515 * mips.h: Improve comments describing the bitfield instruction
518 2006-04-26 Julian Brown <julian@codesourcery.com>
520 * arm.h (FPU_VFP_EXT_V3): Define constant.
521 (FPU_NEON_EXT_V1): Likewise.
522 (FPU_VFP_HARD): Update.
523 (FPU_VFP_V3): Define macro.
524 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
526 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
528 * avr.h (AVR_ISA_PWMx): New.
530 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
532 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
533 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
534 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
535 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
536 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
538 2006-03-10 Paul Brook <paul@codesourcery.com>
540 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
542 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
544 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
545 first. Correct mask of bb "B" opcode.
547 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
549 * i386.h (i386_optab): Support Intel Merom New Instructions.
551 2006-02-24 Paul Brook <paul@codesourcery.com>
553 * arm.h: Add V7 feature bits.
555 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
557 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
559 2006-01-31 Paul Brook <paul@codesourcery.com>
560 Richard Earnshaw <rearnsha@arm.com>
562 * arm.h: Use ARM_CPU_FEATURE.
563 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
564 (arm_feature_set): Change to a structure.
565 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
566 ARM_FEATURE): New macros.
568 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
570 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
571 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
572 (ADD_PC_INCR_OPCODE): Don't define.
574 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
577 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
579 2005-11-14 David Ung <davidu@mips.com>
581 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
582 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
583 save/restore encoding of the args field.
585 2005-10-28 Dave Brolley <brolley@redhat.com>
587 Contribute the following changes:
588 2005-02-16 Dave Brolley <brolley@redhat.com>
590 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
591 cgen_isa_mask_* to cgen_bitset_*.
594 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
596 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
597 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
598 (CGEN_CPU_TABLE): Make isas a ponter.
600 2003-09-29 Dave Brolley <brolley@redhat.com>
602 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
603 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
604 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
606 2002-12-13 Dave Brolley <brolley@redhat.com>
608 * cgen.h (symcat.h): #include it.
609 (cgen-bitset.h): #include it.
610 (CGEN_ATTR_VALUE_TYPE): Now a union.
611 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
612 (CGEN_ATTR_ENTRY): 'value' now unsigned.
613 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
614 * cgen-bitset.h: New file.
616 2005-09-30 Catherine Moore <clm@cm00re.com>
620 2005-10-24 Jan Beulich <jbeulich@novell.com>
622 * ia64.h (enum ia64_opnd): Move memory operand out of set of
625 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
627 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
628 Add FLAG_STRICT to pa10 ftest opcode.
630 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
632 * hppa.h (pa_opcodes): Remove lha entries.
634 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
636 * hppa.h (FLAG_STRICT): Revise comment.
637 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
638 before corresponding pa11 opcodes. Add strict pa10 register-immediate
641 2005-09-30 Catherine Moore <clm@cm00re.com>
645 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
647 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
649 2005-09-06 Chao-ying Fu <fu@mips.com>
651 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
652 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
654 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
655 (INSN_ASE_MASK): Update to include INSN_MT.
656 (INSN_MT): New define for MT ASE.
658 2005-08-25 Chao-ying Fu <fu@mips.com>
660 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
661 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
662 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
663 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
664 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
665 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
667 (INSN_DSP): New define for DSP ASE.
669 2005-08-18 Alan Modra <amodra@bigpond.net.au>
673 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
675 * ppc.h (PPC_OPCODE_E300): Define.
677 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
679 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
681 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
684 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
687 2005-07-27 Jan Beulich <jbeulich@novell.com>
689 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
690 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
691 Add movq-s as 64-bit variants of movd-s.
693 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
695 * hppa.h: Fix punctuation in comment.
697 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
698 implicit space-register addressing. Set space-register bits on opcodes
699 using implicit space-register addressing. Add various missing pa20
700 long-immediate opcodes. Remove various opcodes using implicit 3-bit
701 space-register addressing. Use "fE" instead of "fe" in various
704 2005-07-18 Jan Beulich <jbeulich@novell.com>
706 * i386.h (i386_optab): Operands of aam and aad are unsigned.
708 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
710 * i386.h (i386_optab): Support Intel VMX Instructions.
712 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
714 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
716 2005-07-05 Jan Beulich <jbeulich@novell.com>
718 * i386.h (i386_optab): Add new insns.
720 2005-07-01 Nick Clifton <nickc@redhat.com>
722 * sparc.h: Add typedefs to structure declarations.
724 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
727 * i386.h (i386_optab): Update comments for 64bit addressing on
728 mov. Allow 64bit addressing for mov and movq.
730 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
732 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
733 respectively, in various floating-point load and store patterns.
735 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
737 * hppa.h (FLAG_STRICT): Correct comment.
738 (pa_opcodes): Update load and store entries to allow both PA 1.X and
739 PA 2.0 mneumonics when equivalent. Entries with cache control
740 completers now require PA 1.1. Adjust whitespace.
742 2005-05-19 Anton Blanchard <anton@samba.org>
744 * ppc.h (PPC_OPCODE_POWER5): Define.
746 2005-05-10 Nick Clifton <nickc@redhat.com>
748 * Update the address and phone number of the FSF organization in
749 the GPL notices in the following files:
750 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
751 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
752 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
753 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
754 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
755 tic54x.h, tic80.h, v850.h, vax.h
757 2005-05-09 Jan Beulich <jbeulich@novell.com>
759 * i386.h (i386_optab): Add ht and hnt.
761 2005-04-18 Mark Kettenis <kettenis@gnu.org>
763 * i386.h: Insert hyphens into selected VIA PadLock extensions.
764 Add xcrypt-ctr. Provide aliases without hyphens.
766 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
768 Moved from ../ChangeLog
770 2005-04-12 Paul Brook <paul@codesourcery.com>
771 * m88k.h: Rename psr macros to avoid conflicts.
773 2005-03-12 Zack Weinberg <zack@codesourcery.com>
774 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
775 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
778 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
779 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
780 Remove redundant instruction types.
781 (struct argument): X_op - new field.
782 (struct cst4_entry): Remove.
783 (no_op_insn): Declare.
785 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
786 * crx.h (enum argtype): Rename types, remove unused types.
788 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
789 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
790 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
791 (enum operand_type): Rearrange operands, edit comments.
792 replace us<N> with ui<N> for unsigned immediate.
793 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
794 displacements (respectively).
795 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
796 (instruction type): Add NO_TYPE_INS.
797 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
798 (operand_entry): New field - 'flags'.
799 (operand flags): New.
801 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
802 * crx.h (operand_type): Remove redundant types i3, i4,
804 Add new unsigned immediate types us3, us4, us5, us16.
806 2005-04-12 Mark Kettenis <kettenis@gnu.org>
808 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
809 adjust them accordingly.
811 2005-04-01 Jan Beulich <jbeulich@novell.com>
813 * i386.h (i386_optab): Add rdtscp.
815 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
817 * i386.h (i386_optab): Don't allow the `l' suffix for moving
818 between memory and segment register. Allow movq for moving between
819 general-purpose register and segment register.
821 2005-02-09 Jan Beulich <jbeulich@novell.com>
824 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
825 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
828 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
830 * m68k.h (m68008, m68ec030, m68882): Remove.
832 (cpu_m68k, cpu_cf): New.
833 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
834 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
836 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
838 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
839 * cgen.h (enum cgen_parse_operand_type): Add
840 CGEN_PARSE_OPERAND_SYMBOLIC.
842 2005-01-21 Fred Fish <fnf@specifixinc.com>
844 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
845 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
846 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
848 2005-01-19 Fred Fish <fnf@specifixinc.com>
850 * mips.h (struct mips_opcode): Add new pinfo2 member.
851 (INSN_ALIAS): New define for opcode table entries that are
852 specific instances of another entry, such as 'move' for an 'or'
854 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
855 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
857 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
859 * mips.h (CPU_RM9000): Define.
860 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
862 2004-11-25 Jan Beulich <jbeulich@novell.com>
864 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
865 to/from test registers are illegal in 64-bit mode. Add missing
866 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
867 (previously one had to explicitly encode a rex64 prefix). Re-enable
868 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
869 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
871 2004-11-23 Jan Beulich <jbeulich@novell.com>
873 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
874 available only with SSE2. Change the MMX additions introduced by SSE
875 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
876 instructions by their now designated identifier (since combining i686
877 and 3DNow! does not really imply 3DNow!A).
879 2004-11-19 Alan Modra <amodra@bigpond.net.au>
881 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
882 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
884 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
885 Vineet Sharma <vineets@noida.hcltech.com>
887 * maxq.h: New file: Disassembly information for the maxq port.
889 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
891 * i386.h (i386_optab): Put back "movzb".
893 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
895 * cris.h (enum cris_insn_version_usage): Tweak formatting and
896 comments. Remove member cris_ver_sim. Add members
897 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
898 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
899 (struct cris_support_reg, struct cris_cond15): New types.
900 (cris_conds15): Declare.
901 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
902 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
903 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
904 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
905 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
908 2004-11-04 Jan Beulich <jbeulich@novell.com>
910 * i386.h (sldx_Suf): Remove.
911 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
912 (q_FP): Define, implying no REX64.
913 (x_FP, sl_FP): Imply FloatMF.
914 (i386_optab): Split reg and mem forms of moving from segment registers
915 so that the memory forms can ignore the 16-/32-bit operand size
916 distinction. Adjust a few others for Intel mode. Remove *FP uses from
917 all non-floating-point instructions. Unite 32- and 64-bit forms of
918 movsx, movzx, and movd. Adjust floating point operations for the above
919 changes to the *FP macros. Add DefaultSize to floating point control
920 insns operating on larger memory ranges. Remove left over comments
921 hinting at certain insns being Intel-syntax ones where the ones
922 actually meant are already gone.
924 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
926 * crx.h: Add COPS_REG_INS - Coprocessor Special register
929 2004-09-30 Paul Brook <paul@codesourcery.com>
931 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
932 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
934 2004-09-11 Theodore A. Roth <troth@openavr.org>
936 * avr.h: Add support for
937 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
939 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
941 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
943 2004-08-24 Dmitry Diky <diwil@spec.ru>
945 * msp430.h (msp430_opc): Add new instructions.
946 (msp430_rcodes): Declare new instructions.
947 (msp430_hcodes): Likewise..
949 2004-08-13 Nick Clifton <nickc@redhat.com>
952 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
955 2004-08-30 Michal Ludvig <mludvig@suse.cz>
957 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
959 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
961 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
963 2004-07-21 Jan Beulich <jbeulich@novell.com>
965 * i386.h: Adjust instruction descriptions to better match the
968 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
970 * arm.h: Remove all old content. Replace with architecture defines
971 from gas/config/tc-arm.c.
973 2004-07-09 Andreas Schwab <schwab@suse.de>
975 * m68k.h: Fix comment.
977 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
981 2004-06-24 Alan Modra <amodra@bigpond.net.au>
983 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
985 2004-05-24 Peter Barada <peter@the-baradas.com>
987 * m68k.h: Add 'size' to m68k_opcode.
989 2004-05-05 Peter Barada <peter@the-baradas.com>
991 * m68k.h: Switch from ColdFire chip name to core variant.
993 2004-04-22 Peter Barada <peter@the-baradas.com>
995 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
996 descriptions for new EMAC cases.
997 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
998 handle Motorola MAC syntax.
999 Allow disassembly of ColdFire V4e object files.
1001 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1003 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1005 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1007 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1009 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1011 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1013 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1015 * i386.h (i386_optab): Added xstore/xcrypt insns.
1017 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1019 * h8300.h (32bit ldc/stc): Add relaxing support.
1021 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1023 * h8300.h (BITOP): Pass MEMRELAX flag.
1025 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1027 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1030 For older changes see ChangeLog-9103
1036 version-control: never