1 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
3 * i386.h : Modify opcode to support for the change in POPCNT opcode
4 in amdfam10 architecture.
6 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
8 * i386.h: Replace CpuMNI with CpuSSSE3.
10 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
11 Joseph Myers <joseph@codesourcery.com>
12 Ian Lance Taylor <ian@wasabisystems.com>
13 Ben Elliston <bje@wasabisystems.com>
15 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
17 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
19 * score-datadep.h: New file.
20 * score-inst.h: New file.
22 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
24 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
25 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
28 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
29 Michael Meissner <michael.meissner@amd.com>
31 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
33 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
35 * i386.h (i386_optab): Add "nop" with memory reference.
37 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
39 * i386.h (i386_optab): Update comment for 64bit NOP.
41 2006-06-06 Ben Elliston <bje@au.ibm.com>
42 Anton Blanchard <anton@samba.org>
44 * ppc.h (PPC_OPCODE_POWER6): Define.
47 2006-06-05 Thiemo Seufer <ths@mips.com>
49 * mips.h: Improve description of MT flags.
51 2006-05-25 Richard Sandiford <richard@codesourcery.com>
53 * m68k.h (mcf_mask): Define.
55 2006-05-05 Thiemo Seufer <ths@mips.com>
56 David Ung <davidu@mips.com>
58 * mips.h (enum): Add macro M_CACHE_AB.
60 2006-05-04 Thiemo Seufer <ths@mips.com>
61 Nigel Stephens <nigel@mips.com>
62 David Ung <davidu@mips.com>
64 * mips.h: Add INSN_SMARTMIPS define.
66 2006-04-30 Thiemo Seufer <ths@mips.com>
67 David Ung <davidu@mips.com>
69 * mips.h: Defines udi bits and masks. Add description of
70 characters which may appear in the args field of udi
73 2006-04-26 Thiemo Seufer <ths@networkno.de>
75 * mips.h: Improve comments describing the bitfield instruction
78 2006-04-26 Julian Brown <julian@codesourcery.com>
80 * arm.h (FPU_VFP_EXT_V3): Define constant.
81 (FPU_NEON_EXT_V1): Likewise.
82 (FPU_VFP_HARD): Update.
83 (FPU_VFP_V3): Define macro.
84 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
86 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
88 * avr.h (AVR_ISA_PWMx): New.
90 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
92 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
93 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
94 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
95 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
96 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
98 2006-03-10 Paul Brook <paul@codesourcery.com>
100 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
102 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
104 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
105 first. Correct mask of bb "B" opcode.
107 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
109 * i386.h (i386_optab): Support Intel Merom New Instructions.
111 2006-02-24 Paul Brook <paul@codesourcery.com>
113 * arm.h: Add V7 feature bits.
115 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
117 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
119 2006-01-31 Paul Brook <paul@codesourcery.com>
120 Richard Earnshaw <rearnsha@arm.com>
122 * arm.h: Use ARM_CPU_FEATURE.
123 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
124 (arm_feature_set): Change to a structure.
125 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
126 ARM_FEATURE): New macros.
128 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
130 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
131 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
132 (ADD_PC_INCR_OPCODE): Don't define.
134 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
137 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
139 2005-11-14 David Ung <davidu@mips.com>
141 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
142 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
143 save/restore encoding of the args field.
145 2005-10-28 Dave Brolley <brolley@redhat.com>
147 Contribute the following changes:
148 2005-02-16 Dave Brolley <brolley@redhat.com>
150 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
151 cgen_isa_mask_* to cgen_bitset_*.
154 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
156 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
157 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
158 (CGEN_CPU_TABLE): Make isas a ponter.
160 2003-09-29 Dave Brolley <brolley@redhat.com>
162 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
163 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
164 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
166 2002-12-13 Dave Brolley <brolley@redhat.com>
168 * cgen.h (symcat.h): #include it.
169 (cgen-bitset.h): #include it.
170 (CGEN_ATTR_VALUE_TYPE): Now a union.
171 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
172 (CGEN_ATTR_ENTRY): 'value' now unsigned.
173 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
174 * cgen-bitset.h: New file.
176 2005-09-30 Catherine Moore <clm@cm00re.com>
180 2005-10-24 Jan Beulich <jbeulich@novell.com>
182 * ia64.h (enum ia64_opnd): Move memory operand out of set of
185 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
187 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
188 Add FLAG_STRICT to pa10 ftest opcode.
190 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
192 * hppa.h (pa_opcodes): Remove lha entries.
194 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
196 * hppa.h (FLAG_STRICT): Revise comment.
197 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
198 before corresponding pa11 opcodes. Add strict pa10 register-immediate
201 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
203 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
205 2005-09-06 Chao-ying Fu <fu@mips.com>
207 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
208 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
210 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
211 (INSN_ASE_MASK): Update to include INSN_MT.
212 (INSN_MT): New define for MT ASE.
214 2005-08-25 Chao-ying Fu <fu@mips.com>
216 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
217 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
218 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
219 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
220 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
221 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
223 (INSN_DSP): New define for DSP ASE.
225 2005-08-18 Alan Modra <amodra@bigpond.net.au>
229 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
231 * ppc.h (PPC_OPCODE_E300): Define.
233 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
235 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
237 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
240 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
243 2005-07-27 Jan Beulich <jbeulich@novell.com>
245 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
246 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
247 Add movq-s as 64-bit variants of movd-s.
249 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
251 * hppa.h: Fix punctuation in comment.
253 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
254 implicit space-register addressing. Set space-register bits on opcodes
255 using implicit space-register addressing. Add various missing pa20
256 long-immediate opcodes. Remove various opcodes using implicit 3-bit
257 space-register addressing. Use "fE" instead of "fe" in various
260 2005-07-18 Jan Beulich <jbeulich@novell.com>
262 * i386.h (i386_optab): Operands of aam and aad are unsigned.
264 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
266 * i386.h (i386_optab): Support Intel VMX Instructions.
268 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
270 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
272 2005-07-05 Jan Beulich <jbeulich@novell.com>
274 * i386.h (i386_optab): Add new insns.
276 2005-07-01 Nick Clifton <nickc@redhat.com>
278 * sparc.h: Add typedefs to structure declarations.
280 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
283 * i386.h (i386_optab): Update comments for 64bit addressing on
284 mov. Allow 64bit addressing for mov and movq.
286 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
288 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
289 respectively, in various floating-point load and store patterns.
291 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
293 * hppa.h (FLAG_STRICT): Correct comment.
294 (pa_opcodes): Update load and store entries to allow both PA 1.X and
295 PA 2.0 mneumonics when equivalent. Entries with cache control
296 completers now require PA 1.1. Adjust whitespace.
298 2005-05-19 Anton Blanchard <anton@samba.org>
300 * ppc.h (PPC_OPCODE_POWER5): Define.
302 2005-05-10 Nick Clifton <nickc@redhat.com>
304 * Update the address and phone number of the FSF organization in
305 the GPL notices in the following files:
306 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
307 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
308 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
309 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
310 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
311 tic54x.h, tic80.h, v850.h, vax.h
313 2005-05-09 Jan Beulich <jbeulich@novell.com>
315 * i386.h (i386_optab): Add ht and hnt.
317 2005-04-18 Mark Kettenis <kettenis@gnu.org>
319 * i386.h: Insert hyphens into selected VIA PadLock extensions.
320 Add xcrypt-ctr. Provide aliases without hyphens.
322 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
324 Moved from ../ChangeLog
326 2005-04-12 Paul Brook <paul@codesourcery.com>
327 * m88k.h: Rename psr macros to avoid conflicts.
329 2005-03-12 Zack Weinberg <zack@codesourcery.com>
330 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
331 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
334 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
335 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
336 Remove redundant instruction types.
337 (struct argument): X_op - new field.
338 (struct cst4_entry): Remove.
339 (no_op_insn): Declare.
341 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
342 * crx.h (enum argtype): Rename types, remove unused types.
344 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
345 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
346 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
347 (enum operand_type): Rearrange operands, edit comments.
348 replace us<N> with ui<N> for unsigned immediate.
349 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
350 displacements (respectively).
351 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
352 (instruction type): Add NO_TYPE_INS.
353 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
354 (operand_entry): New field - 'flags'.
355 (operand flags): New.
357 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
358 * crx.h (operand_type): Remove redundant types i3, i4,
360 Add new unsigned immediate types us3, us4, us5, us16.
362 2005-04-12 Mark Kettenis <kettenis@gnu.org>
364 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
365 adjust them accordingly.
367 2005-04-01 Jan Beulich <jbeulich@novell.com>
369 * i386.h (i386_optab): Add rdtscp.
371 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
373 * i386.h (i386_optab): Don't allow the `l' suffix for moving
374 between memory and segment register. Allow movq for moving between
375 general-purpose register and segment register.
377 2005-02-09 Jan Beulich <jbeulich@novell.com>
380 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
381 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
384 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
386 * m68k.h (m68008, m68ec030, m68882): Remove.
388 (cpu_m68k, cpu_cf): New.
389 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
390 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
392 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
394 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
395 * cgen.h (enum cgen_parse_operand_type): Add
396 CGEN_PARSE_OPERAND_SYMBOLIC.
398 2005-01-21 Fred Fish <fnf@specifixinc.com>
400 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
401 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
402 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
404 2005-01-19 Fred Fish <fnf@specifixinc.com>
406 * mips.h (struct mips_opcode): Add new pinfo2 member.
407 (INSN_ALIAS): New define for opcode table entries that are
408 specific instances of another entry, such as 'move' for an 'or'
410 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
411 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
413 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
415 * mips.h (CPU_RM9000): Define.
416 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
418 2004-11-25 Jan Beulich <jbeulich@novell.com>
420 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
421 to/from test registers are illegal in 64-bit mode. Add missing
422 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
423 (previously one had to explicitly encode a rex64 prefix). Re-enable
424 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
425 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
427 2004-11-23 Jan Beulich <jbeulich@novell.com>
429 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
430 available only with SSE2. Change the MMX additions introduced by SSE
431 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
432 instructions by their now designated identifier (since combining i686
433 and 3DNow! does not really imply 3DNow!A).
435 2004-11-19 Alan Modra <amodra@bigpond.net.au>
437 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
438 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
440 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
441 Vineet Sharma <vineets@noida.hcltech.com>
443 * maxq.h: New file: Disassembly information for the maxq port.
445 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
447 * i386.h (i386_optab): Put back "movzb".
449 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
451 * cris.h (enum cris_insn_version_usage): Tweak formatting and
452 comments. Remove member cris_ver_sim. Add members
453 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
454 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
455 (struct cris_support_reg, struct cris_cond15): New types.
456 (cris_conds15): Declare.
457 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
458 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
459 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
460 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
461 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
464 2004-11-04 Jan Beulich <jbeulich@novell.com>
466 * i386.h (sldx_Suf): Remove.
467 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
468 (q_FP): Define, implying no REX64.
469 (x_FP, sl_FP): Imply FloatMF.
470 (i386_optab): Split reg and mem forms of moving from segment registers
471 so that the memory forms can ignore the 16-/32-bit operand size
472 distinction. Adjust a few others for Intel mode. Remove *FP uses from
473 all non-floating-point instructions. Unite 32- and 64-bit forms of
474 movsx, movzx, and movd. Adjust floating point operations for the above
475 changes to the *FP macros. Add DefaultSize to floating point control
476 insns operating on larger memory ranges. Remove left over comments
477 hinting at certain insns being Intel-syntax ones where the ones
478 actually meant are already gone.
480 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
482 * crx.h: Add COPS_REG_INS - Coprocessor Special register
485 2004-09-30 Paul Brook <paul@codesourcery.com>
487 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
488 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
490 2004-09-11 Theodore A. Roth <troth@openavr.org>
492 * avr.h: Add support for
493 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
495 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
497 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
499 2004-08-24 Dmitry Diky <diwil@spec.ru>
501 * msp430.h (msp430_opc): Add new instructions.
502 (msp430_rcodes): Declare new instructions.
503 (msp430_hcodes): Likewise..
505 2004-08-13 Nick Clifton <nickc@redhat.com>
508 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
511 2004-08-30 Michal Ludvig <mludvig@suse.cz>
513 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
515 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
517 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
519 2004-07-21 Jan Beulich <jbeulich@novell.com>
521 * i386.h: Adjust instruction descriptions to better match the
524 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
526 * arm.h: Remove all old content. Replace with architecture defines
527 from gas/config/tc-arm.c.
529 2004-07-09 Andreas Schwab <schwab@suse.de>
531 * m68k.h: Fix comment.
533 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
537 2004-06-24 Alan Modra <amodra@bigpond.net.au>
539 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
541 2004-05-24 Peter Barada <peter@the-baradas.com>
543 * m68k.h: Add 'size' to m68k_opcode.
545 2004-05-05 Peter Barada <peter@the-baradas.com>
547 * m68k.h: Switch from ColdFire chip name to core variant.
549 2004-04-22 Peter Barada <peter@the-baradas.com>
551 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
552 descriptions for new EMAC cases.
553 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
554 handle Motorola MAC syntax.
555 Allow disassembly of ColdFire V4e object files.
557 2004-03-16 Alan Modra <amodra@bigpond.net.au>
559 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
561 2004-03-12 Jakub Jelinek <jakub@redhat.com>
563 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
565 2004-03-12 Michal Ludvig <mludvig@suse.cz>
567 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
569 2004-03-12 Michal Ludvig <mludvig@suse.cz>
571 * i386.h (i386_optab): Added xstore/xcrypt insns.
573 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
575 * h8300.h (32bit ldc/stc): Add relaxing support.
577 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
579 * h8300.h (BITOP): Pass MEMRELAX flag.
581 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
583 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
586 For older changes see ChangeLog-9103
592 version-control: never