1 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
4 (aarch64_sys_ins_reg_has_xt): Declare.
6 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
8 * aarch64.h (AARCH64_FEATURE_RAS): New.
9 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
11 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
13 * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
15 (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
16 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
19 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
21 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
23 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
25 * aarch64.h (aarch64_op): Add OP_BFC.
27 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
29 * aarch64.h (AARCH64_FEATURE_F16): New.
30 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
33 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
35 * aarch64.h (AARCH64_FEATURE_V8_1): New.
36 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
38 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
40 * arm.h (ARM_EXT2_V8_2A): New.
41 (ARM_ARCH_V8_2A): New.
43 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
45 * aarch64.h (AARCH64_FEATURE_V8_2): New.
46 (AARCH64_ARCH_V8_2): New.
48 2015-11-11 Alan Modra <amodra@gmail.com>
49 Peter Bergner <bergner@vnet.ibm.com>
51 * ppc.h (PPC_OPCODE_POWER9): New define.
52 (PPC_OPCODE_VSX3): Likewise.
54 2015-11-02 Nick Clifton <nickc@redhat.com>
56 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
58 2015-11-02 Nick Clifton <nickc@redhat.com>
60 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
62 2015-10-28 Yao Qi <yao.qi@linaro.org>
64 * aarch64.h (aarch64_decode_insn): Update declaration.
66 2015-10-07 Yao Qi <yao.qi@linaro.org>
68 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
71 2015-10-07 Yao Qi <yao.qi@linaro.org>
73 * aarch64.h [__cplusplus]: Wrap in extern "C".
75 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
76 Cupertino Miranda <cmiranda@synopsys.com>
78 * arc-func.h: New file.
81 2015-10-02 Yao Qi <yao.qi@linaro.org>
83 * aarch64.h (aarch64_zero_register_p): Move the declaration
86 2015-10-02 Yao Qi <yao.qi@linaro.org>
88 * aarch64.h (aarch64_decode_insn): Declare it.
90 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
92 * s390.h (S390_INSTR_FLAG_HTM): New flag.
93 (S390_INSTR_FLAG_VX): New flag.
94 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
96 2015-09-23 Nick Clifton <nickc@redhat.com>
98 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
101 2015-09-22 Nick Clifton <nickc@redhat.com>
103 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
105 2015-09-09 Daniel Santos <daniel.santos@pobox.com>
107 * visium.h (gen_reg_table): Make static.
108 (fp_reg_table): Likewise.
109 (cc_table): Likewise.
111 2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
113 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
114 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
115 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
116 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
118 2015-07-03 Alan Modra <amodra@gmail.com>
120 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
122 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
123 Cesar Philippidis <cesar@codesourcery.com>
125 * nios2.h (enum iw_format_type): Add R2 formats.
126 (enum overflow_type): Add signed_immed12_overflow and
127 enumeration_overflow for R2.
128 (struct nios2_opcode): Document new argument letters for R2.
129 (REG_3BIT, REG_LDWM, REG_POP): Define.
130 (includes): Include nios2r2.h.
131 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
132 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
133 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
134 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
135 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
136 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
138 * nios2r2.h: New file.
140 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
142 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
143 (ppc_optional_operand_value): New inline function.
145 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
147 * aarch64.h (AARCH64_V8_1): New.
149 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
151 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
152 (ARM_ARCH_V8_1A): New.
153 (ARM_ARCH_V8_1A_FP): New.
154 (ARM_ARCH_V8_1A_SIMD): New.
155 (ARM_ARCH_V8_1A_CRYPTOV1): New.
156 (ARM_FEATURE_CORE): New.
158 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
160 * arm.h (ARM_EXT2_PAN): New.
161 (ARM_FEATURE_CORE_HIGH): New.
163 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
165 * arm.h (ARM_FEATURE_ALL): New.
167 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
169 * aarch64.h (AARCH64_FEATURE_RDMA): New.
171 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
173 * aarch64.h (AARCH64_FEATURE_LOR): New.
175 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
177 * aarch64.h (AARCH64_FEATURE_PAN): New.
178 (aarch64_sys_reg_supported_p): Declare.
179 (aarch64_pstatefield_supported_p): Declare.
181 2015-04-30 DJ Delorie <dj@redhat.com>
183 * rl78.h (RL78_Dis_Isa): New.
184 (rl78_decode_opcode): Add ISA parameter.
186 2015-03-24 Terry Guo <terry.guo@arm.com>
188 * arm.h (arm_feature_set): Extended to provide more available bits.
189 (ARM_ANY): Updated to follow above new definition.
190 (ARM_CPU_HAS_FEATURE): Likewise.
191 (ARM_CPU_IS_ANY): Likewise.
192 (ARM_MERGE_FEATURE_SETS): Likewise.
193 (ARM_CLEAR_FEATURE): Likewise.
194 (ARM_FEATURE): Likewise.
195 (ARM_FEATURE_COPY): New macro.
196 (ARM_FEATURE_EQUAL): Likewise.
197 (ARM_FEATURE_ZERO): Likewise.
198 (ARM_FEATURE_CORE_EQUAL): Likewise.
199 (ARM_FEATURE_LOW): Likewise.
200 (ARM_FEATURE_CORE_LOW): Likewise.
201 (ARM_FEATURE_CORE_COPROC): Likewise.
203 2015-02-19 Pedro Alves <palves@redhat.com>
205 * cgen.h [__cplusplus]: Wrap in extern "C".
206 * msp430-decode.h [__cplusplus]: Likewise.
207 * nios2.h [__cplusplus]: Likewise.
208 * rl78.h [__cplusplus]: Likewise.
209 * rx.h [__cplusplus]: Likewise.
210 * tilegx.h [__cplusplus]: Likewise.
212 2015-01-28 James Bowman <james.bowman@ftdichip.com>
216 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
218 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
220 2015-01-01 Alan Modra <amodra@gmail.com>
222 Update year range in copyright notice of all files.
224 2014-12-27 Anthony Green <green@moxielogic.com>
226 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
227 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
229 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
231 * visium.h: New file.
233 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
235 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
236 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
237 (NIOS2_INSN_OPTARG): Renumber.
239 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
241 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
242 declaration. Fix obsolete comment.
244 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
246 * nios2.h (enum iw_format_type): New.
247 (struct nios2_opcode): Update comments. Add size and format fields.
248 (NIOS2_INSN_OPTARG): New.
249 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
250 (struct nios2_reg): Add regtype field.
251 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
252 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
253 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
254 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
255 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
256 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
257 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
258 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
259 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
260 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
261 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
262 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
263 (OP_MASK_OP, OP_SH_OP): Delete.
264 (OP_MASK_IOP, OP_SH_IOP): Delete.
265 (OP_MASK_IRD, OP_SH_IRD): Delete.
266 (OP_MASK_IRT, OP_SH_IRT): Delete.
267 (OP_MASK_IRS, OP_SH_IRS): Delete.
268 (OP_MASK_ROP, OP_SH_ROP): Delete.
269 (OP_MASK_RRD, OP_SH_RRD): Delete.
270 (OP_MASK_RRT, OP_SH_RRT): Delete.
271 (OP_MASK_RRS, OP_SH_RRS): Delete.
272 (OP_MASK_JOP, OP_SH_JOP): Delete.
273 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
274 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
275 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
276 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
277 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
278 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
279 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
280 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
281 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
282 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
283 (OP_MASK_<insn>, OP_MASK): Delete.
284 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
285 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
286 Include nios2r1.h to define new instruction opcode constants
288 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
289 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
290 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
291 (NUMOPCODES, NUMREGISTERS): Delete.
292 * nios2r1.h: New file.
294 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
296 * sparc.h (HWCAP2_VIS3B): Documentation improved.
298 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
300 * sparc.h (sparc_opcode): new field `hwcaps2'.
301 (HWCAP2_FJATHPLUS): New define.
302 (HWCAP2_VIS3B): Likewise.
303 (HWCAP2_ADP): Likewise.
304 (HWCAP2_SPARC5): Likewise.
305 (HWCAP2_MWAIT): Likewise.
306 (HWCAP2_XMPMUL): Likewise.
307 (HWCAP2_XMONT): Likewise.
308 (HWCAP2_NSEC): Likewise.
309 (HWCAP2_FJATHHPC): Likewise.
310 (HWCAP2_FJDES): Likewise.
311 (HWCAP2_FJAES): Likewise.
312 Document the new operand kind `{', corresponding to the mcdper
313 ancillary state register.
314 Document the new operand kind }, which represents frsd floating
315 point registers (double precision) which must be the same than
316 frs1 in its containing instruction.
318 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
320 * nds32.h: Add new opcode declaration.
322 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
323 Matthew Fortune <matthew.fortune@imgtec.com>
325 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
326 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
327 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
328 +I, +O, +R, +:, +\, +", +;
329 (mips_check_prev_operand): New struct.
330 (INSN2_FORBIDDEN_SLOT): New define.
331 (INSN_ISA32R6): New define.
332 (INSN_ISA64R6): New define.
333 (INSN_UPTO32R6): New define.
334 (INSN_UPTO64R6): New define.
335 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
336 (ISA_MIPS32R6): New define.
337 (ISA_MIPS64R6): New define.
338 (CPU_MIPS32R6): New define.
339 (CPU_MIPS64R6): New define.
340 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
342 2014-09-03 Jiong Wang <jiong.wang@arm.com>
344 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
345 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
346 (aarch64_insn_class): Add lse_atomic.
347 (F_LSE_SZ): New field added.
348 (opcode_has_special_coder): Recognize F_LSE_SZ.
350 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
352 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
355 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
357 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
358 (INSN_LOAD_COPROC): New define.
359 (INSN_COPROC_MOVE_DELAY): Rename to...
360 (INSN_COPROC_MOVE): New define.
362 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
363 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
364 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
365 Soundararajan <Sounderarajan.D@atmel.com>
367 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
368 (AVR_ISA_2xxxa): Define ISA without LPM.
369 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
370 Add doc for contraint used in 16 bit lds/sts.
371 Adjust ISA group for icall, ijmp, pop and push.
372 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
374 2014-05-19 Nick Clifton <nickc@redhat.com>
376 * msp430.h (struct msp430_operand_s): Add vshift field.
378 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
380 * mips.h (INSN_ISA_MASK): Updated.
381 (INSN_ISA32R3): New define.
382 (INSN_ISA32R5): New define.
383 (INSN_ISA64R3): New define.
384 (INSN_ISA64R5): New define.
385 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
386 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
387 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
389 (INSN_UPTO32R3): New define.
390 (INSN_UPTO32R5): New define.
391 (INSN_UPTO64R3): New define.
392 (INSN_UPTO64R5): New define.
393 (ISA_MIPS32R3): New define.
394 (ISA_MIPS32R5): New define.
395 (ISA_MIPS64R3): New define.
396 (ISA_MIPS64R5): New define.
397 (CPU_MIPS32R3): New define.
398 (CPU_MIPS32R5): New define.
399 (CPU_MIPS64R3): New define.
400 (CPU_MIPS64R5): New define.
402 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
404 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
406 2014-04-22 Christian Svensson <blue@cmd.nu>
410 2014-03-05 Alan Modra <amodra@gmail.com>
412 Update copyright years.
414 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
416 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
419 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
420 Wei-Cheng Wang <cole945@gmail.com>
422 * nds32.h: New file for Andes NDS32.
424 2013-12-07 Mike Frysinger <vapier@gentoo.org>
426 * bfin.h: Remove +x file mode.
428 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
430 * aarch64.h (aarch64_pstatefields): Change element type to
433 2013-11-18 Renlin Li <Renlin.Li@arm.com>
435 * arm.h (ARM_AEXT_V7VE): New define.
436 (ARM_ARCH_V7VE): New define.
437 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
439 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
443 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
445 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
446 (aarch64_sys_reg_writeonly_p): Ditto.
448 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
450 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
451 (aarch64_sys_reg_writeonly_p): Ditto.
453 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
455 * aarch64.h (aarch64_sys_reg): New typedef.
456 (aarch64_sys_regs): Change to define with the new type.
457 (aarch64_sys_reg_deprecated_p): Declare.
459 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
461 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
462 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
464 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
466 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
467 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
468 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
469 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
470 For MIPS, update extension character sequences after +.
471 (ASE_MSA): New define.
472 (ASE_MSA64): New define.
473 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
474 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
475 For microMIPS, update extension character sequences after +.
477 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
482 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
484 * mips.h: Remove references to "+I" and imm2_expr.
486 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
488 * mips.h (M_DEXT, M_DINS): Delete.
490 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
492 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
493 (mips_optional_operand_p): New function.
495 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
496 Richard Sandiford <rdsandiford@googlemail.com>
498 * mips.h: Document new VU0 operand characters.
499 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
500 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
501 (OP_REG_R5900_ACC): New mips_reg_operand_types.
502 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
503 (mips_vu0_channel_mask): Declare.
505 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
507 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
508 (mips_int_operand_min, mips_int_operand_max): New functions.
509 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
511 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
513 * mips.h (mips_decode_reg_operand): New function.
514 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
515 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
516 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
518 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
519 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
520 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
521 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
522 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
523 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
524 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
525 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
526 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
527 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
528 macros to cover the gaps.
529 (INSN2_MOD_SP): Replace with...
530 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
531 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
532 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
533 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
534 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
537 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
539 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
540 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
541 (MIPS16_INSN_COND_BRANCH): Delete.
543 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
544 Kirill Yukhin <kirill.yukhin@intel.com>
545 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
547 * i386.h (BND_PREFIX_OPCODE): New.
549 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
551 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
552 OP_SAVE_RESTORE_LIST.
553 (decode_mips16_operand): Declare.
555 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
557 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
558 (mips_operand, mips_int_operand, mips_mapped_int_operand)
559 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
560 (mips_pcrel_operand): New structures.
561 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
562 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
563 (decode_mips_operand, decode_micromips_operand): Declare.
565 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
567 * mips.h: Document MIPS16 "I" opcode.
569 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
571 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
572 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
573 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
574 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
575 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
576 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
577 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
578 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
579 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
580 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
581 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
582 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
583 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
585 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
586 (M_USD_AB): ...these.
588 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
590 * mips.h: Remove documentation of "[" and "]". Update documentation
591 of "k" and the MDMX formats.
593 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
595 * mips.h: Update documentation of "+s" and "+S".
597 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
599 * mips.h: Document "+i".
601 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
603 * mips.h: Remove "mi" documentation. Update "mh" documentation.
604 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
606 (INSN2_WRITE_GPR_MHI): Rename to...
607 (INSN2_WRITE_GPR_MH): ...this.
609 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
611 * mips.h: Remove documentation of "+D" and "+T".
613 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
615 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
616 Use "source" rather than "destination" for microMIPS "G".
618 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
620 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
623 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
625 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
627 2013-06-17 Catherine Moore <clm@codesourcery.com>
628 Maciej W. Rozycki <macro@codesourcery.com>
629 Chao-Ying Fu <fu@mips.com>
631 * mips.h (OP_SH_EVAOFFSET): Define.
632 (OP_MASK_EVAOFFSET): Define.
633 (INSN_ASE_MASK): Delete.
635 (M_CACHEE_AB, M_CACHEE_OB): New.
636 (M_LBE_OB, M_LBE_AB): New.
637 (M_LBUE_OB, M_LBUE_AB): New.
638 (M_LHE_OB, M_LHE_AB): New.
639 (M_LHUE_OB, M_LHUE_AB): New.
640 (M_LLE_AB, M_LLE_OB): New.
641 (M_LWE_OB, M_LWE_AB): New.
642 (M_LWLE_AB, M_LWLE_OB): New.
643 (M_LWRE_AB, M_LWRE_OB): New.
644 (M_PREFE_AB, M_PREFE_OB): New.
645 (M_SCE_AB, M_SCE_OB): New.
646 (M_SBE_OB, M_SBE_AB): New.
647 (M_SHE_OB, M_SHE_AB): New.
648 (M_SWE_OB, M_SWE_AB): New.
649 (M_SWLE_AB, M_SWLE_OB): New.
650 (M_SWRE_AB, M_SWRE_OB): New.
651 (MICROMIPSOP_SH_EVAOFFSET): Define.
652 (MICROMIPSOP_MASK_EVAOFFSET): Define.
654 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
656 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
658 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
660 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
662 2013-05-09 Andrew Pinski <apinski@cavium.com>
664 * mips.h (OP_MASK_CODE10): Correct definition.
665 (OP_SH_CODE10): Likewise.
666 Add a comment that "+J" is used now for OP_*CODE10.
667 (INSN_ASE_MASK): Update.
668 (INSN_VIRT): New macro.
669 (INSN_VIRT64): New macro
671 2013-05-02 Nick Clifton <nickc@redhat.com>
673 * msp430.h: Add patterns for MSP430X instructions.
675 2013-04-06 David S. Miller <davem@davemloft.net>
677 * sparc.h (F_PREFERRED): Define.
678 (F_PREF_ALIAS): Define.
680 2013-04-03 Nick Clifton <nickc@redhat.com>
682 * v850.h (V850_INVERSE_PCREL): Define.
684 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
687 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
689 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
692 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
694 * tic6xc-opcode-table.h: Add 16-bit insns.
695 * tic6x.h: Add support for 16-bit insns.
697 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
699 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
700 and mov.b/w/l Rs,@(d:32,ERd).
702 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
705 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
706 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
707 tic6x_operand_xregpair operand coding type.
708 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
709 opcode field, usu ORXREGD1324 for the src2 operand and remove the
712 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
715 * tic6x.h (enum tic6x_coding_method): Add
716 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
717 separately the msb and lsb of a register pair. This is needed to
718 encode the opcodes in the same way as TI assembler does.
719 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
720 and rsqrdp opcodes to use the new field coding types.
722 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
724 * arm.h (CRC_EXT_ARMV8): New constant.
725 (ARCH_CRC_ARMV8): New macro.
727 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
729 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
731 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
732 Andrew Jenner <andrew@codesourcery.com>
734 Based on patches from Altera Corporation.
738 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
740 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
742 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
745 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
747 2013-01-24 Nick Clifton <nickc@redhat.com>
749 * v850.h: Add e3v5 support.
751 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
753 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
755 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
757 * ppc.h (PPC_OPCODE_POWER8): New define.
758 (PPC_OPCODE_HTM): Likewise.
760 2013-01-10 Will Newton <will.newton@imgtec.com>
764 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
766 * cr16.h (make_instruction): Rename to cr16_make_instruction.
767 (match_opcode): Rename to cr16_match_opcode.
769 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
771 * mips.h: Add support for r5900 instructions including lq and sq.
773 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
775 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
776 (make_instruction,match_opcode): Added function prototypes.
777 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
779 2012-11-23 Alan Modra <amodra@gmail.com>
781 * ppc.h (ppc_parse_cpu): Update prototype.
783 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
785 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
786 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
788 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
790 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
792 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
794 * ia64.h (ia64_opnd): Add new operand types.
796 2012-08-21 David S. Miller <davem@davemloft.net>
798 * sparc.h (F3F4): New macro.
800 2012-08-13 Ian Bolton <ian.bolton@arm.com>
801 Laurent Desnogues <laurent.desnogues@arm.com>
802 Jim MacArthur <jim.macarthur@arm.com>
803 Marcus Shawcroft <marcus.shawcroft@arm.com>
804 Nigel Stephens <nigel.stephens@arm.com>
805 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
806 Richard Earnshaw <rearnsha@arm.com>
807 Sofiane Naci <sofiane.naci@arm.com>
808 Tejas Belagod <tejas.belagod@arm.com>
809 Yufeng Zhang <yufeng.zhang@arm.com>
811 * aarch64.h: New file.
813 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
814 Maciej W. Rozycki <macro@codesourcery.com>
816 * mips.h (mips_opcode): Add the exclusions field.
817 (OPCODE_IS_MEMBER): Remove macro.
818 (cpu_is_member): New inline function.
819 (opcode_is_member): Likewise.
821 2012-07-31 Chao-Ying Fu <fu@mips.com>
822 Catherine Moore <clm@codesourcery.com>
823 Maciej W. Rozycki <macro@codesourcery.com>
825 * mips.h: Document microMIPS DSP ASE usage.
826 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
827 microMIPS DSP ASE support.
828 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
829 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
830 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
831 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
832 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
833 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
834 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
836 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
838 * mips.h: Fix a typo in description.
840 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
842 * avr.h: (AVR_ISA_XCH): New define.
843 (AVR_ISA_XMEGA): Use it.
844 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
846 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
848 * m68hc11.h: Add XGate definitions.
849 (struct m68hc11_opcode): Add xg_mask field.
851 2012-05-14 Catherine Moore <clm@codesourcery.com>
852 Maciej W. Rozycki <macro@codesourcery.com>
853 Rhonda Wittels <rhonda@codesourcery.com>
855 * ppc.h (PPC_OPCODE_VLE): New definition.
856 (PPC_OP_SA): New macro.
857 (PPC_OP_SE_VLE): New macro.
858 (PPC_OP): Use a variable shift amount.
859 (powerpc_operand): Update comments.
860 (PPC_OPSHIFT_INV): New macro.
861 (PPC_OPERAND_CR): Replace with...
862 (PPC_OPERAND_CR_BIT): ...this and
863 (PPC_OPERAND_CR_REG): ...this.
866 2012-05-03 Sean Keys <skeys@ipdatasys.com>
868 * xgate.h: Header file for XGATE assembler.
870 2012-04-27 David S. Miller <davem@davemloft.net>
872 * sparc.h: Document new arg code' )' for crypto RS3
875 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
876 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
877 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
878 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
879 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
880 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
881 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
882 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
883 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
884 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
885 HWCAP_CBCOND, HWCAP_CRC32): New defines.
887 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
889 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
891 2012-02-27 Alan Modra <amodra@gmail.com>
893 * crx.h (cst4_map): Update declaration.
895 2012-02-25 Walter Lee <walt@tilera.com>
897 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
899 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
900 TILEPRO_OPC_LW_TLS_SN.
902 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
904 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
905 (XRELEASE_PREFIX_OPCODE): Likewise.
907 2011-12-08 Andrew Pinski <apinski@cavium.com>
908 Adam Nemet <anemet@caviumnetworks.com>
910 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
911 (INSN_OCTEON2): New macro.
912 (CPU_OCTEON2): New macro.
913 (OPCODE_IS_MEMBER): Add Octeon2.
915 2011-11-29 Andrew Pinski <apinski@cavium.com>
917 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
918 (INSN_OCTEONP): New macro.
919 (CPU_OCTEONP): New macro.
920 (OPCODE_IS_MEMBER): Add Octeon+.
921 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
923 2011-11-01 DJ Delorie <dj@redhat.com>
927 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
929 * mips.h: Fix a typo in description.
931 2011-09-21 David S. Miller <davem@davemloft.net>
933 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
934 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
935 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
936 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
938 2011-08-09 Chao-ying Fu <fu@mips.com>
939 Maciej W. Rozycki <macro@codesourcery.com>
941 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
942 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
943 (INSN_ASE_MASK): Add the MCU bit.
944 (INSN_MCU): New macro.
945 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
946 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
948 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
950 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
951 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
952 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
953 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
954 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
955 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
956 (INSN2_READ_GPR_MMN): Likewise.
957 (INSN2_READ_FPR_D): Change the bit used.
958 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
959 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
960 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
961 (INSN2_COND_BRANCH): Likewise.
962 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
963 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
964 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
965 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
966 (INSN2_MOD_GPR_MN): Likewise.
968 2011-08-05 David S. Miller <davem@davemloft.net>
970 * sparc.h: Document new format codes '4', '5', and '('.
971 (OPF_LOW4, RS3): New macros.
973 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
975 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
976 order of flags documented.
978 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
980 * mips.h: Clarify the description of microMIPS instruction
982 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
984 2011-07-24 Chao-ying Fu <fu@mips.com>
985 Maciej W. Rozycki <macro@codesourcery.com>
987 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
988 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
989 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
990 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
991 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
992 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
993 (OP_MASK_RS3, OP_SH_RS3): Likewise.
994 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
995 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
996 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
997 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
998 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
999 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
1000 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
1001 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
1002 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
1003 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
1004 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
1005 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
1006 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
1007 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
1008 (INSN_WRITE_GPR_S): New macro.
1009 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
1010 (INSN2_READ_FPR_D): Likewise.
1011 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
1012 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
1013 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
1014 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
1015 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
1016 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
1017 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1018 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1019 (CPU_MICROMIPS): New macro.
1020 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1021 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1022 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1023 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1024 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1025 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1026 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1027 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1028 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1029 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1030 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1031 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1032 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1033 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1034 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1035 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1036 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1037 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1038 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1039 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1040 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1041 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1042 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1043 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1044 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1045 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1046 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1047 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1048 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1049 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1050 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1051 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1052 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1053 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1054 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1055 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1056 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1057 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1058 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1059 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1060 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1061 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1062 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1063 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1064 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1065 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1066 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1067 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1068 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1069 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1070 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1071 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1072 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1073 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1074 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1075 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1076 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1077 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1078 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1079 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1080 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1081 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1082 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1083 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1084 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1085 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1086 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1087 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1088 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1089 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1090 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1091 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1092 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1093 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1094 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1095 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1096 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1097 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1098 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1099 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1100 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1101 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1102 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1103 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1104 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1105 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1106 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1107 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1108 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1109 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1110 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1111 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1112 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1113 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1114 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1115 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1116 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1117 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1118 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1119 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1120 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1121 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1122 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1123 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1124 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1125 (micromips_opcodes): New declaration.
1126 (bfd_micromips_num_opcodes): Likewise.
1128 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1130 * mips.h (INSN_TRAP): Rename to...
1131 (INSN_NO_DELAY_SLOT): ... this.
1132 (INSN_SYNC): Remove macro.
1134 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1136 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1137 a duplicate of AVR_ISA_SPM.
1139 2011-07-01 Nick Clifton <nickc@redhat.com>
1141 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1143 2011-06-18 Robin Getz <robin.getz@analog.com>
1145 * bfin.h (is_macmod_signed): New func
1147 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1149 * bfin.h (is_macmod_pmove): Add missing space before func args.
1150 (is_macmod_hmove): Likewise.
1152 2011-06-13 Walter Lee <walt@tilera.com>
1154 * tilegx.h: New file.
1155 * tilepro.h: New file.
1157 2011-05-31 Paul Brook <paul@codesourcery.com>
1159 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1161 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1163 * s390.h: Replace S390_OPERAND_REG_EVEN with
1164 S390_OPERAND_REG_PAIR.
1166 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1168 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1170 2011-04-18 Julian Brown <julian@codesourcery.com>
1172 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1174 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1177 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1179 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1181 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1182 New instruction set flags.
1183 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1185 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1187 * mips.h (M_PREF_AB): New enum value.
1189 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1191 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1193 (is_macmod_pmove, is_macmod_hmove): New functions.
1195 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1197 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1199 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1201 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1202 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1204 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1207 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1210 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1213 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1215 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1217 * mips.h: Update commentary after last commit.
1219 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1221 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1222 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1223 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1225 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1227 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1229 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1231 * mips.h: Fix previous commit.
1233 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1235 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1236 (INSN_LOONGSON_3A): Clear bit 31.
1238 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1241 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1242 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1243 (ARM_ARCH_V6M_ONLY): New define.
1245 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1247 * mips.h (INSN_LOONGSON_3A): Defined.
1248 (CPU_LOONGSON_3A): Defined.
1249 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1251 2010-10-09 Matt Rice <ratmice@gmail.com>
1253 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1254 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1256 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1258 * arm.h (ARM_EXT_VIRT): New define.
1259 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1260 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1263 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1265 * arm.h (ARM_AEXT_ADIV): New define.
1266 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1268 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1270 * arm.h (ARM_EXT_OS): New define.
1271 (ARM_AEXT_V6SM): Likewise.
1272 (ARM_ARCH_V6SM): Likewise.
1274 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1276 * arm.h (ARM_EXT_MP): Add.
1277 (ARM_ARCH_V7A_MP): Likewise.
1279 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1281 * bfin.h: Declare pseudoChr structs/defines.
1283 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1285 * bfin.h: Strip trailing whitespace.
1287 2010-07-29 DJ Delorie <dj@redhat.com>
1289 * rx.h (RX_Operand_Type): Add TwoReg.
1290 (RX_Opcode_ID): Remove ediv and ediv2.
1292 2010-07-27 DJ Delorie <dj@redhat.com>
1294 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1296 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1297 Ina Pandit <ina.pandit@kpitcummins.com>
1299 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1300 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1301 PROCESSOR_V850E2_ALL.
1302 Remove PROCESSOR_V850EA support.
1303 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1304 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1305 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1306 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1307 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1308 V850_OPERAND_PERCENT.
1309 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1311 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1314 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1316 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1317 (MIPS16_INSN_BRANCH): Rename to...
1318 (MIPS16_INSN_COND_BRANCH): ... this.
1320 2010-07-03 Alan Modra <amodra@gmail.com>
1322 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1323 Renumber other PPC_OPCODE defines.
1325 2010-07-03 Alan Modra <amodra@gmail.com>
1327 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1329 2010-06-29 Alan Modra <amodra@gmail.com>
1331 * maxq.h: Delete file.
1333 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1335 * ppc.h (PPC_OPCODE_E500): Define.
1337 2010-05-26 Catherine Moore <clm@codesourcery.com>
1339 * opcode/mips.h (INSN_MIPS16): Remove.
1341 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1343 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1345 2010-04-15 Nick Clifton <nickc@redhat.com>
1347 * alpha.h: Update copyright notice to use GPLv3.
1353 * convex.h: Likewise.
1360 * h8300.h: Likewise.
1367 * m68hc11.h: Likewise.
1373 * mn10200.h: Likewise.
1374 * mn10300.h: Likewise.
1375 * msp430.h: Likewise.
1377 * ns32k.h: Likewise.
1379 * pdp11.h: Likewise.
1386 * score-datadep.h: Likewise.
1387 * score-inst.h: Likewise.
1388 * sparc.h: Likewise.
1389 * spu-insns.h: Likewise.
1391 * tic30.h: Likewise.
1392 * tic4x.h: Likewise.
1393 * tic54x.h: Likewise.
1394 * tic80.h: Likewise.
1398 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1400 * tic6x-control-registers.h, tic6x-insn-formats.h,
1401 tic6x-opcode-table.h, tic6x.h: New.
1403 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1405 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1407 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1409 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1411 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1413 * ia64.h (ia64_find_opcode): Remove argument name.
1414 (ia64_find_next_opcode): Likewise.
1415 (ia64_dis_opcode): Likewise.
1416 (ia64_free_opcode): Likewise.
1417 (ia64_find_dependency): Likewise.
1419 2009-11-22 Doug Evans <dje@sebabeach.org>
1421 * cgen.h: Include bfd_stdint.h.
1422 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1424 2009-11-18 Paul Brook <paul@codesourcery.com>
1426 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1428 2009-11-17 Paul Brook <paul@codesourcery.com>
1429 Daniel Jacobowitz <dan@codesourcery.com>
1431 * arm.h (ARM_EXT_V6_DSP): Define.
1432 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1433 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1435 2009-11-04 DJ Delorie <dj@redhat.com>
1437 * rx.h (rx_decode_opcode) (mvtipl): Add.
1438 (mvtcp, mvfcp, opecp): Remove.
1440 2009-11-02 Paul Brook <paul@codesourcery.com>
1442 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1443 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1444 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1445 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1446 FPU_ARCH_NEON_VFP_V4): Define.
1448 2009-10-23 Doug Evans <dje@sebabeach.org>
1450 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1451 * cgen.h: Update. Improve multi-inclusion macro name.
1453 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1455 * ppc.h (PPC_OPCODE_476): Define.
1457 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1459 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1461 2009-09-29 DJ Delorie <dj@redhat.com>
1465 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1467 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1469 2009-09-21 Ben Elliston <bje@au.ibm.com>
1471 * ppc.h (PPC_OPCODE_PPCA2): New.
1473 2009-09-05 Martin Thuresson <martin@mtme.org>
1475 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1477 2009-08-29 Martin Thuresson <martin@mtme.org>
1479 * tic30.h (template): Rename type template to
1480 insn_template. Updated code to use new name.
1481 * tic54x.h (template): Rename type template to
1484 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1486 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1488 2009-06-11 Anthony Green <green@moxielogic.com>
1490 * moxie.h (MOXIE_F3_PCREL): Define.
1491 (moxie_form3_opc_info): Grow.
1493 2009-06-06 Anthony Green <green@moxielogic.com>
1495 * moxie.h (MOXIE_F1_M): Define.
1497 2009-04-15 Anthony Green <green@moxielogic.com>
1501 2009-04-06 DJ Delorie <dj@redhat.com>
1503 * h8300.h: Add relaxation attributes to MOVA opcodes.
1505 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1507 * ppc.h (ppc_parse_cpu): Declare.
1509 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1511 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1512 and _IMM11 for mbitclr and mbitset.
1513 * score-datadep.h: Update dependency information.
1515 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1517 * ppc.h (PPC_OPCODE_POWER7): New.
1519 2009-02-06 Doug Evans <dje@google.com>
1521 * i386.h: Add comment regarding sse* insns and prefixes.
1523 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1525 * mips.h (INSN_XLR): Define.
1526 (INSN_CHIP_MASK): Update.
1528 (OPCODE_IS_MEMBER): Update.
1529 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1531 2009-01-28 Doug Evans <dje@google.com>
1533 * opcode/i386.h: Add multiple inclusion protection.
1534 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1535 (EDI_REG_NUM): New macros.
1536 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1537 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1538 (REX_PREFIX_P): New macro.
1540 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1542 * ppc.h (struct powerpc_opcode): New field "deprecated".
1543 (PPC_OPCODE_NOPOWER4): Delete.
1545 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1547 * mips.h: Define CPU_R14000, CPU_R16000.
1548 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1550 2008-11-18 Catherine Moore <clm@codesourcery.com>
1552 * arm.h (FPU_NEON_FP16): New.
1553 (FPU_ARCH_NEON_FP16): New.
1555 2008-11-06 Chao-ying Fu <fu@mips.com>
1557 * mips.h: Doucument '1' for 5-bit sync type.
1559 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1561 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1564 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1566 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1568 2008-07-30 Michael J. Eager <eager@eagercon.com>
1570 * ppc.h (PPC_OPCODE_405): Define.
1571 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1573 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1575 * ppc.h (ppc_cpu_t): New typedef.
1576 (struct powerpc_opcode <flags>): Use it.
1577 (struct powerpc_operand <insert, extract>): Likewise.
1578 (struct powerpc_macro <flags>): Likewise.
1580 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1582 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1583 Update comment before MIPS16 field descriptors to mention MIPS16.
1584 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1586 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1587 New bit masks and shift counts for cins and exts.
1589 * mips.h: Document new field descriptors +Q.
1590 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1592 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1594 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1595 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1597 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1599 * ppc.h: (PPC_OPCODE_E500MC): New.
1601 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1603 * i386.h (MAX_OPERANDS): Set to 5.
1604 (MAX_MNEM_SIZE): Changed to 20.
1606 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1608 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1610 2008-03-09 Paul Brook <paul@codesourcery.com>
1612 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1614 2008-03-04 Paul Brook <paul@codesourcery.com>
1616 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1617 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1618 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1620 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1621 Nick Clifton <nickc@redhat.com>
1624 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1625 with a 32-bit displacement but without the top bit of the 4th byte
1628 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1630 * cr16.h (cr16_num_optab): Declared.
1632 2008-02-14 Hakan Ardo <hakan@debian.org>
1635 * avr.h (AVR_ISA_2xxe): Define.
1637 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1639 * mips.h: Update copyright.
1640 (INSN_CHIP_MASK): New macro.
1641 (INSN_OCTEON): New macro.
1642 (CPU_OCTEON): New macro.
1643 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1645 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1647 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1649 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1651 * avr.h (AVR_ISA_USB162): Add new opcode set.
1652 (AVR_ISA_AVR3): Likewise.
1654 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1656 * mips.h (INSN_LOONGSON_2E): New.
1657 (INSN_LOONGSON_2F): New.
1658 (CPU_LOONGSON_2E): New.
1659 (CPU_LOONGSON_2F): New.
1660 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1662 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1664 * mips.h (INSN_ISA*): Redefine certain values as an
1665 enumeration. Update comments.
1666 (mips_isa_table): New.
1667 (ISA_MIPS*): Redefine to match enumeration.
1668 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1671 2007-08-08 Ben Elliston <bje@au.ibm.com>
1673 * ppc.h (PPC_OPCODE_PPCPS): New.
1675 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1677 * m68k.h: Document j K & E.
1679 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1681 * cr16.h: New file for CR16 target.
1683 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1685 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1687 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1689 * m68k.h (mcfisa_c): New.
1690 (mcfusp, mcf_mask): Adjust.
1692 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1694 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1695 (num_powerpc_operands): Declare.
1696 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1697 (PPC_OPERAND_PLUS1): Define.
1699 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1701 * i386.h (REX_MODE64): Renamed to ...
1703 (REX_EXTX): Renamed to ...
1705 (REX_EXTY): Renamed to ...
1707 (REX_EXTZ): Renamed to ...
1710 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1712 * i386.h: Add entries from config/tc-i386.h and move tables
1713 to opcodes/i386-opc.h.
1715 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1717 * i386.h (FloatDR): Removed.
1718 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1720 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1722 * spu-insns.h: Add soma double-float insns.
1724 2007-02-20 Thiemo Seufer <ths@mips.com>
1725 Chao-Ying Fu <fu@mips.com>
1727 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1728 (INSN_DSPR2): Add flag for DSP R2 instructions.
1729 (M_BALIGN): New macro.
1731 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1733 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1734 and Seg3ShortFrom with Shortform.
1736 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1739 * i386.h (i386_optab): Put the real "test" before the pseudo
1742 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1744 * m68k.h (m68010up): OR fido_a.
1746 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1748 * m68k.h (fido_a): New.
1750 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1752 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1753 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1756 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1758 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1760 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1762 * score-inst.h (enum score_insn_type): Add Insn_internal.
1764 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1765 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1766 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1767 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1768 Alan Modra <amodra@bigpond.net.au>
1770 * spu-insns.h: New file.
1773 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1775 * ppc.h (PPC_OPCODE_CELL): Define.
1777 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1779 * i386.h : Modify opcode to support for the change in POPCNT opcode
1780 in amdfam10 architecture.
1782 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1784 * i386.h: Replace CpuMNI with CpuSSSE3.
1786 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1787 Joseph Myers <joseph@codesourcery.com>
1788 Ian Lance Taylor <ian@wasabisystems.com>
1789 Ben Elliston <bje@wasabisystems.com>
1791 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1793 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1795 * score-datadep.h: New file.
1796 * score-inst.h: New file.
1798 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1800 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1801 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1802 movdq2q and movq2dq.
1804 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1805 Michael Meissner <michael.meissner@amd.com>
1807 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1809 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1811 * i386.h (i386_optab): Add "nop" with memory reference.
1813 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1815 * i386.h (i386_optab): Update comment for 64bit NOP.
1817 2006-06-06 Ben Elliston <bje@au.ibm.com>
1818 Anton Blanchard <anton@samba.org>
1820 * ppc.h (PPC_OPCODE_POWER6): Define.
1823 2006-06-05 Thiemo Seufer <ths@mips.com>
1825 * mips.h: Improve description of MT flags.
1827 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1829 * m68k.h (mcf_mask): Define.
1831 2006-05-05 Thiemo Seufer <ths@mips.com>
1832 David Ung <davidu@mips.com>
1834 * mips.h (enum): Add macro M_CACHE_AB.
1836 2006-05-04 Thiemo Seufer <ths@mips.com>
1837 Nigel Stephens <nigel@mips.com>
1838 David Ung <davidu@mips.com>
1840 * mips.h: Add INSN_SMARTMIPS define.
1842 2006-04-30 Thiemo Seufer <ths@mips.com>
1843 David Ung <davidu@mips.com>
1845 * mips.h: Defines udi bits and masks. Add description of
1846 characters which may appear in the args field of udi
1849 2006-04-26 Thiemo Seufer <ths@networkno.de>
1851 * mips.h: Improve comments describing the bitfield instruction
1854 2006-04-26 Julian Brown <julian@codesourcery.com>
1856 * arm.h (FPU_VFP_EXT_V3): Define constant.
1857 (FPU_NEON_EXT_V1): Likewise.
1858 (FPU_VFP_HARD): Update.
1859 (FPU_VFP_V3): Define macro.
1860 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1862 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1864 * avr.h (AVR_ISA_PWMx): New.
1866 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1868 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1869 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1870 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1871 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1872 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1874 2006-03-10 Paul Brook <paul@codesourcery.com>
1876 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1878 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1880 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1881 first. Correct mask of bb "B" opcode.
1883 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1885 * i386.h (i386_optab): Support Intel Merom New Instructions.
1887 2006-02-24 Paul Brook <paul@codesourcery.com>
1889 * arm.h: Add V7 feature bits.
1891 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1893 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1895 2006-01-31 Paul Brook <paul@codesourcery.com>
1896 Richard Earnshaw <rearnsha@arm.com>
1898 * arm.h: Use ARM_CPU_FEATURE.
1899 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1900 (arm_feature_set): Change to a structure.
1901 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1902 ARM_FEATURE): New macros.
1904 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1906 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1907 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1908 (ADD_PC_INCR_OPCODE): Don't define.
1910 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1913 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1915 2005-11-14 David Ung <davidu@mips.com>
1917 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1918 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1919 save/restore encoding of the args field.
1921 2005-10-28 Dave Brolley <brolley@redhat.com>
1923 Contribute the following changes:
1924 2005-02-16 Dave Brolley <brolley@redhat.com>
1926 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1927 cgen_isa_mask_* to cgen_bitset_*.
1930 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1932 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1933 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1934 (CGEN_CPU_TABLE): Make isas a ponter.
1936 2003-09-29 Dave Brolley <brolley@redhat.com>
1938 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1939 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1940 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1942 2002-12-13 Dave Brolley <brolley@redhat.com>
1944 * cgen.h (symcat.h): #include it.
1945 (cgen-bitset.h): #include it.
1946 (CGEN_ATTR_VALUE_TYPE): Now a union.
1947 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1948 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1949 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1950 * cgen-bitset.h: New file.
1952 2005-09-30 Catherine Moore <clm@cm00re.com>
1956 2005-10-24 Jan Beulich <jbeulich@novell.com>
1958 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1961 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1963 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1964 Add FLAG_STRICT to pa10 ftest opcode.
1966 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1968 * hppa.h (pa_opcodes): Remove lha entries.
1970 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1972 * hppa.h (FLAG_STRICT): Revise comment.
1973 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1974 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1977 2005-09-30 Catherine Moore <clm@cm00re.com>
1981 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1983 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1985 2005-09-06 Chao-ying Fu <fu@mips.com>
1987 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1988 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1990 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1991 (INSN_ASE_MASK): Update to include INSN_MT.
1992 (INSN_MT): New define for MT ASE.
1994 2005-08-25 Chao-ying Fu <fu@mips.com>
1996 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1997 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1998 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1999 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
2000 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
2001 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
2003 (INSN_DSP): New define for DSP ASE.
2005 2005-08-18 Alan Modra <amodra@bigpond.net.au>
2009 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
2011 * ppc.h (PPC_OPCODE_E300): Define.
2013 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
2015 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
2017 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2020 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2023 2005-07-27 Jan Beulich <jbeulich@novell.com>
2025 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2026 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2027 Add movq-s as 64-bit variants of movd-s.
2029 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2031 * hppa.h: Fix punctuation in comment.
2033 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2034 implicit space-register addressing. Set space-register bits on opcodes
2035 using implicit space-register addressing. Add various missing pa20
2036 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2037 space-register addressing. Use "fE" instead of "fe" in various
2040 2005-07-18 Jan Beulich <jbeulich@novell.com>
2042 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2044 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2046 * i386.h (i386_optab): Support Intel VMX Instructions.
2048 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2050 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2052 2005-07-05 Jan Beulich <jbeulich@novell.com>
2054 * i386.h (i386_optab): Add new insns.
2056 2005-07-01 Nick Clifton <nickc@redhat.com>
2058 * sparc.h: Add typedefs to structure declarations.
2060 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2063 * i386.h (i386_optab): Update comments for 64bit addressing on
2064 mov. Allow 64bit addressing for mov and movq.
2066 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2068 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2069 respectively, in various floating-point load and store patterns.
2071 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2073 * hppa.h (FLAG_STRICT): Correct comment.
2074 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2075 PA 2.0 mneumonics when equivalent. Entries with cache control
2076 completers now require PA 1.1. Adjust whitespace.
2078 2005-05-19 Anton Blanchard <anton@samba.org>
2080 * ppc.h (PPC_OPCODE_POWER5): Define.
2082 2005-05-10 Nick Clifton <nickc@redhat.com>
2084 * Update the address and phone number of the FSF organization in
2085 the GPL notices in the following files:
2086 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2087 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2088 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2089 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2090 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2091 tic54x.h, tic80.h, v850.h, vax.h
2093 2005-05-09 Jan Beulich <jbeulich@novell.com>
2095 * i386.h (i386_optab): Add ht and hnt.
2097 2005-04-18 Mark Kettenis <kettenis@gnu.org>
2099 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2100 Add xcrypt-ctr. Provide aliases without hyphens.
2102 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2104 Moved from ../ChangeLog
2106 2005-04-12 Paul Brook <paul@codesourcery.com>
2107 * m88k.h: Rename psr macros to avoid conflicts.
2109 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2110 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2111 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2112 and ARM_ARCH_V6ZKT2.
2114 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2115 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2116 Remove redundant instruction types.
2117 (struct argument): X_op - new field.
2118 (struct cst4_entry): Remove.
2119 (no_op_insn): Declare.
2121 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2122 * crx.h (enum argtype): Rename types, remove unused types.
2124 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2125 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2126 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2127 (enum operand_type): Rearrange operands, edit comments.
2128 replace us<N> with ui<N> for unsigned immediate.
2129 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2130 displacements (respectively).
2131 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2132 (instruction type): Add NO_TYPE_INS.
2133 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2134 (operand_entry): New field - 'flags'.
2135 (operand flags): New.
2137 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2138 * crx.h (operand_type): Remove redundant types i3, i4,
2140 Add new unsigned immediate types us3, us4, us5, us16.
2142 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2144 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2145 adjust them accordingly.
2147 2005-04-01 Jan Beulich <jbeulich@novell.com>
2149 * i386.h (i386_optab): Add rdtscp.
2151 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2153 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2154 between memory and segment register. Allow movq for moving between
2155 general-purpose register and segment register.
2157 2005-02-09 Jan Beulich <jbeulich@novell.com>
2160 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2161 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2164 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2166 * m68k.h (m68008, m68ec030, m68882): Remove.
2168 (cpu_m68k, cpu_cf): New.
2169 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2170 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2172 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2174 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2175 * cgen.h (enum cgen_parse_operand_type): Add
2176 CGEN_PARSE_OPERAND_SYMBOLIC.
2178 2005-01-21 Fred Fish <fnf@specifixinc.com>
2180 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2181 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2182 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2184 2005-01-19 Fred Fish <fnf@specifixinc.com>
2186 * mips.h (struct mips_opcode): Add new pinfo2 member.
2187 (INSN_ALIAS): New define for opcode table entries that are
2188 specific instances of another entry, such as 'move' for an 'or'
2189 with a zero operand.
2190 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2191 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2193 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2195 * mips.h (CPU_RM9000): Define.
2196 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2198 2004-11-25 Jan Beulich <jbeulich@novell.com>
2200 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2201 to/from test registers are illegal in 64-bit mode. Add missing
2202 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2203 (previously one had to explicitly encode a rex64 prefix). Re-enable
2204 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2205 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2207 2004-11-23 Jan Beulich <jbeulich@novell.com>
2209 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2210 available only with SSE2. Change the MMX additions introduced by SSE
2211 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2212 instructions by their now designated identifier (since combining i686
2213 and 3DNow! does not really imply 3DNow!A).
2215 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2217 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2218 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2220 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2221 Vineet Sharma <vineets@noida.hcltech.com>
2223 * maxq.h: New file: Disassembly information for the maxq port.
2225 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2227 * i386.h (i386_optab): Put back "movzb".
2229 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2231 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2232 comments. Remove member cris_ver_sim. Add members
2233 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2234 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2235 (struct cris_support_reg, struct cris_cond15): New types.
2236 (cris_conds15): Declare.
2237 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2238 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2239 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2240 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2241 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2242 SIZE_FIELD_UNSIGNED.
2244 2004-11-04 Jan Beulich <jbeulich@novell.com>
2246 * i386.h (sldx_Suf): Remove.
2247 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2248 (q_FP): Define, implying no REX64.
2249 (x_FP, sl_FP): Imply FloatMF.
2250 (i386_optab): Split reg and mem forms of moving from segment registers
2251 so that the memory forms can ignore the 16-/32-bit operand size
2252 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2253 all non-floating-point instructions. Unite 32- and 64-bit forms of
2254 movsx, movzx, and movd. Adjust floating point operations for the above
2255 changes to the *FP macros. Add DefaultSize to floating point control
2256 insns operating on larger memory ranges. Remove left over comments
2257 hinting at certain insns being Intel-syntax ones where the ones
2258 actually meant are already gone.
2260 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2262 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2265 2004-09-30 Paul Brook <paul@codesourcery.com>
2267 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2268 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2270 2004-09-11 Theodore A. Roth <troth@openavr.org>
2272 * avr.h: Add support for
2273 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2275 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2277 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2279 2004-08-24 Dmitry Diky <diwil@spec.ru>
2281 * msp430.h (msp430_opc): Add new instructions.
2282 (msp430_rcodes): Declare new instructions.
2283 (msp430_hcodes): Likewise..
2285 2004-08-13 Nick Clifton <nickc@redhat.com>
2288 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2291 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2293 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2295 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2297 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2299 2004-07-21 Jan Beulich <jbeulich@novell.com>
2301 * i386.h: Adjust instruction descriptions to better match the
2304 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2306 * arm.h: Remove all old content. Replace with architecture defines
2307 from gas/config/tc-arm.c.
2309 2004-07-09 Andreas Schwab <schwab@suse.de>
2311 * m68k.h: Fix comment.
2313 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2317 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2319 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2321 2004-05-24 Peter Barada <peter@the-baradas.com>
2323 * m68k.h: Add 'size' to m68k_opcode.
2325 2004-05-05 Peter Barada <peter@the-baradas.com>
2327 * m68k.h: Switch from ColdFire chip name to core variant.
2329 2004-04-22 Peter Barada <peter@the-baradas.com>
2331 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2332 descriptions for new EMAC cases.
2333 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2334 handle Motorola MAC syntax.
2335 Allow disassembly of ColdFire V4e object files.
2337 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2339 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2341 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2343 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2345 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2347 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2349 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2351 * i386.h (i386_optab): Added xstore/xcrypt insns.
2353 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2355 * h8300.h (32bit ldc/stc): Add relaxing support.
2357 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2359 * h8300.h (BITOP): Pass MEMRELAX flag.
2361 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2363 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2366 For older changes see ChangeLog-9103
2368 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2370 Copying and distribution of this file, with or without modification,
2371 are permitted in any medium without royalty provided the copyright
2372 notice and this notice are preserved.
2378 version-control: never
projects / external / binutils.git / blob