1 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
3 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
4 and _IMM11 for mbitclr and mbitset.
5 * score-datadep.h: Update dependency information.
7 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
9 * ppc.h (PPC_OPCODE_POWER7): New.
11 2009-02-06 Doug Evans <dje@google.com>
13 * i386.h: Add comment regarding sse* insns and prefixes.
15 2009-02-03 Sandip Matte <sandip@rmicorp.com>
17 * mips.h (INSN_XLR): Define.
18 (INSN_CHIP_MASK): Update.
20 (OPCODE_IS_MEMBER): Update.
21 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
23 2009-01-28 Doug Evans <dje@google.com>
25 * opcode/i386.h: Add multiple inclusion protection.
26 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
27 (EDI_REG_NUM): New macros.
28 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
29 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
30 (REX_PREFIX_P): New macro.
32 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
34 * ppc.h (struct powerpc_opcode): New field "deprecated".
35 (PPC_OPCODE_NOPOWER4): Delete.
37 2008-11-28 Joshua Kinard <kumba@gentoo.org>
39 * mips.h: Define CPU_R14000, CPU_R16000.
40 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
42 2008-11-18 Catherine Moore <clm@codesourcery.com>
44 * arm.h (FPU_NEON_FP16): New.
45 (FPU_ARCH_NEON_FP16): New.
47 2008-11-06 Chao-ying Fu <fu@mips.com>
49 * mips.h: Doucument '1' for 5-bit sync type.
51 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
53 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
56 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
58 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
60 2008-07-30 Michael J. Eager <eager@eagercon.com>
62 * ppc.h (PPC_OPCODE_405): Define.
63 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
65 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
67 * ppc.h (ppc_cpu_t): New typedef.
68 (struct powerpc_opcode <flags>): Use it.
69 (struct powerpc_operand <insert, extract>): Likewise.
70 (struct powerpc_macro <flags>): Likewise.
72 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
74 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
75 Update comment before MIPS16 field descriptors to mention MIPS16.
76 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
78 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
79 New bit masks and shift counts for cins and exts.
81 * mips.h: Document new field descriptors +Q.
82 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
84 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
86 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
87 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
89 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
91 * ppc.h: (PPC_OPCODE_E500MC): New.
93 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
95 * i386.h (MAX_OPERANDS): Set to 5.
96 (MAX_MNEM_SIZE): Changed to 20.
98 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
100 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
102 2008-03-09 Paul Brook <paul@codesourcery.com>
104 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
106 2008-03-04 Paul Brook <paul@codesourcery.com>
108 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
109 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
110 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
112 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
113 Nick Clifton <nickc@redhat.com>
116 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
117 with a 32-bit displacement but without the top bit of the 4th byte
120 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
122 * cr16.h (cr16_num_optab): Declared.
124 2008-02-14 Hakan Ardo <hakan@debian.org>
127 * avr.h (AVR_ISA_2xxe): Define.
129 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
131 * mips.h: Update copyright.
132 (INSN_CHIP_MASK): New macro.
133 (INSN_OCTEON): New macro.
134 (CPU_OCTEON): New macro.
135 (OPCODE_IS_MEMBER): Handle Octeon instructions.
137 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
139 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
141 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
143 * avr.h (AVR_ISA_USB162): Add new opcode set.
144 (AVR_ISA_AVR3): Likewise.
146 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
148 * mips.h (INSN_LOONGSON_2E): New.
149 (INSN_LOONGSON_2F): New.
150 (CPU_LOONGSON_2E): New.
151 (CPU_LOONGSON_2F): New.
152 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
154 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
156 * mips.h (INSN_ISA*): Redefine certain values as an
157 enumeration. Update comments.
158 (mips_isa_table): New.
159 (ISA_MIPS*): Redefine to match enumeration.
160 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
163 2007-08-08 Ben Elliston <bje@au.ibm.com>
165 * ppc.h (PPC_OPCODE_PPCPS): New.
167 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
169 * m68k.h: Document j K & E.
171 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
173 * cr16.h: New file for CR16 target.
175 2007-05-02 Alan Modra <amodra@bigpond.net.au>
177 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
179 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
181 * m68k.h (mcfisa_c): New.
182 (mcfusp, mcf_mask): Adjust.
184 2007-04-20 Alan Modra <amodra@bigpond.net.au>
186 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
187 (num_powerpc_operands): Declare.
188 (PPC_OPERAND_SIGNED et al): Redefine as hex.
189 (PPC_OPERAND_PLUS1): Define.
191 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
193 * i386.h (REX_MODE64): Renamed to ...
195 (REX_EXTX): Renamed to ...
197 (REX_EXTY): Renamed to ...
199 (REX_EXTZ): Renamed to ...
202 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
204 * i386.h: Add entries from config/tc-i386.h and move tables
205 to opcodes/i386-opc.h.
207 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
209 * i386.h (FloatDR): Removed.
210 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
212 2007-03-01 Alan Modra <amodra@bigpond.net.au>
214 * spu-insns.h: Add soma double-float insns.
216 2007-02-20 Thiemo Seufer <ths@mips.com>
217 Chao-Ying Fu <fu@mips.com>
219 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
220 (INSN_DSPR2): Add flag for DSP R2 instructions.
221 (M_BALIGN): New macro.
223 2007-02-14 Alan Modra <amodra@bigpond.net.au>
225 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
226 and Seg3ShortFrom with Shortform.
228 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
231 * i386.h (i386_optab): Put the real "test" before the pseudo
234 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
236 * m68k.h (m68010up): OR fido_a.
238 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
240 * m68k.h (fido_a): New.
242 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
244 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
245 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
248 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
250 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
252 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
254 * score-inst.h (enum score_insn_type): Add Insn_internal.
256 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
257 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
258 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
259 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
260 Alan Modra <amodra@bigpond.net.au>
262 * spu-insns.h: New file.
265 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
267 * ppc.h (PPC_OPCODE_CELL): Define.
269 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
271 * i386.h : Modify opcode to support for the change in POPCNT opcode
272 in amdfam10 architecture.
274 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
276 * i386.h: Replace CpuMNI with CpuSSSE3.
278 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
279 Joseph Myers <joseph@codesourcery.com>
280 Ian Lance Taylor <ian@wasabisystems.com>
281 Ben Elliston <bje@wasabisystems.com>
283 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
285 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
287 * score-datadep.h: New file.
288 * score-inst.h: New file.
290 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
292 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
293 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
296 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
297 Michael Meissner <michael.meissner@amd.com>
299 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
301 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
303 * i386.h (i386_optab): Add "nop" with memory reference.
305 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
307 * i386.h (i386_optab): Update comment for 64bit NOP.
309 2006-06-06 Ben Elliston <bje@au.ibm.com>
310 Anton Blanchard <anton@samba.org>
312 * ppc.h (PPC_OPCODE_POWER6): Define.
315 2006-06-05 Thiemo Seufer <ths@mips.com>
317 * mips.h: Improve description of MT flags.
319 2006-05-25 Richard Sandiford <richard@codesourcery.com>
321 * m68k.h (mcf_mask): Define.
323 2006-05-05 Thiemo Seufer <ths@mips.com>
324 David Ung <davidu@mips.com>
326 * mips.h (enum): Add macro M_CACHE_AB.
328 2006-05-04 Thiemo Seufer <ths@mips.com>
329 Nigel Stephens <nigel@mips.com>
330 David Ung <davidu@mips.com>
332 * mips.h: Add INSN_SMARTMIPS define.
334 2006-04-30 Thiemo Seufer <ths@mips.com>
335 David Ung <davidu@mips.com>
337 * mips.h: Defines udi bits and masks. Add description of
338 characters which may appear in the args field of udi
341 2006-04-26 Thiemo Seufer <ths@networkno.de>
343 * mips.h: Improve comments describing the bitfield instruction
346 2006-04-26 Julian Brown <julian@codesourcery.com>
348 * arm.h (FPU_VFP_EXT_V3): Define constant.
349 (FPU_NEON_EXT_V1): Likewise.
350 (FPU_VFP_HARD): Update.
351 (FPU_VFP_V3): Define macro.
352 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
354 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
356 * avr.h (AVR_ISA_PWMx): New.
358 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
360 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
361 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
362 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
363 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
364 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
366 2006-03-10 Paul Brook <paul@codesourcery.com>
368 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
370 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
372 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
373 first. Correct mask of bb "B" opcode.
375 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
377 * i386.h (i386_optab): Support Intel Merom New Instructions.
379 2006-02-24 Paul Brook <paul@codesourcery.com>
381 * arm.h: Add V7 feature bits.
383 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
385 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
387 2006-01-31 Paul Brook <paul@codesourcery.com>
388 Richard Earnshaw <rearnsha@arm.com>
390 * arm.h: Use ARM_CPU_FEATURE.
391 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
392 (arm_feature_set): Change to a structure.
393 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
394 ARM_FEATURE): New macros.
396 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
398 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
399 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
400 (ADD_PC_INCR_OPCODE): Don't define.
402 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
405 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
407 2005-11-14 David Ung <davidu@mips.com>
409 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
410 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
411 save/restore encoding of the args field.
413 2005-10-28 Dave Brolley <brolley@redhat.com>
415 Contribute the following changes:
416 2005-02-16 Dave Brolley <brolley@redhat.com>
418 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
419 cgen_isa_mask_* to cgen_bitset_*.
422 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
424 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
425 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
426 (CGEN_CPU_TABLE): Make isas a ponter.
428 2003-09-29 Dave Brolley <brolley@redhat.com>
430 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
431 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
432 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
434 2002-12-13 Dave Brolley <brolley@redhat.com>
436 * cgen.h (symcat.h): #include it.
437 (cgen-bitset.h): #include it.
438 (CGEN_ATTR_VALUE_TYPE): Now a union.
439 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
440 (CGEN_ATTR_ENTRY): 'value' now unsigned.
441 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
442 * cgen-bitset.h: New file.
444 2005-09-30 Catherine Moore <clm@cm00re.com>
448 2005-10-24 Jan Beulich <jbeulich@novell.com>
450 * ia64.h (enum ia64_opnd): Move memory operand out of set of
453 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
455 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
456 Add FLAG_STRICT to pa10 ftest opcode.
458 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
460 * hppa.h (pa_opcodes): Remove lha entries.
462 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
464 * hppa.h (FLAG_STRICT): Revise comment.
465 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
466 before corresponding pa11 opcodes. Add strict pa10 register-immediate
469 2005-09-30 Catherine Moore <clm@cm00re.com>
473 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
475 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
477 2005-09-06 Chao-ying Fu <fu@mips.com>
479 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
480 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
482 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
483 (INSN_ASE_MASK): Update to include INSN_MT.
484 (INSN_MT): New define for MT ASE.
486 2005-08-25 Chao-ying Fu <fu@mips.com>
488 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
489 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
490 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
491 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
492 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
493 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
495 (INSN_DSP): New define for DSP ASE.
497 2005-08-18 Alan Modra <amodra@bigpond.net.au>
501 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
503 * ppc.h (PPC_OPCODE_E300): Define.
505 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
507 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
509 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
512 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
515 2005-07-27 Jan Beulich <jbeulich@novell.com>
517 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
518 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
519 Add movq-s as 64-bit variants of movd-s.
521 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
523 * hppa.h: Fix punctuation in comment.
525 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
526 implicit space-register addressing. Set space-register bits on opcodes
527 using implicit space-register addressing. Add various missing pa20
528 long-immediate opcodes. Remove various opcodes using implicit 3-bit
529 space-register addressing. Use "fE" instead of "fe" in various
532 2005-07-18 Jan Beulich <jbeulich@novell.com>
534 * i386.h (i386_optab): Operands of aam and aad are unsigned.
536 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
538 * i386.h (i386_optab): Support Intel VMX Instructions.
540 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
542 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
544 2005-07-05 Jan Beulich <jbeulich@novell.com>
546 * i386.h (i386_optab): Add new insns.
548 2005-07-01 Nick Clifton <nickc@redhat.com>
550 * sparc.h: Add typedefs to structure declarations.
552 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
555 * i386.h (i386_optab): Update comments for 64bit addressing on
556 mov. Allow 64bit addressing for mov and movq.
558 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
560 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
561 respectively, in various floating-point load and store patterns.
563 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
565 * hppa.h (FLAG_STRICT): Correct comment.
566 (pa_opcodes): Update load and store entries to allow both PA 1.X and
567 PA 2.0 mneumonics when equivalent. Entries with cache control
568 completers now require PA 1.1. Adjust whitespace.
570 2005-05-19 Anton Blanchard <anton@samba.org>
572 * ppc.h (PPC_OPCODE_POWER5): Define.
574 2005-05-10 Nick Clifton <nickc@redhat.com>
576 * Update the address and phone number of the FSF organization in
577 the GPL notices in the following files:
578 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
579 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
580 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
581 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
582 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
583 tic54x.h, tic80.h, v850.h, vax.h
585 2005-05-09 Jan Beulich <jbeulich@novell.com>
587 * i386.h (i386_optab): Add ht and hnt.
589 2005-04-18 Mark Kettenis <kettenis@gnu.org>
591 * i386.h: Insert hyphens into selected VIA PadLock extensions.
592 Add xcrypt-ctr. Provide aliases without hyphens.
594 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
596 Moved from ../ChangeLog
598 2005-04-12 Paul Brook <paul@codesourcery.com>
599 * m88k.h: Rename psr macros to avoid conflicts.
601 2005-03-12 Zack Weinberg <zack@codesourcery.com>
602 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
603 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
606 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
607 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
608 Remove redundant instruction types.
609 (struct argument): X_op - new field.
610 (struct cst4_entry): Remove.
611 (no_op_insn): Declare.
613 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
614 * crx.h (enum argtype): Rename types, remove unused types.
616 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
617 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
618 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
619 (enum operand_type): Rearrange operands, edit comments.
620 replace us<N> with ui<N> for unsigned immediate.
621 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
622 displacements (respectively).
623 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
624 (instruction type): Add NO_TYPE_INS.
625 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
626 (operand_entry): New field - 'flags'.
627 (operand flags): New.
629 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
630 * crx.h (operand_type): Remove redundant types i3, i4,
632 Add new unsigned immediate types us3, us4, us5, us16.
634 2005-04-12 Mark Kettenis <kettenis@gnu.org>
636 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
637 adjust them accordingly.
639 2005-04-01 Jan Beulich <jbeulich@novell.com>
641 * i386.h (i386_optab): Add rdtscp.
643 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
645 * i386.h (i386_optab): Don't allow the `l' suffix for moving
646 between memory and segment register. Allow movq for moving between
647 general-purpose register and segment register.
649 2005-02-09 Jan Beulich <jbeulich@novell.com>
652 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
653 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
656 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
658 * m68k.h (m68008, m68ec030, m68882): Remove.
660 (cpu_m68k, cpu_cf): New.
661 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
662 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
664 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
666 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
667 * cgen.h (enum cgen_parse_operand_type): Add
668 CGEN_PARSE_OPERAND_SYMBOLIC.
670 2005-01-21 Fred Fish <fnf@specifixinc.com>
672 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
673 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
674 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
676 2005-01-19 Fred Fish <fnf@specifixinc.com>
678 * mips.h (struct mips_opcode): Add new pinfo2 member.
679 (INSN_ALIAS): New define for opcode table entries that are
680 specific instances of another entry, such as 'move' for an 'or'
682 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
683 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
685 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
687 * mips.h (CPU_RM9000): Define.
688 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
690 2004-11-25 Jan Beulich <jbeulich@novell.com>
692 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
693 to/from test registers are illegal in 64-bit mode. Add missing
694 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
695 (previously one had to explicitly encode a rex64 prefix). Re-enable
696 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
697 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
699 2004-11-23 Jan Beulich <jbeulich@novell.com>
701 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
702 available only with SSE2. Change the MMX additions introduced by SSE
703 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
704 instructions by their now designated identifier (since combining i686
705 and 3DNow! does not really imply 3DNow!A).
707 2004-11-19 Alan Modra <amodra@bigpond.net.au>
709 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
710 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
712 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
713 Vineet Sharma <vineets@noida.hcltech.com>
715 * maxq.h: New file: Disassembly information for the maxq port.
717 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
719 * i386.h (i386_optab): Put back "movzb".
721 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
723 * cris.h (enum cris_insn_version_usage): Tweak formatting and
724 comments. Remove member cris_ver_sim. Add members
725 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
726 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
727 (struct cris_support_reg, struct cris_cond15): New types.
728 (cris_conds15): Declare.
729 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
730 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
731 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
732 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
733 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
736 2004-11-04 Jan Beulich <jbeulich@novell.com>
738 * i386.h (sldx_Suf): Remove.
739 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
740 (q_FP): Define, implying no REX64.
741 (x_FP, sl_FP): Imply FloatMF.
742 (i386_optab): Split reg and mem forms of moving from segment registers
743 so that the memory forms can ignore the 16-/32-bit operand size
744 distinction. Adjust a few others for Intel mode. Remove *FP uses from
745 all non-floating-point instructions. Unite 32- and 64-bit forms of
746 movsx, movzx, and movd. Adjust floating point operations for the above
747 changes to the *FP macros. Add DefaultSize to floating point control
748 insns operating on larger memory ranges. Remove left over comments
749 hinting at certain insns being Intel-syntax ones where the ones
750 actually meant are already gone.
752 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
754 * crx.h: Add COPS_REG_INS - Coprocessor Special register
757 2004-09-30 Paul Brook <paul@codesourcery.com>
759 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
760 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
762 2004-09-11 Theodore A. Roth <troth@openavr.org>
764 * avr.h: Add support for
765 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
767 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
769 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
771 2004-08-24 Dmitry Diky <diwil@spec.ru>
773 * msp430.h (msp430_opc): Add new instructions.
774 (msp430_rcodes): Declare new instructions.
775 (msp430_hcodes): Likewise..
777 2004-08-13 Nick Clifton <nickc@redhat.com>
780 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
783 2004-08-30 Michal Ludvig <mludvig@suse.cz>
785 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
787 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
789 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
791 2004-07-21 Jan Beulich <jbeulich@novell.com>
793 * i386.h: Adjust instruction descriptions to better match the
796 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
798 * arm.h: Remove all old content. Replace with architecture defines
799 from gas/config/tc-arm.c.
801 2004-07-09 Andreas Schwab <schwab@suse.de>
803 * m68k.h: Fix comment.
805 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
809 2004-06-24 Alan Modra <amodra@bigpond.net.au>
811 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
813 2004-05-24 Peter Barada <peter@the-baradas.com>
815 * m68k.h: Add 'size' to m68k_opcode.
817 2004-05-05 Peter Barada <peter@the-baradas.com>
819 * m68k.h: Switch from ColdFire chip name to core variant.
821 2004-04-22 Peter Barada <peter@the-baradas.com>
823 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
824 descriptions for new EMAC cases.
825 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
826 handle Motorola MAC syntax.
827 Allow disassembly of ColdFire V4e object files.
829 2004-03-16 Alan Modra <amodra@bigpond.net.au>
831 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
833 2004-03-12 Jakub Jelinek <jakub@redhat.com>
835 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
837 2004-03-12 Michal Ludvig <mludvig@suse.cz>
839 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
841 2004-03-12 Michal Ludvig <mludvig@suse.cz>
843 * i386.h (i386_optab): Added xstore/xcrypt insns.
845 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
847 * h8300.h (32bit ldc/stc): Add relaxing support.
849 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
851 * h8300.h (BITOP): Pass MEMRELAX flag.
853 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
855 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
858 For older changes see ChangeLog-9103
864 version-control: never