1 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64.h (AARCH64_V8_1): New.
5 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
7 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
9 (ARM_ARCH_V8_1A_FP): New.
10 (ARM_ARCH_V8_1A_SIMD): New.
11 (ARM_ARCH_V8_1A_CRYPTOV1): New.
12 (ARM_FEATURE_CORE): New.
14 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
16 * arm.h (ARM_EXT2_PAN): New.
17 (ARM_FEATURE_CORE_HIGH): New.
19 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
21 * arm.h (ARM_FEATURE_ALL): New.
23 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
25 * aarch64.h (AARCH64_FEATURE_RDMA): New.
27 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
29 * aarch64.h (AARCH64_FEATURE_LOR): New.
31 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
33 * aarch64.h (AARCH64_FEATURE_PAN): New.
34 (aarch64_sys_reg_supported_p): Declare.
35 (aarch64_pstatefield_supported_p): Declare.
37 2015-04-30 DJ Delorie <dj@redhat.com>
39 * rl78.h (RL78_Dis_Isa): New.
40 (rl78_decode_opcode): Add ISA parameter.
42 2015-03-24 Terry Guo <terry.guo@arm.com>
44 * arm.h (arm_feature_set): Extended to provide more available bits.
45 (ARM_ANY): Updated to follow above new definition.
46 (ARM_CPU_HAS_FEATURE): Likewise.
47 (ARM_CPU_IS_ANY): Likewise.
48 (ARM_MERGE_FEATURE_SETS): Likewise.
49 (ARM_CLEAR_FEATURE): Likewise.
50 (ARM_FEATURE): Likewise.
51 (ARM_FEATURE_COPY): New macro.
52 (ARM_FEATURE_EQUAL): Likewise.
53 (ARM_FEATURE_ZERO): Likewise.
54 (ARM_FEATURE_CORE_EQUAL): Likewise.
55 (ARM_FEATURE_LOW): Likewise.
56 (ARM_FEATURE_CORE_LOW): Likewise.
57 (ARM_FEATURE_CORE_COPROC): Likewise.
59 2015-02-19 Pedro Alves <palves@redhat.com>
61 * cgen.h [__cplusplus]: Wrap in extern "C".
62 * msp430-decode.h [__cplusplus]: Likewise.
63 * nios2.h [__cplusplus]: Likewise.
64 * rl78.h [__cplusplus]: Likewise.
65 * rx.h [__cplusplus]: Likewise.
66 * tilegx.h [__cplusplus]: Likewise.
68 2015-01-28 James Bowman <james.bowman@ftdichip.com>
72 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
74 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
76 2015-01-01 Alan Modra <amodra@gmail.com>
78 Update year range in copyright notice of all files.
80 2014-12-27 Anthony Green <green@moxielogic.com>
82 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
83 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
85 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
89 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
91 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
92 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
93 (NIOS2_INSN_OPTARG): Renumber.
95 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
97 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
98 declaration. Fix obsolete comment.
100 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
102 * nios2.h (enum iw_format_type): New.
103 (struct nios2_opcode): Update comments. Add size and format fields.
104 (NIOS2_INSN_OPTARG): New.
105 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
106 (struct nios2_reg): Add regtype field.
107 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
108 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
109 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
110 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
111 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
112 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
113 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
114 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
115 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
116 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
117 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
118 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
119 (OP_MASK_OP, OP_SH_OP): Delete.
120 (OP_MASK_IOP, OP_SH_IOP): Delete.
121 (OP_MASK_IRD, OP_SH_IRD): Delete.
122 (OP_MASK_IRT, OP_SH_IRT): Delete.
123 (OP_MASK_IRS, OP_SH_IRS): Delete.
124 (OP_MASK_ROP, OP_SH_ROP): Delete.
125 (OP_MASK_RRD, OP_SH_RRD): Delete.
126 (OP_MASK_RRT, OP_SH_RRT): Delete.
127 (OP_MASK_RRS, OP_SH_RRS): Delete.
128 (OP_MASK_JOP, OP_SH_JOP): Delete.
129 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
130 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
131 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
132 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
133 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
134 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
135 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
136 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
137 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
138 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
139 (OP_MASK_<insn>, OP_MASK): Delete.
140 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
141 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
142 Include nios2r1.h to define new instruction opcode constants
144 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
145 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
146 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
147 (NUMOPCODES, NUMREGISTERS): Delete.
148 * nios2r1.h: New file.
150 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
152 * sparc.h (HWCAP2_VIS3B): Documentation improved.
154 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
156 * sparc.h (sparc_opcode): new field `hwcaps2'.
157 (HWCAP2_FJATHPLUS): New define.
158 (HWCAP2_VIS3B): Likewise.
159 (HWCAP2_ADP): Likewise.
160 (HWCAP2_SPARC5): Likewise.
161 (HWCAP2_MWAIT): Likewise.
162 (HWCAP2_XMPMUL): Likewise.
163 (HWCAP2_XMONT): Likewise.
164 (HWCAP2_NSEC): Likewise.
165 (HWCAP2_FJATHHPC): Likewise.
166 (HWCAP2_FJDES): Likewise.
167 (HWCAP2_FJAES): Likewise.
168 Document the new operand kind `{', corresponding to the mcdper
169 ancillary state register.
170 Document the new operand kind }, which represents frsd floating
171 point registers (double precision) which must be the same than
172 frs1 in its containing instruction.
174 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
176 * nds32.h: Add new opcode declaration.
178 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
179 Matthew Fortune <matthew.fortune@imgtec.com>
181 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
182 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
183 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
184 +I, +O, +R, +:, +\, +", +;
185 (mips_check_prev_operand): New struct.
186 (INSN2_FORBIDDEN_SLOT): New define.
187 (INSN_ISA32R6): New define.
188 (INSN_ISA64R6): New define.
189 (INSN_UPTO32R6): New define.
190 (INSN_UPTO64R6): New define.
191 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
192 (ISA_MIPS32R6): New define.
193 (ISA_MIPS64R6): New define.
194 (CPU_MIPS32R6): New define.
195 (CPU_MIPS64R6): New define.
196 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
198 2014-09-03 Jiong Wang <jiong.wang@arm.com>
200 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
201 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
202 (aarch64_insn_class): Add lse_atomic.
203 (F_LSE_SZ): New field added.
204 (opcode_has_special_coder): Recognize F_LSE_SZ.
206 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
208 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
211 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
213 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
214 (INSN_LOAD_COPROC): New define.
215 (INSN_COPROC_MOVE_DELAY): Rename to...
216 (INSN_COPROC_MOVE): New define.
218 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
219 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
220 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
221 Soundararajan <Sounderarajan.D@atmel.com>
223 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
224 (AVR_ISA_2xxxa): Define ISA without LPM.
225 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
226 Add doc for contraint used in 16 bit lds/sts.
227 Adjust ISA group for icall, ijmp, pop and push.
228 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
230 2014-05-19 Nick Clifton <nickc@redhat.com>
232 * msp430.h (struct msp430_operand_s): Add vshift field.
234 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
236 * mips.h (INSN_ISA_MASK): Updated.
237 (INSN_ISA32R3): New define.
238 (INSN_ISA32R5): New define.
239 (INSN_ISA64R3): New define.
240 (INSN_ISA64R5): New define.
241 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
242 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
243 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
245 (INSN_UPTO32R3): New define.
246 (INSN_UPTO32R5): New define.
247 (INSN_UPTO64R3): New define.
248 (INSN_UPTO64R5): New define.
249 (ISA_MIPS32R3): New define.
250 (ISA_MIPS32R5): New define.
251 (ISA_MIPS64R3): New define.
252 (ISA_MIPS64R5): New define.
253 (CPU_MIPS32R3): New define.
254 (CPU_MIPS32R5): New define.
255 (CPU_MIPS64R3): New define.
256 (CPU_MIPS64R5): New define.
258 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
260 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
262 2014-04-22 Christian Svensson <blue@cmd.nu>
266 2014-03-05 Alan Modra <amodra@gmail.com>
268 Update copyright years.
270 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
272 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
275 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
276 Wei-Cheng Wang <cole945@gmail.com>
278 * nds32.h: New file for Andes NDS32.
280 2013-12-07 Mike Frysinger <vapier@gentoo.org>
282 * bfin.h: Remove +x file mode.
284 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
286 * aarch64.h (aarch64_pstatefields): Change element type to
289 2013-11-18 Renlin Li <Renlin.Li@arm.com>
291 * arm.h (ARM_AEXT_V7VE): New define.
292 (ARM_ARCH_V7VE): New define.
293 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
295 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
299 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
301 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
302 (aarch64_sys_reg_writeonly_p): Ditto.
304 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
306 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
307 (aarch64_sys_reg_writeonly_p): Ditto.
309 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
311 * aarch64.h (aarch64_sys_reg): New typedef.
312 (aarch64_sys_regs): Change to define with the new type.
313 (aarch64_sys_reg_deprecated_p): Declare.
315 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
317 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
318 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
320 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
322 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
323 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
324 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
325 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
326 For MIPS, update extension character sequences after +.
327 (ASE_MSA): New define.
328 (ASE_MSA64): New define.
329 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
330 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
331 For microMIPS, update extension character sequences after +.
333 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
338 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
340 * mips.h: Remove references to "+I" and imm2_expr.
342 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
344 * mips.h (M_DEXT, M_DINS): Delete.
346 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
348 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
349 (mips_optional_operand_p): New function.
351 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
352 Richard Sandiford <rdsandiford@googlemail.com>
354 * mips.h: Document new VU0 operand characters.
355 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
356 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
357 (OP_REG_R5900_ACC): New mips_reg_operand_types.
358 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
359 (mips_vu0_channel_mask): Declare.
361 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
363 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
364 (mips_int_operand_min, mips_int_operand_max): New functions.
365 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
367 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
369 * mips.h (mips_decode_reg_operand): New function.
370 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
371 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
372 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
374 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
375 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
376 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
377 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
378 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
379 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
380 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
381 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
382 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
383 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
384 macros to cover the gaps.
385 (INSN2_MOD_SP): Replace with...
386 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
387 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
388 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
389 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
390 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
393 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
395 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
396 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
397 (MIPS16_INSN_COND_BRANCH): Delete.
399 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
400 Kirill Yukhin <kirill.yukhin@intel.com>
401 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
403 * i386.h (BND_PREFIX_OPCODE): New.
405 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
407 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
408 OP_SAVE_RESTORE_LIST.
409 (decode_mips16_operand): Declare.
411 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
413 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
414 (mips_operand, mips_int_operand, mips_mapped_int_operand)
415 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
416 (mips_pcrel_operand): New structures.
417 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
418 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
419 (decode_mips_operand, decode_micromips_operand): Declare.
421 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
423 * mips.h: Document MIPS16 "I" opcode.
425 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
427 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
428 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
429 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
430 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
431 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
432 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
433 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
434 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
435 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
436 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
437 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
438 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
439 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
441 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
442 (M_USD_AB): ...these.
444 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
446 * mips.h: Remove documentation of "[" and "]". Update documentation
447 of "k" and the MDMX formats.
449 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
451 * mips.h: Update documentation of "+s" and "+S".
453 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
455 * mips.h: Document "+i".
457 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
459 * mips.h: Remove "mi" documentation. Update "mh" documentation.
460 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
462 (INSN2_WRITE_GPR_MHI): Rename to...
463 (INSN2_WRITE_GPR_MH): ...this.
465 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
467 * mips.h: Remove documentation of "+D" and "+T".
469 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
471 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
472 Use "source" rather than "destination" for microMIPS "G".
474 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
476 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
479 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
481 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
483 2013-06-17 Catherine Moore <clm@codesourcery.com>
484 Maciej W. Rozycki <macro@codesourcery.com>
485 Chao-Ying Fu <fu@mips.com>
487 * mips.h (OP_SH_EVAOFFSET): Define.
488 (OP_MASK_EVAOFFSET): Define.
489 (INSN_ASE_MASK): Delete.
491 (M_CACHEE_AB, M_CACHEE_OB): New.
492 (M_LBE_OB, M_LBE_AB): New.
493 (M_LBUE_OB, M_LBUE_AB): New.
494 (M_LHE_OB, M_LHE_AB): New.
495 (M_LHUE_OB, M_LHUE_AB): New.
496 (M_LLE_AB, M_LLE_OB): New.
497 (M_LWE_OB, M_LWE_AB): New.
498 (M_LWLE_AB, M_LWLE_OB): New.
499 (M_LWRE_AB, M_LWRE_OB): New.
500 (M_PREFE_AB, M_PREFE_OB): New.
501 (M_SCE_AB, M_SCE_OB): New.
502 (M_SBE_OB, M_SBE_AB): New.
503 (M_SHE_OB, M_SHE_AB): New.
504 (M_SWE_OB, M_SWE_AB): New.
505 (M_SWLE_AB, M_SWLE_OB): New.
506 (M_SWRE_AB, M_SWRE_OB): New.
507 (MICROMIPSOP_SH_EVAOFFSET): Define.
508 (MICROMIPSOP_MASK_EVAOFFSET): Define.
510 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
512 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
514 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
516 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
518 2013-05-09 Andrew Pinski <apinski@cavium.com>
520 * mips.h (OP_MASK_CODE10): Correct definition.
521 (OP_SH_CODE10): Likewise.
522 Add a comment that "+J" is used now for OP_*CODE10.
523 (INSN_ASE_MASK): Update.
524 (INSN_VIRT): New macro.
525 (INSN_VIRT64): New macro
527 2013-05-02 Nick Clifton <nickc@redhat.com>
529 * msp430.h: Add patterns for MSP430X instructions.
531 2013-04-06 David S. Miller <davem@davemloft.net>
533 * sparc.h (F_PREFERRED): Define.
534 (F_PREF_ALIAS): Define.
536 2013-04-03 Nick Clifton <nickc@redhat.com>
538 * v850.h (V850_INVERSE_PCREL): Define.
540 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
543 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
545 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
548 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
550 * tic6xc-opcode-table.h: Add 16-bit insns.
551 * tic6x.h: Add support for 16-bit insns.
553 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
555 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
556 and mov.b/w/l Rs,@(d:32,ERd).
558 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
561 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
562 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
563 tic6x_operand_xregpair operand coding type.
564 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
565 opcode field, usu ORXREGD1324 for the src2 operand and remove the
568 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
571 * tic6x.h (enum tic6x_coding_method): Add
572 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
573 separately the msb and lsb of a register pair. This is needed to
574 encode the opcodes in the same way as TI assembler does.
575 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
576 and rsqrdp opcodes to use the new field coding types.
578 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
580 * arm.h (CRC_EXT_ARMV8): New constant.
581 (ARCH_CRC_ARMV8): New macro.
583 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
585 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
587 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
588 Andrew Jenner <andrew@codesourcery.com>
590 Based on patches from Altera Corporation.
594 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
596 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
598 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
601 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
603 2013-01-24 Nick Clifton <nickc@redhat.com>
605 * v850.h: Add e3v5 support.
607 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
609 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
611 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
613 * ppc.h (PPC_OPCODE_POWER8): New define.
614 (PPC_OPCODE_HTM): Likewise.
616 2013-01-10 Will Newton <will.newton@imgtec.com>
620 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
622 * cr16.h (make_instruction): Rename to cr16_make_instruction.
623 (match_opcode): Rename to cr16_match_opcode.
625 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
627 * mips.h: Add support for r5900 instructions including lq and sq.
629 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
631 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
632 (make_instruction,match_opcode): Added function prototypes.
633 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
635 2012-11-23 Alan Modra <amodra@gmail.com>
637 * ppc.h (ppc_parse_cpu): Update prototype.
639 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
641 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
642 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
644 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
646 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
648 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
650 * ia64.h (ia64_opnd): Add new operand types.
652 2012-08-21 David S. Miller <davem@davemloft.net>
654 * sparc.h (F3F4): New macro.
656 2012-08-13 Ian Bolton <ian.bolton@arm.com>
657 Laurent Desnogues <laurent.desnogues@arm.com>
658 Jim MacArthur <jim.macarthur@arm.com>
659 Marcus Shawcroft <marcus.shawcroft@arm.com>
660 Nigel Stephens <nigel.stephens@arm.com>
661 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
662 Richard Earnshaw <rearnsha@arm.com>
663 Sofiane Naci <sofiane.naci@arm.com>
664 Tejas Belagod <tejas.belagod@arm.com>
665 Yufeng Zhang <yufeng.zhang@arm.com>
667 * aarch64.h: New file.
669 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
670 Maciej W. Rozycki <macro@codesourcery.com>
672 * mips.h (mips_opcode): Add the exclusions field.
673 (OPCODE_IS_MEMBER): Remove macro.
674 (cpu_is_member): New inline function.
675 (opcode_is_member): Likewise.
677 2012-07-31 Chao-Ying Fu <fu@mips.com>
678 Catherine Moore <clm@codesourcery.com>
679 Maciej W. Rozycki <macro@codesourcery.com>
681 * mips.h: Document microMIPS DSP ASE usage.
682 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
683 microMIPS DSP ASE support.
684 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
685 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
686 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
687 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
688 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
689 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
690 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
692 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
694 * mips.h: Fix a typo in description.
696 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
698 * avr.h: (AVR_ISA_XCH): New define.
699 (AVR_ISA_XMEGA): Use it.
700 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
702 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
704 * m68hc11.h: Add XGate definitions.
705 (struct m68hc11_opcode): Add xg_mask field.
707 2012-05-14 Catherine Moore <clm@codesourcery.com>
708 Maciej W. Rozycki <macro@codesourcery.com>
709 Rhonda Wittels <rhonda@codesourcery.com>
711 * ppc.h (PPC_OPCODE_VLE): New definition.
712 (PPC_OP_SA): New macro.
713 (PPC_OP_SE_VLE): New macro.
714 (PPC_OP): Use a variable shift amount.
715 (powerpc_operand): Update comments.
716 (PPC_OPSHIFT_INV): New macro.
717 (PPC_OPERAND_CR): Replace with...
718 (PPC_OPERAND_CR_BIT): ...this and
719 (PPC_OPERAND_CR_REG): ...this.
722 2012-05-03 Sean Keys <skeys@ipdatasys.com>
724 * xgate.h: Header file for XGATE assembler.
726 2012-04-27 David S. Miller <davem@davemloft.net>
728 * sparc.h: Document new arg code' )' for crypto RS3
731 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
732 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
733 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
734 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
735 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
736 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
737 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
738 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
739 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
740 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
741 HWCAP_CBCOND, HWCAP_CRC32): New defines.
743 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
745 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
747 2012-02-27 Alan Modra <amodra@gmail.com>
749 * crx.h (cst4_map): Update declaration.
751 2012-02-25 Walter Lee <walt@tilera.com>
753 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
755 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
756 TILEPRO_OPC_LW_TLS_SN.
758 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
760 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
761 (XRELEASE_PREFIX_OPCODE): Likewise.
763 2011-12-08 Andrew Pinski <apinski@cavium.com>
764 Adam Nemet <anemet@caviumnetworks.com>
766 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
767 (INSN_OCTEON2): New macro.
768 (CPU_OCTEON2): New macro.
769 (OPCODE_IS_MEMBER): Add Octeon2.
771 2011-11-29 Andrew Pinski <apinski@cavium.com>
773 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
774 (INSN_OCTEONP): New macro.
775 (CPU_OCTEONP): New macro.
776 (OPCODE_IS_MEMBER): Add Octeon+.
777 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
779 2011-11-01 DJ Delorie <dj@redhat.com>
783 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
785 * mips.h: Fix a typo in description.
787 2011-09-21 David S. Miller <davem@davemloft.net>
789 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
790 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
791 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
792 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
794 2011-08-09 Chao-ying Fu <fu@mips.com>
795 Maciej W. Rozycki <macro@codesourcery.com>
797 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
798 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
799 (INSN_ASE_MASK): Add the MCU bit.
800 (INSN_MCU): New macro.
801 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
802 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
804 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
806 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
807 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
808 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
809 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
810 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
811 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
812 (INSN2_READ_GPR_MMN): Likewise.
813 (INSN2_READ_FPR_D): Change the bit used.
814 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
815 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
816 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
817 (INSN2_COND_BRANCH): Likewise.
818 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
819 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
820 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
821 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
822 (INSN2_MOD_GPR_MN): Likewise.
824 2011-08-05 David S. Miller <davem@davemloft.net>
826 * sparc.h: Document new format codes '4', '5', and '('.
827 (OPF_LOW4, RS3): New macros.
829 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
831 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
832 order of flags documented.
834 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
836 * mips.h: Clarify the description of microMIPS instruction
838 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
840 2011-07-24 Chao-ying Fu <fu@mips.com>
841 Maciej W. Rozycki <macro@codesourcery.com>
843 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
844 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
845 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
846 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
847 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
848 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
849 (OP_MASK_RS3, OP_SH_RS3): Likewise.
850 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
851 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
852 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
853 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
854 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
855 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
856 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
857 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
858 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
859 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
860 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
861 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
862 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
863 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
864 (INSN_WRITE_GPR_S): New macro.
865 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
866 (INSN2_READ_FPR_D): Likewise.
867 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
868 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
869 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
870 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
871 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
872 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
873 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
874 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
875 (CPU_MICROMIPS): New macro.
876 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
877 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
878 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
879 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
880 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
881 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
882 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
883 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
884 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
885 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
886 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
887 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
888 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
889 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
890 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
891 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
892 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
893 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
894 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
895 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
896 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
897 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
898 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
899 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
900 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
901 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
902 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
903 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
904 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
905 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
906 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
907 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
908 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
909 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
910 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
911 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
912 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
913 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
914 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
915 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
916 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
917 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
918 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
919 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
920 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
921 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
922 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
923 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
924 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
925 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
926 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
927 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
928 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
929 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
930 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
931 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
932 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
933 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
934 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
935 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
936 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
937 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
938 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
939 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
940 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
941 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
942 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
943 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
944 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
945 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
946 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
947 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
948 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
949 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
950 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
951 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
952 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
953 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
954 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
955 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
956 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
957 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
958 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
959 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
960 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
961 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
962 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
963 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
964 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
965 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
966 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
967 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
968 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
969 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
970 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
971 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
972 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
973 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
974 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
975 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
976 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
977 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
978 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
979 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
980 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
981 (micromips_opcodes): New declaration.
982 (bfd_micromips_num_opcodes): Likewise.
984 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
986 * mips.h (INSN_TRAP): Rename to...
987 (INSN_NO_DELAY_SLOT): ... this.
988 (INSN_SYNC): Remove macro.
990 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
992 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
993 a duplicate of AVR_ISA_SPM.
995 2011-07-01 Nick Clifton <nickc@redhat.com>
997 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
999 2011-06-18 Robin Getz <robin.getz@analog.com>
1001 * bfin.h (is_macmod_signed): New func
1003 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1005 * bfin.h (is_macmod_pmove): Add missing space before func args.
1006 (is_macmod_hmove): Likewise.
1008 2011-06-13 Walter Lee <walt@tilera.com>
1010 * tilegx.h: New file.
1011 * tilepro.h: New file.
1013 2011-05-31 Paul Brook <paul@codesourcery.com>
1015 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1017 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1019 * s390.h: Replace S390_OPERAND_REG_EVEN with
1020 S390_OPERAND_REG_PAIR.
1022 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1024 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1026 2011-04-18 Julian Brown <julian@codesourcery.com>
1028 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1030 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1033 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1035 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1037 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1038 New instruction set flags.
1039 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1041 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1043 * mips.h (M_PREF_AB): New enum value.
1045 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1047 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1049 (is_macmod_pmove, is_macmod_hmove): New functions.
1051 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1053 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1055 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1057 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1058 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1060 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1063 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1066 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1069 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1071 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1073 * mips.h: Update commentary after last commit.
1075 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1077 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1078 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1079 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1081 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1083 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1085 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1087 * mips.h: Fix previous commit.
1089 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1091 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1092 (INSN_LOONGSON_3A): Clear bit 31.
1094 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1097 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1098 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1099 (ARM_ARCH_V6M_ONLY): New define.
1101 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1103 * mips.h (INSN_LOONGSON_3A): Defined.
1104 (CPU_LOONGSON_3A): Defined.
1105 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1107 2010-10-09 Matt Rice <ratmice@gmail.com>
1109 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1110 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1112 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1114 * arm.h (ARM_EXT_VIRT): New define.
1115 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1116 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1119 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1121 * arm.h (ARM_AEXT_ADIV): New define.
1122 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1124 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1126 * arm.h (ARM_EXT_OS): New define.
1127 (ARM_AEXT_V6SM): Likewise.
1128 (ARM_ARCH_V6SM): Likewise.
1130 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1132 * arm.h (ARM_EXT_MP): Add.
1133 (ARM_ARCH_V7A_MP): Likewise.
1135 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1137 * bfin.h: Declare pseudoChr structs/defines.
1139 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1141 * bfin.h: Strip trailing whitespace.
1143 2010-07-29 DJ Delorie <dj@redhat.com>
1145 * rx.h (RX_Operand_Type): Add TwoReg.
1146 (RX_Opcode_ID): Remove ediv and ediv2.
1148 2010-07-27 DJ Delorie <dj@redhat.com>
1150 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1152 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1153 Ina Pandit <ina.pandit@kpitcummins.com>
1155 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1156 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1157 PROCESSOR_V850E2_ALL.
1158 Remove PROCESSOR_V850EA support.
1159 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1160 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1161 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1162 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1163 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1164 V850_OPERAND_PERCENT.
1165 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1167 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1170 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1172 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1173 (MIPS16_INSN_BRANCH): Rename to...
1174 (MIPS16_INSN_COND_BRANCH): ... this.
1176 2010-07-03 Alan Modra <amodra@gmail.com>
1178 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1179 Renumber other PPC_OPCODE defines.
1181 2010-07-03 Alan Modra <amodra@gmail.com>
1183 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1185 2010-06-29 Alan Modra <amodra@gmail.com>
1187 * maxq.h: Delete file.
1189 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1191 * ppc.h (PPC_OPCODE_E500): Define.
1193 2010-05-26 Catherine Moore <clm@codesourcery.com>
1195 * opcode/mips.h (INSN_MIPS16): Remove.
1197 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1199 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1201 2010-04-15 Nick Clifton <nickc@redhat.com>
1203 * alpha.h: Update copyright notice to use GPLv3.
1209 * convex.h: Likewise.
1216 * h8300.h: Likewise.
1223 * m68hc11.h: Likewise.
1229 * mn10200.h: Likewise.
1230 * mn10300.h: Likewise.
1231 * msp430.h: Likewise.
1233 * ns32k.h: Likewise.
1235 * pdp11.h: Likewise.
1242 * score-datadep.h: Likewise.
1243 * score-inst.h: Likewise.
1244 * sparc.h: Likewise.
1245 * spu-insns.h: Likewise.
1247 * tic30.h: Likewise.
1248 * tic4x.h: Likewise.
1249 * tic54x.h: Likewise.
1250 * tic80.h: Likewise.
1254 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1256 * tic6x-control-registers.h, tic6x-insn-formats.h,
1257 tic6x-opcode-table.h, tic6x.h: New.
1259 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1261 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1263 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1265 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1267 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1269 * ia64.h (ia64_find_opcode): Remove argument name.
1270 (ia64_find_next_opcode): Likewise.
1271 (ia64_dis_opcode): Likewise.
1272 (ia64_free_opcode): Likewise.
1273 (ia64_find_dependency): Likewise.
1275 2009-11-22 Doug Evans <dje@sebabeach.org>
1277 * cgen.h: Include bfd_stdint.h.
1278 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1280 2009-11-18 Paul Brook <paul@codesourcery.com>
1282 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1284 2009-11-17 Paul Brook <paul@codesourcery.com>
1285 Daniel Jacobowitz <dan@codesourcery.com>
1287 * arm.h (ARM_EXT_V6_DSP): Define.
1288 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1289 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1291 2009-11-04 DJ Delorie <dj@redhat.com>
1293 * rx.h (rx_decode_opcode) (mvtipl): Add.
1294 (mvtcp, mvfcp, opecp): Remove.
1296 2009-11-02 Paul Brook <paul@codesourcery.com>
1298 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1299 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1300 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1301 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1302 FPU_ARCH_NEON_VFP_V4): Define.
1304 2009-10-23 Doug Evans <dje@sebabeach.org>
1306 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1307 * cgen.h: Update. Improve multi-inclusion macro name.
1309 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1311 * ppc.h (PPC_OPCODE_476): Define.
1313 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1315 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1317 2009-09-29 DJ Delorie <dj@redhat.com>
1321 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1323 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1325 2009-09-21 Ben Elliston <bje@au.ibm.com>
1327 * ppc.h (PPC_OPCODE_PPCA2): New.
1329 2009-09-05 Martin Thuresson <martin@mtme.org>
1331 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1333 2009-08-29 Martin Thuresson <martin@mtme.org>
1335 * tic30.h (template): Rename type template to
1336 insn_template. Updated code to use new name.
1337 * tic54x.h (template): Rename type template to
1340 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1342 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1344 2009-06-11 Anthony Green <green@moxielogic.com>
1346 * moxie.h (MOXIE_F3_PCREL): Define.
1347 (moxie_form3_opc_info): Grow.
1349 2009-06-06 Anthony Green <green@moxielogic.com>
1351 * moxie.h (MOXIE_F1_M): Define.
1353 2009-04-15 Anthony Green <green@moxielogic.com>
1357 2009-04-06 DJ Delorie <dj@redhat.com>
1359 * h8300.h: Add relaxation attributes to MOVA opcodes.
1361 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1363 * ppc.h (ppc_parse_cpu): Declare.
1365 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1367 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1368 and _IMM11 for mbitclr and mbitset.
1369 * score-datadep.h: Update dependency information.
1371 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1373 * ppc.h (PPC_OPCODE_POWER7): New.
1375 2009-02-06 Doug Evans <dje@google.com>
1377 * i386.h: Add comment regarding sse* insns and prefixes.
1379 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1381 * mips.h (INSN_XLR): Define.
1382 (INSN_CHIP_MASK): Update.
1384 (OPCODE_IS_MEMBER): Update.
1385 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1387 2009-01-28 Doug Evans <dje@google.com>
1389 * opcode/i386.h: Add multiple inclusion protection.
1390 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1391 (EDI_REG_NUM): New macros.
1392 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1393 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1394 (REX_PREFIX_P): New macro.
1396 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1398 * ppc.h (struct powerpc_opcode): New field "deprecated".
1399 (PPC_OPCODE_NOPOWER4): Delete.
1401 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1403 * mips.h: Define CPU_R14000, CPU_R16000.
1404 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1406 2008-11-18 Catherine Moore <clm@codesourcery.com>
1408 * arm.h (FPU_NEON_FP16): New.
1409 (FPU_ARCH_NEON_FP16): New.
1411 2008-11-06 Chao-ying Fu <fu@mips.com>
1413 * mips.h: Doucument '1' for 5-bit sync type.
1415 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1417 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1420 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1422 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1424 2008-07-30 Michael J. Eager <eager@eagercon.com>
1426 * ppc.h (PPC_OPCODE_405): Define.
1427 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1429 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1431 * ppc.h (ppc_cpu_t): New typedef.
1432 (struct powerpc_opcode <flags>): Use it.
1433 (struct powerpc_operand <insert, extract>): Likewise.
1434 (struct powerpc_macro <flags>): Likewise.
1436 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1438 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1439 Update comment before MIPS16 field descriptors to mention MIPS16.
1440 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1442 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1443 New bit masks and shift counts for cins and exts.
1445 * mips.h: Document new field descriptors +Q.
1446 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1448 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1450 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1451 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1453 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1455 * ppc.h: (PPC_OPCODE_E500MC): New.
1457 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1459 * i386.h (MAX_OPERANDS): Set to 5.
1460 (MAX_MNEM_SIZE): Changed to 20.
1462 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1464 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1466 2008-03-09 Paul Brook <paul@codesourcery.com>
1468 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1470 2008-03-04 Paul Brook <paul@codesourcery.com>
1472 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1473 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1474 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1476 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1477 Nick Clifton <nickc@redhat.com>
1480 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1481 with a 32-bit displacement but without the top bit of the 4th byte
1484 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1486 * cr16.h (cr16_num_optab): Declared.
1488 2008-02-14 Hakan Ardo <hakan@debian.org>
1491 * avr.h (AVR_ISA_2xxe): Define.
1493 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1495 * mips.h: Update copyright.
1496 (INSN_CHIP_MASK): New macro.
1497 (INSN_OCTEON): New macro.
1498 (CPU_OCTEON): New macro.
1499 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1501 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1503 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1505 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1507 * avr.h (AVR_ISA_USB162): Add new opcode set.
1508 (AVR_ISA_AVR3): Likewise.
1510 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1512 * mips.h (INSN_LOONGSON_2E): New.
1513 (INSN_LOONGSON_2F): New.
1514 (CPU_LOONGSON_2E): New.
1515 (CPU_LOONGSON_2F): New.
1516 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1518 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1520 * mips.h (INSN_ISA*): Redefine certain values as an
1521 enumeration. Update comments.
1522 (mips_isa_table): New.
1523 (ISA_MIPS*): Redefine to match enumeration.
1524 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1527 2007-08-08 Ben Elliston <bje@au.ibm.com>
1529 * ppc.h (PPC_OPCODE_PPCPS): New.
1531 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1533 * m68k.h: Document j K & E.
1535 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1537 * cr16.h: New file for CR16 target.
1539 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1541 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1543 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1545 * m68k.h (mcfisa_c): New.
1546 (mcfusp, mcf_mask): Adjust.
1548 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1550 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1551 (num_powerpc_operands): Declare.
1552 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1553 (PPC_OPERAND_PLUS1): Define.
1555 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1557 * i386.h (REX_MODE64): Renamed to ...
1559 (REX_EXTX): Renamed to ...
1561 (REX_EXTY): Renamed to ...
1563 (REX_EXTZ): Renamed to ...
1566 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1568 * i386.h: Add entries from config/tc-i386.h and move tables
1569 to opcodes/i386-opc.h.
1571 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1573 * i386.h (FloatDR): Removed.
1574 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1576 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1578 * spu-insns.h: Add soma double-float insns.
1580 2007-02-20 Thiemo Seufer <ths@mips.com>
1581 Chao-Ying Fu <fu@mips.com>
1583 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1584 (INSN_DSPR2): Add flag for DSP R2 instructions.
1585 (M_BALIGN): New macro.
1587 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1589 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1590 and Seg3ShortFrom with Shortform.
1592 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1595 * i386.h (i386_optab): Put the real "test" before the pseudo
1598 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1600 * m68k.h (m68010up): OR fido_a.
1602 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1604 * m68k.h (fido_a): New.
1606 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1608 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1609 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1612 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1614 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1616 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1618 * score-inst.h (enum score_insn_type): Add Insn_internal.
1620 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1621 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1622 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1623 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1624 Alan Modra <amodra@bigpond.net.au>
1626 * spu-insns.h: New file.
1629 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1631 * ppc.h (PPC_OPCODE_CELL): Define.
1633 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1635 * i386.h : Modify opcode to support for the change in POPCNT opcode
1636 in amdfam10 architecture.
1638 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1640 * i386.h: Replace CpuMNI with CpuSSSE3.
1642 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1643 Joseph Myers <joseph@codesourcery.com>
1644 Ian Lance Taylor <ian@wasabisystems.com>
1645 Ben Elliston <bje@wasabisystems.com>
1647 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1649 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1651 * score-datadep.h: New file.
1652 * score-inst.h: New file.
1654 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1656 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1657 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1658 movdq2q and movq2dq.
1660 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1661 Michael Meissner <michael.meissner@amd.com>
1663 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1665 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1667 * i386.h (i386_optab): Add "nop" with memory reference.
1669 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1671 * i386.h (i386_optab): Update comment for 64bit NOP.
1673 2006-06-06 Ben Elliston <bje@au.ibm.com>
1674 Anton Blanchard <anton@samba.org>
1676 * ppc.h (PPC_OPCODE_POWER6): Define.
1679 2006-06-05 Thiemo Seufer <ths@mips.com>
1681 * mips.h: Improve description of MT flags.
1683 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1685 * m68k.h (mcf_mask): Define.
1687 2006-05-05 Thiemo Seufer <ths@mips.com>
1688 David Ung <davidu@mips.com>
1690 * mips.h (enum): Add macro M_CACHE_AB.
1692 2006-05-04 Thiemo Seufer <ths@mips.com>
1693 Nigel Stephens <nigel@mips.com>
1694 David Ung <davidu@mips.com>
1696 * mips.h: Add INSN_SMARTMIPS define.
1698 2006-04-30 Thiemo Seufer <ths@mips.com>
1699 David Ung <davidu@mips.com>
1701 * mips.h: Defines udi bits and masks. Add description of
1702 characters which may appear in the args field of udi
1705 2006-04-26 Thiemo Seufer <ths@networkno.de>
1707 * mips.h: Improve comments describing the bitfield instruction
1710 2006-04-26 Julian Brown <julian@codesourcery.com>
1712 * arm.h (FPU_VFP_EXT_V3): Define constant.
1713 (FPU_NEON_EXT_V1): Likewise.
1714 (FPU_VFP_HARD): Update.
1715 (FPU_VFP_V3): Define macro.
1716 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1718 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1720 * avr.h (AVR_ISA_PWMx): New.
1722 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1724 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1725 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1726 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1727 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1728 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1730 2006-03-10 Paul Brook <paul@codesourcery.com>
1732 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1734 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1736 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1737 first. Correct mask of bb "B" opcode.
1739 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1741 * i386.h (i386_optab): Support Intel Merom New Instructions.
1743 2006-02-24 Paul Brook <paul@codesourcery.com>
1745 * arm.h: Add V7 feature bits.
1747 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1749 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1751 2006-01-31 Paul Brook <paul@codesourcery.com>
1752 Richard Earnshaw <rearnsha@arm.com>
1754 * arm.h: Use ARM_CPU_FEATURE.
1755 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1756 (arm_feature_set): Change to a structure.
1757 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1758 ARM_FEATURE): New macros.
1760 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1762 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1763 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1764 (ADD_PC_INCR_OPCODE): Don't define.
1766 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1769 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1771 2005-11-14 David Ung <davidu@mips.com>
1773 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1774 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1775 save/restore encoding of the args field.
1777 2005-10-28 Dave Brolley <brolley@redhat.com>
1779 Contribute the following changes:
1780 2005-02-16 Dave Brolley <brolley@redhat.com>
1782 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1783 cgen_isa_mask_* to cgen_bitset_*.
1786 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1788 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1789 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1790 (CGEN_CPU_TABLE): Make isas a ponter.
1792 2003-09-29 Dave Brolley <brolley@redhat.com>
1794 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1795 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1796 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1798 2002-12-13 Dave Brolley <brolley@redhat.com>
1800 * cgen.h (symcat.h): #include it.
1801 (cgen-bitset.h): #include it.
1802 (CGEN_ATTR_VALUE_TYPE): Now a union.
1803 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1804 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1805 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1806 * cgen-bitset.h: New file.
1808 2005-09-30 Catherine Moore <clm@cm00re.com>
1812 2005-10-24 Jan Beulich <jbeulich@novell.com>
1814 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1817 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1819 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1820 Add FLAG_STRICT to pa10 ftest opcode.
1822 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1824 * hppa.h (pa_opcodes): Remove lha entries.
1826 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1828 * hppa.h (FLAG_STRICT): Revise comment.
1829 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1830 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1833 2005-09-30 Catherine Moore <clm@cm00re.com>
1837 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1839 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1841 2005-09-06 Chao-ying Fu <fu@mips.com>
1843 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1844 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1846 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1847 (INSN_ASE_MASK): Update to include INSN_MT.
1848 (INSN_MT): New define for MT ASE.
1850 2005-08-25 Chao-ying Fu <fu@mips.com>
1852 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1853 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1854 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1855 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1856 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1857 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1859 (INSN_DSP): New define for DSP ASE.
1861 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1865 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1867 * ppc.h (PPC_OPCODE_E300): Define.
1869 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1871 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1873 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1876 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1879 2005-07-27 Jan Beulich <jbeulich@novell.com>
1881 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1882 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1883 Add movq-s as 64-bit variants of movd-s.
1885 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1887 * hppa.h: Fix punctuation in comment.
1889 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1890 implicit space-register addressing. Set space-register bits on opcodes
1891 using implicit space-register addressing. Add various missing pa20
1892 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1893 space-register addressing. Use "fE" instead of "fe" in various
1896 2005-07-18 Jan Beulich <jbeulich@novell.com>
1898 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1900 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1902 * i386.h (i386_optab): Support Intel VMX Instructions.
1904 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1906 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1908 2005-07-05 Jan Beulich <jbeulich@novell.com>
1910 * i386.h (i386_optab): Add new insns.
1912 2005-07-01 Nick Clifton <nickc@redhat.com>
1914 * sparc.h: Add typedefs to structure declarations.
1916 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1919 * i386.h (i386_optab): Update comments for 64bit addressing on
1920 mov. Allow 64bit addressing for mov and movq.
1922 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1924 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1925 respectively, in various floating-point load and store patterns.
1927 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1929 * hppa.h (FLAG_STRICT): Correct comment.
1930 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1931 PA 2.0 mneumonics when equivalent. Entries with cache control
1932 completers now require PA 1.1. Adjust whitespace.
1934 2005-05-19 Anton Blanchard <anton@samba.org>
1936 * ppc.h (PPC_OPCODE_POWER5): Define.
1938 2005-05-10 Nick Clifton <nickc@redhat.com>
1940 * Update the address and phone number of the FSF organization in
1941 the GPL notices in the following files:
1942 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1943 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1944 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1945 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1946 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1947 tic54x.h, tic80.h, v850.h, vax.h
1949 2005-05-09 Jan Beulich <jbeulich@novell.com>
1951 * i386.h (i386_optab): Add ht and hnt.
1953 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1955 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1956 Add xcrypt-ctr. Provide aliases without hyphens.
1958 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1960 Moved from ../ChangeLog
1962 2005-04-12 Paul Brook <paul@codesourcery.com>
1963 * m88k.h: Rename psr macros to avoid conflicts.
1965 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1966 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1967 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1968 and ARM_ARCH_V6ZKT2.
1970 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1971 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1972 Remove redundant instruction types.
1973 (struct argument): X_op - new field.
1974 (struct cst4_entry): Remove.
1975 (no_op_insn): Declare.
1977 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1978 * crx.h (enum argtype): Rename types, remove unused types.
1980 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1981 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1982 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1983 (enum operand_type): Rearrange operands, edit comments.
1984 replace us<N> with ui<N> for unsigned immediate.
1985 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1986 displacements (respectively).
1987 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1988 (instruction type): Add NO_TYPE_INS.
1989 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1990 (operand_entry): New field - 'flags'.
1991 (operand flags): New.
1993 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1994 * crx.h (operand_type): Remove redundant types i3, i4,
1996 Add new unsigned immediate types us3, us4, us5, us16.
1998 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2000 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2001 adjust them accordingly.
2003 2005-04-01 Jan Beulich <jbeulich@novell.com>
2005 * i386.h (i386_optab): Add rdtscp.
2007 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2009 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2010 between memory and segment register. Allow movq for moving between
2011 general-purpose register and segment register.
2013 2005-02-09 Jan Beulich <jbeulich@novell.com>
2016 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2017 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2020 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2022 * m68k.h (m68008, m68ec030, m68882): Remove.
2024 (cpu_m68k, cpu_cf): New.
2025 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2026 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2028 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2030 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2031 * cgen.h (enum cgen_parse_operand_type): Add
2032 CGEN_PARSE_OPERAND_SYMBOLIC.
2034 2005-01-21 Fred Fish <fnf@specifixinc.com>
2036 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2037 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2038 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2040 2005-01-19 Fred Fish <fnf@specifixinc.com>
2042 * mips.h (struct mips_opcode): Add new pinfo2 member.
2043 (INSN_ALIAS): New define for opcode table entries that are
2044 specific instances of another entry, such as 'move' for an 'or'
2045 with a zero operand.
2046 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2047 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2049 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2051 * mips.h (CPU_RM9000): Define.
2052 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2054 2004-11-25 Jan Beulich <jbeulich@novell.com>
2056 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2057 to/from test registers are illegal in 64-bit mode. Add missing
2058 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2059 (previously one had to explicitly encode a rex64 prefix). Re-enable
2060 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2061 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2063 2004-11-23 Jan Beulich <jbeulich@novell.com>
2065 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2066 available only with SSE2. Change the MMX additions introduced by SSE
2067 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2068 instructions by their now designated identifier (since combining i686
2069 and 3DNow! does not really imply 3DNow!A).
2071 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2073 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2074 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2076 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2077 Vineet Sharma <vineets@noida.hcltech.com>
2079 * maxq.h: New file: Disassembly information for the maxq port.
2081 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2083 * i386.h (i386_optab): Put back "movzb".
2085 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2087 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2088 comments. Remove member cris_ver_sim. Add members
2089 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2090 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2091 (struct cris_support_reg, struct cris_cond15): New types.
2092 (cris_conds15): Declare.
2093 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2094 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2095 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2096 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2097 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2098 SIZE_FIELD_UNSIGNED.
2100 2004-11-04 Jan Beulich <jbeulich@novell.com>
2102 * i386.h (sldx_Suf): Remove.
2103 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2104 (q_FP): Define, implying no REX64.
2105 (x_FP, sl_FP): Imply FloatMF.
2106 (i386_optab): Split reg and mem forms of moving from segment registers
2107 so that the memory forms can ignore the 16-/32-bit operand size
2108 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2109 all non-floating-point instructions. Unite 32- and 64-bit forms of
2110 movsx, movzx, and movd. Adjust floating point operations for the above
2111 changes to the *FP macros. Add DefaultSize to floating point control
2112 insns operating on larger memory ranges. Remove left over comments
2113 hinting at certain insns being Intel-syntax ones where the ones
2114 actually meant are already gone.
2116 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2118 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2121 2004-09-30 Paul Brook <paul@codesourcery.com>
2123 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2124 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2126 2004-09-11 Theodore A. Roth <troth@openavr.org>
2128 * avr.h: Add support for
2129 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2131 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2133 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2135 2004-08-24 Dmitry Diky <diwil@spec.ru>
2137 * msp430.h (msp430_opc): Add new instructions.
2138 (msp430_rcodes): Declare new instructions.
2139 (msp430_hcodes): Likewise..
2141 2004-08-13 Nick Clifton <nickc@redhat.com>
2144 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2147 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2149 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2151 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2153 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2155 2004-07-21 Jan Beulich <jbeulich@novell.com>
2157 * i386.h: Adjust instruction descriptions to better match the
2160 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2162 * arm.h: Remove all old content. Replace with architecture defines
2163 from gas/config/tc-arm.c.
2165 2004-07-09 Andreas Schwab <schwab@suse.de>
2167 * m68k.h: Fix comment.
2169 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2173 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2175 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2177 2004-05-24 Peter Barada <peter@the-baradas.com>
2179 * m68k.h: Add 'size' to m68k_opcode.
2181 2004-05-05 Peter Barada <peter@the-baradas.com>
2183 * m68k.h: Switch from ColdFire chip name to core variant.
2185 2004-04-22 Peter Barada <peter@the-baradas.com>
2187 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2188 descriptions for new EMAC cases.
2189 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2190 handle Motorola MAC syntax.
2191 Allow disassembly of ColdFire V4e object files.
2193 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2195 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2197 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2199 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2201 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2203 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2205 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2207 * i386.h (i386_optab): Added xstore/xcrypt insns.
2209 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2211 * h8300.h (32bit ldc/stc): Add relaxing support.
2213 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2215 * h8300.h (BITOP): Pass MEMRELAX flag.
2217 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2219 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2222 For older changes see ChangeLog-9103
2224 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2226 Copying and distribution of this file, with or without modification,
2227 are permitted in any medium without royalty provided the copyright
2228 notice and this notice are preserved.
2234 version-control: never
projects / external / binutils.git / blob