1 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
5 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
7 * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
8 (aarch64_sys_ins_reg_has_xt): Declare.
10 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
12 * aarch64.h (AARCH64_FEATURE_RAS): New.
13 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
15 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
17 * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
19 (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
20 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
23 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
25 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
27 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
29 * aarch64.h (aarch64_op): Add OP_BFC.
31 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
33 * aarch64.h (AARCH64_FEATURE_F16): New.
34 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
37 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
39 * aarch64.h (AARCH64_FEATURE_V8_1): New.
40 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
42 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
44 * arm.h (ARM_EXT2_V8_2A): New.
45 (ARM_ARCH_V8_2A): New.
47 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
49 * aarch64.h (AARCH64_FEATURE_V8_2): New.
50 (AARCH64_ARCH_V8_2): New.
52 2015-11-11 Alan Modra <amodra@gmail.com>
53 Peter Bergner <bergner@vnet.ibm.com>
55 * ppc.h (PPC_OPCODE_POWER9): New define.
56 (PPC_OPCODE_VSX3): Likewise.
58 2015-11-02 Nick Clifton <nickc@redhat.com>
60 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
62 2015-11-02 Nick Clifton <nickc@redhat.com>
64 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
66 2015-10-28 Yao Qi <yao.qi@linaro.org>
68 * aarch64.h (aarch64_decode_insn): Update declaration.
70 2015-10-07 Yao Qi <yao.qi@linaro.org>
72 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
75 2015-10-07 Yao Qi <yao.qi@linaro.org>
77 * aarch64.h [__cplusplus]: Wrap in extern "C".
79 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
80 Cupertino Miranda <cmiranda@synopsys.com>
82 * arc-func.h: New file.
85 2015-10-02 Yao Qi <yao.qi@linaro.org>
87 * aarch64.h (aarch64_zero_register_p): Move the declaration
90 2015-10-02 Yao Qi <yao.qi@linaro.org>
92 * aarch64.h (aarch64_decode_insn): Declare it.
94 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
96 * s390.h (S390_INSTR_FLAG_HTM): New flag.
97 (S390_INSTR_FLAG_VX): New flag.
98 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
100 2015-09-23 Nick Clifton <nickc@redhat.com>
102 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
105 2015-09-22 Nick Clifton <nickc@redhat.com>
107 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
109 2015-09-09 Daniel Santos <daniel.santos@pobox.com>
111 * visium.h (gen_reg_table): Make static.
112 (fp_reg_table): Likewise.
113 (cc_table): Likewise.
115 2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
117 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
118 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
119 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
120 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
122 2015-07-03 Alan Modra <amodra@gmail.com>
124 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
126 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
127 Cesar Philippidis <cesar@codesourcery.com>
129 * nios2.h (enum iw_format_type): Add R2 formats.
130 (enum overflow_type): Add signed_immed12_overflow and
131 enumeration_overflow for R2.
132 (struct nios2_opcode): Document new argument letters for R2.
133 (REG_3BIT, REG_LDWM, REG_POP): Define.
134 (includes): Include nios2r2.h.
135 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
136 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
137 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
138 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
139 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
140 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
142 * nios2r2.h: New file.
144 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
146 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
147 (ppc_optional_operand_value): New inline function.
149 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
151 * aarch64.h (AARCH64_V8_1): New.
153 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
155 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
156 (ARM_ARCH_V8_1A): New.
157 (ARM_ARCH_V8_1A_FP): New.
158 (ARM_ARCH_V8_1A_SIMD): New.
159 (ARM_ARCH_V8_1A_CRYPTOV1): New.
160 (ARM_FEATURE_CORE): New.
162 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
164 * arm.h (ARM_EXT2_PAN): New.
165 (ARM_FEATURE_CORE_HIGH): New.
167 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
169 * arm.h (ARM_FEATURE_ALL): New.
171 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
173 * aarch64.h (AARCH64_FEATURE_RDMA): New.
175 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
177 * aarch64.h (AARCH64_FEATURE_LOR): New.
179 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
181 * aarch64.h (AARCH64_FEATURE_PAN): New.
182 (aarch64_sys_reg_supported_p): Declare.
183 (aarch64_pstatefield_supported_p): Declare.
185 2015-04-30 DJ Delorie <dj@redhat.com>
187 * rl78.h (RL78_Dis_Isa): New.
188 (rl78_decode_opcode): Add ISA parameter.
190 2015-03-24 Terry Guo <terry.guo@arm.com>
192 * arm.h (arm_feature_set): Extended to provide more available bits.
193 (ARM_ANY): Updated to follow above new definition.
194 (ARM_CPU_HAS_FEATURE): Likewise.
195 (ARM_CPU_IS_ANY): Likewise.
196 (ARM_MERGE_FEATURE_SETS): Likewise.
197 (ARM_CLEAR_FEATURE): Likewise.
198 (ARM_FEATURE): Likewise.
199 (ARM_FEATURE_COPY): New macro.
200 (ARM_FEATURE_EQUAL): Likewise.
201 (ARM_FEATURE_ZERO): Likewise.
202 (ARM_FEATURE_CORE_EQUAL): Likewise.
203 (ARM_FEATURE_LOW): Likewise.
204 (ARM_FEATURE_CORE_LOW): Likewise.
205 (ARM_FEATURE_CORE_COPROC): Likewise.
207 2015-02-19 Pedro Alves <palves@redhat.com>
209 * cgen.h [__cplusplus]: Wrap in extern "C".
210 * msp430-decode.h [__cplusplus]: Likewise.
211 * nios2.h [__cplusplus]: Likewise.
212 * rl78.h [__cplusplus]: Likewise.
213 * rx.h [__cplusplus]: Likewise.
214 * tilegx.h [__cplusplus]: Likewise.
216 2015-01-28 James Bowman <james.bowman@ftdichip.com>
220 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
222 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
224 2015-01-01 Alan Modra <amodra@gmail.com>
226 Update year range in copyright notice of all files.
228 2014-12-27 Anthony Green <green@moxielogic.com>
230 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
231 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
233 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
235 * visium.h: New file.
237 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
239 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
240 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
241 (NIOS2_INSN_OPTARG): Renumber.
243 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
245 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
246 declaration. Fix obsolete comment.
248 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
250 * nios2.h (enum iw_format_type): New.
251 (struct nios2_opcode): Update comments. Add size and format fields.
252 (NIOS2_INSN_OPTARG): New.
253 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
254 (struct nios2_reg): Add regtype field.
255 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
256 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
257 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
258 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
259 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
260 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
261 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
262 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
263 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
264 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
265 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
266 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
267 (OP_MASK_OP, OP_SH_OP): Delete.
268 (OP_MASK_IOP, OP_SH_IOP): Delete.
269 (OP_MASK_IRD, OP_SH_IRD): Delete.
270 (OP_MASK_IRT, OP_SH_IRT): Delete.
271 (OP_MASK_IRS, OP_SH_IRS): Delete.
272 (OP_MASK_ROP, OP_SH_ROP): Delete.
273 (OP_MASK_RRD, OP_SH_RRD): Delete.
274 (OP_MASK_RRT, OP_SH_RRT): Delete.
275 (OP_MASK_RRS, OP_SH_RRS): Delete.
276 (OP_MASK_JOP, OP_SH_JOP): Delete.
277 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
278 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
279 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
280 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
281 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
282 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
283 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
284 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
285 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
286 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
287 (OP_MASK_<insn>, OP_MASK): Delete.
288 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
289 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
290 Include nios2r1.h to define new instruction opcode constants
292 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
293 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
294 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
295 (NUMOPCODES, NUMREGISTERS): Delete.
296 * nios2r1.h: New file.
298 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
300 * sparc.h (HWCAP2_VIS3B): Documentation improved.
302 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
304 * sparc.h (sparc_opcode): new field `hwcaps2'.
305 (HWCAP2_FJATHPLUS): New define.
306 (HWCAP2_VIS3B): Likewise.
307 (HWCAP2_ADP): Likewise.
308 (HWCAP2_SPARC5): Likewise.
309 (HWCAP2_MWAIT): Likewise.
310 (HWCAP2_XMPMUL): Likewise.
311 (HWCAP2_XMONT): Likewise.
312 (HWCAP2_NSEC): Likewise.
313 (HWCAP2_FJATHHPC): Likewise.
314 (HWCAP2_FJDES): Likewise.
315 (HWCAP2_FJAES): Likewise.
316 Document the new operand kind `{', corresponding to the mcdper
317 ancillary state register.
318 Document the new operand kind }, which represents frsd floating
319 point registers (double precision) which must be the same than
320 frs1 in its containing instruction.
322 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
324 * nds32.h: Add new opcode declaration.
326 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
327 Matthew Fortune <matthew.fortune@imgtec.com>
329 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
330 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
331 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
332 +I, +O, +R, +:, +\, +", +;
333 (mips_check_prev_operand): New struct.
334 (INSN2_FORBIDDEN_SLOT): New define.
335 (INSN_ISA32R6): New define.
336 (INSN_ISA64R6): New define.
337 (INSN_UPTO32R6): New define.
338 (INSN_UPTO64R6): New define.
339 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
340 (ISA_MIPS32R6): New define.
341 (ISA_MIPS64R6): New define.
342 (CPU_MIPS32R6): New define.
343 (CPU_MIPS64R6): New define.
344 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
346 2014-09-03 Jiong Wang <jiong.wang@arm.com>
348 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
349 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
350 (aarch64_insn_class): Add lse_atomic.
351 (F_LSE_SZ): New field added.
352 (opcode_has_special_coder): Recognize F_LSE_SZ.
354 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
356 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
359 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
361 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
362 (INSN_LOAD_COPROC): New define.
363 (INSN_COPROC_MOVE_DELAY): Rename to...
364 (INSN_COPROC_MOVE): New define.
366 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
367 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
368 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
369 Soundararajan <Sounderarajan.D@atmel.com>
371 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
372 (AVR_ISA_2xxxa): Define ISA without LPM.
373 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
374 Add doc for contraint used in 16 bit lds/sts.
375 Adjust ISA group for icall, ijmp, pop and push.
376 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
378 2014-05-19 Nick Clifton <nickc@redhat.com>
380 * msp430.h (struct msp430_operand_s): Add vshift field.
382 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
384 * mips.h (INSN_ISA_MASK): Updated.
385 (INSN_ISA32R3): New define.
386 (INSN_ISA32R5): New define.
387 (INSN_ISA64R3): New define.
388 (INSN_ISA64R5): New define.
389 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
390 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
391 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
393 (INSN_UPTO32R3): New define.
394 (INSN_UPTO32R5): New define.
395 (INSN_UPTO64R3): New define.
396 (INSN_UPTO64R5): New define.
397 (ISA_MIPS32R3): New define.
398 (ISA_MIPS32R5): New define.
399 (ISA_MIPS64R3): New define.
400 (ISA_MIPS64R5): New define.
401 (CPU_MIPS32R3): New define.
402 (CPU_MIPS32R5): New define.
403 (CPU_MIPS64R3): New define.
404 (CPU_MIPS64R5): New define.
406 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
408 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
410 2014-04-22 Christian Svensson <blue@cmd.nu>
414 2014-03-05 Alan Modra <amodra@gmail.com>
416 Update copyright years.
418 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
420 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
423 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
424 Wei-Cheng Wang <cole945@gmail.com>
426 * nds32.h: New file for Andes NDS32.
428 2013-12-07 Mike Frysinger <vapier@gentoo.org>
430 * bfin.h: Remove +x file mode.
432 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
434 * aarch64.h (aarch64_pstatefields): Change element type to
437 2013-11-18 Renlin Li <Renlin.Li@arm.com>
439 * arm.h (ARM_AEXT_V7VE): New define.
440 (ARM_ARCH_V7VE): New define.
441 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
443 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
447 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
449 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
450 (aarch64_sys_reg_writeonly_p): Ditto.
452 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
454 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
455 (aarch64_sys_reg_writeonly_p): Ditto.
457 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
459 * aarch64.h (aarch64_sys_reg): New typedef.
460 (aarch64_sys_regs): Change to define with the new type.
461 (aarch64_sys_reg_deprecated_p): Declare.
463 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
465 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
466 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
468 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
470 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
471 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
472 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
473 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
474 For MIPS, update extension character sequences after +.
475 (ASE_MSA): New define.
476 (ASE_MSA64): New define.
477 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
478 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
479 For microMIPS, update extension character sequences after +.
481 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
486 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
488 * mips.h: Remove references to "+I" and imm2_expr.
490 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
492 * mips.h (M_DEXT, M_DINS): Delete.
494 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
496 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
497 (mips_optional_operand_p): New function.
499 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
500 Richard Sandiford <rdsandiford@googlemail.com>
502 * mips.h: Document new VU0 operand characters.
503 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
504 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
505 (OP_REG_R5900_ACC): New mips_reg_operand_types.
506 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
507 (mips_vu0_channel_mask): Declare.
509 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
511 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
512 (mips_int_operand_min, mips_int_operand_max): New functions.
513 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
515 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
517 * mips.h (mips_decode_reg_operand): New function.
518 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
519 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
520 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
522 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
523 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
524 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
525 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
526 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
527 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
528 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
529 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
530 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
531 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
532 macros to cover the gaps.
533 (INSN2_MOD_SP): Replace with...
534 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
535 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
536 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
537 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
538 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
541 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
543 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
544 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
545 (MIPS16_INSN_COND_BRANCH): Delete.
547 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
548 Kirill Yukhin <kirill.yukhin@intel.com>
549 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
551 * i386.h (BND_PREFIX_OPCODE): New.
553 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
555 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
556 OP_SAVE_RESTORE_LIST.
557 (decode_mips16_operand): Declare.
559 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
561 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
562 (mips_operand, mips_int_operand, mips_mapped_int_operand)
563 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
564 (mips_pcrel_operand): New structures.
565 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
566 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
567 (decode_mips_operand, decode_micromips_operand): Declare.
569 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
571 * mips.h: Document MIPS16 "I" opcode.
573 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
575 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
576 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
577 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
578 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
579 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
580 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
581 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
582 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
583 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
584 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
585 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
586 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
587 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
589 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
590 (M_USD_AB): ...these.
592 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
594 * mips.h: Remove documentation of "[" and "]". Update documentation
595 of "k" and the MDMX formats.
597 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
599 * mips.h: Update documentation of "+s" and "+S".
601 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
603 * mips.h: Document "+i".
605 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
607 * mips.h: Remove "mi" documentation. Update "mh" documentation.
608 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
610 (INSN2_WRITE_GPR_MHI): Rename to...
611 (INSN2_WRITE_GPR_MH): ...this.
613 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
615 * mips.h: Remove documentation of "+D" and "+T".
617 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
619 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
620 Use "source" rather than "destination" for microMIPS "G".
622 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
624 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
627 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
629 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
631 2013-06-17 Catherine Moore <clm@codesourcery.com>
632 Maciej W. Rozycki <macro@codesourcery.com>
633 Chao-Ying Fu <fu@mips.com>
635 * mips.h (OP_SH_EVAOFFSET): Define.
636 (OP_MASK_EVAOFFSET): Define.
637 (INSN_ASE_MASK): Delete.
639 (M_CACHEE_AB, M_CACHEE_OB): New.
640 (M_LBE_OB, M_LBE_AB): New.
641 (M_LBUE_OB, M_LBUE_AB): New.
642 (M_LHE_OB, M_LHE_AB): New.
643 (M_LHUE_OB, M_LHUE_AB): New.
644 (M_LLE_AB, M_LLE_OB): New.
645 (M_LWE_OB, M_LWE_AB): New.
646 (M_LWLE_AB, M_LWLE_OB): New.
647 (M_LWRE_AB, M_LWRE_OB): New.
648 (M_PREFE_AB, M_PREFE_OB): New.
649 (M_SCE_AB, M_SCE_OB): New.
650 (M_SBE_OB, M_SBE_AB): New.
651 (M_SHE_OB, M_SHE_AB): New.
652 (M_SWE_OB, M_SWE_AB): New.
653 (M_SWLE_AB, M_SWLE_OB): New.
654 (M_SWRE_AB, M_SWRE_OB): New.
655 (MICROMIPSOP_SH_EVAOFFSET): Define.
656 (MICROMIPSOP_MASK_EVAOFFSET): Define.
658 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
660 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
662 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
664 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
666 2013-05-09 Andrew Pinski <apinski@cavium.com>
668 * mips.h (OP_MASK_CODE10): Correct definition.
669 (OP_SH_CODE10): Likewise.
670 Add a comment that "+J" is used now for OP_*CODE10.
671 (INSN_ASE_MASK): Update.
672 (INSN_VIRT): New macro.
673 (INSN_VIRT64): New macro
675 2013-05-02 Nick Clifton <nickc@redhat.com>
677 * msp430.h: Add patterns for MSP430X instructions.
679 2013-04-06 David S. Miller <davem@davemloft.net>
681 * sparc.h (F_PREFERRED): Define.
682 (F_PREF_ALIAS): Define.
684 2013-04-03 Nick Clifton <nickc@redhat.com>
686 * v850.h (V850_INVERSE_PCREL): Define.
688 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
691 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
693 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
696 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
698 * tic6xc-opcode-table.h: Add 16-bit insns.
699 * tic6x.h: Add support for 16-bit insns.
701 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
703 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
704 and mov.b/w/l Rs,@(d:32,ERd).
706 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
709 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
710 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
711 tic6x_operand_xregpair operand coding type.
712 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
713 opcode field, usu ORXREGD1324 for the src2 operand and remove the
716 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
719 * tic6x.h (enum tic6x_coding_method): Add
720 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
721 separately the msb and lsb of a register pair. This is needed to
722 encode the opcodes in the same way as TI assembler does.
723 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
724 and rsqrdp opcodes to use the new field coding types.
726 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
728 * arm.h (CRC_EXT_ARMV8): New constant.
729 (ARCH_CRC_ARMV8): New macro.
731 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
733 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
735 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
736 Andrew Jenner <andrew@codesourcery.com>
738 Based on patches from Altera Corporation.
742 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
744 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
746 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
749 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
751 2013-01-24 Nick Clifton <nickc@redhat.com>
753 * v850.h: Add e3v5 support.
755 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
757 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
759 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
761 * ppc.h (PPC_OPCODE_POWER8): New define.
762 (PPC_OPCODE_HTM): Likewise.
764 2013-01-10 Will Newton <will.newton@imgtec.com>
768 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
770 * cr16.h (make_instruction): Rename to cr16_make_instruction.
771 (match_opcode): Rename to cr16_match_opcode.
773 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
775 * mips.h: Add support for r5900 instructions including lq and sq.
777 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
779 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
780 (make_instruction,match_opcode): Added function prototypes.
781 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
783 2012-11-23 Alan Modra <amodra@gmail.com>
785 * ppc.h (ppc_parse_cpu): Update prototype.
787 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
789 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
790 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
792 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
794 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
796 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
798 * ia64.h (ia64_opnd): Add new operand types.
800 2012-08-21 David S. Miller <davem@davemloft.net>
802 * sparc.h (F3F4): New macro.
804 2012-08-13 Ian Bolton <ian.bolton@arm.com>
805 Laurent Desnogues <laurent.desnogues@arm.com>
806 Jim MacArthur <jim.macarthur@arm.com>
807 Marcus Shawcroft <marcus.shawcroft@arm.com>
808 Nigel Stephens <nigel.stephens@arm.com>
809 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
810 Richard Earnshaw <rearnsha@arm.com>
811 Sofiane Naci <sofiane.naci@arm.com>
812 Tejas Belagod <tejas.belagod@arm.com>
813 Yufeng Zhang <yufeng.zhang@arm.com>
815 * aarch64.h: New file.
817 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
818 Maciej W. Rozycki <macro@codesourcery.com>
820 * mips.h (mips_opcode): Add the exclusions field.
821 (OPCODE_IS_MEMBER): Remove macro.
822 (cpu_is_member): New inline function.
823 (opcode_is_member): Likewise.
825 2012-07-31 Chao-Ying Fu <fu@mips.com>
826 Catherine Moore <clm@codesourcery.com>
827 Maciej W. Rozycki <macro@codesourcery.com>
829 * mips.h: Document microMIPS DSP ASE usage.
830 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
831 microMIPS DSP ASE support.
832 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
833 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
834 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
835 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
836 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
837 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
838 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
840 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
842 * mips.h: Fix a typo in description.
844 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
846 * avr.h: (AVR_ISA_XCH): New define.
847 (AVR_ISA_XMEGA): Use it.
848 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
850 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
852 * m68hc11.h: Add XGate definitions.
853 (struct m68hc11_opcode): Add xg_mask field.
855 2012-05-14 Catherine Moore <clm@codesourcery.com>
856 Maciej W. Rozycki <macro@codesourcery.com>
857 Rhonda Wittels <rhonda@codesourcery.com>
859 * ppc.h (PPC_OPCODE_VLE): New definition.
860 (PPC_OP_SA): New macro.
861 (PPC_OP_SE_VLE): New macro.
862 (PPC_OP): Use a variable shift amount.
863 (powerpc_operand): Update comments.
864 (PPC_OPSHIFT_INV): New macro.
865 (PPC_OPERAND_CR): Replace with...
866 (PPC_OPERAND_CR_BIT): ...this and
867 (PPC_OPERAND_CR_REG): ...this.
870 2012-05-03 Sean Keys <skeys@ipdatasys.com>
872 * xgate.h: Header file for XGATE assembler.
874 2012-04-27 David S. Miller <davem@davemloft.net>
876 * sparc.h: Document new arg code' )' for crypto RS3
879 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
880 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
881 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
882 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
883 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
884 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
885 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
886 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
887 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
888 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
889 HWCAP_CBCOND, HWCAP_CRC32): New defines.
891 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
893 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
895 2012-02-27 Alan Modra <amodra@gmail.com>
897 * crx.h (cst4_map): Update declaration.
899 2012-02-25 Walter Lee <walt@tilera.com>
901 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
903 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
904 TILEPRO_OPC_LW_TLS_SN.
906 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
908 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
909 (XRELEASE_PREFIX_OPCODE): Likewise.
911 2011-12-08 Andrew Pinski <apinski@cavium.com>
912 Adam Nemet <anemet@caviumnetworks.com>
914 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
915 (INSN_OCTEON2): New macro.
916 (CPU_OCTEON2): New macro.
917 (OPCODE_IS_MEMBER): Add Octeon2.
919 2011-11-29 Andrew Pinski <apinski@cavium.com>
921 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
922 (INSN_OCTEONP): New macro.
923 (CPU_OCTEONP): New macro.
924 (OPCODE_IS_MEMBER): Add Octeon+.
925 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
927 2011-11-01 DJ Delorie <dj@redhat.com>
931 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
933 * mips.h: Fix a typo in description.
935 2011-09-21 David S. Miller <davem@davemloft.net>
937 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
938 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
939 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
940 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
942 2011-08-09 Chao-ying Fu <fu@mips.com>
943 Maciej W. Rozycki <macro@codesourcery.com>
945 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
946 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
947 (INSN_ASE_MASK): Add the MCU bit.
948 (INSN_MCU): New macro.
949 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
950 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
952 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
954 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
955 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
956 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
957 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
958 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
959 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
960 (INSN2_READ_GPR_MMN): Likewise.
961 (INSN2_READ_FPR_D): Change the bit used.
962 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
963 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
964 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
965 (INSN2_COND_BRANCH): Likewise.
966 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
967 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
968 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
969 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
970 (INSN2_MOD_GPR_MN): Likewise.
972 2011-08-05 David S. Miller <davem@davemloft.net>
974 * sparc.h: Document new format codes '4', '5', and '('.
975 (OPF_LOW4, RS3): New macros.
977 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
979 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
980 order of flags documented.
982 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
984 * mips.h: Clarify the description of microMIPS instruction
986 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
988 2011-07-24 Chao-ying Fu <fu@mips.com>
989 Maciej W. Rozycki <macro@codesourcery.com>
991 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
992 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
993 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
994 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
995 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
996 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
997 (OP_MASK_RS3, OP_SH_RS3): Likewise.
998 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
999 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
1000 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
1001 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
1002 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
1003 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
1004 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
1005 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
1006 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
1007 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
1008 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
1009 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
1010 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
1011 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
1012 (INSN_WRITE_GPR_S): New macro.
1013 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
1014 (INSN2_READ_FPR_D): Likewise.
1015 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
1016 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
1017 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
1018 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
1019 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
1020 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
1021 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1022 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1023 (CPU_MICROMIPS): New macro.
1024 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1025 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1026 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1027 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1028 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1029 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1030 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1031 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1032 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1033 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1034 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1035 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1036 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1037 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1038 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1039 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1040 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1041 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1042 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1043 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1044 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1045 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1046 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1047 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1048 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1049 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1050 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1051 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1052 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1053 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1054 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1055 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1056 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1057 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1058 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1059 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1060 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1061 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1062 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1063 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1064 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1065 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1066 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1067 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1068 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1069 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1070 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1071 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1072 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1073 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1074 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1075 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1076 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1077 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1078 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1079 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1080 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1081 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1082 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1083 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1084 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1085 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1086 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1087 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1088 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1089 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1090 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1091 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1092 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1093 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1094 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1095 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1096 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1097 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1098 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1099 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1100 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1101 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1102 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1103 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1104 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1105 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1106 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1107 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1108 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1109 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1110 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1111 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1112 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1113 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1114 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1115 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1116 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1117 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1118 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1119 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1120 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1121 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1122 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1123 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1124 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1125 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1126 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1127 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1128 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1129 (micromips_opcodes): New declaration.
1130 (bfd_micromips_num_opcodes): Likewise.
1132 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1134 * mips.h (INSN_TRAP): Rename to...
1135 (INSN_NO_DELAY_SLOT): ... this.
1136 (INSN_SYNC): Remove macro.
1138 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1140 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1141 a duplicate of AVR_ISA_SPM.
1143 2011-07-01 Nick Clifton <nickc@redhat.com>
1145 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1147 2011-06-18 Robin Getz <robin.getz@analog.com>
1149 * bfin.h (is_macmod_signed): New func
1151 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1153 * bfin.h (is_macmod_pmove): Add missing space before func args.
1154 (is_macmod_hmove): Likewise.
1156 2011-06-13 Walter Lee <walt@tilera.com>
1158 * tilegx.h: New file.
1159 * tilepro.h: New file.
1161 2011-05-31 Paul Brook <paul@codesourcery.com>
1163 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1165 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1167 * s390.h: Replace S390_OPERAND_REG_EVEN with
1168 S390_OPERAND_REG_PAIR.
1170 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1172 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1174 2011-04-18 Julian Brown <julian@codesourcery.com>
1176 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1178 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1181 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1183 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1185 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1186 New instruction set flags.
1187 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1189 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1191 * mips.h (M_PREF_AB): New enum value.
1193 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1195 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1197 (is_macmod_pmove, is_macmod_hmove): New functions.
1199 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1201 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1203 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1205 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1206 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1208 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1211 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1214 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1217 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1219 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1221 * mips.h: Update commentary after last commit.
1223 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1225 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1226 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1227 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1229 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1231 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1233 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1235 * mips.h: Fix previous commit.
1237 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1239 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1240 (INSN_LOONGSON_3A): Clear bit 31.
1242 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1245 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1246 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1247 (ARM_ARCH_V6M_ONLY): New define.
1249 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1251 * mips.h (INSN_LOONGSON_3A): Defined.
1252 (CPU_LOONGSON_3A): Defined.
1253 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1255 2010-10-09 Matt Rice <ratmice@gmail.com>
1257 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1258 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1260 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1262 * arm.h (ARM_EXT_VIRT): New define.
1263 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1264 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1267 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1269 * arm.h (ARM_AEXT_ADIV): New define.
1270 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1272 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1274 * arm.h (ARM_EXT_OS): New define.
1275 (ARM_AEXT_V6SM): Likewise.
1276 (ARM_ARCH_V6SM): Likewise.
1278 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1280 * arm.h (ARM_EXT_MP): Add.
1281 (ARM_ARCH_V7A_MP): Likewise.
1283 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1285 * bfin.h: Declare pseudoChr structs/defines.
1287 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1289 * bfin.h: Strip trailing whitespace.
1291 2010-07-29 DJ Delorie <dj@redhat.com>
1293 * rx.h (RX_Operand_Type): Add TwoReg.
1294 (RX_Opcode_ID): Remove ediv and ediv2.
1296 2010-07-27 DJ Delorie <dj@redhat.com>
1298 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1300 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1301 Ina Pandit <ina.pandit@kpitcummins.com>
1303 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1304 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1305 PROCESSOR_V850E2_ALL.
1306 Remove PROCESSOR_V850EA support.
1307 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1308 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1309 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1310 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1311 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1312 V850_OPERAND_PERCENT.
1313 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1315 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1318 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1320 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1321 (MIPS16_INSN_BRANCH): Rename to...
1322 (MIPS16_INSN_COND_BRANCH): ... this.
1324 2010-07-03 Alan Modra <amodra@gmail.com>
1326 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1327 Renumber other PPC_OPCODE defines.
1329 2010-07-03 Alan Modra <amodra@gmail.com>
1331 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1333 2010-06-29 Alan Modra <amodra@gmail.com>
1335 * maxq.h: Delete file.
1337 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1339 * ppc.h (PPC_OPCODE_E500): Define.
1341 2010-05-26 Catherine Moore <clm@codesourcery.com>
1343 * opcode/mips.h (INSN_MIPS16): Remove.
1345 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1347 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1349 2010-04-15 Nick Clifton <nickc@redhat.com>
1351 * alpha.h: Update copyright notice to use GPLv3.
1357 * convex.h: Likewise.
1364 * h8300.h: Likewise.
1371 * m68hc11.h: Likewise.
1377 * mn10200.h: Likewise.
1378 * mn10300.h: Likewise.
1379 * msp430.h: Likewise.
1381 * ns32k.h: Likewise.
1383 * pdp11.h: Likewise.
1390 * score-datadep.h: Likewise.
1391 * score-inst.h: Likewise.
1392 * sparc.h: Likewise.
1393 * spu-insns.h: Likewise.
1395 * tic30.h: Likewise.
1396 * tic4x.h: Likewise.
1397 * tic54x.h: Likewise.
1398 * tic80.h: Likewise.
1402 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1404 * tic6x-control-registers.h, tic6x-insn-formats.h,
1405 tic6x-opcode-table.h, tic6x.h: New.
1407 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1409 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1411 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1413 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1415 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1417 * ia64.h (ia64_find_opcode): Remove argument name.
1418 (ia64_find_next_opcode): Likewise.
1419 (ia64_dis_opcode): Likewise.
1420 (ia64_free_opcode): Likewise.
1421 (ia64_find_dependency): Likewise.
1423 2009-11-22 Doug Evans <dje@sebabeach.org>
1425 * cgen.h: Include bfd_stdint.h.
1426 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1428 2009-11-18 Paul Brook <paul@codesourcery.com>
1430 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1432 2009-11-17 Paul Brook <paul@codesourcery.com>
1433 Daniel Jacobowitz <dan@codesourcery.com>
1435 * arm.h (ARM_EXT_V6_DSP): Define.
1436 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1437 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1439 2009-11-04 DJ Delorie <dj@redhat.com>
1441 * rx.h (rx_decode_opcode) (mvtipl): Add.
1442 (mvtcp, mvfcp, opecp): Remove.
1444 2009-11-02 Paul Brook <paul@codesourcery.com>
1446 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1447 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1448 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1449 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1450 FPU_ARCH_NEON_VFP_V4): Define.
1452 2009-10-23 Doug Evans <dje@sebabeach.org>
1454 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1455 * cgen.h: Update. Improve multi-inclusion macro name.
1457 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1459 * ppc.h (PPC_OPCODE_476): Define.
1461 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1463 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1465 2009-09-29 DJ Delorie <dj@redhat.com>
1469 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1471 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1473 2009-09-21 Ben Elliston <bje@au.ibm.com>
1475 * ppc.h (PPC_OPCODE_PPCA2): New.
1477 2009-09-05 Martin Thuresson <martin@mtme.org>
1479 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1481 2009-08-29 Martin Thuresson <martin@mtme.org>
1483 * tic30.h (template): Rename type template to
1484 insn_template. Updated code to use new name.
1485 * tic54x.h (template): Rename type template to
1488 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1490 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1492 2009-06-11 Anthony Green <green@moxielogic.com>
1494 * moxie.h (MOXIE_F3_PCREL): Define.
1495 (moxie_form3_opc_info): Grow.
1497 2009-06-06 Anthony Green <green@moxielogic.com>
1499 * moxie.h (MOXIE_F1_M): Define.
1501 2009-04-15 Anthony Green <green@moxielogic.com>
1505 2009-04-06 DJ Delorie <dj@redhat.com>
1507 * h8300.h: Add relaxation attributes to MOVA opcodes.
1509 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1511 * ppc.h (ppc_parse_cpu): Declare.
1513 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1515 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1516 and _IMM11 for mbitclr and mbitset.
1517 * score-datadep.h: Update dependency information.
1519 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1521 * ppc.h (PPC_OPCODE_POWER7): New.
1523 2009-02-06 Doug Evans <dje@google.com>
1525 * i386.h: Add comment regarding sse* insns and prefixes.
1527 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1529 * mips.h (INSN_XLR): Define.
1530 (INSN_CHIP_MASK): Update.
1532 (OPCODE_IS_MEMBER): Update.
1533 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1535 2009-01-28 Doug Evans <dje@google.com>
1537 * opcode/i386.h: Add multiple inclusion protection.
1538 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1539 (EDI_REG_NUM): New macros.
1540 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1541 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1542 (REX_PREFIX_P): New macro.
1544 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1546 * ppc.h (struct powerpc_opcode): New field "deprecated".
1547 (PPC_OPCODE_NOPOWER4): Delete.
1549 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1551 * mips.h: Define CPU_R14000, CPU_R16000.
1552 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1554 2008-11-18 Catherine Moore <clm@codesourcery.com>
1556 * arm.h (FPU_NEON_FP16): New.
1557 (FPU_ARCH_NEON_FP16): New.
1559 2008-11-06 Chao-ying Fu <fu@mips.com>
1561 * mips.h: Doucument '1' for 5-bit sync type.
1563 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1565 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1568 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1570 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1572 2008-07-30 Michael J. Eager <eager@eagercon.com>
1574 * ppc.h (PPC_OPCODE_405): Define.
1575 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1577 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1579 * ppc.h (ppc_cpu_t): New typedef.
1580 (struct powerpc_opcode <flags>): Use it.
1581 (struct powerpc_operand <insert, extract>): Likewise.
1582 (struct powerpc_macro <flags>): Likewise.
1584 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1586 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1587 Update comment before MIPS16 field descriptors to mention MIPS16.
1588 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1590 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1591 New bit masks and shift counts for cins and exts.
1593 * mips.h: Document new field descriptors +Q.
1594 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1596 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1598 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1599 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1601 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1603 * ppc.h: (PPC_OPCODE_E500MC): New.
1605 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1607 * i386.h (MAX_OPERANDS): Set to 5.
1608 (MAX_MNEM_SIZE): Changed to 20.
1610 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1612 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1614 2008-03-09 Paul Brook <paul@codesourcery.com>
1616 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1618 2008-03-04 Paul Brook <paul@codesourcery.com>
1620 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1621 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1622 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1624 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1625 Nick Clifton <nickc@redhat.com>
1628 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1629 with a 32-bit displacement but without the top bit of the 4th byte
1632 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1634 * cr16.h (cr16_num_optab): Declared.
1636 2008-02-14 Hakan Ardo <hakan@debian.org>
1639 * avr.h (AVR_ISA_2xxe): Define.
1641 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1643 * mips.h: Update copyright.
1644 (INSN_CHIP_MASK): New macro.
1645 (INSN_OCTEON): New macro.
1646 (CPU_OCTEON): New macro.
1647 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1649 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1651 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1653 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1655 * avr.h (AVR_ISA_USB162): Add new opcode set.
1656 (AVR_ISA_AVR3): Likewise.
1658 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1660 * mips.h (INSN_LOONGSON_2E): New.
1661 (INSN_LOONGSON_2F): New.
1662 (CPU_LOONGSON_2E): New.
1663 (CPU_LOONGSON_2F): New.
1664 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1666 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1668 * mips.h (INSN_ISA*): Redefine certain values as an
1669 enumeration. Update comments.
1670 (mips_isa_table): New.
1671 (ISA_MIPS*): Redefine to match enumeration.
1672 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1675 2007-08-08 Ben Elliston <bje@au.ibm.com>
1677 * ppc.h (PPC_OPCODE_PPCPS): New.
1679 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1681 * m68k.h: Document j K & E.
1683 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1685 * cr16.h: New file for CR16 target.
1687 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1689 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1691 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1693 * m68k.h (mcfisa_c): New.
1694 (mcfusp, mcf_mask): Adjust.
1696 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1698 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1699 (num_powerpc_operands): Declare.
1700 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1701 (PPC_OPERAND_PLUS1): Define.
1703 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1705 * i386.h (REX_MODE64): Renamed to ...
1707 (REX_EXTX): Renamed to ...
1709 (REX_EXTY): Renamed to ...
1711 (REX_EXTZ): Renamed to ...
1714 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1716 * i386.h: Add entries from config/tc-i386.h and move tables
1717 to opcodes/i386-opc.h.
1719 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1721 * i386.h (FloatDR): Removed.
1722 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1724 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1726 * spu-insns.h: Add soma double-float insns.
1728 2007-02-20 Thiemo Seufer <ths@mips.com>
1729 Chao-Ying Fu <fu@mips.com>
1731 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1732 (INSN_DSPR2): Add flag for DSP R2 instructions.
1733 (M_BALIGN): New macro.
1735 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1737 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1738 and Seg3ShortFrom with Shortform.
1740 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1743 * i386.h (i386_optab): Put the real "test" before the pseudo
1746 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1748 * m68k.h (m68010up): OR fido_a.
1750 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1752 * m68k.h (fido_a): New.
1754 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1756 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1757 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1760 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1762 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1764 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1766 * score-inst.h (enum score_insn_type): Add Insn_internal.
1768 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1769 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1770 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1771 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1772 Alan Modra <amodra@bigpond.net.au>
1774 * spu-insns.h: New file.
1777 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1779 * ppc.h (PPC_OPCODE_CELL): Define.
1781 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1783 * i386.h : Modify opcode to support for the change in POPCNT opcode
1784 in amdfam10 architecture.
1786 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1788 * i386.h: Replace CpuMNI with CpuSSSE3.
1790 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1791 Joseph Myers <joseph@codesourcery.com>
1792 Ian Lance Taylor <ian@wasabisystems.com>
1793 Ben Elliston <bje@wasabisystems.com>
1795 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1797 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1799 * score-datadep.h: New file.
1800 * score-inst.h: New file.
1802 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1804 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1805 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1806 movdq2q and movq2dq.
1808 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1809 Michael Meissner <michael.meissner@amd.com>
1811 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1813 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1815 * i386.h (i386_optab): Add "nop" with memory reference.
1817 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1819 * i386.h (i386_optab): Update comment for 64bit NOP.
1821 2006-06-06 Ben Elliston <bje@au.ibm.com>
1822 Anton Blanchard <anton@samba.org>
1824 * ppc.h (PPC_OPCODE_POWER6): Define.
1827 2006-06-05 Thiemo Seufer <ths@mips.com>
1829 * mips.h: Improve description of MT flags.
1831 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1833 * m68k.h (mcf_mask): Define.
1835 2006-05-05 Thiemo Seufer <ths@mips.com>
1836 David Ung <davidu@mips.com>
1838 * mips.h (enum): Add macro M_CACHE_AB.
1840 2006-05-04 Thiemo Seufer <ths@mips.com>
1841 Nigel Stephens <nigel@mips.com>
1842 David Ung <davidu@mips.com>
1844 * mips.h: Add INSN_SMARTMIPS define.
1846 2006-04-30 Thiemo Seufer <ths@mips.com>
1847 David Ung <davidu@mips.com>
1849 * mips.h: Defines udi bits and masks. Add description of
1850 characters which may appear in the args field of udi
1853 2006-04-26 Thiemo Seufer <ths@networkno.de>
1855 * mips.h: Improve comments describing the bitfield instruction
1858 2006-04-26 Julian Brown <julian@codesourcery.com>
1860 * arm.h (FPU_VFP_EXT_V3): Define constant.
1861 (FPU_NEON_EXT_V1): Likewise.
1862 (FPU_VFP_HARD): Update.
1863 (FPU_VFP_V3): Define macro.
1864 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1866 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1868 * avr.h (AVR_ISA_PWMx): New.
1870 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1872 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1873 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1874 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1875 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1876 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1878 2006-03-10 Paul Brook <paul@codesourcery.com>
1880 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1882 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1884 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1885 first. Correct mask of bb "B" opcode.
1887 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1889 * i386.h (i386_optab): Support Intel Merom New Instructions.
1891 2006-02-24 Paul Brook <paul@codesourcery.com>
1893 * arm.h: Add V7 feature bits.
1895 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1897 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1899 2006-01-31 Paul Brook <paul@codesourcery.com>
1900 Richard Earnshaw <rearnsha@arm.com>
1902 * arm.h: Use ARM_CPU_FEATURE.
1903 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1904 (arm_feature_set): Change to a structure.
1905 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1906 ARM_FEATURE): New macros.
1908 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1910 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1911 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1912 (ADD_PC_INCR_OPCODE): Don't define.
1914 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1917 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1919 2005-11-14 David Ung <davidu@mips.com>
1921 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1922 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1923 save/restore encoding of the args field.
1925 2005-10-28 Dave Brolley <brolley@redhat.com>
1927 Contribute the following changes:
1928 2005-02-16 Dave Brolley <brolley@redhat.com>
1930 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1931 cgen_isa_mask_* to cgen_bitset_*.
1934 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1936 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1937 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1938 (CGEN_CPU_TABLE): Make isas a ponter.
1940 2003-09-29 Dave Brolley <brolley@redhat.com>
1942 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1943 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1944 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1946 2002-12-13 Dave Brolley <brolley@redhat.com>
1948 * cgen.h (symcat.h): #include it.
1949 (cgen-bitset.h): #include it.
1950 (CGEN_ATTR_VALUE_TYPE): Now a union.
1951 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1952 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1953 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1954 * cgen-bitset.h: New file.
1956 2005-09-30 Catherine Moore <clm@cm00re.com>
1960 2005-10-24 Jan Beulich <jbeulich@novell.com>
1962 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1965 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1967 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1968 Add FLAG_STRICT to pa10 ftest opcode.
1970 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1972 * hppa.h (pa_opcodes): Remove lha entries.
1974 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1976 * hppa.h (FLAG_STRICT): Revise comment.
1977 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1978 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1981 2005-09-30 Catherine Moore <clm@cm00re.com>
1985 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1987 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1989 2005-09-06 Chao-ying Fu <fu@mips.com>
1991 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1992 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1994 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1995 (INSN_ASE_MASK): Update to include INSN_MT.
1996 (INSN_MT): New define for MT ASE.
1998 2005-08-25 Chao-ying Fu <fu@mips.com>
2000 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
2001 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
2002 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
2003 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
2004 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
2005 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
2007 (INSN_DSP): New define for DSP ASE.
2009 2005-08-18 Alan Modra <amodra@bigpond.net.au>
2013 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
2015 * ppc.h (PPC_OPCODE_E300): Define.
2017 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
2019 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
2021 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2024 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2027 2005-07-27 Jan Beulich <jbeulich@novell.com>
2029 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2030 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2031 Add movq-s as 64-bit variants of movd-s.
2033 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2035 * hppa.h: Fix punctuation in comment.
2037 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2038 implicit space-register addressing. Set space-register bits on opcodes
2039 using implicit space-register addressing. Add various missing pa20
2040 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2041 space-register addressing. Use "fE" instead of "fe" in various
2044 2005-07-18 Jan Beulich <jbeulich@novell.com>
2046 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2048 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2050 * i386.h (i386_optab): Support Intel VMX Instructions.
2052 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2054 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2056 2005-07-05 Jan Beulich <jbeulich@novell.com>
2058 * i386.h (i386_optab): Add new insns.
2060 2005-07-01 Nick Clifton <nickc@redhat.com>
2062 * sparc.h: Add typedefs to structure declarations.
2064 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2067 * i386.h (i386_optab): Update comments for 64bit addressing on
2068 mov. Allow 64bit addressing for mov and movq.
2070 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2072 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2073 respectively, in various floating-point load and store patterns.
2075 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2077 * hppa.h (FLAG_STRICT): Correct comment.
2078 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2079 PA 2.0 mneumonics when equivalent. Entries with cache control
2080 completers now require PA 1.1. Adjust whitespace.
2082 2005-05-19 Anton Blanchard <anton@samba.org>
2084 * ppc.h (PPC_OPCODE_POWER5): Define.
2086 2005-05-10 Nick Clifton <nickc@redhat.com>
2088 * Update the address and phone number of the FSF organization in
2089 the GPL notices in the following files:
2090 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2091 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2092 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2093 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2094 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2095 tic54x.h, tic80.h, v850.h, vax.h
2097 2005-05-09 Jan Beulich <jbeulich@novell.com>
2099 * i386.h (i386_optab): Add ht and hnt.
2101 2005-04-18 Mark Kettenis <kettenis@gnu.org>
2103 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2104 Add xcrypt-ctr. Provide aliases without hyphens.
2106 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2108 Moved from ../ChangeLog
2110 2005-04-12 Paul Brook <paul@codesourcery.com>
2111 * m88k.h: Rename psr macros to avoid conflicts.
2113 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2114 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2115 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2116 and ARM_ARCH_V6ZKT2.
2118 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2119 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2120 Remove redundant instruction types.
2121 (struct argument): X_op - new field.
2122 (struct cst4_entry): Remove.
2123 (no_op_insn): Declare.
2125 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2126 * crx.h (enum argtype): Rename types, remove unused types.
2128 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2129 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2130 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2131 (enum operand_type): Rearrange operands, edit comments.
2132 replace us<N> with ui<N> for unsigned immediate.
2133 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2134 displacements (respectively).
2135 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2136 (instruction type): Add NO_TYPE_INS.
2137 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2138 (operand_entry): New field - 'flags'.
2139 (operand flags): New.
2141 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2142 * crx.h (operand_type): Remove redundant types i3, i4,
2144 Add new unsigned immediate types us3, us4, us5, us16.
2146 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2148 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2149 adjust them accordingly.
2151 2005-04-01 Jan Beulich <jbeulich@novell.com>
2153 * i386.h (i386_optab): Add rdtscp.
2155 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2157 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2158 between memory and segment register. Allow movq for moving between
2159 general-purpose register and segment register.
2161 2005-02-09 Jan Beulich <jbeulich@novell.com>
2164 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2165 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2168 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2170 * m68k.h (m68008, m68ec030, m68882): Remove.
2172 (cpu_m68k, cpu_cf): New.
2173 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2174 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2176 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2178 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2179 * cgen.h (enum cgen_parse_operand_type): Add
2180 CGEN_PARSE_OPERAND_SYMBOLIC.
2182 2005-01-21 Fred Fish <fnf@specifixinc.com>
2184 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2185 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2186 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2188 2005-01-19 Fred Fish <fnf@specifixinc.com>
2190 * mips.h (struct mips_opcode): Add new pinfo2 member.
2191 (INSN_ALIAS): New define for opcode table entries that are
2192 specific instances of another entry, such as 'move' for an 'or'
2193 with a zero operand.
2194 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2195 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2197 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2199 * mips.h (CPU_RM9000): Define.
2200 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2202 2004-11-25 Jan Beulich <jbeulich@novell.com>
2204 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2205 to/from test registers are illegal in 64-bit mode. Add missing
2206 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2207 (previously one had to explicitly encode a rex64 prefix). Re-enable
2208 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2209 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2211 2004-11-23 Jan Beulich <jbeulich@novell.com>
2213 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2214 available only with SSE2. Change the MMX additions introduced by SSE
2215 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2216 instructions by their now designated identifier (since combining i686
2217 and 3DNow! does not really imply 3DNow!A).
2219 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2221 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2222 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2224 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2225 Vineet Sharma <vineets@noida.hcltech.com>
2227 * maxq.h: New file: Disassembly information for the maxq port.
2229 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2231 * i386.h (i386_optab): Put back "movzb".
2233 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2235 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2236 comments. Remove member cris_ver_sim. Add members
2237 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2238 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2239 (struct cris_support_reg, struct cris_cond15): New types.
2240 (cris_conds15): Declare.
2241 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2242 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2243 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2244 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2245 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2246 SIZE_FIELD_UNSIGNED.
2248 2004-11-04 Jan Beulich <jbeulich@novell.com>
2250 * i386.h (sldx_Suf): Remove.
2251 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2252 (q_FP): Define, implying no REX64.
2253 (x_FP, sl_FP): Imply FloatMF.
2254 (i386_optab): Split reg and mem forms of moving from segment registers
2255 so that the memory forms can ignore the 16-/32-bit operand size
2256 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2257 all non-floating-point instructions. Unite 32- and 64-bit forms of
2258 movsx, movzx, and movd. Adjust floating point operations for the above
2259 changes to the *FP macros. Add DefaultSize to floating point control
2260 insns operating on larger memory ranges. Remove left over comments
2261 hinting at certain insns being Intel-syntax ones where the ones
2262 actually meant are already gone.
2264 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2266 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2269 2004-09-30 Paul Brook <paul@codesourcery.com>
2271 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2272 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2274 2004-09-11 Theodore A. Roth <troth@openavr.org>
2276 * avr.h: Add support for
2277 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2279 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2281 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2283 2004-08-24 Dmitry Diky <diwil@spec.ru>
2285 * msp430.h (msp430_opc): Add new instructions.
2286 (msp430_rcodes): Declare new instructions.
2287 (msp430_hcodes): Likewise..
2289 2004-08-13 Nick Clifton <nickc@redhat.com>
2292 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2295 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2297 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2299 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2301 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2303 2004-07-21 Jan Beulich <jbeulich@novell.com>
2305 * i386.h: Adjust instruction descriptions to better match the
2308 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2310 * arm.h: Remove all old content. Replace with architecture defines
2311 from gas/config/tc-arm.c.
2313 2004-07-09 Andreas Schwab <schwab@suse.de>
2315 * m68k.h: Fix comment.
2317 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2321 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2323 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2325 2004-05-24 Peter Barada <peter@the-baradas.com>
2327 * m68k.h: Add 'size' to m68k_opcode.
2329 2004-05-05 Peter Barada <peter@the-baradas.com>
2331 * m68k.h: Switch from ColdFire chip name to core variant.
2333 2004-04-22 Peter Barada <peter@the-baradas.com>
2335 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2336 descriptions for new EMAC cases.
2337 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2338 handle Motorola MAC syntax.
2339 Allow disassembly of ColdFire V4e object files.
2341 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2343 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2345 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2347 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2349 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2351 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2353 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2355 * i386.h (i386_optab): Added xstore/xcrypt insns.
2357 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2359 * h8300.h (32bit ldc/stc): Add relaxing support.
2361 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2363 * h8300.h (BITOP): Pass MEMRELAX flag.
2365 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2367 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2370 For older changes see ChangeLog-9103
2372 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2374 Copying and distribution of this file, with or without modification,
2375 are permitted in any medium without royalty provided the copyright
2376 notice and this notice are preserved.
2382 version-control: never
projects / external / binutils.git / blob