mtd: cfi: introduce CFI_FLASH_BANKS
[platform/kernel/u-boot.git] / include / mtd / cfi_flash.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2009
4  * Stefan Roese, DENX Software Engineering, sr@denx.de.
5  */
6
7 #ifndef __CFI_FLASH_H__
8 #define __CFI_FLASH_H__
9
10 #define FLASH_CMD_CFI                   0x98
11 #define FLASH_CMD_READ_ID               0x90
12 #define FLASH_CMD_RESET                 0xff
13 #define FLASH_CMD_BLOCK_ERASE           0x20
14 #define FLASH_CMD_ERASE_CONFIRM         0xD0
15 #define FLASH_CMD_WRITE                 0x40
16 #define FLASH_CMD_PROTECT               0x60
17 #define FLASH_CMD_SETUP                 0x60
18 #define FLASH_CMD_SET_CR_CONFIRM        0x03
19 #define FLASH_CMD_PROTECT_SET           0x01
20 #define FLASH_CMD_PROTECT_CLEAR         0xD0
21 #define FLASH_CMD_CLEAR_STATUS          0x50
22 #define FLASH_CMD_READ_STATUS           0x70
23 #define FLASH_CMD_WRITE_TO_BUFFER       0xE8
24 #define FLASH_CMD_WRITE_BUFFER_PROG     0xE9
25 #define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
26
27 #define FLASH_STATUS_DONE               0x80
28 #define FLASH_STATUS_ESS                0x40
29 #define FLASH_STATUS_ECLBS              0x20
30 #define FLASH_STATUS_PSLBS              0x10
31 #define FLASH_STATUS_VPENS              0x08
32 #define FLASH_STATUS_PSS                0x04
33 #define FLASH_STATUS_DPS                0x02
34 #define FLASH_STATUS_R                  0x01
35 #define FLASH_STATUS_PROTECT            0x01
36
37 #define AMD_CMD_RESET                   0xF0
38 #define AMD_CMD_WRITE                   0xA0
39 #define AMD_CMD_ERASE_START             0x80
40 #define AMD_CMD_ERASE_SECTOR            0x30
41 #define AMD_CMD_UNLOCK_START            0xAA
42 #define AMD_CMD_UNLOCK_ACK              0x55
43 #define AMD_CMD_WRITE_TO_BUFFER         0x25
44 #define AMD_CMD_WRITE_BUFFER_CONFIRM    0x29
45 #define AMD_CMD_SET_PPB_ENTRY           0xC0
46 #define AMD_CMD_SET_PPB_EXIT_BC1        0x90
47 #define AMD_CMD_SET_PPB_EXIT_BC2        0x00
48 #define AMD_CMD_PPB_UNLOCK_BC1          0x80
49 #define AMD_CMD_PPB_UNLOCK_BC2          0x30
50 #define AMD_CMD_PPB_LOCK_BC1            0xA0
51 #define AMD_CMD_PPB_LOCK_BC2            0x00
52
53 #define AMD_STATUS_TOGGLE               0x40
54 #define AMD_STATUS_ERROR                0x20
55
56 #define ATM_CMD_UNLOCK_SECT             0x70
57 #define ATM_CMD_SOFTLOCK_START          0x80
58 #define ATM_CMD_LOCK_SECT               0x40
59
60 #define FLASH_CONTINUATION_CODE         0x7F
61
62 #define FLASH_OFFSET_MANUFACTURER_ID    0x00
63 #define FLASH_OFFSET_DEVICE_ID          0x01
64 #define FLASH_OFFSET_LOWER_SW_BITS      0x0C
65 #define FLASH_OFFSET_DEVICE_ID2         0x0E
66 #define FLASH_OFFSET_DEVICE_ID3         0x0F
67 #define FLASH_OFFSET_CFI                0x55
68 #define FLASH_OFFSET_CFI_ALT            0x555
69 #define FLASH_OFFSET_CFI_RESP           0x10
70 #define FLASH_OFFSET_PRIMARY_VENDOR     0x13
71 /* extended query table primary address */
72 #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15
73 #define FLASH_OFFSET_WTOUT              0x1F
74 #define FLASH_OFFSET_WBTOUT             0x20
75 #define FLASH_OFFSET_ETOUT              0x21
76 #define FLASH_OFFSET_CETOUT             0x22
77 #define FLASH_OFFSET_WMAX_TOUT          0x23
78 #define FLASH_OFFSET_WBMAX_TOUT         0x24
79 #define FLASH_OFFSET_EMAX_TOUT          0x25
80 #define FLASH_OFFSET_CEMAX_TOUT         0x26
81 #define FLASH_OFFSET_SIZE               0x27
82 #define FLASH_OFFSET_INTERFACE          0x28
83 #define FLASH_OFFSET_BUFFER_SIZE        0x2A
84 #define FLASH_OFFSET_NUM_ERASE_REGIONS  0x2C
85 #define FLASH_OFFSET_ERASE_REGIONS      0x2D
86 #define FLASH_OFFSET_PROTECT            0x02
87 #define FLASH_OFFSET_USER_PROTECTION    0x85
88 #define FLASH_OFFSET_INTEL_PROTECTION   0x81
89
90 #define CFI_CMDSET_NONE                 0
91 #define CFI_CMDSET_INTEL_EXTENDED       1
92 #define CFI_CMDSET_AMD_STANDARD         2
93 #define CFI_CMDSET_INTEL_STANDARD       3
94 #define CFI_CMDSET_AMD_EXTENDED         4
95 #define CFI_CMDSET_MITSU_STANDARD       256
96 #define CFI_CMDSET_MITSU_EXTENDED       257
97 #define CFI_CMDSET_SST                  258
98 #define CFI_CMDSET_INTEL_PROG_REGIONS   512
99
100 #ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
101 # undef  FLASH_CMD_RESET
102 # define FLASH_CMD_RESET        AMD_CMD_RESET /* use AMD-Reset instead */
103 #endif
104
105 #define NUM_ERASE_REGIONS       4 /* max. number of erase regions */
106
107 typedef union {
108         u8 w8;
109         u16 w16;
110         u32 w32;
111         u64 w64;
112 } cfiword_t;
113
114 /* CFI standard query structure */
115 /* The offsets and sizes of this packed structure members correspond
116  * to the actual layout in CFI Flash chips. Some 16- and 32-bit members
117  * are unaligned and must be accessed with explicit unaligned access macros.
118  */
119 struct cfi_qry {
120         u8      qry[3];
121         u16     p_id;                   /* unaligned */
122         u16     p_adr;                  /* unaligned */
123         u16     a_id;                   /* unaligned */
124         u16     a_adr;                  /* unaligned */
125         u8      vcc_min;
126         u8      vcc_max;
127         u8      vpp_min;
128         u8      vpp_max;
129         u8      word_write_timeout_typ;
130         u8      buf_write_timeout_typ;
131         u8      block_erase_timeout_typ;
132         u8      chip_erase_timeout_typ;
133         u8      word_write_timeout_max;
134         u8      buf_write_timeout_max;
135         u8      block_erase_timeout_max;
136         u8      chip_erase_timeout_max;
137         u8      dev_size;
138         u16     interface_desc;         /* aligned */
139         u16     max_buf_write_size;     /* aligned */
140         u8      num_erase_regions;
141         u32     erase_region_info[NUM_ERASE_REGIONS];   /* unaligned */
142 } __attribute__((packed));
143
144 struct cfi_pri_hdr {
145         u8      pri[3];
146         u8      major_version;
147         u8      minor_version;
148 } __attribute__((packed));
149
150 #ifndef CONFIG_SYS_FLASH_BANKS_LIST
151 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
152 #endif
153
154 /*
155  * CFI_MAX_FLASH_BANKS only used for flash_info struct declaration.
156  *
157  * CFI_FLASH_BANKS selects the correct number of available banks =
158  * cfi_flash_num_flash_banks when CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined
159  * or CONFIG_SYS_MAX_FLASH_BANKS
160  */
161 #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
162 #define CFI_MAX_FLASH_BANKS     CONFIG_SYS_MAX_FLASH_BANKS_DETECT
163 /* map to cfi_flash_num_flash_banks only when supported */
164 #if IS_ENABLED(CONFIG_FLASH_CFI_DRIVER) && \
165     (!IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_SPL_MTD_SUPPORT))
166 #define CFI_FLASH_BANKS         (cfi_flash_num_flash_banks)
167 /* board code can update this variable before CFI detection */
168 extern int cfi_flash_num_flash_banks;
169 #else
170 #define CFI_FLASH_BANKS         CONFIG_SYS_MAX_FLASH_BANKS_DETECT
171 #endif
172 #else
173 #define CFI_MAX_FLASH_BANKS     CONFIG_SYS_MAX_FLASH_BANKS
174 #define CFI_FLASH_BANKS         CONFIG_SYS_MAX_FLASH_BANKS
175 #endif
176
177 phys_addr_t cfi_flash_bank_addr(int i);
178 unsigned long cfi_flash_bank_size(int i);
179 void flash_cmd_reset(flash_info_t *info);
180
181 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
182 void flash_write8(u8 value, void *addr);
183 void flash_write16(u16 value, void *addr);
184 void flash_write32(u32 value, void *addr);
185 void flash_write64(u64 value, void *addr);
186 u8 flash_read8(void *addr);
187 u16 flash_read16(void *addr);
188 u32 flash_read32(void *addr);
189 u64 flash_read64(void *addr);
190 #endif
191
192 #endif /* __CFI_FLASH_H__ */