include/mpc83xx.h

   1 /*
   2  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #ifndef __MPC83XX_H__
  14 #define __MPC83XX_H__
  15
  16 #include <config.h>
  17 #if defined(CONFIG_E300)
  18 #include <asm/e300.h>
  19 #endif
  20
  21 /* MPC83xx cpu provide RCR register to do reset thing specially
  22  */
  23 #define MPC83xx_RESET
  24
  25 /* System reset offset (PowerPC standard)
  26  */
  27 #define EXC_OFF_SYS_RESET               0x0100
  28 #define _START_OFFSET                   EXC_OFF_SYS_RESET
  29
  30 /* IMMRBAR - Internal Memory Register Base Address
  31  */
  32 #define CONFIG_DEFAULT_IMMR             0xFF400000      /* Default IMMR base address */
  33 #define IMMRBAR                         0x0000          /* Register offset to immr */
  34 #define IMMRBAR_BASE_ADDR               0xFFF00000      /* Base address mask */
  35 #define IMMRBAR_RES                     ~(IMMRBAR_BASE_ADDR)
  36
  37 /* LAWBAR - Local Access Window Base Address Register
  38  */
  39 #define LBLAWBAR0                       0x0020          /* Register offset to immr */
  40 #define LBLAWAR0                        0x0024
  41 #define LBLAWBAR1                       0x0028
  42 #define LBLAWAR1                        0x002C
  43 #define LBLAWBAR2                       0x0030
  44 #define LBLAWAR2                        0x0034
  45 #define LBLAWBAR3                       0x0038
  46 #define LBLAWAR3                        0x003C
  47 #define LAWBAR_BAR                      0xFFFFF000      /* Base address mask */
  48
  49 /* SPRIDR - System Part and Revision ID Register
  50  */
  51 #define SPRIDR_PARTID                   0xFFFF0000      /* Part Identification */
  52 #define SPRIDR_REVID                    0x0000FFFF      /* Revision Identification */
  53
  54 #define SPR_8349E_REV10                 0x80300100
  55 #define SPR_8349_REV10                  0x80310100
  56 #define SPR_8347E_REV10_TBGA            0x80320100
  57 #define SPR_8347_REV10_TBGA             0x80330100
  58 #define SPR_8347E_REV10_PBGA            0x80340100
  59 #define SPR_8347_REV10_PBGA             0x80350100
  60 #define SPR_8343E_REV10                 0x80360100
  61 #define SPR_8343_REV10                  0x80370100
  62
  63 #define SPR_8349E_REV11                 0x80300101
  64 #define SPR_8349_REV11                  0x80310101
  65 #define SPR_8347E_REV11_TBGA            0x80320101
  66 #define SPR_8347_REV11_TBGA             0x80330101
  67 #define SPR_8347E_REV11_PBGA            0x80340101
  68 #define SPR_8347_REV11_PBGA             0x80350101
  69 #define SPR_8343E_REV11                 0x80360101
  70 #define SPR_8343_REV11                  0x80370101
  71
  72 #define SPR_8349E_REV31                 0x80300300
  73 #define SPR_8349_REV31                  0x80310300
  74 #define SPR_8347E_REV31_TBGA            0x80320300
  75 #define SPR_8347_REV31_TBGA             0x80330300
  76 #define SPR_8347E_REV31_PBGA            0x80340300
  77 #define SPR_8347_REV31_PBGA             0x80350300
  78 #define SPR_8343E_REV31                 0x80360300
  79 #define SPR_8343_REV31                  0x80370300
  80
  81 #define SPR_8360E_REV10                 0x80480010
  82 #define SPR_8360_REV10                  0x80490010
  83 #define SPR_8360E_REV11                 0x80480011
  84 #define SPR_8360_REV11                  0x80490011
  85 #define SPR_8360E_REV12                 0x80480012
  86 #define SPR_8360_REV12                  0x80490012
  87 #define SPR_8360E_REV20                 0x80480020
  88 #define SPR_8360_REV20                  0x80490020
  89
  90 #define SPR_8323E_REV10                 0x80620010
  91 #define SPR_8323_REV10                  0x80630010
  92 #define SPR_8321E_REV10                 0x80660010
  93 #define SPR_8321_REV10                  0x80670010
  94 #define SPR_8323E_REV11                 0x80620011
  95 #define SPR_8323_REV11                  0x80630011
  96 #define SPR_8321E_REV11                 0x80660011
  97 #define SPR_8321_REV11                  0x80670011
  98
  99 #define SPR_8311_REV10                  0x80B30010
 100 #define SPR_8311E_REV10                 0x80B20010
 101 #define SPR_8313_REV10                  0x80B10010
 102 #define SPR_8313E_REV10                 0x80B00010
 103
 104 /* SPCR - System Priority Configuration Register
 105  */
 106 #define SPCR_PCIHPE                     0x10000000      /* PCI Highest Priority Enable */
 107 #define SPCR_PCIHPE_SHIFT               (31-3)
 108 #define SPCR_PCIPR                      0x03000000      /* PCI bridge system bus request priority */
 109 #define SPCR_PCIPR_SHIFT                (31-7)
 110 #define SPCR_OPT                        0x00800000      /* Optimize */
 111 #define SPCR_TBEN                       0x00400000      /* E300 PowerPC core time base unit enable */
 112 #define SPCR_TBEN_SHIFT                 (31-9)
 113 #define SPCR_COREPR                     0x00300000      /* E300 PowerPC Core system bus request priority */
 114 #define SPCR_COREPR_SHIFT               (31-11)
 115
 116 #if defined(CONFIG_MPC834X)
 117 /* SPCR bits - MPC8349 specific */
 118 #define SPCR_TSEC1DP                    0x00003000      /* TSEC1 data priority */
 119 #define SPCR_TSEC1DP_SHIFT              (31-19)
 120 #define SPCR_TSEC1BDP                   0x00000C00      /* TSEC1 buffer descriptor priority */
 121 #define SPCR_TSEC1BDP_SHIFT             (31-21)
 122 #define SPCR_TSEC1EP                    0x00000300      /* TSEC1 emergency priority */
 123 #define SPCR_TSEC1EP_SHIFT              (31-23)
 124 #define SPCR_TSEC2DP                    0x00000030      /* TSEC2 data priority */
 125 #define SPCR_TSEC2DP_SHIFT              (31-27)
 126 #define SPCR_TSEC2BDP                   0x0000000C      /* TSEC2 buffer descriptor priority */
 127 #define SPCR_TSEC2BDP_SHIFT             (31-29)
 128 #define SPCR_TSEC2EP                    0x00000003      /* TSEC2 emergency priority */
 129 #define SPCR_TSEC2EP_SHIFT              (31-31)
 130
 131 #elif defined(CONFIG_MPC831X)
 132 /* SPCR bits - MPC831x specific */
 133 #define SPCR_TSECDP                     0x00003000      /* TSEC data priority */
 134 #define SPCR_TSECDP_SHIFT               (31-19)
 135 #define SPCR_TSECEP                     0x00000C00      /* TSEC emergency priority */
 136 #define SPCR_TSECEP_SHIFT               (31-21)
 137 #define SPCR_TSECBDP                    0x00000300      /* TSEC buffer descriptor priority */
 138 #define SPCR_TSECBDP_SHIFT              (31-23)
 139 #endif
 140
 141 /* SICRL/H - System I/O Configuration Register Low/High
 142  */
 143 #if defined(CONFIG_MPC834X)
 144 /* SICRL bits - MPC8349 specific */
 145 #define SICRL_LDP_A                     0x80000000
 146 #define SICRL_USB1                      0x40000000
 147 #define SICRL_USB0                      0x20000000
 148 #define SICRL_UART                      0x0C000000
 149 #define SICRL_GPIO1_A                   0x02000000
 150 #define SICRL_GPIO1_B                   0x01000000
 151 #define SICRL_GPIO1_C                   0x00800000
 152 #define SICRL_GPIO1_D                   0x00400000
 153 #define SICRL_GPIO1_E                   0x00200000
 154 #define SICRL_GPIO1_F                   0x00180000
 155 #define SICRL_GPIO1_G                   0x00040000
 156 #define SICRL_GPIO1_H                   0x00020000
 157 #define SICRL_GPIO1_I                   0x00010000
 158 #define SICRL_GPIO1_J                   0x00008000
 159 #define SICRL_GPIO1_K                   0x00004000
 160 #define SICRL_GPIO1_L                   0x00003000
 161
 162 /* SICRH bits - MPC8349 specific */
 163 #define SICRH_DDR                       0x80000000
 164 #define SICRH_TSEC1_A                   0x10000000
 165 #define SICRH_TSEC1_B                   0x08000000
 166 #define SICRH_TSEC1_C                   0x04000000
 167 #define SICRH_TSEC1_D                   0x02000000
 168 #define SICRH_TSEC1_E                   0x01000000
 169 #define SICRH_TSEC1_F                   0x00800000
 170 #define SICRH_TSEC2_A                   0x00400000
 171 #define SICRH_TSEC2_B                   0x00200000
 172 #define SICRH_TSEC2_C                   0x00100000
 173 #define SICRH_TSEC2_D                   0x00080000
 174 #define SICRH_TSEC2_E                   0x00040000
 175 #define SICRH_TSEC2_F                   0x00020000
 176 #define SICRH_TSEC2_G                   0x00010000
 177 #define SICRH_TSEC2_H                   0x00008000
 178 #define SICRH_GPIO2_A                   0x00004000
 179 #define SICRH_GPIO2_B                   0x00002000
 180 #define SICRH_GPIO2_C                   0x00001000
 181 #define SICRH_GPIO2_D                   0x00000800
 182 #define SICRH_GPIO2_E                   0x00000400
 183 #define SICRH_GPIO2_F                   0x00000200
 184 #define SICRH_GPIO2_G                   0x00000180
 185 #define SICRH_GPIO2_H                   0x00000060
 186 #define SICRH_TSOBI1                    0x00000002
 187 #define SICRH_TSOBI2                    0x00000001
 188
 189 #elif defined(CONFIG_MPC8360)
 190 /* SICRL bits - MPC8360 specific */
 191 #define SICRL_LDP_A                     0xC0000000
 192 #define SICRL_LCLK_1                    0x10000000
 193 #define SICRL_LCLK_2                    0x08000000
 194 #define SICRL_SRCID_A                   0x03000000
 195 #define SICRL_IRQ_CKSTP_A               0x00C00000
 196
 197 /* SICRH bits - MPC8360 specific */
 198 #define SICRH_DDR                       0x80000000
 199 #define SICRH_SECONDARY_DDR             0x40000000
 200 #define SICRH_SDDROE                    0x20000000
 201 #define SICRH_IRQ3                      0x10000000
 202 #define SICRH_UC1EOBI                   0x00000004
 203 #define SICRH_UC2E1OBI                  0x00000002
 204 #define SICRH_UC2E2OBI                  0x00000001
 205
 206 #elif defined(CONFIG_MPC832X)
 207 /* SICRL bits - MPC832X specific */
 208 #define SICRL_LDP_LCS_A                 0x80000000
 209 #define SICRL_IRQ_CKS                   0x20000000
 210 #define SICRL_PCI_MSRC                  0x10000000
 211 #define SICRL_URT_CTPR                  0x06000000
 212 #define SICRL_IRQ_CTPR                  0x00C00000
 213
 214 #elif defined(CONFIG_MPC831X)
 215 /* SICRL bits - MPC831x specific */
 216 #define SICRL_LBC                       0x30000000
 217 #define SICRL_UART                      0x0C000000
 218 #define SICRL_SPI_A                     0x03000000
 219 #define SICRL_SPI_B                     0x00C00000
 220 #define SICRL_SPI_C                     0x00300000
 221 #define SICRL_SPI_D                     0x000C0000
 222 #define SICRL_USBDR                     0x00000C00
 223 #define SICRL_ETSEC1_A                  0x0000000C
 224 #define SICRL_ETSEC2_A                  0x00000003
 225
 226 /* SICRH bits - MPC831x specific */
 227 #define SICRH_INTR_A                    0x02000000
 228 #define SICRH_INTR_B                    0x00C00000
 229 #define SICRH_IIC                       0x00300000
 230 #define SICRH_ETSEC2_B                  0x000C0000
 231 #define SICRH_ETSEC2_C                  0x00030000
 232 #define SICRH_ETSEC2_D                  0x0000C000
 233 #define SICRH_ETSEC2_E                  0x00003000
 234 #define SICRH_ETSEC2_F                  0x00000C00
 235 #define SICRH_ETSEC2_G                  0x00000300
 236 #define SICRH_ETSEC1_B                  0x00000080
 237 #define SICRH_ETSEC1_C                  0x00000060
 238 #define SICRH_GTX1_DLY                  0x00000008
 239 #define SICRH_GTX2_DLY                  0x00000004
 240 #define SICRH_TSOBI1                    0x00000002
 241 #define SICRH_TSOBI2                    0x00000001
 242
 243 #endif
 244
 245 /* SWCRR - System Watchdog Control Register
 246  */
 247 #define SWCRR                           0x0204          /* Register offset to immr */
 248 #define SWCRR_SWTC                      0xFFFF0000      /* Software Watchdog Time Count */
 249 #define SWCRR_SWEN                      0x00000004      /* Watchdog Enable bit */
 250 #define SWCRR_SWRI                      0x00000002      /* Software Watchdog Reset/Interrupt Select bit */
 251 #define SWCRR_SWPR                      0x00000001      /* Software Watchdog Counter Prescale bit */
 252 #define SWCRR_RES                       ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
 253
 254 /* SWCNR - System Watchdog Counter Register
 255  */
 256 #define SWCNR                           0x0208          /* Register offset to immr */
 257 #define SWCNR_SWCN                      0x0000FFFF      /* Software Watchdog Count mask */
 258 #define SWCNR_RES                       ~(SWCNR_SWCN)
 259
 260 /* SWSRR - System Watchdog Service Register
 261  */
 262 #define SWSRR                           0x020E          /* Register offset to immr */
 263
 264 /* ACR - Arbiter Configuration Register
 265  */
 266 #define ACR_COREDIS                     0x10000000      /* Core disable */
 267 #define ACR_COREDIS_SHIFT               (31-7)
 268 #define ACR_PIPE_DEP                    0x00070000      /* Pipeline depth */
 269 #define ACR_PIPE_DEP_SHIFT              (31-15)
 270 #define ACR_PCI_RPTCNT                  0x00007000      /* PCI repeat count */
 271 #define ACR_PCI_RPTCNT_SHIFT            (31-19)
 272 #define ACR_RPTCNT                      0x00000700      /* Repeat count */
 273 #define ACR_RPTCNT_SHIFT                (31-23)
 274 #define ACR_APARK                       0x00000030      /* Address parking */
 275 #define ACR_APARK_SHIFT                 (31-27)
 276 #define ACR_PARKM                       0x0000000F      /* Parking master */
 277 #define ACR_PARKM_SHIFT                 (31-31)
 278
 279 /* ATR - Arbiter Timers Register
 280  */
 281 #define ATR_DTO                         0x00FF0000      /* Data time out */
 282 #define ATR_ATO                         0x000000FF      /* Address time out */
 283
 284 /* AER - Arbiter Event Register
 285  */
 286 #define AER_ETEA                        0x00000020      /* Transfer error */
 287 #define AER_RES                         0x00000010      /* Reserved transfer type */
 288 #define AER_ECW                         0x00000008      /* External control word transfer type */
 289 #define AER_AO                          0x00000004      /* Address Only transfer type */
 290 #define AER_DTO                         0x00000002      /* Data time out */
 291 #define AER_ATO                         0x00000001      /* Address time out */
 292
 293 /* AEATR - Arbiter Event Address Register
 294  */
 295 #define AEATR_EVENT                     0x07000000      /* Event type */
 296 #define AEATR_MSTR_ID                   0x001F0000      /* Master Id */
 297 #define AEATR_TBST                      0x00000800      /* Transfer burst */
 298 #define AEATR_TSIZE                     0x00000700      /* Transfer Size */
 299 #define AEATR_TTYPE                     0x0000001F      /* Transfer Type */
 300
 301 /* HRCWL - Hard Reset Configuration Word Low
 302  */
 303 #define HRCWL_LBIUCM                    0x80000000
 304 #define HRCWL_LBIUCM_SHIFT              31
 305 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1    0x00000000
 306 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1    0x80000000
 307
 308 #define HRCWL_DDRCM                     0x40000000
 309 #define HRCWL_DDRCM_SHIFT               30
 310 #define HRCWL_DDR_TO_SCB_CLK_1X1        0x00000000
 311 #define HRCWL_DDR_TO_SCB_CLK_2X1        0x40000000
 312
 313 #define HRCWL_SPMF                      0x0f000000
 314 #define HRCWL_SPMF_SHIFT                24
 315 #define HRCWL_CSB_TO_CLKIN_16X1         0x00000000
 316 #define HRCWL_CSB_TO_CLKIN_1X1          0x01000000
 317 #define HRCWL_CSB_TO_CLKIN_2X1          0x02000000
 318 #define HRCWL_CSB_TO_CLKIN_3X1          0x03000000
 319 #define HRCWL_CSB_TO_CLKIN_4X1          0x04000000
 320 #define HRCWL_CSB_TO_CLKIN_5X1          0x05000000
 321 #define HRCWL_CSB_TO_CLKIN_6X1          0x06000000
 322 #define HRCWL_CSB_TO_CLKIN_7X1          0x07000000
 323 #define HRCWL_CSB_TO_CLKIN_8X1          0x08000000
 324 #define HRCWL_CSB_TO_CLKIN_9X1          0x09000000
 325 #define HRCWL_CSB_TO_CLKIN_10X1         0x0A000000
 326 #define HRCWL_CSB_TO_CLKIN_11X1         0x0B000000
 327 #define HRCWL_CSB_TO_CLKIN_12X1         0x0C000000
 328 #define HRCWL_CSB_TO_CLKIN_13X1         0x0D000000
 329 #define HRCWL_CSB_TO_CLKIN_14X1         0x0E000000
 330 #define HRCWL_CSB_TO_CLKIN_15X1         0x0F000000
 331
 332 #define HRCWL_VCO_BYPASS                0x00000000
 333 #define HRCWL_VCO_1X2                   0x00000000
 334 #define HRCWL_VCO_1X4                   0x00200000
 335 #define HRCWL_VCO_1X8                   0x00400000
 336
 337 #define HRCWL_COREPLL                   0x007F0000
 338 #define HRCWL_COREPLL_SHIFT             16
 339 #define HRCWL_CORE_TO_CSB_BYPASS        0x00000000
 340 #define HRCWL_CORE_TO_CSB_1X1           0x00020000
 341 #define HRCWL_CORE_TO_CSB_1_5X1         0x00030000
 342 #define HRCWL_CORE_TO_CSB_2X1           0x00040000
 343 #define HRCWL_CORE_TO_CSB_2_5X1         0x00050000
 344 #define HRCWL_CORE_TO_CSB_3X1           0x00060000
 345
 346 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 347 #define HRCWL_CEVCOD                    0x000000C0
 348 #define HRCWL_CEVCOD_SHIFT              6
 349 #define HRCWL_CE_PLL_VCO_DIV_4          0x00000000
 350 #define HRCWL_CE_PLL_VCO_DIV_8          0x00000040
 351 #define HRCWL_CE_PLL_VCO_DIV_2          0x00000080
 352
 353 #define HRCWL_CEPDF                     0x00000020
 354 #define HRCWL_CEPDF_SHIFT               5
 355 #define HRCWL_CE_PLL_DIV_1X1            0x00000000
 356 #define HRCWL_CE_PLL_DIV_2X1            0x00000020
 357
 358 #define HRCWL_CEPMF                     0x0000001F
 359 #define HRCWL_CEPMF_SHIFT               0
 360 #define HRCWL_CE_TO_PLL_1X16_           0x00000000
 361 #define HRCWL_CE_TO_PLL_1X2             0x00000002
 362 #define HRCWL_CE_TO_PLL_1X3             0x00000003
 363 #define HRCWL_CE_TO_PLL_1X4             0x00000004
 364 #define HRCWL_CE_TO_PLL_1X5             0x00000005
 365 #define HRCWL_CE_TO_PLL_1X6             0x00000006
 366 #define HRCWL_CE_TO_PLL_1X7             0x00000007
 367 #define HRCWL_CE_TO_PLL_1X8             0x00000008
 368 #define HRCWL_CE_TO_PLL_1X9             0x00000009
 369 #define HRCWL_CE_TO_PLL_1X10            0x0000000A
 370 #define HRCWL_CE_TO_PLL_1X11            0x0000000B
 371 #define HRCWL_CE_TO_PLL_1X12            0x0000000C
 372 #define HRCWL_CE_TO_PLL_1X13            0x0000000D
 373 #define HRCWL_CE_TO_PLL_1X14            0x0000000E
 374 #define HRCWL_CE_TO_PLL_1X15            0x0000000F
 375 #define HRCWL_CE_TO_PLL_1X16            0x00000010
 376 #define HRCWL_CE_TO_PLL_1X17            0x00000011
 377 #define HRCWL_CE_TO_PLL_1X18            0x00000012
 378 #define HRCWL_CE_TO_PLL_1X19            0x00000013
 379 #define HRCWL_CE_TO_PLL_1X20            0x00000014
 380 #define HRCWL_CE_TO_PLL_1X21            0x00000015
 381 #define HRCWL_CE_TO_PLL_1X22            0x00000016
 382 #define HRCWL_CE_TO_PLL_1X23            0x00000017
 383 #define HRCWL_CE_TO_PLL_1X24            0x00000018
 384 #define HRCWL_CE_TO_PLL_1X25            0x00000019
 385 #define HRCWL_CE_TO_PLL_1X26            0x0000001A
 386 #define HRCWL_CE_TO_PLL_1X27            0x0000001B
 387 #define HRCWL_CE_TO_PLL_1X28            0x0000001C
 388 #define HRCWL_CE_TO_PLL_1X29            0x0000001D
 389 #define HRCWL_CE_TO_PLL_1X30            0x0000001E
 390 #define HRCWL_CE_TO_PLL_1X31            0x0000001F
 391 #endif
 392
 393 /* HRCWH - Hardware Reset Configuration Word High
 394  */
 395 #define HRCWH_PCI_HOST                  0x80000000
 396 #define HRCWH_PCI_HOST_SHIFT            31
 397 #define HRCWH_PCI_AGENT                 0x00000000
 398
 399 #if defined(CONFIG_MPC834X)
 400 #define HRCWH_32_BIT_PCI                0x00000000
 401 #define HRCWH_64_BIT_PCI                0x40000000
 402 #endif
 403
 404 #define HRCWH_PCI1_ARBITER_DISABLE      0x00000000
 405 #define HRCWH_PCI1_ARBITER_ENABLE       0x20000000
 406
 407 #define HRCWH_PCI_ARBITER_DISABLE       0x00000000
 408 #define HRCWH_PCI_ARBITER_ENABLE        0x20000000
 409
 410 #if defined(CONFIG_MPC834X)
 411 #define HRCWH_PCI2_ARBITER_DISABLE      0x00000000
 412 #define HRCWH_PCI2_ARBITER_ENABLE       0x10000000
 413
 414 #elif defined(CONFIG_MPC8360)
 415 #define HRCWH_PCICKDRV_DISABLE          0x00000000
 416 #define HRCWH_PCICKDRV_ENABLE           0x10000000
 417 #endif
 418
 419 #define HRCWH_CORE_DISABLE              0x08000000
 420 #define HRCWH_CORE_ENABLE               0x00000000
 421
 422 #define HRCWH_FROM_0X00000100           0x00000000
 423 #define HRCWH_FROM_0XFFF00100           0x04000000
 424
 425 #define HRCWH_BOOTSEQ_DISABLE           0x00000000
 426 #define HRCWH_BOOTSEQ_NORMAL            0x01000000
 427 #define HRCWH_BOOTSEQ_EXTENDED          0x02000000
 428
 429 #define HRCWH_SW_WATCHDOG_DISABLE       0x00000000
 430 #define HRCWH_SW_WATCHDOG_ENABLE        0x00800000
 431
 432 #define HRCWH_ROM_LOC_DDR_SDRAM         0x00000000
 433 #define HRCWH_ROM_LOC_PCI1              0x00100000
 434 #if defined(CONFIG_MPC834X)
 435 #define HRCWH_ROM_LOC_PCI2              0x00200000
 436 #endif
 437 #define HRCWH_ROM_LOC_LOCAL_8BIT        0x00500000
 438 #define HRCWH_ROM_LOC_LOCAL_16BIT       0x00600000
 439 #define HRCWH_ROM_LOC_LOCAL_32BIT       0x00700000
 440
 441 #if defined(CONFIG_MPC831X)
 442 #define HRCWH_ROM_LOC_NAND_SP_8BIT      0x00100000
 443 #define HRCWH_ROM_LOC_NAND_SP_16BIT     0x00200000
 444 #define HRCWH_ROM_LOC_NAND_LP_8BIT      0x00500000
 445 #define HRCWH_ROM_LOC_NAND_LP_16BIT     0x00600000
 446
 447 #define HRCWH_RL_EXT_LEGACY             0x00000000
 448 #define HRCWH_RL_EXT_NAND               0x00040000
 449
 450 #define HRCWH_TSEC1M_IN_MII             0x00000000
 451 #define HRCWH_TSEC1M_IN_RMII            0x00002000
 452 #define HRCWH_TSEC1M_IN_RGMII           0x00006000
 453 #define HRCWH_TSEC1M_IN_RTBI            0x0000A000
 454 #define HRCWH_TSEC1M_IN_SGMII           0x0000C000
 455
 456 #define HRCWH_TSEC2M_IN_MII             0x00000000
 457 #define HRCWH_TSEC2M_IN_RMII            0x00000400
 458 #define HRCWH_TSEC2M_IN_RGMII           0x00000C00
 459 #define HRCWH_TSEC2M_IN_RTBI            0x00001400
 460 #define HRCWH_TSEC2M_IN_SGMII           0x00001800
 461 #endif
 462
 463 #if defined(CONFIG_MPC834X)
 464 #define HRCWH_TSEC1M_IN_RGMII           0x00000000
 465 #define HRCWH_TSEC1M_IN_RTBI            0x00004000
 466 #define HRCWH_TSEC1M_IN_GMII            0x00008000
 467 #define HRCWH_TSEC1M_IN_TBI             0x0000C000
 468 #define HRCWH_TSEC2M_IN_RGMII           0x00000000
 469 #define HRCWH_TSEC2M_IN_RTBI            0x00001000
 470 #define HRCWH_TSEC2M_IN_GMII            0x00002000
 471 #define HRCWH_TSEC2M_IN_TBI             0x00003000
 472 #endif
 473
 474 #if defined(CONFIG_MPC8360)
 475 #define HRCWH_SECONDARY_DDR_DISABLE     0x00000000
 476 #define HRCWH_SECONDARY_DDR_ENABLE      0x00000010
 477 #endif
 478
 479 #define HRCWH_BIG_ENDIAN                0x00000000
 480 #define HRCWH_LITTLE_ENDIAN             0x00000008
 481
 482 #define HRCWH_LALE_NORMAL               0x00000000
 483 #define HRCWH_LALE_EARLY                0x00000004
 484
 485 #define HRCWH_LDP_SET                   0x00000000
 486 #define HRCWH_LDP_CLEAR                 0x00000002
 487
 488 /* RSR - Reset Status Register
 489  */
 490 #define RSR_RSTSRC                      0xE0000000      /* Reset source */
 491 #define RSR_RSTSRC_SHIFT                29
 492 #define RSR_BSF                         0x00010000      /* Boot seq. fail */
 493 #define RSR_BSF_SHIFT                   16
 494 #define RSR_SWSR                        0x00002000      /* software soft reset */
 495 #define RSR_SWSR_SHIFT                  13
 496 #define RSR_SWHR                        0x00001000      /* software hard reset */
 497 #define RSR_SWHR_SHIFT                  12
 498 #define RSR_JHRS                        0x00000200      /* jtag hreset */
 499 #define RSR_JHRS_SHIFT                  9
 500 #define RSR_JSRS                        0x00000100      /* jtag sreset status */
 501 #define RSR_JSRS_SHIFT                  8
 502 #define RSR_CSHR                        0x00000010      /* checkstop reset status */
 503 #define RSR_CSHR_SHIFT                  4
 504 #define RSR_SWRS                        0x00000008      /* software watchdog reset status */
 505 #define RSR_SWRS_SHIFT                  3
 506 #define RSR_BMRS                        0x00000004      /* bus monitop reset status */
 507 #define RSR_BMRS_SHIFT                  2
 508 #define RSR_SRS                         0x00000002      /* soft reset status */
 509 #define RSR_SRS_SHIFT                   1
 510 #define RSR_HRS                         0x00000001      /* hard reset status */
 511 #define RSR_HRS_SHIFT                   0
 512 #define RSR_RES                         ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\
 513                                          RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
 514                                          RSR_BMRS | RSR_SRS | RSR_HRS)
 515 /* RMR - Reset Mode Register
 516  */
 517 #define RMR_CSRE                        0x00000001      /* checkstop reset enable */
 518 #define RMR_CSRE_SHIFT                  0
 519 #define RMR_RES                         ~(RMR_CSRE)
 520
 521 /* RCR - Reset Control Register
 522  */
 523 #define RCR_SWHR                        0x00000002      /* software hard reset */
 524 #define RCR_SWSR                        0x00000001      /* software soft reset */
 525 #define RCR_RES                         ~(RCR_SWHR | RCR_SWSR)
 526
 527 /* RCER - Reset Control Enable Register
 528  */
 529 #define RCER_CRE                        0x00000001      /* software hard reset */
 530 #define RCER_RES                        ~(RCER_CRE)
 531
 532 /* SPMR - System PLL Mode Register
 533  */
 534 #define SPMR_LBIUCM                     0x80000000
 535 #define SPMR_DDRCM                      0x40000000
 536 #define SPMR_SPMF                       0x0F000000
 537 #define SPMR_CKID                       0x00800000
 538 #define SPMR_CKID_SHIFT                 23
 539 #define SPMR_COREPLL                    0x007F0000
 540 #define SPMR_CEVCOD                     0x000000C0
 541 #define SPMR_CEPDF                      0x00000020
 542 #define SPMR_CEPMF                      0x0000001F
 543
 544 /* OCCR - Output Clock Control Register
 545  */
 546 #define OCCR_PCICOE0                    0x80000000
 547 #define OCCR_PCICOE1                    0x40000000
 548 #define OCCR_PCICOE2                    0x20000000
 549 #define OCCR_PCICOE3                    0x10000000
 550 #define OCCR_PCICOE4                    0x08000000
 551 #define OCCR_PCICOE5                    0x04000000
 552 #define OCCR_PCICOE6                    0x02000000
 553 #define OCCR_PCICOE7                    0x01000000
 554 #define OCCR_PCICD0                     0x00800000
 555 #define OCCR_PCICD1                     0x00400000
 556 #define OCCR_PCICD2                     0x00200000
 557 #define OCCR_PCICD3                     0x00100000
 558 #define OCCR_PCICD4                     0x00080000
 559 #define OCCR_PCICD5                     0x00040000
 560 #define OCCR_PCICD6                     0x00020000
 561 #define OCCR_PCICD7                     0x00010000
 562 #define OCCR_PCI1CR                     0x00000002
 563 #define OCCR_PCI2CR                     0x00000001
 564 #define OCCR_PCICR                      OCCR_PCI1CR
 565
 566 /* SCCR - System Clock Control Register
 567  */
 568 #define SCCR_ENCCM                      0x03000000
 569 #define SCCR_ENCCM_SHIFT                24
 570 #define SCCR_ENCCM_0                    0x00000000
 571 #define SCCR_ENCCM_1                    0x01000000
 572 #define SCCR_ENCCM_2                    0x02000000
 573 #define SCCR_ENCCM_3                    0x03000000
 574
 575 #define SCCR_PCICM                      0x00010000
 576 #define SCCR_PCICM_SHIFT                16
 577
 578 /* SCCR bits - MPC8349 specific */
 579 #ifdef CONFIG_MPC834X
 580 #define SCCR_TSEC1CM                    0xc0000000
 581 #define SCCR_TSEC1CM_SHIFT              30
 582 #define SCCR_TSEC1CM_0                  0x00000000
 583 #define SCCR_TSEC1CM_1                  0x40000000
 584 #define SCCR_TSEC1CM_2                  0x80000000
 585 #define SCCR_TSEC1CM_3                  0xC0000000
 586
 587 #define SCCR_TSEC2CM                    0x30000000
 588 #define SCCR_TSEC2CM_SHIFT              28
 589 #define SCCR_TSEC2CM_0                  0x00000000
 590 #define SCCR_TSEC2CM_1                  0x10000000
 591 #define SCCR_TSEC2CM_2                  0x20000000
 592 #define SCCR_TSEC2CM_3                  0x30000000
 593
 594 #elif defined(CONFIG_MPC831X)
 595 /* TSEC1 bits are for TSEC2 as well */
 596 #define SCCR_TSEC1CM                    0xc0000000
 597 #define SCCR_TSEC1CM_SHIFT              30
 598 #define SCCR_TSEC1CM_1                  0x40000000
 599 #define SCCR_TSEC1CM_2                  0x80000000
 600 #define SCCR_TSEC1CM_3                  0xC0000000
 601
 602 #define SCCR_TSEC1ON                    0x20000000
 603 #define SCCR_TSEC2ON                    0x10000000
 604
 605 #endif
 606
 607 #define SCCR_USBMPHCM                   0x00c00000
 608 #define SCCR_USBMPHCM_SHIFT             22
 609 #define SCCR_USBDRCM                    0x00300000
 610 #define SCCR_USBDRCM_SHIFT              20
 611
 612 #define SCCR_USBCM_0                    0x00000000
 613 #define SCCR_USBCM_1                    0x00500000
 614 #define SCCR_USBCM_2                    0x00A00000
 615 #define SCCR_USBCM_3                    0x00F00000
 616
 617 /* CSn_BDNS - Chip Select memory Bounds Register
 618  */
 619 #define CSBNDS_SA                       0x00FF0000
 620 #define CSBNDS_SA_SHIFT                 8
 621 #define CSBNDS_EA                       0x000000FF
 622 #define CSBNDS_EA_SHIFT                 24
 623
 624 /* CSn_CONFIG - Chip Select Configuration Register
 625  */
 626 #define CSCONFIG_EN                     0x80000000
 627 #define CSCONFIG_AP                     0x00800000
 628 #define CSCONFIG_ROW_BIT                0x00000700
 629 #define CSCONFIG_ROW_BIT_12             0x00000000
 630 #define CSCONFIG_ROW_BIT_13             0x00000100
 631 #define CSCONFIG_ROW_BIT_14             0x00000200
 632 #define CSCONFIG_COL_BIT                0x00000007
 633 #define CSCONFIG_COL_BIT_8              0x00000000
 634 #define CSCONFIG_COL_BIT_9              0x00000001
 635 #define CSCONFIG_COL_BIT_10             0x00000002
 636 #define CSCONFIG_COL_BIT_11             0x00000003
 637
 638 /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
 639  */
 640 #define TIMING_CFG0_RWT                 0xC0000000
 641 #define TIMING_CFG0_RWT_SHIFT           30
 642 #define TIMING_CFG0_WRT                 0x30000000
 643 #define TIMING_CFG0_WRT_SHIFT           28
 644 #define TIMING_CFG0_RRT                 0x0C000000
 645 #define TIMING_CFG0_RRT_SHIFT           26
 646 #define TIMING_CFG0_WWT                 0x03000000
 647 #define TIMING_CFG0_WWT_SHIFT           24
 648 #define TIMING_CFG0_ACT_PD_EXIT         0x00700000
 649 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT   20
 650 #define TIMING_CFG0_PRE_PD_EXIT         0x00070000
 651 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT   16
 652 #define TIMING_CFG0_ODT_PD_EXIT         0x00000F00
 653 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT   8
 654 #define TIMING_CFG0_MRS_CYC             0x00000F00
 655 #define TIMING_CFG0_MRS_CYC_SHIFT       0
 656
 657 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
 658  */
 659 #define TIMING_CFG1_PRETOACT            0x70000000
 660 #define TIMING_CFG1_PRETOACT_SHIFT      28
 661 #define TIMING_CFG1_ACTTOPRE            0x0F000000
 662 #define TIMING_CFG1_ACTTOPRE_SHIFT      24
 663 #define TIMING_CFG1_ACTTORW             0x00700000
 664 #define TIMING_CFG1_ACTTORW_SHIFT       20
 665 #define TIMING_CFG1_CASLAT              0x00070000
 666 #define TIMING_CFG1_CASLAT_SHIFT        16
 667 #define TIMING_CFG1_REFREC              0x0000F000
 668 #define TIMING_CFG1_REFREC_SHIFT        12
 669 #define TIMING_CFG1_WRREC               0x00000700
 670 #define TIMING_CFG1_WRREC_SHIFT         8
 671 #define TIMING_CFG1_ACTTOACT            0x00000070
 672 #define TIMING_CFG1_ACTTOACT_SHIFT      4
 673 #define TIMING_CFG1_WRTORD              0x00000007
 674 #define TIMING_CFG1_WRTORD_SHIFT        0
 675 #define TIMING_CFG1_CASLAT_20           0x00030000      /* CAS latency = 2.0 */
 676 #define TIMING_CFG1_CASLAT_25           0x00040000      /* CAS latency = 2.5 */
 677
 678 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
 679  */
 680 #define TIMING_CFG2_CPO                 0x0F800000
 681 #define TIMING_CFG2_CPO_SHIFT           23
 682 #define TIMING_CFG2_ACSM                0x00080000
 683 #define TIMING_CFG2_WR_DATA_DELAY       0x00001C00
 684 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
 685 #define TIMING_CFG2_CPO_DEF             0x00000000      /* default (= CASLAT + 1) */
 686
 687 #define TIMING_CFG2_ADD_LAT             0x70000000
 688 #define TIMING_CFG2_ADD_LAT_SHIFT       28
 689 #define TIMING_CFG2_WR_LAT_DELAY        0x00380000
 690 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT  19
 691 #define TIMING_CFG2_RD_TO_PRE           0x0000E000
 692 #define TIMING_CFG2_RD_TO_PRE_SHIFT     13
 693 #define TIMING_CFG2_CKE_PLS             0x000001C0
 694 #define TIMING_CFG2_CKE_PLS_SHIFT       6
 695 #define TIMING_CFG2_FOUR_ACT            0x0000003F
 696 #define TIMING_CFG2_FOUR_ACT_SHIFT      0
 697
 698 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
 699  */
 700 #define SDRAM_CFG_MEM_EN                0x80000000
 701 #define SDRAM_CFG_SREN                  0x40000000
 702 #define SDRAM_CFG_ECC_EN                0x20000000
 703 #define SDRAM_CFG_RD_EN                 0x10000000
 704 #define SDRAM_CFG_SDRAM_TYPE            0x03000000
 705 #define SDRAM_CFG_SDRAM_TYPE_DDR        0x02000000
 706 #define SDRAM_CFG_SDRAM_TYPE_SHIFT      24
 707 #define SDRAM_CFG_DYN_PWR               0x00200000
 708 #define SDRAM_CFG_32_BE                 0x00080000
 709 #define SDRAM_CFG_8_BE                  0x00040000
 710 #define SDRAM_CFG_NCAP                  0x00020000
 711 #define SDRAM_CFG_2T_EN                 0x00008000
 712 #define SDRAM_CFG_BI                    0x00000001
 713
 714 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register
 715  */
 716 #define SDRAM_MODE_ESD                  0xFFFF0000
 717 #define SDRAM_MODE_ESD_SHIFT            16
 718 #define SDRAM_MODE_SD                   0x0000FFFF
 719 #define SDRAM_MODE_SD_SHIFT             0
 720 #define DDR_MODE_EXT_MODEREG            0x4000          /* select extended mode reg */
 721 #define DDR_MODE_EXT_OPMODE             0x3FF8          /* operating mode, mask */
 722 #define DDR_MODE_EXT_OP_NORMAL          0x0000          /* normal operation */
 723 #define DDR_MODE_QFC                    0x0004          /* QFC / compatibility, mask */
 724 #define DDR_MODE_QFC_COMP               0x0000          /* compatible to older SDRAMs */
 725 #define DDR_MODE_WEAK                   0x0002          /* weak drivers */
 726 #define DDR_MODE_DLL_DIS                0x0001          /* disable DLL */
 727 #define DDR_MODE_CASLAT                 0x0070          /* CAS latency, mask */
 728 #define DDR_MODE_CASLAT_15              0x0010          /* CAS latency 1.5 */
 729 #define DDR_MODE_CASLAT_20              0x0020          /* CAS latency 2 */
 730 #define DDR_MODE_CASLAT_25              0x0060          /* CAS latency 2.5 */
 731 #define DDR_MODE_CASLAT_30              0x0030          /* CAS latency 3 */
 732 #define DDR_MODE_BTYPE_SEQ              0x0000          /* sequential burst */
 733 #define DDR_MODE_BTYPE_ILVD             0x0008          /* interleaved burst */
 734 #define DDR_MODE_BLEN_2                 0x0001          /* burst length 2 */
 735 #define DDR_MODE_BLEN_4                 0x0002          /* burst length 4 */
 736 #define DDR_REFINT_166MHZ_7US           1302            /* exact value for 7.8125us */
 737 #define DDR_BSTOPRE                     256             /* use 256 cycles as a starting point */
 738 #define DDR_MODE_MODEREG                0x0000          /* select mode register */
 739
 740 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
 741  */
 742 #define SDRAM_INTERVAL_REFINT           0x3FFF0000
 743 #define SDRAM_INTERVAL_REFINT_SHIFT     16
 744 #define SDRAM_INTERVAL_BSTOPRE          0x00003FFF
 745 #define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
 746
 747 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
 748  */
 749 #define DDR_SDRAM_CLK_CNTL_SS_EN                0x80000000
 750 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025       0x01000000
 751 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05        0x02000000
 752 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075       0x03000000
 753 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1         0x04000000
 754
 755 /* ECC_ERR_INJECT - Memory data path error injection mask ECC
 756  */
 757 #define ECC_ERR_INJECT_EMB              (0x80000000>>22)        /* ECC Mirror Byte */
 758 #define ECC_ERR_INJECT_EIEN             (0x80000000>>23)        /* Error Injection Enable */
 759 #define ECC_ERR_INJECT_EEIM             (0xff000000>>24)        /* ECC Erroe Injection Enable */
 760 #define ECC_ERR_INJECT_EEIM_SHIFT       0
 761
 762 /* CAPTURE_ECC - Memory data path read capture ECC
 763  */
 764 #define CAPTURE_ECC_ECE                 (0xff000000>>24)
 765 #define CAPTURE_ECC_ECE_SHIFT           0
 766
 767 /* ERR_DETECT - Memory error detect
 768  */
 769 #define ECC_ERROR_DETECT_MME            (0x80000000>>0)         /* Multiple Memory Errors */
 770 #define ECC_ERROR_DETECT_MBE            (0x80000000>>28)        /* Multiple-Bit Error */
 771 #define ECC_ERROR_DETECT_SBE            (0x80000000>>29)        /* Single-Bit ECC Error Pickup */
 772 #define ECC_ERROR_DETECT_MSE            (0x80000000>>31)        /* Memory Select Error */
 773
 774 /* ERR_DISABLE - Memory error disable
 775  */
 776 #define ECC_ERROR_DISABLE_MBED          (0x80000000>>28)        /* Multiple-Bit ECC Error Disable */
 777 #define ECC_ERROR_DISABLE_SBED          (0x80000000>>29)        /* Sinle-Bit ECC Error disable */
 778 #define ECC_ERROR_DISABLE_MSED          (0x80000000>>31)        /* Memory Select Error Disable */
 779 #define ECC_ERROR_ENABLE                ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
 780                                          ECC_ERROR_DISABLE_MBED)
 781 /* ERR_INT_EN - Memory error interrupt enable
 782  */
 783 #define ECC_ERR_INT_EN_MBEE             (0x80000000>>28)        /* Multiple-Bit ECC Error Interrupt Enable */
 784 #define ECC_ERR_INT_EN_SBEE             (0x80000000>>29)        /* Single-Bit ECC Error Interrupt Enable */
 785 #define ECC_ERR_INT_EN_MSEE             (0x80000000>>31)        /* Memory Select Error Interrupt Enable */
 786 #define ECC_ERR_INT_DISABLE             ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
 787                                          ECC_ERR_INT_EN_MSEE)
 788 /* CAPTURE_ATTRIBUTES - Memory error attributes capture
 789  */
 790 #define ECC_CAPT_ATTR_BNUM              (0xe0000000>>1)         /* Data Beat Num */
 791 #define ECC_CAPT_ATTR_BNUM_SHIFT        28
 792 #define ECC_CAPT_ATTR_TSIZ              (0xc0000000>>6)         /* Transaction Size */
 793 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW      0
 794 #define ECC_CAPT_ATTR_TSIZ_ONE_DW       1
 795 #define ECC_CAPT_ATTR_TSIZ_TWO_DW       2
 796 #define ECC_CAPT_ATTR_TSIZ_THREE_DW     3
 797 #define ECC_CAPT_ATTR_TSIZ_SHIFT        24
 798 #define ECC_CAPT_ATTR_TSRC              (0xf8000000>>11)        /* Transaction Source */
 799 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
 800 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
 801 #define ECC_CAPT_ATTR_TSRC_TSEC1        0x4
 802 #define ECC_CAPT_ATTR_TSRC_TSEC2        0x5
 803 #define ECC_CAPT_ATTR_TSRC_USB          (0x06|0x07)
 804 #define ECC_CAPT_ATTR_TSRC_ENCRYPT      0x8
 805 #define ECC_CAPT_ATTR_TSRC_I2C          0x9
 806 #define ECC_CAPT_ATTR_TSRC_JTAG         0xA
 807 #define ECC_CAPT_ATTR_TSRC_PCI1         0xD
 808 #define ECC_CAPT_ATTR_TSRC_PCI2         0xE
 809 #define ECC_CAPT_ATTR_TSRC_DMA          0xF
 810 #define ECC_CAPT_ATTR_TSRC_SHIFT        16
 811 #define ECC_CAPT_ATTR_TTYP              (0xe0000000>>18)        /* Transaction Type */
 812 #define ECC_CAPT_ATTR_TTYP_WRITE        0x1
 813 #define ECC_CAPT_ATTR_TTYP_READ         0x2
 814 #define ECC_CAPT_ATTR_TTYP_R_M_W        0x3
 815 #define ECC_CAPT_ATTR_TTYP_SHIFT        12
 816 #define ECC_CAPT_ATTR_VLD               (0x80000000>>31)        /* Valid */
 817
 818 /* ERR_SBE - Single bit ECC memory error management
 819  */
 820 #define ECC_ERROR_MAN_SBET              (0xff000000>>8)         /* Single-Bit Error Threshold 0..255 */
 821 #define ECC_ERROR_MAN_SBET_SHIFT        16
 822 #define ECC_ERROR_MAN_SBEC              (0xff000000>>24)        /* Single Bit Error Counter 0..255 */
 823 #define ECC_ERROR_MAN_SBEC_SHIFT        0
 824
 825 /* BR - Base Registers
 826  */
 827 #define BR0                             0x5000          /* Register offset to immr */
 828 #define BR1                             0x5008
 829 #define BR2                             0x5010
 830 #define BR3                             0x5018
 831 #define BR4                             0x5020
 832 #define BR5                             0x5028
 833 #define BR6                             0x5030
 834 #define BR7                             0x5038
 835
 836 #define BR_BA                           0xFFFF8000
 837 #define BR_BA_SHIFT                     15
 838 #define BR_PS                           0x00001800
 839 #define BR_PS_SHIFT                     11
 840 #define BR_PS_8                         0x00000800      /* Port Size 8 bit */
 841 #define BR_PS_16                        0x00001000      /* Port Size 16 bit */
 842 #define BR_PS_32                        0x00001800      /* Port Size 32 bit */
 843 #define BR_DECC                         0x00000600
 844 #define BR_DECC_SHIFT                   9
 845 #define BR_DECC_OFF                     0x00000000
 846 #define BR_DECC_CHK                     0x00000200
 847 #define BR_DECC_CHK_GEN                 0x00000400
 848 #define BR_WP                           0x00000100
 849 #define BR_WP_SHIFT                     8
 850 #define BR_MSEL                         0x000000E0
 851 #define BR_MSEL_SHIFT                   5
 852 #define BR_MS_GPCM                      0x00000000      /* GPCM */
 853 #define BR_MS_FCM                       0x00000020      /* FCM */
 854 #define BR_MS_SDRAM                     0x00000060      /* SDRAM */
 855 #define BR_MS_UPMA                      0x00000080      /* UPMA */
 856 #define BR_MS_UPMB                      0x000000A0      /* UPMB */
 857 #define BR_MS_UPMC                      0x000000C0      /* UPMC */
 858 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 859 #define BR_ATOM                         0x0000000C
 860 #define BR_ATOM_SHIFT                   2
 861 #endif
 862 #define BR_V                            0x00000001
 863 #define BR_V_SHIFT                      0
 864
 865 #if defined(CONFIG_MPC834X)
 866 #define BR_RES                          ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
 867 #elif defined(CONFIG_MPC8360)
 868 #define BR_RES                          ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
 869 #endif
 870
 871 /* OR - Option Registers
 872  */
 873 #define OR0                             0x5004          /* Register offset to immr */
 874 #define OR1                             0x500C
 875 #define OR2                             0x5014
 876 #define OR3                             0x501C
 877 #define OR4                             0x5024
 878 #define OR5                             0x502C
 879 #define OR6                             0x5034
 880 #define OR7                             0x503C
 881
 882 #define OR_GPCM_AM                      0xFFFF8000
 883 #define OR_GPCM_AM_SHIFT                15
 884 #define OR_GPCM_BCTLD                   0x00001000
 885 #define OR_GPCM_BCTLD_SHIFT             12
 886 #define OR_GPCM_CSNT                    0x00000800
 887 #define OR_GPCM_CSNT_SHIFT              11
 888 #define OR_GPCM_ACS                     0x00000600
 889 #define OR_GPCM_ACS_SHIFT               9
 890 #define OR_GPCM_ACS_0b10                0x00000400
 891 #define OR_GPCM_ACS_0b11                0x00000600
 892 #define OR_GPCM_XACS                    0x00000100
 893 #define OR_GPCM_XACS_SHIFT              8
 894 #define OR_GPCM_SCY                     0x000000F0
 895 #define OR_GPCM_SCY_SHIFT               4
 896 #define OR_GPCM_SCY_1                   0x00000010
 897 #define OR_GPCM_SCY_2                   0x00000020
 898 #define OR_GPCM_SCY_3                   0x00000030
 899 #define OR_GPCM_SCY_4                   0x00000040
 900 #define OR_GPCM_SCY_5                   0x00000050
 901 #define OR_GPCM_SCY_6                   0x00000060
 902 #define OR_GPCM_SCY_7                   0x00000070
 903 #define OR_GPCM_SCY_8                   0x00000080
 904 #define OR_GPCM_SCY_9                   0x00000090
 905 #define OR_GPCM_SCY_10                  0x000000a0
 906 #define OR_GPCM_SCY_11                  0x000000b0
 907 #define OR_GPCM_SCY_12                  0x000000c0
 908 #define OR_GPCM_SCY_13                  0x000000d0
 909 #define OR_GPCM_SCY_14                  0x000000e0
 910 #define OR_GPCM_SCY_15                  0x000000f0
 911 #define OR_GPCM_SETA                    0x00000008
 912 #define OR_GPCM_SETA_SHIFT              3
 913 #define OR_GPCM_TRLX                    0x00000004
 914 #define OR_GPCM_TRLX_SHIFT              2
 915 #define OR_GPCM_EHTR                    0x00000002
 916 #define OR_GPCM_EHTR_SHIFT              1
 917 #define OR_GPCM_EAD                     0x00000001
 918 #define OR_GPCM_EAD_SHIFT               0
 919
 920 #define OR_FCM_AM                       0xFFFF8000
 921 #define OR_FCM_AM_SHIFT                         15
 922 #define OR_FCM_BCTLD                    0x00001000
 923 #define OR_FCM_BCTLD_SHIFT                      12
 924 #define OR_FCM_PGS                      0x00000400
 925 #define OR_FCM_PGS_SHIFT                        10
 926 #define OR_FCM_CSCT                     0x00000200
 927 #define OR_FCM_CSCT_SHIFT                        9
 928 #define OR_FCM_CST                      0x00000100
 929 #define OR_FCM_CST_SHIFT                         8
 930 #define OR_FCM_CHT                      0x00000080
 931 #define OR_FCM_CHT_SHIFT                         7
 932 #define OR_FCM_SCY                      0x00000070
 933 #define OR_FCM_SCY_SHIFT                         4
 934 #define OR_FCM_SCY_1                    0x00000010
 935 #define OR_FCM_SCY_2                    0x00000020
 936 #define OR_FCM_SCY_3                    0x00000030
 937 #define OR_FCM_SCY_4                    0x00000040
 938 #define OR_FCM_SCY_5                    0x00000050
 939 #define OR_FCM_SCY_6                    0x00000060
 940 #define OR_FCM_SCY_7                    0x00000070
 941 #define OR_FCM_RST                      0x00000008
 942 #define OR_FCM_RST_SHIFT                         3
 943 #define OR_FCM_TRLX                     0x00000004
 944 #define OR_FCM_TRLX_SHIFT                        2
 945 #define OR_FCM_EHTR                     0x00000002
 946 #define OR_FCM_EHTR_SHIFT                        1
 947
 948 #define OR_UPM_AM                       0xFFFF8000
 949 #define OR_UPM_AM_SHIFT                 15
 950 #define OR_UPM_XAM                      0x00006000
 951 #define OR_UPM_XAM_SHIFT                13
 952 #define OR_UPM_BCTLD                    0x00001000
 953 #define OR_UPM_BCTLD_SHIFT              12
 954 #define OR_UPM_BI                       0x00000100
 955 #define OR_UPM_BI_SHIFT                 8
 956 #define OR_UPM_TRLX                     0x00000004
 957 #define OR_UPM_TRLX_SHIFT               2
 958 #define OR_UPM_EHTR                     0x00000002
 959 #define OR_UPM_EHTR_SHIFT               1
 960 #define OR_UPM_EAD                      0x00000001
 961 #define OR_UPM_EAD_SHIFT                0
 962
 963 #define OR_SDRAM_AM                     0xFFFF8000
 964 #define OR_SDRAM_AM_SHIFT               15
 965 #define OR_SDRAM_XAM                    0x00006000
 966 #define OR_SDRAM_XAM_SHIFT              13
 967 #define OR_SDRAM_COLS                   0x00001C00
 968 #define OR_SDRAM_COLS_SHIFT             10
 969 #define OR_SDRAM_ROWS                   0x000001C0
 970 #define OR_SDRAM_ROWS_SHIFT             6
 971 #define OR_SDRAM_PMSEL                  0x00000020
 972 #define OR_SDRAM_PMSEL_SHIFT            5
 973 #define OR_SDRAM_EAD                    0x00000001
 974 #define OR_SDRAM_EAD_SHIFT              0
 975
 976 #define OR_AM_32KB                      0xFFFF8000
 977 #define OR_AM_64KB                      0xFFFF0000
 978 #define OR_AM_128KB                     0xFFFE0000
 979 #define OR_AM_256KB                     0xFFFC0000
 980 #define OR_AM_512KB                     0xFFF80000
 981 #define OR_AM_1MB                       0xFFF00000
 982 #define OR_AM_2MB                       0xFFE00000
 983 #define OR_AM_4MB                       0xFFC00000
 984 #define OR_AM_8MB                       0xFF800000
 985 #define OR_AM_16MB                      0xFF000000
 986 #define OR_AM_32MB                      0xFE000000
 987 #define OR_AM_64MB                      0xFC000000
 988 #define OR_AM_128MB                     0xF8000000
 989 #define OR_AM_256MB                     0xF0000000
 990 #define OR_AM_512MB                     0xE0000000
 991 #define OR_AM_1GB                       0xC0000000
 992 #define OR_AM_2GB                       0x80000000
 993 #define OR_AM_4GB                       0x00000000
 994
 995 #define LBLAWAR_EN                      0x80000000
 996 #define LBLAWAR_4KB                     0x0000000B
 997 #define LBLAWAR_8KB                     0x0000000C
 998 #define LBLAWAR_16KB                    0x0000000D
 999 #define LBLAWAR_32KB                    0x0000000E
1000 #define LBLAWAR_64KB                    0x0000000F
1001 #define LBLAWAR_128KB                   0x00000010
1002 #define LBLAWAR_256KB                   0x00000011
1003 #define LBLAWAR_512KB                   0x00000012
1004 #define LBLAWAR_1MB                     0x00000013
1005 #define LBLAWAR_2MB                     0x00000014
1006 #define LBLAWAR_4MB                     0x00000015
1007 #define LBLAWAR_8MB                     0x00000016
1008 #define LBLAWAR_16MB                    0x00000017
1009 #define LBLAWAR_32MB                    0x00000018
1010 #define LBLAWAR_64MB                    0x00000019
1011 #define LBLAWAR_128MB                   0x0000001A
1012 #define LBLAWAR_256MB                   0x0000001B
1013 #define LBLAWAR_512MB                   0x0000001C
1014 #define LBLAWAR_1GB                     0x0000001D
1015 #define LBLAWAR_2GB                     0x0000001E
1016
1017 /* LBCR - Local Bus Configuration Register
1018  */
1019 #define LBCR_LDIS                       0x80000000
1020 #define LBCR_LDIS_SHIFT                 31
1021 #define LBCR_BCTLC                      0x00C00000
1022 #define LBCR_BCTLC_SHIFT                22
1023 #define LBCR_LPBSE                      0x00020000
1024 #define LBCR_LPBSE_SHIFT                17
1025 #define LBCR_EPAR                       0x00010000
1026 #define LBCR_EPAR_SHIFT                 16
1027 #define LBCR_BMT                        0x0000FF00
1028 #define LBCR_BMT_SHIFT                  8
1029
1030 /* LCRR - Clock Ratio Register
1031  */
1032 #define LCRR_DBYP                       0x80000000
1033 #define LCRR_DBYP_SHIFT                 31
1034 #define LCRR_BUFCMDC                    0x30000000
1035 #define LCRR_BUFCMDC_SHIFT              28
1036 #define LCRR_BUFCMDC_1                  0x10000000
1037 #define LCRR_BUFCMDC_2                  0x20000000
1038 #define LCRR_BUFCMDC_3                  0x30000000
1039 #define LCRR_BUFCMDC_4                  0x00000000
1040 #define LCRR_ECL                        0x03000000
1041 #define LCRR_ECL_SHIFT                  24
1042 #define LCRR_ECL_4                      0x00000000
1043 #define LCRR_ECL_5                      0x01000000
1044 #define LCRR_ECL_6                      0x02000000
1045 #define LCRR_ECL_7                      0x03000000
1046 #define LCRR_EADC                       0x00030000
1047 #define LCRR_EADC_SHIFT                 16
1048 #define LCRR_EADC_1                     0x00010000
1049 #define LCRR_EADC_2                     0x00020000
1050 #define LCRR_EADC_3                     0x00030000
1051 #define LCRR_EADC_4                     0x00000000
1052 #define LCRR_CLKDIV                     0x0000000F
1053 #define LCRR_CLKDIV_SHIFT               0
1054 #define LCRR_CLKDIV_2                   0x00000002
1055 #define LCRR_CLKDIV_4                   0x00000004
1056 #define LCRR_CLKDIV_8                   0x00000008
1057
1058 /* DMAMR - DMA Mode Register
1059  */
1060 #define DMA_CHANNEL_START                       0x00000001      /* Bit - DMAMRn CS */
1061 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT        0x00000004      /* Bit - DMAMRn CTM */
1062 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN      0x00001000      /* Bit - DMAMRn SAHE */
1063 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B      0x00000000      /* 2Bit- DMAMRn SAHTS 1byte */
1064 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B      0x00004000      /* 2Bit- DMAMRn SAHTS 2bytes */
1065 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B      0x00008000      /* 2Bit- DMAMRn SAHTS 4bytes */
1066 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B      0x0000c000      /* 2Bit- DMAMRn SAHTS 8bytes */
1067 #define DMA_CHANNEL_SNOOP                       0x00010000      /* Bit - DMAMRn DMSEN */
1068
1069 /* DMASR - DMA Status Register
1070  */
1071 #define DMA_CHANNEL_BUSY                        0x00000004      /* Bit - DMASRn CB */
1072 #define DMA_CHANNEL_TRANSFER_ERROR              0x00000080      /* Bit - DMASRn TE */
1073
1074 /* CONFIG_ADDRESS - PCI Config Address Register
1075  */
1076 #define PCI_CONFIG_ADDRESS_EN           0x80000000
1077 #define PCI_CONFIG_ADDRESS_BN_SHIFT     16
1078 #define PCI_CONFIG_ADDRESS_BN_MASK      0x00ff0000
1079 #define PCI_CONFIG_ADDRESS_DN_SHIFT     11
1080 #define PCI_CONFIG_ADDRESS_DN_MASK      0x0000f800
1081 #define PCI_CONFIG_ADDRESS_FN_SHIFT     8
1082 #define PCI_CONFIG_ADDRESS_FN_MASK      0x00000700
1083 #define PCI_CONFIG_ADDRESS_RN_SHIFT     0
1084 #define PCI_CONFIG_ADDRESS_RN_MASK      0x000000fc
1085
1086 /* POTAR - PCI Outbound Translation Address Register
1087  */
1088 #define POTAR_TA_MASK                   0x000fffff
1089
1090 /* POBAR - PCI Outbound Base Address Register
1091  */
1092 #define POBAR_BA_MASK                   0x000fffff
1093
1094 /* POCMR - PCI Outbound Comparision Mask Register
1095  */
1096 #define POCMR_EN                        0x80000000
1097 #define POCMR_IO                        0x40000000      /* 0-memory space 1-I/O space */
1098 #define POCMR_SE                        0x20000000      /* streaming enable */
1099 #define POCMR_DST                       0x10000000      /* 0-PCI1 1-PCI2 */
1100 #define POCMR_CM_MASK                   0x000fffff
1101 #define POCMR_CM_4G                     0x00000000
1102 #define POCMR_CM_2G                     0x00080000
1103 #define POCMR_CM_1G                     0x000C0000
1104 #define POCMR_CM_512M                   0x000E0000
1105 #define POCMR_CM_256M                   0x000F0000
1106 #define POCMR_CM_128M                   0x000F8000
1107 #define POCMR_CM_64M                    0x000FC000
1108 #define POCMR_CM_32M                    0x000FE000
1109 #define POCMR_CM_16M                    0x000FF000
1110 #define POCMR_CM_8M                     0x000FF800
1111 #define POCMR_CM_4M                     0x000FFC00
1112 #define POCMR_CM_2M                     0x000FFE00
1113 #define POCMR_CM_1M                     0x000FFF00
1114 #define POCMR_CM_512K                   0x000FFF80
1115 #define POCMR_CM_256K                   0x000FFFC0
1116 #define POCMR_CM_128K                   0x000FFFE0
1117 #define POCMR_CM_64K                    0x000FFFF0
1118 #define POCMR_CM_32K                    0x000FFFF8
1119 #define POCMR_CM_16K                    0x000FFFFC
1120 #define POCMR_CM_8K                     0x000FFFFE
1121 #define POCMR_CM_4K                     0x000FFFFF
1122
1123 /* PITAR - PCI Inbound Translation Address Register
1124  */
1125 #define PITAR_TA_MASK                   0x000fffff
1126
1127 /* PIBAR - PCI Inbound Base/Extended Address Register
1128  */
1129 #define PIBAR_MASK                      0xffffffff
1130 #define PIEBAR_EBA_MASK                 0x000fffff
1131
1132 /* PIWAR - PCI Inbound Windows Attributes Register
1133  */
1134 #define PIWAR_EN                        0x80000000
1135 #define PIWAR_PF                        0x20000000
1136 #define PIWAR_RTT_MASK                  0x000f0000
1137 #define PIWAR_RTT_NO_SNOOP              0x00040000
1138 #define PIWAR_RTT_SNOOP                 0x00050000
1139 #define PIWAR_WTT_MASK                  0x0000f000
1140 #define PIWAR_WTT_NO_SNOOP              0x00004000
1141 #define PIWAR_WTT_SNOOP                 0x00005000
1142 #define PIWAR_IWS_MASK                  0x0000003F
1143 #define PIWAR_IWS_4K                    0x0000000B
1144 #define PIWAR_IWS_8K                    0x0000000C
1145 #define PIWAR_IWS_16K                   0x0000000D
1146 #define PIWAR_IWS_32K                   0x0000000E
1147 #define PIWAR_IWS_64K                   0x0000000F
1148 #define PIWAR_IWS_128K                  0x00000010
1149 #define PIWAR_IWS_256K                  0x00000011
1150 #define PIWAR_IWS_512K                  0x00000012
1151 #define PIWAR_IWS_1M                    0x00000013
1152 #define PIWAR_IWS_2M                    0x00000014
1153 #define PIWAR_IWS_4M                    0x00000015
1154 #define PIWAR_IWS_8M                    0x00000016
1155 #define PIWAR_IWS_16M                   0x00000017
1156 #define PIWAR_IWS_32M                   0x00000018
1157 #define PIWAR_IWS_64M                   0x00000019
1158 #define PIWAR_IWS_128M                  0x0000001A
1159 #define PIWAR_IWS_256M                  0x0000001B
1160 #define PIWAR_IWS_512M                  0x0000001C
1161 #define PIWAR_IWS_1G                    0x0000001D
1162 #define PIWAR_IWS_2G                    0x0000001E
1163
1164 /* PMCCR1 - PCI Configuration Register 1
1165  */
1166 #define PMCCR1_POWER_OFF                0x00000020
1167
1168 /* FMR - Flash Mode Register
1169  */
1170 #define FMR_CWTO                0x0000F000
1171 #define FMR_CWTO_SHIFT          12
1172 #define FMR_BOOT                0x00000800
1173 #define FMR_ECCM                0x00000100
1174 #define FMR_AL                  0x00000030
1175 #define FMR_AL_SHIFT            4
1176 #define FMR_OP                  0x00000003
1177 #define FMR_OP_SHIFT            0
1178
1179 /* FIR - Flash Instruction Register
1180  */
1181 #define FIR_OP0                 0xF0000000
1182 #define FIR_OP0_SHIFT           28
1183 #define FIR_OP1                 0x0F000000
1184 #define FIR_OP1_SHIFT           24
1185 #define FIR_OP2                 0x00F00000
1186 #define FIR_OP2_SHIFT           20
1187 #define FIR_OP3                 0x000F0000
1188 #define FIR_OP3_SHIFT           16
1189 #define FIR_OP4                 0x0000F000
1190 #define FIR_OP4_SHIFT           12
1191 #define FIR_OP5                 0x00000F00
1192 #define FIR_OP5_SHIFT           8
1193 #define FIR_OP6                 0x000000F0
1194 #define FIR_OP6_SHIFT           4
1195 #define FIR_OP7                 0x0000000F
1196 #define FIR_OP7_SHIFT           0
1197 #define FIR_OP_NOP              0x0 /* No operation and end of sequence */
1198 #define FIR_OP_CA               0x1 /* Issue current column address */
1199 #define FIR_OP_PA               0x2 /* Issue current block+page address */
1200 #define FIR_OP_UA               0x3 /* Issue user defined address */
1201 #define FIR_OP_CM0              0x4 /* Issue command from FCR[CMD0] */
1202 #define FIR_OP_CM1              0x5 /* Issue command from FCR[CMD1] */
1203 #define FIR_OP_CM2              0x6 /* Issue command from FCR[CMD2] */
1204 #define FIR_OP_CM3              0x7 /* Issue command from FCR[CMD3] */
1205 #define FIR_OP_WB               0x8 /* Write FBCR bytes from FCM buffer */
1206 #define FIR_OP_WS               0x9 /* Write 1 or 2 bytes from MDR[AS] */
1207 #define FIR_OP_RB               0xA /* Read FBCR bytes to FCM buffer */
1208 #define FIR_OP_RS               0xB /* Read 1 or 2 bytes to MDR[AS] */
1209 #define FIR_OP_CW0              0xC /* Wait then issue FCR[CMD0] */
1210 #define FIR_OP_CW1              0xD /* Wait then issue FCR[CMD1] */
1211 #define FIR_OP_RBW              0xE /* Wait then read FBCR bytes */
1212 #define FIR_OP_RSW              0xF /* Wait then read 1 or 2 bytes */
1213
1214 /* FCR - Flash Command Register
1215  */
1216 #define FCR_CMD0                0xFF000000
1217 #define FCR_CMD0_SHIFT          24
1218 #define FCR_CMD1                0x00FF0000
1219 #define FCR_CMD1_SHIFT          16
1220 #define FCR_CMD2                0x0000FF00
1221 #define FCR_CMD2_SHIFT          8
1222 #define FCR_CMD3                0x000000FF
1223 #define FCR_CMD3_SHIFT          0
1224
1225 /* FBAR - Flash Block Address Register
1226  */
1227 #define FBAR_BLK                0x00FFFFFF
1228
1229 /* FPAR - Flash Page Address Register
1230  */
1231 #define FPAR_SP_PI              0x00007C00
1232 #define FPAR_SP_PI_SHIFT        10
1233 #define FPAR_SP_MS              0x00000200
1234 #define FPAR_SP_CI              0x000001FF
1235 #define FPAR_SP_CI_SHIFT        0
1236 #define FPAR_LP_PI              0x0003F000
1237 #define FPAR_LP_PI_SHIFT        12
1238 #define FPAR_LP_MS              0x00000800
1239 #define FPAR_LP_CI              0x000007FF
1240 #define FPAR_LP_CI_SHIFT        0
1241
1242 /* LTESR - Transfer Error Status Register
1243  */
1244 #define LTESR_BM                0x80000000
1245 #define LTESR_FCT               0x40000000
1246 #define LTESR_PAR               0x20000000
1247 #define LTESR_WP                0x04000000
1248 #define LTESR_ATMW              0x00800000
1249 #define LTESR_ATMR              0x00400000
1250 #define LTESR_CS                0x00080000
1251 #define LTESR_CC                0x00000001
1252
1253 /* DDR Control Driver Register
1254  */
1255 #define DDRCDR_EN               0x40000000
1256 #define DDRCDR_PZ               0x3C000000
1257 #define DDRCDR_PZ_MAXZ          0x00000000
1258 #define DDRCDR_PZ_HIZ           0x20000000
1259 #define DDRCDR_PZ_NOMZ          0x30000000
1260 #define DDRCDR_PZ_LOZ           0x38000000
1261 #define DDRCDR_PZ_MINZ          0x3C000000
1262 #define DDRCDR_NZ               0x3C000000
1263 #define DDRCDR_NZ_MAXZ          0x00000000
1264 #define DDRCDR_NZ_HIZ           0x02000000
1265 #define DDRCDR_NZ_NOMZ          0x03000000
1266 #define DDRCDR_NZ_LOZ           0x03800000
1267 #define DDRCDR_NZ_MINZ          0x03C00000
1268 #define DDRCDR_ODT              0x00080000
1269 #define DDRCDR_DDR_CFG          0x00040000
1270 #define DDRCDR_M_ODR            0x00000002
1271 #define DDRCDR_Q_DRN            0x00000001
1272
1273 #ifndef __ASSEMBLY__
1274 struct pci_region;
1275 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
1276 #endif
1277
1278 #endif  /* __MPC83XX_H__ */