2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
17 #if defined(CONFIG_E300)
21 /* MPC83xx cpu provide RCR register to do reset thing specially
25 /* System reset offset (PowerPC standard)
27 #define EXC_OFF_SYS_RESET 0x0100
29 /* IMMRBAR - Internal Memory Register Base Address
31 #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */
32 #define IMMRBAR 0x0000 /* Register offset to immr */
33 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */
34 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
36 /* LAWBAR - Local Access Window Base Address Register
38 #define LBLAWBAR0 0x0020 /* Register offset to immr */
39 #define LBLAWAR0 0x0024
40 #define LBLAWBAR1 0x0028
41 #define LBLAWAR1 0x002C
42 #define LBLAWBAR2 0x0030
43 #define LBLAWAR2 0x0034
44 #define LBLAWBAR3 0x0038
45 #define LBLAWAR3 0x003C
46 #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */
48 /* SPRIDR - System Part and Revision ID Register
50 #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
51 #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
53 #define SPR_8349E_REV10 0x80300100
54 #define SPR_8349_REV10 0x80310100
55 #define SPR_8347E_REV10_TBGA 0x80320100
56 #define SPR_8347_REV10_TBGA 0x80330100
57 #define SPR_8347E_REV10_PBGA 0x80340100
58 #define SPR_8347_REV10_PBGA 0x80350100
59 #define SPR_8343E_REV10 0x80360100
60 #define SPR_8343_REV10 0x80370100
62 #define SPR_8349E_REV11 0x80300101
63 #define SPR_8349_REV11 0x80310101
64 #define SPR_8347E_REV11_TBGA 0x80320101
65 #define SPR_8347_REV11_TBGA 0x80330101
66 #define SPR_8347E_REV11_PBGA 0x80340101
67 #define SPR_8347_REV11_PBGA 0x80350101
68 #define SPR_8343E_REV11 0x80360101
69 #define SPR_8343_REV11 0x80370101
71 #define SPR_8349E_REV31 0x80300300
72 #define SPR_8349_REV31 0x80310300
73 #define SPR_8347E_REV31_TBGA 0x80320300
74 #define SPR_8347_REV31_TBGA 0x80330300
75 #define SPR_8347E_REV31_PBGA 0x80340300
76 #define SPR_8347_REV31_PBGA 0x80350300
77 #define SPR_8343E_REV31 0x80360300
78 #define SPR_8343_REV31 0x80370300
80 #define SPR_8360E_REV10 0x80480010
81 #define SPR_8360_REV10 0x80490010
82 #define SPR_8360E_REV11 0x80480011
83 #define SPR_8360_REV11 0x80490011
84 #define SPR_8360E_REV12 0x80480012
85 #define SPR_8360_REV12 0x80490012
87 #define SPR_8323E_REV10 0x80620010
88 #define SPR_8323_REV10 0x80630010
89 #define SPR_8321E_REV10 0x80660010
90 #define SPR_8321_REV10 0x80670010
91 #define SPR_8323E_REV11 0x80620011
92 #define SPR_8323_REV11 0x80630011
93 #define SPR_8321E_REV11 0x80660011
94 #define SPR_8321_REV11 0x80670011
96 /* SPCR - System Priority Configuration Register
98 #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
99 #define SPCR_PCIHPE_SHIFT (31-3)
100 #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */
101 #define SPCR_PCIPR_SHIFT (31-7)
102 #define SPCR_OPT 0x00800000 /* Optimize */
103 #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */
104 #define SPCR_TBEN_SHIFT (31-9)
105 #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */
106 #define SPCR_COREPR_SHIFT (31-11)
108 #if defined(CONFIG_MPC834X)
109 /* SPCR bits - MPC8349 specific */
110 #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */
111 #define SPCR_TSEC1DP_SHIFT (31-19)
112 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */
113 #define SPCR_TSEC1BDP_SHIFT (31-21)
114 #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */
115 #define SPCR_TSEC1EP_SHIFT (31-23)
116 #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */
117 #define SPCR_TSEC2DP_SHIFT (31-27)
118 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */
119 #define SPCR_TSEC2BDP_SHIFT (31-29)
120 #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */
121 #define SPCR_TSEC2EP_SHIFT (31-31)
124 /* SICRL/H - System I/O Configuration Register Low/High
126 #if defined(CONFIG_MPC834X)
127 /* SICRL bits - MPC8349 specific */
128 #define SICRL_LDP_A 0x80000000
129 #define SICRL_USB1 0x40000000
130 #define SICRL_USB0 0x20000000
131 #define SICRL_UART 0x0C000000
132 #define SICRL_GPIO1_A 0x02000000
133 #define SICRL_GPIO1_B 0x01000000
134 #define SICRL_GPIO1_C 0x00800000
135 #define SICRL_GPIO1_D 0x00400000
136 #define SICRL_GPIO1_E 0x00200000
137 #define SICRL_GPIO1_F 0x00180000
138 #define SICRL_GPIO1_G 0x00040000
139 #define SICRL_GPIO1_H 0x00020000
140 #define SICRL_GPIO1_I 0x00010000
141 #define SICRL_GPIO1_J 0x00008000
142 #define SICRL_GPIO1_K 0x00004000
143 #define SICRL_GPIO1_L 0x00003000
145 /* SICRH bits - MPC8349 specific */
146 #define SICRH_DDR 0x80000000
147 #define SICRH_TSEC1_A 0x10000000
148 #define SICRH_TSEC1_B 0x08000000
149 #define SICRH_TSEC1_C 0x04000000
150 #define SICRH_TSEC1_D 0x02000000
151 #define SICRH_TSEC1_E 0x01000000
152 #define SICRH_TSEC1_F 0x00800000
153 #define SICRH_TSEC2_A 0x00400000
154 #define SICRH_TSEC2_B 0x00200000
155 #define SICRH_TSEC2_C 0x00100000
156 #define SICRH_TSEC2_D 0x00080000
157 #define SICRH_TSEC2_E 0x00040000
158 #define SICRH_TSEC2_F 0x00020000
159 #define SICRH_TSEC2_G 0x00010000
160 #define SICRH_TSEC2_H 0x00008000
161 #define SICRH_GPIO2_A 0x00004000
162 #define SICRH_GPIO2_B 0x00002000
163 #define SICRH_GPIO2_C 0x00001000
164 #define SICRH_GPIO2_D 0x00000800
165 #define SICRH_GPIO2_E 0x00000400
166 #define SICRH_GPIO2_F 0x00000200
167 #define SICRH_GPIO2_G 0x00000180
168 #define SICRH_GPIO2_H 0x00000060
169 #define SICRH_TSOBI1 0x00000002
170 #define SICRH_TSOBI2 0x00000001
172 #elif defined(CONFIG_MPC8360)
173 /* SICRL bits - MPC8360 specific */
174 #define SICRL_LDP_A 0xC0000000
175 #define SICRL_LCLK_1 0x10000000
176 #define SICRL_LCLK_2 0x08000000
177 #define SICRL_SRCID_A 0x03000000
178 #define SICRL_IRQ_CKSTP_A 0x00C00000
180 /* SICRH bits - MPC8360 specific */
181 #define SICRH_DDR 0x80000000
182 #define SICRH_SECONDARY_DDR 0x40000000
183 #define SICRH_SDDROE 0x20000000
184 #define SICRH_IRQ3 0x10000000
185 #define SICRH_UC1EOBI 0x00000004
186 #define SICRH_UC2E1OBI 0x00000002
187 #define SICRH_UC2E2OBI 0x00000001
189 #elif defined(CONFIG_MPC832X)
190 /* SICRL bits - MPC832X specific */
191 #define SICRL_LDP_LCS_A 0x80000000
192 #define SICRL_IRQ_CKS 0x20000000
193 #define SICRL_PCI_MSRC 0x10000000
194 #define SICRL_URT_CTPR 0x06000000
195 #define SICRL_IRQ_CTPR 0x00C00000
198 /* SWCRR - System Watchdog Control Register
200 #define SWCRR 0x0204 /* Register offset to immr */
201 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */
202 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */
203 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */
204 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */
205 #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
207 /* SWCNR - System Watchdog Counter Register
209 #define SWCNR 0x0208 /* Register offset to immr */
210 #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */
211 #define SWCNR_RES ~(SWCNR_SWCN)
213 /* SWSRR - System Watchdog Service Register
215 #define SWSRR 0x020E /* Register offset to immr */
217 /* ACR - Arbiter Configuration Register
219 #define ACR_COREDIS 0x10000000 /* Core disable */
220 #define ACR_COREDIS_SHIFT (31-7)
221 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
222 #define ACR_PIPE_DEP_SHIFT (31-15)
223 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
224 #define ACR_PCI_RPTCNT_SHIFT (31-19)
225 #define ACR_RPTCNT 0x00000700 /* Repeat count */
226 #define ACR_RPTCNT_SHIFT (31-23)
227 #define ACR_APARK 0x00000030 /* Address parking */
228 #define ACR_APARK_SHIFT (31-27)
229 #define ACR_PARKM 0x0000000F /* Parking master */
230 #define ACR_PARKM_SHIFT (31-31)
232 /* ATR - Arbiter Timers Register
234 #define ATR_DTO 0x00FF0000 /* Data time out */
235 #define ATR_ATO 0x000000FF /* Address time out */
237 /* AER - Arbiter Event Register
239 #define AER_ETEA 0x00000020 /* Transfer error */
240 #define AER_RES 0x00000010 /* Reserved transfer type */
241 #define AER_ECW 0x00000008 /* External control word transfer type */
242 #define AER_AO 0x00000004 /* Address Only transfer type */
243 #define AER_DTO 0x00000002 /* Data time out */
244 #define AER_ATO 0x00000001 /* Address time out */
246 /* AEATR - Arbiter Event Address Register
248 #define AEATR_EVENT 0x07000000 /* Event type */
249 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */
250 #define AEATR_TBST 0x00000800 /* Transfer burst */
251 #define AEATR_TSIZE 0x00000700 /* Transfer Size */
252 #define AEATR_TTYPE 0x0000001F /* Transfer Type */
254 /* HRCWL - Hard Reset Configuration Word Low
256 #define HRCWL_LBIUCM 0x80000000
257 #define HRCWL_LBIUCM_SHIFT 31
258 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
259 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
261 #define HRCWL_DDRCM 0x40000000
262 #define HRCWL_DDRCM_SHIFT 30
263 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
264 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
266 #define HRCWL_SPMF 0x0f000000
267 #define HRCWL_SPMF_SHIFT 24
268 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
269 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
270 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
271 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
272 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
273 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
274 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
275 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
276 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
277 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
278 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
279 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
280 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
281 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
282 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
283 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
285 #define HRCWL_VCO_BYPASS 0x00000000
286 #define HRCWL_VCO_1X2 0x00000000
287 #define HRCWL_VCO_1X4 0x00200000
288 #define HRCWL_VCO_1X8 0x00400000
290 #define HRCWL_COREPLL 0x007F0000
291 #define HRCWL_COREPLL_SHIFT 16
292 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
293 #define HRCWL_CORE_TO_CSB_1X1 0x00020000
294 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
295 #define HRCWL_CORE_TO_CSB_2X1 0x00040000
296 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
297 #define HRCWL_CORE_TO_CSB_3X1 0x00060000
299 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
300 #define HRCWL_CEVCOD 0x000000C0
301 #define HRCWL_CEVCOD_SHIFT 6
302 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
303 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
304 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
306 #define HRCWL_CEPDF 0x00000020
307 #define HRCWL_CEPDF_SHIFT 5
308 #define HRCWL_CE_PLL_DIV_1X1 0x00000000
309 #define HRCWL_CE_PLL_DIV_2X1 0x00000020
311 #define HRCWL_CEPMF 0x0000001F
312 #define HRCWL_CEPMF_SHIFT 0
313 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000
314 #define HRCWL_CE_TO_PLL_1X2 0x00000002
315 #define HRCWL_CE_TO_PLL_1X3 0x00000003
316 #define HRCWL_CE_TO_PLL_1X4 0x00000004
317 #define HRCWL_CE_TO_PLL_1X5 0x00000005
318 #define HRCWL_CE_TO_PLL_1X6 0x00000006
319 #define HRCWL_CE_TO_PLL_1X7 0x00000007
320 #define HRCWL_CE_TO_PLL_1X8 0x00000008
321 #define HRCWL_CE_TO_PLL_1X9 0x00000009
322 #define HRCWL_CE_TO_PLL_1X10 0x0000000A
323 #define HRCWL_CE_TO_PLL_1X11 0x0000000B
324 #define HRCWL_CE_TO_PLL_1X12 0x0000000C
325 #define HRCWL_CE_TO_PLL_1X13 0x0000000D
326 #define HRCWL_CE_TO_PLL_1X14 0x0000000E
327 #define HRCWL_CE_TO_PLL_1X15 0x0000000F
328 #define HRCWL_CE_TO_PLL_1X16 0x00000010
329 #define HRCWL_CE_TO_PLL_1X17 0x00000011
330 #define HRCWL_CE_TO_PLL_1X18 0x00000012
331 #define HRCWL_CE_TO_PLL_1X19 0x00000013
332 #define HRCWL_CE_TO_PLL_1X20 0x00000014
333 #define HRCWL_CE_TO_PLL_1X21 0x00000015
334 #define HRCWL_CE_TO_PLL_1X22 0x00000016
335 #define HRCWL_CE_TO_PLL_1X23 0x00000017
336 #define HRCWL_CE_TO_PLL_1X24 0x00000018
337 #define HRCWL_CE_TO_PLL_1X25 0x00000019
338 #define HRCWL_CE_TO_PLL_1X26 0x0000001A
339 #define HRCWL_CE_TO_PLL_1X27 0x0000001B
340 #define HRCWL_CE_TO_PLL_1X28 0x0000001C
341 #define HRCWL_CE_TO_PLL_1X29 0x0000001D
342 #define HRCWL_CE_TO_PLL_1X30 0x0000001E
343 #define HRCWL_CE_TO_PLL_1X31 0x0000001F
346 /* HRCWH - Hardware Reset Configuration Word High
348 #define HRCWH_PCI_HOST 0x80000000
349 #define HRCWH_PCI_HOST_SHIFT 31
350 #define HRCWH_PCI_AGENT 0x00000000
352 #if defined(CONFIG_MPC834X)
353 #define HRCWH_32_BIT_PCI 0x00000000
354 #define HRCWH_64_BIT_PCI 0x40000000
357 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
358 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
360 #define HRCWH_PCI_ARBITER_DISABLE 0x00000000
361 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000
363 #if defined(CONFIG_MPC834X)
364 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
365 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
367 #elif defined(CONFIG_MPC8360)
368 #define HRCWH_PCICKDRV_DISABLE 0x00000000
369 #define HRCWH_PCICKDRV_ENABLE 0x10000000
372 #define HRCWH_CORE_DISABLE 0x08000000
373 #define HRCWH_CORE_ENABLE 0x00000000
375 #define HRCWH_FROM_0X00000100 0x00000000
376 #define HRCWH_FROM_0XFFF00100 0x04000000
378 #define HRCWH_BOOTSEQ_DISABLE 0x00000000
379 #define HRCWH_BOOTSEQ_NORMAL 0x01000000
380 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000
382 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
383 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
385 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
386 #define HRCWH_ROM_LOC_PCI1 0x00100000
387 #if defined(CONFIG_MPC834X)
388 #define HRCWH_ROM_LOC_PCI2 0x00200000
390 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
391 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
392 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
394 #if defined(CONFIG_MPC834X)
395 #define HRCWH_TSEC1M_IN_RGMII 0x00000000
396 #define HRCWH_TSEC1M_IN_RTBI 0x00004000
397 #define HRCWH_TSEC1M_IN_GMII 0x00008000
398 #define HRCWH_TSEC1M_IN_TBI 0x0000C000
399 #define HRCWH_TSEC2M_IN_RGMII 0x00000000
400 #define HRCWH_TSEC2M_IN_RTBI 0x00001000
401 #define HRCWH_TSEC2M_IN_GMII 0x00002000
402 #define HRCWH_TSEC2M_IN_TBI 0x00003000
405 #if defined(CONFIG_MPC8360)
406 #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
407 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
410 #define HRCWH_BIG_ENDIAN 0x00000000
411 #define HRCWH_LITTLE_ENDIAN 0x00000008
413 #define HRCWH_LALE_NORMAL 0x00000000
414 #define HRCWH_LALE_EARLY 0x00000004
416 #define HRCWH_LDP_SET 0x00000000
417 #define HRCWH_LDP_CLEAR 0x00000002
419 /* RSR - Reset Status Register
421 #define RSR_RSTSRC 0xE0000000 /* Reset source */
422 #define RSR_RSTSRC_SHIFT 29
423 #define RSR_BSF 0x00010000 /* Boot seq. fail */
424 #define RSR_BSF_SHIFT 16
425 #define RSR_SWSR 0x00002000 /* software soft reset */
426 #define RSR_SWSR_SHIFT 13
427 #define RSR_SWHR 0x00001000 /* software hard reset */
428 #define RSR_SWHR_SHIFT 12
429 #define RSR_JHRS 0x00000200 /* jtag hreset */
430 #define RSR_JHRS_SHIFT 9
431 #define RSR_JSRS 0x00000100 /* jtag sreset status */
432 #define RSR_JSRS_SHIFT 8
433 #define RSR_CSHR 0x00000010 /* checkstop reset status */
434 #define RSR_CSHR_SHIFT 4
435 #define RSR_SWRS 0x00000008 /* software watchdog reset status */
436 #define RSR_SWRS_SHIFT 3
437 #define RSR_BMRS 0x00000004 /* bus monitop reset status */
438 #define RSR_BMRS_SHIFT 2
439 #define RSR_SRS 0x00000002 /* soft reset status */
440 #define RSR_SRS_SHIFT 1
441 #define RSR_HRS 0x00000001 /* hard reset status */
442 #define RSR_HRS_SHIFT 0
443 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\
444 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
445 RSR_BMRS | RSR_SRS | RSR_HRS)
446 /* RMR - Reset Mode Register
448 #define RMR_CSRE 0x00000001 /* checkstop reset enable */
449 #define RMR_CSRE_SHIFT 0
450 #define RMR_RES ~(RMR_CSRE)
452 /* RCR - Reset Control Register
454 #define RCR_SWHR 0x00000002 /* software hard reset */
455 #define RCR_SWSR 0x00000001 /* software soft reset */
456 #define RCR_RES ~(RCR_SWHR | RCR_SWSR)
458 /* RCER - Reset Control Enable Register
460 #define RCER_CRE 0x00000001 /* software hard reset */
461 #define RCER_RES ~(RCER_CRE)
463 /* SPMR - System PLL Mode Register
465 #define SPMR_LBIUCM 0x80000000
466 #define SPMR_DDRCM 0x40000000
467 #define SPMR_SPMF 0x0F000000
468 #define SPMR_CKID 0x00800000
469 #define SPMR_CKID_SHIFT 23
470 #define SPMR_COREPLL 0x007F0000
471 #define SPMR_CEVCOD 0x000000C0
472 #define SPMR_CEPDF 0x00000020
473 #define SPMR_CEPMF 0x0000001F
475 /* OCCR - Output Clock Control Register
477 #define OCCR_PCICOE0 0x80000000
478 #define OCCR_PCICOE1 0x40000000
479 #define OCCR_PCICOE2 0x20000000
480 #define OCCR_PCICOE3 0x10000000
481 #define OCCR_PCICOE4 0x08000000
482 #define OCCR_PCICOE5 0x04000000
483 #define OCCR_PCICOE6 0x02000000
484 #define OCCR_PCICOE7 0x01000000
485 #define OCCR_PCICD0 0x00800000
486 #define OCCR_PCICD1 0x00400000
487 #define OCCR_PCICD2 0x00200000
488 #define OCCR_PCICD3 0x00100000
489 #define OCCR_PCICD4 0x00080000
490 #define OCCR_PCICD5 0x00040000
491 #define OCCR_PCICD6 0x00020000
492 #define OCCR_PCICD7 0x00010000
493 #define OCCR_PCI1CR 0x00000002
494 #define OCCR_PCI2CR 0x00000001
495 #define OCCR_PCICR OCCR_PCI1CR
497 /* SCCR - System Clock Control Register
499 #define SCCR_ENCCM 0x03000000
500 #define SCCR_ENCCM_SHIFT 24
501 #define SCCR_ENCCM_0 0x00000000
502 #define SCCR_ENCCM_1 0x01000000
503 #define SCCR_ENCCM_2 0x02000000
504 #define SCCR_ENCCM_3 0x03000000
506 #define SCCR_PCICM 0x00010000
507 #define SCCR_PCICM_SHIFT 16
509 /* SCCR bits - MPC8349 specific */
510 #define SCCR_TSEC1CM 0xc0000000
511 #define SCCR_TSEC1CM_SHIFT 30
512 #define SCCR_TSEC1CM_0 0x00000000
513 #define SCCR_TSEC1CM_1 0x40000000
514 #define SCCR_TSEC1CM_2 0x80000000
515 #define SCCR_TSEC1CM_3 0xC0000000
517 #define SCCR_TSEC2CM 0x30000000
518 #define SCCR_TSEC2CM_SHIFT 28
519 #define SCCR_TSEC2CM_0 0x00000000
520 #define SCCR_TSEC2CM_1 0x10000000
521 #define SCCR_TSEC2CM_2 0x20000000
522 #define SCCR_TSEC2CM_3 0x30000000
524 #define SCCR_USBMPHCM 0x00c00000
525 #define SCCR_USBMPHCM_SHIFT 22
526 #define SCCR_USBDRCM 0x00300000
527 #define SCCR_USBDRCM_SHIFT 20
529 #define SCCR_USBCM_0 0x00000000
530 #define SCCR_USBCM_1 0x00500000
531 #define SCCR_USBCM_2 0x00A00000
532 #define SCCR_USBCM_3 0x00F00000
534 #define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \
539 #define SCCR_DEFAULT 0xFFFFFFFF
541 /* CSn_BDNS - Chip Select memory Bounds Register
543 #define CSBNDS_SA 0x00FF0000
544 #define CSBNDS_SA_SHIFT 8
545 #define CSBNDS_EA 0x000000FF
546 #define CSBNDS_EA_SHIFT 24
548 /* CSn_CONFIG - Chip Select Configuration Register
550 #define CSCONFIG_EN 0x80000000
551 #define CSCONFIG_AP 0x00800000
552 #define CSCONFIG_ROW_BIT 0x00000700
553 #define CSCONFIG_ROW_BIT_12 0x00000000
554 #define CSCONFIG_ROW_BIT_13 0x00000100
555 #define CSCONFIG_ROW_BIT_14 0x00000200
556 #define CSCONFIG_COL_BIT 0x00000007
557 #define CSCONFIG_COL_BIT_8 0x00000000
558 #define CSCONFIG_COL_BIT_9 0x00000001
559 #define CSCONFIG_COL_BIT_10 0x00000002
560 #define CSCONFIG_COL_BIT_11 0x00000003
562 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
564 #define TIMING_CFG1_PRETOACT 0x70000000
565 #define TIMING_CFG1_PRETOACT_SHIFT 28
566 #define TIMING_CFG1_ACTTOPRE 0x0F000000
567 #define TIMING_CFG1_ACTTOPRE_SHIFT 24
568 #define TIMING_CFG1_ACTTORW 0x00700000
569 #define TIMING_CFG1_ACTTORW_SHIFT 20
570 #define TIMING_CFG1_CASLAT 0x00070000
571 #define TIMING_CFG1_CASLAT_SHIFT 16
572 #define TIMING_CFG1_REFREC 0x0000F000
573 #define TIMING_CFG1_REFREC_SHIFT 12
574 #define TIMING_CFG1_WRREC 0x00000700
575 #define TIMING_CFG1_WRREC_SHIFT 8
576 #define TIMING_CFG1_ACTTOACT 0x00000070
577 #define TIMING_CFG1_ACTTOACT_SHIFT 4
578 #define TIMING_CFG1_WRTORD 0x00000007
579 #define TIMING_CFG1_WRTORD_SHIFT 0
580 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
581 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
583 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
585 #define TIMING_CFG2_CPO 0x0F800000
586 #define TIMING_CFG2_CPO_SHIFT 23
587 #define TIMING_CFG2_ACSM 0x00080000
588 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
589 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
590 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
592 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
594 #define SDRAM_CFG_MEM_EN 0x80000000
595 #define SDRAM_CFG_SREN 0x40000000
596 #define SDRAM_CFG_ECC_EN 0x20000000
597 #define SDRAM_CFG_RD_EN 0x10000000
598 #define SDRAM_CFG_SDRAM_TYPE 0x03000000
599 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
600 #define SDRAM_CFG_DYN_PWR 0x00200000
601 #define SDRAM_CFG_32_BE 0x00080000
602 #define SDRAM_CFG_8_BE 0x00040000
603 #define SDRAM_CFG_NCAP 0x00020000
604 #define SDRAM_CFG_2T_EN 0x00008000
605 #define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
607 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register
609 #define SDRAM_MODE_ESD 0xFFFF0000
610 #define SDRAM_MODE_ESD_SHIFT 16
611 #define SDRAM_MODE_SD 0x0000FFFF
612 #define SDRAM_MODE_SD_SHIFT 0
613 #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
614 #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
615 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
616 #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
617 #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
618 #define DDR_MODE_WEAK 0x0002 /* weak drivers */
619 #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
620 #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
621 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
622 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
623 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
624 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
625 #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
626 #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
627 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
628 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
629 #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */
630 #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
631 #define DDR_MODE_MODEREG 0x0000 /* select mode register */
633 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
635 #define SDRAM_INTERVAL_REFINT 0x3FFF0000
636 #define SDRAM_INTERVAL_REFINT_SHIFT 16
637 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
638 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
640 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
642 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
643 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
644 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
645 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
646 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
648 /* ECC_ERR_INJECT - Memory data path error injection mask ECC
650 #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */
651 #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */
652 #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */
653 #define ECC_ERR_INJECT_EEIM_SHIFT 0
655 /* CAPTURE_ECC - Memory data path read capture ECC
657 #define CAPTURE_ECC_ECE (0xff000000>>24)
658 #define CAPTURE_ECC_ECE_SHIFT 0
660 /* ERR_DETECT - Memory error detect
662 #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */
663 #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */
664 #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */
665 #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */
667 /* ERR_DISABLE - Memory error disable
669 #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */
670 #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */
671 #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */
672 #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
673 ECC_ERROR_DISABLE_MBED)
674 /* ERR_INT_EN - Memory error interrupt enable
676 #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */
677 #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */
678 #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */
679 #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
681 /* CAPTURE_ATTRIBUTES - Memory error attributes capture
683 #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */
684 #define ECC_CAPT_ATTR_BNUM_SHIFT 28
685 #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */
686 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
687 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
688 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
689 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
690 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24
691 #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */
692 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
693 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
694 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
695 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
696 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
697 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
698 #define ECC_CAPT_ATTR_TSRC_I2C 0x9
699 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA
700 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD
701 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE
702 #define ECC_CAPT_ATTR_TSRC_DMA 0xF
703 #define ECC_CAPT_ATTR_TSRC_SHIFT 16
704 #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */
705 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1
706 #define ECC_CAPT_ATTR_TTYP_READ 0x2
707 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
708 #define ECC_CAPT_ATTR_TTYP_SHIFT 12
709 #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */
711 /* ERR_SBE - Single bit ECC memory error management
713 #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */
714 #define ECC_ERROR_MAN_SBET_SHIFT 16
715 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */
716 #define ECC_ERROR_MAN_SBEC_SHIFT 0
718 /* BR - Base Registers
720 #define BR0 0x5000 /* Register offset to immr */
729 #define BR_BA 0xFFFF8000
730 #define BR_BA_SHIFT 15
731 #define BR_PS 0x00001800
732 #define BR_PS_SHIFT 11
733 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
734 #define BR_PS_16 0x00001000 /* Port Size 16 bit */
735 #define BR_PS_32 0x00001800 /* Port Size 32 bit */
736 #define BR_DECC 0x00000600
737 #define BR_DECC_SHIFT 9
738 #define BR_WP 0x00000100
739 #define BR_WP_SHIFT 8
740 #define BR_MSEL 0x000000E0
741 #define BR_MSEL_SHIFT 5
742 #define BR_MS_GPCM 0x00000000 /* GPCM */
743 #define BR_MS_SDRAM 0x00000060 /* SDRAM */
744 #define BR_MS_UPMA 0x00000080 /* UPMA */
745 #define BR_MS_UPMB 0x000000A0 /* UPMB */
746 #define BR_MS_UPMC 0x000000C0 /* UPMC */
747 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
748 #define BR_ATOM 0x0000000C
749 #define BR_ATOM_SHIFT 2
751 #define BR_V 0x00000001
754 #if defined(CONFIG_MPC834X)
755 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
756 #elif defined(CONFIG_MPC8360)
757 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
760 /* OR - Option Registers
762 #define OR0 0x5004 /* Register offset to immr */
771 #define OR_GPCM_AM 0xFFFF8000
772 #define OR_GPCM_AM_SHIFT 15
773 #define OR_GPCM_BCTLD 0x00001000
774 #define OR_GPCM_BCTLD_SHIFT 12
775 #define OR_GPCM_CSNT 0x00000800
776 #define OR_GPCM_CSNT_SHIFT 11
777 #define OR_GPCM_ACS 0x00000600
778 #define OR_GPCM_ACS_SHIFT 9
779 #define OR_GPCM_ACS_0b10 0x00000400
780 #define OR_GPCM_ACS_0b11 0x00000600
781 #define OR_GPCM_XACS 0x00000100
782 #define OR_GPCM_XACS_SHIFT 8
783 #define OR_GPCM_SCY 0x000000F0
784 #define OR_GPCM_SCY_SHIFT 4
785 #define OR_GPCM_SCY_1 0x00000010
786 #define OR_GPCM_SCY_2 0x00000020
787 #define OR_GPCM_SCY_3 0x00000030
788 #define OR_GPCM_SCY_4 0x00000040
789 #define OR_GPCM_SCY_5 0x00000050
790 #define OR_GPCM_SCY_6 0x00000060
791 #define OR_GPCM_SCY_7 0x00000070
792 #define OR_GPCM_SCY_8 0x00000080
793 #define OR_GPCM_SCY_9 0x00000090
794 #define OR_GPCM_SCY_10 0x000000a0
795 #define OR_GPCM_SCY_11 0x000000b0
796 #define OR_GPCM_SCY_12 0x000000c0
797 #define OR_GPCM_SCY_13 0x000000d0
798 #define OR_GPCM_SCY_14 0x000000e0
799 #define OR_GPCM_SCY_15 0x000000f0
800 #define OR_GPCM_SETA 0x00000008
801 #define OR_GPCM_SETA_SHIFT 3
802 #define OR_GPCM_TRLX 0x00000004
803 #define OR_GPCM_TRLX_SHIFT 2
804 #define OR_GPCM_EHTR 0x00000002
805 #define OR_GPCM_EHTR_SHIFT 1
806 #define OR_GPCM_EAD 0x00000001
807 #define OR_GPCM_EAD_SHIFT 0
809 #define OR_UPM_AM 0xFFFF8000
810 #define OR_UPM_AM_SHIFT 15
811 #define OR_UPM_XAM 0x00006000
812 #define OR_UPM_XAM_SHIFT 13
813 #define OR_UPM_BCTLD 0x00001000
814 #define OR_UPM_BCTLD_SHIFT 12
815 #define OR_UPM_BI 0x00000100
816 #define OR_UPM_BI_SHIFT 8
817 #define OR_UPM_TRLX 0x00000004
818 #define OR_UPM_TRLX_SHIFT 2
819 #define OR_UPM_EHTR 0x00000002
820 #define OR_UPM_EHTR_SHIFT 1
821 #define OR_UPM_EAD 0x00000001
822 #define OR_UPM_EAD_SHIFT 0
824 #define OR_SDRAM_AM 0xFFFF8000
825 #define OR_SDRAM_AM_SHIFT 15
826 #define OR_SDRAM_XAM 0x00006000
827 #define OR_SDRAM_XAM_SHIFT 13
828 #define OR_SDRAM_COLS 0x00001C00
829 #define OR_SDRAM_COLS_SHIFT 10
830 #define OR_SDRAM_ROWS 0x000001C0
831 #define OR_SDRAM_ROWS_SHIFT 6
832 #define OR_SDRAM_PMSEL 0x00000020
833 #define OR_SDRAM_PMSEL_SHIFT 5
834 #define OR_SDRAM_EAD 0x00000001
835 #define OR_SDRAM_EAD_SHIFT 0
837 #define OR_AM_32KB 0xFFFF8000
838 #define OR_AM_64KB 0xFFFF0000
839 #define OR_AM_128KB 0xFFFE0000
840 #define OR_AM_256KB 0xFFFC0000
841 #define OR_AM_512KB 0xFFF80000
842 #define OR_AM_1MB 0xFFF00000
843 #define OR_AM_2MB 0xFFE00000
844 #define OR_AM_4MB 0xFFC00000
845 #define OR_AM_8MB 0xFF800000
846 #define OR_AM_16MB 0xFF000000
847 #define OR_AM_32MB 0xFE000000
848 #define OR_AM_64MB 0xFC000000
849 #define OR_AM_128MB 0xF8000000
850 #define OR_AM_256MB 0xF0000000
851 #define OR_AM_512MB 0xE0000000
852 #define OR_AM_1GB 0xC0000000
853 #define OR_AM_2GB 0x80000000
854 #define OR_AM_4GB 0x00000000
856 #define LBLAWAR_EN 0x80000000
857 #define LBLAWAR_4KB 0x0000000B
858 #define LBLAWAR_8KB 0x0000000C
859 #define LBLAWAR_16KB 0x0000000D
860 #define LBLAWAR_32KB 0x0000000E
861 #define LBLAWAR_64KB 0x0000000F
862 #define LBLAWAR_128KB 0x00000010
863 #define LBLAWAR_256KB 0x00000011
864 #define LBLAWAR_512KB 0x00000012
865 #define LBLAWAR_1MB 0x00000013
866 #define LBLAWAR_2MB 0x00000014
867 #define LBLAWAR_4MB 0x00000015
868 #define LBLAWAR_8MB 0x00000016
869 #define LBLAWAR_16MB 0x00000017
870 #define LBLAWAR_32MB 0x00000018
871 #define LBLAWAR_64MB 0x00000019
872 #define LBLAWAR_128MB 0x0000001A
873 #define LBLAWAR_256MB 0x0000001B
874 #define LBLAWAR_512MB 0x0000001C
875 #define LBLAWAR_1GB 0x0000001D
876 #define LBLAWAR_2GB 0x0000001E
878 /* LBCR - Local Bus Configuration Register
880 #define LBCR_LDIS 0x80000000
881 #define LBCR_LDIS_SHIFT 31
882 #define LBCR_BCTLC 0x00C00000
883 #define LBCR_BCTLC_SHIFT 22
884 #define LBCR_LPBSE 0x00020000
885 #define LBCR_LPBSE_SHIFT 17
886 #define LBCR_EPAR 0x00010000
887 #define LBCR_EPAR_SHIFT 16
888 #define LBCR_BMT 0x0000FF00
889 #define LBCR_BMT_SHIFT 8
891 /* LCRR - Clock Ratio Register
893 #define LCRR_DBYP 0x80000000
894 #define LCRR_DBYP_SHIFT 31
895 #define LCRR_BUFCMDC 0x30000000
896 #define LCRR_BUFCMDC_SHIFT 28
897 #define LCRR_BUFCMDC_1 0x10000000
898 #define LCRR_BUFCMDC_2 0x20000000
899 #define LCRR_BUFCMDC_3 0x30000000
900 #define LCRR_BUFCMDC_4 0x00000000
901 #define LCRR_ECL 0x03000000
902 #define LCRR_ECL_SHIFT 24
903 #define LCRR_ECL_4 0x00000000
904 #define LCRR_ECL_5 0x01000000
905 #define LCRR_ECL_6 0x02000000
906 #define LCRR_ECL_7 0x03000000
907 #define LCRR_EADC 0x00030000
908 #define LCRR_EADC_SHIFT 16
909 #define LCRR_EADC_1 0x00010000
910 #define LCRR_EADC_2 0x00020000
911 #define LCRR_EADC_3 0x00030000
912 #define LCRR_EADC_4 0x00000000
913 #define LCRR_CLKDIV 0x0000000F
914 #define LCRR_CLKDIV_SHIFT 0
915 #define LCRR_CLKDIV_2 0x00000002
916 #define LCRR_CLKDIV_4 0x00000004
917 #define LCRR_CLKDIV_8 0x00000008
919 /* DMAMR - DMA Mode Register
921 #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */
922 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */
923 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */
924 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */
925 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */
926 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */
927 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */
928 #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */
930 /* DMASR - DMA Status Register
932 #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */
933 #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */
935 /* CONFIG_ADDRESS - PCI Config Address Register
937 #define PCI_CONFIG_ADDRESS_EN 0x80000000
938 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16
939 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
940 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11
941 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
942 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8
943 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
944 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0
945 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
947 /* POTAR - PCI Outbound Translation Address Register
949 #define POTAR_TA_MASK 0x000fffff
951 /* POBAR - PCI Outbound Base Address Register
953 #define POBAR_BA_MASK 0x000fffff
955 /* POCMR - PCI Outbound Comparision Mask Register
957 #define POCMR_EN 0x80000000
958 #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */
959 #define POCMR_SE 0x20000000 /* streaming enable */
960 #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
961 #define POCMR_CM_MASK 0x000fffff
962 #define POCMR_CM_4G 0x00000000
963 #define POCMR_CM_2G 0x00080000
964 #define POCMR_CM_1G 0x000C0000
965 #define POCMR_CM_512M 0x000E0000
966 #define POCMR_CM_256M 0x000F0000
967 #define POCMR_CM_128M 0x000F8000
968 #define POCMR_CM_64M 0x000FC000
969 #define POCMR_CM_32M 0x000FE000
970 #define POCMR_CM_16M 0x000FF000
971 #define POCMR_CM_8M 0x000FF800
972 #define POCMR_CM_4M 0x000FFC00
973 #define POCMR_CM_2M 0x000FFE00
974 #define POCMR_CM_1M 0x000FFF00
975 #define POCMR_CM_512K 0x000FFF80
976 #define POCMR_CM_256K 0x000FFFC0
977 #define POCMR_CM_128K 0x000FFFE0
978 #define POCMR_CM_64K 0x000FFFF0
979 #define POCMR_CM_32K 0x000FFFF8
980 #define POCMR_CM_16K 0x000FFFFC
981 #define POCMR_CM_8K 0x000FFFFE
982 #define POCMR_CM_4K 0x000FFFFF
984 /* PITAR - PCI Inbound Translation Address Register
986 #define PITAR_TA_MASK 0x000fffff
988 /* PIBAR - PCI Inbound Base/Extended Address Register
990 #define PIBAR_MASK 0xffffffff
991 #define PIEBAR_EBA_MASK 0x000fffff
993 /* PIWAR - PCI Inbound Windows Attributes Register
995 #define PIWAR_EN 0x80000000
996 #define PIWAR_PF 0x20000000
997 #define PIWAR_RTT_MASK 0x000f0000
998 #define PIWAR_RTT_NO_SNOOP 0x00040000
999 #define PIWAR_RTT_SNOOP 0x00050000
1000 #define PIWAR_WTT_MASK 0x0000f000
1001 #define PIWAR_WTT_NO_SNOOP 0x00004000
1002 #define PIWAR_WTT_SNOOP 0x00005000
1003 #define PIWAR_IWS_MASK 0x0000003F
1004 #define PIWAR_IWS_4K 0x0000000B
1005 #define PIWAR_IWS_8K 0x0000000C
1006 #define PIWAR_IWS_16K 0x0000000D
1007 #define PIWAR_IWS_32K 0x0000000E
1008 #define PIWAR_IWS_64K 0x0000000F
1009 #define PIWAR_IWS_128K 0x00000010
1010 #define PIWAR_IWS_256K 0x00000011
1011 #define PIWAR_IWS_512K 0x00000012
1012 #define PIWAR_IWS_1M 0x00000013
1013 #define PIWAR_IWS_2M 0x00000014
1014 #define PIWAR_IWS_4M 0x00000015
1015 #define PIWAR_IWS_8M 0x00000016
1016 #define PIWAR_IWS_16M 0x00000017
1017 #define PIWAR_IWS_32M 0x00000018
1018 #define PIWAR_IWS_64M 0x00000019
1019 #define PIWAR_IWS_128M 0x0000001A
1020 #define PIWAR_IWS_256M 0x0000001B
1021 #define PIWAR_IWS_512M 0x0000001C
1022 #define PIWAR_IWS_1G 0x0000001D
1023 #define PIWAR_IWS_2G 0x0000001E
1025 #endif /* __MPC83XX_H__ */
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