2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
17 #if defined(CONFIG_E300)
21 /* MPC83xx cpu provide RCR register to do reset thing specially
25 /* System reset offset (PowerPC standard)
27 #define EXC_OFF_SYS_RESET 0x0100
29 /* IMMRBAR - Internal Memory Register Base Address
31 #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */
32 #define IMMRBAR 0x0000 /* Register offset to immr */
33 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */
34 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
36 /* LAWBAR - Local Access Window Base Address Register
38 #define LBLAWBAR0 0x0020 /* Register offset to immr */
39 #define LBLAWAR0 0x0024
40 #define LBLAWBAR1 0x0028
41 #define LBLAWAR1 0x002C
42 #define LBLAWBAR2 0x0030
43 #define LBLAWAR2 0x0034
44 #define LBLAWBAR3 0x0038
45 #define LBLAWAR3 0x003C
46 #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */
48 /* SPRIDR - System Part and Revision ID Register
50 #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
51 #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
53 #define SPR_8349E_REV10 0x80300100
54 #define SPR_8349_REV10 0x80310100
55 #define SPR_8347E_REV10_TBGA 0x80320100
56 #define SPR_8347_REV10_TBGA 0x80330100
57 #define SPR_8347E_REV10_PBGA 0x80340100
58 #define SPR_8347_REV10_PBGA 0x80350100
59 #define SPR_8343E_REV10 0x80360100
60 #define SPR_8343_REV10 0x80370100
62 #define SPR_8349E_REV11 0x80300101
63 #define SPR_8349_REV11 0x80310101
64 #define SPR_8347E_REV11_TBGA 0x80320101
65 #define SPR_8347_REV11_TBGA 0x80330101
66 #define SPR_8347E_REV11_PBGA 0x80340101
67 #define SPR_8347_REV11_PBGA 0x80350101
68 #define SPR_8343E_REV11 0x80360101
69 #define SPR_8343_REV11 0x80370101
71 #define SPR_8360E_REV10 0x80480010
72 #define SPR_8360_REV10 0x80490010
73 #define SPR_8360E_REV11 0x80480011
74 #define SPR_8360_REV11 0x80490011
75 #define SPR_8360E_REV12 0x80480012
76 #define SPR_8360_REV12 0x80490012
78 #define SPR_8323E_REV10 0x80620010
79 #define SPR_8323_REV10 0x80630010
80 #define SPR_8321E_REV10 0x80660010
81 #define SPR_8321_REV10 0x80670010
82 #define SPR_8323E_REV11 0x80620011
83 #define SPR_8323_REV11 0x80630011
84 #define SPR_8321E_REV11 0x80660011
85 #define SPR_8321_REV11 0x80670011
87 /* SPCR - System Priority Configuration Register
89 #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
90 #define SPCR_PCIHPE_SHIFT (31-3)
91 #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */
92 #define SPCR_PCIPR_SHIFT (31-7)
93 #define SPCR_OPT 0x00800000 /* Optimize */
94 #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */
95 #define SPCR_TBEN_SHIFT (31-9)
96 #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */
97 #define SPCR_COREPR_SHIFT (31-11)
99 #if defined(CONFIG_MPC834X)
100 /* SPCR bits - MPC8349 specific */
101 #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */
102 #define SPCR_TSEC1DP_SHIFT (31-19)
103 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */
104 #define SPCR_TSEC1BDP_SHIFT (31-21)
105 #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */
106 #define SPCR_TSEC1EP_SHIFT (31-23)
107 #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */
108 #define SPCR_TSEC2DP_SHIFT (31-27)
109 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */
110 #define SPCR_TSEC2BDP_SHIFT (31-29)
111 #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */
112 #define SPCR_TSEC2EP_SHIFT (31-31)
115 /* SICRL/H - System I/O Configuration Register Low/High
117 #if defined(CONFIG_MPC834X)
118 /* SICRL bits - MPC8349 specific */
119 #define SICRL_LDP_A 0x80000000
120 #define SICRL_USB1 0x40000000
121 #define SICRL_USB0 0x20000000
122 #define SICRL_UART 0x0C000000
123 #define SICRL_GPIO1_A 0x02000000
124 #define SICRL_GPIO1_B 0x01000000
125 #define SICRL_GPIO1_C 0x00800000
126 #define SICRL_GPIO1_D 0x00400000
127 #define SICRL_GPIO1_E 0x00200000
128 #define SICRL_GPIO1_F 0x00180000
129 #define SICRL_GPIO1_G 0x00040000
130 #define SICRL_GPIO1_H 0x00020000
131 #define SICRL_GPIO1_I 0x00010000
132 #define SICRL_GPIO1_J 0x00008000
133 #define SICRL_GPIO1_K 0x00004000
134 #define SICRL_GPIO1_L 0x00003000
136 /* SICRH bits - MPC8349 specific */
137 #define SICRH_DDR 0x80000000
138 #define SICRH_TSEC1_A 0x10000000
139 #define SICRH_TSEC1_B 0x08000000
140 #define SICRH_TSEC1_C 0x04000000
141 #define SICRH_TSEC1_D 0x02000000
142 #define SICRH_TSEC1_E 0x01000000
143 #define SICRH_TSEC1_F 0x00800000
144 #define SICRH_TSEC2_A 0x00400000
145 #define SICRH_TSEC2_B 0x00200000
146 #define SICRH_TSEC2_C 0x00100000
147 #define SICRH_TSEC2_D 0x00080000
148 #define SICRH_TSEC2_E 0x00040000
149 #define SICRH_TSEC2_F 0x00020000
150 #define SICRH_TSEC2_G 0x00010000
151 #define SICRH_TSEC2_H 0x00008000
152 #define SICRH_GPIO2_A 0x00004000
153 #define SICRH_GPIO2_B 0x00002000
154 #define SICRH_GPIO2_C 0x00001000
155 #define SICRH_GPIO2_D 0x00000800
156 #define SICRH_GPIO2_E 0x00000400
157 #define SICRH_GPIO2_F 0x00000200
158 #define SICRH_GPIO2_G 0x00000180
159 #define SICRH_GPIO2_H 0x00000060
160 #define SICRH_TSOBI1 0x00000002
161 #define SICRH_TSOBI2 0x00000001
163 #elif defined(CONFIG_MPC8360)
164 /* SICRL bits - MPC8360 specific */
165 #define SICRL_LDP_A 0xC0000000
166 #define SICRL_LCLK_1 0x10000000
167 #define SICRL_LCLK_2 0x08000000
168 #define SICRL_SRCID_A 0x03000000
169 #define SICRL_IRQ_CKSTP_A 0x00C00000
171 /* SICRH bits - MPC8360 specific */
172 #define SICRH_DDR 0x80000000
173 #define SICRH_SECONDARY_DDR 0x40000000
174 #define SICRH_SDDROE 0x20000000
175 #define SICRH_IRQ3 0x10000000
176 #define SICRH_UC1EOBI 0x00000004
177 #define SICRH_UC2E1OBI 0x00000002
178 #define SICRH_UC2E2OBI 0x00000001
180 #elif defined(CONFIG_MPC832X)
181 /* SICRL bits - MPC832X specific */
182 #define SICRL_LDP_LCS_A 0x80000000
183 #define SICRL_IRQ_CKS 0x20000000
184 #define SICRL_PCI_MSRC 0x10000000
185 #define SICRL_URT_CTPR 0x06000000
186 #define SICRL_IRQ_CTPR 0x00C00000
189 /* SWCRR - System Watchdog Control Register
191 #define SWCRR 0x0204 /* Register offset to immr */
192 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */
193 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */
194 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */
195 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */
196 #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
198 /* SWCNR - System Watchdog Counter Register
200 #define SWCNR 0x0208 /* Register offset to immr */
201 #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */
202 #define SWCNR_RES ~(SWCNR_SWCN)
204 /* SWSRR - System Watchdog Service Register
206 #define SWSRR 0x020E /* Register offset to immr */
208 /* ACR - Arbiter Configuration Register
210 #define ACR_COREDIS 0x10000000 /* Core disable */
211 #define ACR_COREDIS_SHIFT (31-7)
212 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
213 #define ACR_PIPE_DEP_SHIFT (31-15)
214 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
215 #define ACR_PCI_RPTCNT_SHIFT (31-19)
216 #define ACR_RPTCNT 0x00000700 /* Repeat count */
217 #define ACR_RPTCNT_SHIFT (31-23)
218 #define ACR_APARK 0x00000030 /* Address parking */
219 #define ACR_APARK_SHIFT (31-27)
220 #define ACR_PARKM 0x0000000F /* Parking master */
221 #define ACR_PARKM_SHIFT (31-31)
223 /* ATR - Arbiter Timers Register
225 #define ATR_DTO 0x00FF0000 /* Data time out */
226 #define ATR_ATO 0x000000FF /* Address time out */
228 /* AER - Arbiter Event Register
230 #define AER_ETEA 0x00000020 /* Transfer error */
231 #define AER_RES 0x00000010 /* Reserved transfer type */
232 #define AER_ECW 0x00000008 /* External control word transfer type */
233 #define AER_AO 0x00000004 /* Address Only transfer type */
234 #define AER_DTO 0x00000002 /* Data time out */
235 #define AER_ATO 0x00000001 /* Address time out */
237 /* AEATR - Arbiter Event Address Register
239 #define AEATR_EVENT 0x07000000 /* Event type */
240 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */
241 #define AEATR_TBST 0x00000800 /* Transfer burst */
242 #define AEATR_TSIZE 0x00000700 /* Transfer Size */
243 #define AEATR_TTYPE 0x0000001F /* Transfer Type */
245 /* HRCWL - Hard Reset Configuration Word Low
247 #define HRCWL_LBIUCM 0x80000000
248 #define HRCWL_LBIUCM_SHIFT 31
249 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
250 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
252 #define HRCWL_DDRCM 0x40000000
253 #define HRCWL_DDRCM_SHIFT 30
254 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
255 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
257 #define HRCWL_SPMF 0x0f000000
258 #define HRCWL_SPMF_SHIFT 24
259 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
260 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
261 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
262 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
263 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
264 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
265 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
266 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
267 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
268 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
269 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
270 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
271 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
272 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
273 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
274 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
276 #define HRCWL_VCO_BYPASS 0x00000000
277 #define HRCWL_VCO_1X2 0x00000000
278 #define HRCWL_VCO_1X4 0x00200000
279 #define HRCWL_VCO_1X8 0x00400000
281 #define HRCWL_COREPLL 0x007F0000
282 #define HRCWL_COREPLL_SHIFT 16
283 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
284 #define HRCWL_CORE_TO_CSB_1X1 0x00020000
285 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
286 #define HRCWL_CORE_TO_CSB_2X1 0x00040000
287 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
288 #define HRCWL_CORE_TO_CSB_3X1 0x00060000
290 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
291 #define HRCWL_CEVCOD 0x000000C0
292 #define HRCWL_CEVCOD_SHIFT 6
293 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
294 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
295 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
297 #define HRCWL_CEPDF 0x00000020
298 #define HRCWL_CEPDF_SHIFT 5
299 #define HRCWL_CE_PLL_DIV_1X1 0x00000000
300 #define HRCWL_CE_PLL_DIV_2X1 0x00000020
302 #define HRCWL_CEPMF 0x0000001F
303 #define HRCWL_CEPMF_SHIFT 0
304 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000
305 #define HRCWL_CE_TO_PLL_1X2 0x00000002
306 #define HRCWL_CE_TO_PLL_1X3 0x00000003
307 #define HRCWL_CE_TO_PLL_1X4 0x00000004
308 #define HRCWL_CE_TO_PLL_1X5 0x00000005
309 #define HRCWL_CE_TO_PLL_1X6 0x00000006
310 #define HRCWL_CE_TO_PLL_1X7 0x00000007
311 #define HRCWL_CE_TO_PLL_1X8 0x00000008
312 #define HRCWL_CE_TO_PLL_1X9 0x00000009
313 #define HRCWL_CE_TO_PLL_1X10 0x0000000A
314 #define HRCWL_CE_TO_PLL_1X11 0x0000000B
315 #define HRCWL_CE_TO_PLL_1X12 0x0000000C
316 #define HRCWL_CE_TO_PLL_1X13 0x0000000D
317 #define HRCWL_CE_TO_PLL_1X14 0x0000000E
318 #define HRCWL_CE_TO_PLL_1X15 0x0000000F
319 #define HRCWL_CE_TO_PLL_1X16 0x00000010
320 #define HRCWL_CE_TO_PLL_1X17 0x00000011
321 #define HRCWL_CE_TO_PLL_1X18 0x00000012
322 #define HRCWL_CE_TO_PLL_1X19 0x00000013
323 #define HRCWL_CE_TO_PLL_1X20 0x00000014
324 #define HRCWL_CE_TO_PLL_1X21 0x00000015
325 #define HRCWL_CE_TO_PLL_1X22 0x00000016
326 #define HRCWL_CE_TO_PLL_1X23 0x00000017
327 #define HRCWL_CE_TO_PLL_1X24 0x00000018
328 #define HRCWL_CE_TO_PLL_1X25 0x00000019
329 #define HRCWL_CE_TO_PLL_1X26 0x0000001A
330 #define HRCWL_CE_TO_PLL_1X27 0x0000001B
331 #define HRCWL_CE_TO_PLL_1X28 0x0000001C
332 #define HRCWL_CE_TO_PLL_1X29 0x0000001D
333 #define HRCWL_CE_TO_PLL_1X30 0x0000001E
334 #define HRCWL_CE_TO_PLL_1X31 0x0000001F
337 /* HRCWH - Hardware Reset Configuration Word High
339 #define HRCWH_PCI_HOST 0x80000000
340 #define HRCWH_PCI_HOST_SHIFT 31
341 #define HRCWH_PCI_AGENT 0x00000000
343 #if defined(CONFIG_MPC834X)
344 #define HRCWH_32_BIT_PCI 0x00000000
345 #define HRCWH_64_BIT_PCI 0x40000000
348 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
349 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
351 #define HRCWH_PCI_ARBITER_DISABLE 0x00000000
352 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000
354 #if defined(CONFIG_MPC834X)
355 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
356 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
358 #elif defined(CONFIG_MPC8360)
359 #define HRCWH_PCICKDRV_DISABLE 0x00000000
360 #define HRCWH_PCICKDRV_ENABLE 0x10000000
363 #define HRCWH_CORE_DISABLE 0x08000000
364 #define HRCWH_CORE_ENABLE 0x00000000
366 #define HRCWH_FROM_0X00000100 0x00000000
367 #define HRCWH_FROM_0XFFF00100 0x04000000
369 #define HRCWH_BOOTSEQ_DISABLE 0x00000000
370 #define HRCWH_BOOTSEQ_NORMAL 0x01000000
371 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000
373 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
374 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
376 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
377 #define HRCWH_ROM_LOC_PCI1 0x00100000
378 #if defined(CONFIG_MPC834X)
379 #define HRCWH_ROM_LOC_PCI2 0x00200000
381 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
382 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
383 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
385 #if defined(CONFIG_MPC834X)
386 #define HRCWH_TSEC1M_IN_RGMII 0x00000000
387 #define HRCWH_TSEC1M_IN_RTBI 0x00004000
388 #define HRCWH_TSEC1M_IN_GMII 0x00008000
389 #define HRCWH_TSEC1M_IN_TBI 0x0000C000
390 #define HRCWH_TSEC2M_IN_RGMII 0x00000000
391 #define HRCWH_TSEC2M_IN_RTBI 0x00001000
392 #define HRCWH_TSEC2M_IN_GMII 0x00002000
393 #define HRCWH_TSEC2M_IN_TBI 0x00003000
396 #if defined(CONFIG_MPC8360)
397 #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
398 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
401 #define HRCWH_BIG_ENDIAN 0x00000000
402 #define HRCWH_LITTLE_ENDIAN 0x00000008
404 #define HRCWH_LALE_NORMAL 0x00000000
405 #define HRCWH_LALE_EARLY 0x00000004
407 #define HRCWH_LDP_SET 0x00000000
408 #define HRCWH_LDP_CLEAR 0x00000002
410 /* RSR - Reset Status Register
412 #define RSR_RSTSRC 0xE0000000 /* Reset source */
413 #define RSR_RSTSRC_SHIFT 29
414 #define RSR_BSF 0x00010000 /* Boot seq. fail */
415 #define RSR_BSF_SHIFT 16
416 #define RSR_SWSR 0x00002000 /* software soft reset */
417 #define RSR_SWSR_SHIFT 13
418 #define RSR_SWHR 0x00001000 /* software hard reset */
419 #define RSR_SWHR_SHIFT 12
420 #define RSR_JHRS 0x00000200 /* jtag hreset */
421 #define RSR_JHRS_SHIFT 9
422 #define RSR_JSRS 0x00000100 /* jtag sreset status */
423 #define RSR_JSRS_SHIFT 8
424 #define RSR_CSHR 0x00000010 /* checkstop reset status */
425 #define RSR_CSHR_SHIFT 4
426 #define RSR_SWRS 0x00000008 /* software watchdog reset status */
427 #define RSR_SWRS_SHIFT 3
428 #define RSR_BMRS 0x00000004 /* bus monitop reset status */
429 #define RSR_BMRS_SHIFT 2
430 #define RSR_SRS 0x00000002 /* soft reset status */
431 #define RSR_SRS_SHIFT 1
432 #define RSR_HRS 0x00000001 /* hard reset status */
433 #define RSR_HRS_SHIFT 0
434 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\
435 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
436 RSR_BMRS | RSR_SRS | RSR_HRS)
437 /* RMR - Reset Mode Register
439 #define RMR_CSRE 0x00000001 /* checkstop reset enable */
440 #define RMR_CSRE_SHIFT 0
441 #define RMR_RES ~(RMR_CSRE)
443 /* RCR - Reset Control Register
445 #define RCR_SWHR 0x00000002 /* software hard reset */
446 #define RCR_SWSR 0x00000001 /* software soft reset */
447 #define RCR_RES ~(RCR_SWHR | RCR_SWSR)
449 /* RCER - Reset Control Enable Register
451 #define RCER_CRE 0x00000001 /* software hard reset */
452 #define RCER_RES ~(RCER_CRE)
454 /* SPMR - System PLL Mode Register
456 #define SPMR_LBIUCM 0x80000000
457 #define SPMR_DDRCM 0x40000000
458 #define SPMR_SPMF 0x0F000000
459 #define SPMR_CKID 0x00800000
460 #define SPMR_CKID_SHIFT 23
461 #define SPMR_COREPLL 0x007F0000
462 #define SPMR_CEVCOD 0x000000C0
463 #define SPMR_CEPDF 0x00000020
464 #define SPMR_CEPMF 0x0000001F
466 /* OCCR - Output Clock Control Register
468 #define OCCR_PCICOE0 0x80000000
469 #define OCCR_PCICOE1 0x40000000
470 #define OCCR_PCICOE2 0x20000000
471 #define OCCR_PCICOE3 0x10000000
472 #define OCCR_PCICOE4 0x08000000
473 #define OCCR_PCICOE5 0x04000000
474 #define OCCR_PCICOE6 0x02000000
475 #define OCCR_PCICOE7 0x01000000
476 #define OCCR_PCICD0 0x00800000
477 #define OCCR_PCICD1 0x00400000
478 #define OCCR_PCICD2 0x00200000
479 #define OCCR_PCICD3 0x00100000
480 #define OCCR_PCICD4 0x00080000
481 #define OCCR_PCICD5 0x00040000
482 #define OCCR_PCICD6 0x00020000
483 #define OCCR_PCICD7 0x00010000
484 #define OCCR_PCI1CR 0x00000002
485 #define OCCR_PCI2CR 0x00000001
486 #define OCCR_PCICR OCCR_PCI1CR
488 /* SCCR - System Clock Control Register
490 #define SCCR_ENCCM 0x03000000
491 #define SCCR_ENCCM_SHIFT 24
492 #define SCCR_ENCCM_0 0x00000000
493 #define SCCR_ENCCM_1 0x01000000
494 #define SCCR_ENCCM_2 0x02000000
495 #define SCCR_ENCCM_3 0x03000000
497 #define SCCR_PCICM 0x00010000
498 #define SCCR_PCICM_SHIFT 16
500 /* SCCR bits - MPC8349 specific */
501 #define SCCR_TSEC1CM 0xc0000000
502 #define SCCR_TSEC1CM_SHIFT 30
503 #define SCCR_TSEC1CM_0 0x00000000
504 #define SCCR_TSEC1CM_1 0x40000000
505 #define SCCR_TSEC1CM_2 0x80000000
506 #define SCCR_TSEC1CM_3 0xC0000000
508 #define SCCR_TSEC2CM 0x30000000
509 #define SCCR_TSEC2CM_SHIFT 28
510 #define SCCR_TSEC2CM_0 0x00000000
511 #define SCCR_TSEC2CM_1 0x10000000
512 #define SCCR_TSEC2CM_2 0x20000000
513 #define SCCR_TSEC2CM_3 0x30000000
515 #define SCCR_USBMPHCM 0x00c00000
516 #define SCCR_USBMPHCM_SHIFT 22
517 #define SCCR_USBDRCM 0x00300000
518 #define SCCR_USBDRCM_SHIFT 20
520 #define SCCR_USBCM_0 0x00000000
521 #define SCCR_USBCM_1 0x00500000
522 #define SCCR_USBCM_2 0x00A00000
523 #define SCCR_USBCM_3 0x00F00000
525 #define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \
530 #define SCCR_DEFAULT 0xFFFFFFFF
532 /* CSn_BDNS - Chip Select memory Bounds Register
534 #define CSBNDS_SA 0x00FF0000
535 #define CSBNDS_SA_SHIFT 8
536 #define CSBNDS_EA 0x000000FF
537 #define CSBNDS_EA_SHIFT 24
539 /* CSn_CONFIG - Chip Select Configuration Register
541 #define CSCONFIG_EN 0x80000000
542 #define CSCONFIG_AP 0x00800000
543 #define CSCONFIG_ROW_BIT 0x00000700
544 #define CSCONFIG_ROW_BIT_12 0x00000000
545 #define CSCONFIG_ROW_BIT_13 0x00000100
546 #define CSCONFIG_ROW_BIT_14 0x00000200
547 #define CSCONFIG_COL_BIT 0x00000007
548 #define CSCONFIG_COL_BIT_8 0x00000000
549 #define CSCONFIG_COL_BIT_9 0x00000001
550 #define CSCONFIG_COL_BIT_10 0x00000002
551 #define CSCONFIG_COL_BIT_11 0x00000003
553 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
555 #define TIMING_CFG1_PRETOACT 0x70000000
556 #define TIMING_CFG1_PRETOACT_SHIFT 28
557 #define TIMING_CFG1_ACTTOPRE 0x0F000000
558 #define TIMING_CFG1_ACTTOPRE_SHIFT 24
559 #define TIMING_CFG1_ACTTORW 0x00700000
560 #define TIMING_CFG1_ACTTORW_SHIFT 20
561 #define TIMING_CFG1_CASLAT 0x00070000
562 #define TIMING_CFG1_CASLAT_SHIFT 16
563 #define TIMING_CFG1_REFREC 0x0000F000
564 #define TIMING_CFG1_REFREC_SHIFT 12
565 #define TIMING_CFG1_WRREC 0x00000700
566 #define TIMING_CFG1_WRREC_SHIFT 8
567 #define TIMING_CFG1_ACTTOACT 0x00000070
568 #define TIMING_CFG1_ACTTOACT_SHIFT 4
569 #define TIMING_CFG1_WRTORD 0x00000007
570 #define TIMING_CFG1_WRTORD_SHIFT 0
571 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
572 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
574 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
576 #define TIMING_CFG2_CPO 0x0F000000
577 #define TIMING_CFG2_CPO_SHIFT 24
578 #define TIMING_CFG2_ACSM 0x00080000
579 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
580 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
581 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
583 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
585 #define SDRAM_CFG_MEM_EN 0x80000000
586 #define SDRAM_CFG_SREN 0x40000000
587 #define SDRAM_CFG_ECC_EN 0x20000000
588 #define SDRAM_CFG_RD_EN 0x10000000
589 #define SDRAM_CFG_SDRAM_TYPE 0x03000000
590 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
591 #define SDRAM_CFG_DYN_PWR 0x00200000
592 #define SDRAM_CFG_32_BE 0x00080000
593 #define SDRAM_CFG_8_BE 0x00040000
594 #define SDRAM_CFG_NCAP 0x00020000
595 #define SDRAM_CFG_2T_EN 0x00008000
596 #define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
598 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register
600 #define SDRAM_MODE_ESD 0xFFFF0000
601 #define SDRAM_MODE_ESD_SHIFT 16
602 #define SDRAM_MODE_SD 0x0000FFFF
603 #define SDRAM_MODE_SD_SHIFT 0
604 #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
605 #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
606 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
607 #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
608 #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
609 #define DDR_MODE_WEAK 0x0002 /* weak drivers */
610 #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
611 #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
612 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
613 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
614 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
615 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
616 #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
617 #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
618 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
619 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
620 #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */
621 #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
622 #define DDR_MODE_MODEREG 0x0000 /* select mode register */
624 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
626 #define SDRAM_INTERVAL_REFINT 0x3FFF0000
627 #define SDRAM_INTERVAL_REFINT_SHIFT 16
628 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
629 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
631 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
633 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
634 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
635 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
636 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
637 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
639 /* ECC_ERR_INJECT - Memory data path error injection mask ECC
641 #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */
642 #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */
643 #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */
644 #define ECC_ERR_INJECT_EEIM_SHIFT 0
646 /* CAPTURE_ECC - Memory data path read capture ECC
648 #define CAPTURE_ECC_ECE (0xff000000>>24)
649 #define CAPTURE_ECC_ECE_SHIFT 0
651 /* ERR_DETECT - Memory error detect
653 #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */
654 #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */
655 #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */
656 #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */
658 /* ERR_DISABLE - Memory error disable
660 #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */
661 #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */
662 #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */
663 #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
664 ECC_ERROR_DISABLE_MBED)
665 /* ERR_INT_EN - Memory error interrupt enable
667 #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */
668 #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */
669 #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */
670 #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
672 /* CAPTURE_ATTRIBUTES - Memory error attributes capture
674 #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */
675 #define ECC_CAPT_ATTR_BNUM_SHIFT 28
676 #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */
677 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
678 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
679 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
680 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
681 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24
682 #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */
683 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
684 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
685 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
686 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
687 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
688 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
689 #define ECC_CAPT_ATTR_TSRC_I2C 0x9
690 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA
691 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD
692 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE
693 #define ECC_CAPT_ATTR_TSRC_DMA 0xF
694 #define ECC_CAPT_ATTR_TSRC_SHIFT 16
695 #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */
696 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1
697 #define ECC_CAPT_ATTR_TTYP_READ 0x2
698 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
699 #define ECC_CAPT_ATTR_TTYP_SHIFT 12
700 #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */
702 /* ERR_SBE - Single bit ECC memory error management
704 #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */
705 #define ECC_ERROR_MAN_SBET_SHIFT 16
706 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */
707 #define ECC_ERROR_MAN_SBEC_SHIFT 0
709 /* BR - Base Registers
711 #define BR0 0x5000 /* Register offset to immr */
720 #define BR_BA 0xFFFF8000
721 #define BR_BA_SHIFT 15
722 #define BR_PS 0x00001800
723 #define BR_PS_SHIFT 11
724 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
725 #define BR_PS_16 0x00001000 /* Port Size 16 bit */
726 #define BR_PS_32 0x00001800 /* Port Size 32 bit */
727 #define BR_DECC 0x00000600
728 #define BR_DECC_SHIFT 9
729 #define BR_WP 0x00000100
730 #define BR_WP_SHIFT 8
731 #define BR_MSEL 0x000000E0
732 #define BR_MSEL_SHIFT 5
733 #define BR_MS_GPCM 0x00000000 /* GPCM */
734 #define BR_MS_SDRAM 0x00000060 /* SDRAM */
735 #define BR_MS_UPMA 0x00000080 /* UPMA */
736 #define BR_MS_UPMB 0x000000A0 /* UPMB */
737 #define BR_MS_UPMC 0x000000C0 /* UPMC */
738 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
739 #define BR_ATOM 0x0000000C
740 #define BR_ATOM_SHIFT 2
742 #define BR_V 0x00000001
745 #if defined(CONFIG_MPC834X)
746 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
747 #elif defined(CONFIG_MPC8360)
748 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
751 /* OR - Option Registers
753 #define OR0 0x5004 /* Register offset to immr */
762 #define OR_GPCM_AM 0xFFFF8000
763 #define OR_GPCM_AM_SHIFT 15
764 #define OR_GPCM_BCTLD 0x00001000
765 #define OR_GPCM_BCTLD_SHIFT 12
766 #define OR_GPCM_CSNT 0x00000800
767 #define OR_GPCM_CSNT_SHIFT 11
768 #define OR_GPCM_ACS 0x00000600
769 #define OR_GPCM_ACS_SHIFT 9
770 #define OR_GPCM_ACS_0b10 0x00000400
771 #define OR_GPCM_ACS_0b11 0x00000600
772 #define OR_GPCM_XACS 0x00000100
773 #define OR_GPCM_XACS_SHIFT 8
774 #define OR_GPCM_SCY 0x000000F0
775 #define OR_GPCM_SCY_SHIFT 4
776 #define OR_GPCM_SCY_1 0x00000010
777 #define OR_GPCM_SCY_2 0x00000020
778 #define OR_GPCM_SCY_3 0x00000030
779 #define OR_GPCM_SCY_4 0x00000040
780 #define OR_GPCM_SCY_5 0x00000050
781 #define OR_GPCM_SCY_6 0x00000060
782 #define OR_GPCM_SCY_7 0x00000070
783 #define OR_GPCM_SCY_8 0x00000080
784 #define OR_GPCM_SCY_9 0x00000090
785 #define OR_GPCM_SCY_10 0x000000a0
786 #define OR_GPCM_SCY_11 0x000000b0
787 #define OR_GPCM_SCY_12 0x000000c0
788 #define OR_GPCM_SCY_13 0x000000d0
789 #define OR_GPCM_SCY_14 0x000000e0
790 #define OR_GPCM_SCY_15 0x000000f0
791 #define OR_GPCM_SETA 0x00000008
792 #define OR_GPCM_SETA_SHIFT 3
793 #define OR_GPCM_TRLX 0x00000004
794 #define OR_GPCM_TRLX_SHIFT 2
795 #define OR_GPCM_EHTR 0x00000002
796 #define OR_GPCM_EHTR_SHIFT 1
797 #define OR_GPCM_EAD 0x00000001
798 #define OR_GPCM_EAD_SHIFT 0
800 #define OR_UPM_AM 0xFFFF8000
801 #define OR_UPM_AM_SHIFT 15
802 #define OR_UPM_XAM 0x00006000
803 #define OR_UPM_XAM_SHIFT 13
804 #define OR_UPM_BCTLD 0x00001000
805 #define OR_UPM_BCTLD_SHIFT 12
806 #define OR_UPM_BI 0x00000100
807 #define OR_UPM_BI_SHIFT 8
808 #define OR_UPM_TRLX 0x00000004
809 #define OR_UPM_TRLX_SHIFT 2
810 #define OR_UPM_EHTR 0x00000002
811 #define OR_UPM_EHTR_SHIFT 1
812 #define OR_UPM_EAD 0x00000001
813 #define OR_UPM_EAD_SHIFT 0
815 #define OR_SDRAM_AM 0xFFFF8000
816 #define OR_SDRAM_AM_SHIFT 15
817 #define OR_SDRAM_XAM 0x00006000
818 #define OR_SDRAM_XAM_SHIFT 13
819 #define OR_SDRAM_COLS 0x00001C00
820 #define OR_SDRAM_COLS_SHIFT 10
821 #define OR_SDRAM_ROWS 0x000001C0
822 #define OR_SDRAM_ROWS_SHIFT 6
823 #define OR_SDRAM_PMSEL 0x00000020
824 #define OR_SDRAM_PMSEL_SHIFT 5
825 #define OR_SDRAM_EAD 0x00000001
826 #define OR_SDRAM_EAD_SHIFT 0
828 /* LBCR - Local Bus Configuration Register
830 #define LBCR_LDIS 0x80000000
831 #define LBCR_LDIS_SHIFT 31
832 #define LBCR_BCTLC 0x00C00000
833 #define LBCR_BCTLC_SHIFT 22
834 #define LBCR_LPBSE 0x00020000
835 #define LBCR_LPBSE_SHIFT 17
836 #define LBCR_EPAR 0x00010000
837 #define LBCR_EPAR_SHIFT 16
838 #define LBCR_BMT 0x0000FF00
839 #define LBCR_BMT_SHIFT 8
841 /* LCRR - Clock Ratio Register
843 #define LCRR_DBYP 0x80000000
844 #define LCRR_DBYP_SHIFT 31
845 #define LCRR_BUFCMDC 0x30000000
846 #define LCRR_BUFCMDC_SHIFT 28
847 #define LCRR_BUFCMDC_1 0x10000000
848 #define LCRR_BUFCMDC_2 0x20000000
849 #define LCRR_BUFCMDC_3 0x30000000
850 #define LCRR_BUFCMDC_4 0x00000000
851 #define LCRR_ECL 0x03000000
852 #define LCRR_ECL_SHIFT 24
853 #define LCRR_ECL_4 0x00000000
854 #define LCRR_ECL_5 0x01000000
855 #define LCRR_ECL_6 0x02000000
856 #define LCRR_ECL_7 0x03000000
857 #define LCRR_EADC 0x00030000
858 #define LCRR_EADC_SHIFT 16
859 #define LCRR_EADC_1 0x00010000
860 #define LCRR_EADC_2 0x00020000
861 #define LCRR_EADC_3 0x00030000
862 #define LCRR_EADC_4 0x00000000
863 #define LCRR_CLKDIV 0x0000000F
864 #define LCRR_CLKDIV_SHIFT 0
865 #define LCRR_CLKDIV_2 0x00000002
866 #define LCRR_CLKDIV_4 0x00000004
867 #define LCRR_CLKDIV_8 0x00000008
869 /* DMAMR - DMA Mode Register
871 #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */
872 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */
873 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */
874 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */
875 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */
876 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */
877 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */
878 #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */
880 /* DMASR - DMA Status Register
882 #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */
883 #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */
885 /* CONFIG_ADDRESS - PCI Config Address Register
887 #define PCI_CONFIG_ADDRESS_EN 0x80000000
888 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16
889 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
890 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11
891 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
892 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8
893 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
894 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0
895 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
897 /* POTAR - PCI Outbound Translation Address Register
899 #define POTAR_TA_MASK 0x000fffff
901 /* POBAR - PCI Outbound Base Address Register
903 #define POBAR_BA_MASK 0x000fffff
905 /* POCMR - PCI Outbound Comparision Mask Register
907 #define POCMR_EN 0x80000000
908 #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */
909 #define POCMR_SE 0x20000000 /* streaming enable */
910 #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
911 #define POCMR_CM_MASK 0x000fffff
912 #define POCMR_CM_4G 0x00000000
913 #define POCMR_CM_2G 0x00080000
914 #define POCMR_CM_1G 0x000C0000
915 #define POCMR_CM_512M 0x000E0000
916 #define POCMR_CM_256M 0x000F0000
917 #define POCMR_CM_128M 0x000F8000
918 #define POCMR_CM_64M 0x000FC000
919 #define POCMR_CM_32M 0x000FE000
920 #define POCMR_CM_16M 0x000FF000
921 #define POCMR_CM_8M 0x000FF800
922 #define POCMR_CM_4M 0x000FFC00
923 #define POCMR_CM_2M 0x000FFE00
924 #define POCMR_CM_1M 0x000FFF00
925 #define POCMR_CM_512K 0x000FFF80
926 #define POCMR_CM_256K 0x000FFFC0
927 #define POCMR_CM_128K 0x000FFFE0
928 #define POCMR_CM_64K 0x000FFFF0
929 #define POCMR_CM_32K 0x000FFFF8
930 #define POCMR_CM_16K 0x000FFFFC
931 #define POCMR_CM_8K 0x000FFFFE
932 #define POCMR_CM_4K 0x000FFFFF
934 /* PITAR - PCI Inbound Translation Address Register
936 #define PITAR_TA_MASK 0x000fffff
938 /* PIBAR - PCI Inbound Base/Extended Address Register
940 #define PIBAR_MASK 0xffffffff
941 #define PIEBAR_EBA_MASK 0x000fffff
943 /* PIWAR - PCI Inbound Windows Attributes Register
945 #define PIWAR_EN 0x80000000
946 #define PIWAR_PF 0x20000000
947 #define PIWAR_RTT_MASK 0x000f0000
948 #define PIWAR_RTT_NO_SNOOP 0x00040000
949 #define PIWAR_RTT_SNOOP 0x00050000
950 #define PIWAR_WTT_MASK 0x0000f000
951 #define PIWAR_WTT_NO_SNOOP 0x00004000
952 #define PIWAR_WTT_SNOOP 0x00005000
953 #define PIWAR_IWS_MASK 0x0000003F
954 #define PIWAR_IWS_4K 0x0000000B
955 #define PIWAR_IWS_8K 0x0000000C
956 #define PIWAR_IWS_16K 0x0000000D
957 #define PIWAR_IWS_32K 0x0000000E
958 #define PIWAR_IWS_64K 0x0000000F
959 #define PIWAR_IWS_128K 0x00000010
960 #define PIWAR_IWS_256K 0x00000011
961 #define PIWAR_IWS_512K 0x00000012
962 #define PIWAR_IWS_1M 0x00000013
963 #define PIWAR_IWS_2M 0x00000014
964 #define PIWAR_IWS_4M 0x00000015
965 #define PIWAR_IWS_8M 0x00000016
966 #define PIWAR_IWS_16M 0x00000017
967 #define PIWAR_IWS_32M 0x00000018
968 #define PIWAR_IWS_64M 0x00000019
969 #define PIWAR_IWS_128M 0x0000001A
970 #define PIWAR_IWS_256M 0x0000001B
971 #define PIWAR_IWS_512M 0x0000001C
972 #define PIWAR_IWS_1G 0x0000001D
973 #define PIWAR_IWS_2G 0x0000001E
975 #endif /* __MPC83XX_H__ */
projects / platform / kernel / u-boot.git / blob