Merge branch 'master' of git://www.denx.de/git/u-boot-sh
[platform/kernel/u-boot.git] / include / mpc83xx.h
1 /*
2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  */
12
13 #ifndef __MPC83XX_H__
14 #define __MPC83XX_H__
15
16 #include <config.h>
17 #include <asm/fsl_lbc.h>
18 #if defined(CONFIG_E300)
19 #include <asm/e300.h>
20 #endif
21
22 /* MPC83xx cpu provide RCR register to do reset thing specially
23  */
24 #define MPC83xx_RESET
25
26 /* System reset offset (PowerPC standard)
27  */
28 #define EXC_OFF_SYS_RESET               0x0100
29 #define _START_OFFSET                   EXC_OFF_SYS_RESET
30
31 /* IMMRBAR - Internal Memory Register Base Address
32  */
33 #define CONFIG_DEFAULT_IMMR             0xFF400000      /* Default IMMR base address */
34 #define IMMRBAR                         0x0000          /* Register offset to immr */
35 #define IMMRBAR_BASE_ADDR               0xFFF00000      /* Base address mask */
36 #define IMMRBAR_RES                     ~(IMMRBAR_BASE_ADDR)
37
38 /* LAWBAR - Local Access Window Base Address Register
39  */
40 #define LBLAWBAR0                       0x0020          /* Register offset to immr */
41 #define LBLAWAR0                        0x0024
42 #define LBLAWBAR1                       0x0028
43 #define LBLAWAR1                        0x002C
44 #define LBLAWBAR2                       0x0030
45 #define LBLAWAR2                        0x0034
46 #define LBLAWBAR3                       0x0038
47 #define LBLAWAR3                        0x003C
48 #define LAWBAR_BAR                      0xFFFFF000      /* Base address mask */
49
50 /* SPRIDR - System Part and Revision ID Register
51  */
52 #define SPRIDR_PARTID                   0xFFFF0000      /* Part Id */
53 #define SPRIDR_REVID                    0x0000FFFF      /* Revision Id */
54
55 #if defined(CONFIG_MPC834X)
56 #define REVID_MAJOR(spridr)             ((spridr & 0x0000FF00) >> 8)
57 #define REVID_MINOR(spridr)             (spridr & 0x000000FF)
58 #else
59 #define REVID_MAJOR(spridr)             ((spridr & 0x000000F0) >> 4)
60 #define REVID_MINOR(spridr)             (spridr & 0x0000000F)
61 #endif
62
63 #define PARTID_NO_E(spridr)             ((spridr & 0xFFFE0000) >> 16)
64 #define IS_E_PROCESSOR(spridr)          (!(spridr & 0x00010000)) /* has SEC */
65
66 #define SPR_8311                        0x80B2
67 #define SPR_8313                        0x80B0
68 #define SPR_8314                        0x80B6
69 #define SPR_8315                        0x80B4
70 #define SPR_8321                        0x8066
71 #define SPR_8323                        0x8062
72 #define SPR_8343                        0x8036
73 #define SPR_8347_TBGA_                  0x8032
74 #define SPR_8347_PBGA_                  0x8034
75 #define SPR_8349                        0x8030
76 #define SPR_8358_TBGA_                  0x804A
77 #define SPR_8358_PBGA_                  0x804E
78 #define SPR_8360                        0x8048
79 #define SPR_8377                        0x80C6
80 #define SPR_8378                        0x80C4
81 #define SPR_8379                        0x80C2
82
83 /* SPCR - System Priority Configuration Register
84  */
85 #define SPCR_PCIHPE                     0x10000000      /* PCI Highest Priority Enable */
86 #define SPCR_PCIHPE_SHIFT               (31-3)
87 #define SPCR_PCIPR                      0x03000000      /* PCI bridge system bus request priority */
88 #define SPCR_PCIPR_SHIFT                (31-7)
89 #define SPCR_OPT                        0x00800000      /* Optimize */
90 #define SPCR_OPT_SHIFT                  (31-8)
91 #define SPCR_TBEN                       0x00400000      /* E300 PowerPC core time base unit enable */
92 #define SPCR_TBEN_SHIFT                 (31-9)
93 #define SPCR_COREPR                     0x00300000      /* E300 PowerPC Core system bus request priority */
94 #define SPCR_COREPR_SHIFT               (31-11)
95
96 #if defined(CONFIG_MPC834X)
97 /* SPCR bits - MPC8349 specific */
98 #define SPCR_TSEC1DP                    0x00003000      /* TSEC1 data priority */
99 #define SPCR_TSEC1DP_SHIFT              (31-19)
100 #define SPCR_TSEC1BDP                   0x00000C00      /* TSEC1 buffer descriptor priority */
101 #define SPCR_TSEC1BDP_SHIFT             (31-21)
102 #define SPCR_TSEC1EP                    0x00000300      /* TSEC1 emergency priority */
103 #define SPCR_TSEC1EP_SHIFT              (31-23)
104 #define SPCR_TSEC2DP                    0x00000030      /* TSEC2 data priority */
105 #define SPCR_TSEC2DP_SHIFT              (31-27)
106 #define SPCR_TSEC2BDP                   0x0000000C      /* TSEC2 buffer descriptor priority */
107 #define SPCR_TSEC2BDP_SHIFT             (31-29)
108 #define SPCR_TSEC2EP                    0x00000003      /* TSEC2 emergency priority */
109 #define SPCR_TSEC2EP_SHIFT              (31-31)
110
111 #elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
112 /* SPCR bits - MPC831x and MPC837x specific */
113 #define SPCR_TSECDP                     0x00003000      /* TSEC data priority */
114 #define SPCR_TSECDP_SHIFT               (31-19)
115 #define SPCR_TSECBDP                    0x00000C00      /* TSEC buffer descriptor priority */
116 #define SPCR_TSECBDP_SHIFT              (31-21)
117 #define SPCR_TSECEP                     0x00000300      /* TSEC emergency priority */
118 #define SPCR_TSECEP_SHIFT               (31-23)
119 #endif
120
121 /* SICRL/H - System I/O Configuration Register Low/High
122  */
123 #if defined(CONFIG_MPC834X)
124 /* SICRL bits - MPC8349 specific */
125 #define SICRL_LDP_A                     0x80000000
126 #define SICRL_USB1                      0x40000000
127 #define SICRL_USB0                      0x20000000
128 #define SICRL_UART                      0x0C000000
129 #define SICRL_GPIO1_A                   0x02000000
130 #define SICRL_GPIO1_B                   0x01000000
131 #define SICRL_GPIO1_C                   0x00800000
132 #define SICRL_GPIO1_D                   0x00400000
133 #define SICRL_GPIO1_E                   0x00200000
134 #define SICRL_GPIO1_F                   0x00180000
135 #define SICRL_GPIO1_G                   0x00040000
136 #define SICRL_GPIO1_H                   0x00020000
137 #define SICRL_GPIO1_I                   0x00010000
138 #define SICRL_GPIO1_J                   0x00008000
139 #define SICRL_GPIO1_K                   0x00004000
140 #define SICRL_GPIO1_L                   0x00003000
141
142 /* SICRH bits - MPC8349 specific */
143 #define SICRH_DDR                       0x80000000
144 #define SICRH_TSEC1_A                   0x10000000
145 #define SICRH_TSEC1_B                   0x08000000
146 #define SICRH_TSEC1_C                   0x04000000
147 #define SICRH_TSEC1_D                   0x02000000
148 #define SICRH_TSEC1_E                   0x01000000
149 #define SICRH_TSEC1_F                   0x00800000
150 #define SICRH_TSEC2_A                   0x00400000
151 #define SICRH_TSEC2_B                   0x00200000
152 #define SICRH_TSEC2_C                   0x00100000
153 #define SICRH_TSEC2_D                   0x00080000
154 #define SICRH_TSEC2_E                   0x00040000
155 #define SICRH_TSEC2_F                   0x00020000
156 #define SICRH_TSEC2_G                   0x00010000
157 #define SICRH_TSEC2_H                   0x00008000
158 #define SICRH_GPIO2_A                   0x00004000
159 #define SICRH_GPIO2_B                   0x00002000
160 #define SICRH_GPIO2_C                   0x00001000
161 #define SICRH_GPIO2_D                   0x00000800
162 #define SICRH_GPIO2_E                   0x00000400
163 #define SICRH_GPIO2_F                   0x00000200
164 #define SICRH_GPIO2_G                   0x00000180
165 #define SICRH_GPIO2_H                   0x00000060
166 #define SICRH_TSOBI1                    0x00000002
167 #define SICRH_TSOBI2                    0x00000001
168
169 #elif defined(CONFIG_MPC8360)
170 /* SICRL bits - MPC8360 specific */
171 #define SICRL_LDP_A                     0xC0000000
172 #define SICRL_LCLK_1                    0x10000000
173 #define SICRL_LCLK_2                    0x08000000
174 #define SICRL_SRCID_A                   0x03000000
175 #define SICRL_IRQ_CKSTP_A               0x00C00000
176
177 /* SICRH bits - MPC8360 specific */
178 #define SICRH_DDR                       0x80000000
179 #define SICRH_SECONDARY_DDR             0x40000000
180 #define SICRH_SDDROE                    0x20000000
181 #define SICRH_IRQ3                      0x10000000
182 #define SICRH_UC1EOBI                   0x00000004
183 #define SICRH_UC2E1OBI                  0x00000002
184 #define SICRH_UC2E2OBI                  0x00000001
185
186 #elif defined(CONFIG_MPC832X)
187 /* SICRL bits - MPC832X specific */
188 #define SICRL_LDP_LCS_A                 0x80000000
189 #define SICRL_IRQ_CKS                   0x20000000
190 #define SICRL_PCI_MSRC                  0x10000000
191 #define SICRL_URT_CTPR                  0x06000000
192 #define SICRL_IRQ_CTPR                  0x00C00000
193
194 #elif defined(CONFIG_MPC8313)
195 /* SICRL bits - MPC8313 specific */
196 #define SICRL_LBC                       0x30000000
197 #define SICRL_UART                      0x0C000000
198 #define SICRL_SPI_A                     0x03000000
199 #define SICRL_SPI_B                     0x00C00000
200 #define SICRL_SPI_C                     0x00300000
201 #define SICRL_SPI_D                     0x000C0000
202 #define SICRL_USBDR                     0x00000C00
203 #define SICRL_ETSEC1_A                  0x0000000C
204 #define SICRL_ETSEC2_A                  0x00000003
205
206 /* SICRH bits - MPC8313 specific */
207 #define SICRH_INTR_A                    0x02000000
208 #define SICRH_INTR_B                    0x00C00000
209 #define SICRH_IIC                       0x00300000
210 #define SICRH_ETSEC2_B                  0x000C0000
211 #define SICRH_ETSEC2_C                  0x00030000
212 #define SICRH_ETSEC2_D                  0x0000C000
213 #define SICRH_ETSEC2_E                  0x00003000
214 #define SICRH_ETSEC2_F                  0x00000C00
215 #define SICRH_ETSEC2_G                  0x00000300
216 #define SICRH_ETSEC1_B                  0x00000080
217 #define SICRH_ETSEC1_C                  0x00000060
218 #define SICRH_GTX1_DLY                  0x00000008
219 #define SICRH_GTX2_DLY                  0x00000004
220 #define SICRH_TSOBI1                    0x00000002
221 #define SICRH_TSOBI2                    0x00000001
222
223 #elif defined(CONFIG_MPC8315)
224 /* SICRL bits - MPC8315 specific */
225 #define SICRL_DMA_CH0                   0xc0000000
226 #define SICRL_DMA_SPI                   0x30000000
227 #define SICRL_UART                      0x0c000000
228 #define SICRL_IRQ4                      0x02000000
229 #define SICRL_IRQ5                      0x01800000
230 #define SICRL_IRQ6_7                    0x00400000
231 #define SICRL_IIC1                      0x00300000
232 #define SICRL_TDM                       0x000c0000
233 #define SICRL_TDM_SHARED                0x00030000
234 #define SICRL_PCI_A                     0x0000c000
235 #define SICRL_ELBC_A                    0x00003000
236 #define SICRL_ETSEC1_A                  0x000000c0
237 #define SICRL_ETSEC1_B                  0x00000030
238 #define SICRL_ETSEC1_C                  0x0000000c
239 #define SICRL_TSEXPOBI                  0x00000001
240
241 /* SICRH bits - MPC8315 specific */
242 #define SICRH_GPIO_0                    0xc0000000
243 #define SICRH_GPIO_1                    0x30000000
244 #define SICRH_GPIO_2                    0x0c000000
245 #define SICRH_GPIO_3                    0x03000000
246 #define SICRH_GPIO_4                    0x00c00000
247 #define SICRH_GPIO_5                    0x00300000
248 #define SICRH_GPIO_6                    0x000c0000
249 #define SICRH_GPIO_7                    0x00030000
250 #define SICRH_GPIO_8                    0x0000c000
251 #define SICRH_GPIO_9                    0x00003000
252 #define SICRH_GPIO_10                   0x00000c00
253 #define SICRH_GPIO_11                   0x00000300
254 #define SICRH_ETSEC2_A                  0x000000c0
255 #define SICRH_TSOBI1                    0x00000002
256 #define SICRH_TSOBI2                    0x00000001
257
258 #elif defined(CONFIG_MPC837X)
259 /* SICRL bits - MPC837x specific */
260 #define SICRL_USB_A                     0xC0000000
261 #define SICRL_USB_B                     0x30000000
262 #define SICRL_UART                      0x0C000000
263 #define SICRL_GPIO_A                    0x02000000
264 #define SICRL_GPIO_B                    0x01000000
265 #define SICRL_GPIO_C                    0x00800000
266 #define SICRL_GPIO_D                    0x00400000
267 #define SICRL_GPIO_E                    0x00200000
268 #define SICRL_GPIO_F                    0x00180000
269 #define SICRL_GPIO_G                    0x00040000
270 #define SICRL_GPIO_H                    0x00020000
271 #define SICRL_GPIO_I                    0x00010000
272 #define SICRL_GPIO_J                    0x00008000
273 #define SICRL_GPIO_K                    0x00004000
274 #define SICRL_GPIO_L                    0x00003000
275 #define SICRL_DMA_A                     0x00000800
276 #define SICRL_DMA_B                     0x00000400
277 #define SICRL_DMA_C                     0x00000200
278 #define SICRL_DMA_D                     0x00000100
279 #define SICRL_DMA_E                     0x00000080
280 #define SICRL_DMA_F                     0x00000040
281 #define SICRL_DMA_G                     0x00000020
282 #define SICRL_DMA_H                     0x00000010
283 #define SICRL_DMA_I                     0x00000008
284 #define SICRL_DMA_J                     0x00000004
285 #define SICRL_LDP_A                     0x00000002
286 #define SICRL_LDP_B                     0x00000001
287
288 /* SICRH bits - MPC837x specific */
289 #define SICRH_DDR                       0x80000000
290 #define SICRH_TSEC1_A                   0x10000000
291 #define SICRH_TSEC1_B                   0x08000000
292 #define SICRH_TSEC2_A                   0x00400000
293 #define SICRH_TSEC2_B                   0x00200000
294 #define SICRH_TSEC2_C                   0x00100000
295 #define SICRH_TSEC2_D                   0x00080000
296 #define SICRH_TSEC2_E                   0x00040000
297 #define SICRH_TMR                       0x00010000
298 #define SICRH_GPIO2_A                   0x00008000
299 #define SICRH_GPIO2_B                   0x00004000
300 #define SICRH_GPIO2_C                   0x00002000
301 #define SICRH_GPIO2_D                   0x00001000
302 #define SICRH_GPIO2_E                   0x00000C00
303 #define SICRH_GPIO2_F                   0x00000300
304 #define SICRH_GPIO2_G                   0x000000C0
305 #define SICRH_GPIO2_H                   0x00000030
306 #define SICRH_SPI                       0x00000003
307 #endif
308
309 /* SWCRR - System Watchdog Control Register
310  */
311 #define SWCRR                           0x0204          /* Register offset to immr */
312 #define SWCRR_SWTC                      0xFFFF0000      /* Software Watchdog Time Count */
313 #define SWCRR_SWEN                      0x00000004      /* Watchdog Enable bit */
314 #define SWCRR_SWRI                      0x00000002      /* Software Watchdog Reset/Interrupt Select bit */
315 #define SWCRR_SWPR                      0x00000001      /* Software Watchdog Counter Prescale bit */
316 #define SWCRR_RES                       ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
317
318 /* SWCNR - System Watchdog Counter Register
319  */
320 #define SWCNR                           0x0208          /* Register offset to immr */
321 #define SWCNR_SWCN                      0x0000FFFF      /* Software Watchdog Count mask */
322 #define SWCNR_RES                       ~(SWCNR_SWCN)
323
324 /* SWSRR - System Watchdog Service Register
325  */
326 #define SWSRR                           0x020E          /* Register offset to immr */
327
328 /* ACR - Arbiter Configuration Register
329  */
330 #define ACR_COREDIS                     0x10000000      /* Core disable */
331 #define ACR_COREDIS_SHIFT               (31-7)
332 #define ACR_PIPE_DEP                    0x00070000      /* Pipeline depth */
333 #define ACR_PIPE_DEP_SHIFT              (31-15)
334 #define ACR_PCI_RPTCNT                  0x00007000      /* PCI repeat count */
335 #define ACR_PCI_RPTCNT_SHIFT            (31-19)
336 #define ACR_RPTCNT                      0x00000700      /* Repeat count */
337 #define ACR_RPTCNT_SHIFT                (31-23)
338 #define ACR_APARK                       0x00000030      /* Address parking */
339 #define ACR_APARK_SHIFT                 (31-27)
340 #define ACR_PARKM                       0x0000000F      /* Parking master */
341 #define ACR_PARKM_SHIFT                 (31-31)
342
343 /* ATR - Arbiter Timers Register
344  */
345 #define ATR_DTO                         0x00FF0000      /* Data time out */
346 #define ATR_ATO                         0x000000FF      /* Address time out */
347
348 /* AER - Arbiter Event Register
349  */
350 #define AER_ETEA                        0x00000020      /* Transfer error */
351 #define AER_RES                         0x00000010      /* Reserved transfer type */
352 #define AER_ECW                         0x00000008      /* External control word transfer type */
353 #define AER_AO                          0x00000004      /* Address Only transfer type */
354 #define AER_DTO                         0x00000002      /* Data time out */
355 #define AER_ATO                         0x00000001      /* Address time out */
356
357 /* AEATR - Arbiter Event Address Register
358  */
359 #define AEATR_EVENT                     0x07000000      /* Event type */
360 #define AEATR_MSTR_ID                   0x001F0000      /* Master Id */
361 #define AEATR_TBST                      0x00000800      /* Transfer burst */
362 #define AEATR_TSIZE                     0x00000700      /* Transfer Size */
363 #define AEATR_TTYPE                     0x0000001F      /* Transfer Type */
364
365 /* HRCWL - Hard Reset Configuration Word Low
366  */
367 #define HRCWL_LBIUCM                    0x80000000
368 #define HRCWL_LBIUCM_SHIFT              31
369 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1    0x00000000
370 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1    0x80000000
371
372 #define HRCWL_DDRCM                     0x40000000
373 #define HRCWL_DDRCM_SHIFT               30
374 #define HRCWL_DDR_TO_SCB_CLK_1X1        0x00000000
375 #define HRCWL_DDR_TO_SCB_CLK_2X1        0x40000000
376
377 #define HRCWL_SPMF                      0x0f000000
378 #define HRCWL_SPMF_SHIFT                24
379 #define HRCWL_CSB_TO_CLKIN_16X1         0x00000000
380 #define HRCWL_CSB_TO_CLKIN_1X1          0x01000000
381 #define HRCWL_CSB_TO_CLKIN_2X1          0x02000000
382 #define HRCWL_CSB_TO_CLKIN_3X1          0x03000000
383 #define HRCWL_CSB_TO_CLKIN_4X1          0x04000000
384 #define HRCWL_CSB_TO_CLKIN_5X1          0x05000000
385 #define HRCWL_CSB_TO_CLKIN_6X1          0x06000000
386 #define HRCWL_CSB_TO_CLKIN_7X1          0x07000000
387 #define HRCWL_CSB_TO_CLKIN_8X1          0x08000000
388 #define HRCWL_CSB_TO_CLKIN_9X1          0x09000000
389 #define HRCWL_CSB_TO_CLKIN_10X1         0x0A000000
390 #define HRCWL_CSB_TO_CLKIN_11X1         0x0B000000
391 #define HRCWL_CSB_TO_CLKIN_12X1         0x0C000000
392 #define HRCWL_CSB_TO_CLKIN_13X1         0x0D000000
393 #define HRCWL_CSB_TO_CLKIN_14X1         0x0E000000
394 #define HRCWL_CSB_TO_CLKIN_15X1         0x0F000000
395
396 #define HRCWL_VCO_BYPASS                0x00000000
397 #define HRCWL_VCO_1X2                   0x00000000
398 #define HRCWL_VCO_1X4                   0x00200000
399 #define HRCWL_VCO_1X8                   0x00400000
400
401 #define HRCWL_COREPLL                   0x007F0000
402 #define HRCWL_COREPLL_SHIFT             16
403 #define HRCWL_CORE_TO_CSB_BYPASS        0x00000000
404 #define HRCWL_CORE_TO_CSB_1X1           0x00020000
405 #define HRCWL_CORE_TO_CSB_1_5X1         0x00030000
406 #define HRCWL_CORE_TO_CSB_2X1           0x00040000
407 #define HRCWL_CORE_TO_CSB_2_5X1         0x00050000
408 #define HRCWL_CORE_TO_CSB_3X1           0x00060000
409
410 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
411 #define HRCWL_CEVCOD                    0x000000C0
412 #define HRCWL_CEVCOD_SHIFT              6
413 #define HRCWL_CE_PLL_VCO_DIV_4          0x00000000
414 #define HRCWL_CE_PLL_VCO_DIV_8          0x00000040
415 #define HRCWL_CE_PLL_VCO_DIV_2          0x00000080
416
417 #define HRCWL_CEPDF                     0x00000020
418 #define HRCWL_CEPDF_SHIFT               5
419 #define HRCWL_CE_PLL_DIV_1X1            0x00000000
420 #define HRCWL_CE_PLL_DIV_2X1            0x00000020
421
422 #define HRCWL_CEPMF                     0x0000001F
423 #define HRCWL_CEPMF_SHIFT               0
424 #define HRCWL_CE_TO_PLL_1X16_           0x00000000
425 #define HRCWL_CE_TO_PLL_1X2             0x00000002
426 #define HRCWL_CE_TO_PLL_1X3             0x00000003
427 #define HRCWL_CE_TO_PLL_1X4             0x00000004
428 #define HRCWL_CE_TO_PLL_1X5             0x00000005
429 #define HRCWL_CE_TO_PLL_1X6             0x00000006
430 #define HRCWL_CE_TO_PLL_1X7             0x00000007
431 #define HRCWL_CE_TO_PLL_1X8             0x00000008
432 #define HRCWL_CE_TO_PLL_1X9             0x00000009
433 #define HRCWL_CE_TO_PLL_1X10            0x0000000A
434 #define HRCWL_CE_TO_PLL_1X11            0x0000000B
435 #define HRCWL_CE_TO_PLL_1X12            0x0000000C
436 #define HRCWL_CE_TO_PLL_1X13            0x0000000D
437 #define HRCWL_CE_TO_PLL_1X14            0x0000000E
438 #define HRCWL_CE_TO_PLL_1X15            0x0000000F
439 #define HRCWL_CE_TO_PLL_1X16            0x00000010
440 #define HRCWL_CE_TO_PLL_1X17            0x00000011
441 #define HRCWL_CE_TO_PLL_1X18            0x00000012
442 #define HRCWL_CE_TO_PLL_1X19            0x00000013
443 #define HRCWL_CE_TO_PLL_1X20            0x00000014
444 #define HRCWL_CE_TO_PLL_1X21            0x00000015
445 #define HRCWL_CE_TO_PLL_1X22            0x00000016
446 #define HRCWL_CE_TO_PLL_1X23            0x00000017
447 #define HRCWL_CE_TO_PLL_1X24            0x00000018
448 #define HRCWL_CE_TO_PLL_1X25            0x00000019
449 #define HRCWL_CE_TO_PLL_1X26            0x0000001A
450 #define HRCWL_CE_TO_PLL_1X27            0x0000001B
451 #define HRCWL_CE_TO_PLL_1X28            0x0000001C
452 #define HRCWL_CE_TO_PLL_1X29            0x0000001D
453 #define HRCWL_CE_TO_PLL_1X30            0x0000001E
454 #define HRCWL_CE_TO_PLL_1X31            0x0000001F
455
456 #elif defined(CONFIG_MPC8315)
457 #define HRCWL_SVCOD                     0x30000000
458 #define HRCWL_SVCOD_SHIFT               28
459 #define HRCWL_SVCOD_DIV_2               0x00000000
460 #define HRCWL_SVCOD_DIV_4               0x10000000
461 #define HRCWL_SVCOD_DIV_8               0x20000000
462 #define HRCWL_SVCOD_DIV_1               0x30000000
463
464 #elif defined(CONFIG_MPC837X)
465 #define HRCWL_SVCOD                     0x30000000
466 #define HRCWL_SVCOD_SHIFT               28
467 #define HRCWL_SVCOD_DIV_4               0x00000000
468 #define HRCWL_SVCOD_DIV_8               0x10000000
469 #define HRCWL_SVCOD_DIV_2               0x20000000
470 #define HRCWL_SVCOD_DIV_1               0x30000000
471 #endif
472
473 /* HRCWH - Hardware Reset Configuration Word High
474  */
475 #define HRCWH_PCI_HOST                  0x80000000
476 #define HRCWH_PCI_HOST_SHIFT            31
477 #define HRCWH_PCI_AGENT                 0x00000000
478
479 #if defined(CONFIG_MPC834X)
480 #define HRCWH_32_BIT_PCI                0x00000000
481 #define HRCWH_64_BIT_PCI                0x40000000
482 #endif
483
484 #define HRCWH_PCI1_ARBITER_DISABLE      0x00000000
485 #define HRCWH_PCI1_ARBITER_ENABLE       0x20000000
486
487 #define HRCWH_PCI_ARBITER_DISABLE       0x00000000
488 #define HRCWH_PCI_ARBITER_ENABLE        0x20000000
489
490 #if defined(CONFIG_MPC834X)
491 #define HRCWH_PCI2_ARBITER_DISABLE      0x00000000
492 #define HRCWH_PCI2_ARBITER_ENABLE       0x10000000
493
494 #elif defined(CONFIG_MPC8360)
495 #define HRCWH_PCICKDRV_DISABLE          0x00000000
496 #define HRCWH_PCICKDRV_ENABLE           0x10000000
497 #endif
498
499 #define HRCWH_CORE_DISABLE              0x08000000
500 #define HRCWH_CORE_ENABLE               0x00000000
501
502 #define HRCWH_FROM_0X00000100           0x00000000
503 #define HRCWH_FROM_0XFFF00100           0x04000000
504
505 #define HRCWH_BOOTSEQ_DISABLE           0x00000000
506 #define HRCWH_BOOTSEQ_NORMAL            0x01000000
507 #define HRCWH_BOOTSEQ_EXTENDED          0x02000000
508
509 #define HRCWH_SW_WATCHDOG_DISABLE       0x00000000
510 #define HRCWH_SW_WATCHDOG_ENABLE        0x00800000
511
512 #define HRCWH_ROM_LOC_DDR_SDRAM         0x00000000
513 #define HRCWH_ROM_LOC_PCI1              0x00100000
514 #if defined(CONFIG_MPC834X)
515 #define HRCWH_ROM_LOC_PCI2              0x00200000
516 #endif
517 #if defined(CONIFG_MPC837X)
518 #define HRCWH_ROM_LOC_ON_CHIP_ROM       0x00300000
519 #endif
520 #define HRCWH_ROM_LOC_LOCAL_8BIT        0x00500000
521 #define HRCWH_ROM_LOC_LOCAL_16BIT       0x00600000
522 #define HRCWH_ROM_LOC_LOCAL_32BIT       0x00700000
523
524 #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
525 #define HRCWH_ROM_LOC_NAND_SP_8BIT      0x00100000
526 #define HRCWH_ROM_LOC_NAND_SP_16BIT     0x00200000
527 #define HRCWH_ROM_LOC_NAND_LP_8BIT      0x00500000
528 #define HRCWH_ROM_LOC_NAND_LP_16BIT     0x00600000
529
530 #define HRCWH_RL_EXT_LEGACY             0x00000000
531 #define HRCWH_RL_EXT_NAND               0x00040000
532
533 #define HRCWH_TSEC1M_IN_MII             0x00000000
534 #define HRCWH_TSEC1M_IN_RMII            0x00002000
535 #define HRCWH_TSEC1M_IN_RGMII           0x00006000
536 #define HRCWH_TSEC1M_IN_RTBI            0x0000A000
537 #define HRCWH_TSEC1M_IN_SGMII           0x0000C000
538
539 #define HRCWH_TSEC2M_IN_MII             0x00000000
540 #define HRCWH_TSEC2M_IN_RMII            0x00000400
541 #define HRCWH_TSEC2M_IN_RGMII           0x00000C00
542 #define HRCWH_TSEC2M_IN_RTBI            0x00001400
543 #define HRCWH_TSEC2M_IN_SGMII           0x00001800
544 #endif
545
546 #if defined(CONFIG_MPC834X)
547 #define HRCWH_TSEC1M_IN_RGMII           0x00000000
548 #define HRCWH_TSEC1M_IN_RTBI            0x00004000
549 #define HRCWH_TSEC1M_IN_GMII            0x00008000
550 #define HRCWH_TSEC1M_IN_TBI             0x0000C000
551 #define HRCWH_TSEC2M_IN_RGMII           0x00000000
552 #define HRCWH_TSEC2M_IN_RTBI            0x00001000
553 #define HRCWH_TSEC2M_IN_GMII            0x00002000
554 #define HRCWH_TSEC2M_IN_TBI             0x00003000
555 #endif
556
557 #if defined(CONFIG_MPC8360)
558 #define HRCWH_SECONDARY_DDR_DISABLE     0x00000000
559 #define HRCWH_SECONDARY_DDR_ENABLE      0x00000010
560 #endif
561
562 #define HRCWH_BIG_ENDIAN                0x00000000
563 #define HRCWH_LITTLE_ENDIAN             0x00000008
564
565 #define HRCWH_LALE_NORMAL               0x00000000
566 #define HRCWH_LALE_EARLY                0x00000004
567
568 #define HRCWH_LDP_SET                   0x00000000
569 #define HRCWH_LDP_CLEAR                 0x00000002
570
571 /* RSR - Reset Status Register
572  */
573 #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
574 #define RSR_RSTSRC                      0xF0000000      /* Reset source */
575 #define RSR_RSTSRC_SHIFT                28
576 #else
577 #define RSR_RSTSRC                      0xE0000000      /* Reset source */
578 #define RSR_RSTSRC_SHIFT                29
579 #endif
580 #define RSR_BSF                         0x00010000      /* Boot seq. fail */
581 #define RSR_BSF_SHIFT                   16
582 #define RSR_SWSR                        0x00002000      /* software soft reset */
583 #define RSR_SWSR_SHIFT                  13
584 #define RSR_SWHR                        0x00001000      /* software hard reset */
585 #define RSR_SWHR_SHIFT                  12
586 #define RSR_JHRS                        0x00000200      /* jtag hreset */
587 #define RSR_JHRS_SHIFT                  9
588 #define RSR_JSRS                        0x00000100      /* jtag sreset status */
589 #define RSR_JSRS_SHIFT                  8
590 #define RSR_CSHR                        0x00000010      /* checkstop reset status */
591 #define RSR_CSHR_SHIFT                  4
592 #define RSR_SWRS                        0x00000008      /* software watchdog reset status */
593 #define RSR_SWRS_SHIFT                  3
594 #define RSR_BMRS                        0x00000004      /* bus monitop reset status */
595 #define RSR_BMRS_SHIFT                  2
596 #define RSR_SRS                         0x00000002      /* soft reset status */
597 #define RSR_SRS_SHIFT                   1
598 #define RSR_HRS                         0x00000001      /* hard reset status */
599 #define RSR_HRS_SHIFT                   0
600 #define RSR_RES                         ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\
601                                          RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
602                                          RSR_BMRS | RSR_SRS | RSR_HRS)
603 /* RMR - Reset Mode Register
604  */
605 #define RMR_CSRE                        0x00000001      /* checkstop reset enable */
606 #define RMR_CSRE_SHIFT                  0
607 #define RMR_RES                         ~(RMR_CSRE)
608
609 /* RCR - Reset Control Register
610  */
611 #define RCR_SWHR                        0x00000002      /* software hard reset */
612 #define RCR_SWSR                        0x00000001      /* software soft reset */
613 #define RCR_RES                         ~(RCR_SWHR | RCR_SWSR)
614
615 /* RCER - Reset Control Enable Register
616  */
617 #define RCER_CRE                        0x00000001      /* software hard reset */
618 #define RCER_RES                        ~(RCER_CRE)
619
620 /* SPMR - System PLL Mode Register
621  */
622 #define SPMR_LBIUCM                     0x80000000
623 #define SPMR_DDRCM                      0x40000000
624 #define SPMR_SPMF                       0x0F000000
625 #define SPMR_CKID                       0x00800000
626 #define SPMR_CKID_SHIFT                 23
627 #define SPMR_COREPLL                    0x007F0000
628 #define SPMR_CEVCOD                     0x000000C0
629 #define SPMR_CEPDF                      0x00000020
630 #define SPMR_CEPMF                      0x0000001F
631
632 /* OCCR - Output Clock Control Register
633  */
634 #define OCCR_PCICOE0                    0x80000000
635 #define OCCR_PCICOE1                    0x40000000
636 #define OCCR_PCICOE2                    0x20000000
637 #define OCCR_PCICOE3                    0x10000000
638 #define OCCR_PCICOE4                    0x08000000
639 #define OCCR_PCICOE5                    0x04000000
640 #define OCCR_PCICOE6                    0x02000000
641 #define OCCR_PCICOE7                    0x01000000
642 #define OCCR_PCICD0                     0x00800000
643 #define OCCR_PCICD1                     0x00400000
644 #define OCCR_PCICD2                     0x00200000
645 #define OCCR_PCICD3                     0x00100000
646 #define OCCR_PCICD4                     0x00080000
647 #define OCCR_PCICD5                     0x00040000
648 #define OCCR_PCICD6                     0x00020000
649 #define OCCR_PCICD7                     0x00010000
650 #define OCCR_PCI1CR                     0x00000002
651 #define OCCR_PCI2CR                     0x00000001
652 #define OCCR_PCICR                      OCCR_PCI1CR
653
654 /* SCCR - System Clock Control Register
655  */
656 #define SCCR_ENCCM                      0x03000000
657 #define SCCR_ENCCM_SHIFT                24
658 #define SCCR_ENCCM_0                    0x00000000
659 #define SCCR_ENCCM_1                    0x01000000
660 #define SCCR_ENCCM_2                    0x02000000
661 #define SCCR_ENCCM_3                    0x03000000
662
663 #define SCCR_PCICM                      0x00010000
664 #define SCCR_PCICM_SHIFT                16
665
666 #if defined(CONFIG_MPC834X)
667 /* SCCR bits - MPC834x specific */
668 #define SCCR_TSEC1CM                    0xc0000000
669 #define SCCR_TSEC1CM_SHIFT              30
670 #define SCCR_TSEC1CM_0                  0x00000000
671 #define SCCR_TSEC1CM_1                  0x40000000
672 #define SCCR_TSEC1CM_2                  0x80000000
673 #define SCCR_TSEC1CM_3                  0xC0000000
674
675 #define SCCR_TSEC2CM                    0x30000000
676 #define SCCR_TSEC2CM_SHIFT              28
677 #define SCCR_TSEC2CM_0                  0x00000000
678 #define SCCR_TSEC2CM_1                  0x10000000
679 #define SCCR_TSEC2CM_2                  0x20000000
680 #define SCCR_TSEC2CM_3                  0x30000000
681
682 /* The MPH must have the same clock ratio as DR, unless its clock disabled */
683 #define SCCR_USBMPHCM                   0x00c00000
684 #define SCCR_USBMPHCM_SHIFT             22
685 #define SCCR_USBDRCM                    0x00300000
686 #define SCCR_USBDRCM_SHIFT              20
687 #define SCCR_USBCM                      0x00f00000
688 #define SCCR_USBCM_SHIFT                20
689 #define SCCR_USBCM_0                    0x00000000
690 #define SCCR_USBCM_1                    0x00500000
691 #define SCCR_USBCM_2                    0x00A00000
692 #define SCCR_USBCM_3                    0x00F00000
693
694 #elif defined(CONFIG_MPC8313)
695 /* TSEC1 bits are for TSEC2 as well */
696 #define SCCR_TSEC1CM                    0xc0000000
697 #define SCCR_TSEC1CM_SHIFT              30
698 #define SCCR_TSEC1CM_0                  0x00000000
699 #define SCCR_TSEC1CM_1                  0x40000000
700 #define SCCR_TSEC1CM_2                  0x80000000
701 #define SCCR_TSEC1CM_3                  0xC0000000
702
703 #define SCCR_TSEC1ON                    0x20000000
704 #define SCCR_TSEC1ON_SHIFT              29
705 #define SCCR_TSEC2ON                    0x10000000
706 #define SCCR_TSEC2ON_SHIFT              28
707
708 #define SCCR_USBDRCM                    0x00300000
709 #define SCCR_USBDRCM_SHIFT              20
710 #define SCCR_USBDRCM_0                  0x00000000
711 #define SCCR_USBDRCM_1                  0x00100000
712 #define SCCR_USBDRCM_2                  0x00200000
713 #define SCCR_USBDRCM_3                  0x00300000
714
715 #elif defined(CONFIG_MPC8315)
716 /* SCCR bits - MPC8315 specific */
717 #define SCCR_TSEC1CM                    0xc0000000
718 #define SCCR_TSEC1CM_SHIFT              30
719 #define SCCR_TSEC1CM_0                  0x00000000
720 #define SCCR_TSEC1CM_1                  0x40000000
721 #define SCCR_TSEC1CM_2                  0x80000000
722 #define SCCR_TSEC1CM_3                  0xC0000000
723
724 #define SCCR_TSEC2CM                    0x30000000
725 #define SCCR_TSEC2CM_SHIFT              28
726 #define SCCR_TSEC2CM_0                  0x00000000
727 #define SCCR_TSEC2CM_1                  0x10000000
728 #define SCCR_TSEC2CM_2                  0x20000000
729 #define SCCR_TSEC2CM_3                  0x30000000
730
731 #define SCCR_USBDRCM                    0x00c00000
732 #define SCCR_USBDRCM_SHIFT              22
733 #define SCCR_USBDRCM_0                  0x00000000
734 #define SCCR_USBDRCM_1                  0x00400000
735 #define SCCR_USBDRCM_2                  0x00800000
736 #define SCCR_USBDRCM_3                  0x00c00000
737
738 #define SCCR_PCIEXP1CM                  0x00300000
739 #define SCCR_PCIEXP2CM                  0x000c0000
740
741 #define SCCR_SATA1CM                    0x00003000
742 #define SCCR_SATA1CM_SHIFT              12
743 #define SCCR_SATACM                     0x00003c00
744 #define SCCR_SATACM_SHIFT               10
745 #define SCCR_SATACM_0                   0x00000000
746 #define SCCR_SATACM_1                   0x00001400
747 #define SCCR_SATACM_2                   0x00002800
748 #define SCCR_SATACM_3                   0x00003c00
749
750 #define SCCR_TDMCM                      0x00000030
751 #define SCCR_TDMCM_SHIFT                4
752 #define SCCR_TDMCM_0                    0x00000000
753 #define SCCR_TDMCM_1                    0x00000010
754 #define SCCR_TDMCM_2                    0x00000020
755 #define SCCR_TDMCM_3                    0x00000030
756
757 #elif defined(CONFIG_MPC837X)
758 /* SCCR bits - MPC837x specific */
759 #define SCCR_TSEC1CM                    0xc0000000
760 #define SCCR_TSEC1CM_SHIFT              30
761 #define SCCR_TSEC1CM_0                  0x00000000
762 #define SCCR_TSEC1CM_1                  0x40000000
763 #define SCCR_TSEC1CM_2                  0x80000000
764 #define SCCR_TSEC1CM_3                  0xC0000000
765
766 #define SCCR_TSEC2CM                    0x30000000
767 #define SCCR_TSEC2CM_SHIFT              28
768 #define SCCR_TSEC2CM_0                  0x00000000
769 #define SCCR_TSEC2CM_1                  0x10000000
770 #define SCCR_TSEC2CM_2                  0x20000000
771 #define SCCR_TSEC2CM_3                  0x30000000
772
773 #define SCCR_SDHCCM                     0x0c000000
774 #define SCCR_SDHCCM_SHIFT               26
775 #define SCCR_SDHCCM_0                   0x00000000
776 #define SCCR_SDHCCM_1                   0x04000000
777 #define SCCR_SDHCCM_2                   0x08000000
778 #define SCCR_SDHCCM_3                   0x0c000000
779
780 #define SCCR_USBDRCM                    0x00c00000
781 #define SCCR_USBDRCM_SHIFT              22
782 #define SCCR_USBDRCM_0                  0x00000000
783 #define SCCR_USBDRCM_1                  0x00400000
784 #define SCCR_USBDRCM_2                  0x00800000
785 #define SCCR_USBDRCM_3                  0x00c00000
786
787 #define SCCR_PCIEXP1CM                  0x00300000
788 #define SCCR_PCIEXP1CM_SHIFT            20
789 #define SCCR_PCIEXP1CM_0                0x00000000
790 #define SCCR_PCIEXP1CM_1                0x00100000
791 #define SCCR_PCIEXP1CM_2                0x00200000
792 #define SCCR_PCIEXP1CM_3                0x00300000
793
794 #define SCCR_PCIEXP2CM                  0x000c0000
795 #define SCCR_PCIEXP2CM_SHIFT            18
796 #define SCCR_PCIEXP2CM_0                0x00000000
797 #define SCCR_PCIEXP2CM_1                0x00040000
798 #define SCCR_PCIEXP2CM_2                0x00080000
799 #define SCCR_PCIEXP2CM_3                0x000c0000
800
801 /* All of the four SATA controllers must have the same clock ratio */
802 #define SCCR_SATA1CM                    0x000000c0
803 #define SCCR_SATA1CM_SHIFT              6
804 #define SCCR_SATACM                     0x000000ff
805 #define SCCR_SATACM_SHIFT               0
806 #define SCCR_SATACM_0                   0x00000000
807 #define SCCR_SATACM_1                   0x00000055
808 #define SCCR_SATACM_2                   0x000000aa
809 #define SCCR_SATACM_3                   0x000000ff
810 #endif
811
812 /* CSn_BDNS - Chip Select memory Bounds Register
813  */
814 #define CSBNDS_SA                       0x00FF0000
815 #define CSBNDS_SA_SHIFT                 8
816 #define CSBNDS_EA                       0x000000FF
817 #define CSBNDS_EA_SHIFT                 24
818
819 /* CSn_CONFIG - Chip Select Configuration Register
820  */
821 #define CSCONFIG_EN                     0x80000000
822 #define CSCONFIG_AP                     0x00800000
823 #define CSCONFIG_ODT_WR_ACS             0x00010000
824 #define CSCONFIG_BANK_BIT_3             0x00004000
825 #define CSCONFIG_ROW_BIT                0x00000700
826 #define CSCONFIG_ROW_BIT_12             0x00000000
827 #define CSCONFIG_ROW_BIT_13             0x00000100
828 #define CSCONFIG_ROW_BIT_14             0x00000200
829 #define CSCONFIG_COL_BIT                0x00000007
830 #define CSCONFIG_COL_BIT_8              0x00000000
831 #define CSCONFIG_COL_BIT_9              0x00000001
832 #define CSCONFIG_COL_BIT_10             0x00000002
833 #define CSCONFIG_COL_BIT_11             0x00000003
834
835 /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
836  */
837 #define TIMING_CFG0_RWT                 0xC0000000
838 #define TIMING_CFG0_RWT_SHIFT           30
839 #define TIMING_CFG0_WRT                 0x30000000
840 #define TIMING_CFG0_WRT_SHIFT           28
841 #define TIMING_CFG0_RRT                 0x0C000000
842 #define TIMING_CFG0_RRT_SHIFT           26
843 #define TIMING_CFG0_WWT                 0x03000000
844 #define TIMING_CFG0_WWT_SHIFT           24
845 #define TIMING_CFG0_ACT_PD_EXIT         0x00700000
846 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT   20
847 #define TIMING_CFG0_PRE_PD_EXIT         0x00070000
848 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT   16
849 #define TIMING_CFG0_ODT_PD_EXIT         0x00000F00
850 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT   8
851 #define TIMING_CFG0_MRS_CYC             0x0000000F
852 #define TIMING_CFG0_MRS_CYC_SHIFT       0
853
854 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
855  */
856 #define TIMING_CFG1_PRETOACT            0x70000000
857 #define TIMING_CFG1_PRETOACT_SHIFT      28
858 #define TIMING_CFG1_ACTTOPRE            0x0F000000
859 #define TIMING_CFG1_ACTTOPRE_SHIFT      24
860 #define TIMING_CFG1_ACTTORW             0x00700000
861 #define TIMING_CFG1_ACTTORW_SHIFT       20
862 #define TIMING_CFG1_CASLAT              0x00070000
863 #define TIMING_CFG1_CASLAT_SHIFT        16
864 #define TIMING_CFG1_REFREC              0x0000F000
865 #define TIMING_CFG1_REFREC_SHIFT        12
866 #define TIMING_CFG1_WRREC               0x00000700
867 #define TIMING_CFG1_WRREC_SHIFT         8
868 #define TIMING_CFG1_ACTTOACT            0x00000070
869 #define TIMING_CFG1_ACTTOACT_SHIFT      4
870 #define TIMING_CFG1_WRTORD              0x00000007
871 #define TIMING_CFG1_WRTORD_SHIFT        0
872 #define TIMING_CFG1_CASLAT_20           0x00030000      /* CAS latency = 2.0 */
873 #define TIMING_CFG1_CASLAT_25           0x00040000      /* CAS latency = 2.5 */
874 #define TIMING_CFG1_CASLAT_30           0x00050000      /* CAS latency = 2.5 */
875
876 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
877  */
878 #define TIMING_CFG2_CPO                 0x0F800000
879 #define TIMING_CFG2_CPO_SHIFT           23
880 #define TIMING_CFG2_ACSM                0x00080000
881 #define TIMING_CFG2_WR_DATA_DELAY       0x00001C00
882 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
883 #define TIMING_CFG2_CPO_DEF             0x00000000      /* default (= CASLAT + 1) */
884
885 #define TIMING_CFG2_ADD_LAT             0x70000000
886 #define TIMING_CFG2_ADD_LAT_SHIFT       28
887 #define TIMING_CFG2_WR_LAT_DELAY        0x00380000
888 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT  19
889 #define TIMING_CFG2_RD_TO_PRE           0x0000E000
890 #define TIMING_CFG2_RD_TO_PRE_SHIFT     13
891 #define TIMING_CFG2_CKE_PLS             0x000001C0
892 #define TIMING_CFG2_CKE_PLS_SHIFT       6
893 #define TIMING_CFG2_FOUR_ACT            0x0000003F
894 #define TIMING_CFG2_FOUR_ACT_SHIFT      0
895
896 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
897  */
898 #define SDRAM_CFG_MEM_EN                0x80000000
899 #define SDRAM_CFG_SREN                  0x40000000
900 #define SDRAM_CFG_ECC_EN                0x20000000
901 #define SDRAM_CFG_RD_EN                 0x10000000
902 #define SDRAM_CFG_SDRAM_TYPE_DDR1       0x02000000
903 #define SDRAM_CFG_SDRAM_TYPE_DDR2       0x03000000
904 #define SDRAM_CFG_SDRAM_TYPE_MASK       0x07000000
905 #define SDRAM_CFG_SDRAM_TYPE_SHIFT      24
906 #define SDRAM_CFG_DYN_PWR               0x00200000
907 #define SDRAM_CFG_32_BE                 0x00080000
908 #define SDRAM_CFG_8_BE                  0x00040000
909 #define SDRAM_CFG_NCAP                  0x00020000
910 #define SDRAM_CFG_2T_EN                 0x00008000
911 #define SDRAM_CFG_BI                    0x00000001
912
913 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register
914  */
915 #define SDRAM_MODE_ESD                  0xFFFF0000
916 #define SDRAM_MODE_ESD_SHIFT            16
917 #define SDRAM_MODE_SD                   0x0000FFFF
918 #define SDRAM_MODE_SD_SHIFT             0
919 #define DDR_MODE_EXT_MODEREG            0x4000          /* select extended mode reg */
920 #define DDR_MODE_EXT_OPMODE             0x3FF8          /* operating mode, mask */
921 #define DDR_MODE_EXT_OP_NORMAL          0x0000          /* normal operation */
922 #define DDR_MODE_QFC                    0x0004          /* QFC / compatibility, mask */
923 #define DDR_MODE_QFC_COMP               0x0000          /* compatible to older SDRAMs */
924 #define DDR_MODE_WEAK                   0x0002          /* weak drivers */
925 #define DDR_MODE_DLL_DIS                0x0001          /* disable DLL */
926 #define DDR_MODE_CASLAT                 0x0070          /* CAS latency, mask */
927 #define DDR_MODE_CASLAT_15              0x0010          /* CAS latency 1.5 */
928 #define DDR_MODE_CASLAT_20              0x0020          /* CAS latency 2 */
929 #define DDR_MODE_CASLAT_25              0x0060          /* CAS latency 2.5 */
930 #define DDR_MODE_CASLAT_30              0x0030          /* CAS latency 3 */
931 #define DDR_MODE_BTYPE_SEQ              0x0000          /* sequential burst */
932 #define DDR_MODE_BTYPE_ILVD             0x0008          /* interleaved burst */
933 #define DDR_MODE_BLEN_2                 0x0001          /* burst length 2 */
934 #define DDR_MODE_BLEN_4                 0x0002          /* burst length 4 */
935 #define DDR_REFINT_166MHZ_7US           1302            /* exact value for 7.8125us */
936 #define DDR_BSTOPRE                     256             /* use 256 cycles as a starting point */
937 #define DDR_MODE_MODEREG                0x0000          /* select mode register */
938
939 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
940  */
941 #define SDRAM_INTERVAL_REFINT           0x3FFF0000
942 #define SDRAM_INTERVAL_REFINT_SHIFT     16
943 #define SDRAM_INTERVAL_BSTOPRE          0x00003FFF
944 #define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
945
946 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
947  */
948 #define DDR_SDRAM_CLK_CNTL_SS_EN                0x80000000
949 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025       0x01000000
950 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05        0x02000000
951 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075       0x03000000
952 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1         0x04000000
953
954 /* ECC_ERR_INJECT - Memory data path error injection mask ECC
955  */
956 #define ECC_ERR_INJECT_EMB              (0x80000000>>22)        /* ECC Mirror Byte */
957 #define ECC_ERR_INJECT_EIEN             (0x80000000>>23)        /* Error Injection Enable */
958 #define ECC_ERR_INJECT_EEIM             (0xff000000>>24)        /* ECC Erroe Injection Enable */
959 #define ECC_ERR_INJECT_EEIM_SHIFT       0
960
961 /* CAPTURE_ECC - Memory data path read capture ECC
962  */
963 #define CAPTURE_ECC_ECE                 (0xff000000>>24)
964 #define CAPTURE_ECC_ECE_SHIFT           0
965
966 /* ERR_DETECT - Memory error detect
967  */
968 #define ECC_ERROR_DETECT_MME            (0x80000000>>0)         /* Multiple Memory Errors */
969 #define ECC_ERROR_DETECT_MBE            (0x80000000>>28)        /* Multiple-Bit Error */
970 #define ECC_ERROR_DETECT_SBE            (0x80000000>>29)        /* Single-Bit ECC Error Pickup */
971 #define ECC_ERROR_DETECT_MSE            (0x80000000>>31)        /* Memory Select Error */
972
973 /* ERR_DISABLE - Memory error disable
974  */
975 #define ECC_ERROR_DISABLE_MBED          (0x80000000>>28)        /* Multiple-Bit ECC Error Disable */
976 #define ECC_ERROR_DISABLE_SBED          (0x80000000>>29)        /* Sinle-Bit ECC Error disable */
977 #define ECC_ERROR_DISABLE_MSED          (0x80000000>>31)        /* Memory Select Error Disable */
978 #define ECC_ERROR_ENABLE                ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
979                                          ECC_ERROR_DISABLE_MBED)
980 /* ERR_INT_EN - Memory error interrupt enable
981  */
982 #define ECC_ERR_INT_EN_MBEE             (0x80000000>>28)        /* Multiple-Bit ECC Error Interrupt Enable */
983 #define ECC_ERR_INT_EN_SBEE             (0x80000000>>29)        /* Single-Bit ECC Error Interrupt Enable */
984 #define ECC_ERR_INT_EN_MSEE             (0x80000000>>31)        /* Memory Select Error Interrupt Enable */
985 #define ECC_ERR_INT_DISABLE             ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
986                                          ECC_ERR_INT_EN_MSEE)
987 /* CAPTURE_ATTRIBUTES - Memory error attributes capture
988  */
989 #define ECC_CAPT_ATTR_BNUM              (0xe0000000>>1)         /* Data Beat Num */
990 #define ECC_CAPT_ATTR_BNUM_SHIFT        28
991 #define ECC_CAPT_ATTR_TSIZ              (0xc0000000>>6)         /* Transaction Size */
992 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW      0
993 #define ECC_CAPT_ATTR_TSIZ_ONE_DW       1
994 #define ECC_CAPT_ATTR_TSIZ_TWO_DW       2
995 #define ECC_CAPT_ATTR_TSIZ_THREE_DW     3
996 #define ECC_CAPT_ATTR_TSIZ_SHIFT        24
997 #define ECC_CAPT_ATTR_TSRC              (0xf8000000>>11)        /* Transaction Source */
998 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
999 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
1000 #define ECC_CAPT_ATTR_TSRC_TSEC1        0x4
1001 #define ECC_CAPT_ATTR_TSRC_TSEC2        0x5
1002 #define ECC_CAPT_ATTR_TSRC_USB          (0x06|0x07)
1003 #define ECC_CAPT_ATTR_TSRC_ENCRYPT      0x8
1004 #define ECC_CAPT_ATTR_TSRC_I2C          0x9
1005 #define ECC_CAPT_ATTR_TSRC_JTAG         0xA
1006 #define ECC_CAPT_ATTR_TSRC_PCI1         0xD
1007 #define ECC_CAPT_ATTR_TSRC_PCI2         0xE
1008 #define ECC_CAPT_ATTR_TSRC_DMA          0xF
1009 #define ECC_CAPT_ATTR_TSRC_SHIFT        16
1010 #define ECC_CAPT_ATTR_TTYP              (0xe0000000>>18)        /* Transaction Type */
1011 #define ECC_CAPT_ATTR_TTYP_WRITE        0x1
1012 #define ECC_CAPT_ATTR_TTYP_READ         0x2
1013 #define ECC_CAPT_ATTR_TTYP_R_M_W        0x3
1014 #define ECC_CAPT_ATTR_TTYP_SHIFT        12
1015 #define ECC_CAPT_ATTR_VLD               (0x80000000>>31)        /* Valid */
1016
1017 /* ERR_SBE - Single bit ECC memory error management
1018  */
1019 #define ECC_ERROR_MAN_SBET              (0xff000000>>8)         /* Single-Bit Error Threshold 0..255 */
1020 #define ECC_ERROR_MAN_SBET_SHIFT        16
1021 #define ECC_ERROR_MAN_SBEC              (0xff000000>>24)        /* Single Bit Error Counter 0..255 */
1022 #define ECC_ERROR_MAN_SBEC_SHIFT        0
1023
1024 /* DMAMR - DMA Mode Register
1025  */
1026 #define DMA_CHANNEL_START                       0x00000001      /* Bit - DMAMRn CS */
1027 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT        0x00000004      /* Bit - DMAMRn CTM */
1028 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN      0x00001000      /* Bit - DMAMRn SAHE */
1029 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B      0x00000000      /* 2Bit- DMAMRn SAHTS 1byte */
1030 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B      0x00004000      /* 2Bit- DMAMRn SAHTS 2bytes */
1031 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B      0x00008000      /* 2Bit- DMAMRn SAHTS 4bytes */
1032 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B      0x0000c000      /* 2Bit- DMAMRn SAHTS 8bytes */
1033 #define DMA_CHANNEL_SNOOP                       0x00010000      /* Bit - DMAMRn DMSEN */
1034
1035 /* DMASR - DMA Status Register
1036  */
1037 #define DMA_CHANNEL_BUSY                        0x00000004      /* Bit - DMASRn CB */
1038 #define DMA_CHANNEL_TRANSFER_ERROR              0x00000080      /* Bit - DMASRn TE */
1039
1040 /* CONFIG_ADDRESS - PCI Config Address Register
1041  */
1042 #define PCI_CONFIG_ADDRESS_EN           0x80000000
1043 #define PCI_CONFIG_ADDRESS_BN_SHIFT     16
1044 #define PCI_CONFIG_ADDRESS_BN_MASK      0x00ff0000
1045 #define PCI_CONFIG_ADDRESS_DN_SHIFT     11
1046 #define PCI_CONFIG_ADDRESS_DN_MASK      0x0000f800
1047 #define PCI_CONFIG_ADDRESS_FN_SHIFT     8
1048 #define PCI_CONFIG_ADDRESS_FN_MASK      0x00000700
1049 #define PCI_CONFIG_ADDRESS_RN_SHIFT     0
1050 #define PCI_CONFIG_ADDRESS_RN_MASK      0x000000fc
1051
1052 /* POTAR - PCI Outbound Translation Address Register
1053  */
1054 #define POTAR_TA_MASK                   0x000fffff
1055
1056 /* POBAR - PCI Outbound Base Address Register
1057  */
1058 #define POBAR_BA_MASK                   0x000fffff
1059
1060 /* POCMR - PCI Outbound Comparision Mask Register
1061  */
1062 #define POCMR_EN                        0x80000000
1063 #define POCMR_IO                        0x40000000      /* 0-memory space 1-I/O space */
1064 #define POCMR_SE                        0x20000000      /* streaming enable */
1065 #define POCMR_DST                       0x10000000      /* 0-PCI1 1-PCI2 */
1066 #define POCMR_CM_MASK                   0x000fffff
1067 #define POCMR_CM_4G                     0x00000000
1068 #define POCMR_CM_2G                     0x00080000
1069 #define POCMR_CM_1G                     0x000C0000
1070 #define POCMR_CM_512M                   0x000E0000
1071 #define POCMR_CM_256M                   0x000F0000
1072 #define POCMR_CM_128M                   0x000F8000
1073 #define POCMR_CM_64M                    0x000FC000
1074 #define POCMR_CM_32M                    0x000FE000
1075 #define POCMR_CM_16M                    0x000FF000
1076 #define POCMR_CM_8M                     0x000FF800
1077 #define POCMR_CM_4M                     0x000FFC00
1078 #define POCMR_CM_2M                     0x000FFE00
1079 #define POCMR_CM_1M                     0x000FFF00
1080 #define POCMR_CM_512K                   0x000FFF80
1081 #define POCMR_CM_256K                   0x000FFFC0
1082 #define POCMR_CM_128K                   0x000FFFE0
1083 #define POCMR_CM_64K                    0x000FFFF0
1084 #define POCMR_CM_32K                    0x000FFFF8
1085 #define POCMR_CM_16K                    0x000FFFFC
1086 #define POCMR_CM_8K                     0x000FFFFE
1087 #define POCMR_CM_4K                     0x000FFFFF
1088
1089 /* PITAR - PCI Inbound Translation Address Register
1090  */
1091 #define PITAR_TA_MASK                   0x000fffff
1092
1093 /* PIBAR - PCI Inbound Base/Extended Address Register
1094  */
1095 #define PIBAR_MASK                      0xffffffff
1096 #define PIEBAR_EBA_MASK                 0x000fffff
1097
1098 /* PIWAR - PCI Inbound Windows Attributes Register
1099  */
1100 #define PIWAR_EN                        0x80000000
1101 #define PIWAR_PF                        0x20000000
1102 #define PIWAR_RTT_MASK                  0x000f0000
1103 #define PIWAR_RTT_NO_SNOOP              0x00040000
1104 #define PIWAR_RTT_SNOOP                 0x00050000
1105 #define PIWAR_WTT_MASK                  0x0000f000
1106 #define PIWAR_WTT_NO_SNOOP              0x00004000
1107 #define PIWAR_WTT_SNOOP                 0x00005000
1108 #define PIWAR_IWS_MASK                  0x0000003F
1109 #define PIWAR_IWS_4K                    0x0000000B
1110 #define PIWAR_IWS_8K                    0x0000000C
1111 #define PIWAR_IWS_16K                   0x0000000D
1112 #define PIWAR_IWS_32K                   0x0000000E
1113 #define PIWAR_IWS_64K                   0x0000000F
1114 #define PIWAR_IWS_128K                  0x00000010
1115 #define PIWAR_IWS_256K                  0x00000011
1116 #define PIWAR_IWS_512K                  0x00000012
1117 #define PIWAR_IWS_1M                    0x00000013
1118 #define PIWAR_IWS_2M                    0x00000014
1119 #define PIWAR_IWS_4M                    0x00000015
1120 #define PIWAR_IWS_8M                    0x00000016
1121 #define PIWAR_IWS_16M                   0x00000017
1122 #define PIWAR_IWS_32M                   0x00000018
1123 #define PIWAR_IWS_64M                   0x00000019
1124 #define PIWAR_IWS_128M                  0x0000001A
1125 #define PIWAR_IWS_256M                  0x0000001B
1126 #define PIWAR_IWS_512M                  0x0000001C
1127 #define PIWAR_IWS_1G                    0x0000001D
1128 #define PIWAR_IWS_2G                    0x0000001E
1129
1130 /* PMCCR1 - PCI Configuration Register 1
1131  */
1132 #define PMCCR1_POWER_OFF                0x00000020
1133
1134 /* FMR - Flash Mode Register
1135  */
1136 #define FMR_CWTO                0x0000F000
1137 #define FMR_CWTO_SHIFT          12
1138 #define FMR_BOOT                0x00000800
1139 #define FMR_ECCM                0x00000100
1140 #define FMR_AL                  0x00000030
1141 #define FMR_AL_SHIFT            4
1142 #define FMR_OP                  0x00000003
1143 #define FMR_OP_SHIFT            0
1144
1145 /* FIR - Flash Instruction Register
1146  */
1147 #define FIR_OP0                 0xF0000000
1148 #define FIR_OP0_SHIFT           28
1149 #define FIR_OP1                 0x0F000000
1150 #define FIR_OP1_SHIFT           24
1151 #define FIR_OP2                 0x00F00000
1152 #define FIR_OP2_SHIFT           20
1153 #define FIR_OP3                 0x000F0000
1154 #define FIR_OP3_SHIFT           16
1155 #define FIR_OP4                 0x0000F000
1156 #define FIR_OP4_SHIFT           12
1157 #define FIR_OP5                 0x00000F00
1158 #define FIR_OP5_SHIFT           8
1159 #define FIR_OP6                 0x000000F0
1160 #define FIR_OP6_SHIFT           4
1161 #define FIR_OP7                 0x0000000F
1162 #define FIR_OP7_SHIFT           0
1163 #define FIR_OP_NOP              0x0 /* No operation and end of sequence */
1164 #define FIR_OP_CA               0x1 /* Issue current column address */
1165 #define FIR_OP_PA               0x2 /* Issue current block+page address */
1166 #define FIR_OP_UA               0x3 /* Issue user defined address */
1167 #define FIR_OP_CM0              0x4 /* Issue command from FCR[CMD0] */
1168 #define FIR_OP_CM1              0x5 /* Issue command from FCR[CMD1] */
1169 #define FIR_OP_CM2              0x6 /* Issue command from FCR[CMD2] */
1170 #define FIR_OP_CM3              0x7 /* Issue command from FCR[CMD3] */
1171 #define FIR_OP_WB               0x8 /* Write FBCR bytes from FCM buffer */
1172 #define FIR_OP_WS               0x9 /* Write 1 or 2 bytes from MDR[AS] */
1173 #define FIR_OP_RB               0xA /* Read FBCR bytes to FCM buffer */
1174 #define FIR_OP_RS               0xB /* Read 1 or 2 bytes to MDR[AS] */
1175 #define FIR_OP_CW0              0xC /* Wait then issue FCR[CMD0] */
1176 #define FIR_OP_CW1              0xD /* Wait then issue FCR[CMD1] */
1177 #define FIR_OP_RBW              0xE /* Wait then read FBCR bytes */
1178 #define FIR_OP_RSW              0xF /* Wait then read 1 or 2 bytes */
1179
1180 /* FCR - Flash Command Register
1181  */
1182 #define FCR_CMD0                0xFF000000
1183 #define FCR_CMD0_SHIFT          24
1184 #define FCR_CMD1                0x00FF0000
1185 #define FCR_CMD1_SHIFT          16
1186 #define FCR_CMD2                0x0000FF00
1187 #define FCR_CMD2_SHIFT          8
1188 #define FCR_CMD3                0x000000FF
1189 #define FCR_CMD3_SHIFT          0
1190
1191 /* FBAR - Flash Block Address Register
1192  */
1193 #define FBAR_BLK                0x00FFFFFF
1194
1195 /* FPAR - Flash Page Address Register
1196  */
1197 #define FPAR_SP_PI              0x00007C00
1198 #define FPAR_SP_PI_SHIFT        10
1199 #define FPAR_SP_MS              0x00000200
1200 #define FPAR_SP_CI              0x000001FF
1201 #define FPAR_SP_CI_SHIFT        0
1202 #define FPAR_LP_PI              0x0003F000
1203 #define FPAR_LP_PI_SHIFT        12
1204 #define FPAR_LP_MS              0x00000800
1205 #define FPAR_LP_CI              0x000007FF
1206 #define FPAR_LP_CI_SHIFT        0
1207
1208 /* LTESR - Transfer Error Status Register
1209  */
1210 #define LTESR_BM                0x80000000
1211 #define LTESR_FCT               0x40000000
1212 #define LTESR_PAR               0x20000000
1213 #define LTESR_WP                0x04000000
1214 #define LTESR_ATMW              0x00800000
1215 #define LTESR_ATMR              0x00400000
1216 #define LTESR_CS                0x00080000
1217 #define LTESR_CC                0x00000001
1218
1219 /* DDRCDR - DDR Control Driver Register
1220  */
1221 #define DDRCDR_DHC_EN           0x80000000
1222 #define DDRCDR_EN               0x40000000
1223 #define DDRCDR_PZ               0x3C000000
1224 #define DDRCDR_PZ_MAXZ          0x00000000
1225 #define DDRCDR_PZ_HIZ           0x20000000
1226 #define DDRCDR_PZ_NOMZ          0x30000000
1227 #define DDRCDR_PZ_LOZ           0x38000000
1228 #define DDRCDR_PZ_MINZ          0x3C000000
1229 #define DDRCDR_NZ               0x3C000000
1230 #define DDRCDR_NZ_MAXZ          0x00000000
1231 #define DDRCDR_NZ_HIZ           0x02000000
1232 #define DDRCDR_NZ_NOMZ          0x03000000
1233 #define DDRCDR_NZ_LOZ           0x03800000
1234 #define DDRCDR_NZ_MINZ          0x03C00000
1235 #define DDRCDR_ODT              0x00080000
1236 #define DDRCDR_DDR_CFG          0x00040000
1237 #define DDRCDR_M_ODR            0x00000002
1238 #define DDRCDR_Q_DRN            0x00000001
1239
1240 #ifndef __ASSEMBLY__
1241 struct pci_region;
1242 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
1243 #endif
1244
1245 #endif  /* __MPC83XX_H__ */