include/mc9sdz60.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de>
   4  *
   5  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   6  */
   7
   8 #ifndef __ASM_ARCH_MC9SDZ60_H
   9 #define __ASM_ARCH_MC9SDZ60_H
  10
  11 /**
  12  * Register addresses for the MC9SDZ60
  13  *
  14  * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h
  15  * but not include/linux/mfd/mc9s08dz60/pmic.h
  16  *
  17  */
  18 enum mc9sdz60_reg {
  19         MC9SDZ60_REG_VERSION            = 0x00,
  20         /* reserved                       0x01 */
  21         MC9SDZ60_REG_SECS               = 0x02,
  22         MC9SDZ60_REG_MINS               = 0x03,
  23         MC9SDZ60_REG_HRS                = 0x04,
  24         MC9SDZ60_REG_DAY                = 0x05,
  25         MC9SDZ60_REG_DATE               = 0x06,
  26         MC9SDZ60_REG_MONTH              = 0x07,
  27         MC9SDZ60_REG_YEAR               = 0x08,
  28         MC9SDZ60_REG_ALARM_SECS         = 0x09,
  29         MC9SDZ60_REG_ALARM_MINS         = 0x0a,
  30         MC9SDZ60_REG_ALARM_HRS          = 0x0b,
  31         /* reserved                       0x0c */
  32         /* reserved                       0x0d */
  33         MC9SDZ60_REG_TS_CONTROL         = 0x0e,
  34         MC9SDZ60_REG_X_LOW              = 0x0f,
  35         MC9SDZ60_REG_Y_LOW              = 0x10,
  36         MC9SDZ60_REG_XY_HIGH            = 0x11,
  37         MC9SDZ60_REG_X_LEFT_LOW         = 0x12,
  38         MC9SDZ60_REG_X_LEFT_HIGH        = 0x13,
  39         MC9SDZ60_REG_X_RIGHT            = 0x14,
  40         MC9SDZ60_REG_Y_TOP_LOW          = 0x15,
  41         MC9SDZ60_REG_Y_TOP_HIGH         = 0x16,
  42         MC9SDZ60_REG_Y_BOTTOM           = 0x17,
  43         /* reserved                       0x18 */
  44         /* reserved                       0x19 */
  45         MC9SDZ60_REG_RESET_1            = 0x1a,
  46         MC9SDZ60_REG_RESET_2            = 0x1b,
  47         MC9SDZ60_REG_POWER_CTL          = 0x1c,
  48         MC9SDZ60_REG_DELAY_CONFIG       = 0x1d,
  49         /* reserved                       0x1e */
  50         /* reserved                       0x1f */
  51         MC9SDZ60_REG_GPIO_1             = 0x20,
  52         MC9SDZ60_REG_GPIO_2             = 0x21,
  53         MC9SDZ60_REG_KPD_1              = 0x22,
  54         MC9SDZ60_REG_KPD_2              = 0x23,
  55         MC9SDZ60_REG_KPD_CONTROL        = 0x24,
  56         MC9SDZ60_REG_INT_ENABLE_1       = 0x25,
  57         MC9SDZ60_REG_INT_ENABLE_2       = 0x26,
  58         MC9SDZ60_REG_INT_FLAG_1         = 0x27,
  59         MC9SDZ60_REG_INT_FLAG_2         = 0x28,
  60         MC9SDZ60_REG_DES_FLAG           = 0x29,
  61 };
  62
  63 extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg);
  64 extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val);
  65
  66 #endif /* __ASM_ARCH_MC9SDZ60_H */