1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Texas Instruments Inc, <www.ti.com>
6 * Author: Dan Murphy <dmurphy@ti.com>
9 #ifndef _ASM_ARCH_XHCI_OMAP_H_
10 #define _ASM_ARCH_XHCI_OMAP_H_
13 #if CONFIG_USB_XHCI_DRA7XX_INDEX == 1
14 #define OMAP_XHCI_BASE 0x488d0000
15 #define OMAP_OCP1_SCP_BASE 0x4A081000
16 #define OMAP_OTG_WRAPPER_BASE 0x488c0000
17 #elif CONFIG_USB_XHCI_DRA7XX_INDEX == 0
18 #define OMAP_XHCI_BASE 0x48890000
19 #define OMAP_OCP1_SCP_BASE 0x4A084c00
20 #define OMAP_OTG_WRAPPER_BASE 0x48880000
21 #endif /* CONFIG_USB_XHCI_DRA7XX_INDEX == 1 */
22 #elif defined CONFIG_AM43XX
23 #define OMAP_XHCI_BASE 0x483d0000
24 #define OMAP_OCP1_SCP_BASE 0x483E8000
25 #define OMAP_OTG_WRAPPER_BASE 0x483dc100
27 /* Default to the OMAP5 XHCI defines */
28 #define OMAP_XHCI_BASE 0x4a030000
29 #define OMAP_OCP1_SCP_BASE 0x4a084c00
30 #define OMAP_OTG_WRAPPER_BASE 0x4A020000
33 /* Phy register MACRO definitions */
34 #define PLL_REGM_MASK 0x001FFE00
35 #define PLL_REGM_SHIFT 0x9
36 #define PLL_REGM_F_MASK 0x0003FFFF
37 #define PLL_REGM_F_SHIFT 0x0
38 #define PLL_REGN_MASK 0x000001FE
39 #define PLL_REGN_SHIFT 0x1
40 #define PLL_SELFREQDCO_MASK 0x0000000E
41 #define PLL_SELFREQDCO_SHIFT 0x1
42 #define PLL_SD_MASK 0x0003FC00
43 #define PLL_SD_SHIFT 0x9
44 #define SET_PLL_GO 0x1
45 #define PLL_TICOPWDN 0x10000
49 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
50 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
51 #define USB3_PHY_PARTIAL_RX_POWERON (1 << 6)
52 #define USB3_PHY_RX_POWERON (1 << 14)
53 #define USB3_PHY_TX_POWERON (1 << 15)
54 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
55 #define USB3_PWRCTL_CLK_CMD_SHIFT 14
56 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22
58 /* USBOTGSS_WRAPPER definitions */
59 #define USBOTGSS_WRAPRESET (1 << 17)
60 #define USBOTGSS_DMADISABLE (1 << 16)
61 #define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4)
62 #define USBOTGSS_STANDBYMODE_SMRT (1 << 5)
63 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
64 #define USBOTGSS_IDLEMODE_NOIDLE (1 << 2)
65 #define USBOTGSS_IDLEMODE_SMRT (1 << 3)
66 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
68 /* USBOTGSS_IRQENABLE_SET_0 bit */
69 #define USBOTGSS_COREIRQ_EN (1 << 0)
71 /* USBOTGSS_IRQENABLE_SET_1 bits */
72 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0)
73 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3)
74 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4)
75 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5)
76 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8)
77 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11)
78 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12)
79 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13)
80 #define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16)
81 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17)
84 * USBOTGSS_WRAPPER registers
86 struct omap_dwc_wrapper {
91 u32 sysconfig; /* offset of 0x10 */
96 u32 irqstatus_raw_0; /* offset of 0x24 */
101 u32 irqstatus_raw_1; /* offset of 0x34 */
108 u32 utmi_otg_ctrl; /* offset of 0x80 */
113 u32 mram_offset; /* offset of 0x100 */
120 /* XHCI PHY register structure */
121 struct omap_usb3_phy {
128 u32 pll_ssc_config_1;
129 u32 pll_ssc_config_2;
134 struct omap_dwc_wrapper *otg_wrapper;
135 struct omap_usb3_phy *usb3_phy;
136 struct xhci_hccr *hcd;
137 struct dwc3 *dwc3_reg;
140 /* USB PHY functions */
141 void omap_enable_phy(struct omap_xhci *omap);
142 void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
143 void usb_phy_power(int on);
145 #endif /* _ASM_ARCH_XHCI_OMAP_H_ */