2 * Microsemi Switchtec PCIe Driver
3 * Copyright (c) 2017, Microsemi Corporation
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 #include <linux/pci.h>
20 #include <linux/cdev.h>
22 #define MICROSEMI_VENDOR_ID 0x11f8
23 #define MICROSEMI_NTB_CLASSCODE 0x068000
24 #define MICROSEMI_MGMT_CLASSCODE 0x058000
26 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
27 #define SWITCHTEC_MAX_PFF_CSR 48
29 #define SWITCHTEC_EVENT_OCCURRED BIT(0)
30 #define SWITCHTEC_EVENT_CLEAR BIT(0)
31 #define SWITCHTEC_EVENT_EN_LOG BIT(1)
32 #define SWITCHTEC_EVENT_EN_CLI BIT(2)
33 #define SWITCHTEC_EVENT_EN_IRQ BIT(3)
34 #define SWITCHTEC_EVENT_FATAL BIT(4)
37 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
38 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
39 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
40 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
41 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
42 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
43 SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
44 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
48 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
49 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
56 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
57 SWITCHTEC_MRPC_STATUS_DONE = 2,
58 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
59 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
62 struct sw_event_regs {
63 u64 event_report_ctrl;
65 u64 part_event_bitmap;
69 u32 stack_error_event_hdr;
70 u32 stack_error_event_data;
72 u32 ppu_error_event_hdr;
73 u32 ppu_error_event_data;
75 u32 isp_error_event_hdr;
76 u32 isp_error_event_data;
78 u32 sys_reset_event_hdr;
88 u32 twi_mrpc_comp_hdr;
89 u32 twi_mrpc_comp_data;
91 u32 twi_mrpc_comp_async_hdr;
92 u32 twi_mrpc_comp_async_data;
94 u32 cli_mrpc_comp_hdr;
95 u32 cli_mrpc_comp_data;
97 u32 cli_mrpc_comp_async_hdr;
98 u32 cli_mrpc_comp_async_data;
100 u32 gpio_interrupt_hdr;
101 u32 gpio_interrupt_data;
106 SWITCHTEC_CFG0_RUNNING = 0x04,
107 SWITCHTEC_CFG1_RUNNING = 0x05,
108 SWITCHTEC_IMG0_RUNNING = 0x03,
109 SWITCHTEC_IMG1_RUNNING = 0x07,
112 struct sys_info_regs {
115 u32 firmware_version;
117 u32 vendor_table_revision;
118 u32 table_format_version;
120 u32 cfg_file_fmt_version;
126 char product_revision[4];
127 char component_vendor[8];
129 u8 component_revision;
132 struct flash_info_regs {
133 u32 flash_part_map_upd_idx;
135 struct active_partition_info {
141 struct active_partition_info active_cfg;
142 struct active_partition_info inactive_img;
143 struct active_partition_info inactive_cfg;
147 struct partition_info {
152 struct partition_info cfg1;
153 struct partition_info img0;
154 struct partition_info img1;
155 struct partition_info nvlog;
156 struct partition_info vendor[8];
160 SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
161 SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
162 SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
165 struct ntb_info_regs {
173 struct part_cfg_regs {
180 u32 dsp_pff_inst_id[47];
182 u16 vep_vector_number;
183 u16 usp_vector_number;
184 u32 port_event_bitmap;
186 u32 part_event_summary;
189 u32 part_reset_data[5];
191 u32 mrpc_comp_data[5];
192 u32 mrpc_comp_async_hdr;
193 u32 mrpc_comp_async_data[5];
195 u32 dyn_binding_data[5];
200 NTB_CTRL_PART_OP_LOCK = 0x1,
201 NTB_CTRL_PART_OP_CFG = 0x2,
202 NTB_CTRL_PART_OP_RESET = 0x3,
204 NTB_CTRL_PART_STATUS_NORMAL = 0x1,
205 NTB_CTRL_PART_STATUS_LOCKED = 0x2,
206 NTB_CTRL_PART_STATUS_LOCKING = 0x3,
207 NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
208 NTB_CTRL_PART_STATUS_RESETTING = 0x5,
210 NTB_CTRL_BAR_VALID = 1 << 0,
211 NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
212 NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
214 NTB_CTRL_REQ_ID_EN = 1 << 0,
216 NTB_CTRL_LUT_EN = 1 << 0,
218 NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
221 struct ntb_ctrl_regs {
222 u32 partition_status;
227 u16 lut_table_entries;
228 u16 lut_table_offset;
230 u16 req_id_table_size;
231 u16 req_id_table_offset;
240 u32 req_id_table[256];
245 #define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
246 #define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
248 struct ntb_dbmsg_regs {
278 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
279 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
280 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
281 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
284 struct pff_csr_regs {
287 u32 pci_cfg_header[15];
288 u32 pci_cap_region[48];
289 u32 pcie_cap_region[448];
290 u32 indirect_gas_window[128];
291 u32 indirect_gas_window_off;
293 u32 pff_event_summary;
296 u32 aer_in_p2p_data[5];
298 u32 aer_in_vep_data[5];
309 u32 threshold_data[5];
311 u32 power_mgmt_data[5];
312 u32 tlp_throttling_hdr;
313 u32 tlp_throttling_data[5];
315 u32 force_speed_data[5];
316 u32 credit_timeout_hdr;
317 u32 credit_timeout_data[5];
319 u32 link_state_data[5];
323 struct switchtec_ntb;
325 struct switchtec_dev {
326 struct pci_dev *pdev;
333 char pff_local[SWITCHTEC_MAX_PFF_CSR];
336 struct mrpc_regs __iomem *mmio_mrpc;
337 struct sw_event_regs __iomem *mmio_sw_event;
338 struct sys_info_regs __iomem *mmio_sys_info;
339 struct flash_info_regs __iomem *mmio_flash_info;
340 struct ntb_info_regs __iomem *mmio_ntb;
341 struct part_cfg_regs __iomem *mmio_part_cfg;
342 struct part_cfg_regs __iomem *mmio_part_cfg_all;
343 struct pff_csr_regs __iomem *mmio_pff_csr;
346 * The mrpc mutex must be held when accessing the other
347 * mrpc_ fields, alive flag and stuser->state field
349 struct mutex mrpc_mutex;
350 struct list_head mrpc_queue;
352 struct work_struct mrpc_work;
353 struct delayed_work mrpc_timeout;
356 wait_queue_head_t event_wq;
359 struct work_struct link_event_work;
360 void (*link_notifier)(struct switchtec_dev *stdev);
361 u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
363 struct switchtec_ntb *sndev;
366 static inline struct switchtec_dev *to_stdev(struct device *dev)
368 return container_of(dev, struct switchtec_dev, dev);
371 extern struct class *switchtec_class;