include/linux/switchtec.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Microsemi Switchtec PCIe Driver
   4  * Copyright (c) 2017, Microsemi Corporation
   5  */
   6
   7 #ifndef _SWITCHTEC_H
   8 #define _SWITCHTEC_H
   9
  10 #include <linux/pci.h>
  11 #include <linux/cdev.h>
  12
  13 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
  14 #define SWITCHTEC_MAX_PFF_CSR 255
  15
  16 #define SWITCHTEC_EVENT_OCCURRED BIT(0)
  17 #define SWITCHTEC_EVENT_CLEAR    BIT(0)
  18 #define SWITCHTEC_EVENT_EN_LOG   BIT(1)
  19 #define SWITCHTEC_EVENT_EN_CLI   BIT(2)
  20 #define SWITCHTEC_EVENT_EN_IRQ   BIT(3)
  21 #define SWITCHTEC_EVENT_FATAL    BIT(4)
  22
  23 #define SWITCHTEC_DMA_MRPC_EN   BIT(0)
  24
  25 #define MRPC_GAS_READ           0x29
  26 #define MRPC_GAS_WRITE          0x87
  27 #define MRPC_CMD_ID(x)          ((x) & 0xffff)
  28
  29 enum {
  30         SWITCHTEC_GAS_MRPC_OFFSET       = 0x0000,
  31         SWITCHTEC_GAS_TOP_CFG_OFFSET    = 0x1000,
  32         SWITCHTEC_GAS_SW_EVENT_OFFSET   = 0x1800,
  33         SWITCHTEC_GAS_SYS_INFO_OFFSET   = 0x2000,
  34         SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
  35         SWITCHTEC_GAS_PART_CFG_OFFSET   = 0x4000,
  36         SWITCHTEC_GAS_NTB_OFFSET        = 0x10000,
  37         SWITCHTEC_GAS_PFF_CSR_OFFSET    = 0x134000,
  38 };
  39
  40 enum switchtec_gen {
  41         SWITCHTEC_GEN3,
  42         SWITCHTEC_GEN4,
  43 };
  44
  45 struct mrpc_regs {
  46         u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
  47         u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
  48         u32 cmd;
  49         u32 status;
  50         u32 ret_value;
  51         u32 dma_en;
  52         u64 dma_addr;
  53         u32 dma_vector;
  54         u32 dma_ver;
  55 } __packed;
  56
  57 enum mrpc_status {
  58         SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
  59         SWITCHTEC_MRPC_STATUS_DONE = 2,
  60         SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
  61         SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
  62 };
  63
  64 struct sw_event_regs {
  65         u64 event_report_ctrl;
  66         u64 reserved1;
  67         u64 part_event_bitmap;
  68         u64 reserved2;
  69         u32 global_summary;
  70         u32 reserved3[3];
  71         u32 stack_error_event_hdr;
  72         u32 stack_error_event_data;
  73         u32 reserved4[4];
  74         u32 ppu_error_event_hdr;
  75         u32 ppu_error_event_data;
  76         u32 reserved5[4];
  77         u32 isp_error_event_hdr;
  78         u32 isp_error_event_data;
  79         u32 reserved6[4];
  80         u32 sys_reset_event_hdr;
  81         u32 reserved7[5];
  82         u32 fw_exception_hdr;
  83         u32 reserved8[5];
  84         u32 fw_nmi_hdr;
  85         u32 reserved9[5];
  86         u32 fw_non_fatal_hdr;
  87         u32 reserved10[5];
  88         u32 fw_fatal_hdr;
  89         u32 reserved11[5];
  90         u32 twi_mrpc_comp_hdr;
  91         u32 twi_mrpc_comp_data;
  92         u32 reserved12[4];
  93         u32 twi_mrpc_comp_async_hdr;
  94         u32 twi_mrpc_comp_async_data;
  95         u32 reserved13[4];
  96         u32 cli_mrpc_comp_hdr;
  97         u32 cli_mrpc_comp_data;
  98         u32 reserved14[4];
  99         u32 cli_mrpc_comp_async_hdr;
 100         u32 cli_mrpc_comp_async_data;
 101         u32 reserved15[4];
 102         u32 gpio_interrupt_hdr;
 103         u32 gpio_interrupt_data;
 104         u32 reserved16[4];
 105         u32 gfms_event_hdr;
 106         u32 gfms_event_data;
 107         u32 reserved17[4];
 108 } __packed;
 109
 110 enum {
 111         SWITCHTEC_GEN3_CFG0_RUNNING = 0x04,
 112         SWITCHTEC_GEN3_CFG1_RUNNING = 0x05,
 113         SWITCHTEC_GEN3_IMG0_RUNNING = 0x03,
 114         SWITCHTEC_GEN3_IMG1_RUNNING = 0x07,
 115 };
 116
 117 enum {
 118         SWITCHTEC_GEN4_MAP0_RUNNING = 0x00,
 119         SWITCHTEC_GEN4_MAP1_RUNNING = 0x01,
 120         SWITCHTEC_GEN4_KEY0_RUNNING = 0x02,
 121         SWITCHTEC_GEN4_KEY1_RUNNING = 0x03,
 122         SWITCHTEC_GEN4_BL2_0_RUNNING = 0x04,
 123         SWITCHTEC_GEN4_BL2_1_RUNNING = 0x05,
 124         SWITCHTEC_GEN4_CFG0_RUNNING = 0x06,
 125         SWITCHTEC_GEN4_CFG1_RUNNING = 0x07,
 126         SWITCHTEC_GEN4_IMG0_RUNNING = 0x08,
 127         SWITCHTEC_GEN4_IMG1_RUNNING = 0x09,
 128 };
 129
 130 enum {
 131         SWITCHTEC_GEN4_KEY0_ACTIVE = 0,
 132         SWITCHTEC_GEN4_KEY1_ACTIVE = 1,
 133         SWITCHTEC_GEN4_BL2_0_ACTIVE = 0,
 134         SWITCHTEC_GEN4_BL2_1_ACTIVE = 1,
 135         SWITCHTEC_GEN4_CFG0_ACTIVE = 0,
 136         SWITCHTEC_GEN4_CFG1_ACTIVE = 1,
 137         SWITCHTEC_GEN4_IMG0_ACTIVE = 0,
 138         SWITCHTEC_GEN4_IMG1_ACTIVE = 1,
 139 };
 140
 141 struct sys_info_regs_gen3 {
 142         u32 reserved1;
 143         u32 vendor_table_revision;
 144         u32 table_format_version;
 145         u32 partition_id;
 146         u32 cfg_file_fmt_version;
 147         u16 cfg_running;
 148         u16 img_running;
 149         u32 reserved2[57];
 150         char vendor_id[8];
 151         char product_id[16];
 152         char product_revision[4];
 153         char component_vendor[8];
 154         u16 component_id;
 155         u8 component_revision;
 156 } __packed;
 157
 158 struct sys_info_regs_gen4 {
 159         u16 gas_layout_ver;
 160         u8 evlist_ver;
 161         u8 reserved1;
 162         u16 mgmt_cmd_set_ver;
 163         u16 fabric_cmd_set_ver;
 164         u32 reserved2[2];
 165         u8 mrpc_uart_ver;
 166         u8 mrpc_twi_ver;
 167         u8 mrpc_eth_ver;
 168         u8 mrpc_inband_ver;
 169         u32 reserved3[7];
 170         u32 fw_update_tmo;
 171         u32 xml_version_cfg;
 172         u32 xml_version_img;
 173         u32 partition_id;
 174         u16 bl2_running;
 175         u16 cfg_running;
 176         u16 img_running;
 177         u16 key_running;
 178         u32 reserved4[43];
 179         u32 vendor_seeprom_twi;
 180         u32 vendor_table_revision;
 181         u32 vendor_specific_info[2];
 182         u16 p2p_vendor_id;
 183         u16 p2p_device_id;
 184         u8 p2p_revision_id;
 185         u8 reserved5[3];
 186         u32 p2p_class_id;
 187         u16 subsystem_vendor_id;
 188         u16 subsystem_id;
 189         u32 p2p_serial_number[2];
 190         u8 mac_addr[6];
 191         u8 reserved6[2];
 192         u32 reserved7[3];
 193         char vendor_id[8];
 194         char product_id[24];
 195         char  product_revision[2];
 196         u16 reserved8;
 197 } __packed;
 198
 199 struct sys_info_regs {
 200         u32 device_id;
 201         u32 device_version;
 202         u32 firmware_version;
 203         union {
 204                 struct sys_info_regs_gen3 gen3;
 205                 struct sys_info_regs_gen4 gen4;
 206         };
 207 } __packed;
 208
 209 struct partition_info {
 210         u32 address;
 211         u32 length;
 212 };
 213
 214 struct flash_info_regs_gen3 {
 215         u32 flash_part_map_upd_idx;
 216
 217         struct active_partition_info_gen3 {
 218                 u32 address;
 219                 u32 build_version;
 220                 u32 build_string;
 221         } active_img;
 222
 223         struct active_partition_info_gen3 active_cfg;
 224         struct active_partition_info_gen3 inactive_img;
 225         struct active_partition_info_gen3 inactive_cfg;
 226
 227         u32 flash_length;
 228
 229         struct partition_info cfg0;
 230         struct partition_info cfg1;
 231         struct partition_info img0;
 232         struct partition_info img1;
 233         struct partition_info nvlog;
 234         struct partition_info vendor[8];
 235 };
 236
 237 struct flash_info_regs_gen4 {
 238         u32 flash_address;
 239         u32 flash_length;
 240
 241         struct active_partition_info_gen4 {
 242                 unsigned char bl2;
 243                 unsigned char cfg;
 244                 unsigned char img;
 245                 unsigned char key;
 246         } active_flag;
 247
 248         u32 reserved[3];
 249
 250         struct partition_info map0;
 251         struct partition_info map1;
 252         struct partition_info key0;
 253         struct partition_info key1;
 254         struct partition_info bl2_0;
 255         struct partition_info bl2_1;
 256         struct partition_info cfg0;
 257         struct partition_info cfg1;
 258         struct partition_info img0;
 259         struct partition_info img1;
 260         struct partition_info nvlog;
 261         struct partition_info vendor[8];
 262 };
 263
 264 struct flash_info_regs {
 265         union {
 266                 struct flash_info_regs_gen3 gen3;
 267                 struct flash_info_regs_gen4 gen4;
 268         };
 269 };
 270
 271 enum {
 272         SWITCHTEC_NTB_REG_INFO_OFFSET   = 0x0000,
 273         SWITCHTEC_NTB_REG_CTRL_OFFSET   = 0x4000,
 274         SWITCHTEC_NTB_REG_DBMSG_OFFSET  = 0x64000,
 275 };
 276
 277 struct ntb_info_regs {
 278         u8  partition_count;
 279         u8  partition_id;
 280         u16 reserved1;
 281         u64 ep_map;
 282         u16 requester_id;
 283         u16 reserved2;
 284         u32 reserved3[4];
 285         struct nt_partition_info {
 286                 u32 xlink_enabled;
 287                 u32 target_part_low;
 288                 u32 target_part_high;
 289                 u32 reserved;
 290         } ntp_info[48];
 291 } __packed;
 292
 293 struct part_cfg_regs {
 294         u32 status;
 295         u32 state;
 296         u32 port_cnt;
 297         u32 usp_port_mode;
 298         u32 usp_pff_inst_id;
 299         u32 vep_pff_inst_id;
 300         u32 dsp_pff_inst_id[47];
 301         u32 reserved1[11];
 302         u16 vep_vector_number;
 303         u16 usp_vector_number;
 304         u32 port_event_bitmap;
 305         u32 reserved2[3];
 306         u32 part_event_summary;
 307         u32 reserved3[3];
 308         u32 part_reset_hdr;
 309         u32 part_reset_data[5];
 310         u32 mrpc_comp_hdr;
 311         u32 mrpc_comp_data[5];
 312         u32 mrpc_comp_async_hdr;
 313         u32 mrpc_comp_async_data[5];
 314         u32 dyn_binding_hdr;
 315         u32 dyn_binding_data[5];
 316         u32 intercomm_notify_hdr;
 317         u32 intercomm_notify_data[5];
 318         u32 reserved4[153];
 319 } __packed;
 320
 321 enum {
 322         NTB_CTRL_PART_OP_LOCK = 0x1,
 323         NTB_CTRL_PART_OP_CFG = 0x2,
 324         NTB_CTRL_PART_OP_RESET = 0x3,
 325
 326         NTB_CTRL_PART_STATUS_NORMAL = 0x1,
 327         NTB_CTRL_PART_STATUS_LOCKED = 0x2,
 328         NTB_CTRL_PART_STATUS_LOCKING = 0x3,
 329         NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
 330         NTB_CTRL_PART_STATUS_RESETTING = 0x5,
 331
 332         NTB_CTRL_BAR_VALID = 1 << 0,
 333         NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
 334         NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
 335
 336         NTB_CTRL_REQ_ID_EN = 1 << 0,
 337
 338         NTB_CTRL_LUT_EN = 1 << 0,
 339
 340         NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
 341 };
 342
 343 struct ntb_ctrl_regs {
 344         u32 partition_status;
 345         u32 partition_op;
 346         u32 partition_ctrl;
 347         u32 bar_setup;
 348         u32 bar_error;
 349         u16 lut_table_entries;
 350         u16 lut_table_offset;
 351         u32 lut_error;
 352         u16 req_id_table_size;
 353         u16 req_id_table_offset;
 354         u32 req_id_error;
 355         u32 reserved1[7];
 356         struct {
 357                 u32 ctl;
 358                 u32 win_size;
 359                 u64 xlate_addr;
 360         } bar_entry[6];
 361         struct {
 362                 u32 win_size;
 363                 u32 reserved[3];
 364         } bar_ext_entry[6];
 365         u32 reserved2[192];
 366         u32 req_id_table[512];
 367         u32 reserved3[256];
 368         u64 lut_entry[512];
 369 } __packed;
 370
 371 #define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
 372 #define NTB_DBMSG_IMSG_MASK   BIT_ULL(40)
 373
 374 struct ntb_dbmsg_regs {
 375         u32 reserved1[1024];
 376         u64 odb;
 377         u64 odb_mask;
 378         u64 idb;
 379         u64 idb_mask;
 380         u8  idb_vec_map[64];
 381         u32 msg_map;
 382         u32 reserved2;
 383         struct {
 384                 u32 msg;
 385                 u32 status;
 386         } omsg[4];
 387
 388         struct {
 389                 u32 msg;
 390                 u8  status;
 391                 u8  mask;
 392                 u8  src;
 393                 u8  reserved;
 394         } imsg[4];
 395
 396         u8 reserved3[3928];
 397         u8 msix_table[1024];
 398         u8 reserved4[3072];
 399         u8 pba[24];
 400         u8 reserved5[4072];
 401 } __packed;
 402
 403 enum {
 404         SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
 405         SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
 406         SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
 407         SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
 408 };
 409
 410 struct pff_csr_regs {
 411         u16 vendor_id;
 412         u16 device_id;
 413         u16 pcicmd;
 414         u16 pcists;
 415         u32 pci_class;
 416         u32 pci_opts;
 417         union {
 418                 u32 pci_bar[6];
 419                 u64 pci_bar64[3];
 420         };
 421         u32 pci_cardbus;
 422         u32 pci_subsystem_id;
 423         u32 pci_expansion_rom;
 424         u32 pci_cap_ptr;
 425         u32 reserved1;
 426         u32 pci_irq;
 427         u32 pci_cap_region[48];
 428         u32 pcie_cap_region[448];
 429         u32 indirect_gas_window[128];
 430         u32 indirect_gas_window_off;
 431         u32 reserved[127];
 432         u32 pff_event_summary;
 433         u32 reserved2[3];
 434         u32 aer_in_p2p_hdr;
 435         u32 aer_in_p2p_data[5];
 436         u32 aer_in_vep_hdr;
 437         u32 aer_in_vep_data[5];
 438         u32 dpc_hdr;
 439         u32 dpc_data[5];
 440         u32 cts_hdr;
 441         u32 cts_data[5];
 442         u32 uec_hdr;
 443         u32 uec_data[5];
 444         u32 hotplug_hdr;
 445         u32 hotplug_data[5];
 446         u32 ier_hdr;
 447         u32 ier_data[5];
 448         u32 threshold_hdr;
 449         u32 threshold_data[5];
 450         u32 power_mgmt_hdr;
 451         u32 power_mgmt_data[5];
 452         u32 tlp_throttling_hdr;
 453         u32 tlp_throttling_data[5];
 454         u32 force_speed_hdr;
 455         u32 force_speed_data[5];
 456         u32 credit_timeout_hdr;
 457         u32 credit_timeout_data[5];
 458         u32 link_state_hdr;
 459         u32 link_state_data[5];
 460         u32 reserved4[174];
 461 } __packed;
 462
 463 struct switchtec_ntb;
 464
 465 struct dma_mrpc_output {
 466         u32 status;
 467         u32 cmd_id;
 468         u32 rtn_code;
 469         u32 output_size;
 470         u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
 471 };
 472
 473 struct switchtec_dev {
 474         struct pci_dev *pdev;
 475         struct device dev;
 476         struct cdev cdev;
 477
 478         enum switchtec_gen gen;
 479
 480         int partition;
 481         int partition_count;
 482         int pff_csr_count;
 483         char pff_local[SWITCHTEC_MAX_PFF_CSR];
 484
 485         void __iomem *mmio;
 486         struct mrpc_regs __iomem *mmio_mrpc;
 487         struct sw_event_regs __iomem *mmio_sw_event;
 488         struct sys_info_regs __iomem *mmio_sys_info;
 489         struct flash_info_regs __iomem *mmio_flash_info;
 490         struct ntb_info_regs __iomem *mmio_ntb;
 491         struct part_cfg_regs __iomem *mmio_part_cfg;
 492         struct part_cfg_regs __iomem *mmio_part_cfg_all;
 493         struct pff_csr_regs __iomem *mmio_pff_csr;
 494
 495         /*
 496          * The mrpc mutex must be held when accessing the other
 497          * mrpc_ fields, alive flag and stuser->state field
 498          */
 499         struct mutex mrpc_mutex;
 500         struct list_head mrpc_queue;
 501         int mrpc_busy;
 502         struct work_struct mrpc_work;
 503         struct delayed_work mrpc_timeout;
 504         bool alive;
 505
 506         wait_queue_head_t event_wq;
 507         atomic_t event_cnt;
 508
 509         struct work_struct link_event_work;
 510         void (*link_notifier)(struct switchtec_dev *stdev);
 511         u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
 512
 513         struct switchtec_ntb *sndev;
 514
 515         struct dma_mrpc_output *dma_mrpc;
 516         dma_addr_t dma_mrpc_dma_addr;
 517 };
 518
 519 static inline struct switchtec_dev *to_stdev(struct device *dev)
 520 {
 521         return container_of(dev, struct switchtec_dev, dev);
 522 }
 523
 524 extern struct class *switchtec_class;
 525
 526 #endif