1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*******************************************************************************
4 Header file for stmmac platform data
6 Copyright (C) 2009 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10 *******************************************************************************/
12 #ifndef __STMMAC_PLATFORM_DATA
13 #define __STMMAC_PLATFORM_DATA
15 #include <linux/platform_device.h>
16 #include <linux/phy.h>
18 #define MTL_MAX_RX_QUEUES 8
19 #define MTL_MAX_TX_QUEUES 8
20 #define STMMAC_CH_MAX 8
22 #define STMMAC_RX_COE_NONE 0
23 #define STMMAC_RX_COE_TYPE1 1
24 #define STMMAC_RX_COE_TYPE2 2
26 /* Define the macros for CSR clock range parameters to be passed by
28 * This could also be configured at run time using CPU freq framework. */
30 /* MDC Clock Selection define*/
31 #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
32 #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
33 #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
34 #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
35 #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
36 #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
38 /* MTL algorithms identifiers */
39 #define MTL_TX_ALGORITHM_WRR 0x0
40 #define MTL_TX_ALGORITHM_WFQ 0x1
41 #define MTL_TX_ALGORITHM_DWRR 0x2
42 #define MTL_TX_ALGORITHM_SP 0x3
43 #define MTL_RX_ALGORITHM_SP 0x4
44 #define MTL_RX_ALGORITHM_WSP 0x5
46 /* RX/TX Queue Mode */
47 #define MTL_QUEUE_AVB 0x0
48 #define MTL_QUEUE_DCB 0x1
50 /* The MDC clock could be set higher than the IEEE 802.3
51 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
52 * of value different than the above defined values. The resultant MDIO
53 * clock frequency of 12.5 MHz is applicable for the interfacing chips
54 * supporting higher MDC clocks.
55 * The MDC clock selection macros need to be defined for MDC clock rate
56 * of 12.5 MHz, corresponding to the following selection.
58 #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
59 #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
60 #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
61 #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
62 #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
63 #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
64 #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
65 #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
67 /* AXI DMA Burst length supported */
68 #define DMA_AXI_BLEN_4 (1 << 1)
69 #define DMA_AXI_BLEN_8 (1 << 2)
70 #define DMA_AXI_BLEN_16 (1 << 3)
71 #define DMA_AXI_BLEN_32 (1 << 4)
72 #define DMA_AXI_BLEN_64 (1 << 5)
73 #define DMA_AXI_BLEN_128 (1 << 6)
74 #define DMA_AXI_BLEN_256 (1 << 7)
75 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
76 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
77 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
79 /* Platfrom data for platform device structure's platform_data field */
81 struct stmmac_mdio_bus_data {
82 unsigned int phy_mask;
83 unsigned int has_xpcs;
84 unsigned int xpcs_an_inband;
90 struct stmmac_dma_cfg {
110 u32 axi_blen[AXI_BLEN];
125 u32 gcl_unaligned[EST_GCL];
130 struct stmmac_rxq_cfg {
138 struct stmmac_txq_cfg {
141 /* Credit Base Shaper parameters */
152 enum stmmac_fpe_state {
154 FPE_STATE_CAPABLE = 1,
155 FPE_STATE_ENTERING_ON = 2,
159 /* FPE link-partner hand-shaking mPacket type */
160 enum stmmac_mpacket_type {
162 MPACKET_RESPONSE = 1,
165 enum stmmac_fpe_task_state_t {
170 struct stmmac_fpe_cfg {
171 bool enable; /* FPE enable */
172 bool hs_enable; /* FPE handshake enable */
173 enum stmmac_fpe_state lp_fpe_state; /* Link Partner FPE state */
174 enum stmmac_fpe_state lo_fpe_state; /* Local station FPE state */
177 struct stmmac_safety_feature_cfg {
189 /* Addresses that may be customized by a platform */
190 struct dwmac4_addrs {
196 u32 mtl_ets_ctrl_offset;
198 u32 mtl_txq_weight_offset;
199 u32 mtl_send_slp_cred;
200 u32 mtl_send_slp_cred_offset;
202 u32 mtl_high_cred_offset;
204 u32 mtl_low_cred_offset;
207 #define STMMAC_FLAG_HAS_INTEGRATED_PCS BIT(0)
208 #define STMMAC_FLAG_SPH_DISABLE BIT(1)
209 #define STMMAC_FLAG_USE_PHY_WOL BIT(2)
210 #define STMMAC_FLAG_HAS_SUN8I BIT(3)
212 struct plat_stmmacenet_data {
216 phy_interface_t phy_interface;
217 struct stmmac_mdio_bus_data *mdio_bus_data;
218 struct device_node *phy_node;
219 struct device_node *phylink_node;
220 struct device_node *mdio_node;
221 struct stmmac_dma_cfg *dma_cfg;
222 struct stmmac_est *est;
223 struct stmmac_fpe_cfg *fpe_cfg;
224 struct stmmac_safety_feature_cfg *safety_feat_cfg;
232 int force_sf_dma_mode;
233 int force_thresh_dma_mode;
237 int multicast_filter_bins;
238 int unicast_filter_entries;
242 u32 rx_queues_to_use;
243 u32 tx_queues_to_use;
244 u8 rx_sched_algorithm;
245 u8 tx_sched_algorithm;
246 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
247 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
248 void (*fix_mac_speed)(void *priv, unsigned int speed);
249 int (*fix_soc_reset)(void *priv, void __iomem *ioaddr);
250 int (*serdes_powerup)(struct net_device *ndev, void *priv);
251 void (*serdes_powerdown)(struct net_device *ndev, void *priv);
252 void (*speed_mode_2500)(struct net_device *ndev, void *priv);
253 void (*ptp_clk_freq_config)(void *priv);
254 int (*init)(struct platform_device *pdev, void *priv);
255 void (*exit)(struct platform_device *pdev, void *priv);
256 struct mac_device_info *(*setup)(void *priv);
257 int (*clks_config)(void *priv, bool enabled);
258 int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
260 void (*dump_debug_regs)(void *priv);
262 struct clk *stmmac_clk;
264 struct clk *clk_ptp_ref;
265 unsigned int clk_ptp_rate;
266 unsigned int clk_ref_rate;
267 unsigned int mult_fact_100ns;
270 struct reset_control *stmmac_rst;
271 struct reset_control *stmmac_ahb_rst;
272 struct stmmac_axi *axi;
276 int mac_port_sel_speed;
277 bool en_tx_lpi_clockgating;
278 bool rx_clk_runs_in_lpi;
282 unsigned int eee_usecs_rate;
283 struct pci_dev *pdev;
284 int int_snapshot_num;
285 int ext_snapshot_num;
286 bool int_snapshot_en;
287 bool ext_snapshot_en;
296 bool serdes_up_after_phy_linkup;
297 const struct dwmac4_addrs *dwmac4_addrs;