1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
7 #include <linux/irqreturn.h>
8 #include <linux/soundwire/sdw.h>
10 /*********************************************************************
11 * cAVS and ACE1.x definitions
12 *********************************************************************/
14 #define SDW_SHIM_BASE 0x2C000
15 #define SDW_ALH_BASE 0x2C800
16 #define SDW_SHIM_BASE_ACE 0x38000
17 #define SDW_ALH_BASE_ACE 0x24000
18 #define SDW_LINK_BASE 0x30000
19 #define SDW_LINK_SIZE 0x10000
21 /* Intel SHIM Registers Definition */
23 #define SDW_SHIM_LCAP 0x0
24 #define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)
27 #define SDW_SHIM_LCTL 0x4
29 #define SDW_SHIM_LCTL_SPA BIT(0)
30 #define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
31 #define SDW_SHIM_LCTL_CPA BIT(8)
32 #define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
35 #define SDW_SHIM_SYNC 0xC
37 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
38 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
39 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
40 #define SDW_SHIM_SYNC_SYNCCPU BIT(15)
41 #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
42 #define SDW_SHIM_SYNC_CMDSYNC BIT(16)
43 #define SDW_SHIM_SYNC_SYNCGO BIT(24)
45 /* Control stream capabililities and channel mask */
46 #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
47 #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
48 #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
49 #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
50 #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
52 /* PCM Stream capabilities */
53 #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
55 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
56 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
57 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
59 /* PCM Stream Channel Map */
60 #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
62 /* PCM Stream Channel Count */
63 #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
65 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
66 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
67 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
68 #define SDW_SHIM_PCMSYCM_DIR BIT(15)
71 #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
73 #define SDW_SHIM_IOCTL_MIF BIT(0)
74 #define SDW_SHIM_IOCTL_CO BIT(1)
75 #define SDW_SHIM_IOCTL_COE BIT(2)
76 #define SDW_SHIM_IOCTL_DO BIT(3)
77 #define SDW_SHIM_IOCTL_DOE BIT(4)
78 #define SDW_SHIM_IOCTL_BKE BIT(5)
79 #define SDW_SHIM_IOCTL_WPDD BIT(6)
80 #define SDW_SHIM_IOCTL_CIBD BIT(8)
81 #define SDW_SHIM_IOCTL_DIBD BIT(9)
84 #define SDW_SHIM_WAKEEN 0x190
86 #define SDW_SHIM_WAKEEN_ENABLE BIT(0)
89 #define SDW_SHIM_WAKESTS 0x192
91 #define SDW_SHIM_WAKESTS_STATUS BIT(0)
93 /* AC Timing control */
94 #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
96 #define SDW_SHIM_CTMCTL_DACTQE BIT(0)
97 #define SDW_SHIM_CTMCTL_DODS BIT(1)
98 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
100 /* Intel ALH Register definitions */
101 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
102 #define SDW_ALH_NUM_STREAMS 64
104 #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
105 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
106 #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
108 /*********************************************************************
109 * ACE2.x definitions for SHIM registers - only accessible when the
110 * HDAudio extended link LCTL.SPA/CPA = 1.
111 *********************************************************************/
112 /* x variable is link index */
113 #define SDW_SHIM2_GENERIC_BASE(x) (0x00030000 + 0x8000 * (x))
114 #define SDW_IP_BASE(x) (0x00030100 + 0x8000 * (x))
115 #define SDW_SHIM2_VS_BASE(x) (0x00036000 + 0x8000 * (x))
117 /* SHIM2 Generic Registers */
118 /* Read-only capabilities */
119 #define SDW_SHIM2_LECAP 0x00
120 #define SDW_SHIM2_LECAP_HDS BIT(0) /* unset -> Host mode */
121 #define SDW_SHIM2_LECAP_MLC GENMASK(3, 1) /* Number of Lanes */
123 /* PCM Stream capabilities */
124 #define SDW_SHIM2_PCMSCAP 0x10
125 #define SDW_SHIM2_PCMSCAP_ISS GENMASK(3, 0) /* Input-only streams */
126 #define SDW_SHIM2_PCMSCAP_OSS GENMASK(7, 4) /* Output-only streams */
127 #define SDW_SHIM2_PCMSCAP_BSS GENMASK(12, 8) /* Bidirectional streams */
129 /* Read-only PCM Stream Channel Count, y variable is stream */
130 #define SDW_SHIM2_PCMSYCHC(y) (0x14 + (0x4 * (y)))
131 #define SDW_SHIM2_PCMSYCHC_CS GENMASK(3, 0) /* Channels Supported */
133 /* PCM Stream Channel Map */
134 #define SDW_SHIM2_PCMSYCHM(y) (0x16 + (0x4 * (y)))
135 #define SDW_SHIM2_PCMSYCHM_LCHAN GENMASK(3, 0) /* Lowest channel used by the FIFO port */
136 #define SDW_SHIM2_PCMSYCHM_HCHAN GENMASK(7, 4) /* Lowest channel used by the FIFO port */
137 #define SDW_SHIM2_PCMSYCHM_STRM GENMASK(13, 8) /* HDaudio stream tag */
138 #define SDW_SHIM2_PCMSYCHM_DIR BIT(15) /* HDaudio stream direction */
140 /* SHIM2 vendor-specific registers */
141 #define SDW_SHIM2_INTEL_VS_LVSCTL 0x04
142 #define SDW_SHIM2_INTEL_VS_LVSCTL_FCG BIT(26)
143 #define SDW_SHIM2_INTEL_VS_LVSCTL_MLCS GENMASK(29, 27)
144 #define SDW_SHIM2_INTEL_VS_LVSCTL_DCGD BIT(30)
145 #define SDW_SHIM2_INTEL_VS_LVSCTL_ICGD BIT(31)
147 #define SDW_SHIM2_MLCS_XTAL_CLK 0x0
148 #define SDW_SHIM2_MLCS_CARDINAL_CLK 0x1
149 #define SDW_SHIM2_MLCS_AUDIO_PLL_CLK 0x2
150 #define SDW_SHIM2_MLCS_MCLK_INPUT_CLK 0x3
151 #define SDW_SHIM2_MLCS_WOV_RING_OSC_CLK 0x4
153 #define SDW_SHIM2_INTEL_VS_WAKEEN 0x08
154 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWE BIT(0)
156 #define SDW_SHIM2_INTEL_VS_WAKESTS 0x0A
157 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWS BIT(0)
159 #define SDW_SHIM2_INTEL_VS_IOCTL 0x0C
160 #define SDW_SHIM2_INTEL_VS_IOCTL_MIF BIT(0)
161 #define SDW_SHIM2_INTEL_VS_IOCTL_CO BIT(1)
162 #define SDW_SHIM2_INTEL_VS_IOCTL_COE BIT(2)
163 #define SDW_SHIM2_INTEL_VS_IOCTL_DO BIT(3)
164 #define SDW_SHIM2_INTEL_VS_IOCTL_DOE BIT(4)
165 #define SDW_SHIM2_INTEL_VS_IOCTL_BKE BIT(5)
166 #define SDW_SHIM2_INTEL_VS_IOCTL_WPDD BIT(6)
167 #define SDW_SHIM2_INTEL_VS_IOCTL_ODC BIT(7)
168 #define SDW_SHIM2_INTEL_VS_IOCTL_CIBD BIT(8)
169 #define SDW_SHIM2_INTEL_VS_IOCTL_DIBD BIT(9)
170 #define SDW_SHIM2_INTEL_VS_IOCTL_HAMIFD BIT(10)
172 #define SDW_SHIM2_INTEL_VS_ACTMCTL 0x0E
173 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE BIT(0)
174 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODS BIT(1)
175 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE BIT(2)
176 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS GENMASK(4, 3)
177 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE BIT(5)
180 * struct sdw_intel_stream_params_data: configuration passed during
181 * the @params_stream callback, e.g. for interaction with DSP
184 struct sdw_intel_stream_params_data {
185 struct snd_pcm_substream *substream;
186 struct snd_soc_dai *dai;
187 struct snd_pcm_hw_params *hw_params;
193 * struct sdw_intel_stream_free_data: configuration passed during
194 * the @free_stream callback, e.g. for interaction with DSP
197 struct sdw_intel_stream_free_data {
198 struct snd_pcm_substream *substream;
199 struct snd_soc_dai *dai;
204 * struct sdw_intel_ops: Intel audio driver callback ops
207 struct sdw_intel_ops {
208 int (*params_stream)(struct device *dev,
209 struct sdw_intel_stream_params_data *params_data);
210 int (*free_stream)(struct device *dev,
211 struct sdw_intel_stream_free_data *free_data);
212 int (*trigger)(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai);
216 * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
217 * @handle: ACPI controller handle
218 * @count: link count found with "sdw-master-count" property
219 * @link_mask: bit-wise mask listing links enabled by BIOS menu
221 * this structure could be expanded to e.g. provide all the _ADR
222 * information in case the link_mask is not sufficient to identify
223 * platform capabilities.
225 struct sdw_intel_acpi_info {
231 struct sdw_intel_link_dev;
233 /* Intel clock-stop/pm_runtime quirk definitions */
236 * Force the clock to remain on during pm_runtime suspend. This might
237 * be needed if Slave devices do not have an alternate clock source or
238 * if the latency requirements are very strict.
240 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED BIT(0)
243 * Stop the bus during pm_runtime suspend. If set, a complete bus
244 * reset and re-enumeration will be performed when the bus
245 * restarts. This mode shall not be used if Slave devices can generate
248 #define SDW_INTEL_CLK_STOP_TEARDOWN BIT(1)
251 * Stop the bus during pm_suspend if Slaves are not wake capable
252 * (e.g. speaker amplifiers). The clock-stop mode is typically
253 * slightly higher power than when the IP is completely powered-off.
255 #define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY BIT(2)
258 * Require a bus reset (and complete re-enumeration) when exiting
259 * clock stop modes. This may be needed if the controller power was
260 * turned off and all context lost. This quirk shall not be used if a
261 * Slave device needs to remain enumerated and keep its context,
262 * e.g. to provide the reasons for the wake, report acoustic events or
263 * pass a history buffer.
265 #define SDW_INTEL_CLK_STOP_BUS_RESET BIT(3)
267 struct sdw_intel_slave_id {
269 struct sdw_slave_id id;
275 * struct sdw_intel_ctx - context allocated by the controller
278 * @mmio_base: mmio base of SoundWire registers, only used to check
279 * hardware capabilities after all power dependencies are settled.
280 * @link_mask: bit-wise mask listing SoundWire links reported by the
282 * @num_slaves: total number of devices exposed across all enabled links
283 * @handle: ACPI parent handle
284 * @ldev: information for each link (controller-specific and kept
286 * @ids: array of slave_id, representing Slaves exposed across all enabled
288 * @link_list: list to handle interrupts across all links
289 * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
290 * @shim_mask: flags to track initialization of SHIM shared registers
291 * @shim_base: sdw shim base.
292 * @alh_base: sdw alh base.
294 struct sdw_intel_ctx {
296 void __iomem *mmio_base;
300 struct sdw_intel_link_dev **ldev;
301 struct sdw_intel_slave_id *ids;
302 struct list_head link_list;
303 struct mutex shim_lock; /* lock for access to shared SHIM registers */
310 * struct sdw_intel_res - Soundwire Intel global resource structure,
311 * typically populated by the DSP driver
313 * @hw_ops: abstraction for platform ops
315 * @mmio_base: mmio base of SoundWire registers
316 * @irq: interrupt number
317 * @handle: ACPI parent handle
318 * @parent: parent device
320 * @dev: device implementing hwparams and free callbacks
321 * @link_mask: bit-wise mask listing links selected by the DSP driver
322 * This mask may be a subset of the one reported by the controller since
323 * machine-specific quirks are handled in the DSP driver.
324 * @clock_stop_quirks: mask array of possible behaviors requested by the
325 * DSP driver. The quirks are common for all links for now.
326 * @shim_base: sdw shim base.
327 * @alh_base: sdw alh base.
328 * @ext: extended HDaudio link support
329 * @hbus: hdac_bus pointer, needed for power management
330 * @eml_lock: mutex protecting shared registers in the HDaudio multi-link
333 struct sdw_intel_res {
334 const struct sdw_intel_hw_ops *hw_ops;
336 void __iomem *mmio_base;
339 struct device *parent;
340 const struct sdw_intel_ops *ops;
343 u32 clock_stop_quirks;
347 struct hdac_bus *hbus;
348 struct mutex *eml_lock;
352 * On Intel platforms, the SoundWire IP has dependencies on power
353 * rails shared with the DSP, and the initialization steps are split
354 * in three. First an ACPI scan to check what the firmware describes
355 * in DSDT tables, then an allocation step (with no hardware
356 * configuration but with all the relevant devices created) and last
357 * the actual hardware configuration. The final stage is a global
358 * interrupt enable which is controlled by the DSP driver. Splitting
359 * these phases helps simplify the boot flow and make early decisions
360 * on e.g. which machine driver to select (I2S mode, HDaudio or
363 int sdw_intel_acpi_scan(acpi_handle *parent_handle,
364 struct sdw_intel_acpi_info *info);
366 void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx);
368 struct sdw_intel_ctx *
369 sdw_intel_probe(struct sdw_intel_res *res);
371 int sdw_intel_startup(struct sdw_intel_ctx *ctx);
373 void sdw_intel_exit(struct sdw_intel_ctx *ctx);
375 irqreturn_t sdw_intel_thread(int irq, void *dev_id);
377 #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1)
381 /* struct intel_sdw_hw_ops - SoundWire ops for Intel platforms.
382 * @debugfs_init: initialize all debugfs capabilities
383 * @debugfs_exit: close and cleanup debugfs capabilities
384 * @register_dai: read all PDI information and register DAIs
385 * @check_clock_stop: throw error message if clock is not stopped.
386 * @start_bus: normal start
387 * @start_bus_after_reset: start after reset
388 * @start_bus_after_clock_stop: start after mode0 clock stop
389 * @stop_bus: stop all bus
390 * @link_power_up: power-up using chip-specific helpers
391 * @link_power_down: power-down with chip-specific helpers
392 * @shim_check_wake: check if a wake was received
393 * @shim_wake: enable/disable in-band wake management
394 * @pre_bank_switch: helper for bus management
395 * @post_bank_switch: helper for bus management
396 * @sync_arm: helper for multi-link synchronization
397 * @sync_go_unlocked: helper for multi-link synchronization -
398 * shim_lock is assumed to be locked at higher level
399 * @sync_go: helper for multi-link synchronization
400 * @sync_check_cmdsync_unlocked: helper for multi-link synchronization
401 * and bank switch - shim_lock is assumed to be locked at higher level
402 * @program_sdi: helper for codec command/control based on dev_num
404 struct sdw_intel_hw_ops {
405 void (*debugfs_init)(struct sdw_intel *sdw);
406 void (*debugfs_exit)(struct sdw_intel *sdw);
408 int (*register_dai)(struct sdw_intel *sdw);
410 void (*check_clock_stop)(struct sdw_intel *sdw);
411 int (*start_bus)(struct sdw_intel *sdw);
412 int (*start_bus_after_reset)(struct sdw_intel *sdw);
413 int (*start_bus_after_clock_stop)(struct sdw_intel *sdw);
414 int (*stop_bus)(struct sdw_intel *sdw, bool clock_stop);
416 int (*link_power_up)(struct sdw_intel *sdw);
417 int (*link_power_down)(struct sdw_intel *sdw);
419 int (*shim_check_wake)(struct sdw_intel *sdw);
420 void (*shim_wake)(struct sdw_intel *sdw, bool wake_enable);
422 int (*pre_bank_switch)(struct sdw_intel *sdw);
423 int (*post_bank_switch)(struct sdw_intel *sdw);
425 void (*sync_arm)(struct sdw_intel *sdw);
426 int (*sync_go_unlocked)(struct sdw_intel *sdw);
427 int (*sync_go)(struct sdw_intel *sdw);
428 bool (*sync_check_cmdsync_unlocked)(struct sdw_intel *sdw);
430 void (*program_sdi)(struct sdw_intel *sdw, int dev_num);
433 extern const struct sdw_intel_hw_ops sdw_intel_cnl_hw_ops;
434 extern const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops;