include/linux/pruss_driver.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2
   3 #ifndef __TI_PRUSS_H
   4 #define __TI_PRUSS_H
   5
   6 /*
   7  * PRU_ICSS_CFG registers
   8  * SYSCFG, ISRP, ISP, IESP, IECP, SCRP applicable on AMxxxx devices only
   9  */
  10 #define PRUSS_CFG_REVID         0x00
  11 #define PRUSS_CFG_SYSCFG        0x04
  12 #define PRUSS_CFG_GPCFG(x)      (0x08 + (x) * 4)
  13 #define PRUSS_CFG_CGR           0x10
  14 #define PRUSS_CFG_ISRP          0x14
  15 #define PRUSS_CFG_ISP           0x18
  16 #define PRUSS_CFG_IESP          0x1C
  17 #define PRUSS_CFG_IECP          0x20
  18 #define PRUSS_CFG_SCRP          0x24
  19 #define PRUSS_CFG_PMAO          0x28
  20 #define PRUSS_CFG_MII_RT        0x2C
  21 #define PRUSS_CFG_IEPCLK        0x30
  22 #define PRUSS_CFG_SPP           0x34
  23 #define PRUSS_CFG_PIN_MX        0x40
  24
  25 /* PRUSS_GPCFG register bits */
  26 #define PRUSS_GPCFG_PRU_GPO_SH_SEL              BIT(25)
  27
  28 #define PRUSS_GPCFG_PRU_DIV1_SHIFT              20
  29 #define PRUSS_GPCFG_PRU_DIV1_MASK               GENMASK(24, 20)
  30
  31 #define PRUSS_GPCFG_PRU_DIV0_SHIFT              15
  32 #define PRUSS_GPCFG_PRU_DIV0_MASK               GENMASK(15, 19)
  33
  34 #define PRUSS_GPCFG_PRU_GPO_MODE                BIT(14)
  35 #define PRUSS_GPCFG_PRU_GPO_MODE_DIRECT         0
  36 #define PRUSS_GPCFG_PRU_GPO_MODE_SERIAL         BIT(14)
  37
  38 #define PRUSS_GPCFG_PRU_GPI_SB                  BIT(13)
  39
  40 #define PRUSS_GPCFG_PRU_GPI_DIV1_SHIFT          8
  41 #define PRUSS_GPCFG_PRU_GPI_DIV1_MASK           GENMASK(12, 8)
  42
  43 #define PRUSS_GPCFG_PRU_GPI_DIV0_SHIFT          3
  44 #define PRUSS_GPCFG_PRU_GPI_DIV0_MASK           GENMASK(7, 3)
  45
  46 #define PRUSS_GPCFG_PRU_GPI_CLK_MODE_POSITIVE   0
  47 #define PRUSS_GPCFG_PRU_GPI_CLK_MODE_NEGATIVE   BIT(2)
  48 #define PRUSS_GPCFG_PRU_GPI_CLK_MODE            BIT(2)
  49
  50 #define PRUSS_GPCFG_PRU_GPI_MODE_MASK           GENMASK(1, 0)
  51 #define PRUSS_GPCFG_PRU_GPI_MODE_SHIFT          0
  52
  53 #define PRUSS_GPCFG_PRU_MUX_SEL_SHIFT           26
  54 #define PRUSS_GPCFG_PRU_MUX_SEL_MASK            GENMASK(29, 26)
  55
  56 /* PRUSS_MII_RT register bits */
  57 #define PRUSS_MII_RT_EVENT_EN                   BIT(0)
  58
  59 /* PRUSS_SPP register bits */
  60 #define PRUSS_SPP_PRU1_PAD_HP_EN                BIT(0)
  61 #define PRUSS_SPP_XFER_SHIFT_EN                 BIT(1)
  62 #define PRUSS_SPP_XFR_BYTE_SHIFT_EN             BIT(2)
  63 #define PRUSS_SPP_RTU_XFR_SHIFT_EN              BIT(3)
  64
  65 /**
  66  * enum pruss_gp_mux_sel - PRUSS GPI/O Mux modes for the
  67  * PRUSS_GPCFG0/1 registers
  68  *
  69  * NOTE: The below defines are the most common values, but there
  70  * are some exceptions like on 66AK2G, where the RESERVED and MII2
  71  * values are interchanged. Also, this bit-field does not exist on
  72  * AM335x SoCs
  73  */
  74 enum pruss_gp_mux_sel {
  75         PRUSS_GP_MUX_SEL_GP = 0,
  76         PRUSS_GP_MUX_SEL_ENDAT,
  77         PRUSS_GP_MUX_SEL_RESERVED,
  78         PRUSS_GP_MUX_SEL_SD,
  79         PRUSS_GP_MUX_SEL_MII2,
  80         PRUSS_GP_MUX_SEL_MAX,
  81 };
  82
  83 /**
  84  * enum pruss_gpi_mode - PRUSS GPI configuration modes, used
  85  *                       to program the PRUSS_GPCFG0/1 registers
  86  */
  87 enum pruss_gpi_mode {
  88         PRUSS_GPI_MODE_DIRECT = 0,
  89         PRUSS_GPI_MODE_PARALLEL,
  90         PRUSS_GPI_MODE_28BIT_SHIFT,
  91         PRUSS_GPI_MODE_MII,
  92 };
  93
  94 /**
  95  * enum pruss_pru_id - PRU core identifiers
  96  */
  97 enum pruss_pru_id {
  98         PRUSS_PRU0 = 0,
  99         PRUSS_PRU1,
 100         PRUSS_NUM_PRUS,
 101 };
 102
 103 /**
 104  * enum pru_ctable_idx - Configurable Constant table index identifiers
 105  */
 106 enum pru_ctable_idx {
 107         PRU_C24 = 0,
 108         PRU_C25,
 109         PRU_C26,
 110         PRU_C27,
 111         PRU_C28,
 112         PRU_C29,
 113         PRU_C30,
 114         PRU_C31,
 115 };
 116
 117 /**
 118  * enum pruss_mem - PRUSS memory range identifiers
 119  */
 120 enum pruss_mem {
 121         PRUSS_MEM_DRAM0 = 0,
 122         PRUSS_MEM_DRAM1,
 123         PRUSS_MEM_SHRD_RAM2,
 124         PRUSS_MEM_MAX,
 125 };
 126
 127 /**
 128  * struct pruss_mem_region - PRUSS memory region structure
 129  * @va: kernel virtual address of the PRUSS memory region
 130  * @pa: physical (bus) address of the PRUSS memory region
 131  * @size: size of the PRUSS memory region
 132  */
 133 struct pruss_mem_region {
 134         void __iomem *va;
 135         phys_addr_t pa;
 136         size_t size;
 137 };
 138
 139 /**
 140  * struct pruss - PRUSS parent structure
 141  * @dev: pruss device pointer
 142  * @cfg: regmap for config region
 143  * @mem_regions: data for each of the PRUSS memory regions
 144  * @mem_in_use: to indicate if memory resource is in use
 145  */
 146 struct pruss {
 147         struct udevice *dev;
 148         struct regmap *cfg;
 149         struct pruss_mem_region mem_regions[PRUSS_MEM_MAX];
 150         struct pruss_mem_region *mem_in_use[PRUSS_MEM_MAX];
 151 };
 152
 153 int pruss_request_tm_region(struct udevice *dev, phys_addr_t *loc);
 154 int pruss_request_mem_region(struct udevice *dev, enum pruss_mem mem_id,
 155                              struct pruss_mem_region *region);
 156 int pruss_release_mem_region(struct udevice *dev, struct pruss_mem_region *region);
 157 int pruss_cfg_update(struct udevice *dev, unsigned int reg,
 158                      unsigned int mask, unsigned int val);
 159
 160 /**
 161  * pruss_cfg_gpimode() - set the GPI mode of the PRU
 162  * @dev: the pruss device
 163  * @pru_id: the rproc instance handle of the PRU
 164  * @mode: GPI mode to set
 165  *
 166  * Sets the GPI mode for a given PRU by programming the
 167  * corresponding PRUSS_CFG_GPCFGx register
 168  *
 169  * Returns 0 on success, or an error code otherwise
 170  */
 171 static inline int pruss_cfg_gpimode(struct udevice *dev, enum pruss_pru_id id,
 172                                     enum pruss_gpi_mode mode)
 173 {
 174         if (id < 0)
 175                 return -EINVAL;
 176
 177         return pruss_cfg_update(dev, PRUSS_CFG_GPCFG(id),
 178                                 PRUSS_GPCFG_PRU_GPI_MODE_MASK,
 179                                 mode << PRUSS_GPCFG_PRU_GPI_MODE_SHIFT);
 180 }
 181
 182 /**
 183  * pruss_cfg_miirt_enable() - Enable/disable MII RT Events
 184  * @dev: the pruss device
 185  * @enable: enable/disable
 186  *
 187  * Enable/disable the MII RT Events for the PRUSS.
 188  */
 189 static inline int pruss_cfg_miirt_enable(struct udevice *dev, bool enable)
 190 {
 191         u32 set = enable ? PRUSS_MII_RT_EVENT_EN : 0;
 192
 193         return pruss_cfg_update(dev, PRUSS_CFG_MII_RT,
 194                                 PRUSS_MII_RT_EVENT_EN, set);
 195 }
 196
 197 /**
 198  * pruss_cfg_xfr_enable() - Enable/disable XIN XOUT shift functionality
 199  * @dev: the pruss device
 200  * @enable: enable/disable
 201  */
 202 static inline int pruss_cfg_xfr_enable(struct udevice *dev, bool enable)
 203 {
 204         u32 set = enable ? PRUSS_SPP_XFER_SHIFT_EN : 0;
 205
 206         return pruss_cfg_update(dev, PRUSS_CFG_SPP,
 207                         PRUSS_SPP_XFER_SHIFT_EN, set);
 208 }
 209
 210 /**
 211  * pruss_cfg_set_gpmux() - set the GPMUX value for a PRU device
 212  * @pruss: pruss device
 213  * @pru_id: PRU identifier (0-1)
 214  * @mux: new mux value for PRU
 215  */
 216 static inline int pruss_cfg_set_gpmux(struct udevice *dev,
 217                                       enum pruss_pru_id id, u8 mux)
 218 {
 219         if (mux >= PRUSS_GP_MUX_SEL_MAX)
 220                 return -EINVAL;
 221
 222         return pruss_cfg_update(dev, PRUSS_CFG_GPCFG(id),
 223                         PRUSS_GPCFG_PRU_MUX_SEL_MASK,
 224                         (u32)mux << PRUSS_GPCFG_PRU_MUX_SEL_SHIFT);
 225 }
 226
 227 #endif /* __TI_PRUSS_H */