2 * Copyright (C) 2010 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #ifndef _PLAT_BCM2708_DMA_H
10 #define _PLAT_BCM2708_DMA_H
12 /* DMA CS Control and Status bits */
13 #define BCM2708_DMA_ACTIVE BIT(0)
14 #define BCM2708_DMA_INT BIT(2)
15 #define BCM2708_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
16 #define BCM2708_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
17 #define BCM2708_DMA_ERR BIT(8)
18 #define BCM2708_DMA_ABORT BIT(30) /* stop current CB, go to next, WO */
19 #define BCM2708_DMA_RESET BIT(31) /* WO, self clearing */
21 /* DMA control block "info" field bits */
22 #define BCM2708_DMA_INT_EN BIT(0)
23 #define BCM2708_DMA_TDMODE BIT(1)
24 #define BCM2708_DMA_WAIT_RESP BIT(3)
25 #define BCM2708_DMA_D_INC BIT(4)
26 #define BCM2708_DMA_D_WIDTH BIT(5)
27 #define BCM2708_DMA_D_DREQ BIT(6)
28 #define BCM2708_DMA_S_INC BIT(8)
29 #define BCM2708_DMA_S_WIDTH BIT(9)
30 #define BCM2708_DMA_S_DREQ BIT(10)
32 #define BCM2708_DMA_BURST(x) (((x) & 0xf) << 12)
33 #define BCM2708_DMA_PER_MAP(x) ((x) << 16)
34 #define BCM2708_DMA_WAITS(x) (((x) & 0x1f) << 21)
36 #define BCM2708_DMA_DREQ_EMMC 11
37 #define BCM2708_DMA_DREQ_SDHOST 13
39 #define BCM2708_DMA_CS 0x00 /* Control and Status */
40 #define BCM2708_DMA_ADDR 0x04
41 /* the current control block appears in the following registers - read only */
42 #define BCM2708_DMA_INFO 0x08
43 #define BCM2708_DMA_SOURCE_AD 0x0c
44 #define BCM2708_DMA_DEST_AD 0x10
45 #define BCM2708_DMA_NEXTCB 0x1C
46 #define BCM2708_DMA_DEBUG 0x20
48 #define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4) + BCM2708_DMA_CS)
49 #define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4) + BCM2708_DMA_ADDR)
51 #define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
53 /* When listing features we can ask for when allocating DMA channels give
54 those with higher priority smaller ordinal numbers */
55 #define BCM_DMA_FEATURE_FAST_ORD 0
56 #define BCM_DMA_FEATURE_BULK_ORD 1
57 #define BCM_DMA_FEATURE_NORMAL_ORD 2
58 #define BCM_DMA_FEATURE_LITE_ORD 3
59 #define BCM_DMA_FEATURE_FAST BIT(BCM_DMA_FEATURE_FAST_ORD)
60 #define BCM_DMA_FEATURE_BULK BIT(BCM_DMA_FEATURE_BULK_ORD)
61 #define BCM_DMA_FEATURE_NORMAL BIT(BCM_DMA_FEATURE_NORMAL_ORD)
62 #define BCM_DMA_FEATURE_LITE BIT(BCM_DMA_FEATURE_LITE_ORD)
63 #define BCM_DMA_FEATURE_COUNT 4
65 struct bcm2708_dma_cb {
76 struct platform_device;
78 #if defined(CONFIG_DMA_BCM2708) || defined(CONFIG_DMA_BCM2708_MODULE)
80 int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
81 void bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block);
82 void bcm_dma_wait_idle(void __iomem *dma_chan_base);
83 bool bcm_dma_is_busy(void __iomem *dma_chan_base);
84 int bcm_dma_abort(void __iomem *dma_chan_base);
86 /* return channel no or -ve error */
87 int bcm_dma_chan_alloc(unsigned preferred_feature_set,
88 void __iomem **out_dma_base, int *out_dma_irq);
89 int bcm_dma_chan_free(int channel);
91 int bcm_dmaman_probe(struct platform_device *pdev, void __iomem *base,
93 int bcm_dmaman_remove(struct platform_device *pdev);
95 #else /* CONFIG_DMA_BCM2708 */
97 static inline int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr,
103 static inline void bcm_dma_start(void __iomem *dma_chan_base,
104 dma_addr_t control_block) { }
106 static inline void bcm_dma_wait_idle(void __iomem *dma_chan_base) { }
108 static inline bool bcm_dma_is_busy(void __iomem *dma_chan_base)
113 static inline int bcm_dma_abort(void __iomem *dma_chan_base)
118 static inline int bcm_dma_chan_alloc(unsigned preferred_feature_set,
119 void __iomem **out_dma_base,
125 static inline int bcm_dma_chan_free(int channel)
130 static inline int bcm_dmaman_probe(struct platform_device *pdev,
131 void __iomem *base, u32 chans_available)
136 static inline int bcm_dmaman_remove(struct platform_device *pdev)
141 #endif /* CONFIG_DMA_BCM2708 || CONFIG_DMA_BCM2708_MODULE */
143 #endif /* _PLAT_BCM2708_DMA_H */