1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
43 #include <linux/pci_ids.h>
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
52 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
53 #define PCI_NUM_RESET_METHODS 7
55 #define PCI_RESET_PROBE true
56 #define PCI_RESET_DO_RESET false
59 * The PCI interface treats multi-function devices as independent
60 * devices. The slot/function address of each device is encoded
61 * in a single byte as follows:
66 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
67 * In the interest of not exposing interfaces to user-space unnecessarily,
68 * the following kernel-only defines are being added here.
70 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
71 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
72 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74 /* pci_slot represents a physical slot */
76 struct pci_bus *bus; /* Bus this slot is on */
77 struct list_head list; /* Node in list of slots */
78 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
79 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
83 static inline const char *pci_slot_name(const struct pci_slot *slot)
85 return kobject_name(&slot->kobj);
88 /* File state for mmap()s on /proc/bus/pci/X/Y */
94 /* For PCI devices, the region numbers are assigned this way: */
96 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
100 /* #6: expansion ROM resource */
103 /* Device-specific resources */
104 #ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
109 /* PCI-to-PCI (P2P) bridge windows */
110 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
111 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
112 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114 /* CardBus bridge windows */
115 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
116 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
117 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
118 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120 /* Total number of bridge resources for P2P and CardBus */
121 #define PCI_BRIDGE_RESOURCE_NUM 4
123 /* Resources assigned to buses behind the bridge */
124 PCI_BRIDGE_RESOURCES,
125 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
126 PCI_BRIDGE_RESOURCE_NUM - 1,
128 /* Total resources associated with a PCI device */
131 /* Preserve this for compatibility */
132 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
136 * enum pci_interrupt_pin - PCI INTx interrupt values
137 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
138 * @PCI_INTERRUPT_INTA: PCI INTA pin
139 * @PCI_INTERRUPT_INTB: PCI INTB pin
140 * @PCI_INTERRUPT_INTC: PCI INTC pin
141 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
144 * PCI_INTERRUPT_PIN register.
146 enum pci_interrupt_pin {
147 PCI_INTERRUPT_UNKNOWN,
154 /* The number of legacy PCI INTx interrupts */
155 #define PCI_NUM_INTX 4
158 * pci_power_t values must match the bits in the Capabilities PME_Support
159 * and Control/Status PowerState fields in the Power Management capability.
161 typedef int __bitwise pci_power_t;
163 #define PCI_D0 ((pci_power_t __force) 0)
164 #define PCI_D1 ((pci_power_t __force) 1)
165 #define PCI_D2 ((pci_power_t __force) 2)
166 #define PCI_D3hot ((pci_power_t __force) 3)
167 #define PCI_D3cold ((pci_power_t __force) 4)
168 #define PCI_UNKNOWN ((pci_power_t __force) 5)
169 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
171 /* Remember to update this when the list above changes! */
172 extern const char *pci_power_names[];
174 static inline const char *pci_power_name(pci_power_t state)
176 return pci_power_names[1 + (__force int) state];
180 * typedef pci_channel_state_t
182 * The pci_channel state describes connectivity between the CPU and
183 * the PCI device. If some PCI bus between here and the PCI device
184 * has crashed or locked up, this info is reflected here.
186 typedef unsigned int __bitwise pci_channel_state_t;
189 /* I/O channel is in normal state */
190 pci_channel_io_normal = (__force pci_channel_state_t) 1,
192 /* I/O to channel is blocked */
193 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
195 /* PCI card is dead */
196 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
199 typedef unsigned int __bitwise pcie_reset_state_t;
201 enum pcie_reset_state {
202 /* Reset is NOT asserted (Use to deassert reset) */
203 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
205 /* Use #PERST to reset PCIe device */
206 pcie_warm_reset = (__force pcie_reset_state_t) 2,
208 /* Use PCIe Hot Reset to reset device */
209 pcie_hot_reset = (__force pcie_reset_state_t) 3
212 typedef unsigned short __bitwise pci_dev_flags_t;
214 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
215 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
216 /* Device configuration is irrevocably lost if disabled into D3 */
217 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
218 /* Provide indication device is assigned by a Virtual Machine Manager */
219 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
220 /* Flag for quirk use to store if quirk-specific ACS is enabled */
221 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
222 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
223 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
224 /* Do not use bus resets for device */
225 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
226 /* Do not use PM reset even if device advertises NoSoftRst- */
227 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
228 /* Get VPD from function 0 VPD */
229 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
230 /* A non-root bridge where translation occurs, stop alias search here */
231 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
232 /* Do not use FLR even if device advertises PCI_AF_CAP */
233 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
234 /* Don't use Relaxed Ordering for TLPs directed at this device */
235 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
238 enum pci_irq_reroute_variant {
239 INTEL_IRQ_REROUTE_VARIANT = 1,
240 MAX_IRQ_REROUTE_VARIANTS = 3
243 typedef unsigned short __bitwise pci_bus_flags_t;
245 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
246 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
247 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
248 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
251 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
252 enum pcie_link_width {
253 PCIE_LNK_WIDTH_RESRV = 0x00,
261 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
264 /* See matching string table in pci_speed_string() */
266 PCI_SPEED_33MHz = 0x00,
267 PCI_SPEED_66MHz = 0x01,
268 PCI_SPEED_66MHz_PCIX = 0x02,
269 PCI_SPEED_100MHz_PCIX = 0x03,
270 PCI_SPEED_133MHz_PCIX = 0x04,
271 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
272 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
273 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
274 PCI_SPEED_66MHz_PCIX_266 = 0x09,
275 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
276 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
282 PCI_SPEED_66MHz_PCIX_533 = 0x11,
283 PCI_SPEED_100MHz_PCIX_533 = 0x12,
284 PCI_SPEED_133MHz_PCIX_533 = 0x13,
285 PCIE_SPEED_2_5GT = 0x14,
286 PCIE_SPEED_5_0GT = 0x15,
287 PCIE_SPEED_8_0GT = 0x16,
288 PCIE_SPEED_16_0GT = 0x17,
289 PCIE_SPEED_32_0GT = 0x18,
290 PCIE_SPEED_64_0GT = 0x19,
291 PCI_SPEED_UNKNOWN = 0xff,
294 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
295 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
304 struct pcie_link_state;
309 /* The pci_dev structure describes PCI devices */
311 struct list_head bus_list; /* Node in per-bus list */
312 struct pci_bus *bus; /* Bus this device is on */
313 struct pci_bus *subordinate; /* Bus this device bridges to */
315 void *sysdata; /* Hook for sys-specific extension */
316 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
317 struct pci_slot *slot; /* Physical slot this device is in */
319 unsigned int devfn; /* Encoded device & function index */
320 unsigned short vendor;
321 unsigned short device;
322 unsigned short subsystem_vendor;
323 unsigned short subsystem_device;
324 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
325 u8 revision; /* PCI revision, low byte of class word */
326 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
327 #ifdef CONFIG_PCIEAER
328 u16 aer_cap; /* AER capability offset */
329 struct aer_stats *aer_stats; /* AER stats for this device */
331 #ifdef CONFIG_PCIEPORTBUS
332 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
333 struct pci_dev *rcec; /* Associated RCEC device */
335 u32 devcap; /* PCIe Device Capabilities */
336 u8 pcie_cap; /* PCIe capability offset */
337 u8 msi_cap; /* MSI capability offset */
338 u8 msix_cap; /* MSI-X capability offset */
339 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
340 u8 rom_base_reg; /* Config register controlling ROM */
341 u8 pin; /* Interrupt pin this device uses */
342 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
343 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
345 struct pci_driver *driver; /* Driver bound to this device */
346 u64 dma_mask; /* Mask of the bits of bus address this
347 device implements. Normally this is
348 0xffffffff. You only need to change
349 this if your device has broken DMA
350 or supports 64-bit transfers. */
352 struct device_dma_parameters dma_parms;
354 pci_power_t current_state; /* Current operating state. In ACPI,
355 this is D0-D3, D0 being fully
356 functional, and D3 being off. */
357 unsigned int imm_ready:1; /* Supports Immediate Readiness */
358 u8 pm_cap; /* PM capability offset */
359 unsigned int pme_support:5; /* Bitmask of states from which PME#
361 unsigned int pme_poll:1; /* Poll device's PME status bit */
362 unsigned int d1_support:1; /* Low power state D1 is supported */
363 unsigned int d2_support:1; /* Low power state D2 is supported */
364 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
365 unsigned int no_d3cold:1; /* D3cold is forbidden */
366 unsigned int bridge_d3:1; /* Allow D3 for bridge */
367 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
368 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
369 decoding during BAR sizing */
370 unsigned int wakeup_prepared:1;
371 unsigned int runtime_d3cold:1; /* Whether go through runtime
372 D3cold, not set for devices
373 powered on/off by the
374 corresponding bridge */
375 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
376 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
377 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
378 controlled exclusively by
380 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
382 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
383 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
385 #ifdef CONFIG_PCIEASPM
386 struct pcie_link_state *link_state; /* ASPM link state */
387 unsigned int ltr_path:1; /* Latency Tolerance Reporting
388 supported from root to here */
389 u16 l1ss; /* L1SS Capability pointer */
391 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
392 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
394 pci_channel_state_t error_state; /* Current connectivity state */
395 struct device dev; /* Generic device interface */
397 int cfg_size; /* Size of config space */
400 * Instead of touching interrupt line and base address registers
401 * directly, use the values stored here. They might be different!
404 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
406 bool match_driver; /* Skip attaching driver */
408 unsigned int transparent:1; /* Subtractive decode bridge */
409 unsigned int io_window:1; /* Bridge has I/O window */
410 unsigned int pref_window:1; /* Bridge has pref mem window */
411 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
412 unsigned int multifunction:1; /* Multi-function device */
414 unsigned int is_busmaster:1; /* Is busmaster */
415 unsigned int no_msi:1; /* May not use MSI */
416 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
417 unsigned int block_cfg_access:1; /* Config space access blocked */
418 unsigned int broken_parity_status:1; /* Generates false positive parity */
419 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
420 unsigned int msi_enabled:1;
421 unsigned int msix_enabled:1;
422 unsigned int ari_enabled:1; /* ARI forwarding */
423 unsigned int ats_enabled:1; /* Address Translation Svc */
424 unsigned int pasid_enabled:1; /* Process Address Space ID */
425 unsigned int pri_enabled:1; /* Page Request Interface */
426 unsigned int is_managed:1;
427 unsigned int needs_freset:1; /* Requires fundamental reset */
428 unsigned int state_saved:1;
429 unsigned int is_physfn:1;
430 unsigned int is_virtfn:1;
431 unsigned int is_hotplug_bridge:1;
432 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
433 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
435 * Devices marked being untrusted are the ones that can potentially
436 * execute DMA attacks and similar. They are typically connected
437 * through external ports such as Thunderbolt but not limited to
438 * that. When an IOMMU is enabled they should be getting full
439 * mappings to make sure they cannot access arbitrary memory.
441 unsigned int untrusted:1;
443 * Info from the platform, e.g., ACPI or device tree, may mark a
444 * device as "external-facing". An external-facing device is
445 * itself internal but devices downstream from it are external.
447 unsigned int external_facing:1;
448 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
449 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
450 unsigned int irq_managed:1;
451 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
452 unsigned int is_probed:1; /* Device probing in progress */
453 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
454 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
455 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
456 pci_dev_flags_t dev_flags;
457 atomic_t enable_cnt; /* pci_enable_device has been called */
459 u32 saved_config_space[16]; /* Config space saved at suspend time */
460 struct hlist_head saved_cap_space;
461 int rom_attr_enabled; /* Display of ROM attribute enabled? */
462 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
463 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
465 #ifdef CONFIG_HOTPLUG_PCI_PCIE
466 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
468 #ifdef CONFIG_PCIE_PTM
469 unsigned int ptm_root:1;
470 unsigned int ptm_enabled:1;
473 #ifdef CONFIG_PCI_MSI
474 const struct attribute_group **msi_irq_groups;
477 #ifdef CONFIG_PCIE_DPC
479 unsigned int dpc_rp_extensions:1;
482 #ifdef CONFIG_PCI_ATS
484 struct pci_sriov *sriov; /* PF: SR-IOV info */
485 struct pci_dev *physfn; /* VF: related PF */
487 u16 ats_cap; /* ATS Capability offset */
488 u8 ats_stu; /* ATS Smallest Translation Unit */
490 #ifdef CONFIG_PCI_PRI
491 u16 pri_cap; /* PRI Capability offset */
492 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
493 unsigned int pasid_required:1; /* PRG Response PASID Required */
495 #ifdef CONFIG_PCI_PASID
496 u16 pasid_cap; /* PASID Capability offset */
499 #ifdef CONFIG_PCI_P2PDMA
500 struct pci_p2pdma __rcu *p2pdma;
502 u16 acs_cap; /* ACS Capability offset */
503 phys_addr_t rom; /* Physical address if not from BAR */
504 size_t romlen; /* Length if not from BAR */
505 char *driver_override; /* Driver name to force a match */
507 unsigned long priv_flags; /* Private flags for the PCI driver */
509 /* These methods index pci_reset_fn_methods[] */
510 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
513 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
515 #ifdef CONFIG_PCI_IOV
522 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
524 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
525 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
527 static inline int pci_channel_offline(struct pci_dev *pdev)
529 return (pdev->error_state != pci_channel_io_normal);
533 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
534 * Group number is limited to a 16-bit value, therefore (int)-1 is
535 * not a valid PCI domain number, and can be used as a sentinel
536 * value indicating ->domain_nr is not set by the driver (and
537 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
538 * pci_bus_find_domain_nr()).
540 #define PCI_DOMAIN_NR_NOT_SET (-1)
542 struct pci_host_bridge {
544 struct pci_bus *bus; /* Root bus */
546 struct pci_ops *child_ops;
550 struct list_head windows; /* resource_entry */
551 struct list_head dma_ranges; /* dma ranges resource list */
552 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
553 int (*map_irq)(const struct pci_dev *, u8, u8);
554 void (*release_fn)(struct pci_host_bridge *);
556 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
557 unsigned int no_ext_tags:1; /* No Extended Tags */
558 unsigned int native_aer:1; /* OS may use PCIe AER */
559 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
560 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
561 unsigned int native_pme:1; /* OS may use PCIe PME */
562 unsigned int native_ltr:1; /* OS may use PCIe LTR */
563 unsigned int native_dpc:1; /* OS may use PCIe DPC */
564 unsigned int preserve_config:1; /* Preserve FW resource setup */
565 unsigned int size_windows:1; /* Enable root bus sizing */
566 unsigned int msi_domain:1; /* Bridge wants MSI domain */
568 /* Resource alignment requirements */
569 resource_size_t (*align_resource)(struct pci_dev *dev,
570 const struct resource *res,
571 resource_size_t start,
572 resource_size_t size,
573 resource_size_t align);
574 unsigned long private[] ____cacheline_aligned;
577 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
579 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
581 return (void *)bridge->private;
584 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
586 return container_of(priv, struct pci_host_bridge, private);
589 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
590 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
592 void pci_free_host_bridge(struct pci_host_bridge *bridge);
593 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
595 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
596 void (*release_fn)(struct pci_host_bridge *),
599 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
602 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
603 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
604 * buses below host bridges or subtractive decode bridges) go in the list.
605 * Use pci_bus_for_each_resource() to iterate through all the resources.
609 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
610 * and there's no way to program the bridge with the details of the window.
611 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
612 * decode bit set, because they are explicit and can be programmed with _SRS.
614 #define PCI_SUBTRACTIVE_DECODE 0x1
616 struct pci_bus_resource {
617 struct list_head list;
618 struct resource *res;
622 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
625 struct list_head node; /* Node in list of buses */
626 struct pci_bus *parent; /* Parent bus this bridge is on */
627 struct list_head children; /* List of child buses */
628 struct list_head devices; /* List of devices on this bus */
629 struct pci_dev *self; /* Bridge device as seen by parent */
630 struct list_head slots; /* List of slots on this bus;
631 protected by pci_slot_mutex */
632 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
633 struct list_head resources; /* Address space routed to this bus */
634 struct resource busn_res; /* Bus numbers routed to this bus */
636 struct pci_ops *ops; /* Configuration access functions */
637 void *sysdata; /* Hook for sys-specific extension */
638 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
640 unsigned char number; /* Bus number */
641 unsigned char primary; /* Number of primary bridge */
642 unsigned char max_bus_speed; /* enum pci_bus_speed */
643 unsigned char cur_bus_speed; /* enum pci_bus_speed */
644 #ifdef CONFIG_PCI_DOMAINS_GENERIC
650 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
651 pci_bus_flags_t bus_flags; /* Inherited by child buses */
652 struct device *bridge;
654 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
655 struct bin_attribute *legacy_mem; /* Legacy mem */
656 unsigned int is_added:1;
659 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
661 static inline u16 pci_dev_id(struct pci_dev *dev)
663 return PCI_DEVID(dev->bus->number, dev->devfn);
667 * Returns true if the PCI bus is root (behind host-PCI bridge),
670 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
671 * This is incorrect because "virtual" buses added for SR-IOV (via
672 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
674 static inline bool pci_is_root_bus(struct pci_bus *pbus)
676 return !(pbus->parent);
680 * pci_is_bridge - check if the PCI device is a bridge
683 * Return true if the PCI device is bridge whether it has subordinate
686 static inline bool pci_is_bridge(struct pci_dev *dev)
688 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
689 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
692 #define for_each_pci_bridge(dev, bus) \
693 list_for_each_entry(dev, &bus->devices, bus_list) \
694 if (!pci_is_bridge(dev)) {} else
696 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
698 dev = pci_physfn(dev);
699 if (pci_is_root_bus(dev->bus))
702 return dev->bus->self;
705 #ifdef CONFIG_PCI_MSI
706 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
708 return pci_dev->msi_enabled || pci_dev->msix_enabled;
711 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
714 /* Error values that may be returned by PCI functions */
715 #define PCIBIOS_SUCCESSFUL 0x00
716 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
717 #define PCIBIOS_BAD_VENDOR_ID 0x83
718 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
719 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
720 #define PCIBIOS_SET_FAILED 0x88
721 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
723 /* Translate above to generic errno for passing back through non-PCI code */
724 static inline int pcibios_err_to_errno(int err)
726 if (err <= PCIBIOS_SUCCESSFUL)
727 return err; /* Assume already errno */
730 case PCIBIOS_FUNC_NOT_SUPPORTED:
732 case PCIBIOS_BAD_VENDOR_ID:
734 case PCIBIOS_DEVICE_NOT_FOUND:
736 case PCIBIOS_BAD_REGISTER_NUMBER:
738 case PCIBIOS_SET_FAILED:
740 case PCIBIOS_BUFFER_TOO_SMALL:
747 /* Low-level architecture-dependent routines */
750 int (*add_bus)(struct pci_bus *bus);
751 void (*remove_bus)(struct pci_bus *bus);
752 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
753 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
754 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
758 * ACPI needs to be able to access PCI config space before we've done a
759 * PCI bus scan and created pci_bus structures.
761 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
762 int reg, int len, u32 *val);
763 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
764 int reg, int len, u32 val);
766 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
767 typedef u64 pci_bus_addr_t;
769 typedef u32 pci_bus_addr_t;
772 struct pci_bus_region {
773 pci_bus_addr_t start;
778 spinlock_t lock; /* Protects list, index */
779 struct list_head list; /* For IDs added at runtime */
784 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
785 * a set of callbacks in struct pci_error_handlers, that device driver
786 * will be notified of PCI bus errors, and will be driven to recovery
787 * when an error occurs.
790 typedef unsigned int __bitwise pci_ers_result_t;
792 enum pci_ers_result {
793 /* No result/none/not supported in device driver */
794 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
796 /* Device driver can recover without slot reset */
797 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
799 /* Device driver wants slot to be reset */
800 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
802 /* Device has completely failed, is unrecoverable */
803 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
805 /* Device driver is fully recovered and operational */
806 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
808 /* No AER capabilities registered for the driver */
809 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
812 /* PCI bus error event callbacks */
813 struct pci_error_handlers {
814 /* PCI bus error detected on this device */
815 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
816 pci_channel_state_t error);
818 /* MMIO has been re-enabled, but not DMA */
819 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
821 /* PCI slot has been reset */
822 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
824 /* PCI function reset prepare or completed */
825 void (*reset_prepare)(struct pci_dev *dev);
826 void (*reset_done)(struct pci_dev *dev);
828 /* Device driver may resume normal operations */
829 void (*resume)(struct pci_dev *dev);
836 * struct pci_driver - PCI driver structure
837 * @node: List of driver structures.
838 * @name: Driver name.
839 * @id_table: Pointer to table of device IDs the driver is
840 * interested in. Most drivers should export this
841 * table using MODULE_DEVICE_TABLE(pci,...).
842 * @probe: This probing function gets called (during execution
843 * of pci_register_driver() for already existing
844 * devices or later if a new device gets inserted) for
845 * all PCI devices which match the ID table and are not
846 * "owned" by the other drivers yet. This function gets
847 * passed a "struct pci_dev \*" for each device whose
848 * entry in the ID table matches the device. The probe
849 * function returns zero when the driver chooses to
850 * take "ownership" of the device or an error code
851 * (negative number) otherwise.
852 * The probe function always gets called from process
853 * context, so it can sleep.
854 * @remove: The remove() function gets called whenever a device
855 * being handled by this driver is removed (either during
856 * deregistration of the driver or when it's manually
857 * pulled out of a hot-pluggable slot).
858 * The remove function always gets called from process
859 * context, so it can sleep.
860 * @suspend: Put device into low power state.
861 * @resume: Wake device from low power state.
862 * (Please see Documentation/power/pci.rst for descriptions
863 * of PCI Power Management and the related functions.)
864 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
865 * Intended to stop any idling DMA operations.
866 * Useful for enabling wake-on-lan (NIC) or changing
867 * the power state of a device before reboot.
868 * e.g. drivers/net/e100.c.
869 * @sriov_configure: Optional driver callback to allow configuration of
870 * number of VFs to enable via sysfs "sriov_numvfs" file.
871 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
872 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
873 * This will change MSI-X Table Size in the VF Message Control
875 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
876 * MSI-X vectors available for distribution to the VFs.
877 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
878 * @groups: Sysfs attribute groups.
879 * @dev_groups: Attributes attached to the device that will be
880 * created once it is bound to the driver.
881 * @driver: Driver model structure.
882 * @dynids: List of dynamically added device IDs.
885 struct list_head node;
887 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
888 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
889 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
890 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
891 int (*resume)(struct pci_dev *dev); /* Device woken up */
892 void (*shutdown)(struct pci_dev *dev);
893 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
894 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
895 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
896 const struct pci_error_handlers *err_handler;
897 const struct attribute_group **groups;
898 const struct attribute_group **dev_groups;
899 struct device_driver driver;
900 struct pci_dynids dynids;
903 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
906 * PCI_DEVICE - macro used to describe a specific PCI device
907 * @vend: the 16 bit PCI Vendor ID
908 * @dev: the 16 bit PCI Device ID
910 * This macro is used to create a struct pci_device_id that matches a
911 * specific device. The subvendor and subdevice fields will be set to
914 #define PCI_DEVICE(vend,dev) \
915 .vendor = (vend), .device = (dev), \
916 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
919 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
920 * @vend: the 16 bit PCI Vendor ID
921 * @dev: the 16 bit PCI Device ID
922 * @subvend: the 16 bit PCI Subvendor ID
923 * @subdev: the 16 bit PCI Subdevice ID
925 * This macro is used to create a struct pci_device_id that matches a
926 * specific device with subsystem information.
928 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
929 .vendor = (vend), .device = (dev), \
930 .subvendor = (subvend), .subdevice = (subdev)
933 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
934 * @dev_class: the class, subclass, prog-if triple for this device
935 * @dev_class_mask: the class mask for this device
937 * This macro is used to create a struct pci_device_id that matches a
938 * specific PCI class. The vendor, device, subvendor, and subdevice
939 * fields will be set to PCI_ANY_ID.
941 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
942 .class = (dev_class), .class_mask = (dev_class_mask), \
943 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
944 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
947 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
948 * @vend: the vendor name
949 * @dev: the 16 bit PCI Device ID
951 * This macro is used to create a struct pci_device_id that matches a
952 * specific PCI device. The subvendor, and subdevice fields will be set
953 * to PCI_ANY_ID. The macro allows the next field to follow as the device
956 #define PCI_VDEVICE(vend, dev) \
957 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
958 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
961 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
962 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
963 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
964 * @data: the driver data to be filled
966 * This macro is used to create a struct pci_device_id that matches a
967 * specific PCI device. The subvendor, and subdevice fields will be set
970 #define PCI_DEVICE_DATA(vend, dev, data) \
971 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
972 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
973 .driver_data = (kernel_ulong_t)(data)
976 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
977 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
978 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
979 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
980 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
981 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
982 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
985 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
986 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
987 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
988 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
990 /* These external functions are only available when PCI support is enabled */
993 extern unsigned int pci_flags;
995 static inline void pci_set_flags(int flags) { pci_flags = flags; }
996 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
997 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
998 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1000 void pcie_bus_configure_settings(struct pci_bus *bus);
1002 enum pcie_bus_config_types {
1003 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1004 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1005 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1006 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1007 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1010 extern enum pcie_bus_config_types pcie_bus_config;
1012 extern struct bus_type pci_bus_type;
1014 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1015 * code, or PCI core code. */
1016 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1017 /* Some device drivers need know if PCI is initiated */
1018 int no_pci_devices(void);
1020 void pcibios_resource_survey_bus(struct pci_bus *bus);
1021 void pcibios_bus_add_device(struct pci_dev *pdev);
1022 void pcibios_add_bus(struct pci_bus *bus);
1023 void pcibios_remove_bus(struct pci_bus *bus);
1024 void pcibios_fixup_bus(struct pci_bus *);
1025 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1026 /* Architecture-specific versions may override this (weak) */
1027 char *pcibios_setup(char *str);
1029 /* Used only when drivers/pci/setup.c is used */
1030 resource_size_t pcibios_align_resource(void *, const struct resource *,
1034 /* Weak but can be overridden by arch */
1035 void pci_fixup_cardbus(struct pci_bus *);
1037 /* Generic PCI functions used internally */
1039 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1040 struct resource *res);
1041 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1042 struct pci_bus_region *region);
1043 void pcibios_scan_specific_bus(int busn);
1044 struct pci_bus *pci_find_bus(int domain, int busnr);
1045 void pci_bus_add_devices(const struct pci_bus *bus);
1046 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1047 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1048 struct pci_ops *ops, void *sysdata,
1049 struct list_head *resources);
1050 int pci_host_probe(struct pci_host_bridge *bridge);
1051 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1052 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1053 void pci_bus_release_busn_res(struct pci_bus *b);
1054 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1055 struct pci_ops *ops, void *sysdata,
1056 struct list_head *resources);
1057 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1058 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1060 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1062 struct hotplug_slot *hotplug);
1063 void pci_destroy_slot(struct pci_slot *slot);
1065 void pci_dev_assign_slot(struct pci_dev *dev);
1067 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1069 int pci_scan_slot(struct pci_bus *bus, int devfn);
1070 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1071 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1072 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1073 void pci_bus_add_device(struct pci_dev *dev);
1074 void pci_read_bridge_bases(struct pci_bus *child);
1075 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1076 struct resource *res);
1077 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1078 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1079 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1080 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1081 void pci_dev_put(struct pci_dev *dev);
1082 void pci_remove_bus(struct pci_bus *b);
1083 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1084 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1085 void pci_stop_root_bus(struct pci_bus *bus);
1086 void pci_remove_root_bus(struct pci_bus *bus);
1087 void pci_setup_cardbus(struct pci_bus *bus);
1088 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1089 void pci_sort_breadthfirst(void);
1090 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1091 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1093 /* Generic PCI functions exported to card drivers */
1095 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1096 u8 pci_find_capability(struct pci_dev *dev, int cap);
1097 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1098 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1099 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1100 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1101 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1102 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1103 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1105 u64 pci_get_dsn(struct pci_dev *dev);
1107 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1108 struct pci_dev *from);
1109 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1110 unsigned int ss_vendor, unsigned int ss_device,
1111 struct pci_dev *from);
1112 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1113 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1114 unsigned int devfn);
1115 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1116 int pci_dev_present(const struct pci_device_id *ids);
1118 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1119 int where, u8 *val);
1120 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1121 int where, u16 *val);
1122 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1123 int where, u32 *val);
1124 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1126 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1127 int where, u16 val);
1128 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1129 int where, u32 val);
1131 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1132 int where, int size, u32 *val);
1133 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1134 int where, int size, u32 val);
1135 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1136 int where, int size, u32 *val);
1137 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1138 int where, int size, u32 val);
1140 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1142 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1143 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1144 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1145 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1146 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1147 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1149 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1150 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1151 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1152 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1153 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1154 u16 clear, u16 set);
1155 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1156 u32 clear, u32 set);
1158 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1161 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1164 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1167 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1170 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1173 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1176 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1179 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1182 /* User-space driven config access */
1183 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1184 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1185 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1186 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1187 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1188 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1190 int __must_check pci_enable_device(struct pci_dev *dev);
1191 int __must_check pci_enable_device_io(struct pci_dev *dev);
1192 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1193 int __must_check pci_reenable_device(struct pci_dev *);
1194 int __must_check pcim_enable_device(struct pci_dev *pdev);
1195 void pcim_pin_device(struct pci_dev *pdev);
1197 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1200 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1201 * writable and no quirk has marked the feature broken.
1203 return !pdev->broken_intx_masking;
1206 static inline int pci_is_enabled(struct pci_dev *pdev)
1208 return (atomic_read(&pdev->enable_cnt) > 0);
1211 static inline int pci_is_managed(struct pci_dev *pdev)
1213 return pdev->is_managed;
1216 void pci_disable_device(struct pci_dev *dev);
1218 extern unsigned int pcibios_max_latency;
1219 void pci_set_master(struct pci_dev *dev);
1220 void pci_clear_master(struct pci_dev *dev);
1222 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1223 int pci_set_cacheline_size(struct pci_dev *dev);
1224 int __must_check pci_set_mwi(struct pci_dev *dev);
1225 int __must_check pcim_set_mwi(struct pci_dev *dev);
1226 int pci_try_set_mwi(struct pci_dev *dev);
1227 void pci_clear_mwi(struct pci_dev *dev);
1228 void pci_disable_parity(struct pci_dev *dev);
1229 void pci_intx(struct pci_dev *dev, int enable);
1230 bool pci_check_and_mask_intx(struct pci_dev *dev);
1231 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1232 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1233 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1234 int pcix_get_max_mmrbc(struct pci_dev *dev);
1235 int pcix_get_mmrbc(struct pci_dev *dev);
1236 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1237 int pcie_get_readrq(struct pci_dev *dev);
1238 int pcie_set_readrq(struct pci_dev *dev, int rq);
1239 int pcie_get_mps(struct pci_dev *dev);
1240 int pcie_set_mps(struct pci_dev *dev, int mps);
1241 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1242 enum pci_bus_speed *speed,
1243 enum pcie_link_width *width);
1244 void pcie_print_link_status(struct pci_dev *dev);
1245 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1246 int pcie_flr(struct pci_dev *dev);
1247 int __pci_reset_function_locked(struct pci_dev *dev);
1248 int pci_reset_function(struct pci_dev *dev);
1249 int pci_reset_function_locked(struct pci_dev *dev);
1250 int pci_try_reset_function(struct pci_dev *dev);
1251 int pci_probe_reset_slot(struct pci_slot *slot);
1252 int pci_probe_reset_bus(struct pci_bus *bus);
1253 int pci_reset_bus(struct pci_dev *dev);
1254 void pci_reset_secondary_bus(struct pci_dev *dev);
1255 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1256 void pci_update_resource(struct pci_dev *dev, int resno);
1257 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1258 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1259 void pci_release_resource(struct pci_dev *dev, int resno);
1260 static inline int pci_rebar_bytes_to_size(u64 bytes)
1262 bytes = roundup_pow_of_two(bytes);
1264 /* Return BAR size as defined in the resizable BAR specification */
1265 return max(ilog2(bytes), 20) - 20;
1268 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1269 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1270 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1271 bool pci_device_is_present(struct pci_dev *pdev);
1272 void pci_ignore_hotplug(struct pci_dev *dev);
1273 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1274 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1276 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1277 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1278 const char *fmt, ...);
1279 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1281 /* ROM control related routines */
1282 int pci_enable_rom(struct pci_dev *pdev);
1283 void pci_disable_rom(struct pci_dev *pdev);
1284 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1285 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1287 /* Power management related routines */
1288 int pci_save_state(struct pci_dev *dev);
1289 void pci_restore_state(struct pci_dev *dev);
1290 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1291 int pci_load_saved_state(struct pci_dev *dev,
1292 struct pci_saved_state *state);
1293 int pci_load_and_free_saved_state(struct pci_dev *dev,
1294 struct pci_saved_state **state);
1295 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1296 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1297 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1298 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1299 void pci_pme_active(struct pci_dev *dev, bool enable);
1300 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1301 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1302 int pci_prepare_to_sleep(struct pci_dev *dev);
1303 int pci_back_from_sleep(struct pci_dev *dev);
1304 bool pci_dev_run_wake(struct pci_dev *dev);
1305 void pci_d3cold_enable(struct pci_dev *dev);
1306 void pci_d3cold_disable(struct pci_dev *dev);
1307 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1308 void pci_resume_bus(struct pci_bus *bus);
1309 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1311 /* For use by arch with custom probe code */
1312 void set_pcie_port_type(struct pci_dev *pdev);
1313 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1315 /* Functions for PCI Hotplug drivers to use */
1316 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1317 unsigned int pci_rescan_bus(struct pci_bus *bus);
1318 void pci_lock_rescan_remove(void);
1319 void pci_unlock_rescan_remove(void);
1321 /* Vital Product Data routines */
1322 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1323 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1325 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1326 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1327 void pci_bus_assign_resources(const struct pci_bus *bus);
1328 void pci_bus_claim_resources(struct pci_bus *bus);
1329 void pci_bus_size_bridges(struct pci_bus *bus);
1330 int pci_claim_resource(struct pci_dev *, int);
1331 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1332 void pci_assign_unassigned_resources(void);
1333 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1334 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1335 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1336 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1337 void pdev_enable_device(struct pci_dev *);
1338 int pci_enable_resources(struct pci_dev *, int mask);
1339 void pci_assign_irq(struct pci_dev *dev);
1340 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1341 #define HAVE_PCI_REQ_REGIONS 2
1342 int __must_check pci_request_regions(struct pci_dev *, const char *);
1343 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1344 void pci_release_regions(struct pci_dev *);
1345 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1346 void pci_release_region(struct pci_dev *, int);
1347 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1348 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1349 void pci_release_selected_regions(struct pci_dev *, int);
1351 /* drivers/pci/bus.c */
1352 void pci_add_resource(struct list_head *resources, struct resource *res);
1353 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1354 resource_size_t offset);
1355 void pci_free_resource_list(struct list_head *resources);
1356 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1357 unsigned int flags);
1358 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1359 void pci_bus_remove_resources(struct pci_bus *bus);
1360 int devm_request_pci_bus_resources(struct device *dev,
1361 struct list_head *resources);
1363 /* Temporary until new and working PCI SBR API in place */
1364 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1366 #define pci_bus_for_each_resource(bus, res, i) \
1368 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1371 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1372 struct resource *res, resource_size_t size,
1373 resource_size_t align, resource_size_t min,
1374 unsigned long type_mask,
1375 resource_size_t (*alignf)(void *,
1376 const struct resource *,
1382 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1383 resource_size_t size);
1384 unsigned long pci_address_to_pio(phys_addr_t addr);
1385 phys_addr_t pci_pio_to_address(unsigned long pio);
1386 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1387 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1388 phys_addr_t phys_addr);
1389 void pci_unmap_iospace(struct resource *res);
1390 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1391 resource_size_t offset,
1392 resource_size_t size);
1393 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1394 struct resource *res);
1396 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1398 struct pci_bus_region region;
1400 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1401 return region.start;
1404 /* Proper probing supporting hot-pluggable devices */
1405 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1406 const char *mod_name);
1408 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1409 #define pci_register_driver(driver) \
1410 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1412 void pci_unregister_driver(struct pci_driver *dev);
1415 * module_pci_driver() - Helper macro for registering a PCI driver
1416 * @__pci_driver: pci_driver struct
1418 * Helper macro for PCI drivers which do not do anything special in module
1419 * init/exit. This eliminates a lot of boilerplate. Each module may only
1420 * use this macro once, and calling it replaces module_init() and module_exit()
1422 #define module_pci_driver(__pci_driver) \
1423 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1426 * builtin_pci_driver() - Helper macro for registering a PCI driver
1427 * @__pci_driver: pci_driver struct
1429 * Helper macro for PCI drivers which do not do anything special in their
1430 * init code. This eliminates a lot of boilerplate. Each driver may only
1431 * use this macro once, and calling it replaces device_initcall(...)
1433 #define builtin_pci_driver(__pci_driver) \
1434 builtin_driver(__pci_driver, pci_register_driver)
1436 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1437 int pci_add_dynid(struct pci_driver *drv,
1438 unsigned int vendor, unsigned int device,
1439 unsigned int subvendor, unsigned int subdevice,
1440 unsigned int class, unsigned int class_mask,
1441 unsigned long driver_data);
1442 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1443 struct pci_dev *dev);
1444 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1447 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1449 int pci_cfg_space_size(struct pci_dev *dev);
1450 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1451 void pci_setup_bridge(struct pci_bus *bus);
1452 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1453 unsigned long type);
1455 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1456 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1458 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1459 unsigned int command_bits, u32 flags);
1462 * Virtual interrupts allow for more interrupts to be allocated
1463 * than the device has interrupts for. These are not programmed
1464 * into the device's MSI-X table and must be handled by some
1465 * other driver means.
1467 #define PCI_IRQ_VIRTUAL (1 << 4)
1469 #define PCI_IRQ_ALL_TYPES \
1470 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1472 /* kmem_cache style wrapper around pci_alloc_consistent() */
1474 #include <linux/dmapool.h>
1476 #define pci_pool dma_pool
1477 #define pci_pool_create(name, pdev, size, align, allocation) \
1478 dma_pool_create(name, &pdev->dev, size, align, allocation)
1479 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1480 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1481 #define pci_pool_zalloc(pool, flags, handle) \
1482 dma_pool_zalloc(pool, flags, handle)
1483 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1486 u32 vector; /* Kernel uses to write allocated vector */
1487 u16 entry; /* Driver uses to specify entry, OS writes */
1490 #ifdef CONFIG_PCI_MSI
1491 int pci_msi_vec_count(struct pci_dev *dev);
1492 void pci_disable_msi(struct pci_dev *dev);
1493 int pci_msix_vec_count(struct pci_dev *dev);
1494 void pci_disable_msix(struct pci_dev *dev);
1495 void pci_restore_msi_state(struct pci_dev *dev);
1496 int pci_msi_enabled(void);
1497 int pci_enable_msi(struct pci_dev *dev);
1498 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1499 int minvec, int maxvec);
1500 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1501 struct msix_entry *entries, int nvec)
1503 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1508 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1509 unsigned int max_vecs, unsigned int flags,
1510 struct irq_affinity *affd);
1512 void pci_free_irq_vectors(struct pci_dev *dev);
1513 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1514 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1517 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1518 static inline void pci_disable_msi(struct pci_dev *dev) { }
1519 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1520 static inline void pci_disable_msix(struct pci_dev *dev) { }
1521 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1522 static inline int pci_msi_enabled(void) { return 0; }
1523 static inline int pci_enable_msi(struct pci_dev *dev)
1525 static inline int pci_enable_msix_range(struct pci_dev *dev,
1526 struct msix_entry *entries, int minvec, int maxvec)
1528 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1529 struct msix_entry *entries, int nvec)
1533 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1534 unsigned int max_vecs, unsigned int flags,
1535 struct irq_affinity *aff_desc)
1537 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1542 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1546 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1548 if (WARN_ON_ONCE(nr > 0))
1552 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1555 return cpu_possible_mask;
1560 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1561 * @d: the INTx IRQ domain
1562 * @node: the DT node for the device whose interrupt we're translating
1563 * @intspec: the interrupt specifier data from the DT
1564 * @intsize: the number of entries in @intspec
1565 * @out_hwirq: pointer at which to write the hwirq number
1566 * @out_type: pointer at which to write the interrupt type
1568 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1569 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1570 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1571 * INTx value to obtain the hwirq number.
1573 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1575 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1576 struct device_node *node,
1578 unsigned int intsize,
1579 unsigned long *out_hwirq,
1580 unsigned int *out_type)
1582 const u32 intx = intspec[0];
1584 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1587 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1591 #ifdef CONFIG_PCIEPORTBUS
1592 extern bool pcie_ports_disabled;
1593 extern bool pcie_ports_native;
1595 #define pcie_ports_disabled true
1596 #define pcie_ports_native false
1599 #define PCIE_LINK_STATE_L0S BIT(0)
1600 #define PCIE_LINK_STATE_L1 BIT(1)
1601 #define PCIE_LINK_STATE_CLKPM BIT(2)
1602 #define PCIE_LINK_STATE_L1_1 BIT(3)
1603 #define PCIE_LINK_STATE_L1_2 BIT(4)
1604 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1605 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1607 #ifdef CONFIG_PCIEASPM
1608 int pci_disable_link_state(struct pci_dev *pdev, int state);
1609 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1610 void pcie_no_aspm(void);
1611 bool pcie_aspm_support_enabled(void);
1612 bool pcie_aspm_enabled(struct pci_dev *pdev);
1614 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1616 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1618 static inline void pcie_no_aspm(void) { }
1619 static inline bool pcie_aspm_support_enabled(void) { return false; }
1620 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1623 #ifdef CONFIG_PCIEAER
1624 bool pci_aer_available(void);
1626 static inline bool pci_aer_available(void) { return false; }
1629 bool pci_ats_disabled(void);
1631 void pci_cfg_access_lock(struct pci_dev *dev);
1632 bool pci_cfg_access_trylock(struct pci_dev *dev);
1633 void pci_cfg_access_unlock(struct pci_dev *dev);
1635 int pci_dev_trylock(struct pci_dev *dev);
1636 void pci_dev_unlock(struct pci_dev *dev);
1639 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1640 * a PCI domain is defined to be a set of PCI buses which share
1641 * configuration space.
1643 #ifdef CONFIG_PCI_DOMAINS
1644 extern int pci_domains_supported;
1646 enum { pci_domains_supported = 0 };
1647 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1648 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1649 #endif /* CONFIG_PCI_DOMAINS */
1652 * Generic implementation for PCI domain support. If your
1653 * architecture does not need custom management of PCI
1654 * domains then this implementation will be used
1656 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1657 static inline int pci_domain_nr(struct pci_bus *bus)
1659 return bus->domain_nr;
1662 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1664 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1667 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1670 /* Some architectures require additional setup to direct VGA traffic */
1671 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1672 unsigned int command_bits, u32 flags);
1673 void pci_register_set_vga_state(arch_set_vga_state_t func);
1676 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1678 return pci_request_selected_regions(pdev,
1679 pci_select_bars(pdev, IORESOURCE_IO), name);
1683 pci_release_io_regions(struct pci_dev *pdev)
1685 return pci_release_selected_regions(pdev,
1686 pci_select_bars(pdev, IORESOURCE_IO));
1690 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1692 return pci_request_selected_regions(pdev,
1693 pci_select_bars(pdev, IORESOURCE_MEM), name);
1697 pci_release_mem_regions(struct pci_dev *pdev)
1699 return pci_release_selected_regions(pdev,
1700 pci_select_bars(pdev, IORESOURCE_MEM));
1703 #else /* CONFIG_PCI is not enabled */
1705 static inline void pci_set_flags(int flags) { }
1706 static inline void pci_add_flags(int flags) { }
1707 static inline void pci_clear_flags(int flags) { }
1708 static inline int pci_has_flag(int flag) { return 0; }
1711 * If the system does not have PCI, clearly these return errors. Define
1712 * these as simple inline functions to avoid hair in drivers.
1714 #define _PCI_NOP(o, s, t) \
1715 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1717 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1719 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1720 _PCI_NOP(o, word, u16 x) \
1721 _PCI_NOP(o, dword, u32 x)
1722 _PCI_NOP_ALL(read, *)
1723 _PCI_NOP_ALL(write,)
1725 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1726 unsigned int device,
1727 struct pci_dev *from)
1730 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1731 unsigned int device,
1732 unsigned int ss_vendor,
1733 unsigned int ss_device,
1734 struct pci_dev *from)
1737 static inline struct pci_dev *pci_get_class(unsigned int class,
1738 struct pci_dev *from)
1741 #define pci_dev_present(ids) (0)
1742 #define no_pci_devices() (1)
1743 #define pci_dev_put(dev) do { } while (0)
1745 static inline void pci_set_master(struct pci_dev *dev) { }
1746 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1747 static inline void pci_disable_device(struct pci_dev *dev) { }
1748 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1749 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1751 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1752 struct module *owner,
1753 const char *mod_name)
1755 static inline int pci_register_driver(struct pci_driver *drv)
1757 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1758 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1760 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1763 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1766 static inline u64 pci_get_dsn(struct pci_dev *dev)
1769 /* Power management related routines */
1770 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1771 static inline void pci_restore_state(struct pci_dev *dev) { }
1772 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1774 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1776 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1779 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1783 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1784 struct resource *res)
1786 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1788 static inline void pci_release_regions(struct pci_dev *dev) { }
1790 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1791 phys_addr_t addr, resource_size_t size)
1794 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1796 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1798 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1801 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1802 unsigned int bus, unsigned int devfn)
1805 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1806 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1808 #define dev_is_pci(d) (false)
1809 #define dev_is_pf(d) (false)
1810 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1812 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1813 struct device_node *node,
1815 unsigned int intsize,
1816 unsigned long *out_hwirq,
1817 unsigned int *out_type)
1820 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1821 struct pci_dev *dev)
1823 static inline bool pci_ats_disabled(void) { return true; }
1825 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1831 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1832 unsigned int max_vecs, unsigned int flags,
1833 struct irq_affinity *aff_desc)
1837 #endif /* CONFIG_PCI */
1840 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1841 unsigned int max_vecs, unsigned int flags)
1843 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1847 /* Include architecture-dependent settings and functions */
1849 #include <asm/pci.h>
1851 /* These two functions provide almost identical functionality. Depending
1852 * on the architecture, one will be implemented as a wrapper around the
1853 * other (in drivers/pci/mmap.c).
1855 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1856 * is expected to be an offset within that region.
1858 * pci_mmap_page_range() is the legacy architecture-specific interface,
1859 * which accepts a "user visible" resource address converted by
1860 * pci_resource_to_user(), as used in the legacy mmap() interface in
1863 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1864 struct vm_area_struct *vma,
1865 enum pci_mmap_state mmap_state, int write_combine);
1866 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1867 struct vm_area_struct *vma,
1868 enum pci_mmap_state mmap_state, int write_combine);
1870 #ifndef arch_can_pci_mmap_wc
1871 #define arch_can_pci_mmap_wc() 0
1874 #ifndef arch_can_pci_mmap_io
1875 #define arch_can_pci_mmap_io() 0
1876 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1878 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1881 #ifndef pci_root_bus_fwnode
1882 #define pci_root_bus_fwnode(bus) NULL
1886 * These helpers provide future and backwards compatibility
1887 * for accessing popular PCI BAR info
1889 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1890 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1891 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1892 #define pci_resource_len(dev,bar) \
1893 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1895 (pci_resource_end((dev), (bar)) - \
1896 pci_resource_start((dev), (bar)) + 1))
1899 * Similar to the helpers above, these manipulate per-pci_dev
1900 * driver-specific data. They are really just a wrapper around
1901 * the generic device structure functions of these calls.
1903 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1905 return dev_get_drvdata(&pdev->dev);
1908 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1910 dev_set_drvdata(&pdev->dev, data);
1913 static inline const char *pci_name(const struct pci_dev *pdev)
1915 return dev_name(&pdev->dev);
1918 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1919 const struct resource *rsrc,
1920 resource_size_t *start, resource_size_t *end);
1923 * The world is not perfect and supplies us with broken PCI devices.
1924 * For at least a part of these bugs we need a work-around, so both
1925 * generic (drivers/pci/quirks.c) and per-architecture code can define
1926 * fixup hooks to be called for particular buggy devices.
1930 u16 vendor; /* Or PCI_ANY_ID */
1931 u16 device; /* Or PCI_ANY_ID */
1932 u32 class; /* Or PCI_ANY_ID */
1933 unsigned int class_shift; /* should be 0, 8, 16 */
1934 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1937 void (*hook)(struct pci_dev *dev);
1941 enum pci_fixup_pass {
1942 pci_fixup_early, /* Before probing BARs */
1943 pci_fixup_header, /* After reading configuration header */
1944 pci_fixup_final, /* Final phase of device fixups */
1945 pci_fixup_enable, /* pci_enable_device() time */
1946 pci_fixup_resume, /* pci_device_resume() */
1947 pci_fixup_suspend, /* pci_device_suspend() */
1948 pci_fixup_resume_early, /* pci_device_resume_early() */
1949 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1952 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1953 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1954 class_shift, hook) \
1955 __ADDRESSABLE(hook) \
1956 asm(".section " #sec ", \"a\" \n" \
1958 ".short " #vendor ", " #device " \n" \
1959 ".long " #class ", " #class_shift " \n" \
1960 ".long " #hook " - . \n" \
1964 * Clang's LTO may rename static functions in C, but has no way to
1965 * handle such renamings when referenced from inline asm. To work
1966 * around this, create global C stubs for these cases.
1968 #ifdef CONFIG_LTO_CLANG
1969 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1970 class_shift, hook, stub) \
1971 void __cficanonical stub(struct pci_dev *dev); \
1972 void __cficanonical stub(struct pci_dev *dev) \
1976 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1979 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1980 class_shift, hook, stub) \
1981 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1985 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1986 class_shift, hook) \
1987 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1988 class_shift, hook, __UNIQUE_ID(hook))
1990 /* Anonymous variables would be nice... */
1991 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1992 class_shift, hook) \
1993 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1994 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1995 = { vendor, device, class, class_shift, hook };
1998 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1999 class_shift, hook) \
2000 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2001 hook, vendor, device, class, class_shift, hook)
2002 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2003 class_shift, hook) \
2004 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2005 hook, vendor, device, class, class_shift, hook)
2006 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2007 class_shift, hook) \
2008 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2009 hook, vendor, device, class, class_shift, hook)
2010 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2011 class_shift, hook) \
2012 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2013 hook, vendor, device, class, class_shift, hook)
2014 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2015 class_shift, hook) \
2016 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2017 resume##hook, vendor, device, class, class_shift, hook)
2018 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2019 class_shift, hook) \
2020 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2021 resume_early##hook, vendor, device, class, class_shift, hook)
2022 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2023 class_shift, hook) \
2024 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2025 suspend##hook, vendor, device, class, class_shift, hook)
2026 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2027 class_shift, hook) \
2028 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2029 suspend_late##hook, vendor, device, class, class_shift, hook)
2031 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2032 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2033 hook, vendor, device, PCI_ANY_ID, 0, hook)
2034 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2035 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2036 hook, vendor, device, PCI_ANY_ID, 0, hook)
2037 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2038 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2039 hook, vendor, device, PCI_ANY_ID, 0, hook)
2040 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2041 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2042 hook, vendor, device, PCI_ANY_ID, 0, hook)
2043 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2044 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2045 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2046 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2047 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2048 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2049 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2050 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2051 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2052 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2053 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2054 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2056 #ifdef CONFIG_PCI_QUIRKS
2057 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2059 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2060 struct pci_dev *dev) { }
2063 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2064 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2065 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2066 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2067 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2069 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2071 extern int pci_pci_problems;
2072 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2073 #define PCIPCI_TRITON 2
2074 #define PCIPCI_NATOMA 4
2075 #define PCIPCI_VIAETBF 8
2076 #define PCIPCI_VSFX 16
2077 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2078 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2080 extern unsigned long pci_cardbus_io_size;
2081 extern unsigned long pci_cardbus_mem_size;
2082 extern u8 pci_dfl_cache_line_size;
2083 extern u8 pci_cache_line_size;
2085 /* Architecture-specific versions may override these (weak) */
2086 void pcibios_disable_device(struct pci_dev *dev);
2087 void pcibios_set_master(struct pci_dev *dev);
2088 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2089 enum pcie_reset_state state);
2090 int pcibios_add_device(struct pci_dev *dev);
2091 void pcibios_release_device(struct pci_dev *dev);
2093 void pcibios_penalize_isa_irq(int irq, int active);
2095 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2097 int pcibios_alloc_irq(struct pci_dev *dev);
2098 void pcibios_free_irq(struct pci_dev *dev);
2099 resource_size_t pcibios_default_alignment(void);
2101 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2102 void __init pci_mmcfg_early_init(void);
2103 void __init pci_mmcfg_late_init(void);
2105 static inline void pci_mmcfg_early_init(void) { }
2106 static inline void pci_mmcfg_late_init(void) { }
2109 int pci_ext_cfg_avail(void);
2111 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2112 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2114 #ifdef CONFIG_PCI_IOV
2115 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2116 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2118 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2119 void pci_disable_sriov(struct pci_dev *dev);
2121 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2122 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2123 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2124 int pci_num_vf(struct pci_dev *dev);
2125 int pci_vfs_assigned(struct pci_dev *dev);
2126 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2127 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2128 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2129 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2130 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2132 /* Arch may override these (weak) */
2133 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2134 int pcibios_sriov_disable(struct pci_dev *pdev);
2135 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2137 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2141 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2145 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2148 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2149 struct pci_dev *virtfn, int id)
2153 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2157 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2159 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2160 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2161 static inline int pci_vfs_assigned(struct pci_dev *dev)
2163 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2165 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2167 #define pci_sriov_configure_simple NULL
2168 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2170 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2173 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2174 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2175 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2179 * pci_pcie_cap - get the saved PCIe capability offset
2182 * PCIe capability offset is calculated at PCI device initialization
2183 * time and saved in the data structure. This function returns saved
2184 * PCIe capability offset. Using this instead of pci_find_capability()
2185 * reduces unnecessary search in the PCI configuration space. If you
2186 * need to calculate PCIe capability offset from raw device for some
2187 * reasons, please use pci_find_capability() instead.
2189 static inline int pci_pcie_cap(struct pci_dev *dev)
2191 return dev->pcie_cap;
2195 * pci_is_pcie - check if the PCI device is PCI Express capable
2198 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2200 static inline bool pci_is_pcie(struct pci_dev *dev)
2202 return pci_pcie_cap(dev);
2206 * pcie_caps_reg - get the PCIe Capabilities Register
2209 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2211 return dev->pcie_flags_reg;
2215 * pci_pcie_type - get the PCIe device/port type
2218 static inline int pci_pcie_type(const struct pci_dev *dev)
2220 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2224 * pcie_find_root_port - Get the PCIe root port device
2227 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2228 * for a given PCI/PCIe Device.
2230 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2233 if (pci_is_pcie(dev) &&
2234 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2236 dev = pci_upstream_bridge(dev);
2242 void pci_request_acs(void);
2243 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2244 bool pci_acs_path_enabled(struct pci_dev *start,
2245 struct pci_dev *end, u16 acs_flags);
2246 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2248 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2249 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2251 /* Large Resource Data Type Tag Item Names */
2252 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2253 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2254 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2256 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2257 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2258 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2260 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2261 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2262 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2263 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2264 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2267 * pci_vpd_alloc - Allocate buffer and read VPD into it
2269 * @size: pointer to field where VPD length is returned
2271 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2273 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2276 * pci_vpd_find_id_string - Locate id string in VPD
2277 * @buf: Pointer to buffered VPD data
2278 * @len: The length of the buffer area in which to search
2279 * @size: Pointer to field where length of id string is returned
2281 * Returns the index of the id string or -ENOENT if not found.
2283 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2286 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2287 * @buf: Pointer to buffered VPD data
2288 * @len: The length of the buffer area in which to search
2289 * @kw: The keyword to search for
2290 * @size: Pointer to field where length of found keyword data is returned
2292 * Returns the index of the information field keyword data or -ENOENT if
2295 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2296 const char *kw, unsigned int *size);
2299 * pci_vpd_check_csum - Check VPD checksum
2300 * @buf: Pointer to buffered VPD data
2303 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2305 int pci_vpd_check_csum(const void *buf, unsigned int len);
2307 /* PCI <-> OF binding helpers */
2311 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2312 bool pci_host_of_has_msi_map(struct device *dev);
2314 /* Arch may override this (weak) */
2315 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2317 #else /* CONFIG_OF */
2318 static inline struct irq_domain *
2319 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2320 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2321 #endif /* CONFIG_OF */
2323 static inline struct device_node *
2324 pci_device_to_OF_node(const struct pci_dev *pdev)
2326 return pdev ? pdev->dev.of_node : NULL;
2329 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2331 return bus ? bus->dev.of_node : NULL;
2335 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2338 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2339 bool pci_pr3_present(struct pci_dev *pdev);
2341 static inline struct irq_domain *
2342 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2343 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2347 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2349 return pdev->dev.archdata.edev;
2353 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2354 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2355 int pci_for_each_dma_alias(struct pci_dev *pdev,
2356 int (*fn)(struct pci_dev *pdev,
2357 u16 alias, void *data), void *data);
2359 /* Helper functions for operation of device flag */
2360 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2362 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2364 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2366 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2368 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2370 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2374 * pci_ari_enabled - query ARI forwarding status
2377 * Returns true if ARI forwarding is enabled.
2379 static inline bool pci_ari_enabled(struct pci_bus *bus)
2381 return bus->self && bus->self->ari_enabled;
2385 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2386 * @pdev: PCI device to check
2388 * Walk upwards from @pdev and check for each encountered bridge if it's part
2389 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2390 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2392 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2394 struct pci_dev *parent = pdev;
2396 if (pdev->is_thunderbolt)
2399 while ((parent = pci_upstream_bridge(parent)))
2400 if (parent->is_thunderbolt)
2406 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2407 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2410 /* Provide the legacy pci_dma_* API */
2411 #include <linux/pci-dma-compat.h>
2413 #define pci_printk(level, pdev, fmt, arg...) \
2414 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2416 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2417 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2418 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2419 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2420 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2421 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2422 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2423 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2425 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2426 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2428 #define pci_info_ratelimited(pdev, fmt, arg...) \
2429 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2431 #define pci_WARN(pdev, condition, fmt, arg...) \
2432 WARN(condition, "%s %s: " fmt, \
2433 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2435 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2436 WARN_ONCE(condition, "%s %s: " fmt, \
2437 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2439 #endif /* LINUX_PCI_H */