1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
43 #include <linux/pci_ids.h>
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
53 * The PCI interface treats multi-function devices as independent
54 * devices. The slot/function address of each device is encoded
55 * in a single byte as follows:
60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
61 * In the interest of not exposing interfaces to user-space unnecessarily,
62 * the following kernel-only defines are being added here.
64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
68 /* pci_slot represents a physical slot */
70 struct pci_bus *bus; /* Bus this slot is on */
71 struct list_head list; /* Node in list of slots */
72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
77 static inline const char *pci_slot_name(const struct pci_slot *slot)
79 return kobject_name(&slot->kobj);
82 /* File state for mmap()s on /proc/bus/pci/X/Y */
88 /* For PCI devices, the region numbers are assigned this way: */
90 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
94 /* #6: expansion ROM resource */
97 /* Device-specific resources */
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
103 /* PCI-to-PCI (P2P) bridge windows */
104 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
105 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
106 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
108 /* CardBus bridge windows */
109 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
110 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
111 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
112 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
114 /* Total number of bridge resources for P2P and CardBus */
115 #define PCI_BRIDGE_RESOURCE_NUM 4
117 /* Resources assigned to buses behind the bridge */
118 PCI_BRIDGE_RESOURCES,
119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
120 PCI_BRIDGE_RESOURCE_NUM - 1,
122 /* Total resources associated with a PCI device */
125 /* Preserve this for compatibility */
126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
130 * enum pci_interrupt_pin - PCI INTx interrupt values
131 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
132 * @PCI_INTERRUPT_INTA: PCI INTA pin
133 * @PCI_INTERRUPT_INTB: PCI INTB pin
134 * @PCI_INTERRUPT_INTC: PCI INTC pin
135 * @PCI_INTERRUPT_INTD: PCI INTD pin
137 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
138 * PCI_INTERRUPT_PIN register.
140 enum pci_interrupt_pin {
141 PCI_INTERRUPT_UNKNOWN,
148 /* The number of legacy PCI INTx interrupts */
149 #define PCI_NUM_INTX 4
152 * pci_power_t values must match the bits in the Capabilities PME_Support
153 * and Control/Status PowerState fields in the Power Management capability.
155 typedef int __bitwise pci_power_t;
157 #define PCI_D0 ((pci_power_t __force) 0)
158 #define PCI_D1 ((pci_power_t __force) 1)
159 #define PCI_D2 ((pci_power_t __force) 2)
160 #define PCI_D3hot ((pci_power_t __force) 3)
161 #define PCI_D3cold ((pci_power_t __force) 4)
162 #define PCI_UNKNOWN ((pci_power_t __force) 5)
163 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
165 /* Remember to update this when the list above changes! */
166 extern const char *pci_power_names[];
168 static inline const char *pci_power_name(pci_power_t state)
170 return pci_power_names[1 + (__force int) state];
174 * typedef pci_channel_state_t
176 * The pci_channel state describes connectivity between the CPU and
177 * the PCI device. If some PCI bus between here and the PCI device
178 * has crashed or locked up, this info is reflected here.
180 typedef unsigned int __bitwise pci_channel_state_t;
183 /* I/O channel is in normal state */
184 pci_channel_io_normal = (__force pci_channel_state_t) 1,
186 /* I/O to channel is blocked */
187 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
189 /* PCI card is dead */
190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
193 typedef unsigned int __bitwise pcie_reset_state_t;
195 enum pcie_reset_state {
196 /* Reset is NOT asserted (Use to deassert reset) */
197 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
199 /* Use #PERST to reset PCIe device */
200 pcie_warm_reset = (__force pcie_reset_state_t) 2,
202 /* Use PCIe Hot Reset to reset device */
203 pcie_hot_reset = (__force pcie_reset_state_t) 3
206 typedef unsigned short __bitwise pci_dev_flags_t;
208 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
210 /* Device configuration is irrevocably lost if disabled into D3 */
211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
212 /* Provide indication device is assigned by a Virtual Machine Manager */
213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
214 /* Flag for quirk use to store if quirk-specific ACS is enabled */
215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
216 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
218 /* Do not use bus resets for device */
219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
220 /* Do not use PM reset even if device advertises NoSoftRst- */
221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
222 /* Get VPD from function 0 VPD */
223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
224 /* A non-root bridge where translation occurs, stop alias search here */
225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
226 /* Do not use FLR even if device advertises PCI_AF_CAP */
227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
228 /* Don't use Relaxed Ordering for TLPs directed at this device */
229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
232 enum pci_irq_reroute_variant {
233 INTEL_IRQ_REROUTE_VARIANT = 1,
234 MAX_IRQ_REROUTE_VARIANTS = 3
237 typedef unsigned short __bitwise pci_bus_flags_t;
239 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
240 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
241 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
242 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
245 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
246 enum pcie_link_width {
247 PCIE_LNK_WIDTH_RESRV = 0x00,
255 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
258 /* See matching string table in pci_speed_string() */
260 PCI_SPEED_33MHz = 0x00,
261 PCI_SPEED_66MHz = 0x01,
262 PCI_SPEED_66MHz_PCIX = 0x02,
263 PCI_SPEED_100MHz_PCIX = 0x03,
264 PCI_SPEED_133MHz_PCIX = 0x04,
265 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
266 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
267 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
268 PCI_SPEED_66MHz_PCIX_266 = 0x09,
269 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
270 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
276 PCI_SPEED_66MHz_PCIX_533 = 0x11,
277 PCI_SPEED_100MHz_PCIX_533 = 0x12,
278 PCI_SPEED_133MHz_PCIX_533 = 0x13,
279 PCIE_SPEED_2_5GT = 0x14,
280 PCIE_SPEED_5_0GT = 0x15,
281 PCIE_SPEED_8_0GT = 0x16,
282 PCIE_SPEED_16_0GT = 0x17,
283 PCIE_SPEED_32_0GT = 0x18,
284 PCIE_SPEED_64_0GT = 0x19,
285 PCI_SPEED_UNKNOWN = 0xff,
288 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
289 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
291 struct pci_cap_saved_data {
298 struct pci_cap_saved_state {
299 struct hlist_node next;
300 struct pci_cap_saved_data cap;
310 struct pcie_link_state;
315 /* The pci_dev structure describes PCI devices */
317 struct list_head bus_list; /* Node in per-bus list */
318 struct pci_bus *bus; /* Bus this device is on */
319 struct pci_bus *subordinate; /* Bus this device bridges to */
321 void *sysdata; /* Hook for sys-specific extension */
322 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
323 struct pci_slot *slot; /* Physical slot this device is in */
325 unsigned int devfn; /* Encoded device & function index */
326 unsigned short vendor;
327 unsigned short device;
328 unsigned short subsystem_vendor;
329 unsigned short subsystem_device;
330 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
331 u8 revision; /* PCI revision, low byte of class word */
332 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
333 #ifdef CONFIG_PCIEAER
334 u16 aer_cap; /* AER capability offset */
335 struct aer_stats *aer_stats; /* AER stats for this device */
337 #ifdef CONFIG_PCIEPORTBUS
338 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
339 struct pci_dev *rcec; /* Associated RCEC device */
341 u8 pcie_cap; /* PCIe capability offset */
342 u8 msi_cap; /* MSI capability offset */
343 u8 msix_cap; /* MSI-X capability offset */
344 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
345 u8 rom_base_reg; /* Config register controlling ROM */
346 u8 pin; /* Interrupt pin this device uses */
347 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
348 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
350 struct pci_driver *driver; /* Driver bound to this device */
351 u64 dma_mask; /* Mask of the bits of bus address this
352 device implements. Normally this is
353 0xffffffff. You only need to change
354 this if your device has broken DMA
355 or supports 64-bit transfers. */
357 struct device_dma_parameters dma_parms;
359 pci_power_t current_state; /* Current operating state. In ACPI,
360 this is D0-D3, D0 being fully
361 functional, and D3 being off. */
362 unsigned int imm_ready:1; /* Supports Immediate Readiness */
363 u8 pm_cap; /* PM capability offset */
364 unsigned int pme_support:5; /* Bitmask of states from which PME#
366 unsigned int pme_poll:1; /* Poll device's PME status bit */
367 unsigned int d1_support:1; /* Low power state D1 is supported */
368 unsigned int d2_support:1; /* Low power state D2 is supported */
369 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
370 unsigned int no_d3cold:1; /* D3cold is forbidden */
371 unsigned int bridge_d3:1; /* Allow D3 for bridge */
372 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
373 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
374 decoding during BAR sizing */
375 unsigned int wakeup_prepared:1;
376 unsigned int runtime_d3cold:1; /* Whether go through runtime
377 D3cold, not set for devices
378 powered on/off by the
379 corresponding bridge */
380 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
381 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
382 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
383 controlled exclusively by
385 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
387 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
388 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
390 #ifdef CONFIG_PCIEASPM
391 struct pcie_link_state *link_state; /* ASPM link state */
392 unsigned int ltr_path:1; /* Latency Tolerance Reporting
393 supported from root to here */
394 u16 l1ss; /* L1SS Capability pointer */
396 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
398 pci_channel_state_t error_state; /* Current connectivity state */
399 struct device dev; /* Generic device interface */
401 int cfg_size; /* Size of config space */
404 * Instead of touching interrupt line and base address registers
405 * directly, use the values stored here. They might be different!
408 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
410 bool match_driver; /* Skip attaching driver */
412 unsigned int transparent:1; /* Subtractive decode bridge */
413 unsigned int io_window:1; /* Bridge has I/O window */
414 unsigned int pref_window:1; /* Bridge has pref mem window */
415 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
416 unsigned int multifunction:1; /* Multi-function device */
418 unsigned int is_busmaster:1; /* Is busmaster */
419 unsigned int no_msi:1; /* May not use MSI */
420 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
421 unsigned int block_cfg_access:1; /* Config space access blocked */
422 unsigned int broken_parity_status:1; /* Generates false positive parity */
423 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
424 unsigned int msi_enabled:1;
425 unsigned int msix_enabled:1;
426 unsigned int ari_enabled:1; /* ARI forwarding */
427 unsigned int ats_enabled:1; /* Address Translation Svc */
428 unsigned int pasid_enabled:1; /* Process Address Space ID */
429 unsigned int pri_enabled:1; /* Page Request Interface */
430 unsigned int is_managed:1;
431 unsigned int needs_freset:1; /* Requires fundamental reset */
432 unsigned int state_saved:1;
433 unsigned int is_physfn:1;
434 unsigned int is_virtfn:1;
435 unsigned int reset_fn:1;
436 unsigned int is_hotplug_bridge:1;
437 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
438 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
440 * Devices marked being untrusted are the ones that can potentially
441 * execute DMA attacks and similar. They are typically connected
442 * through external ports such as Thunderbolt but not limited to
443 * that. When an IOMMU is enabled they should be getting full
444 * mappings to make sure they cannot access arbitrary memory.
446 unsigned int untrusted:1;
448 * Info from the platform, e.g., ACPI or device tree, may mark a
449 * device as "external-facing". An external-facing device is
450 * itself internal but devices downstream from it are external.
452 unsigned int external_facing:1;
453 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
454 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
455 unsigned int irq_managed:1;
456 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
457 unsigned int is_probed:1; /* Device probing in progress */
458 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
459 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
460 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
461 pci_dev_flags_t dev_flags;
462 atomic_t enable_cnt; /* pci_enable_device has been called */
464 u32 saved_config_space[16]; /* Config space saved at suspend time */
465 struct hlist_head saved_cap_space;
466 int rom_attr_enabled; /* Display of ROM attribute enabled? */
467 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
468 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
470 #ifdef CONFIG_HOTPLUG_PCI_PCIE
471 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
473 #ifdef CONFIG_PCIE_PTM
474 unsigned int ptm_root:1;
475 unsigned int ptm_enabled:1;
478 #ifdef CONFIG_PCI_MSI
479 const struct attribute_group **msi_irq_groups;
482 #ifdef CONFIG_PCIE_DPC
484 unsigned int dpc_rp_extensions:1;
487 #ifdef CONFIG_PCI_ATS
489 struct pci_sriov *sriov; /* PF: SR-IOV info */
490 struct pci_dev *physfn; /* VF: related PF */
492 u16 ats_cap; /* ATS Capability offset */
493 u8 ats_stu; /* ATS Smallest Translation Unit */
495 #ifdef CONFIG_PCI_PRI
496 u16 pri_cap; /* PRI Capability offset */
497 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
498 unsigned int pasid_required:1; /* PRG Response PASID Required */
500 #ifdef CONFIG_PCI_PASID
501 u16 pasid_cap; /* PASID Capability offset */
504 #ifdef CONFIG_PCI_P2PDMA
505 struct pci_p2pdma __rcu *p2pdma;
507 u16 acs_cap; /* ACS Capability offset */
508 phys_addr_t rom; /* Physical address if not from BAR */
509 size_t romlen; /* Length if not from BAR */
510 char *driver_override; /* Driver name to force a match */
512 unsigned long priv_flags; /* Private flags for the PCI driver */
515 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
517 #ifdef CONFIG_PCI_IOV
524 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
526 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
527 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
529 static inline int pci_channel_offline(struct pci_dev *pdev)
531 return (pdev->error_state != pci_channel_io_normal);
534 struct pci_host_bridge {
536 struct pci_bus *bus; /* Root bus */
538 struct pci_ops *child_ops;
541 struct list_head windows; /* resource_entry */
542 struct list_head dma_ranges; /* dma ranges resource list */
543 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
544 int (*map_irq)(const struct pci_dev *, u8, u8);
545 void (*release_fn)(struct pci_host_bridge *);
547 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
548 unsigned int no_ext_tags:1; /* No Extended Tags */
549 unsigned int native_aer:1; /* OS may use PCIe AER */
550 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
551 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
552 unsigned int native_pme:1; /* OS may use PCIe PME */
553 unsigned int native_ltr:1; /* OS may use PCIe LTR */
554 unsigned int native_dpc:1; /* OS may use PCIe DPC */
555 unsigned int preserve_config:1; /* Preserve FW resource setup */
556 unsigned int size_windows:1; /* Enable root bus sizing */
557 unsigned int msi_domain:1; /* Bridge wants MSI domain */
559 /* Resource alignment requirements */
560 resource_size_t (*align_resource)(struct pci_dev *dev,
561 const struct resource *res,
562 resource_size_t start,
563 resource_size_t size,
564 resource_size_t align);
565 unsigned long private[] ____cacheline_aligned;
568 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
570 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
572 return (void *)bridge->private;
575 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
577 return container_of(priv, struct pci_host_bridge, private);
580 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
581 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
583 void pci_free_host_bridge(struct pci_host_bridge *bridge);
584 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
586 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
587 void (*release_fn)(struct pci_host_bridge *),
590 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
593 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
594 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
595 * buses below host bridges or subtractive decode bridges) go in the list.
596 * Use pci_bus_for_each_resource() to iterate through all the resources.
600 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
601 * and there's no way to program the bridge with the details of the window.
602 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
603 * decode bit set, because they are explicit and can be programmed with _SRS.
605 #define PCI_SUBTRACTIVE_DECODE 0x1
607 struct pci_bus_resource {
608 struct list_head list;
609 struct resource *res;
613 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
616 struct list_head node; /* Node in list of buses */
617 struct pci_bus *parent; /* Parent bus this bridge is on */
618 struct list_head children; /* List of child buses */
619 struct list_head devices; /* List of devices on this bus */
620 struct pci_dev *self; /* Bridge device as seen by parent */
621 struct list_head slots; /* List of slots on this bus;
622 protected by pci_slot_mutex */
623 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
624 struct list_head resources; /* Address space routed to this bus */
625 struct resource busn_res; /* Bus numbers routed to this bus */
627 struct pci_ops *ops; /* Configuration access functions */
628 void *sysdata; /* Hook for sys-specific extension */
629 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
631 unsigned char number; /* Bus number */
632 unsigned char primary; /* Number of primary bridge */
633 unsigned char max_bus_speed; /* enum pci_bus_speed */
634 unsigned char cur_bus_speed; /* enum pci_bus_speed */
635 #ifdef CONFIG_PCI_DOMAINS_GENERIC
641 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
642 pci_bus_flags_t bus_flags; /* Inherited by child buses */
643 struct device *bridge;
645 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
646 struct bin_attribute *legacy_mem; /* Legacy mem */
647 unsigned int is_added:1;
650 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
652 static inline u16 pci_dev_id(struct pci_dev *dev)
654 return PCI_DEVID(dev->bus->number, dev->devfn);
658 * Returns true if the PCI bus is root (behind host-PCI bridge),
661 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
662 * This is incorrect because "virtual" buses added for SR-IOV (via
663 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
665 static inline bool pci_is_root_bus(struct pci_bus *pbus)
667 return !(pbus->parent);
671 * pci_is_bridge - check if the PCI device is a bridge
674 * Return true if the PCI device is bridge whether it has subordinate
677 static inline bool pci_is_bridge(struct pci_dev *dev)
679 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
680 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
683 #define for_each_pci_bridge(dev, bus) \
684 list_for_each_entry(dev, &bus->devices, bus_list) \
685 if (!pci_is_bridge(dev)) {} else
687 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
689 dev = pci_physfn(dev);
690 if (pci_is_root_bus(dev->bus))
693 return dev->bus->self;
696 #ifdef CONFIG_PCI_MSI
697 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
699 return pci_dev->msi_enabled || pci_dev->msix_enabled;
702 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
705 /* Error values that may be returned by PCI functions */
706 #define PCIBIOS_SUCCESSFUL 0x00
707 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
708 #define PCIBIOS_BAD_VENDOR_ID 0x83
709 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
710 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
711 #define PCIBIOS_SET_FAILED 0x88
712 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
714 /* Translate above to generic errno for passing back through non-PCI code */
715 static inline int pcibios_err_to_errno(int err)
717 if (err <= PCIBIOS_SUCCESSFUL)
718 return err; /* Assume already errno */
721 case PCIBIOS_FUNC_NOT_SUPPORTED:
723 case PCIBIOS_BAD_VENDOR_ID:
725 case PCIBIOS_DEVICE_NOT_FOUND:
727 case PCIBIOS_BAD_REGISTER_NUMBER:
729 case PCIBIOS_SET_FAILED:
731 case PCIBIOS_BUFFER_TOO_SMALL:
738 /* Low-level architecture-dependent routines */
741 int (*add_bus)(struct pci_bus *bus);
742 void (*remove_bus)(struct pci_bus *bus);
743 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
744 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
745 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
749 * ACPI needs to be able to access PCI config space before we've done a
750 * PCI bus scan and created pci_bus structures.
752 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
753 int reg, int len, u32 *val);
754 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
755 int reg, int len, u32 val);
757 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
758 typedef u64 pci_bus_addr_t;
760 typedef u32 pci_bus_addr_t;
763 struct pci_bus_region {
764 pci_bus_addr_t start;
769 spinlock_t lock; /* Protects list, index */
770 struct list_head list; /* For IDs added at runtime */
775 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
776 * a set of callbacks in struct pci_error_handlers, that device driver
777 * will be notified of PCI bus errors, and will be driven to recovery
778 * when an error occurs.
781 typedef unsigned int __bitwise pci_ers_result_t;
783 enum pci_ers_result {
784 /* No result/none/not supported in device driver */
785 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
787 /* Device driver can recover without slot reset */
788 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
790 /* Device driver wants slot to be reset */
791 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
793 /* Device has completely failed, is unrecoverable */
794 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
796 /* Device driver is fully recovered and operational */
797 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
799 /* No AER capabilities registered for the driver */
800 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
803 /* PCI bus error event callbacks */
804 struct pci_error_handlers {
805 /* PCI bus error detected on this device */
806 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
807 pci_channel_state_t error);
809 /* MMIO has been re-enabled, but not DMA */
810 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
812 /* PCI slot has been reset */
813 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
815 /* PCI function reset prepare or completed */
816 void (*reset_prepare)(struct pci_dev *dev);
817 void (*reset_done)(struct pci_dev *dev);
819 /* Device driver may resume normal operations */
820 void (*resume)(struct pci_dev *dev);
827 * struct pci_driver - PCI driver structure
828 * @node: List of driver structures.
829 * @name: Driver name.
830 * @id_table: Pointer to table of device IDs the driver is
831 * interested in. Most drivers should export this
832 * table using MODULE_DEVICE_TABLE(pci,...).
833 * @probe: This probing function gets called (during execution
834 * of pci_register_driver() for already existing
835 * devices or later if a new device gets inserted) for
836 * all PCI devices which match the ID table and are not
837 * "owned" by the other drivers yet. This function gets
838 * passed a "struct pci_dev \*" for each device whose
839 * entry in the ID table matches the device. The probe
840 * function returns zero when the driver chooses to
841 * take "ownership" of the device or an error code
842 * (negative number) otherwise.
843 * The probe function always gets called from process
844 * context, so it can sleep.
845 * @remove: The remove() function gets called whenever a device
846 * being handled by this driver is removed (either during
847 * deregistration of the driver or when it's manually
848 * pulled out of a hot-pluggable slot).
849 * The remove function always gets called from process
850 * context, so it can sleep.
851 * @suspend: Put device into low power state.
852 * @resume: Wake device from low power state.
853 * (Please see Documentation/power/pci.rst for descriptions
854 * of PCI Power Management and the related functions.)
855 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
856 * Intended to stop any idling DMA operations.
857 * Useful for enabling wake-on-lan (NIC) or changing
858 * the power state of a device before reboot.
859 * e.g. drivers/net/e100.c.
860 * @sriov_configure: Optional driver callback to allow configuration of
861 * number of VFs to enable via sysfs "sriov_numvfs" file.
862 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
863 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
864 * This will change MSI-X Table Size in the VF Message Control
866 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
867 * MSI-X vectors available for distribution to the VFs.
868 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
869 * @groups: Sysfs attribute groups.
870 * @dev_groups: Attributes attached to the device that will be
871 * created once it is bound to the driver.
872 * @driver: Driver model structure.
873 * @dynids: List of dynamically added device IDs.
876 struct list_head node;
878 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
879 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
880 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
881 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
882 int (*resume)(struct pci_dev *dev); /* Device woken up */
883 void (*shutdown)(struct pci_dev *dev);
884 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
885 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
886 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
887 const struct pci_error_handlers *err_handler;
888 const struct attribute_group **groups;
889 const struct attribute_group **dev_groups;
890 struct device_driver driver;
891 struct pci_dynids dynids;
894 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
897 * PCI_DEVICE - macro used to describe a specific PCI device
898 * @vend: the 16 bit PCI Vendor ID
899 * @dev: the 16 bit PCI Device ID
901 * This macro is used to create a struct pci_device_id that matches a
902 * specific device. The subvendor and subdevice fields will be set to
905 #define PCI_DEVICE(vend,dev) \
906 .vendor = (vend), .device = (dev), \
907 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
910 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
911 * @vend: the 16 bit PCI Vendor ID
912 * @dev: the 16 bit PCI Device ID
913 * @subvend: the 16 bit PCI Subvendor ID
914 * @subdev: the 16 bit PCI Subdevice ID
916 * This macro is used to create a struct pci_device_id that matches a
917 * specific device with subsystem information.
919 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
920 .vendor = (vend), .device = (dev), \
921 .subvendor = (subvend), .subdevice = (subdev)
924 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
925 * @dev_class: the class, subclass, prog-if triple for this device
926 * @dev_class_mask: the class mask for this device
928 * This macro is used to create a struct pci_device_id that matches a
929 * specific PCI class. The vendor, device, subvendor, and subdevice
930 * fields will be set to PCI_ANY_ID.
932 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
933 .class = (dev_class), .class_mask = (dev_class_mask), \
934 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
935 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
938 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
939 * @vend: the vendor name
940 * @dev: the 16 bit PCI Device ID
942 * This macro is used to create a struct pci_device_id that matches a
943 * specific PCI device. The subvendor, and subdevice fields will be set
944 * to PCI_ANY_ID. The macro allows the next field to follow as the device
947 #define PCI_VDEVICE(vend, dev) \
948 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
949 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
952 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
953 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
954 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
955 * @data: the driver data to be filled
957 * This macro is used to create a struct pci_device_id that matches a
958 * specific PCI device. The subvendor, and subdevice fields will be set
961 #define PCI_DEVICE_DATA(vend, dev, data) \
962 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
963 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
964 .driver_data = (kernel_ulong_t)(data)
967 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
968 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
969 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
970 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
971 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
972 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
973 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
976 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
977 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
978 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
979 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
981 /* These external functions are only available when PCI support is enabled */
984 extern unsigned int pci_flags;
986 static inline void pci_set_flags(int flags) { pci_flags = flags; }
987 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
988 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
989 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
991 void pcie_bus_configure_settings(struct pci_bus *bus);
993 enum pcie_bus_config_types {
994 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
995 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
996 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
997 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
998 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1001 extern enum pcie_bus_config_types pcie_bus_config;
1003 extern struct bus_type pci_bus_type;
1005 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1006 * code, or PCI core code. */
1007 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1008 /* Some device drivers need know if PCI is initiated */
1009 int no_pci_devices(void);
1011 void pcibios_resource_survey_bus(struct pci_bus *bus);
1012 void pcibios_bus_add_device(struct pci_dev *pdev);
1013 void pcibios_add_bus(struct pci_bus *bus);
1014 void pcibios_remove_bus(struct pci_bus *bus);
1015 void pcibios_fixup_bus(struct pci_bus *);
1016 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1017 /* Architecture-specific versions may override this (weak) */
1018 char *pcibios_setup(char *str);
1020 /* Used only when drivers/pci/setup.c is used */
1021 resource_size_t pcibios_align_resource(void *, const struct resource *,
1025 /* Weak but can be overridden by arch */
1026 void pci_fixup_cardbus(struct pci_bus *);
1028 /* Generic PCI functions used internally */
1030 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1031 struct resource *res);
1032 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1033 struct pci_bus_region *region);
1034 void pcibios_scan_specific_bus(int busn);
1035 struct pci_bus *pci_find_bus(int domain, int busnr);
1036 void pci_bus_add_devices(const struct pci_bus *bus);
1037 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1038 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1039 struct pci_ops *ops, void *sysdata,
1040 struct list_head *resources);
1041 int pci_host_probe(struct pci_host_bridge *bridge);
1042 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1043 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1044 void pci_bus_release_busn_res(struct pci_bus *b);
1045 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1046 struct pci_ops *ops, void *sysdata,
1047 struct list_head *resources);
1048 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1049 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1051 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1053 struct hotplug_slot *hotplug);
1054 void pci_destroy_slot(struct pci_slot *slot);
1056 void pci_dev_assign_slot(struct pci_dev *dev);
1058 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1060 int pci_scan_slot(struct pci_bus *bus, int devfn);
1061 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1062 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1063 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1064 void pci_bus_add_device(struct pci_dev *dev);
1065 void pci_read_bridge_bases(struct pci_bus *child);
1066 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1067 struct resource *res);
1068 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1069 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1070 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1071 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1072 void pci_dev_put(struct pci_dev *dev);
1073 void pci_remove_bus(struct pci_bus *b);
1074 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1075 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1076 void pci_stop_root_bus(struct pci_bus *bus);
1077 void pci_remove_root_bus(struct pci_bus *bus);
1078 void pci_setup_cardbus(struct pci_bus *bus);
1079 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1080 void pci_sort_breadthfirst(void);
1081 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1082 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1084 /* Generic PCI functions exported to card drivers */
1086 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1087 u8 pci_find_capability(struct pci_dev *dev, int cap);
1088 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1089 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1090 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1091 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1092 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1093 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1094 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1096 u64 pci_get_dsn(struct pci_dev *dev);
1098 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1099 struct pci_dev *from);
1100 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1101 unsigned int ss_vendor, unsigned int ss_device,
1102 struct pci_dev *from);
1103 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1104 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1105 unsigned int devfn);
1106 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1107 int pci_dev_present(const struct pci_device_id *ids);
1109 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1110 int where, u8 *val);
1111 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1112 int where, u16 *val);
1113 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1114 int where, u32 *val);
1115 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1117 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1118 int where, u16 val);
1119 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1120 int where, u32 val);
1122 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1123 int where, int size, u32 *val);
1124 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1125 int where, int size, u32 val);
1126 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1127 int where, int size, u32 *val);
1128 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1129 int where, int size, u32 val);
1131 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1133 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1134 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1135 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1136 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1137 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1138 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1140 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1141 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1142 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1143 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1144 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1145 u16 clear, u16 set);
1146 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1147 u32 clear, u32 set);
1149 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1152 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1155 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1158 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1161 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1164 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1167 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1170 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1173 /* User-space driven config access */
1174 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1175 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1176 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1177 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1178 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1179 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1181 int __must_check pci_enable_device(struct pci_dev *dev);
1182 int __must_check pci_enable_device_io(struct pci_dev *dev);
1183 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1184 int __must_check pci_reenable_device(struct pci_dev *);
1185 int __must_check pcim_enable_device(struct pci_dev *pdev);
1186 void pcim_pin_device(struct pci_dev *pdev);
1188 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1191 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1192 * writable and no quirk has marked the feature broken.
1194 return !pdev->broken_intx_masking;
1197 static inline int pci_is_enabled(struct pci_dev *pdev)
1199 return (atomic_read(&pdev->enable_cnt) > 0);
1202 static inline int pci_is_managed(struct pci_dev *pdev)
1204 return pdev->is_managed;
1207 void pci_disable_device(struct pci_dev *dev);
1209 extern unsigned int pcibios_max_latency;
1210 void pci_set_master(struct pci_dev *dev);
1211 void pci_clear_master(struct pci_dev *dev);
1213 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1214 int pci_set_cacheline_size(struct pci_dev *dev);
1215 int __must_check pci_set_mwi(struct pci_dev *dev);
1216 int __must_check pcim_set_mwi(struct pci_dev *dev);
1217 int pci_try_set_mwi(struct pci_dev *dev);
1218 void pci_clear_mwi(struct pci_dev *dev);
1219 void pci_disable_parity(struct pci_dev *dev);
1220 void pci_intx(struct pci_dev *dev, int enable);
1221 bool pci_check_and_mask_intx(struct pci_dev *dev);
1222 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1223 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1224 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1225 int pcix_get_max_mmrbc(struct pci_dev *dev);
1226 int pcix_get_mmrbc(struct pci_dev *dev);
1227 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1228 int pcie_get_readrq(struct pci_dev *dev);
1229 int pcie_set_readrq(struct pci_dev *dev, int rq);
1230 int pcie_get_mps(struct pci_dev *dev);
1231 int pcie_set_mps(struct pci_dev *dev, int mps);
1232 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1233 enum pci_bus_speed *speed,
1234 enum pcie_link_width *width);
1235 void pcie_print_link_status(struct pci_dev *dev);
1236 bool pcie_has_flr(struct pci_dev *dev);
1237 int pcie_flr(struct pci_dev *dev);
1238 int __pci_reset_function_locked(struct pci_dev *dev);
1239 int pci_reset_function(struct pci_dev *dev);
1240 int pci_reset_function_locked(struct pci_dev *dev);
1241 int pci_try_reset_function(struct pci_dev *dev);
1242 int pci_probe_reset_slot(struct pci_slot *slot);
1243 int pci_probe_reset_bus(struct pci_bus *bus);
1244 int pci_reset_bus(struct pci_dev *dev);
1245 void pci_reset_secondary_bus(struct pci_dev *dev);
1246 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1247 void pci_update_resource(struct pci_dev *dev, int resno);
1248 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1249 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1250 void pci_release_resource(struct pci_dev *dev, int resno);
1251 static inline int pci_rebar_bytes_to_size(u64 bytes)
1253 bytes = roundup_pow_of_two(bytes);
1255 /* Return BAR size as defined in the resizable BAR specification */
1256 return max(ilog2(bytes), 20) - 20;
1259 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1260 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1261 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1262 bool pci_device_is_present(struct pci_dev *pdev);
1263 void pci_ignore_hotplug(struct pci_dev *dev);
1264 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1265 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1267 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1268 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1269 const char *fmt, ...);
1270 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1272 /* ROM control related routines */
1273 int pci_enable_rom(struct pci_dev *pdev);
1274 void pci_disable_rom(struct pci_dev *pdev);
1275 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1276 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1278 /* Power management related routines */
1279 int pci_save_state(struct pci_dev *dev);
1280 void pci_restore_state(struct pci_dev *dev);
1281 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1282 int pci_load_saved_state(struct pci_dev *dev,
1283 struct pci_saved_state *state);
1284 int pci_load_and_free_saved_state(struct pci_dev *dev,
1285 struct pci_saved_state **state);
1286 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1287 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1289 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1290 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1291 u16 cap, unsigned int size);
1292 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1293 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1294 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1295 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1296 void pci_pme_active(struct pci_dev *dev, bool enable);
1297 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1298 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1299 int pci_prepare_to_sleep(struct pci_dev *dev);
1300 int pci_back_from_sleep(struct pci_dev *dev);
1301 bool pci_dev_run_wake(struct pci_dev *dev);
1302 void pci_d3cold_enable(struct pci_dev *dev);
1303 void pci_d3cold_disable(struct pci_dev *dev);
1304 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1305 void pci_resume_bus(struct pci_bus *bus);
1306 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1308 /* For use by arch with custom probe code */
1309 void set_pcie_port_type(struct pci_dev *pdev);
1310 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1312 /* Functions for PCI Hotplug drivers to use */
1313 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1314 unsigned int pci_rescan_bus(struct pci_bus *bus);
1315 void pci_lock_rescan_remove(void);
1316 void pci_unlock_rescan_remove(void);
1318 /* Vital Product Data routines */
1319 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1320 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1322 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1323 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1324 void pci_bus_assign_resources(const struct pci_bus *bus);
1325 void pci_bus_claim_resources(struct pci_bus *bus);
1326 void pci_bus_size_bridges(struct pci_bus *bus);
1327 int pci_claim_resource(struct pci_dev *, int);
1328 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1329 void pci_assign_unassigned_resources(void);
1330 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1331 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1332 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1333 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1334 void pdev_enable_device(struct pci_dev *);
1335 int pci_enable_resources(struct pci_dev *, int mask);
1336 void pci_assign_irq(struct pci_dev *dev);
1337 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1338 #define HAVE_PCI_REQ_REGIONS 2
1339 int __must_check pci_request_regions(struct pci_dev *, const char *);
1340 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1341 void pci_release_regions(struct pci_dev *);
1342 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1343 void pci_release_region(struct pci_dev *, int);
1344 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1345 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1346 void pci_release_selected_regions(struct pci_dev *, int);
1348 /* drivers/pci/bus.c */
1349 void pci_add_resource(struct list_head *resources, struct resource *res);
1350 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1351 resource_size_t offset);
1352 void pci_free_resource_list(struct list_head *resources);
1353 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1354 unsigned int flags);
1355 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1356 void pci_bus_remove_resources(struct pci_bus *bus);
1357 int devm_request_pci_bus_resources(struct device *dev,
1358 struct list_head *resources);
1360 /* Temporary until new and working PCI SBR API in place */
1361 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1363 #define pci_bus_for_each_resource(bus, res, i) \
1365 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1368 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1369 struct resource *res, resource_size_t size,
1370 resource_size_t align, resource_size_t min,
1371 unsigned long type_mask,
1372 resource_size_t (*alignf)(void *,
1373 const struct resource *,
1379 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1380 resource_size_t size);
1381 unsigned long pci_address_to_pio(phys_addr_t addr);
1382 phys_addr_t pci_pio_to_address(unsigned long pio);
1383 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1384 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1385 phys_addr_t phys_addr);
1386 void pci_unmap_iospace(struct resource *res);
1387 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1388 resource_size_t offset,
1389 resource_size_t size);
1390 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1391 struct resource *res);
1393 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1395 struct pci_bus_region region;
1397 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1398 return region.start;
1401 /* Proper probing supporting hot-pluggable devices */
1402 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1403 const char *mod_name);
1405 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1406 #define pci_register_driver(driver) \
1407 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1409 void pci_unregister_driver(struct pci_driver *dev);
1412 * module_pci_driver() - Helper macro for registering a PCI driver
1413 * @__pci_driver: pci_driver struct
1415 * Helper macro for PCI drivers which do not do anything special in module
1416 * init/exit. This eliminates a lot of boilerplate. Each module may only
1417 * use this macro once, and calling it replaces module_init() and module_exit()
1419 #define module_pci_driver(__pci_driver) \
1420 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1423 * builtin_pci_driver() - Helper macro for registering a PCI driver
1424 * @__pci_driver: pci_driver struct
1426 * Helper macro for PCI drivers which do not do anything special in their
1427 * init code. This eliminates a lot of boilerplate. Each driver may only
1428 * use this macro once, and calling it replaces device_initcall(...)
1430 #define builtin_pci_driver(__pci_driver) \
1431 builtin_driver(__pci_driver, pci_register_driver)
1433 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1434 int pci_add_dynid(struct pci_driver *drv,
1435 unsigned int vendor, unsigned int device,
1436 unsigned int subvendor, unsigned int subdevice,
1437 unsigned int class, unsigned int class_mask,
1438 unsigned long driver_data);
1439 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1440 struct pci_dev *dev);
1441 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1444 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1446 int pci_cfg_space_size(struct pci_dev *dev);
1447 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1448 void pci_setup_bridge(struct pci_bus *bus);
1449 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1450 unsigned long type);
1452 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1453 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1455 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1456 unsigned int command_bits, u32 flags);
1459 * Virtual interrupts allow for more interrupts to be allocated
1460 * than the device has interrupts for. These are not programmed
1461 * into the device's MSI-X table and must be handled by some
1462 * other driver means.
1464 #define PCI_IRQ_VIRTUAL (1 << 4)
1466 #define PCI_IRQ_ALL_TYPES \
1467 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1469 /* kmem_cache style wrapper around pci_alloc_consistent() */
1471 #include <linux/dmapool.h>
1473 #define pci_pool dma_pool
1474 #define pci_pool_create(name, pdev, size, align, allocation) \
1475 dma_pool_create(name, &pdev->dev, size, align, allocation)
1476 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1477 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1478 #define pci_pool_zalloc(pool, flags, handle) \
1479 dma_pool_zalloc(pool, flags, handle)
1480 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1483 u32 vector; /* Kernel uses to write allocated vector */
1484 u16 entry; /* Driver uses to specify entry, OS writes */
1487 #ifdef CONFIG_PCI_MSI
1488 int pci_msi_vec_count(struct pci_dev *dev);
1489 void pci_disable_msi(struct pci_dev *dev);
1490 int pci_msix_vec_count(struct pci_dev *dev);
1491 void pci_disable_msix(struct pci_dev *dev);
1492 void pci_restore_msi_state(struct pci_dev *dev);
1493 int pci_msi_enabled(void);
1494 int pci_enable_msi(struct pci_dev *dev);
1495 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1496 int minvec, int maxvec);
1497 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1498 struct msix_entry *entries, int nvec)
1500 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1505 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1506 unsigned int max_vecs, unsigned int flags,
1507 struct irq_affinity *affd);
1509 void pci_free_irq_vectors(struct pci_dev *dev);
1510 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1511 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1514 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1515 static inline void pci_disable_msi(struct pci_dev *dev) { }
1516 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1517 static inline void pci_disable_msix(struct pci_dev *dev) { }
1518 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1519 static inline int pci_msi_enabled(void) { return 0; }
1520 static inline int pci_enable_msi(struct pci_dev *dev)
1522 static inline int pci_enable_msix_range(struct pci_dev *dev,
1523 struct msix_entry *entries, int minvec, int maxvec)
1525 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1526 struct msix_entry *entries, int nvec)
1530 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1531 unsigned int max_vecs, unsigned int flags,
1532 struct irq_affinity *aff_desc)
1534 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1539 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1543 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1545 if (WARN_ON_ONCE(nr > 0))
1549 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1552 return cpu_possible_mask;
1557 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1558 * @d: the INTx IRQ domain
1559 * @node: the DT node for the device whose interrupt we're translating
1560 * @intspec: the interrupt specifier data from the DT
1561 * @intsize: the number of entries in @intspec
1562 * @out_hwirq: pointer at which to write the hwirq number
1563 * @out_type: pointer at which to write the interrupt type
1565 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1566 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1567 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1568 * INTx value to obtain the hwirq number.
1570 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1572 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1573 struct device_node *node,
1575 unsigned int intsize,
1576 unsigned long *out_hwirq,
1577 unsigned int *out_type)
1579 const u32 intx = intspec[0];
1581 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1584 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1588 #ifdef CONFIG_PCIEPORTBUS
1589 extern bool pcie_ports_disabled;
1590 extern bool pcie_ports_native;
1592 #define pcie_ports_disabled true
1593 #define pcie_ports_native false
1596 #define PCIE_LINK_STATE_L0S BIT(0)
1597 #define PCIE_LINK_STATE_L1 BIT(1)
1598 #define PCIE_LINK_STATE_CLKPM BIT(2)
1599 #define PCIE_LINK_STATE_L1_1 BIT(3)
1600 #define PCIE_LINK_STATE_L1_2 BIT(4)
1601 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1602 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1604 #ifdef CONFIG_PCIEASPM
1605 int pci_disable_link_state(struct pci_dev *pdev, int state);
1606 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1607 void pcie_no_aspm(void);
1608 bool pcie_aspm_support_enabled(void);
1609 bool pcie_aspm_enabled(struct pci_dev *pdev);
1611 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1613 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1615 static inline void pcie_no_aspm(void) { }
1616 static inline bool pcie_aspm_support_enabled(void) { return false; }
1617 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1620 #ifdef CONFIG_PCIEAER
1621 bool pci_aer_available(void);
1623 static inline bool pci_aer_available(void) { return false; }
1626 bool pci_ats_disabled(void);
1628 void pci_cfg_access_lock(struct pci_dev *dev);
1629 bool pci_cfg_access_trylock(struct pci_dev *dev);
1630 void pci_cfg_access_unlock(struct pci_dev *dev);
1632 int pci_dev_trylock(struct pci_dev *dev);
1633 void pci_dev_unlock(struct pci_dev *dev);
1636 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1637 * a PCI domain is defined to be a set of PCI buses which share
1638 * configuration space.
1640 #ifdef CONFIG_PCI_DOMAINS
1641 extern int pci_domains_supported;
1643 enum { pci_domains_supported = 0 };
1644 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1645 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1646 #endif /* CONFIG_PCI_DOMAINS */
1649 * Generic implementation for PCI domain support. If your
1650 * architecture does not need custom management of PCI
1651 * domains then this implementation will be used
1653 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1654 static inline int pci_domain_nr(struct pci_bus *bus)
1656 return bus->domain_nr;
1659 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1661 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1664 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1667 /* Some architectures require additional setup to direct VGA traffic */
1668 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1669 unsigned int command_bits, u32 flags);
1670 void pci_register_set_vga_state(arch_set_vga_state_t func);
1673 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1675 return pci_request_selected_regions(pdev,
1676 pci_select_bars(pdev, IORESOURCE_IO), name);
1680 pci_release_io_regions(struct pci_dev *pdev)
1682 return pci_release_selected_regions(pdev,
1683 pci_select_bars(pdev, IORESOURCE_IO));
1687 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1689 return pci_request_selected_regions(pdev,
1690 pci_select_bars(pdev, IORESOURCE_MEM), name);
1694 pci_release_mem_regions(struct pci_dev *pdev)
1696 return pci_release_selected_regions(pdev,
1697 pci_select_bars(pdev, IORESOURCE_MEM));
1700 #else /* CONFIG_PCI is not enabled */
1702 static inline void pci_set_flags(int flags) { }
1703 static inline void pci_add_flags(int flags) { }
1704 static inline void pci_clear_flags(int flags) { }
1705 static inline int pci_has_flag(int flag) { return 0; }
1708 * If the system does not have PCI, clearly these return errors. Define
1709 * these as simple inline functions to avoid hair in drivers.
1711 #define _PCI_NOP(o, s, t) \
1712 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1714 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1716 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1717 _PCI_NOP(o, word, u16 x) \
1718 _PCI_NOP(o, dword, u32 x)
1719 _PCI_NOP_ALL(read, *)
1720 _PCI_NOP_ALL(write,)
1722 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1723 unsigned int device,
1724 struct pci_dev *from)
1727 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1728 unsigned int device,
1729 unsigned int ss_vendor,
1730 unsigned int ss_device,
1731 struct pci_dev *from)
1734 static inline struct pci_dev *pci_get_class(unsigned int class,
1735 struct pci_dev *from)
1738 #define pci_dev_present(ids) (0)
1739 #define no_pci_devices() (1)
1740 #define pci_dev_put(dev) do { } while (0)
1742 static inline void pci_set_master(struct pci_dev *dev) { }
1743 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1744 static inline void pci_disable_device(struct pci_dev *dev) { }
1745 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1746 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1748 static inline int __pci_register_driver(struct pci_driver *drv,
1749 struct module *owner)
1751 static inline int pci_register_driver(struct pci_driver *drv)
1753 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1754 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1756 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1759 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1762 static inline u64 pci_get_dsn(struct pci_dev *dev)
1765 /* Power management related routines */
1766 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1767 static inline void pci_restore_state(struct pci_dev *dev) { }
1768 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1770 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1772 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1775 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1779 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1780 struct resource *res)
1782 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1784 static inline void pci_release_regions(struct pci_dev *dev) { }
1786 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1787 phys_addr_t addr, resource_size_t size)
1790 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1792 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1794 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1797 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1798 unsigned int bus, unsigned int devfn)
1801 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1802 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1804 #define dev_is_pci(d) (false)
1805 #define dev_is_pf(d) (false)
1806 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1808 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1809 struct device_node *node,
1811 unsigned int intsize,
1812 unsigned long *out_hwirq,
1813 unsigned int *out_type)
1816 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1817 struct pci_dev *dev)
1819 static inline bool pci_ats_disabled(void) { return true; }
1821 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1827 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1828 unsigned int max_vecs, unsigned int flags,
1829 struct irq_affinity *aff_desc)
1833 #endif /* CONFIG_PCI */
1836 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1837 unsigned int max_vecs, unsigned int flags)
1839 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1843 /* Include architecture-dependent settings and functions */
1845 #include <asm/pci.h>
1847 /* These two functions provide almost identical functionality. Depending
1848 * on the architecture, one will be implemented as a wrapper around the
1849 * other (in drivers/pci/mmap.c).
1851 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1852 * is expected to be an offset within that region.
1854 * pci_mmap_page_range() is the legacy architecture-specific interface,
1855 * which accepts a "user visible" resource address converted by
1856 * pci_resource_to_user(), as used in the legacy mmap() interface in
1859 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1860 struct vm_area_struct *vma,
1861 enum pci_mmap_state mmap_state, int write_combine);
1862 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1863 struct vm_area_struct *vma,
1864 enum pci_mmap_state mmap_state, int write_combine);
1866 #ifndef arch_can_pci_mmap_wc
1867 #define arch_can_pci_mmap_wc() 0
1870 #ifndef arch_can_pci_mmap_io
1871 #define arch_can_pci_mmap_io() 0
1872 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1874 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1877 #ifndef pci_root_bus_fwnode
1878 #define pci_root_bus_fwnode(bus) NULL
1882 * These helpers provide future and backwards compatibility
1883 * for accessing popular PCI BAR info
1885 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1886 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1887 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1888 #define pci_resource_len(dev,bar) \
1889 ((pci_resource_start((dev), (bar)) == 0 && \
1890 pci_resource_end((dev), (bar)) == \
1891 pci_resource_start((dev), (bar))) ? 0 : \
1893 (pci_resource_end((dev), (bar)) - \
1894 pci_resource_start((dev), (bar)) + 1))
1897 * Similar to the helpers above, these manipulate per-pci_dev
1898 * driver-specific data. They are really just a wrapper around
1899 * the generic device structure functions of these calls.
1901 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1903 return dev_get_drvdata(&pdev->dev);
1906 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1908 dev_set_drvdata(&pdev->dev, data);
1911 static inline const char *pci_name(const struct pci_dev *pdev)
1913 return dev_name(&pdev->dev);
1916 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1917 const struct resource *rsrc,
1918 resource_size_t *start, resource_size_t *end);
1921 * The world is not perfect and supplies us with broken PCI devices.
1922 * For at least a part of these bugs we need a work-around, so both
1923 * generic (drivers/pci/quirks.c) and per-architecture code can define
1924 * fixup hooks to be called for particular buggy devices.
1928 u16 vendor; /* Or PCI_ANY_ID */
1929 u16 device; /* Or PCI_ANY_ID */
1930 u32 class; /* Or PCI_ANY_ID */
1931 unsigned int class_shift; /* should be 0, 8, 16 */
1932 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1935 void (*hook)(struct pci_dev *dev);
1939 enum pci_fixup_pass {
1940 pci_fixup_early, /* Before probing BARs */
1941 pci_fixup_header, /* After reading configuration header */
1942 pci_fixup_final, /* Final phase of device fixups */
1943 pci_fixup_enable, /* pci_enable_device() time */
1944 pci_fixup_resume, /* pci_device_resume() */
1945 pci_fixup_suspend, /* pci_device_suspend() */
1946 pci_fixup_resume_early, /* pci_device_resume_early() */
1947 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1950 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1951 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1952 class_shift, hook) \
1953 __ADDRESSABLE(hook) \
1954 asm(".section " #sec ", \"a\" \n" \
1956 ".short " #vendor ", " #device " \n" \
1957 ".long " #class ", " #class_shift " \n" \
1958 ".long " #hook " - . \n" \
1962 * Clang's LTO may rename static functions in C, but has no way to
1963 * handle such renamings when referenced from inline asm. To work
1964 * around this, create global C stubs for these cases.
1966 #ifdef CONFIG_LTO_CLANG
1967 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1968 class_shift, hook, stub) \
1969 void __cficanonical stub(struct pci_dev *dev); \
1970 void __cficanonical stub(struct pci_dev *dev) \
1974 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1977 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1978 class_shift, hook, stub) \
1979 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1983 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1984 class_shift, hook) \
1985 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1986 class_shift, hook, __UNIQUE_ID(hook))
1988 /* Anonymous variables would be nice... */
1989 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1990 class_shift, hook) \
1991 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1992 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1993 = { vendor, device, class, class_shift, hook };
1996 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1997 class_shift, hook) \
1998 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1999 hook, vendor, device, class, class_shift, hook)
2000 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2001 class_shift, hook) \
2002 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2003 hook, vendor, device, class, class_shift, hook)
2004 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2005 class_shift, hook) \
2006 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2007 hook, vendor, device, class, class_shift, hook)
2008 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2009 class_shift, hook) \
2010 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2011 hook, vendor, device, class, class_shift, hook)
2012 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2013 class_shift, hook) \
2014 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2015 resume##hook, vendor, device, class, class_shift, hook)
2016 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2017 class_shift, hook) \
2018 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2019 resume_early##hook, vendor, device, class, class_shift, hook)
2020 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2021 class_shift, hook) \
2022 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2023 suspend##hook, vendor, device, class, class_shift, hook)
2024 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2025 class_shift, hook) \
2026 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2027 suspend_late##hook, vendor, device, class, class_shift, hook)
2029 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2030 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2031 hook, vendor, device, PCI_ANY_ID, 0, hook)
2032 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2033 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2034 hook, vendor, device, PCI_ANY_ID, 0, hook)
2035 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2036 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2037 hook, vendor, device, PCI_ANY_ID, 0, hook)
2038 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2039 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2040 hook, vendor, device, PCI_ANY_ID, 0, hook)
2041 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2042 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2043 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2044 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2045 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2046 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2047 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2048 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2049 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2050 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2051 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2052 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2054 #ifdef CONFIG_PCI_QUIRKS
2055 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2057 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2058 struct pci_dev *dev) { }
2061 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2062 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2063 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2064 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2065 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2067 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2069 extern int pci_pci_problems;
2070 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2071 #define PCIPCI_TRITON 2
2072 #define PCIPCI_NATOMA 4
2073 #define PCIPCI_VIAETBF 8
2074 #define PCIPCI_VSFX 16
2075 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2076 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2078 extern unsigned long pci_cardbus_io_size;
2079 extern unsigned long pci_cardbus_mem_size;
2080 extern u8 pci_dfl_cache_line_size;
2081 extern u8 pci_cache_line_size;
2083 /* Architecture-specific versions may override these (weak) */
2084 void pcibios_disable_device(struct pci_dev *dev);
2085 void pcibios_set_master(struct pci_dev *dev);
2086 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2087 enum pcie_reset_state state);
2088 int pcibios_add_device(struct pci_dev *dev);
2089 void pcibios_release_device(struct pci_dev *dev);
2091 void pcibios_penalize_isa_irq(int irq, int active);
2093 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2095 int pcibios_alloc_irq(struct pci_dev *dev);
2096 void pcibios_free_irq(struct pci_dev *dev);
2097 resource_size_t pcibios_default_alignment(void);
2099 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2100 void __init pci_mmcfg_early_init(void);
2101 void __init pci_mmcfg_late_init(void);
2103 static inline void pci_mmcfg_early_init(void) { }
2104 static inline void pci_mmcfg_late_init(void) { }
2107 int pci_ext_cfg_avail(void);
2109 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2110 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2112 #ifdef CONFIG_PCI_IOV
2113 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2114 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2116 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2117 void pci_disable_sriov(struct pci_dev *dev);
2119 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2120 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2121 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2122 int pci_num_vf(struct pci_dev *dev);
2123 int pci_vfs_assigned(struct pci_dev *dev);
2124 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2125 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2126 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2127 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2128 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2130 /* Arch may override these (weak) */
2131 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2132 int pcibios_sriov_disable(struct pci_dev *pdev);
2133 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2135 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2139 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2143 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2146 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2147 struct pci_dev *virtfn, int id)
2151 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2155 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2157 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2158 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2159 static inline int pci_vfs_assigned(struct pci_dev *dev)
2161 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2163 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2165 #define pci_sriov_configure_simple NULL
2166 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2168 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2171 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2172 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2173 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2177 * pci_pcie_cap - get the saved PCIe capability offset
2180 * PCIe capability offset is calculated at PCI device initialization
2181 * time and saved in the data structure. This function returns saved
2182 * PCIe capability offset. Using this instead of pci_find_capability()
2183 * reduces unnecessary search in the PCI configuration space. If you
2184 * need to calculate PCIe capability offset from raw device for some
2185 * reasons, please use pci_find_capability() instead.
2187 static inline int pci_pcie_cap(struct pci_dev *dev)
2189 return dev->pcie_cap;
2193 * pci_is_pcie - check if the PCI device is PCI Express capable
2196 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2198 static inline bool pci_is_pcie(struct pci_dev *dev)
2200 return pci_pcie_cap(dev);
2204 * pcie_caps_reg - get the PCIe Capabilities Register
2207 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2209 return dev->pcie_flags_reg;
2213 * pci_pcie_type - get the PCIe device/port type
2216 static inline int pci_pcie_type(const struct pci_dev *dev)
2218 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2222 * pcie_find_root_port - Get the PCIe root port device
2225 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2226 * for a given PCI/PCIe Device.
2228 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2231 if (pci_is_pcie(dev) &&
2232 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2234 dev = pci_upstream_bridge(dev);
2240 void pci_request_acs(void);
2241 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2242 bool pci_acs_path_enabled(struct pci_dev *start,
2243 struct pci_dev *end, u16 acs_flags);
2244 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2246 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2247 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2249 /* Large Resource Data Type Tag Item Names */
2250 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2251 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2252 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2254 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2255 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2256 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2258 /* Small Resource Data Type Tag Item Names */
2259 #define PCI_VPD_STIN_END 0x0f /* End */
2261 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2263 #define PCI_VPD_SRDT_TIN_MASK 0x78
2264 #define PCI_VPD_SRDT_LEN_MASK 0x07
2265 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2267 #define PCI_VPD_LRDT_TAG_SIZE 3
2268 #define PCI_VPD_SRDT_TAG_SIZE 1
2270 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2272 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2273 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2274 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2275 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2276 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2279 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2280 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2282 * Returns the extracted Large Resource Data Type length.
2284 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2286 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2290 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2291 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2293 * Returns the extracted Large Resource Data Type Tag item.
2295 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2297 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2301 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2302 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2304 * Returns the extracted Small Resource Data Type length.
2306 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2308 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2312 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2313 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2315 * Returns the extracted Small Resource Data Type Tag Item.
2317 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2319 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2323 * pci_vpd_info_field_size - Extracts the information field length
2324 * @info_field: Pointer to the beginning of an information field header
2326 * Returns the extracted information field length.
2328 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2330 return info_field[2];
2334 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2335 * @buf: Pointer to buffered vpd data
2336 * @len: The length of the vpd buffer
2337 * @rdt: The Resource Data Type to search for
2339 * Returns the index where the Resource Data Type was found or
2340 * -ENOENT otherwise.
2342 int pci_vpd_find_tag(const u8 *buf, unsigned int len, u8 rdt);
2345 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2346 * @buf: Pointer to buffered vpd data
2347 * @off: The offset into the buffer at which to begin the search
2348 * @len: The length of the buffer area, relative to off, in which to search
2349 * @kw: The keyword to search for
2351 * Returns the index where the information field keyword was found or
2352 * -ENOENT otherwise.
2354 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2355 unsigned int len, const char *kw);
2357 /* PCI <-> OF binding helpers */
2361 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2362 bool pci_host_of_has_msi_map(struct device *dev);
2364 /* Arch may override this (weak) */
2365 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2367 #else /* CONFIG_OF */
2368 static inline struct irq_domain *
2369 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2370 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2371 #endif /* CONFIG_OF */
2373 static inline struct device_node *
2374 pci_device_to_OF_node(const struct pci_dev *pdev)
2376 return pdev ? pdev->dev.of_node : NULL;
2379 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2381 return bus ? bus->dev.of_node : NULL;
2385 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2388 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2389 bool pci_pr3_present(struct pci_dev *pdev);
2391 static inline struct irq_domain *
2392 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2393 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2397 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2399 return pdev->dev.archdata.edev;
2403 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2404 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2405 int pci_for_each_dma_alias(struct pci_dev *pdev,
2406 int (*fn)(struct pci_dev *pdev,
2407 u16 alias, void *data), void *data);
2409 /* Helper functions for operation of device flag */
2410 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2412 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2414 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2416 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2418 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2420 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2424 * pci_ari_enabled - query ARI forwarding status
2427 * Returns true if ARI forwarding is enabled.
2429 static inline bool pci_ari_enabled(struct pci_bus *bus)
2431 return bus->self && bus->self->ari_enabled;
2435 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2436 * @pdev: PCI device to check
2438 * Walk upwards from @pdev and check for each encountered bridge if it's part
2439 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2440 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2442 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2444 struct pci_dev *parent = pdev;
2446 if (pdev->is_thunderbolt)
2449 while ((parent = pci_upstream_bridge(parent)))
2450 if (parent->is_thunderbolt)
2456 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2457 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2460 /* Provide the legacy pci_dma_* API */
2461 #include <linux/pci-dma-compat.h>
2463 #define pci_printk(level, pdev, fmt, arg...) \
2464 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2466 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2467 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2468 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2469 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2470 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2471 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2472 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2473 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2475 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2476 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2478 #define pci_info_ratelimited(pdev, fmt, arg...) \
2479 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2481 #define pci_WARN(pdev, condition, fmt, arg...) \
2482 WARN(condition, "%s %s: " fmt, \
2483 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2485 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2486 WARN_ONCE(condition, "%s %s: " fmt, \
2487 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2489 #endif /* LINUX_PCI_H */