1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <linux/msi_api.h>
42 #include <uapi/linux/pci.h>
44 #include <linux/pci_ids.h>
46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
54 #define PCI_NUM_RESET_METHODS 7
56 #define PCI_RESET_PROBE true
57 #define PCI_RESET_DO_RESET false
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
75 /* pci_slot represents a physical slot */
77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
84 static inline const char *pci_slot_name(const struct pci_slot *slot)
86 return kobject_name(&slot->kobj);
89 /* File state for mmap()s on /proc/bus/pci/X/Y */
95 /* For PCI devices, the region numbers are assigned this way: */
97 /* #0-5: standard PCI resources */
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
101 /* #6: expansion ROM resource */
104 /* Device-specific resources */
105 #ifdef CONFIG_PCI_IOV
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
110 /* PCI-to-PCI (P2P) bridge windows */
111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
115 /* CardBus bridge windows */
116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
121 /* Total number of bridge resources for P2P and CardBus */
122 #define PCI_BRIDGE_RESOURCE_NUM 4
124 /* Resources assigned to buses behind the bridge */
125 PCI_BRIDGE_RESOURCES,
126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 PCI_BRIDGE_RESOURCE_NUM - 1,
129 /* Total resources associated with a PCI device */
132 /* Preserve this for compatibility */
133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
137 * enum pci_interrupt_pin - PCI INTx interrupt values
138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 * @PCI_INTERRUPT_INTA: PCI INTA pin
140 * @PCI_INTERRUPT_INTB: PCI INTB pin
141 * @PCI_INTERRUPT_INTC: PCI INTC pin
142 * @PCI_INTERRUPT_INTD: PCI INTD pin
144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 * PCI_INTERRUPT_PIN register.
147 enum pci_interrupt_pin {
148 PCI_INTERRUPT_UNKNOWN,
155 /* The number of legacy PCI INTx interrupts */
156 #define PCI_NUM_INTX 4
159 * Reading from a device that doesn't respond typically returns ~0. A
160 * successful read from a device may also return ~0, so you need additional
161 * information to reliably identify errors.
163 #define PCI_ERROR_RESPONSE (~0ULL)
164 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
165 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
168 * pci_power_t values must match the bits in the Capabilities PME_Support
169 * and Control/Status PowerState fields in the Power Management capability.
171 typedef int __bitwise pci_power_t;
173 #define PCI_D0 ((pci_power_t __force) 0)
174 #define PCI_D1 ((pci_power_t __force) 1)
175 #define PCI_D2 ((pci_power_t __force) 2)
176 #define PCI_D3hot ((pci_power_t __force) 3)
177 #define PCI_D3cold ((pci_power_t __force) 4)
178 #define PCI_UNKNOWN ((pci_power_t __force) 5)
179 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
181 /* Remember to update this when the list above changes! */
182 extern const char *pci_power_names[];
184 static inline const char *pci_power_name(pci_power_t state)
186 return pci_power_names[1 + (__force int) state];
190 * typedef pci_channel_state_t
192 * The pci_channel state describes connectivity between the CPU and
193 * the PCI device. If some PCI bus between here and the PCI device
194 * has crashed or locked up, this info is reflected here.
196 typedef unsigned int __bitwise pci_channel_state_t;
199 /* I/O channel is in normal state */
200 pci_channel_io_normal = (__force pci_channel_state_t) 1,
202 /* I/O to channel is blocked */
203 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
205 /* PCI card is dead */
206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
209 typedef unsigned int __bitwise pcie_reset_state_t;
211 enum pcie_reset_state {
212 /* Reset is NOT asserted (Use to deassert reset) */
213 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
215 /* Use #PERST to reset PCIe device */
216 pcie_warm_reset = (__force pcie_reset_state_t) 2,
218 /* Use PCIe Hot Reset to reset device */
219 pcie_hot_reset = (__force pcie_reset_state_t) 3
222 typedef unsigned short __bitwise pci_dev_flags_t;
224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
226 /* Device configuration is irrevocably lost if disabled into D3 */
227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
228 /* Provide indication device is assigned by a Virtual Machine Manager */
229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
230 /* Flag for quirk use to store if quirk-specific ACS is enabled */
231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
234 /* Do not use bus resets for device */
235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
236 /* Do not use PM reset even if device advertises NoSoftRst- */
237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
238 /* Get VPD from function 0 VPD */
239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
240 /* A non-root bridge where translation occurs, stop alias search here */
241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
242 /* Do not use FLR even if device advertises PCI_AF_CAP */
243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
244 /* Don't use Relaxed Ordering for TLPs directed at this device */
245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
246 /* Device does honor MSI masking despite saying otherwise */
247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
250 enum pci_irq_reroute_variant {
251 INTEL_IRQ_REROUTE_VARIANT = 1,
252 MAX_IRQ_REROUTE_VARIANTS = 3
255 typedef unsigned short __bitwise pci_bus_flags_t;
257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
263 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
264 enum pcie_link_width {
265 PCIE_LNK_WIDTH_RESRV = 0x00,
273 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
276 /* See matching string table in pci_speed_string() */
278 PCI_SPEED_33MHz = 0x00,
279 PCI_SPEED_66MHz = 0x01,
280 PCI_SPEED_66MHz_PCIX = 0x02,
281 PCI_SPEED_100MHz_PCIX = 0x03,
282 PCI_SPEED_133MHz_PCIX = 0x04,
283 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
284 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
285 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
286 PCI_SPEED_66MHz_PCIX_266 = 0x09,
287 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
288 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
294 PCI_SPEED_66MHz_PCIX_533 = 0x11,
295 PCI_SPEED_100MHz_PCIX_533 = 0x12,
296 PCI_SPEED_133MHz_PCIX_533 = 0x13,
297 PCIE_SPEED_2_5GT = 0x14,
298 PCIE_SPEED_5_0GT = 0x15,
299 PCIE_SPEED_8_0GT = 0x16,
300 PCIE_SPEED_16_0GT = 0x17,
301 PCIE_SPEED_32_0GT = 0x18,
302 PCIE_SPEED_64_0GT = 0x19,
303 PCI_SPEED_UNKNOWN = 0xff,
306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
307 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
316 struct pcie_link_state;
321 /* The pci_dev structure describes PCI devices */
323 struct list_head bus_list; /* Node in per-bus list */
324 struct pci_bus *bus; /* Bus this device is on */
325 struct pci_bus *subordinate; /* Bus this device bridges to */
327 void *sysdata; /* Hook for sys-specific extension */
328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
329 struct pci_slot *slot; /* Physical slot this device is in */
331 unsigned int devfn; /* Encoded device & function index */
332 unsigned short vendor;
333 unsigned short device;
334 unsigned short subsystem_vendor;
335 unsigned short subsystem_device;
336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
337 u8 revision; /* PCI revision, low byte of class word */
338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
339 #ifdef CONFIG_PCIEAER
340 u16 aer_cap; /* AER capability offset */
341 struct aer_stats *aer_stats; /* AER stats for this device */
343 #ifdef CONFIG_PCIEPORTBUS
344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
345 struct pci_dev *rcec; /* Associated RCEC device */
347 u32 devcap; /* PCIe Device Capabilities */
348 u8 pcie_cap; /* PCIe capability offset */
349 u8 msi_cap; /* MSI capability offset */
350 u8 msix_cap; /* MSI-X capability offset */
351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
352 u8 rom_base_reg; /* Config register controlling ROM */
353 u8 pin; /* Interrupt pin this device uses */
354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
357 struct pci_driver *driver; /* Driver bound to this device */
358 u64 dma_mask; /* Mask of the bits of bus address this
359 device implements. Normally this is
360 0xffffffff. You only need to change
361 this if your device has broken DMA
362 or supports 64-bit transfers. */
364 struct device_dma_parameters dma_parms;
366 pci_power_t current_state; /* Current operating state. In ACPI,
367 this is D0-D3, D0 being fully
368 functional, and D3 being off. */
369 unsigned int imm_ready:1; /* Supports Immediate Readiness */
370 u8 pm_cap; /* PM capability offset */
371 unsigned int pme_support:5; /* Bitmask of states from which PME#
373 unsigned int pme_poll:1; /* Poll device's PME status bit */
374 unsigned int d1_support:1; /* Low power state D1 is supported */
375 unsigned int d2_support:1; /* Low power state D2 is supported */
376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
377 unsigned int no_d3cold:1; /* D3cold is forbidden */
378 unsigned int bridge_d3:1; /* Allow D3 for bridge */
379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
381 decoding during BAR sizing */
382 unsigned int wakeup_prepared:1;
383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
386 controlled exclusively by
388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
393 #ifdef CONFIG_PCIEASPM
394 struct pcie_link_state *link_state; /* ASPM link state */
395 unsigned int ltr_path:1; /* Latency Tolerance Reporting
396 supported from root to here */
397 u16 l1ss; /* L1SS Capability pointer */
399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
402 pci_channel_state_t error_state; /* Current connectivity state */
403 struct device dev; /* Generic device interface */
405 int cfg_size; /* Size of config space */
408 * Instead of touching interrupt line and base address registers
409 * directly, use the values stored here. They might be different!
412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
413 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */
415 bool match_driver; /* Skip attaching driver */
417 unsigned int transparent:1; /* Subtractive decode bridge */
418 unsigned int io_window:1; /* Bridge has I/O window */
419 unsigned int pref_window:1; /* Bridge has pref mem window */
420 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
421 unsigned int multifunction:1; /* Multi-function device */
423 unsigned int is_busmaster:1; /* Is busmaster */
424 unsigned int no_msi:1; /* May not use MSI */
425 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
426 unsigned int block_cfg_access:1; /* Config space access blocked */
427 unsigned int broken_parity_status:1; /* Generates false positive parity */
428 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
429 unsigned int msi_enabled:1;
430 unsigned int msix_enabled:1;
431 unsigned int ari_enabled:1; /* ARI forwarding */
432 unsigned int ats_enabled:1; /* Address Translation Svc */
433 unsigned int pasid_enabled:1; /* Process Address Space ID */
434 unsigned int pri_enabled:1; /* Page Request Interface */
435 unsigned int is_managed:1; /* Managed via devres */
436 unsigned int is_msi_managed:1; /* MSI release via devres installed */
437 unsigned int needs_freset:1; /* Requires fundamental reset */
438 unsigned int state_saved:1;
439 unsigned int is_physfn:1;
440 unsigned int is_virtfn:1;
441 unsigned int is_hotplug_bridge:1;
442 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
443 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
445 * Devices marked being untrusted are the ones that can potentially
446 * execute DMA attacks and similar. They are typically connected
447 * through external ports such as Thunderbolt but not limited to
448 * that. When an IOMMU is enabled they should be getting full
449 * mappings to make sure they cannot access arbitrary memory.
451 unsigned int untrusted:1;
453 * Info from the platform, e.g., ACPI or device tree, may mark a
454 * device as "external-facing". An external-facing device is
455 * itself internal but devices downstream from it are external.
457 unsigned int external_facing:1;
458 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
459 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
460 unsigned int irq_managed:1;
461 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
462 unsigned int is_probed:1; /* Device probing in progress */
463 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
464 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
465 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
466 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
467 pci_dev_flags_t dev_flags;
468 atomic_t enable_cnt; /* pci_enable_device has been called */
470 u32 saved_config_space[16]; /* Config space saved at suspend time */
471 struct hlist_head saved_cap_space;
472 int rom_attr_enabled; /* Display of ROM attribute enabled? */
473 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
474 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
476 #ifdef CONFIG_HOTPLUG_PCI_PCIE
477 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
479 #ifdef CONFIG_PCIE_PTM
480 u16 ptm_cap; /* PTM Capability */
481 unsigned int ptm_root:1;
482 unsigned int ptm_enabled:1;
485 #ifdef CONFIG_PCI_MSI
486 void __iomem *msix_base;
487 raw_spinlock_t msi_lock;
490 #ifdef CONFIG_PCIE_DPC
492 unsigned int dpc_rp_extensions:1;
495 #ifdef CONFIG_PCI_ATS
497 struct pci_sriov *sriov; /* PF: SR-IOV info */
498 struct pci_dev *physfn; /* VF: related PF */
500 u16 ats_cap; /* ATS Capability offset */
501 u8 ats_stu; /* ATS Smallest Translation Unit */
503 #ifdef CONFIG_PCI_PRI
504 u16 pri_cap; /* PRI Capability offset */
505 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
506 unsigned int pasid_required:1; /* PRG Response PASID Required */
508 #ifdef CONFIG_PCI_PASID
509 u16 pasid_cap; /* PASID Capability offset */
512 #ifdef CONFIG_PCI_P2PDMA
513 struct pci_p2pdma __rcu *p2pdma;
515 u16 acs_cap; /* ACS Capability offset */
516 phys_addr_t rom; /* Physical address if not from BAR */
517 size_t romlen; /* Length if not from BAR */
519 * Driver name to force a match. Do not set directly, because core
520 * frees it. Use driver_set_override() to set or clear it.
522 const char *driver_override;
524 unsigned long priv_flags; /* Private flags for the PCI driver */
526 /* These methods index pci_reset_fn_methods[] */
527 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
530 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
532 #ifdef CONFIG_PCI_IOV
539 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
541 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
542 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
544 static inline int pci_channel_offline(struct pci_dev *pdev)
546 return (pdev->error_state != pci_channel_io_normal);
550 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
551 * Group number is limited to a 16-bit value, therefore (int)-1 is
552 * not a valid PCI domain number, and can be used as a sentinel
553 * value indicating ->domain_nr is not set by the driver (and
554 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
555 * pci_bus_find_domain_nr()).
557 #define PCI_DOMAIN_NR_NOT_SET (-1)
559 struct pci_host_bridge {
561 struct pci_bus *bus; /* Root bus */
563 struct pci_ops *child_ops;
567 struct list_head windows; /* resource_entry */
568 struct list_head dma_ranges; /* dma ranges resource list */
569 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
570 int (*map_irq)(const struct pci_dev *, u8, u8);
571 void (*release_fn)(struct pci_host_bridge *);
573 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
574 unsigned int no_ext_tags:1; /* No Extended Tags */
575 unsigned int no_inc_mrrs:1; /* No Increase MRRS */
576 unsigned int native_aer:1; /* OS may use PCIe AER */
577 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
578 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
579 unsigned int native_pme:1; /* OS may use PCIe PME */
580 unsigned int native_ltr:1; /* OS may use PCIe LTR */
581 unsigned int native_dpc:1; /* OS may use PCIe DPC */
582 unsigned int preserve_config:1; /* Preserve FW resource setup */
583 unsigned int size_windows:1; /* Enable root bus sizing */
584 unsigned int msi_domain:1; /* Bridge wants MSI domain */
586 /* Resource alignment requirements */
587 resource_size_t (*align_resource)(struct pci_dev *dev,
588 const struct resource *res,
589 resource_size_t start,
590 resource_size_t size,
591 resource_size_t align);
592 unsigned long private[] ____cacheline_aligned;
595 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
597 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
599 return (void *)bridge->private;
602 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
604 return container_of(priv, struct pci_host_bridge, private);
607 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
608 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
610 void pci_free_host_bridge(struct pci_host_bridge *bridge);
611 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
613 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
614 void (*release_fn)(struct pci_host_bridge *),
617 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
620 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
621 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
622 * buses below host bridges or subtractive decode bridges) go in the list.
623 * Use pci_bus_for_each_resource() to iterate through all the resources.
627 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
628 * and there's no way to program the bridge with the details of the window.
629 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
630 * decode bit set, because they are explicit and can be programmed with _SRS.
632 #define PCI_SUBTRACTIVE_DECODE 0x1
634 struct pci_bus_resource {
635 struct list_head list;
636 struct resource *res;
640 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
643 struct list_head node; /* Node in list of buses */
644 struct pci_bus *parent; /* Parent bus this bridge is on */
645 struct list_head children; /* List of child buses */
646 struct list_head devices; /* List of devices on this bus */
647 struct pci_dev *self; /* Bridge device as seen by parent */
648 struct list_head slots; /* List of slots on this bus;
649 protected by pci_slot_mutex */
650 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
651 struct list_head resources; /* Address space routed to this bus */
652 struct resource busn_res; /* Bus numbers routed to this bus */
654 struct pci_ops *ops; /* Configuration access functions */
655 void *sysdata; /* Hook for sys-specific extension */
656 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
658 unsigned char number; /* Bus number */
659 unsigned char primary; /* Number of primary bridge */
660 unsigned char max_bus_speed; /* enum pci_bus_speed */
661 unsigned char cur_bus_speed; /* enum pci_bus_speed */
662 #ifdef CONFIG_PCI_DOMAINS_GENERIC
668 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
669 pci_bus_flags_t bus_flags; /* Inherited by child buses */
670 struct device *bridge;
672 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
673 struct bin_attribute *legacy_mem; /* Legacy mem */
674 unsigned int is_added:1;
675 unsigned int unsafe_warn:1; /* warned about RW1C config write */
678 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
680 static inline u16 pci_dev_id(struct pci_dev *dev)
682 return PCI_DEVID(dev->bus->number, dev->devfn);
686 * Returns true if the PCI bus is root (behind host-PCI bridge),
689 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
690 * This is incorrect because "virtual" buses added for SR-IOV (via
691 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
693 static inline bool pci_is_root_bus(struct pci_bus *pbus)
695 return !(pbus->parent);
699 * pci_is_bridge - check if the PCI device is a bridge
702 * Return true if the PCI device is bridge whether it has subordinate
705 static inline bool pci_is_bridge(struct pci_dev *dev)
707 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
708 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
711 #define for_each_pci_bridge(dev, bus) \
712 list_for_each_entry(dev, &bus->devices, bus_list) \
713 if (!pci_is_bridge(dev)) {} else
715 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
717 dev = pci_physfn(dev);
718 if (pci_is_root_bus(dev->bus))
721 return dev->bus->self;
724 #ifdef CONFIG_PCI_MSI
725 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
727 return pci_dev->msi_enabled || pci_dev->msix_enabled;
730 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
733 /* Error values that may be returned by PCI functions */
734 #define PCIBIOS_SUCCESSFUL 0x00
735 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
736 #define PCIBIOS_BAD_VENDOR_ID 0x83
737 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
738 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
739 #define PCIBIOS_SET_FAILED 0x88
740 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
742 /* Translate above to generic errno for passing back through non-PCI code */
743 static inline int pcibios_err_to_errno(int err)
745 if (err <= PCIBIOS_SUCCESSFUL)
746 return err; /* Assume already errno */
749 case PCIBIOS_FUNC_NOT_SUPPORTED:
751 case PCIBIOS_BAD_VENDOR_ID:
753 case PCIBIOS_DEVICE_NOT_FOUND:
755 case PCIBIOS_BAD_REGISTER_NUMBER:
757 case PCIBIOS_SET_FAILED:
759 case PCIBIOS_BUFFER_TOO_SMALL:
766 /* Low-level architecture-dependent routines */
769 int (*add_bus)(struct pci_bus *bus);
770 void (*remove_bus)(struct pci_bus *bus);
771 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
772 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
773 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
777 * ACPI needs to be able to access PCI config space before we've done a
778 * PCI bus scan and created pci_bus structures.
780 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
781 int reg, int len, u32 *val);
782 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
783 int reg, int len, u32 val);
785 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
786 typedef u64 pci_bus_addr_t;
788 typedef u32 pci_bus_addr_t;
791 struct pci_bus_region {
792 pci_bus_addr_t start;
797 spinlock_t lock; /* Protects list, index */
798 struct list_head list; /* For IDs added at runtime */
803 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
804 * a set of callbacks in struct pci_error_handlers, that device driver
805 * will be notified of PCI bus errors, and will be driven to recovery
806 * when an error occurs.
809 typedef unsigned int __bitwise pci_ers_result_t;
811 enum pci_ers_result {
812 /* No result/none/not supported in device driver */
813 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
815 /* Device driver can recover without slot reset */
816 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
818 /* Device driver wants slot to be reset */
819 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
821 /* Device has completely failed, is unrecoverable */
822 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
824 /* Device driver is fully recovered and operational */
825 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
827 /* No AER capabilities registered for the driver */
828 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
831 /* PCI bus error event callbacks */
832 struct pci_error_handlers {
833 /* PCI bus error detected on this device */
834 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
835 pci_channel_state_t error);
837 /* MMIO has been re-enabled, but not DMA */
838 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
840 /* PCI slot has been reset */
841 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
843 /* PCI function reset prepare or completed */
844 void (*reset_prepare)(struct pci_dev *dev);
845 void (*reset_done)(struct pci_dev *dev);
847 /* Device driver may resume normal operations */
848 void (*resume)(struct pci_dev *dev);
850 /* Allow device driver to record more details of a correctable error */
851 void (*cor_error_detected)(struct pci_dev *dev);
858 * struct pci_driver - PCI driver structure
859 * @node: List of driver structures.
860 * @name: Driver name.
861 * @id_table: Pointer to table of device IDs the driver is
862 * interested in. Most drivers should export this
863 * table using MODULE_DEVICE_TABLE(pci,...).
864 * @probe: This probing function gets called (during execution
865 * of pci_register_driver() for already existing
866 * devices or later if a new device gets inserted) for
867 * all PCI devices which match the ID table and are not
868 * "owned" by the other drivers yet. This function gets
869 * passed a "struct pci_dev \*" for each device whose
870 * entry in the ID table matches the device. The probe
871 * function returns zero when the driver chooses to
872 * take "ownership" of the device or an error code
873 * (negative number) otherwise.
874 * The probe function always gets called from process
875 * context, so it can sleep.
876 * @remove: The remove() function gets called whenever a device
877 * being handled by this driver is removed (either during
878 * deregistration of the driver or when it's manually
879 * pulled out of a hot-pluggable slot).
880 * The remove function always gets called from process
881 * context, so it can sleep.
882 * @suspend: Put device into low power state.
883 * @resume: Wake device from low power state.
884 * (Please see Documentation/power/pci.rst for descriptions
885 * of PCI Power Management and the related functions.)
886 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
887 * Intended to stop any idling DMA operations.
888 * Useful for enabling wake-on-lan (NIC) or changing
889 * the power state of a device before reboot.
890 * e.g. drivers/net/e100.c.
891 * @sriov_configure: Optional driver callback to allow configuration of
892 * number of VFs to enable via sysfs "sriov_numvfs" file.
893 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
894 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
895 * This will change MSI-X Table Size in the VF Message Control
897 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
898 * MSI-X vectors available for distribution to the VFs.
899 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
900 * @groups: Sysfs attribute groups.
901 * @dev_groups: Attributes attached to the device that will be
902 * created once it is bound to the driver.
903 * @driver: Driver model structure.
904 * @dynids: List of dynamically added device IDs.
905 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
906 * For most device drivers, no need to care about this flag
907 * as long as all DMAs are handled through the kernel DMA API.
908 * For some special ones, for example VFIO drivers, they know
909 * how to manage the DMA themselves and set this flag so that
910 * the IOMMU layer will allow them to setup and manage their
911 * own I/O address space.
914 struct list_head node;
916 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
917 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
918 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
919 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
920 int (*resume)(struct pci_dev *dev); /* Device woken up */
921 void (*shutdown)(struct pci_dev *dev);
922 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
923 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
924 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
925 const struct pci_error_handlers *err_handler;
926 const struct attribute_group **groups;
927 const struct attribute_group **dev_groups;
928 struct device_driver driver;
929 struct pci_dynids dynids;
930 bool driver_managed_dma;
933 static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
935 return drv ? container_of(drv, struct pci_driver, driver) : NULL;
939 * PCI_DEVICE - macro used to describe a specific PCI device
940 * @vend: the 16 bit PCI Vendor ID
941 * @dev: the 16 bit PCI Device ID
943 * This macro is used to create a struct pci_device_id that matches a
944 * specific device. The subvendor and subdevice fields will be set to
947 #define PCI_DEVICE(vend,dev) \
948 .vendor = (vend), .device = (dev), \
949 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
952 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
953 * override_only flags.
954 * @vend: the 16 bit PCI Vendor ID
955 * @dev: the 16 bit PCI Device ID
956 * @driver_override: the 32 bit PCI Device override_only
958 * This macro is used to create a struct pci_device_id that matches only a
959 * driver_override device. The subvendor and subdevice fields will be set to
962 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
963 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
964 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
967 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
968 * "driver_override" PCI device.
969 * @vend: the 16 bit PCI Vendor ID
970 * @dev: the 16 bit PCI Device ID
972 * This macro is used to create a struct pci_device_id that matches a
973 * specific device. The subvendor and subdevice fields will be set to
974 * PCI_ANY_ID and the driver_override will be set to
975 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
977 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
978 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
981 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
982 * @vend: the 16 bit PCI Vendor ID
983 * @dev: the 16 bit PCI Device ID
984 * @subvend: the 16 bit PCI Subvendor ID
985 * @subdev: the 16 bit PCI Subdevice ID
987 * This macro is used to create a struct pci_device_id that matches a
988 * specific device with subsystem information.
990 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
991 .vendor = (vend), .device = (dev), \
992 .subvendor = (subvend), .subdevice = (subdev)
995 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
996 * @dev_class: the class, subclass, prog-if triple for this device
997 * @dev_class_mask: the class mask for this device
999 * This macro is used to create a struct pci_device_id that matches a
1000 * specific PCI class. The vendor, device, subvendor, and subdevice
1001 * fields will be set to PCI_ANY_ID.
1003 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
1004 .class = (dev_class), .class_mask = (dev_class_mask), \
1005 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1006 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1009 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1010 * @vend: the vendor name
1011 * @dev: the 16 bit PCI Device ID
1013 * This macro is used to create a struct pci_device_id that matches a
1014 * specific PCI device. The subvendor, and subdevice fields will be set
1015 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1018 #define PCI_VDEVICE(vend, dev) \
1019 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1020 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1023 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1024 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1025 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1026 * @data: the driver data to be filled
1028 * This macro is used to create a struct pci_device_id that matches a
1029 * specific PCI device. The subvendor, and subdevice fields will be set
1032 #define PCI_DEVICE_DATA(vend, dev, data) \
1033 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1034 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1035 .driver_data = (kernel_ulong_t)(data)
1038 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1039 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1040 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1041 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1042 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1043 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1044 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1047 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1048 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1049 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1050 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1052 /* These external functions are only available when PCI support is enabled */
1055 extern unsigned int pci_flags;
1057 static inline void pci_set_flags(int flags) { pci_flags = flags; }
1058 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1059 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1060 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1062 void pcie_bus_configure_settings(struct pci_bus *bus);
1064 enum pcie_bus_config_types {
1065 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1066 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1067 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1068 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1069 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1072 extern enum pcie_bus_config_types pcie_bus_config;
1074 extern struct bus_type pci_bus_type;
1076 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1077 * code, or PCI core code. */
1078 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1079 /* Some device drivers need know if PCI is initiated */
1080 int no_pci_devices(void);
1082 void pcibios_resource_survey_bus(struct pci_bus *bus);
1083 void pcibios_bus_add_device(struct pci_dev *pdev);
1084 void pcibios_add_bus(struct pci_bus *bus);
1085 void pcibios_remove_bus(struct pci_bus *bus);
1086 void pcibios_fixup_bus(struct pci_bus *);
1087 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1088 /* Architecture-specific versions may override this (weak) */
1089 char *pcibios_setup(char *str);
1091 /* Used only when drivers/pci/setup.c is used */
1092 resource_size_t pcibios_align_resource(void *, const struct resource *,
1096 /* Weak but can be overridden by arch */
1097 void pci_fixup_cardbus(struct pci_bus *);
1099 /* Generic PCI functions used internally */
1101 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1102 struct resource *res);
1103 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1104 struct pci_bus_region *region);
1105 void pcibios_scan_specific_bus(int busn);
1106 struct pci_bus *pci_find_bus(int domain, int busnr);
1107 void pci_bus_add_devices(const struct pci_bus *bus);
1108 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1109 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1110 struct pci_ops *ops, void *sysdata,
1111 struct list_head *resources);
1112 int pci_host_probe(struct pci_host_bridge *bridge);
1113 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1114 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1115 void pci_bus_release_busn_res(struct pci_bus *b);
1116 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1117 struct pci_ops *ops, void *sysdata,
1118 struct list_head *resources);
1119 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1120 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1122 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1124 struct hotplug_slot *hotplug);
1125 void pci_destroy_slot(struct pci_slot *slot);
1127 void pci_dev_assign_slot(struct pci_dev *dev);
1129 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1131 int pci_scan_slot(struct pci_bus *bus, int devfn);
1132 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1133 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1134 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1135 void pci_bus_add_device(struct pci_dev *dev);
1136 void pci_read_bridge_bases(struct pci_bus *child);
1137 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1138 struct resource *res);
1139 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1140 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1141 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1142 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1143 void pci_dev_put(struct pci_dev *dev);
1144 void pci_remove_bus(struct pci_bus *b);
1145 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1146 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1147 void pci_stop_root_bus(struct pci_bus *bus);
1148 void pci_remove_root_bus(struct pci_bus *bus);
1149 void pci_setup_cardbus(struct pci_bus *bus);
1150 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1151 void pci_sort_breadthfirst(void);
1152 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1153 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1155 /* Generic PCI functions exported to card drivers */
1157 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1158 u8 pci_find_capability(struct pci_dev *dev, int cap);
1159 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1160 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1161 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1162 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1163 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1164 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1165 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1166 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1168 u64 pci_get_dsn(struct pci_dev *dev);
1170 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1171 struct pci_dev *from);
1172 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1173 unsigned int ss_vendor, unsigned int ss_device,
1174 struct pci_dev *from);
1175 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1176 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1177 unsigned int devfn);
1178 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1179 int pci_dev_present(const struct pci_device_id *ids);
1181 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1182 int where, u8 *val);
1183 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1184 int where, u16 *val);
1185 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1186 int where, u32 *val);
1187 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1189 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1190 int where, u16 val);
1191 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1192 int where, u32 val);
1194 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1195 int where, int size, u32 *val);
1196 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1197 int where, int size, u32 val);
1198 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1199 int where, int size, u32 *val);
1200 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1201 int where, int size, u32 val);
1203 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1205 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1206 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1207 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1208 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1209 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1210 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1212 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1213 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1214 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1215 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1216 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1217 u16 clear, u16 set);
1218 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1219 u32 clear, u32 set);
1221 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1224 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1227 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1230 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1233 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1236 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1239 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1242 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1245 /* User-space driven config access */
1246 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1247 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1248 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1249 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1250 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1251 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1253 int __must_check pci_enable_device(struct pci_dev *dev);
1254 int __must_check pci_enable_device_io(struct pci_dev *dev);
1255 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1256 int __must_check pci_reenable_device(struct pci_dev *);
1257 int __must_check pcim_enable_device(struct pci_dev *pdev);
1258 void pcim_pin_device(struct pci_dev *pdev);
1260 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1263 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1264 * writable and no quirk has marked the feature broken.
1266 return !pdev->broken_intx_masking;
1269 static inline int pci_is_enabled(struct pci_dev *pdev)
1271 return (atomic_read(&pdev->enable_cnt) > 0);
1274 static inline int pci_is_managed(struct pci_dev *pdev)
1276 return pdev->is_managed;
1279 void pci_disable_device(struct pci_dev *dev);
1281 extern unsigned int pcibios_max_latency;
1282 void pci_set_master(struct pci_dev *dev);
1283 void pci_clear_master(struct pci_dev *dev);
1285 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1286 int pci_set_cacheline_size(struct pci_dev *dev);
1287 int __must_check pci_set_mwi(struct pci_dev *dev);
1288 int __must_check pcim_set_mwi(struct pci_dev *dev);
1289 int pci_try_set_mwi(struct pci_dev *dev);
1290 void pci_clear_mwi(struct pci_dev *dev);
1291 void pci_disable_parity(struct pci_dev *dev);
1292 void pci_intx(struct pci_dev *dev, int enable);
1293 bool pci_check_and_mask_intx(struct pci_dev *dev);
1294 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1295 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1296 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1297 int pcix_get_max_mmrbc(struct pci_dev *dev);
1298 int pcix_get_mmrbc(struct pci_dev *dev);
1299 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1300 int pcie_get_readrq(struct pci_dev *dev);
1301 int pcie_set_readrq(struct pci_dev *dev, int rq);
1302 int pcie_get_mps(struct pci_dev *dev);
1303 int pcie_set_mps(struct pci_dev *dev, int mps);
1304 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1305 enum pci_bus_speed *speed,
1306 enum pcie_link_width *width);
1307 void pcie_print_link_status(struct pci_dev *dev);
1308 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1309 int pcie_flr(struct pci_dev *dev);
1310 int __pci_reset_function_locked(struct pci_dev *dev);
1311 int pci_reset_function(struct pci_dev *dev);
1312 int pci_reset_function_locked(struct pci_dev *dev);
1313 int pci_try_reset_function(struct pci_dev *dev);
1314 int pci_probe_reset_slot(struct pci_slot *slot);
1315 int pci_probe_reset_bus(struct pci_bus *bus);
1316 int pci_reset_bus(struct pci_dev *dev);
1317 void pci_reset_secondary_bus(struct pci_dev *dev);
1318 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1319 void pci_update_resource(struct pci_dev *dev, int resno);
1320 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1321 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1322 void pci_release_resource(struct pci_dev *dev, int resno);
1323 static inline int pci_rebar_bytes_to_size(u64 bytes)
1325 bytes = roundup_pow_of_two(bytes);
1327 /* Return BAR size as defined in the resizable BAR specification */
1328 return max(ilog2(bytes), 20) - 20;
1331 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1332 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1333 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1334 bool pci_device_is_present(struct pci_dev *pdev);
1335 void pci_ignore_hotplug(struct pci_dev *dev);
1336 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1337 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1339 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1340 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1341 const char *fmt, ...);
1342 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1344 /* ROM control related routines */
1345 int pci_enable_rom(struct pci_dev *pdev);
1346 void pci_disable_rom(struct pci_dev *pdev);
1347 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1348 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1350 /* Power management related routines */
1351 int pci_save_state(struct pci_dev *dev);
1352 void pci_restore_state(struct pci_dev *dev);
1353 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1354 int pci_load_saved_state(struct pci_dev *dev,
1355 struct pci_saved_state *state);
1356 int pci_load_and_free_saved_state(struct pci_dev *dev,
1357 struct pci_saved_state **state);
1358 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1359 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1360 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1361 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1362 void pci_pme_active(struct pci_dev *dev, bool enable);
1363 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1364 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1365 int pci_prepare_to_sleep(struct pci_dev *dev);
1366 int pci_back_from_sleep(struct pci_dev *dev);
1367 bool pci_dev_run_wake(struct pci_dev *dev);
1368 void pci_d3cold_enable(struct pci_dev *dev);
1369 void pci_d3cold_disable(struct pci_dev *dev);
1370 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1371 void pci_resume_bus(struct pci_bus *bus);
1372 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1374 /* For use by arch with custom probe code */
1375 void set_pcie_port_type(struct pci_dev *pdev);
1376 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1378 /* Functions for PCI Hotplug drivers to use */
1379 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1380 unsigned int pci_rescan_bus(struct pci_bus *bus);
1381 void pci_lock_rescan_remove(void);
1382 void pci_unlock_rescan_remove(void);
1384 /* Vital Product Data routines */
1385 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1386 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1387 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1388 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1390 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1391 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1392 void pci_bus_assign_resources(const struct pci_bus *bus);
1393 void pci_bus_claim_resources(struct pci_bus *bus);
1394 void pci_bus_size_bridges(struct pci_bus *bus);
1395 int pci_claim_resource(struct pci_dev *, int);
1396 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1397 void pci_assign_unassigned_resources(void);
1398 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1399 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1400 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1401 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1402 void pdev_enable_device(struct pci_dev *);
1403 int pci_enable_resources(struct pci_dev *, int mask);
1404 void pci_assign_irq(struct pci_dev *dev);
1405 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1406 #define HAVE_PCI_REQ_REGIONS 2
1407 int __must_check pci_request_regions(struct pci_dev *, const char *);
1408 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1409 void pci_release_regions(struct pci_dev *);
1410 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1411 void pci_release_region(struct pci_dev *, int);
1412 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1413 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1414 void pci_release_selected_regions(struct pci_dev *, int);
1416 static inline __must_check struct resource *
1417 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset,
1418 unsigned int len, const char *name)
1420 return __request_region(&pdev->driver_exclusive_resource, offset, len,
1421 name, IORESOURCE_EXCLUSIVE);
1424 static inline void pci_release_config_region(struct pci_dev *pdev,
1425 unsigned int offset,
1428 __release_region(&pdev->driver_exclusive_resource, offset, len);
1431 /* drivers/pci/bus.c */
1432 void pci_add_resource(struct list_head *resources, struct resource *res);
1433 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1434 resource_size_t offset);
1435 void pci_free_resource_list(struct list_head *resources);
1436 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1437 unsigned int flags);
1438 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1439 void pci_bus_remove_resources(struct pci_bus *bus);
1440 int devm_request_pci_bus_resources(struct device *dev,
1441 struct list_head *resources);
1443 /* Temporary until new and working PCI SBR API in place */
1444 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1446 #define pci_bus_for_each_resource(bus, res, i) \
1448 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1451 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1452 struct resource *res, resource_size_t size,
1453 resource_size_t align, resource_size_t min,
1454 unsigned long type_mask,
1455 resource_size_t (*alignf)(void *,
1456 const struct resource *,
1462 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1463 resource_size_t size);
1464 unsigned long pci_address_to_pio(phys_addr_t addr);
1465 phys_addr_t pci_pio_to_address(unsigned long pio);
1466 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1467 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1468 phys_addr_t phys_addr);
1469 void pci_unmap_iospace(struct resource *res);
1470 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1471 resource_size_t offset,
1472 resource_size_t size);
1473 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1474 struct resource *res);
1476 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1478 struct pci_bus_region region;
1480 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1481 return region.start;
1484 /* Proper probing supporting hot-pluggable devices */
1485 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1486 const char *mod_name);
1488 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1489 #define pci_register_driver(driver) \
1490 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1492 void pci_unregister_driver(struct pci_driver *dev);
1495 * module_pci_driver() - Helper macro for registering a PCI driver
1496 * @__pci_driver: pci_driver struct
1498 * Helper macro for PCI drivers which do not do anything special in module
1499 * init/exit. This eliminates a lot of boilerplate. Each module may only
1500 * use this macro once, and calling it replaces module_init() and module_exit()
1502 #define module_pci_driver(__pci_driver) \
1503 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1506 * builtin_pci_driver() - Helper macro for registering a PCI driver
1507 * @__pci_driver: pci_driver struct
1509 * Helper macro for PCI drivers which do not do anything special in their
1510 * init code. This eliminates a lot of boilerplate. Each driver may only
1511 * use this macro once, and calling it replaces device_initcall(...)
1513 #define builtin_pci_driver(__pci_driver) \
1514 builtin_driver(__pci_driver, pci_register_driver)
1516 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1517 int pci_add_dynid(struct pci_driver *drv,
1518 unsigned int vendor, unsigned int device,
1519 unsigned int subvendor, unsigned int subdevice,
1520 unsigned int class, unsigned int class_mask,
1521 unsigned long driver_data);
1522 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1523 struct pci_dev *dev);
1524 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1527 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1529 int pci_cfg_space_size(struct pci_dev *dev);
1530 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1531 void pci_setup_bridge(struct pci_bus *bus);
1532 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1533 unsigned long type);
1535 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1536 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1538 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1539 unsigned int command_bits, u32 flags);
1542 * Virtual interrupts allow for more interrupts to be allocated
1543 * than the device has interrupts for. These are not programmed
1544 * into the device's MSI-X table and must be handled by some
1545 * other driver means.
1547 #define PCI_IRQ_VIRTUAL (1 << 4)
1549 #define PCI_IRQ_ALL_TYPES \
1550 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1552 #include <linux/dmapool.h>
1555 u32 vector; /* Kernel uses to write allocated vector */
1556 u16 entry; /* Driver uses to specify entry, OS writes */
1559 #ifdef CONFIG_PCI_MSI
1560 int pci_msi_vec_count(struct pci_dev *dev);
1561 void pci_disable_msi(struct pci_dev *dev);
1562 int pci_msix_vec_count(struct pci_dev *dev);
1563 void pci_disable_msix(struct pci_dev *dev);
1564 void pci_restore_msi_state(struct pci_dev *dev);
1565 int pci_msi_enabled(void);
1566 int pci_enable_msi(struct pci_dev *dev);
1567 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1568 int minvec, int maxvec);
1569 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1570 struct msix_entry *entries, int nvec)
1572 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1577 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1578 unsigned int max_vecs, unsigned int flags);
1579 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1580 unsigned int max_vecs, unsigned int flags,
1581 struct irq_affinity *affd);
1583 bool pci_msix_can_alloc_dyn(struct pci_dev *dev);
1584 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1585 const struct irq_affinity_desc *affdesc);
1586 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
1588 void pci_free_irq_vectors(struct pci_dev *dev);
1589 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1590 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1593 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1594 static inline void pci_disable_msi(struct pci_dev *dev) { }
1595 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1596 static inline void pci_disable_msix(struct pci_dev *dev) { }
1597 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1598 static inline int pci_msi_enabled(void) { return 0; }
1599 static inline int pci_enable_msi(struct pci_dev *dev)
1601 static inline int pci_enable_msix_range(struct pci_dev *dev,
1602 struct msix_entry *entries, int minvec, int maxvec)
1604 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1605 struct msix_entry *entries, int nvec)
1609 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1610 unsigned int max_vecs, unsigned int flags,
1611 struct irq_affinity *aff_desc)
1613 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1618 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1619 unsigned int max_vecs, unsigned int flags)
1621 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,
1625 static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1626 const struct irq_affinity_desc *affdesc)
1628 struct msi_map map = { .index = -ENOSYS, };
1633 static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map)
1637 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1641 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1643 if (WARN_ON_ONCE(nr > 0))
1647 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1650 return cpu_possible_mask;
1655 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1656 * @d: the INTx IRQ domain
1657 * @node: the DT node for the device whose interrupt we're translating
1658 * @intspec: the interrupt specifier data from the DT
1659 * @intsize: the number of entries in @intspec
1660 * @out_hwirq: pointer at which to write the hwirq number
1661 * @out_type: pointer at which to write the interrupt type
1663 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1664 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1665 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1666 * INTx value to obtain the hwirq number.
1668 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1670 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1671 struct device_node *node,
1673 unsigned int intsize,
1674 unsigned long *out_hwirq,
1675 unsigned int *out_type)
1677 const u32 intx = intspec[0];
1679 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1682 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1686 #ifdef CONFIG_PCIEPORTBUS
1687 extern bool pcie_ports_disabled;
1688 extern bool pcie_ports_native;
1690 #define pcie_ports_disabled true
1691 #define pcie_ports_native false
1694 #define PCIE_LINK_STATE_L0S BIT(0)
1695 #define PCIE_LINK_STATE_L1 BIT(1)
1696 #define PCIE_LINK_STATE_CLKPM BIT(2)
1697 #define PCIE_LINK_STATE_L1_1 BIT(3)
1698 #define PCIE_LINK_STATE_L1_2 BIT(4)
1699 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1700 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1702 #ifdef CONFIG_PCIEASPM
1703 int pci_disable_link_state(struct pci_dev *pdev, int state);
1704 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1705 void pcie_no_aspm(void);
1706 bool pcie_aspm_support_enabled(void);
1707 bool pcie_aspm_enabled(struct pci_dev *pdev);
1709 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1711 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1713 static inline void pcie_no_aspm(void) { }
1714 static inline bool pcie_aspm_support_enabled(void) { return false; }
1715 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1718 #ifdef CONFIG_PCIEAER
1719 bool pci_aer_available(void);
1721 static inline bool pci_aer_available(void) { return false; }
1724 bool pci_ats_disabled(void);
1726 #ifdef CONFIG_PCIE_PTM
1727 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1728 void pci_disable_ptm(struct pci_dev *dev);
1729 bool pcie_ptm_enabled(struct pci_dev *dev);
1731 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1733 static inline void pci_disable_ptm(struct pci_dev *dev) { }
1734 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1738 void pci_cfg_access_lock(struct pci_dev *dev);
1739 bool pci_cfg_access_trylock(struct pci_dev *dev);
1740 void pci_cfg_access_unlock(struct pci_dev *dev);
1742 void pci_dev_lock(struct pci_dev *dev);
1743 int pci_dev_trylock(struct pci_dev *dev);
1744 void pci_dev_unlock(struct pci_dev *dev);
1747 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1748 * a PCI domain is defined to be a set of PCI buses which share
1749 * configuration space.
1751 #ifdef CONFIG_PCI_DOMAINS
1752 extern int pci_domains_supported;
1754 enum { pci_domains_supported = 0 };
1755 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1756 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1757 #endif /* CONFIG_PCI_DOMAINS */
1760 * Generic implementation for PCI domain support. If your
1761 * architecture does not need custom management of PCI
1762 * domains then this implementation will be used
1764 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1765 static inline int pci_domain_nr(struct pci_bus *bus)
1767 return bus->domain_nr;
1770 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1772 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1775 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1776 void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent);
1779 /* Some architectures require additional setup to direct VGA traffic */
1780 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1781 unsigned int command_bits, u32 flags);
1782 void pci_register_set_vga_state(arch_set_vga_state_t func);
1785 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1787 return pci_request_selected_regions(pdev,
1788 pci_select_bars(pdev, IORESOURCE_IO), name);
1792 pci_release_io_regions(struct pci_dev *pdev)
1794 return pci_release_selected_regions(pdev,
1795 pci_select_bars(pdev, IORESOURCE_IO));
1799 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1801 return pci_request_selected_regions(pdev,
1802 pci_select_bars(pdev, IORESOURCE_MEM), name);
1806 pci_release_mem_regions(struct pci_dev *pdev)
1808 return pci_release_selected_regions(pdev,
1809 pci_select_bars(pdev, IORESOURCE_MEM));
1812 #else /* CONFIG_PCI is not enabled */
1814 static inline void pci_set_flags(int flags) { }
1815 static inline void pci_add_flags(int flags) { }
1816 static inline void pci_clear_flags(int flags) { }
1817 static inline int pci_has_flag(int flag) { return 0; }
1820 * If the system does not have PCI, clearly these return errors. Define
1821 * these as simple inline functions to avoid hair in drivers.
1823 #define _PCI_NOP(o, s, t) \
1824 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1826 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1828 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1829 _PCI_NOP(o, word, u16 x) \
1830 _PCI_NOP(o, dword, u32 x)
1831 _PCI_NOP_ALL(read, *)
1832 _PCI_NOP_ALL(write,)
1834 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1835 unsigned int device,
1836 struct pci_dev *from)
1839 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1840 unsigned int device,
1841 unsigned int ss_vendor,
1842 unsigned int ss_device,
1843 struct pci_dev *from)
1846 static inline struct pci_dev *pci_get_class(unsigned int class,
1847 struct pci_dev *from)
1851 static inline int pci_dev_present(const struct pci_device_id *ids)
1854 #define no_pci_devices() (1)
1855 #define pci_dev_put(dev) do { } while (0)
1857 static inline void pci_set_master(struct pci_dev *dev) { }
1858 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1859 static inline void pci_disable_device(struct pci_dev *dev) { }
1860 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1861 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1863 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1864 struct module *owner,
1865 const char *mod_name)
1867 static inline int pci_register_driver(struct pci_driver *drv)
1869 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1870 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1872 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1875 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1878 static inline u64 pci_get_dsn(struct pci_dev *dev)
1881 /* Power management related routines */
1882 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1883 static inline void pci_restore_state(struct pci_dev *dev) { }
1884 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1886 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1888 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1891 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1895 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1896 struct resource *res)
1898 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1900 static inline void pci_release_regions(struct pci_dev *dev) { }
1902 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1903 phys_addr_t addr, resource_size_t size)
1906 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1908 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1910 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1913 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1914 unsigned int bus, unsigned int devfn)
1917 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1918 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1920 #define dev_is_pci(d) (false)
1921 #define dev_is_pf(d) (false)
1922 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1924 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1925 struct device_node *node,
1927 unsigned int intsize,
1928 unsigned long *out_hwirq,
1929 unsigned int *out_type)
1932 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1933 struct pci_dev *dev)
1935 static inline bool pci_ats_disabled(void) { return true; }
1937 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1943 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1944 unsigned int max_vecs, unsigned int flags,
1945 struct irq_affinity *aff_desc)
1950 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1951 unsigned int max_vecs, unsigned int flags)
1955 #endif /* CONFIG_PCI */
1957 /* Include architecture-dependent settings and functions */
1959 #include <asm/pci.h>
1962 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1963 * is expected to be an offset within that region.
1966 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1967 struct vm_area_struct *vma,
1968 enum pci_mmap_state mmap_state, int write_combine);
1970 #ifndef arch_can_pci_mmap_wc
1971 #define arch_can_pci_mmap_wc() 0
1974 #ifndef arch_can_pci_mmap_io
1975 #define arch_can_pci_mmap_io() 0
1976 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1978 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1981 #ifndef pci_root_bus_fwnode
1982 #define pci_root_bus_fwnode(bus) NULL
1986 * These helpers provide future and backwards compatibility
1987 * for accessing popular PCI BAR info
1989 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1990 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1991 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1992 #define pci_resource_len(dev,bar) \
1993 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1995 (pci_resource_end((dev), (bar)) - \
1996 pci_resource_start((dev), (bar)) + 1))
1999 * Similar to the helpers above, these manipulate per-pci_dev
2000 * driver-specific data. They are really just a wrapper around
2001 * the generic device structure functions of these calls.
2003 static inline void *pci_get_drvdata(struct pci_dev *pdev)
2005 return dev_get_drvdata(&pdev->dev);
2008 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
2010 dev_set_drvdata(&pdev->dev, data);
2013 static inline const char *pci_name(const struct pci_dev *pdev)
2015 return dev_name(&pdev->dev);
2018 void pci_resource_to_user(const struct pci_dev *dev, int bar,
2019 const struct resource *rsrc,
2020 resource_size_t *start, resource_size_t *end);
2023 * The world is not perfect and supplies us with broken PCI devices.
2024 * For at least a part of these bugs we need a work-around, so both
2025 * generic (drivers/pci/quirks.c) and per-architecture code can define
2026 * fixup hooks to be called for particular buggy devices.
2030 u16 vendor; /* Or PCI_ANY_ID */
2031 u16 device; /* Or PCI_ANY_ID */
2032 u32 class; /* Or PCI_ANY_ID */
2033 unsigned int class_shift; /* should be 0, 8, 16 */
2034 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2037 void (*hook)(struct pci_dev *dev);
2041 enum pci_fixup_pass {
2042 pci_fixup_early, /* Before probing BARs */
2043 pci_fixup_header, /* After reading configuration header */
2044 pci_fixup_final, /* Final phase of device fixups */
2045 pci_fixup_enable, /* pci_enable_device() time */
2046 pci_fixup_resume, /* pci_device_resume() */
2047 pci_fixup_suspend, /* pci_device_suspend() */
2048 pci_fixup_resume_early, /* pci_device_resume_early() */
2049 pci_fixup_suspend_late, /* pci_device_suspend_late() */
2052 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2053 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2054 class_shift, hook) \
2055 __ADDRESSABLE(hook) \
2056 asm(".section " #sec ", \"a\" \n" \
2058 ".short " #vendor ", " #device " \n" \
2059 ".long " #class ", " #class_shift " \n" \
2060 ".long " #hook " - . \n" \
2064 * Clang's LTO may rename static functions in C, but has no way to
2065 * handle such renamings when referenced from inline asm. To work
2066 * around this, create global C stubs for these cases.
2068 #ifdef CONFIG_LTO_CLANG
2069 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2070 class_shift, hook, stub) \
2071 void stub(struct pci_dev *dev); \
2072 void stub(struct pci_dev *dev) \
2076 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2079 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2080 class_shift, hook, stub) \
2081 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2085 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2086 class_shift, hook) \
2087 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2088 class_shift, hook, __UNIQUE_ID(hook))
2090 /* Anonymous variables would be nice... */
2091 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2092 class_shift, hook) \
2093 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2094 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2095 = { vendor, device, class, class_shift, hook };
2098 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2099 class_shift, hook) \
2100 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2101 hook, vendor, device, class, class_shift, hook)
2102 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2103 class_shift, hook) \
2104 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2105 hook, vendor, device, class, class_shift, hook)
2106 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2107 class_shift, hook) \
2108 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2109 hook, vendor, device, class, class_shift, hook)
2110 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2111 class_shift, hook) \
2112 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2113 hook, vendor, device, class, class_shift, hook)
2114 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2115 class_shift, hook) \
2116 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2117 resume##hook, vendor, device, class, class_shift, hook)
2118 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2119 class_shift, hook) \
2120 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2121 resume_early##hook, vendor, device, class, class_shift, hook)
2122 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2123 class_shift, hook) \
2124 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2125 suspend##hook, vendor, device, class, class_shift, hook)
2126 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2127 class_shift, hook) \
2128 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2129 suspend_late##hook, vendor, device, class, class_shift, hook)
2131 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2132 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2133 hook, vendor, device, PCI_ANY_ID, 0, hook)
2134 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2135 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2136 hook, vendor, device, PCI_ANY_ID, 0, hook)
2137 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2138 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2139 hook, vendor, device, PCI_ANY_ID, 0, hook)
2140 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2141 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2142 hook, vendor, device, PCI_ANY_ID, 0, hook)
2143 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2144 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2145 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2146 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2147 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2148 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2149 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2150 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2151 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2152 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2153 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2154 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2156 #ifdef CONFIG_PCI_QUIRKS
2157 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2159 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2160 struct pci_dev *dev) { }
2163 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2164 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2165 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2166 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2167 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2169 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2171 extern int pci_pci_problems;
2172 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2173 #define PCIPCI_TRITON 2
2174 #define PCIPCI_NATOMA 4
2175 #define PCIPCI_VIAETBF 8
2176 #define PCIPCI_VSFX 16
2177 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2178 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2180 extern unsigned long pci_cardbus_io_size;
2181 extern unsigned long pci_cardbus_mem_size;
2182 extern u8 pci_dfl_cache_line_size;
2183 extern u8 pci_cache_line_size;
2185 /* Architecture-specific versions may override these (weak) */
2186 void pcibios_disable_device(struct pci_dev *dev);
2187 void pcibios_set_master(struct pci_dev *dev);
2188 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2189 enum pcie_reset_state state);
2190 int pcibios_device_add(struct pci_dev *dev);
2191 void pcibios_release_device(struct pci_dev *dev);
2193 void pcibios_penalize_isa_irq(int irq, int active);
2195 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2197 int pcibios_alloc_irq(struct pci_dev *dev);
2198 void pcibios_free_irq(struct pci_dev *dev);
2199 resource_size_t pcibios_default_alignment(void);
2201 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2202 void __init pci_mmcfg_early_init(void);
2203 void __init pci_mmcfg_late_init(void);
2205 static inline void pci_mmcfg_early_init(void) { }
2206 static inline void pci_mmcfg_late_init(void) { }
2209 int pci_ext_cfg_avail(void);
2211 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2212 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2214 #ifdef CONFIG_PCI_IOV
2215 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2216 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2217 int pci_iov_vf_id(struct pci_dev *dev);
2218 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
2219 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2220 void pci_disable_sriov(struct pci_dev *dev);
2222 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2223 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2224 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2225 int pci_num_vf(struct pci_dev *dev);
2226 int pci_vfs_assigned(struct pci_dev *dev);
2227 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2228 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2229 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2230 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2231 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2233 /* Arch may override these (weak) */
2234 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2235 int pcibios_sriov_disable(struct pci_dev *pdev);
2236 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2238 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2242 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2247 static inline int pci_iov_vf_id(struct pci_dev *dev)
2252 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2253 struct pci_driver *pf_driver)
2255 return ERR_PTR(-EINVAL);
2258 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2261 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2262 struct pci_dev *virtfn, int id)
2266 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2270 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2272 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2273 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2274 static inline int pci_vfs_assigned(struct pci_dev *dev)
2276 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2278 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2280 #define pci_sriov_configure_simple NULL
2281 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2283 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2286 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2287 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2288 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2292 * pci_pcie_cap - get the saved PCIe capability offset
2295 * PCIe capability offset is calculated at PCI device initialization
2296 * time and saved in the data structure. This function returns saved
2297 * PCIe capability offset. Using this instead of pci_find_capability()
2298 * reduces unnecessary search in the PCI configuration space. If you
2299 * need to calculate PCIe capability offset from raw device for some
2300 * reasons, please use pci_find_capability() instead.
2302 static inline int pci_pcie_cap(struct pci_dev *dev)
2304 return dev->pcie_cap;
2308 * pci_is_pcie - check if the PCI device is PCI Express capable
2311 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2313 static inline bool pci_is_pcie(struct pci_dev *dev)
2315 return pci_pcie_cap(dev);
2319 * pcie_caps_reg - get the PCIe Capabilities Register
2322 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2324 return dev->pcie_flags_reg;
2328 * pci_pcie_type - get the PCIe device/port type
2331 static inline int pci_pcie_type(const struct pci_dev *dev)
2333 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2337 * pcie_find_root_port - Get the PCIe root port device
2340 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2341 * for a given PCI/PCIe Device.
2343 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2346 if (pci_is_pcie(dev) &&
2347 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2349 dev = pci_upstream_bridge(dev);
2355 void pci_request_acs(void);
2356 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2357 bool pci_acs_path_enabled(struct pci_dev *start,
2358 struct pci_dev *end, u16 acs_flags);
2359 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2361 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2362 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2364 /* Large Resource Data Type Tag Item Names */
2365 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2366 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2367 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2369 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2370 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2371 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2373 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2374 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2375 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2376 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2377 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2380 * pci_vpd_alloc - Allocate buffer and read VPD into it
2382 * @size: pointer to field where VPD length is returned
2384 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2386 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2389 * pci_vpd_find_id_string - Locate id string in VPD
2390 * @buf: Pointer to buffered VPD data
2391 * @len: The length of the buffer area in which to search
2392 * @size: Pointer to field where length of id string is returned
2394 * Returns the index of the id string or -ENOENT if not found.
2396 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2399 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2400 * @buf: Pointer to buffered VPD data
2401 * @len: The length of the buffer area in which to search
2402 * @kw: The keyword to search for
2403 * @size: Pointer to field where length of found keyword data is returned
2405 * Returns the index of the information field keyword data or -ENOENT if
2408 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2409 const char *kw, unsigned int *size);
2412 * pci_vpd_check_csum - Check VPD checksum
2413 * @buf: Pointer to buffered VPD data
2416 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2418 int pci_vpd_check_csum(const void *buf, unsigned int len);
2420 /* PCI <-> OF binding helpers */
2424 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2425 bool pci_host_of_has_msi_map(struct device *dev);
2427 /* Arch may override this (weak) */
2428 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2430 #else /* CONFIG_OF */
2431 static inline struct irq_domain *
2432 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2433 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2434 #endif /* CONFIG_OF */
2436 static inline struct device_node *
2437 pci_device_to_OF_node(const struct pci_dev *pdev)
2439 return pdev ? pdev->dev.of_node : NULL;
2442 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2444 return bus ? bus->dev.of_node : NULL;
2448 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2451 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2452 bool pci_pr3_present(struct pci_dev *pdev);
2454 static inline struct irq_domain *
2455 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2456 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2460 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2462 return pdev->dev.archdata.edev;
2466 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2467 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2468 int pci_for_each_dma_alias(struct pci_dev *pdev,
2469 int (*fn)(struct pci_dev *pdev,
2470 u16 alias, void *data), void *data);
2472 /* Helper functions for operation of device flag */
2473 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2475 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2477 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2479 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2481 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2483 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2487 * pci_ari_enabled - query ARI forwarding status
2490 * Returns true if ARI forwarding is enabled.
2492 static inline bool pci_ari_enabled(struct pci_bus *bus)
2494 return bus->self && bus->self->ari_enabled;
2498 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2499 * @pdev: PCI device to check
2501 * Walk upwards from @pdev and check for each encountered bridge if it's part
2502 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2503 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2505 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2507 struct pci_dev *parent = pdev;
2509 if (pdev->is_thunderbolt)
2512 while ((parent = pci_upstream_bridge(parent)))
2513 if (parent->is_thunderbolt)
2519 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2520 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2523 struct msi_domain_template;
2525 bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
2526 unsigned int hwsize, void *data);
2527 struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie,
2528 const struct irq_affinity_desc *affdesc);
2529 void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map);
2531 #include <linux/dma-mapping.h>
2533 #define pci_printk(level, pdev, fmt, arg...) \
2534 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2536 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2537 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2538 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2539 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2540 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2541 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg)
2542 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2543 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2544 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2546 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2547 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2549 #define pci_info_ratelimited(pdev, fmt, arg...) \
2550 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2552 #define pci_WARN(pdev, condition, fmt, arg...) \
2553 WARN(condition, "%s %s: " fmt, \
2554 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2556 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2557 WARN_ONCE(condition, "%s %s: " fmt, \
2558 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2560 #endif /* LINUX_PCI_H */