include/linux/nvme.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Definitions for the NVM Express interface
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #ifndef _LINUX_NVME_H
   8 #define _LINUX_NVME_H
   9
  10 #include <linux/types.h>
  11 #include <linux/uuid.h>
  12
  13 /* NQN names in commands fields specified one size */
  14 #define NVMF_NQN_FIELD_LEN      256
  15
  16 /* However the max length of a qualified name is another size */
  17 #define NVMF_NQN_SIZE           223
  18
  19 #define NVMF_TRSVCID_SIZE       32
  20 #define NVMF_TRADDR_SIZE        256
  21 #define NVMF_TSAS_SIZE          256
  22
  23 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  24
  25 #define NVME_RDMA_IP_PORT       4420
  26
  27 #define NVME_NSID_ALL           0xffffffff
  28
  29 enum nvme_subsys_type {
  30         /* Referral to another discovery type target subsystem */
  31         NVME_NQN_DISC   = 1,
  32
  33         /* NVME type target subsystem */
  34         NVME_NQN_NVME   = 2,
  35
  36         /* Current discovery type target subsystem */
  37         NVME_NQN_CURR   = 3,
  38 };
  39
  40 enum nvme_ctrl_type {
  41         NVME_CTRL_IO    = 1,            /* I/O controller */
  42         NVME_CTRL_DISC  = 2,            /* Discovery controller */
  43         NVME_CTRL_ADMIN = 3,            /* Administrative controller */
  44 };
  45
  46 enum nvme_dctype {
  47         NVME_DCTYPE_NOT_REPORTED        = 0,
  48         NVME_DCTYPE_DDC                 = 1, /* Direct Discovery Controller */
  49         NVME_DCTYPE_CDC                 = 2, /* Central Discovery Controller */
  50 };
  51
  52 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  53 enum {
  54         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  55         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  56         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  57         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  58         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  59         NVMF_ADDR_FAMILY_LOOP   = 254,  /* Reserved for host usage */
  60         NVMF_ADDR_FAMILY_MAX,
  61 };
  62
  63 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  64 enum {
  65         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  66         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  67         NVMF_TRTYPE_TCP         = 3,    /* TCP/IP */
  68         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  69         NVMF_TRTYPE_MAX,
  70 };
  71
  72 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  73 enum {
  74         NVMF_TREQ_NOT_SPECIFIED = 0,            /* Not specified */
  75         NVMF_TREQ_REQUIRED      = 1,            /* Required */
  76         NVMF_TREQ_NOT_REQUIRED  = 2,            /* Not Required */
  77 #define NVME_TREQ_SECURE_CHANNEL_MASK \
  78         (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
  79
  80         NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),    /* Supports SQ flow control disable */
  81 };
  82
  83 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  84  * RDMA_QPTYPE field
  85  */
  86 enum {
  87         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
  88         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
  89 };
  90
  91 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  92  * RDMA_QPTYPE field
  93  */
  94 enum {
  95         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
  96         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
  97         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
  98         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
  99         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
 100 };
 101
 102 /* RDMA Connection Management Service Type codes for Discovery Log Page
 103  * entry TSAS RDMA_CMS field
 104  */
 105 enum {
 106         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
 107 };
 108
 109 #define NVME_AQ_DEPTH           32
 110 #define NVME_NR_AEN_COMMANDS    1
 111 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
 112
 113 /*
 114  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
 115  * NVM-Express 1.2 specification, section 4.1.2.
 116  */
 117 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
 118
 119 enum {
 120         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
 121         NVME_REG_VS     = 0x0008,       /* Version */
 122         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
 123         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
 124         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
 125         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
 126         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
 127         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 128         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 129         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 130         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 131         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 132         NVME_REG_BPINFO = 0x0040,       /* Boot Partition Information */
 133         NVME_REG_BPRSEL = 0x0044,       /* Boot Partition Read Select */
 134         NVME_REG_BPMBL  = 0x0048,       /* Boot Partition Memory Buffer
 135                                          * Location
 136                                          */
 137         NVME_REG_CMBMSC = 0x0050,       /* Controller Memory Buffer Memory
 138                                          * Space Control
 139                                          */
 140         NVME_REG_CRTO   = 0x0068,       /* Controller Ready Timeouts */
 141         NVME_REG_PMRCAP = 0x0e00,       /* Persistent Memory Capabilities */
 142         NVME_REG_PMRCTL = 0x0e04,       /* Persistent Memory Region Control */
 143         NVME_REG_PMRSTS = 0x0e08,       /* Persistent Memory Region Status */
 144         NVME_REG_PMREBS = 0x0e0c,       /* Persistent Memory Region Elasticity
 145                                          * Buffer Size
 146                                          */
 147         NVME_REG_PMRSWTP = 0x0e10,      /* Persistent Memory Region Sustained
 148                                          * Write Throughput
 149                                          */
 150         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
 151 };
 152
 153 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 154 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 155 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 156 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 157 #define NVME_CAP_CSS(cap)       (((cap) >> 37) & 0xff)
 158 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 159 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 160 #define NVME_CAP_CMBS(cap)      (((cap) >> 57) & 0x1)
 161
 162 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 163 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 164
 165 #define NVME_CRTO_CRIMT(crto)   ((crto) >> 16)
 166 #define NVME_CRTO_CRWMT(crto)   ((crto) & 0xffff)
 167
 168 enum {
 169         NVME_CMBSZ_SQS          = 1 << 0,
 170         NVME_CMBSZ_CQS          = 1 << 1,
 171         NVME_CMBSZ_LISTS        = 1 << 2,
 172         NVME_CMBSZ_RDS          = 1 << 3,
 173         NVME_CMBSZ_WDS          = 1 << 4,
 174
 175         NVME_CMBSZ_SZ_SHIFT     = 12,
 176         NVME_CMBSZ_SZ_MASK      = 0xfffff,
 177
 178         NVME_CMBSZ_SZU_SHIFT    = 8,
 179         NVME_CMBSZ_SZU_MASK     = 0xf,
 180 };
 181
 182 /*
 183  * Submission and Completion Queue Entry Sizes for the NVM command set.
 184  * (In bytes and specified as a power of two (2^n)).
 185  */
 186 #define NVME_ADM_SQES       6
 187 #define NVME_NVM_IOSQES         6
 188 #define NVME_NVM_IOCQES         4
 189
 190 enum {
 191         NVME_CC_ENABLE          = 1 << 0,
 192         NVME_CC_EN_SHIFT        = 0,
 193         NVME_CC_CSS_SHIFT       = 4,
 194         NVME_CC_MPS_SHIFT       = 7,
 195         NVME_CC_AMS_SHIFT       = 11,
 196         NVME_CC_SHN_SHIFT       = 14,
 197         NVME_CC_IOSQES_SHIFT    = 16,
 198         NVME_CC_IOCQES_SHIFT    = 20,
 199         NVME_CC_CSS_NVM         = 0 << NVME_CC_CSS_SHIFT,
 200         NVME_CC_CSS_CSI         = 6 << NVME_CC_CSS_SHIFT,
 201         NVME_CC_CSS_MASK        = 7 << NVME_CC_CSS_SHIFT,
 202         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
 203         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
 204         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
 205         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
 206         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
 207         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
 208         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
 209         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
 210         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
 211         NVME_CC_CRIME           = 1 << 24,
 212 };
 213
 214 enum {
 215         NVME_CSTS_RDY           = 1 << 0,
 216         NVME_CSTS_CFS           = 1 << 1,
 217         NVME_CSTS_NSSRO         = 1 << 4,
 218         NVME_CSTS_PP            = 1 << 5,
 219         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 220         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 221         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 222         NVME_CSTS_SHST_MASK     = 3 << 2,
 223 };
 224
 225 enum {
 226         NVME_CMBMSC_CRE         = 1 << 0,
 227         NVME_CMBMSC_CMSE        = 1 << 1,
 228 };
 229
 230 enum {
 231         NVME_CAP_CSS_NVM        = 1 << 0,
 232         NVME_CAP_CSS_CSI        = 1 << 6,
 233 };
 234
 235 enum {
 236         NVME_CAP_CRMS_CRWMS     = 1ULL << 59,
 237         NVME_CAP_CRMS_CRIMS     = 1ULL << 60,
 238 };
 239
 240 struct nvme_id_power_state {
 241         __le16                  max_power;      /* centiwatts */
 242         __u8                    rsvd2;
 243         __u8                    flags;
 244         __le32                  entry_lat;      /* microseconds */
 245         __le32                  exit_lat;       /* microseconds */
 246         __u8                    read_tput;
 247         __u8                    read_lat;
 248         __u8                    write_tput;
 249         __u8                    write_lat;
 250         __le16                  idle_power;
 251         __u8                    idle_scale;
 252         __u8                    rsvd19;
 253         __le16                  active_power;
 254         __u8                    active_work_scale;
 255         __u8                    rsvd23[9];
 256 };
 257
 258 enum {
 259         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 260         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 261 };
 262
 263 enum nvme_ctrl_attr {
 264         NVME_CTRL_ATTR_HID_128_BIT      = (1 << 0),
 265         NVME_CTRL_ATTR_TBKAS            = (1 << 6),
 266         NVME_CTRL_ATTR_ELBAS            = (1 << 15),
 267 };
 268
 269 struct nvme_id_ctrl {
 270         __le16                  vid;
 271         __le16                  ssvid;
 272         char                    sn[20];
 273         char                    mn[40];
 274         char                    fr[8];
 275         __u8                    rab;
 276         __u8                    ieee[3];
 277         __u8                    cmic;
 278         __u8                    mdts;
 279         __le16                  cntlid;
 280         __le32                  ver;
 281         __le32                  rtd3r;
 282         __le32                  rtd3e;
 283         __le32                  oaes;
 284         __le32                  ctratt;
 285         __u8                    rsvd100[11];
 286         __u8                    cntrltype;
 287         __u8                    fguid[16];
 288         __le16                  crdt1;
 289         __le16                  crdt2;
 290         __le16                  crdt3;
 291         __u8                    rsvd134[122];
 292         __le16                  oacs;
 293         __u8                    acl;
 294         __u8                    aerl;
 295         __u8                    frmw;
 296         __u8                    lpa;
 297         __u8                    elpe;
 298         __u8                    npss;
 299         __u8                    avscc;
 300         __u8                    apsta;
 301         __le16                  wctemp;
 302         __le16                  cctemp;
 303         __le16                  mtfa;
 304         __le32                  hmpre;
 305         __le32                  hmmin;
 306         __u8                    tnvmcap[16];
 307         __u8                    unvmcap[16];
 308         __le32                  rpmbs;
 309         __le16                  edstt;
 310         __u8                    dsto;
 311         __u8                    fwug;
 312         __le16                  kas;
 313         __le16                  hctma;
 314         __le16                  mntmt;
 315         __le16                  mxtmt;
 316         __le32                  sanicap;
 317         __le32                  hmminds;
 318         __le16                  hmmaxd;
 319         __u8                    rsvd338[4];
 320         __u8                    anatt;
 321         __u8                    anacap;
 322         __le32                  anagrpmax;
 323         __le32                  nanagrpid;
 324         __u8                    rsvd352[160];
 325         __u8                    sqes;
 326         __u8                    cqes;
 327         __le16                  maxcmd;
 328         __le32                  nn;
 329         __le16                  oncs;
 330         __le16                  fuses;
 331         __u8                    fna;
 332         __u8                    vwc;
 333         __le16                  awun;
 334         __le16                  awupf;
 335         __u8                    nvscc;
 336         __u8                    nwpc;
 337         __le16                  acwu;
 338         __u8                    rsvd534[2];
 339         __le32                  sgls;
 340         __le32                  mnan;
 341         __u8                    rsvd544[224];
 342         char                    subnqn[256];
 343         __u8                    rsvd1024[768];
 344         __le32                  ioccsz;
 345         __le32                  iorcsz;
 346         __le16                  icdoff;
 347         __u8                    ctrattr;
 348         __u8                    msdbd;
 349         __u8                    rsvd1804[2];
 350         __u8                    dctype;
 351         __u8                    rsvd1807[241];
 352         struct nvme_id_power_state      psd[32];
 353         __u8                    vs[1024];
 354 };
 355
 356 enum {
 357         NVME_CTRL_CMIC_MULTI_PORT               = 1 << 0,
 358         NVME_CTRL_CMIC_MULTI_CTRL               = 1 << 1,
 359         NVME_CTRL_CMIC_ANA                      = 1 << 3,
 360         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 361         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 362         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 363         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 364         NVME_CTRL_ONCS_RESERVATIONS             = 1 << 5,
 365         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
 366         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 367         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
 368         NVME_CTRL_OACS_NS_MNGT_SUPP             = 1 << 3,
 369         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
 370         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
 371         NVME_CTRL_LPA_CMD_EFFECTS_LOG           = 1 << 1,
 372         NVME_CTRL_CTRATT_128_ID                 = 1 << 0,
 373         NVME_CTRL_CTRATT_NON_OP_PSP             = 1 << 1,
 374         NVME_CTRL_CTRATT_NVM_SETS               = 1 << 2,
 375         NVME_CTRL_CTRATT_READ_RECV_LVLS         = 1 << 3,
 376         NVME_CTRL_CTRATT_ENDURANCE_GROUPS       = 1 << 4,
 377         NVME_CTRL_CTRATT_PREDICTABLE_LAT        = 1 << 5,
 378         NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY  = 1 << 7,
 379         NVME_CTRL_CTRATT_UUID_LIST              = 1 << 9,
 380 };
 381
 382 struct nvme_lbaf {
 383         __le16                  ms;
 384         __u8                    ds;
 385         __u8                    rp;
 386 };
 387
 388 struct nvme_id_ns {
 389         __le64                  nsze;
 390         __le64                  ncap;
 391         __le64                  nuse;
 392         __u8                    nsfeat;
 393         __u8                    nlbaf;
 394         __u8                    flbas;
 395         __u8                    mc;
 396         __u8                    dpc;
 397         __u8                    dps;
 398         __u8                    nmic;
 399         __u8                    rescap;
 400         __u8                    fpi;
 401         __u8                    dlfeat;
 402         __le16                  nawun;
 403         __le16                  nawupf;
 404         __le16                  nacwu;
 405         __le16                  nabsn;
 406         __le16                  nabo;
 407         __le16                  nabspf;
 408         __le16                  noiob;
 409         __u8                    nvmcap[16];
 410         __le16                  npwg;
 411         __le16                  npwa;
 412         __le16                  npdg;
 413         __le16                  npda;
 414         __le16                  nows;
 415         __u8                    rsvd74[18];
 416         __le32                  anagrpid;
 417         __u8                    rsvd96[3];
 418         __u8                    nsattr;
 419         __le16                  nvmsetid;
 420         __le16                  endgid;
 421         __u8                    nguid[16];
 422         __u8                    eui64[8];
 423         struct nvme_lbaf        lbaf[64];
 424         __u8                    vs[3712];
 425 };
 426
 427 /* I/O Command Set Independent Identify Namespace Data Structure */
 428 struct nvme_id_ns_cs_indep {
 429         __u8                    nsfeat;
 430         __u8                    nmic;
 431         __u8                    rescap;
 432         __u8                    fpi;
 433         __le32                  anagrpid;
 434         __u8                    nsattr;
 435         __u8                    rsvd9;
 436         __le16                  nvmsetid;
 437         __le16                  endgid;
 438         __u8                    nstat;
 439         __u8                    rsvd15[4081];
 440 };
 441
 442 struct nvme_zns_lbafe {
 443         __le64                  zsze;
 444         __u8                    zdes;
 445         __u8                    rsvd9[7];
 446 };
 447
 448 struct nvme_id_ns_zns {
 449         __le16                  zoc;
 450         __le16                  ozcs;
 451         __le32                  mar;
 452         __le32                  mor;
 453         __le32                  rrl;
 454         __le32                  frl;
 455         __u8                    rsvd20[2796];
 456         struct nvme_zns_lbafe   lbafe[64];
 457         __u8                    vs[256];
 458 };
 459
 460 struct nvme_id_ctrl_zns {
 461         __u8    zasl;
 462         __u8    rsvd1[4095];
 463 };
 464
 465 struct nvme_id_ns_nvm {
 466         __le64  lbstm;
 467         __u8    pic;
 468         __u8    rsvd9[3];
 469         __le32  elbaf[64];
 470         __u8    rsvd268[3828];
 471 };
 472
 473 enum {
 474         NVME_ID_NS_NVM_STS_MASK         = 0x3f,
 475         NVME_ID_NS_NVM_GUARD_SHIFT      = 7,
 476         NVME_ID_NS_NVM_GUARD_MASK       = 0x3,
 477 };
 478
 479 static inline __u8 nvme_elbaf_sts(__u32 elbaf)
 480 {
 481         return elbaf & NVME_ID_NS_NVM_STS_MASK;
 482 }
 483
 484 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
 485 {
 486         return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
 487 }
 488
 489 struct nvme_id_ctrl_nvm {
 490         __u8    vsl;
 491         __u8    wzsl;
 492         __u8    wusl;
 493         __u8    dmrl;
 494         __le32  dmrsl;
 495         __le64  dmsl;
 496         __u8    rsvd16[4080];
 497 };
 498
 499 enum {
 500         NVME_ID_CNS_NS                  = 0x00,
 501         NVME_ID_CNS_CTRL                = 0x01,
 502         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 503         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
 504         NVME_ID_CNS_CS_NS               = 0x05,
 505         NVME_ID_CNS_CS_CTRL             = 0x06,
 506         NVME_ID_CNS_NS_CS_INDEP         = 0x08,
 507         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 508         NVME_ID_CNS_NS_PRESENT          = 0x11,
 509         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 510         NVME_ID_CNS_CTRL_LIST           = 0x13,
 511         NVME_ID_CNS_SCNDRY_CTRL_LIST    = 0x15,
 512         NVME_ID_CNS_NS_GRANULARITY      = 0x16,
 513         NVME_ID_CNS_UUID_LIST           = 0x17,
 514 };
 515
 516 enum {
 517         NVME_CSI_NVM                    = 0,
 518         NVME_CSI_ZNS                    = 2,
 519 };
 520
 521 enum {
 522         NVME_DIR_IDENTIFY               = 0x00,
 523         NVME_DIR_STREAMS                = 0x01,
 524         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
 525         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
 526         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
 527         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
 528         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
 529         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
 530         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
 531         NVME_DIR_ENDIR                  = 0x01,
 532 };
 533
 534 enum {
 535         NVME_NS_FEAT_THIN       = 1 << 0,
 536         NVME_NS_FEAT_ATOMICS    = 1 << 1,
 537         NVME_NS_FEAT_IO_OPT     = 1 << 4,
 538         NVME_NS_ATTR_RO         = 1 << 0,
 539         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 540         NVME_NS_FLBAS_LBA_UMASK = 0x60,
 541         NVME_NS_FLBAS_LBA_SHIFT = 1,
 542         NVME_NS_FLBAS_META_EXT  = 0x10,
 543         NVME_NS_NMIC_SHARED     = 1 << 0,
 544         NVME_LBAF_RP_BEST       = 0,
 545         NVME_LBAF_RP_BETTER     = 1,
 546         NVME_LBAF_RP_GOOD       = 2,
 547         NVME_LBAF_RP_DEGRADED   = 3,
 548         NVME_NS_DPC_PI_LAST     = 1 << 4,
 549         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 550         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 551         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 552         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 553         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 554         NVME_NS_DPS_PI_MASK     = 0x7,
 555         NVME_NS_DPS_PI_TYPE1    = 1,
 556         NVME_NS_DPS_PI_TYPE2    = 2,
 557         NVME_NS_DPS_PI_TYPE3    = 3,
 558 };
 559
 560 enum {
 561         NVME_NSTAT_NRDY         = 1 << 0,
 562 };
 563
 564 enum {
 565         NVME_NVM_NS_16B_GUARD   = 0,
 566         NVME_NVM_NS_32B_GUARD   = 1,
 567         NVME_NVM_NS_64B_GUARD   = 2,
 568 };
 569
 570 static inline __u8 nvme_lbaf_index(__u8 flbas)
 571 {
 572         return (flbas & NVME_NS_FLBAS_LBA_MASK) |
 573                 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
 574 }
 575
 576 /* Identify Namespace Metadata Capabilities (MC): */
 577 enum {
 578         NVME_MC_EXTENDED_LBA    = (1 << 0),
 579         NVME_MC_METADATA_PTR    = (1 << 1),
 580 };
 581
 582 struct nvme_ns_id_desc {
 583         __u8 nidt;
 584         __u8 nidl;
 585         __le16 reserved;
 586 };
 587
 588 #define NVME_NIDT_EUI64_LEN     8
 589 #define NVME_NIDT_NGUID_LEN     16
 590 #define NVME_NIDT_UUID_LEN      16
 591 #define NVME_NIDT_CSI_LEN       1
 592
 593 enum {
 594         NVME_NIDT_EUI64         = 0x01,
 595         NVME_NIDT_NGUID         = 0x02,
 596         NVME_NIDT_UUID          = 0x03,
 597         NVME_NIDT_CSI           = 0x04,
 598 };
 599
 600 struct nvme_smart_log {
 601         __u8                    critical_warning;
 602         __u8                    temperature[2];
 603         __u8                    avail_spare;
 604         __u8                    spare_thresh;
 605         __u8                    percent_used;
 606         __u8                    endu_grp_crit_warn_sumry;
 607         __u8                    rsvd7[25];
 608         __u8                    data_units_read[16];
 609         __u8                    data_units_written[16];
 610         __u8                    host_reads[16];
 611         __u8                    host_writes[16];
 612         __u8                    ctrl_busy_time[16];
 613         __u8                    power_cycles[16];
 614         __u8                    power_on_hours[16];
 615         __u8                    unsafe_shutdowns[16];
 616         __u8                    media_errors[16];
 617         __u8                    num_err_log_entries[16];
 618         __le32                  warning_temp_time;
 619         __le32                  critical_comp_time;
 620         __le16                  temp_sensor[8];
 621         __le32                  thm_temp1_trans_count;
 622         __le32                  thm_temp2_trans_count;
 623         __le32                  thm_temp1_total_time;
 624         __le32                  thm_temp2_total_time;
 625         __u8                    rsvd232[280];
 626 };
 627
 628 struct nvme_fw_slot_info_log {
 629         __u8                    afi;
 630         __u8                    rsvd1[7];
 631         __le64                  frs[7];
 632         __u8                    rsvd64[448];
 633 };
 634
 635 enum {
 636         NVME_CMD_EFFECTS_CSUPP          = 1 << 0,
 637         NVME_CMD_EFFECTS_LBCC           = 1 << 1,
 638         NVME_CMD_EFFECTS_NCC            = 1 << 2,
 639         NVME_CMD_EFFECTS_NIC            = 1 << 3,
 640         NVME_CMD_EFFECTS_CCC            = 1 << 4,
 641         NVME_CMD_EFFECTS_CSE_MASK       = 3 << 16,
 642         NVME_CMD_EFFECTS_UUID_SEL       = 1 << 19,
 643 };
 644
 645 struct nvme_effects_log {
 646         __le32 acs[256];
 647         __le32 iocs[256];
 648         __u8   resv[2048];
 649 };
 650
 651 enum nvme_ana_state {
 652         NVME_ANA_OPTIMIZED              = 0x01,
 653         NVME_ANA_NONOPTIMIZED           = 0x02,
 654         NVME_ANA_INACCESSIBLE           = 0x03,
 655         NVME_ANA_PERSISTENT_LOSS        = 0x04,
 656         NVME_ANA_CHANGE                 = 0x0f,
 657 };
 658
 659 struct nvme_ana_group_desc {
 660         __le32  grpid;
 661         __le32  nnsids;
 662         __le64  chgcnt;
 663         __u8    state;
 664         __u8    rsvd17[15];
 665         __le32  nsids[];
 666 };
 667
 668 /* flag for the log specific field of the ANA log */
 669 #define NVME_ANA_LOG_RGO        (1 << 0)
 670
 671 struct nvme_ana_rsp_hdr {
 672         __le64  chgcnt;
 673         __le16  ngrps;
 674         __le16  rsvd10[3];
 675 };
 676
 677 struct nvme_zone_descriptor {
 678         __u8            zt;
 679         __u8            zs;
 680         __u8            za;
 681         __u8            rsvd3[5];
 682         __le64          zcap;
 683         __le64          zslba;
 684         __le64          wp;
 685         __u8            rsvd32[32];
 686 };
 687
 688 enum {
 689         NVME_ZONE_TYPE_SEQWRITE_REQ     = 0x2,
 690 };
 691
 692 struct nvme_zone_report {
 693         __le64          nr_zones;
 694         __u8            resv8[56];
 695         struct nvme_zone_descriptor entries[];
 696 };
 697
 698 enum {
 699         NVME_SMART_CRIT_SPARE           = 1 << 0,
 700         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 701         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 702         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 703         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 704 };
 705
 706 enum {
 707         NVME_AER_ERROR                  = 0,
 708         NVME_AER_SMART                  = 1,
 709         NVME_AER_NOTICE                 = 2,
 710         NVME_AER_CSS                    = 6,
 711         NVME_AER_VS                     = 7,
 712 };
 713
 714 enum {
 715         NVME_AER_NOTICE_NS_CHANGED      = 0x00,
 716         NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
 717         NVME_AER_NOTICE_ANA             = 0x03,
 718         NVME_AER_NOTICE_DISC_CHANGED    = 0xf0,
 719 };
 720
 721 enum {
 722         NVME_AEN_BIT_NS_ATTR            = 8,
 723         NVME_AEN_BIT_FW_ACT             = 9,
 724         NVME_AEN_BIT_ANA_CHANGE         = 11,
 725         NVME_AEN_BIT_DISC_CHANGE        = 31,
 726 };
 727
 728 enum {
 729         NVME_AEN_CFG_NS_ATTR            = 1 << NVME_AEN_BIT_NS_ATTR,
 730         NVME_AEN_CFG_FW_ACT             = 1 << NVME_AEN_BIT_FW_ACT,
 731         NVME_AEN_CFG_ANA_CHANGE         = 1 << NVME_AEN_BIT_ANA_CHANGE,
 732         NVME_AEN_CFG_DISC_CHANGE        = 1 << NVME_AEN_BIT_DISC_CHANGE,
 733 };
 734
 735 struct nvme_lba_range_type {
 736         __u8                    type;
 737         __u8                    attributes;
 738         __u8                    rsvd2[14];
 739         __le64                  slba;
 740         __le64                  nlb;
 741         __u8                    guid[16];
 742         __u8                    rsvd48[16];
 743 };
 744
 745 enum {
 746         NVME_LBART_TYPE_FS      = 0x01,
 747         NVME_LBART_TYPE_RAID    = 0x02,
 748         NVME_LBART_TYPE_CACHE   = 0x03,
 749         NVME_LBART_TYPE_SWAP    = 0x04,
 750
 751         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 752         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 753 };
 754
 755 struct nvme_reservation_status {
 756         __le32  gen;
 757         __u8    rtype;
 758         __u8    regctl[2];
 759         __u8    resv5[2];
 760         __u8    ptpls;
 761         __u8    resv10[13];
 762         struct {
 763                 __le16  cntlid;
 764                 __u8    rcsts;
 765                 __u8    resv3[5];
 766                 __le64  hostid;
 767                 __le64  rkey;
 768         } regctl_ds[];
 769 };
 770
 771 enum nvme_async_event_type {
 772         NVME_AER_TYPE_ERROR     = 0,
 773         NVME_AER_TYPE_SMART     = 1,
 774         NVME_AER_TYPE_NOTICE    = 2,
 775 };
 776
 777 /* I/O commands */
 778
 779 enum nvme_opcode {
 780         nvme_cmd_flush          = 0x00,
 781         nvme_cmd_write          = 0x01,
 782         nvme_cmd_read           = 0x02,
 783         nvme_cmd_write_uncor    = 0x04,
 784         nvme_cmd_compare        = 0x05,
 785         nvme_cmd_write_zeroes   = 0x08,
 786         nvme_cmd_dsm            = 0x09,
 787         nvme_cmd_verify         = 0x0c,
 788         nvme_cmd_resv_register  = 0x0d,
 789         nvme_cmd_resv_report    = 0x0e,
 790         nvme_cmd_resv_acquire   = 0x11,
 791         nvme_cmd_resv_release   = 0x15,
 792         nvme_cmd_zone_mgmt_send = 0x79,
 793         nvme_cmd_zone_mgmt_recv = 0x7a,
 794         nvme_cmd_zone_append    = 0x7d,
 795 };
 796
 797 #define nvme_opcode_name(opcode)        { opcode, #opcode }
 798 #define show_nvm_opcode_name(val)                               \
 799         __print_symbolic(val,                                   \
 800                 nvme_opcode_name(nvme_cmd_flush),               \
 801                 nvme_opcode_name(nvme_cmd_write),               \
 802                 nvme_opcode_name(nvme_cmd_read),                \
 803                 nvme_opcode_name(nvme_cmd_write_uncor),         \
 804                 nvme_opcode_name(nvme_cmd_compare),             \
 805                 nvme_opcode_name(nvme_cmd_write_zeroes),        \
 806                 nvme_opcode_name(nvme_cmd_dsm),                 \
 807                 nvme_opcode_name(nvme_cmd_resv_register),       \
 808                 nvme_opcode_name(nvme_cmd_resv_report),         \
 809                 nvme_opcode_name(nvme_cmd_resv_acquire),        \
 810                 nvme_opcode_name(nvme_cmd_resv_release),        \
 811                 nvme_opcode_name(nvme_cmd_zone_mgmt_send),      \
 812                 nvme_opcode_name(nvme_cmd_zone_mgmt_recv),      \
 813                 nvme_opcode_name(nvme_cmd_zone_append))
 814
 815
 816
 817 /*
 818  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 819  *
 820  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 821  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 822  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
 823  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 824  *                            request subtype
 825  */
 826 enum {
 827         NVME_SGL_FMT_ADDRESS            = 0x00,
 828         NVME_SGL_FMT_OFFSET             = 0x01,
 829         NVME_SGL_FMT_TRANSPORT_A        = 0x0A,
 830         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 831 };
 832
 833 /*
 834  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 835  *
 836  * For struct nvme_sgl_desc:
 837  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 838  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 839  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 840  *
 841  * For struct nvme_keyed_sgl_desc:
 842  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 843  *
 844  * Transport-specific SGL types:
 845  *   @NVME_TRANSPORT_SGL_DATA_DESC:     Transport SGL data dlock descriptor
 846  */
 847 enum {
 848         NVME_SGL_FMT_DATA_DESC          = 0x00,
 849         NVME_SGL_FMT_SEG_DESC           = 0x02,
 850         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 851         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 852         NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
 853 };
 854
 855 struct nvme_sgl_desc {
 856         __le64  addr;
 857         __le32  length;
 858         __u8    rsvd[3];
 859         __u8    type;
 860 };
 861
 862 struct nvme_keyed_sgl_desc {
 863         __le64  addr;
 864         __u8    length[3];
 865         __u8    key[4];
 866         __u8    type;
 867 };
 868
 869 union nvme_data_ptr {
 870         struct {
 871                 __le64  prp1;
 872                 __le64  prp2;
 873         };
 874         struct nvme_sgl_desc    sgl;
 875         struct nvme_keyed_sgl_desc ksgl;
 876 };
 877
 878 /*
 879  * Lowest two bits of our flags field (FUSE field in the spec):
 880  *
 881  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 882  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 883  *
 884  * Highest two bits in our flags field (PSDT field in the spec):
 885  *
 886  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 887  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 888  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 889  *      If used, MPTR contains an address of an SGL segment containing
 890  *      exactly 1 SGL descriptor (qword aligned).
 891  */
 892 enum {
 893         NVME_CMD_FUSE_FIRST     = (1 << 0),
 894         NVME_CMD_FUSE_SECOND    = (1 << 1),
 895
 896         NVME_CMD_SGL_METABUF    = (1 << 6),
 897         NVME_CMD_SGL_METASEG    = (1 << 7),
 898         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 899 };
 900
 901 struct nvme_common_command {
 902         __u8                    opcode;
 903         __u8                    flags;
 904         __u16                   command_id;
 905         __le32                  nsid;
 906         __le32                  cdw2[2];
 907         __le64                  metadata;
 908         union nvme_data_ptr     dptr;
 909         struct_group(cdws,
 910         __le32                  cdw10;
 911         __le32                  cdw11;
 912         __le32                  cdw12;
 913         __le32                  cdw13;
 914         __le32                  cdw14;
 915         __le32                  cdw15;
 916         );
 917 };
 918
 919 struct nvme_rw_command {
 920         __u8                    opcode;
 921         __u8                    flags;
 922         __u16                   command_id;
 923         __le32                  nsid;
 924         __le32                  cdw2;
 925         __le32                  cdw3;
 926         __le64                  metadata;
 927         union nvme_data_ptr     dptr;
 928         __le64                  slba;
 929         __le16                  length;
 930         __le16                  control;
 931         __le32                  dsmgmt;
 932         __le32                  reftag;
 933         __le16                  apptag;
 934         __le16                  appmask;
 935 };
 936
 937 enum {
 938         NVME_RW_LR                      = 1 << 15,
 939         NVME_RW_FUA                     = 1 << 14,
 940         NVME_RW_APPEND_PIREMAP          = 1 << 9,
 941         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 942         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 943         NVME_RW_DSM_FREQ_RARE           = 2,
 944         NVME_RW_DSM_FREQ_READS          = 3,
 945         NVME_RW_DSM_FREQ_WRITES         = 4,
 946         NVME_RW_DSM_FREQ_RW             = 5,
 947         NVME_RW_DSM_FREQ_ONCE           = 6,
 948         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 949         NVME_RW_DSM_FREQ_TEMP           = 8,
 950         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 951         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 952         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 953         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 954         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 955         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 956         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
 957         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
 958         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
 959         NVME_RW_PRINFO_PRACT            = 1 << 13,
 960         NVME_RW_DTYPE_STREAMS           = 1 << 4,
 961 };
 962
 963 struct nvme_dsm_cmd {
 964         __u8                    opcode;
 965         __u8                    flags;
 966         __u16                   command_id;
 967         __le32                  nsid;
 968         __u64                   rsvd2[2];
 969         union nvme_data_ptr     dptr;
 970         __le32                  nr;
 971         __le32                  attributes;
 972         __u32                   rsvd12[4];
 973 };
 974
 975 enum {
 976         NVME_DSMGMT_IDR         = 1 << 0,
 977         NVME_DSMGMT_IDW         = 1 << 1,
 978         NVME_DSMGMT_AD          = 1 << 2,
 979 };
 980
 981 #define NVME_DSM_MAX_RANGES     256
 982
 983 struct nvme_dsm_range {
 984         __le32                  cattr;
 985         __le32                  nlb;
 986         __le64                  slba;
 987 };
 988
 989 struct nvme_write_zeroes_cmd {
 990         __u8                    opcode;
 991         __u8                    flags;
 992         __u16                   command_id;
 993         __le32                  nsid;
 994         __u64                   rsvd2;
 995         __le64                  metadata;
 996         union nvme_data_ptr     dptr;
 997         __le64                  slba;
 998         __le16                  length;
 999         __le16                  control;
1000         __le32                  dsmgmt;
1001         __le32                  reftag;
1002         __le16                  apptag;
1003         __le16                  appmask;
1004 };
1005
1006 enum nvme_zone_mgmt_action {
1007         NVME_ZONE_CLOSE         = 0x1,
1008         NVME_ZONE_FINISH        = 0x2,
1009         NVME_ZONE_OPEN          = 0x3,
1010         NVME_ZONE_RESET         = 0x4,
1011         NVME_ZONE_OFFLINE       = 0x5,
1012         NVME_ZONE_SET_DESC_EXT  = 0x10,
1013 };
1014
1015 struct nvme_zone_mgmt_send_cmd {
1016         __u8                    opcode;
1017         __u8                    flags;
1018         __u16                   command_id;
1019         __le32                  nsid;
1020         __le32                  cdw2[2];
1021         __le64                  metadata;
1022         union nvme_data_ptr     dptr;
1023         __le64                  slba;
1024         __le32                  cdw12;
1025         __u8                    zsa;
1026         __u8                    select_all;
1027         __u8                    rsvd13[2];
1028         __le32                  cdw14[2];
1029 };
1030
1031 struct nvme_zone_mgmt_recv_cmd {
1032         __u8                    opcode;
1033         __u8                    flags;
1034         __u16                   command_id;
1035         __le32                  nsid;
1036         __le64                  rsvd2[2];
1037         union nvme_data_ptr     dptr;
1038         __le64                  slba;
1039         __le32                  numd;
1040         __u8                    zra;
1041         __u8                    zrasf;
1042         __u8                    pr;
1043         __u8                    rsvd13;
1044         __le32                  cdw14[2];
1045 };
1046
1047 enum {
1048         NVME_ZRA_ZONE_REPORT            = 0,
1049         NVME_ZRASF_ZONE_REPORT_ALL      = 0,
1050         NVME_ZRASF_ZONE_STATE_EMPTY     = 0x01,
1051         NVME_ZRASF_ZONE_STATE_IMP_OPEN  = 0x02,
1052         NVME_ZRASF_ZONE_STATE_EXP_OPEN  = 0x03,
1053         NVME_ZRASF_ZONE_STATE_CLOSED    = 0x04,
1054         NVME_ZRASF_ZONE_STATE_READONLY  = 0x05,
1055         NVME_ZRASF_ZONE_STATE_FULL      = 0x06,
1056         NVME_ZRASF_ZONE_STATE_OFFLINE   = 0x07,
1057         NVME_REPORT_ZONE_PARTIAL        = 1,
1058 };
1059
1060 /* Features */
1061
1062 enum {
1063         NVME_TEMP_THRESH_MASK           = 0xffff,
1064         NVME_TEMP_THRESH_SELECT_SHIFT   = 16,
1065         NVME_TEMP_THRESH_TYPE_UNDER     = 0x100000,
1066 };
1067
1068 struct nvme_feat_auto_pst {
1069         __le64 entries[32];
1070 };
1071
1072 enum {
1073         NVME_HOST_MEM_ENABLE    = (1 << 0),
1074         NVME_HOST_MEM_RETURN    = (1 << 1),
1075 };
1076
1077 struct nvme_feat_host_behavior {
1078         __u8 acre;
1079         __u8 etdas;
1080         __u8 lbafee;
1081         __u8 resv1[509];
1082 };
1083
1084 enum {
1085         NVME_ENABLE_ACRE        = 1,
1086         NVME_ENABLE_LBAFEE      = 1,
1087 };
1088
1089 /* Admin commands */
1090
1091 enum nvme_admin_opcode {
1092         nvme_admin_delete_sq            = 0x00,
1093         nvme_admin_create_sq            = 0x01,
1094         nvme_admin_get_log_page         = 0x02,
1095         nvme_admin_delete_cq            = 0x04,
1096         nvme_admin_create_cq            = 0x05,
1097         nvme_admin_identify             = 0x06,
1098         nvme_admin_abort_cmd            = 0x08,
1099         nvme_admin_set_features         = 0x09,
1100         nvme_admin_get_features         = 0x0a,
1101         nvme_admin_async_event          = 0x0c,
1102         nvme_admin_ns_mgmt              = 0x0d,
1103         nvme_admin_activate_fw          = 0x10,
1104         nvme_admin_download_fw          = 0x11,
1105         nvme_admin_dev_self_test        = 0x14,
1106         nvme_admin_ns_attach            = 0x15,
1107         nvme_admin_keep_alive           = 0x18,
1108         nvme_admin_directive_send       = 0x19,
1109         nvme_admin_directive_recv       = 0x1a,
1110         nvme_admin_virtual_mgmt         = 0x1c,
1111         nvme_admin_nvme_mi_send         = 0x1d,
1112         nvme_admin_nvme_mi_recv         = 0x1e,
1113         nvme_admin_dbbuf                = 0x7C,
1114         nvme_admin_format_nvm           = 0x80,
1115         nvme_admin_security_send        = 0x81,
1116         nvme_admin_security_recv        = 0x82,
1117         nvme_admin_sanitize_nvm         = 0x84,
1118         nvme_admin_get_lba_status       = 0x86,
1119         nvme_admin_vendor_start         = 0xC0,
1120 };
1121
1122 #define nvme_admin_opcode_name(opcode)  { opcode, #opcode }
1123 #define show_admin_opcode_name(val)                                     \
1124         __print_symbolic(val,                                           \
1125                 nvme_admin_opcode_name(nvme_admin_delete_sq),           \
1126                 nvme_admin_opcode_name(nvme_admin_create_sq),           \
1127                 nvme_admin_opcode_name(nvme_admin_get_log_page),        \
1128                 nvme_admin_opcode_name(nvme_admin_delete_cq),           \
1129                 nvme_admin_opcode_name(nvme_admin_create_cq),           \
1130                 nvme_admin_opcode_name(nvme_admin_identify),            \
1131                 nvme_admin_opcode_name(nvme_admin_abort_cmd),           \
1132                 nvme_admin_opcode_name(nvme_admin_set_features),        \
1133                 nvme_admin_opcode_name(nvme_admin_get_features),        \
1134                 nvme_admin_opcode_name(nvme_admin_async_event),         \
1135                 nvme_admin_opcode_name(nvme_admin_ns_mgmt),             \
1136                 nvme_admin_opcode_name(nvme_admin_activate_fw),         \
1137                 nvme_admin_opcode_name(nvme_admin_download_fw),         \
1138                 nvme_admin_opcode_name(nvme_admin_ns_attach),           \
1139                 nvme_admin_opcode_name(nvme_admin_keep_alive),          \
1140                 nvme_admin_opcode_name(nvme_admin_directive_send),      \
1141                 nvme_admin_opcode_name(nvme_admin_directive_recv),      \
1142                 nvme_admin_opcode_name(nvme_admin_dbbuf),               \
1143                 nvme_admin_opcode_name(nvme_admin_format_nvm),          \
1144                 nvme_admin_opcode_name(nvme_admin_security_send),       \
1145                 nvme_admin_opcode_name(nvme_admin_security_recv),       \
1146                 nvme_admin_opcode_name(nvme_admin_sanitize_nvm),        \
1147                 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1148
1149 enum {
1150         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
1151         NVME_CQ_IRQ_ENABLED     = (1 << 1),
1152         NVME_SQ_PRIO_URGENT     = (0 << 1),
1153         NVME_SQ_PRIO_HIGH       = (1 << 1),
1154         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
1155         NVME_SQ_PRIO_LOW        = (3 << 1),
1156         NVME_FEAT_ARBITRATION   = 0x01,
1157         NVME_FEAT_POWER_MGMT    = 0x02,
1158         NVME_FEAT_LBA_RANGE     = 0x03,
1159         NVME_FEAT_TEMP_THRESH   = 0x04,
1160         NVME_FEAT_ERR_RECOVERY  = 0x05,
1161         NVME_FEAT_VOLATILE_WC   = 0x06,
1162         NVME_FEAT_NUM_QUEUES    = 0x07,
1163         NVME_FEAT_IRQ_COALESCE  = 0x08,
1164         NVME_FEAT_IRQ_CONFIG    = 0x09,
1165         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
1166         NVME_FEAT_ASYNC_EVENT   = 0x0b,
1167         NVME_FEAT_AUTO_PST      = 0x0c,
1168         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
1169         NVME_FEAT_TIMESTAMP     = 0x0e,
1170         NVME_FEAT_KATO          = 0x0f,
1171         NVME_FEAT_HCTM          = 0x10,
1172         NVME_FEAT_NOPSC         = 0x11,
1173         NVME_FEAT_RRL           = 0x12,
1174         NVME_FEAT_PLM_CONFIG    = 0x13,
1175         NVME_FEAT_PLM_WINDOW    = 0x14,
1176         NVME_FEAT_HOST_BEHAVIOR = 0x16,
1177         NVME_FEAT_SANITIZE      = 0x17,
1178         NVME_FEAT_SW_PROGRESS   = 0x80,
1179         NVME_FEAT_HOST_ID       = 0x81,
1180         NVME_FEAT_RESV_MASK     = 0x82,
1181         NVME_FEAT_RESV_PERSIST  = 0x83,
1182         NVME_FEAT_WRITE_PROTECT = 0x84,
1183         NVME_FEAT_VENDOR_START  = 0xC0,
1184         NVME_FEAT_VENDOR_END    = 0xFF,
1185         NVME_LOG_ERROR          = 0x01,
1186         NVME_LOG_SMART          = 0x02,
1187         NVME_LOG_FW_SLOT        = 0x03,
1188         NVME_LOG_CHANGED_NS     = 0x04,
1189         NVME_LOG_CMD_EFFECTS    = 0x05,
1190         NVME_LOG_DEVICE_SELF_TEST = 0x06,
1191         NVME_LOG_TELEMETRY_HOST = 0x07,
1192         NVME_LOG_TELEMETRY_CTRL = 0x08,
1193         NVME_LOG_ENDURANCE_GROUP = 0x09,
1194         NVME_LOG_ANA            = 0x0c,
1195         NVME_LOG_DISC           = 0x70,
1196         NVME_LOG_RESERVATION    = 0x80,
1197         NVME_FWACT_REPL         = (0 << 3),
1198         NVME_FWACT_REPL_ACTV    = (1 << 3),
1199         NVME_FWACT_ACTV         = (2 << 3),
1200 };
1201
1202 /* NVMe Namespace Write Protect State */
1203 enum {
1204         NVME_NS_NO_WRITE_PROTECT = 0,
1205         NVME_NS_WRITE_PROTECT,
1206         NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1207         NVME_NS_WRITE_PROTECT_PERMANENT,
1208 };
1209
1210 #define NVME_MAX_CHANGED_NAMESPACES     1024
1211
1212 struct nvme_identify {
1213         __u8                    opcode;
1214         __u8                    flags;
1215         __u16                   command_id;
1216         __le32                  nsid;
1217         __u64                   rsvd2[2];
1218         union nvme_data_ptr     dptr;
1219         __u8                    cns;
1220         __u8                    rsvd3;
1221         __le16                  ctrlid;
1222         __u8                    rsvd11[3];
1223         __u8                    csi;
1224         __u32                   rsvd12[4];
1225 };
1226
1227 #define NVME_IDENTIFY_DATA_SIZE 4096
1228
1229 struct nvme_features {
1230         __u8                    opcode;
1231         __u8                    flags;
1232         __u16                   command_id;
1233         __le32                  nsid;
1234         __u64                   rsvd2[2];
1235         union nvme_data_ptr     dptr;
1236         __le32                  fid;
1237         __le32                  dword11;
1238         __le32                  dword12;
1239         __le32                  dword13;
1240         __le32                  dword14;
1241         __le32                  dword15;
1242 };
1243
1244 struct nvme_host_mem_buf_desc {
1245         __le64                  addr;
1246         __le32                  size;
1247         __u32                   rsvd;
1248 };
1249
1250 struct nvme_create_cq {
1251         __u8                    opcode;
1252         __u8                    flags;
1253         __u16                   command_id;
1254         __u32                   rsvd1[5];
1255         __le64                  prp1;
1256         __u64                   rsvd8;
1257         __le16                  cqid;
1258         __le16                  qsize;
1259         __le16                  cq_flags;
1260         __le16                  irq_vector;
1261         __u32                   rsvd12[4];
1262 };
1263
1264 struct nvme_create_sq {
1265         __u8                    opcode;
1266         __u8                    flags;
1267         __u16                   command_id;
1268         __u32                   rsvd1[5];
1269         __le64                  prp1;
1270         __u64                   rsvd8;
1271         __le16                  sqid;
1272         __le16                  qsize;
1273         __le16                  sq_flags;
1274         __le16                  cqid;
1275         __u32                   rsvd12[4];
1276 };
1277
1278 struct nvme_delete_queue {
1279         __u8                    opcode;
1280         __u8                    flags;
1281         __u16                   command_id;
1282         __u32                   rsvd1[9];
1283         __le16                  qid;
1284         __u16                   rsvd10;
1285         __u32                   rsvd11[5];
1286 };
1287
1288 struct nvme_abort_cmd {
1289         __u8                    opcode;
1290         __u8                    flags;
1291         __u16                   command_id;
1292         __u32                   rsvd1[9];
1293         __le16                  sqid;
1294         __u16                   cid;
1295         __u32                   rsvd11[5];
1296 };
1297
1298 struct nvme_download_firmware {
1299         __u8                    opcode;
1300         __u8                    flags;
1301         __u16                   command_id;
1302         __u32                   rsvd1[5];
1303         union nvme_data_ptr     dptr;
1304         __le32                  numd;
1305         __le32                  offset;
1306         __u32                   rsvd12[4];
1307 };
1308
1309 struct nvme_format_cmd {
1310         __u8                    opcode;
1311         __u8                    flags;
1312         __u16                   command_id;
1313         __le32                  nsid;
1314         __u64                   rsvd2[4];
1315         __le32                  cdw10;
1316         __u32                   rsvd11[5];
1317 };
1318
1319 struct nvme_get_log_page_command {
1320         __u8                    opcode;
1321         __u8                    flags;
1322         __u16                   command_id;
1323         __le32                  nsid;
1324         __u64                   rsvd2[2];
1325         union nvme_data_ptr     dptr;
1326         __u8                    lid;
1327         __u8                    lsp; /* upper 4 bits reserved */
1328         __le16                  numdl;
1329         __le16                  numdu;
1330         __u16                   rsvd11;
1331         union {
1332                 struct {
1333                         __le32 lpol;
1334                         __le32 lpou;
1335                 };
1336                 __le64 lpo;
1337         };
1338         __u8                    rsvd14[3];
1339         __u8                    csi;
1340         __u32                   rsvd15;
1341 };
1342
1343 struct nvme_directive_cmd {
1344         __u8                    opcode;
1345         __u8                    flags;
1346         __u16                   command_id;
1347         __le32                  nsid;
1348         __u64                   rsvd2[2];
1349         union nvme_data_ptr     dptr;
1350         __le32                  numd;
1351         __u8                    doper;
1352         __u8                    dtype;
1353         __le16                  dspec;
1354         __u8                    endir;
1355         __u8                    tdtype;
1356         __u16                   rsvd15;
1357
1358         __u32                   rsvd16[3];
1359 };
1360
1361 /*
1362  * Fabrics subcommands.
1363  */
1364 enum nvmf_fabrics_opcode {
1365         nvme_fabrics_command            = 0x7f,
1366 };
1367
1368 enum nvmf_capsule_command {
1369         nvme_fabrics_type_property_set  = 0x00,
1370         nvme_fabrics_type_connect       = 0x01,
1371         nvme_fabrics_type_property_get  = 0x04,
1372 };
1373
1374 #define nvme_fabrics_type_name(type)   { type, #type }
1375 #define show_fabrics_type_name(type)                                    \
1376         __print_symbolic(type,                                          \
1377                 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1378                 nvme_fabrics_type_name(nvme_fabrics_type_connect),      \
1379                 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1380
1381 /*
1382  * If not fabrics command, fctype will be ignored.
1383  */
1384 #define show_opcode_name(qid, opcode, fctype)                   \
1385         ((opcode) == nvme_fabrics_command ?                     \
1386          show_fabrics_type_name(fctype) :                       \
1387         ((qid) ?                                                \
1388          show_nvm_opcode_name(opcode) :                         \
1389          show_admin_opcode_name(opcode)))
1390
1391 struct nvmf_common_command {
1392         __u8    opcode;
1393         __u8    resv1;
1394         __u16   command_id;
1395         __u8    fctype;
1396         __u8    resv2[35];
1397         __u8    ts[24];
1398 };
1399
1400 /*
1401  * The legal cntlid range a NVMe Target will provide.
1402  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1403  * Devices based on earlier specs did not have the subsystem concept;
1404  * therefore, those devices had their cntlid value set to 0 as a result.
1405  */
1406 #define NVME_CNTLID_MIN         1
1407 #define NVME_CNTLID_MAX         0xffef
1408 #define NVME_CNTLID_DYNAMIC     0xffff
1409
1410 #define MAX_DISC_LOGS   255
1411
1412 /* Discovery log page entry flags (EFLAGS): */
1413 enum {
1414         NVME_DISC_EFLAGS_EPCSD          = (1 << 1),
1415         NVME_DISC_EFLAGS_DUPRETINFO     = (1 << 0),
1416 };
1417
1418 /* Discovery log page entry */
1419 struct nvmf_disc_rsp_page_entry {
1420         __u8            trtype;
1421         __u8            adrfam;
1422         __u8            subtype;
1423         __u8            treq;
1424         __le16          portid;
1425         __le16          cntlid;
1426         __le16          asqsz;
1427         __le16          eflags;
1428         __u8            resv10[20];
1429         char            trsvcid[NVMF_TRSVCID_SIZE];
1430         __u8            resv64[192];
1431         char            subnqn[NVMF_NQN_FIELD_LEN];
1432         char            traddr[NVMF_TRADDR_SIZE];
1433         union tsas {
1434                 char            common[NVMF_TSAS_SIZE];
1435                 struct rdma {
1436                         __u8    qptype;
1437                         __u8    prtype;
1438                         __u8    cms;
1439                         __u8    resv3[5];
1440                         __u16   pkey;
1441                         __u8    resv10[246];
1442                 } rdma;
1443         } tsas;
1444 };
1445
1446 /* Discovery log page header */
1447 struct nvmf_disc_rsp_page_hdr {
1448         __le64          genctr;
1449         __le64          numrec;
1450         __le16          recfmt;
1451         __u8            resv14[1006];
1452         struct nvmf_disc_rsp_page_entry entries[];
1453 };
1454
1455 enum {
1456         NVME_CONNECT_DISABLE_SQFLOW     = (1 << 2),
1457 };
1458
1459 struct nvmf_connect_command {
1460         __u8            opcode;
1461         __u8            resv1;
1462         __u16           command_id;
1463         __u8            fctype;
1464         __u8            resv2[19];
1465         union nvme_data_ptr dptr;
1466         __le16          recfmt;
1467         __le16          qid;
1468         __le16          sqsize;
1469         __u8            cattr;
1470         __u8            resv3;
1471         __le32          kato;
1472         __u8            resv4[12];
1473 };
1474
1475 struct nvmf_connect_data {
1476         uuid_t          hostid;
1477         __le16          cntlid;
1478         char            resv4[238];
1479         char            subsysnqn[NVMF_NQN_FIELD_LEN];
1480         char            hostnqn[NVMF_NQN_FIELD_LEN];
1481         char            resv5[256];
1482 };
1483
1484 struct nvmf_property_set_command {
1485         __u8            opcode;
1486         __u8            resv1;
1487         __u16           command_id;
1488         __u8            fctype;
1489         __u8            resv2[35];
1490         __u8            attrib;
1491         __u8            resv3[3];
1492         __le32          offset;
1493         __le64          value;
1494         __u8            resv4[8];
1495 };
1496
1497 struct nvmf_property_get_command {
1498         __u8            opcode;
1499         __u8            resv1;
1500         __u16           command_id;
1501         __u8            fctype;
1502         __u8            resv2[35];
1503         __u8            attrib;
1504         __u8            resv3[3];
1505         __le32          offset;
1506         __u8            resv4[16];
1507 };
1508
1509 struct nvme_dbbuf {
1510         __u8                    opcode;
1511         __u8                    flags;
1512         __u16                   command_id;
1513         __u32                   rsvd1[5];
1514         __le64                  prp1;
1515         __le64                  prp2;
1516         __u32                   rsvd12[6];
1517 };
1518
1519 struct streams_directive_params {
1520         __le16  msl;
1521         __le16  nssa;
1522         __le16  nsso;
1523         __u8    rsvd[10];
1524         __le32  sws;
1525         __le16  sgs;
1526         __le16  nsa;
1527         __le16  nso;
1528         __u8    rsvd2[6];
1529 };
1530
1531 struct nvme_command {
1532         union {
1533                 struct nvme_common_command common;
1534                 struct nvme_rw_command rw;
1535                 struct nvme_identify identify;
1536                 struct nvme_features features;
1537                 struct nvme_create_cq create_cq;
1538                 struct nvme_create_sq create_sq;
1539                 struct nvme_delete_queue delete_queue;
1540                 struct nvme_download_firmware dlfw;
1541                 struct nvme_format_cmd format;
1542                 struct nvme_dsm_cmd dsm;
1543                 struct nvme_write_zeroes_cmd write_zeroes;
1544                 struct nvme_zone_mgmt_send_cmd zms;
1545                 struct nvme_zone_mgmt_recv_cmd zmr;
1546                 struct nvme_abort_cmd abort;
1547                 struct nvme_get_log_page_command get_log_page;
1548                 struct nvmf_common_command fabrics;
1549                 struct nvmf_connect_command connect;
1550                 struct nvmf_property_set_command prop_set;
1551                 struct nvmf_property_get_command prop_get;
1552                 struct nvme_dbbuf dbbuf;
1553                 struct nvme_directive_cmd directive;
1554         };
1555 };
1556
1557 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1558 {
1559         return cmd->common.opcode == nvme_fabrics_command;
1560 }
1561
1562 struct nvme_error_slot {
1563         __le64          error_count;
1564         __le16          sqid;
1565         __le16          cmdid;
1566         __le16          status_field;
1567         __le16          param_error_location;
1568         __le64          lba;
1569         __le32          nsid;
1570         __u8            vs;
1571         __u8            resv[3];
1572         __le64          cs;
1573         __u8            resv2[24];
1574 };
1575
1576 static inline bool nvme_is_write(struct nvme_command *cmd)
1577 {
1578         /*
1579          * What a mess...
1580          *
1581          * Why can't we simply have a Fabrics In and Fabrics out command?
1582          */
1583         if (unlikely(nvme_is_fabrics(cmd)))
1584                 return cmd->fabrics.fctype & 1;
1585         return cmd->common.opcode & 1;
1586 }
1587
1588 enum {
1589         /*
1590          * Generic Command Status:
1591          */
1592         NVME_SC_SUCCESS                 = 0x0,
1593         NVME_SC_INVALID_OPCODE          = 0x1,
1594         NVME_SC_INVALID_FIELD           = 0x2,
1595         NVME_SC_CMDID_CONFLICT          = 0x3,
1596         NVME_SC_DATA_XFER_ERROR         = 0x4,
1597         NVME_SC_POWER_LOSS              = 0x5,
1598         NVME_SC_INTERNAL                = 0x6,
1599         NVME_SC_ABORT_REQ               = 0x7,
1600         NVME_SC_ABORT_QUEUE             = 0x8,
1601         NVME_SC_FUSED_FAIL              = 0x9,
1602         NVME_SC_FUSED_MISSING           = 0xa,
1603         NVME_SC_INVALID_NS              = 0xb,
1604         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1605         NVME_SC_SGL_INVALID_LAST        = 0xd,
1606         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1607         NVME_SC_SGL_INVALID_DATA        = 0xf,
1608         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1609         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1610         NVME_SC_CMB_INVALID_USE         = 0x12,
1611         NVME_SC_PRP_INVALID_OFFSET      = 0x13,
1612         NVME_SC_ATOMIC_WU_EXCEEDED      = 0x14,
1613         NVME_SC_OP_DENIED               = 0x15,
1614         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1615         NVME_SC_RESERVED                = 0x17,
1616         NVME_SC_HOST_ID_INCONSIST       = 0x18,
1617         NVME_SC_KA_TIMEOUT_EXPIRED      = 0x19,
1618         NVME_SC_KA_TIMEOUT_INVALID      = 0x1A,
1619         NVME_SC_ABORTED_PREEMPT_ABORT   = 0x1B,
1620         NVME_SC_SANITIZE_FAILED         = 0x1C,
1621         NVME_SC_SANITIZE_IN_PROGRESS    = 0x1D,
1622         NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1623         NVME_SC_CMD_NOT_SUP_CMB_QUEUE   = 0x1F,
1624         NVME_SC_NS_WRITE_PROTECTED      = 0x20,
1625         NVME_SC_CMD_INTERRUPTED         = 0x21,
1626         NVME_SC_TRANSIENT_TR_ERR        = 0x22,
1627         NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
1628         NVME_SC_INVALID_IO_CMD_SET      = 0x2C,
1629
1630         NVME_SC_LBA_RANGE               = 0x80,
1631         NVME_SC_CAP_EXCEEDED            = 0x81,
1632         NVME_SC_NS_NOT_READY            = 0x82,
1633         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1634         NVME_SC_FORMAT_IN_PROGRESS      = 0x84,
1635
1636         /*
1637          * Command Specific Status:
1638          */
1639         NVME_SC_CQ_INVALID              = 0x100,
1640         NVME_SC_QID_INVALID             = 0x101,
1641         NVME_SC_QUEUE_SIZE              = 0x102,
1642         NVME_SC_ABORT_LIMIT             = 0x103,
1643         NVME_SC_ABORT_MISSING           = 0x104,
1644         NVME_SC_ASYNC_LIMIT             = 0x105,
1645         NVME_SC_FIRMWARE_SLOT           = 0x106,
1646         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1647         NVME_SC_INVALID_VECTOR          = 0x108,
1648         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1649         NVME_SC_INVALID_FORMAT          = 0x10a,
1650         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1651         NVME_SC_INVALID_QUEUE           = 0x10c,
1652         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1653         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1654         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1655         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1656         NVME_SC_FW_NEEDS_RESET          = 0x111,
1657         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1658         NVME_SC_FW_ACTIVATE_PROHIBITED  = 0x113,
1659         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1660         NVME_SC_NS_INSUFFICIENT_CAP     = 0x115,
1661         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1662         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1663         NVME_SC_NS_IS_PRIVATE           = 0x119,
1664         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1665         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1666         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1667         NVME_SC_SELT_TEST_IN_PROGRESS   = 0x11d,
1668         NVME_SC_BP_WRITE_PROHIBITED     = 0x11e,
1669         NVME_SC_CTRL_ID_INVALID         = 0x11f,
1670         NVME_SC_SEC_CTRL_STATE_INVALID  = 0x120,
1671         NVME_SC_CTRL_RES_NUM_INVALID    = 0x121,
1672         NVME_SC_RES_ID_INVALID          = 0x122,
1673         NVME_SC_PMR_SAN_PROHIBITED      = 0x123,
1674         NVME_SC_ANA_GROUP_ID_INVALID    = 0x124,
1675         NVME_SC_ANA_ATTACH_FAILED       = 0x125,
1676
1677         /*
1678          * I/O Command Set Specific - NVM commands:
1679          */
1680         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1681         NVME_SC_INVALID_PI              = 0x181,
1682         NVME_SC_READ_ONLY               = 0x182,
1683         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1684
1685         /*
1686          * I/O Command Set Specific - Fabrics commands:
1687          */
1688         NVME_SC_CONNECT_FORMAT          = 0x180,
1689         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1690         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1691         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1692         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1693
1694         NVME_SC_DISCOVERY_RESTART       = 0x190,
1695         NVME_SC_AUTH_REQUIRED           = 0x191,
1696
1697         /*
1698          * I/O Command Set Specific - Zoned commands:
1699          */
1700         NVME_SC_ZONE_BOUNDARY_ERROR     = 0x1b8,
1701         NVME_SC_ZONE_FULL               = 0x1b9,
1702         NVME_SC_ZONE_READ_ONLY          = 0x1ba,
1703         NVME_SC_ZONE_OFFLINE            = 0x1bb,
1704         NVME_SC_ZONE_INVALID_WRITE      = 0x1bc,
1705         NVME_SC_ZONE_TOO_MANY_ACTIVE    = 0x1bd,
1706         NVME_SC_ZONE_TOO_MANY_OPEN      = 0x1be,
1707         NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1708
1709         /*
1710          * Media and Data Integrity Errors:
1711          */
1712         NVME_SC_WRITE_FAULT             = 0x280,
1713         NVME_SC_READ_ERROR              = 0x281,
1714         NVME_SC_GUARD_CHECK             = 0x282,
1715         NVME_SC_APPTAG_CHECK            = 0x283,
1716         NVME_SC_REFTAG_CHECK            = 0x284,
1717         NVME_SC_COMPARE_FAILED          = 0x285,
1718         NVME_SC_ACCESS_DENIED           = 0x286,
1719         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1720
1721         /*
1722          * Path-related Errors:
1723          */
1724         NVME_SC_INTERNAL_PATH_ERROR     = 0x300,
1725         NVME_SC_ANA_PERSISTENT_LOSS     = 0x301,
1726         NVME_SC_ANA_INACCESSIBLE        = 0x302,
1727         NVME_SC_ANA_TRANSITION          = 0x303,
1728         NVME_SC_CTRL_PATH_ERROR         = 0x360,
1729         NVME_SC_HOST_PATH_ERROR         = 0x370,
1730         NVME_SC_HOST_ABORTED_CMD        = 0x371,
1731
1732         NVME_SC_CRD                     = 0x1800,
1733         NVME_SC_MORE                    = 0x2000,
1734         NVME_SC_DNR                     = 0x4000,
1735 };
1736
1737 struct nvme_completion {
1738         /*
1739          * Used by Admin and Fabrics commands to return data:
1740          */
1741         union nvme_result {
1742                 __le16  u16;
1743                 __le32  u32;
1744                 __le64  u64;
1745         } result;
1746         __le16  sq_head;        /* how much of this queue may be reclaimed */
1747         __le16  sq_id;          /* submission queue that generated this entry */
1748         __u16   command_id;     /* of the command which completed */
1749         __le16  status;         /* did the command fail, and if so, why? */
1750 };
1751
1752 #define NVME_VS(major, minor, tertiary) \
1753         (((major) << 16) | ((minor) << 8) | (tertiary))
1754
1755 #define NVME_MAJOR(ver)         ((ver) >> 16)
1756 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
1757 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
1758
1759 #endif /* _LINUX_NVME_H */