include/linux/nvme.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Definitions for the NVM Express interface
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #ifndef _LINUX_NVME_H
   8 #define _LINUX_NVME_H
   9
  10 #include <linux/types.h>
  11 #include <linux/uuid.h>
  12
  13 /* NQN names in commands fields specified one size */
  14 #define NVMF_NQN_FIELD_LEN      256
  15
  16 /* However the max length of a qualified name is another size */
  17 #define NVMF_NQN_SIZE           223
  18
  19 #define NVMF_TRSVCID_SIZE       32
  20 #define NVMF_TRADDR_SIZE        256
  21 #define NVMF_TSAS_SIZE          256
  22
  23 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  24
  25 #define NVME_RDMA_IP_PORT       4420
  26
  27 #define NVME_NSID_ALL           0xffffffff
  28
  29 enum nvme_subsys_type {
  30         /* Referral to another discovery type target subsystem */
  31         NVME_NQN_DISC   = 1,
  32
  33         /* NVME type target subsystem */
  34         NVME_NQN_NVME   = 2,
  35
  36         /* Current discovery type target subsystem */
  37         NVME_NQN_CURR   = 3,
  38 };
  39
  40 enum nvme_ctrl_type {
  41         NVME_CTRL_IO    = 1,            /* I/O controller */
  42         NVME_CTRL_DISC  = 2,            /* Discovery controller */
  43         NVME_CTRL_ADMIN = 3,            /* Administrative controller */
  44 };
  45
  46 enum nvme_dctype {
  47         NVME_DCTYPE_NOT_REPORTED        = 0,
  48         NVME_DCTYPE_DDC                 = 1, /* Direct Discovery Controller */
  49         NVME_DCTYPE_CDC                 = 2, /* Central Discovery Controller */
  50 };
  51
  52 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  53 enum {
  54         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  55         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  56         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  57         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  58         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  59         NVMF_ADDR_FAMILY_LOOP   = 254,  /* Reserved for host usage */
  60         NVMF_ADDR_FAMILY_MAX,
  61 };
  62
  63 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  64 enum {
  65         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  66         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  67         NVMF_TRTYPE_TCP         = 3,    /* TCP/IP */
  68         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  69         NVMF_TRTYPE_MAX,
  70 };
  71
  72 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  73 enum {
  74         NVMF_TREQ_NOT_SPECIFIED = 0,            /* Not specified */
  75         NVMF_TREQ_REQUIRED      = 1,            /* Required */
  76         NVMF_TREQ_NOT_REQUIRED  = 2,            /* Not Required */
  77 #define NVME_TREQ_SECURE_CHANNEL_MASK \
  78         (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
  79
  80         NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),    /* Supports SQ flow control disable */
  81 };
  82
  83 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  84  * RDMA_QPTYPE field
  85  */
  86 enum {
  87         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
  88         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
  89 };
  90
  91 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  92  * RDMA_QPTYPE field
  93  */
  94 enum {
  95         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
  96         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
  97         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
  98         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
  99         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
 100 };
 101
 102 /* RDMA Connection Management Service Type codes for Discovery Log Page
 103  * entry TSAS RDMA_CMS field
 104  */
 105 enum {
 106         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
 107 };
 108
 109 #define NVME_AQ_DEPTH           32
 110 #define NVME_NR_AEN_COMMANDS    1
 111 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
 112
 113 /*
 114  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
 115  * NVM-Express 1.2 specification, section 4.1.2.
 116  */
 117 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
 118
 119 enum {
 120         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
 121         NVME_REG_VS     = 0x0008,       /* Version */
 122         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
 123         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
 124         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
 125         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
 126         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
 127         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 128         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 129         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 130         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 131         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 132         NVME_REG_BPINFO = 0x0040,       /* Boot Partition Information */
 133         NVME_REG_BPRSEL = 0x0044,       /* Boot Partition Read Select */
 134         NVME_REG_BPMBL  = 0x0048,       /* Boot Partition Memory Buffer
 135                                          * Location
 136                                          */
 137         NVME_REG_CMBMSC = 0x0050,       /* Controller Memory Buffer Memory
 138                                          * Space Control
 139                                          */
 140         NVME_REG_PMRCAP = 0x0e00,       /* Persistent Memory Capabilities */
 141         NVME_REG_PMRCTL = 0x0e04,       /* Persistent Memory Region Control */
 142         NVME_REG_PMRSTS = 0x0e08,       /* Persistent Memory Region Status */
 143         NVME_REG_PMREBS = 0x0e0c,       /* Persistent Memory Region Elasticity
 144                                          * Buffer Size
 145                                          */
 146         NVME_REG_PMRSWTP = 0x0e10,      /* Persistent Memory Region Sustained
 147                                          * Write Throughput
 148                                          */
 149         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
 150 };
 151
 152 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 153 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 154 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 155 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 156 #define NVME_CAP_CSS(cap)       (((cap) >> 37) & 0xff)
 157 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 158 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 159 #define NVME_CAP_CMBS(cap)      (((cap) >> 57) & 0x1)
 160
 161 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 162 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 163
 164 enum {
 165         NVME_CMBSZ_SQS          = 1 << 0,
 166         NVME_CMBSZ_CQS          = 1 << 1,
 167         NVME_CMBSZ_LISTS        = 1 << 2,
 168         NVME_CMBSZ_RDS          = 1 << 3,
 169         NVME_CMBSZ_WDS          = 1 << 4,
 170
 171         NVME_CMBSZ_SZ_SHIFT     = 12,
 172         NVME_CMBSZ_SZ_MASK      = 0xfffff,
 173
 174         NVME_CMBSZ_SZU_SHIFT    = 8,
 175         NVME_CMBSZ_SZU_MASK     = 0xf,
 176 };
 177
 178 /*
 179  * Submission and Completion Queue Entry Sizes for the NVM command set.
 180  * (In bytes and specified as a power of two (2^n)).
 181  */
 182 #define NVME_ADM_SQES       6
 183 #define NVME_NVM_IOSQES         6
 184 #define NVME_NVM_IOCQES         4
 185
 186 enum {
 187         NVME_CC_ENABLE          = 1 << 0,
 188         NVME_CC_EN_SHIFT        = 0,
 189         NVME_CC_CSS_SHIFT       = 4,
 190         NVME_CC_MPS_SHIFT       = 7,
 191         NVME_CC_AMS_SHIFT       = 11,
 192         NVME_CC_SHN_SHIFT       = 14,
 193         NVME_CC_IOSQES_SHIFT    = 16,
 194         NVME_CC_IOCQES_SHIFT    = 20,
 195         NVME_CC_CSS_NVM         = 0 << NVME_CC_CSS_SHIFT,
 196         NVME_CC_CSS_CSI         = 6 << NVME_CC_CSS_SHIFT,
 197         NVME_CC_CSS_MASK        = 7 << NVME_CC_CSS_SHIFT,
 198         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
 199         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
 200         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
 201         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
 202         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
 203         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
 204         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
 205         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
 206         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
 207         NVME_CAP_CSS_NVM        = 1 << 0,
 208         NVME_CAP_CSS_CSI        = 1 << 6,
 209         NVME_CSTS_RDY           = 1 << 0,
 210         NVME_CSTS_CFS           = 1 << 1,
 211         NVME_CSTS_NSSRO         = 1 << 4,
 212         NVME_CSTS_PP            = 1 << 5,
 213         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 214         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 215         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 216         NVME_CSTS_SHST_MASK     = 3 << 2,
 217         NVME_CMBMSC_CRE         = 1 << 0,
 218         NVME_CMBMSC_CMSE        = 1 << 1,
 219 };
 220
 221 struct nvme_id_power_state {
 222         __le16                  max_power;      /* centiwatts */
 223         __u8                    rsvd2;
 224         __u8                    flags;
 225         __le32                  entry_lat;      /* microseconds */
 226         __le32                  exit_lat;       /* microseconds */
 227         __u8                    read_tput;
 228         __u8                    read_lat;
 229         __u8                    write_tput;
 230         __u8                    write_lat;
 231         __le16                  idle_power;
 232         __u8                    idle_scale;
 233         __u8                    rsvd19;
 234         __le16                  active_power;
 235         __u8                    active_work_scale;
 236         __u8                    rsvd23[9];
 237 };
 238
 239 enum {
 240         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 241         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 242 };
 243
 244 enum nvme_ctrl_attr {
 245         NVME_CTRL_ATTR_HID_128_BIT      = (1 << 0),
 246         NVME_CTRL_ATTR_TBKAS            = (1 << 6),
 247 };
 248
 249 struct nvme_id_ctrl {
 250         __le16                  vid;
 251         __le16                  ssvid;
 252         char                    sn[20];
 253         char                    mn[40];
 254         char                    fr[8];
 255         __u8                    rab;
 256         __u8                    ieee[3];
 257         __u8                    cmic;
 258         __u8                    mdts;
 259         __le16                  cntlid;
 260         __le32                  ver;
 261         __le32                  rtd3r;
 262         __le32                  rtd3e;
 263         __le32                  oaes;
 264         __le32                  ctratt;
 265         __u8                    rsvd100[11];
 266         __u8                    cntrltype;
 267         __u8                    fguid[16];
 268         __le16                  crdt1;
 269         __le16                  crdt2;
 270         __le16                  crdt3;
 271         __u8                    rsvd134[122];
 272         __le16                  oacs;
 273         __u8                    acl;
 274         __u8                    aerl;
 275         __u8                    frmw;
 276         __u8                    lpa;
 277         __u8                    elpe;
 278         __u8                    npss;
 279         __u8                    avscc;
 280         __u8                    apsta;
 281         __le16                  wctemp;
 282         __le16                  cctemp;
 283         __le16                  mtfa;
 284         __le32                  hmpre;
 285         __le32                  hmmin;
 286         __u8                    tnvmcap[16];
 287         __u8                    unvmcap[16];
 288         __le32                  rpmbs;
 289         __le16                  edstt;
 290         __u8                    dsto;
 291         __u8                    fwug;
 292         __le16                  kas;
 293         __le16                  hctma;
 294         __le16                  mntmt;
 295         __le16                  mxtmt;
 296         __le32                  sanicap;
 297         __le32                  hmminds;
 298         __le16                  hmmaxd;
 299         __u8                    rsvd338[4];
 300         __u8                    anatt;
 301         __u8                    anacap;
 302         __le32                  anagrpmax;
 303         __le32                  nanagrpid;
 304         __u8                    rsvd352[160];
 305         __u8                    sqes;
 306         __u8                    cqes;
 307         __le16                  maxcmd;
 308         __le32                  nn;
 309         __le16                  oncs;
 310         __le16                  fuses;
 311         __u8                    fna;
 312         __u8                    vwc;
 313         __le16                  awun;
 314         __le16                  awupf;
 315         __u8                    nvscc;
 316         __u8                    nwpc;
 317         __le16                  acwu;
 318         __u8                    rsvd534[2];
 319         __le32                  sgls;
 320         __le32                  mnan;
 321         __u8                    rsvd544[224];
 322         char                    subnqn[256];
 323         __u8                    rsvd1024[768];
 324         __le32                  ioccsz;
 325         __le32                  iorcsz;
 326         __le16                  icdoff;
 327         __u8                    ctrattr;
 328         __u8                    msdbd;
 329         __u8                    rsvd1804[2];
 330         __u8                    dctype;
 331         __u8                    rsvd1807[241];
 332         struct nvme_id_power_state      psd[32];
 333         __u8                    vs[1024];
 334 };
 335
 336 enum {
 337         NVME_CTRL_CMIC_MULTI_PORT               = 1 << 0,
 338         NVME_CTRL_CMIC_MULTI_CTRL               = 1 << 1,
 339         NVME_CTRL_CMIC_ANA                      = 1 << 3,
 340         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 341         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 342         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 343         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 344         NVME_CTRL_ONCS_RESERVATIONS             = 1 << 5,
 345         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
 346         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 347         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
 348         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
 349         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
 350         NVME_CTRL_LPA_CMD_EFFECTS_LOG           = 1 << 1,
 351         NVME_CTRL_CTRATT_128_ID                 = 1 << 0,
 352         NVME_CTRL_CTRATT_NON_OP_PSP             = 1 << 1,
 353         NVME_CTRL_CTRATT_NVM_SETS               = 1 << 2,
 354         NVME_CTRL_CTRATT_READ_RECV_LVLS         = 1 << 3,
 355         NVME_CTRL_CTRATT_ENDURANCE_GROUPS       = 1 << 4,
 356         NVME_CTRL_CTRATT_PREDICTABLE_LAT        = 1 << 5,
 357         NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY  = 1 << 7,
 358         NVME_CTRL_CTRATT_UUID_LIST              = 1 << 9,
 359 };
 360
 361 struct nvme_lbaf {
 362         __le16                  ms;
 363         __u8                    ds;
 364         __u8                    rp;
 365 };
 366
 367 struct nvme_id_ns {
 368         __le64                  nsze;
 369         __le64                  ncap;
 370         __le64                  nuse;
 371         __u8                    nsfeat;
 372         __u8                    nlbaf;
 373         __u8                    flbas;
 374         __u8                    mc;
 375         __u8                    dpc;
 376         __u8                    dps;
 377         __u8                    nmic;
 378         __u8                    rescap;
 379         __u8                    fpi;
 380         __u8                    dlfeat;
 381         __le16                  nawun;
 382         __le16                  nawupf;
 383         __le16                  nacwu;
 384         __le16                  nabsn;
 385         __le16                  nabo;
 386         __le16                  nabspf;
 387         __le16                  noiob;
 388         __u8                    nvmcap[16];
 389         __le16                  npwg;
 390         __le16                  npwa;
 391         __le16                  npdg;
 392         __le16                  npda;
 393         __le16                  nows;
 394         __u8                    rsvd74[18];
 395         __le32                  anagrpid;
 396         __u8                    rsvd96[3];
 397         __u8                    nsattr;
 398         __le16                  nvmsetid;
 399         __le16                  endgid;
 400         __u8                    nguid[16];
 401         __u8                    eui64[8];
 402         struct nvme_lbaf        lbaf[16];
 403         __u8                    rsvd192[192];
 404         __u8                    vs[3712];
 405 };
 406
 407 struct nvme_zns_lbafe {
 408         __le64                  zsze;
 409         __u8                    zdes;
 410         __u8                    rsvd9[7];
 411 };
 412
 413 struct nvme_id_ns_zns {
 414         __le16                  zoc;
 415         __le16                  ozcs;
 416         __le32                  mar;
 417         __le32                  mor;
 418         __le32                  rrl;
 419         __le32                  frl;
 420         __u8                    rsvd20[2796];
 421         struct nvme_zns_lbafe   lbafe[16];
 422         __u8                    rsvd3072[768];
 423         __u8                    vs[256];
 424 };
 425
 426 struct nvme_id_ctrl_zns {
 427         __u8    zasl;
 428         __u8    rsvd1[4095];
 429 };
 430
 431 struct nvme_id_ctrl_nvm {
 432         __u8    vsl;
 433         __u8    wzsl;
 434         __u8    wusl;
 435         __u8    dmrl;
 436         __le32  dmrsl;
 437         __le64  dmsl;
 438         __u8    rsvd16[4080];
 439 };
 440
 441 enum {
 442         NVME_ID_CNS_NS                  = 0x00,
 443         NVME_ID_CNS_CTRL                = 0x01,
 444         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 445         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
 446         NVME_ID_CNS_CS_NS               = 0x05,
 447         NVME_ID_CNS_CS_CTRL             = 0x06,
 448         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 449         NVME_ID_CNS_NS_PRESENT          = 0x11,
 450         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 451         NVME_ID_CNS_CTRL_LIST           = 0x13,
 452         NVME_ID_CNS_SCNDRY_CTRL_LIST    = 0x15,
 453         NVME_ID_CNS_NS_GRANULARITY      = 0x16,
 454         NVME_ID_CNS_UUID_LIST           = 0x17,
 455 };
 456
 457 enum {
 458         NVME_CSI_NVM                    = 0,
 459         NVME_CSI_ZNS                    = 2,
 460 };
 461
 462 enum {
 463         NVME_DIR_IDENTIFY               = 0x00,
 464         NVME_DIR_STREAMS                = 0x01,
 465         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
 466         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
 467         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
 468         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
 469         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
 470         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
 471         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
 472         NVME_DIR_ENDIR                  = 0x01,
 473 };
 474
 475 enum {
 476         NVME_NS_FEAT_THIN       = 1 << 0,
 477         NVME_NS_FEAT_ATOMICS    = 1 << 1,
 478         NVME_NS_FEAT_IO_OPT     = 1 << 4,
 479         NVME_NS_ATTR_RO         = 1 << 0,
 480         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 481         NVME_NS_FLBAS_META_EXT  = 0x10,
 482         NVME_NS_NMIC_SHARED     = 1 << 0,
 483         NVME_LBAF_RP_BEST       = 0,
 484         NVME_LBAF_RP_BETTER     = 1,
 485         NVME_LBAF_RP_GOOD       = 2,
 486         NVME_LBAF_RP_DEGRADED   = 3,
 487         NVME_NS_DPC_PI_LAST     = 1 << 4,
 488         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 489         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 490         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 491         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 492         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 493         NVME_NS_DPS_PI_MASK     = 0x7,
 494         NVME_NS_DPS_PI_TYPE1    = 1,
 495         NVME_NS_DPS_PI_TYPE2    = 2,
 496         NVME_NS_DPS_PI_TYPE3    = 3,
 497 };
 498
 499 /* Identify Namespace Metadata Capabilities (MC): */
 500 enum {
 501         NVME_MC_EXTENDED_LBA    = (1 << 0),
 502         NVME_MC_METADATA_PTR    = (1 << 1),
 503 };
 504
 505 struct nvme_ns_id_desc {
 506         __u8 nidt;
 507         __u8 nidl;
 508         __le16 reserved;
 509 };
 510
 511 #define NVME_NIDT_EUI64_LEN     8
 512 #define NVME_NIDT_NGUID_LEN     16
 513 #define NVME_NIDT_UUID_LEN      16
 514 #define NVME_NIDT_CSI_LEN       1
 515
 516 enum {
 517         NVME_NIDT_EUI64         = 0x01,
 518         NVME_NIDT_NGUID         = 0x02,
 519         NVME_NIDT_UUID          = 0x03,
 520         NVME_NIDT_CSI           = 0x04,
 521 };
 522
 523 struct nvme_smart_log {
 524         __u8                    critical_warning;
 525         __u8                    temperature[2];
 526         __u8                    avail_spare;
 527         __u8                    spare_thresh;
 528         __u8                    percent_used;
 529         __u8                    endu_grp_crit_warn_sumry;
 530         __u8                    rsvd7[25];
 531         __u8                    data_units_read[16];
 532         __u8                    data_units_written[16];
 533         __u8                    host_reads[16];
 534         __u8                    host_writes[16];
 535         __u8                    ctrl_busy_time[16];
 536         __u8                    power_cycles[16];
 537         __u8                    power_on_hours[16];
 538         __u8                    unsafe_shutdowns[16];
 539         __u8                    media_errors[16];
 540         __u8                    num_err_log_entries[16];
 541         __le32                  warning_temp_time;
 542         __le32                  critical_comp_time;
 543         __le16                  temp_sensor[8];
 544         __le32                  thm_temp1_trans_count;
 545         __le32                  thm_temp2_trans_count;
 546         __le32                  thm_temp1_total_time;
 547         __le32                  thm_temp2_total_time;
 548         __u8                    rsvd232[280];
 549 };
 550
 551 struct nvme_fw_slot_info_log {
 552         __u8                    afi;
 553         __u8                    rsvd1[7];
 554         __le64                  frs[7];
 555         __u8                    rsvd64[448];
 556 };
 557
 558 enum {
 559         NVME_CMD_EFFECTS_CSUPP          = 1 << 0,
 560         NVME_CMD_EFFECTS_LBCC           = 1 << 1,
 561         NVME_CMD_EFFECTS_NCC            = 1 << 2,
 562         NVME_CMD_EFFECTS_NIC            = 1 << 3,
 563         NVME_CMD_EFFECTS_CCC            = 1 << 4,
 564         NVME_CMD_EFFECTS_CSE_MASK       = 3 << 16,
 565         NVME_CMD_EFFECTS_UUID_SEL       = 1 << 19,
 566 };
 567
 568 struct nvme_effects_log {
 569         __le32 acs[256];
 570         __le32 iocs[256];
 571         __u8   resv[2048];
 572 };
 573
 574 enum nvme_ana_state {
 575         NVME_ANA_OPTIMIZED              = 0x01,
 576         NVME_ANA_NONOPTIMIZED           = 0x02,
 577         NVME_ANA_INACCESSIBLE           = 0x03,
 578         NVME_ANA_PERSISTENT_LOSS        = 0x04,
 579         NVME_ANA_CHANGE                 = 0x0f,
 580 };
 581
 582 struct nvme_ana_group_desc {
 583         __le32  grpid;
 584         __le32  nnsids;
 585         __le64  chgcnt;
 586         __u8    state;
 587         __u8    rsvd17[15];
 588         __le32  nsids[];
 589 };
 590
 591 /* flag for the log specific field of the ANA log */
 592 #define NVME_ANA_LOG_RGO        (1 << 0)
 593
 594 struct nvme_ana_rsp_hdr {
 595         __le64  chgcnt;
 596         __le16  ngrps;
 597         __le16  rsvd10[3];
 598 };
 599
 600 struct nvme_zone_descriptor {
 601         __u8            zt;
 602         __u8            zs;
 603         __u8            za;
 604         __u8            rsvd3[5];
 605         __le64          zcap;
 606         __le64          zslba;
 607         __le64          wp;
 608         __u8            rsvd32[32];
 609 };
 610
 611 enum {
 612         NVME_ZONE_TYPE_SEQWRITE_REQ     = 0x2,
 613 };
 614
 615 struct nvme_zone_report {
 616         __le64          nr_zones;
 617         __u8            resv8[56];
 618         struct nvme_zone_descriptor entries[];
 619 };
 620
 621 enum {
 622         NVME_SMART_CRIT_SPARE           = 1 << 0,
 623         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 624         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 625         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 626         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 627 };
 628
 629 enum {
 630         NVME_AER_ERROR                  = 0,
 631         NVME_AER_SMART                  = 1,
 632         NVME_AER_NOTICE                 = 2,
 633         NVME_AER_CSS                    = 6,
 634         NVME_AER_VS                     = 7,
 635 };
 636
 637 enum {
 638         NVME_AER_NOTICE_NS_CHANGED      = 0x00,
 639         NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
 640         NVME_AER_NOTICE_ANA             = 0x03,
 641         NVME_AER_NOTICE_DISC_CHANGED    = 0xf0,
 642 };
 643
 644 enum {
 645         NVME_AEN_BIT_NS_ATTR            = 8,
 646         NVME_AEN_BIT_FW_ACT             = 9,
 647         NVME_AEN_BIT_ANA_CHANGE         = 11,
 648         NVME_AEN_BIT_DISC_CHANGE        = 31,
 649 };
 650
 651 enum {
 652         NVME_AEN_CFG_NS_ATTR            = 1 << NVME_AEN_BIT_NS_ATTR,
 653         NVME_AEN_CFG_FW_ACT             = 1 << NVME_AEN_BIT_FW_ACT,
 654         NVME_AEN_CFG_ANA_CHANGE         = 1 << NVME_AEN_BIT_ANA_CHANGE,
 655         NVME_AEN_CFG_DISC_CHANGE        = 1 << NVME_AEN_BIT_DISC_CHANGE,
 656 };
 657
 658 struct nvme_lba_range_type {
 659         __u8                    type;
 660         __u8                    attributes;
 661         __u8                    rsvd2[14];
 662         __le64                  slba;
 663         __le64                  nlb;
 664         __u8                    guid[16];
 665         __u8                    rsvd48[16];
 666 };
 667
 668 enum {
 669         NVME_LBART_TYPE_FS      = 0x01,
 670         NVME_LBART_TYPE_RAID    = 0x02,
 671         NVME_LBART_TYPE_CACHE   = 0x03,
 672         NVME_LBART_TYPE_SWAP    = 0x04,
 673
 674         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 675         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 676 };
 677
 678 struct nvme_reservation_status {
 679         __le32  gen;
 680         __u8    rtype;
 681         __u8    regctl[2];
 682         __u8    resv5[2];
 683         __u8    ptpls;
 684         __u8    resv10[13];
 685         struct {
 686                 __le16  cntlid;
 687                 __u8    rcsts;
 688                 __u8    resv3[5];
 689                 __le64  hostid;
 690                 __le64  rkey;
 691         } regctl_ds[];
 692 };
 693
 694 enum nvme_async_event_type {
 695         NVME_AER_TYPE_ERROR     = 0,
 696         NVME_AER_TYPE_SMART     = 1,
 697         NVME_AER_TYPE_NOTICE    = 2,
 698 };
 699
 700 /* I/O commands */
 701
 702 enum nvme_opcode {
 703         nvme_cmd_flush          = 0x00,
 704         nvme_cmd_write          = 0x01,
 705         nvme_cmd_read           = 0x02,
 706         nvme_cmd_write_uncor    = 0x04,
 707         nvme_cmd_compare        = 0x05,
 708         nvme_cmd_write_zeroes   = 0x08,
 709         nvme_cmd_dsm            = 0x09,
 710         nvme_cmd_verify         = 0x0c,
 711         nvme_cmd_resv_register  = 0x0d,
 712         nvme_cmd_resv_report    = 0x0e,
 713         nvme_cmd_resv_acquire   = 0x11,
 714         nvme_cmd_resv_release   = 0x15,
 715         nvme_cmd_zone_mgmt_send = 0x79,
 716         nvme_cmd_zone_mgmt_recv = 0x7a,
 717         nvme_cmd_zone_append    = 0x7d,
 718 };
 719
 720 #define nvme_opcode_name(opcode)        { opcode, #opcode }
 721 #define show_nvm_opcode_name(val)                               \
 722         __print_symbolic(val,                                   \
 723                 nvme_opcode_name(nvme_cmd_flush),               \
 724                 nvme_opcode_name(nvme_cmd_write),               \
 725                 nvme_opcode_name(nvme_cmd_read),                \
 726                 nvme_opcode_name(nvme_cmd_write_uncor),         \
 727                 nvme_opcode_name(nvme_cmd_compare),             \
 728                 nvme_opcode_name(nvme_cmd_write_zeroes),        \
 729                 nvme_opcode_name(nvme_cmd_dsm),                 \
 730                 nvme_opcode_name(nvme_cmd_resv_register),       \
 731                 nvme_opcode_name(nvme_cmd_resv_report),         \
 732                 nvme_opcode_name(nvme_cmd_resv_acquire),        \
 733                 nvme_opcode_name(nvme_cmd_resv_release),        \
 734                 nvme_opcode_name(nvme_cmd_zone_mgmt_send),      \
 735                 nvme_opcode_name(nvme_cmd_zone_mgmt_recv),      \
 736                 nvme_opcode_name(nvme_cmd_zone_append))
 737
 738
 739
 740 /*
 741  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 742  *
 743  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 744  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 745  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
 746  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 747  *                            request subtype
 748  */
 749 enum {
 750         NVME_SGL_FMT_ADDRESS            = 0x00,
 751         NVME_SGL_FMT_OFFSET             = 0x01,
 752         NVME_SGL_FMT_TRANSPORT_A        = 0x0A,
 753         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 754 };
 755
 756 /*
 757  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 758  *
 759  * For struct nvme_sgl_desc:
 760  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 761  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 762  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 763  *
 764  * For struct nvme_keyed_sgl_desc:
 765  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 766  *
 767  * Transport-specific SGL types:
 768  *   @NVME_TRANSPORT_SGL_DATA_DESC:     Transport SGL data dlock descriptor
 769  */
 770 enum {
 771         NVME_SGL_FMT_DATA_DESC          = 0x00,
 772         NVME_SGL_FMT_SEG_DESC           = 0x02,
 773         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 774         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 775         NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
 776 };
 777
 778 struct nvme_sgl_desc {
 779         __le64  addr;
 780         __le32  length;
 781         __u8    rsvd[3];
 782         __u8    type;
 783 };
 784
 785 struct nvme_keyed_sgl_desc {
 786         __le64  addr;
 787         __u8    length[3];
 788         __u8    key[4];
 789         __u8    type;
 790 };
 791
 792 union nvme_data_ptr {
 793         struct {
 794                 __le64  prp1;
 795                 __le64  prp2;
 796         };
 797         struct nvme_sgl_desc    sgl;
 798         struct nvme_keyed_sgl_desc ksgl;
 799 };
 800
 801 /*
 802  * Lowest two bits of our flags field (FUSE field in the spec):
 803  *
 804  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 805  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 806  *
 807  * Highest two bits in our flags field (PSDT field in the spec):
 808  *
 809  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 810  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 811  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 812  *      If used, MPTR contains an address of an SGL segment containing
 813  *      exactly 1 SGL descriptor (qword aligned).
 814  */
 815 enum {
 816         NVME_CMD_FUSE_FIRST     = (1 << 0),
 817         NVME_CMD_FUSE_SECOND    = (1 << 1),
 818
 819         NVME_CMD_SGL_METABUF    = (1 << 6),
 820         NVME_CMD_SGL_METASEG    = (1 << 7),
 821         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 822 };
 823
 824 struct nvme_common_command {
 825         __u8                    opcode;
 826         __u8                    flags;
 827         __u16                   command_id;
 828         __le32                  nsid;
 829         __le32                  cdw2[2];
 830         __le64                  metadata;
 831         union nvme_data_ptr     dptr;
 832         __le32                  cdw10;
 833         __le32                  cdw11;
 834         __le32                  cdw12;
 835         __le32                  cdw13;
 836         __le32                  cdw14;
 837         __le32                  cdw15;
 838 };
 839
 840 struct nvme_rw_command {
 841         __u8                    opcode;
 842         __u8                    flags;
 843         __u16                   command_id;
 844         __le32                  nsid;
 845         __u64                   rsvd2;
 846         __le64                  metadata;
 847         union nvme_data_ptr     dptr;
 848         __le64                  slba;
 849         __le16                  length;
 850         __le16                  control;
 851         __le32                  dsmgmt;
 852         __le32                  reftag;
 853         __le16                  apptag;
 854         __le16                  appmask;
 855 };
 856
 857 enum {
 858         NVME_RW_LR                      = 1 << 15,
 859         NVME_RW_FUA                     = 1 << 14,
 860         NVME_RW_APPEND_PIREMAP          = 1 << 9,
 861         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 862         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 863         NVME_RW_DSM_FREQ_RARE           = 2,
 864         NVME_RW_DSM_FREQ_READS          = 3,
 865         NVME_RW_DSM_FREQ_WRITES         = 4,
 866         NVME_RW_DSM_FREQ_RW             = 5,
 867         NVME_RW_DSM_FREQ_ONCE           = 6,
 868         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 869         NVME_RW_DSM_FREQ_TEMP           = 8,
 870         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 871         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 872         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 873         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 874         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 875         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 876         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
 877         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
 878         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
 879         NVME_RW_PRINFO_PRACT            = 1 << 13,
 880         NVME_RW_DTYPE_STREAMS           = 1 << 4,
 881 };
 882
 883 struct nvme_dsm_cmd {
 884         __u8                    opcode;
 885         __u8                    flags;
 886         __u16                   command_id;
 887         __le32                  nsid;
 888         __u64                   rsvd2[2];
 889         union nvme_data_ptr     dptr;
 890         __le32                  nr;
 891         __le32                  attributes;
 892         __u32                   rsvd12[4];
 893 };
 894
 895 enum {
 896         NVME_DSMGMT_IDR         = 1 << 0,
 897         NVME_DSMGMT_IDW         = 1 << 1,
 898         NVME_DSMGMT_AD          = 1 << 2,
 899 };
 900
 901 #define NVME_DSM_MAX_RANGES     256
 902
 903 struct nvme_dsm_range {
 904         __le32                  cattr;
 905         __le32                  nlb;
 906         __le64                  slba;
 907 };
 908
 909 struct nvme_write_zeroes_cmd {
 910         __u8                    opcode;
 911         __u8                    flags;
 912         __u16                   command_id;
 913         __le32                  nsid;
 914         __u64                   rsvd2;
 915         __le64                  metadata;
 916         union nvme_data_ptr     dptr;
 917         __le64                  slba;
 918         __le16                  length;
 919         __le16                  control;
 920         __le32                  dsmgmt;
 921         __le32                  reftag;
 922         __le16                  apptag;
 923         __le16                  appmask;
 924 };
 925
 926 enum nvme_zone_mgmt_action {
 927         NVME_ZONE_CLOSE         = 0x1,
 928         NVME_ZONE_FINISH        = 0x2,
 929         NVME_ZONE_OPEN          = 0x3,
 930         NVME_ZONE_RESET         = 0x4,
 931         NVME_ZONE_OFFLINE       = 0x5,
 932         NVME_ZONE_SET_DESC_EXT  = 0x10,
 933 };
 934
 935 struct nvme_zone_mgmt_send_cmd {
 936         __u8                    opcode;
 937         __u8                    flags;
 938         __u16                   command_id;
 939         __le32                  nsid;
 940         __le32                  cdw2[2];
 941         __le64                  metadata;
 942         union nvme_data_ptr     dptr;
 943         __le64                  slba;
 944         __le32                  cdw12;
 945         __u8                    zsa;
 946         __u8                    select_all;
 947         __u8                    rsvd13[2];
 948         __le32                  cdw14[2];
 949 };
 950
 951 struct nvme_zone_mgmt_recv_cmd {
 952         __u8                    opcode;
 953         __u8                    flags;
 954         __u16                   command_id;
 955         __le32                  nsid;
 956         __le64                  rsvd2[2];
 957         union nvme_data_ptr     dptr;
 958         __le64                  slba;
 959         __le32                  numd;
 960         __u8                    zra;
 961         __u8                    zrasf;
 962         __u8                    pr;
 963         __u8                    rsvd13;
 964         __le32                  cdw14[2];
 965 };
 966
 967 enum {
 968         NVME_ZRA_ZONE_REPORT            = 0,
 969         NVME_ZRASF_ZONE_REPORT_ALL      = 0,
 970         NVME_ZRASF_ZONE_STATE_EMPTY     = 0x01,
 971         NVME_ZRASF_ZONE_STATE_IMP_OPEN  = 0x02,
 972         NVME_ZRASF_ZONE_STATE_EXP_OPEN  = 0x03,
 973         NVME_ZRASF_ZONE_STATE_CLOSED    = 0x04,
 974         NVME_ZRASF_ZONE_STATE_READONLY  = 0x05,
 975         NVME_ZRASF_ZONE_STATE_FULL      = 0x06,
 976         NVME_ZRASF_ZONE_STATE_OFFLINE   = 0x07,
 977         NVME_REPORT_ZONE_PARTIAL        = 1,
 978 };
 979
 980 /* Features */
 981
 982 enum {
 983         NVME_TEMP_THRESH_MASK           = 0xffff,
 984         NVME_TEMP_THRESH_SELECT_SHIFT   = 16,
 985         NVME_TEMP_THRESH_TYPE_UNDER     = 0x100000,
 986 };
 987
 988 struct nvme_feat_auto_pst {
 989         __le64 entries[32];
 990 };
 991
 992 enum {
 993         NVME_HOST_MEM_ENABLE    = (1 << 0),
 994         NVME_HOST_MEM_RETURN    = (1 << 1),
 995 };
 996
 997 struct nvme_feat_host_behavior {
 998         __u8 acre;
 999         __u8 resv1[511];
1000 };
1001
1002 enum {
1003         NVME_ENABLE_ACRE        = 1,
1004 };
1005
1006 /* Admin commands */
1007
1008 enum nvme_admin_opcode {
1009         nvme_admin_delete_sq            = 0x00,
1010         nvme_admin_create_sq            = 0x01,
1011         nvme_admin_get_log_page         = 0x02,
1012         nvme_admin_delete_cq            = 0x04,
1013         nvme_admin_create_cq            = 0x05,
1014         nvme_admin_identify             = 0x06,
1015         nvme_admin_abort_cmd            = 0x08,
1016         nvme_admin_set_features         = 0x09,
1017         nvme_admin_get_features         = 0x0a,
1018         nvme_admin_async_event          = 0x0c,
1019         nvme_admin_ns_mgmt              = 0x0d,
1020         nvme_admin_activate_fw          = 0x10,
1021         nvme_admin_download_fw          = 0x11,
1022         nvme_admin_dev_self_test        = 0x14,
1023         nvme_admin_ns_attach            = 0x15,
1024         nvme_admin_keep_alive           = 0x18,
1025         nvme_admin_directive_send       = 0x19,
1026         nvme_admin_directive_recv       = 0x1a,
1027         nvme_admin_virtual_mgmt         = 0x1c,
1028         nvme_admin_nvme_mi_send         = 0x1d,
1029         nvme_admin_nvme_mi_recv         = 0x1e,
1030         nvme_admin_dbbuf                = 0x7C,
1031         nvme_admin_format_nvm           = 0x80,
1032         nvme_admin_security_send        = 0x81,
1033         nvme_admin_security_recv        = 0x82,
1034         nvme_admin_sanitize_nvm         = 0x84,
1035         nvme_admin_get_lba_status       = 0x86,
1036         nvme_admin_vendor_start         = 0xC0,
1037 };
1038
1039 #define nvme_admin_opcode_name(opcode)  { opcode, #opcode }
1040 #define show_admin_opcode_name(val)                                     \
1041         __print_symbolic(val,                                           \
1042                 nvme_admin_opcode_name(nvme_admin_delete_sq),           \
1043                 nvme_admin_opcode_name(nvme_admin_create_sq),           \
1044                 nvme_admin_opcode_name(nvme_admin_get_log_page),        \
1045                 nvme_admin_opcode_name(nvme_admin_delete_cq),           \
1046                 nvme_admin_opcode_name(nvme_admin_create_cq),           \
1047                 nvme_admin_opcode_name(nvme_admin_identify),            \
1048                 nvme_admin_opcode_name(nvme_admin_abort_cmd),           \
1049                 nvme_admin_opcode_name(nvme_admin_set_features),        \
1050                 nvme_admin_opcode_name(nvme_admin_get_features),        \
1051                 nvme_admin_opcode_name(nvme_admin_async_event),         \
1052                 nvme_admin_opcode_name(nvme_admin_ns_mgmt),             \
1053                 nvme_admin_opcode_name(nvme_admin_activate_fw),         \
1054                 nvme_admin_opcode_name(nvme_admin_download_fw),         \
1055                 nvme_admin_opcode_name(nvme_admin_ns_attach),           \
1056                 nvme_admin_opcode_name(nvme_admin_keep_alive),          \
1057                 nvme_admin_opcode_name(nvme_admin_directive_send),      \
1058                 nvme_admin_opcode_name(nvme_admin_directive_recv),      \
1059                 nvme_admin_opcode_name(nvme_admin_dbbuf),               \
1060                 nvme_admin_opcode_name(nvme_admin_format_nvm),          \
1061                 nvme_admin_opcode_name(nvme_admin_security_send),       \
1062                 nvme_admin_opcode_name(nvme_admin_security_recv),       \
1063                 nvme_admin_opcode_name(nvme_admin_sanitize_nvm),        \
1064                 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1065
1066 enum {
1067         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
1068         NVME_CQ_IRQ_ENABLED     = (1 << 1),
1069         NVME_SQ_PRIO_URGENT     = (0 << 1),
1070         NVME_SQ_PRIO_HIGH       = (1 << 1),
1071         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
1072         NVME_SQ_PRIO_LOW        = (3 << 1),
1073         NVME_FEAT_ARBITRATION   = 0x01,
1074         NVME_FEAT_POWER_MGMT    = 0x02,
1075         NVME_FEAT_LBA_RANGE     = 0x03,
1076         NVME_FEAT_TEMP_THRESH   = 0x04,
1077         NVME_FEAT_ERR_RECOVERY  = 0x05,
1078         NVME_FEAT_VOLATILE_WC   = 0x06,
1079         NVME_FEAT_NUM_QUEUES    = 0x07,
1080         NVME_FEAT_IRQ_COALESCE  = 0x08,
1081         NVME_FEAT_IRQ_CONFIG    = 0x09,
1082         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
1083         NVME_FEAT_ASYNC_EVENT   = 0x0b,
1084         NVME_FEAT_AUTO_PST      = 0x0c,
1085         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
1086         NVME_FEAT_TIMESTAMP     = 0x0e,
1087         NVME_FEAT_KATO          = 0x0f,
1088         NVME_FEAT_HCTM          = 0x10,
1089         NVME_FEAT_NOPSC         = 0x11,
1090         NVME_FEAT_RRL           = 0x12,
1091         NVME_FEAT_PLM_CONFIG    = 0x13,
1092         NVME_FEAT_PLM_WINDOW    = 0x14,
1093         NVME_FEAT_HOST_BEHAVIOR = 0x16,
1094         NVME_FEAT_SANITIZE      = 0x17,
1095         NVME_FEAT_SW_PROGRESS   = 0x80,
1096         NVME_FEAT_HOST_ID       = 0x81,
1097         NVME_FEAT_RESV_MASK     = 0x82,
1098         NVME_FEAT_RESV_PERSIST  = 0x83,
1099         NVME_FEAT_WRITE_PROTECT = 0x84,
1100         NVME_FEAT_VENDOR_START  = 0xC0,
1101         NVME_FEAT_VENDOR_END    = 0xFF,
1102         NVME_LOG_ERROR          = 0x01,
1103         NVME_LOG_SMART          = 0x02,
1104         NVME_LOG_FW_SLOT        = 0x03,
1105         NVME_LOG_CHANGED_NS     = 0x04,
1106         NVME_LOG_CMD_EFFECTS    = 0x05,
1107         NVME_LOG_DEVICE_SELF_TEST = 0x06,
1108         NVME_LOG_TELEMETRY_HOST = 0x07,
1109         NVME_LOG_TELEMETRY_CTRL = 0x08,
1110         NVME_LOG_ENDURANCE_GROUP = 0x09,
1111         NVME_LOG_ANA            = 0x0c,
1112         NVME_LOG_DISC           = 0x70,
1113         NVME_LOG_RESERVATION    = 0x80,
1114         NVME_FWACT_REPL         = (0 << 3),
1115         NVME_FWACT_REPL_ACTV    = (1 << 3),
1116         NVME_FWACT_ACTV         = (2 << 3),
1117 };
1118
1119 /* NVMe Namespace Write Protect State */
1120 enum {
1121         NVME_NS_NO_WRITE_PROTECT = 0,
1122         NVME_NS_WRITE_PROTECT,
1123         NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1124         NVME_NS_WRITE_PROTECT_PERMANENT,
1125 };
1126
1127 #define NVME_MAX_CHANGED_NAMESPACES     1024
1128
1129 struct nvme_identify {
1130         __u8                    opcode;
1131         __u8                    flags;
1132         __u16                   command_id;
1133         __le32                  nsid;
1134         __u64                   rsvd2[2];
1135         union nvme_data_ptr     dptr;
1136         __u8                    cns;
1137         __u8                    rsvd3;
1138         __le16                  ctrlid;
1139         __u8                    rsvd11[3];
1140         __u8                    csi;
1141         __u32                   rsvd12[4];
1142 };
1143
1144 #define NVME_IDENTIFY_DATA_SIZE 4096
1145
1146 struct nvme_features {
1147         __u8                    opcode;
1148         __u8                    flags;
1149         __u16                   command_id;
1150         __le32                  nsid;
1151         __u64                   rsvd2[2];
1152         union nvme_data_ptr     dptr;
1153         __le32                  fid;
1154         __le32                  dword11;
1155         __le32                  dword12;
1156         __le32                  dword13;
1157         __le32                  dword14;
1158         __le32                  dword15;
1159 };
1160
1161 struct nvme_host_mem_buf_desc {
1162         __le64                  addr;
1163         __le32                  size;
1164         __u32                   rsvd;
1165 };
1166
1167 struct nvme_create_cq {
1168         __u8                    opcode;
1169         __u8                    flags;
1170         __u16                   command_id;
1171         __u32                   rsvd1[5];
1172         __le64                  prp1;
1173         __u64                   rsvd8;
1174         __le16                  cqid;
1175         __le16                  qsize;
1176         __le16                  cq_flags;
1177         __le16                  irq_vector;
1178         __u32                   rsvd12[4];
1179 };
1180
1181 struct nvme_create_sq {
1182         __u8                    opcode;
1183         __u8                    flags;
1184         __u16                   command_id;
1185         __u32                   rsvd1[5];
1186         __le64                  prp1;
1187         __u64                   rsvd8;
1188         __le16                  sqid;
1189         __le16                  qsize;
1190         __le16                  sq_flags;
1191         __le16                  cqid;
1192         __u32                   rsvd12[4];
1193 };
1194
1195 struct nvme_delete_queue {
1196         __u8                    opcode;
1197         __u8                    flags;
1198         __u16                   command_id;
1199         __u32                   rsvd1[9];
1200         __le16                  qid;
1201         __u16                   rsvd10;
1202         __u32                   rsvd11[5];
1203 };
1204
1205 struct nvme_abort_cmd {
1206         __u8                    opcode;
1207         __u8                    flags;
1208         __u16                   command_id;
1209         __u32                   rsvd1[9];
1210         __le16                  sqid;
1211         __u16                   cid;
1212         __u32                   rsvd11[5];
1213 };
1214
1215 struct nvme_download_firmware {
1216         __u8                    opcode;
1217         __u8                    flags;
1218         __u16                   command_id;
1219         __u32                   rsvd1[5];
1220         union nvme_data_ptr     dptr;
1221         __le32                  numd;
1222         __le32                  offset;
1223         __u32                   rsvd12[4];
1224 };
1225
1226 struct nvme_format_cmd {
1227         __u8                    opcode;
1228         __u8                    flags;
1229         __u16                   command_id;
1230         __le32                  nsid;
1231         __u64                   rsvd2[4];
1232         __le32                  cdw10;
1233         __u32                   rsvd11[5];
1234 };
1235
1236 struct nvme_get_log_page_command {
1237         __u8                    opcode;
1238         __u8                    flags;
1239         __u16                   command_id;
1240         __le32                  nsid;
1241         __u64                   rsvd2[2];
1242         union nvme_data_ptr     dptr;
1243         __u8                    lid;
1244         __u8                    lsp; /* upper 4 bits reserved */
1245         __le16                  numdl;
1246         __le16                  numdu;
1247         __u16                   rsvd11;
1248         union {
1249                 struct {
1250                         __le32 lpol;
1251                         __le32 lpou;
1252                 };
1253                 __le64 lpo;
1254         };
1255         __u8                    rsvd14[3];
1256         __u8                    csi;
1257         __u32                   rsvd15;
1258 };
1259
1260 struct nvme_directive_cmd {
1261         __u8                    opcode;
1262         __u8                    flags;
1263         __u16                   command_id;
1264         __le32                  nsid;
1265         __u64                   rsvd2[2];
1266         union nvme_data_ptr     dptr;
1267         __le32                  numd;
1268         __u8                    doper;
1269         __u8                    dtype;
1270         __le16                  dspec;
1271         __u8                    endir;
1272         __u8                    tdtype;
1273         __u16                   rsvd15;
1274
1275         __u32                   rsvd16[3];
1276 };
1277
1278 /*
1279  * Fabrics subcommands.
1280  */
1281 enum nvmf_fabrics_opcode {
1282         nvme_fabrics_command            = 0x7f,
1283 };
1284
1285 enum nvmf_capsule_command {
1286         nvme_fabrics_type_property_set  = 0x00,
1287         nvme_fabrics_type_connect       = 0x01,
1288         nvme_fabrics_type_property_get  = 0x04,
1289 };
1290
1291 #define nvme_fabrics_type_name(type)   { type, #type }
1292 #define show_fabrics_type_name(type)                                    \
1293         __print_symbolic(type,                                          \
1294                 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1295                 nvme_fabrics_type_name(nvme_fabrics_type_connect),      \
1296                 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1297
1298 /*
1299  * If not fabrics command, fctype will be ignored.
1300  */
1301 #define show_opcode_name(qid, opcode, fctype)                   \
1302         ((opcode) == nvme_fabrics_command ?                     \
1303          show_fabrics_type_name(fctype) :                       \
1304         ((qid) ?                                                \
1305          show_nvm_opcode_name(opcode) :                         \
1306          show_admin_opcode_name(opcode)))
1307
1308 struct nvmf_common_command {
1309         __u8    opcode;
1310         __u8    resv1;
1311         __u16   command_id;
1312         __u8    fctype;
1313         __u8    resv2[35];
1314         __u8    ts[24];
1315 };
1316
1317 /*
1318  * The legal cntlid range a NVMe Target will provide.
1319  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1320  * Devices based on earlier specs did not have the subsystem concept;
1321  * therefore, those devices had their cntlid value set to 0 as a result.
1322  */
1323 #define NVME_CNTLID_MIN         1
1324 #define NVME_CNTLID_MAX         0xffef
1325 #define NVME_CNTLID_DYNAMIC     0xffff
1326
1327 #define MAX_DISC_LOGS   255
1328
1329 /* Discovery log page entry flags (EFLAGS): */
1330 enum {
1331         NVME_DISC_EFLAGS_EPCSD          = (1 << 1),
1332         NVME_DISC_EFLAGS_DUPRETINFO     = (1 << 0),
1333 };
1334
1335 /* Discovery log page entry */
1336 struct nvmf_disc_rsp_page_entry {
1337         __u8            trtype;
1338         __u8            adrfam;
1339         __u8            subtype;
1340         __u8            treq;
1341         __le16          portid;
1342         __le16          cntlid;
1343         __le16          asqsz;
1344         __le16          eflags;
1345         __u8            resv10[20];
1346         char            trsvcid[NVMF_TRSVCID_SIZE];
1347         __u8            resv64[192];
1348         char            subnqn[NVMF_NQN_FIELD_LEN];
1349         char            traddr[NVMF_TRADDR_SIZE];
1350         union tsas {
1351                 char            common[NVMF_TSAS_SIZE];
1352                 struct rdma {
1353                         __u8    qptype;
1354                         __u8    prtype;
1355                         __u8    cms;
1356                         __u8    resv3[5];
1357                         __u16   pkey;
1358                         __u8    resv10[246];
1359                 } rdma;
1360         } tsas;
1361 };
1362
1363 /* Discovery log page header */
1364 struct nvmf_disc_rsp_page_hdr {
1365         __le64          genctr;
1366         __le64          numrec;
1367         __le16          recfmt;
1368         __u8            resv14[1006];
1369         struct nvmf_disc_rsp_page_entry entries[];
1370 };
1371
1372 enum {
1373         NVME_CONNECT_DISABLE_SQFLOW     = (1 << 2),
1374 };
1375
1376 struct nvmf_connect_command {
1377         __u8            opcode;
1378         __u8            resv1;
1379         __u16           command_id;
1380         __u8            fctype;
1381         __u8            resv2[19];
1382         union nvme_data_ptr dptr;
1383         __le16          recfmt;
1384         __le16          qid;
1385         __le16          sqsize;
1386         __u8            cattr;
1387         __u8            resv3;
1388         __le32          kato;
1389         __u8            resv4[12];
1390 };
1391
1392 struct nvmf_connect_data {
1393         uuid_t          hostid;
1394         __le16          cntlid;
1395         char            resv4[238];
1396         char            subsysnqn[NVMF_NQN_FIELD_LEN];
1397         char            hostnqn[NVMF_NQN_FIELD_LEN];
1398         char            resv5[256];
1399 };
1400
1401 struct nvmf_property_set_command {
1402         __u8            opcode;
1403         __u8            resv1;
1404         __u16           command_id;
1405         __u8            fctype;
1406         __u8            resv2[35];
1407         __u8            attrib;
1408         __u8            resv3[3];
1409         __le32          offset;
1410         __le64          value;
1411         __u8            resv4[8];
1412 };
1413
1414 struct nvmf_property_get_command {
1415         __u8            opcode;
1416         __u8            resv1;
1417         __u16           command_id;
1418         __u8            fctype;
1419         __u8            resv2[35];
1420         __u8            attrib;
1421         __u8            resv3[3];
1422         __le32          offset;
1423         __u8            resv4[16];
1424 };
1425
1426 struct nvme_dbbuf {
1427         __u8                    opcode;
1428         __u8                    flags;
1429         __u16                   command_id;
1430         __u32                   rsvd1[5];
1431         __le64                  prp1;
1432         __le64                  prp2;
1433         __u32                   rsvd12[6];
1434 };
1435
1436 struct streams_directive_params {
1437         __le16  msl;
1438         __le16  nssa;
1439         __le16  nsso;
1440         __u8    rsvd[10];
1441         __le32  sws;
1442         __le16  sgs;
1443         __le16  nsa;
1444         __le16  nso;
1445         __u8    rsvd2[6];
1446 };
1447
1448 struct nvme_command {
1449         union {
1450                 struct nvme_common_command common;
1451                 struct nvme_rw_command rw;
1452                 struct nvme_identify identify;
1453                 struct nvme_features features;
1454                 struct nvme_create_cq create_cq;
1455                 struct nvme_create_sq create_sq;
1456                 struct nvme_delete_queue delete_queue;
1457                 struct nvme_download_firmware dlfw;
1458                 struct nvme_format_cmd format;
1459                 struct nvme_dsm_cmd dsm;
1460                 struct nvme_write_zeroes_cmd write_zeroes;
1461                 struct nvme_zone_mgmt_send_cmd zms;
1462                 struct nvme_zone_mgmt_recv_cmd zmr;
1463                 struct nvme_abort_cmd abort;
1464                 struct nvme_get_log_page_command get_log_page;
1465                 struct nvmf_common_command fabrics;
1466                 struct nvmf_connect_command connect;
1467                 struct nvmf_property_set_command prop_set;
1468                 struct nvmf_property_get_command prop_get;
1469                 struct nvme_dbbuf dbbuf;
1470                 struct nvme_directive_cmd directive;
1471         };
1472 };
1473
1474 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1475 {
1476         return cmd->common.opcode == nvme_fabrics_command;
1477 }
1478
1479 struct nvme_error_slot {
1480         __le64          error_count;
1481         __le16          sqid;
1482         __le16          cmdid;
1483         __le16          status_field;
1484         __le16          param_error_location;
1485         __le64          lba;
1486         __le32          nsid;
1487         __u8            vs;
1488         __u8            resv[3];
1489         __le64          cs;
1490         __u8            resv2[24];
1491 };
1492
1493 static inline bool nvme_is_write(struct nvme_command *cmd)
1494 {
1495         /*
1496          * What a mess...
1497          *
1498          * Why can't we simply have a Fabrics In and Fabrics out command?
1499          */
1500         if (unlikely(nvme_is_fabrics(cmd)))
1501                 return cmd->fabrics.fctype & 1;
1502         return cmd->common.opcode & 1;
1503 }
1504
1505 enum {
1506         /*
1507          * Generic Command Status:
1508          */
1509         NVME_SC_SUCCESS                 = 0x0,
1510         NVME_SC_INVALID_OPCODE          = 0x1,
1511         NVME_SC_INVALID_FIELD           = 0x2,
1512         NVME_SC_CMDID_CONFLICT          = 0x3,
1513         NVME_SC_DATA_XFER_ERROR         = 0x4,
1514         NVME_SC_POWER_LOSS              = 0x5,
1515         NVME_SC_INTERNAL                = 0x6,
1516         NVME_SC_ABORT_REQ               = 0x7,
1517         NVME_SC_ABORT_QUEUE             = 0x8,
1518         NVME_SC_FUSED_FAIL              = 0x9,
1519         NVME_SC_FUSED_MISSING           = 0xa,
1520         NVME_SC_INVALID_NS              = 0xb,
1521         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1522         NVME_SC_SGL_INVALID_LAST        = 0xd,
1523         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1524         NVME_SC_SGL_INVALID_DATA        = 0xf,
1525         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1526         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1527         NVME_SC_CMB_INVALID_USE         = 0x12,
1528         NVME_SC_PRP_INVALID_OFFSET      = 0x13,
1529         NVME_SC_ATOMIC_WU_EXCEEDED      = 0x14,
1530         NVME_SC_OP_DENIED               = 0x15,
1531         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1532         NVME_SC_RESERVED                = 0x17,
1533         NVME_SC_HOST_ID_INCONSIST       = 0x18,
1534         NVME_SC_KA_TIMEOUT_EXPIRED      = 0x19,
1535         NVME_SC_KA_TIMEOUT_INVALID      = 0x1A,
1536         NVME_SC_ABORTED_PREEMPT_ABORT   = 0x1B,
1537         NVME_SC_SANITIZE_FAILED         = 0x1C,
1538         NVME_SC_SANITIZE_IN_PROGRESS    = 0x1D,
1539         NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1540         NVME_SC_CMD_NOT_SUP_CMB_QUEUE   = 0x1F,
1541         NVME_SC_NS_WRITE_PROTECTED      = 0x20,
1542         NVME_SC_CMD_INTERRUPTED         = 0x21,
1543         NVME_SC_TRANSIENT_TR_ERR        = 0x22,
1544         NVME_SC_INVALID_IO_CMD_SET      = 0x2C,
1545
1546         NVME_SC_LBA_RANGE               = 0x80,
1547         NVME_SC_CAP_EXCEEDED            = 0x81,
1548         NVME_SC_NS_NOT_READY            = 0x82,
1549         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1550         NVME_SC_FORMAT_IN_PROGRESS      = 0x84,
1551
1552         /*
1553          * Command Specific Status:
1554          */
1555         NVME_SC_CQ_INVALID              = 0x100,
1556         NVME_SC_QID_INVALID             = 0x101,
1557         NVME_SC_QUEUE_SIZE              = 0x102,
1558         NVME_SC_ABORT_LIMIT             = 0x103,
1559         NVME_SC_ABORT_MISSING           = 0x104,
1560         NVME_SC_ASYNC_LIMIT             = 0x105,
1561         NVME_SC_FIRMWARE_SLOT           = 0x106,
1562         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1563         NVME_SC_INVALID_VECTOR          = 0x108,
1564         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1565         NVME_SC_INVALID_FORMAT          = 0x10a,
1566         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1567         NVME_SC_INVALID_QUEUE           = 0x10c,
1568         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1569         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1570         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1571         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1572         NVME_SC_FW_NEEDS_RESET          = 0x111,
1573         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1574         NVME_SC_FW_ACTIVATE_PROHIBITED  = 0x113,
1575         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1576         NVME_SC_NS_INSUFFICIENT_CAP     = 0x115,
1577         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1578         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1579         NVME_SC_NS_IS_PRIVATE           = 0x119,
1580         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1581         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1582         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1583         NVME_SC_SELT_TEST_IN_PROGRESS   = 0x11d,
1584         NVME_SC_BP_WRITE_PROHIBITED     = 0x11e,
1585         NVME_SC_CTRL_ID_INVALID         = 0x11f,
1586         NVME_SC_SEC_CTRL_STATE_INVALID  = 0x120,
1587         NVME_SC_CTRL_RES_NUM_INVALID    = 0x121,
1588         NVME_SC_RES_ID_INVALID          = 0x122,
1589         NVME_SC_PMR_SAN_PROHIBITED      = 0x123,
1590         NVME_SC_ANA_GROUP_ID_INVALID    = 0x124,
1591         NVME_SC_ANA_ATTACH_FAILED       = 0x125,
1592
1593         /*
1594          * I/O Command Set Specific - NVM commands:
1595          */
1596         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1597         NVME_SC_INVALID_PI              = 0x181,
1598         NVME_SC_READ_ONLY               = 0x182,
1599         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1600
1601         /*
1602          * I/O Command Set Specific - Fabrics commands:
1603          */
1604         NVME_SC_CONNECT_FORMAT          = 0x180,
1605         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1606         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1607         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1608         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1609
1610         NVME_SC_DISCOVERY_RESTART       = 0x190,
1611         NVME_SC_AUTH_REQUIRED           = 0x191,
1612
1613         /*
1614          * I/O Command Set Specific - Zoned commands:
1615          */
1616         NVME_SC_ZONE_BOUNDARY_ERROR     = 0x1b8,
1617         NVME_SC_ZONE_FULL               = 0x1b9,
1618         NVME_SC_ZONE_READ_ONLY          = 0x1ba,
1619         NVME_SC_ZONE_OFFLINE            = 0x1bb,
1620         NVME_SC_ZONE_INVALID_WRITE      = 0x1bc,
1621         NVME_SC_ZONE_TOO_MANY_ACTIVE    = 0x1bd,
1622         NVME_SC_ZONE_TOO_MANY_OPEN      = 0x1be,
1623         NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1624
1625         /*
1626          * Media and Data Integrity Errors:
1627          */
1628         NVME_SC_WRITE_FAULT             = 0x280,
1629         NVME_SC_READ_ERROR              = 0x281,
1630         NVME_SC_GUARD_CHECK             = 0x282,
1631         NVME_SC_APPTAG_CHECK            = 0x283,
1632         NVME_SC_REFTAG_CHECK            = 0x284,
1633         NVME_SC_COMPARE_FAILED          = 0x285,
1634         NVME_SC_ACCESS_DENIED           = 0x286,
1635         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1636
1637         /*
1638          * Path-related Errors:
1639          */
1640         NVME_SC_ANA_PERSISTENT_LOSS     = 0x301,
1641         NVME_SC_ANA_INACCESSIBLE        = 0x302,
1642         NVME_SC_ANA_TRANSITION          = 0x303,
1643         NVME_SC_HOST_PATH_ERROR         = 0x370,
1644         NVME_SC_HOST_ABORTED_CMD        = 0x371,
1645
1646         NVME_SC_CRD                     = 0x1800,
1647         NVME_SC_MORE                    = 0x2000,
1648         NVME_SC_DNR                     = 0x4000,
1649 };
1650
1651 struct nvme_completion {
1652         /*
1653          * Used by Admin and Fabrics commands to return data:
1654          */
1655         union nvme_result {
1656                 __le16  u16;
1657                 __le32  u32;
1658                 __le64  u64;
1659         } result;
1660         __le16  sq_head;        /* how much of this queue may be reclaimed */
1661         __le16  sq_id;          /* submission queue that generated this entry */
1662         __u16   command_id;     /* of the command which completed */
1663         __le16  status;         /* did the command fail, and if so, why? */
1664 };
1665
1666 #define NVME_VS(major, minor, tertiary) \
1667         (((major) << 16) | ((minor) << 8) | (tertiary))
1668
1669 #define NVME_MAJOR(ver)         ((ver) >> 16)
1670 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
1671 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
1672
1673 #endif /* _LINUX_NVME_H */