include/linux/nvme.h

   1 /*
   2  * Definitions for the NVM Express interface
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #ifndef _LINUX_NVME_H
  20 #define _LINUX_NVME_H
  21
  22 #include <linux/types.h>
  23
  24 struct nvme_bar {
  25         __u64                   cap;    /* Controller Capabilities */
  26         __u32                   vs;     /* Version */
  27         __u32                   intms;  /* Interrupt Mask Set */
  28         __u32                   intmc;  /* Interrupt Mask Clear */
  29         __u32                   cc;     /* Controller Configuration */
  30         __u32                   rsvd1;  /* Reserved */
  31         __u32                   csts;   /* Controller Status */
  32         __u32                   rsvd2;  /* Reserved */
  33         __u32                   aqa;    /* Admin Queue Attributes */
  34         __u64                   asq;    /* Admin SQ Base Address */
  35         __u64                   acq;    /* Admin CQ Base Address */
  36 };
  37
  38 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
  39 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
  40
  41 enum {
  42         NVME_CC_ENABLE          = 1 << 0,
  43         NVME_CC_CSS_NVM         = 0 << 4,
  44         NVME_CC_MPS_SHIFT       = 7,
  45         NVME_CC_ARB_RR          = 0 << 11,
  46         NVME_CC_ARB_WRRU        = 1 << 11,
  47         NVME_CC_ARB_VS          = 7 << 11,
  48         NVME_CC_SHN_NONE        = 0 << 14,
  49         NVME_CC_SHN_NORMAL      = 1 << 14,
  50         NVME_CC_SHN_ABRUPT      = 2 << 14,
  51         NVME_CC_IOSQES          = 6 << 16,
  52         NVME_CC_IOCQES          = 4 << 20,
  53         NVME_CSTS_RDY           = 1 << 0,
  54         NVME_CSTS_CFS           = 1 << 1,
  55         NVME_CSTS_SHST_NORMAL   = 0 << 2,
  56         NVME_CSTS_SHST_OCCUR    = 1 << 2,
  57         NVME_CSTS_SHST_CMPLT    = 2 << 2,
  58 };
  59
  60 struct nvme_id_power_state {
  61         __le16                  max_power;      /* centiwatts */
  62         __u16                   rsvd2;
  63         __le32                  entry_lat;      /* microseconds */
  64         __le32                  exit_lat;       /* microseconds */
  65         __u8                    read_tput;
  66         __u8                    read_lat;
  67         __u8                    write_tput;
  68         __u8                    write_lat;
  69         __u8                    rsvd16[16];
  70 };
  71
  72 #define NVME_VS(major, minor)   (major << 16 | minor)
  73
  74 struct nvme_id_ctrl {
  75         __le16                  vid;
  76         __le16                  ssvid;
  77         char                    sn[20];
  78         char                    mn[40];
  79         char                    fr[8];
  80         __u8                    rab;
  81         __u8                    ieee[3];
  82         __u8                    mic;
  83         __u8                    mdts;
  84         __u8                    rsvd78[178];
  85         __le16                  oacs;
  86         __u8                    acl;
  87         __u8                    aerl;
  88         __u8                    frmw;
  89         __u8                    lpa;
  90         __u8                    elpe;
  91         __u8                    npss;
  92         __u8                    rsvd264[248];
  93         __u8                    sqes;
  94         __u8                    cqes;
  95         __u8                    rsvd514[2];
  96         __le32                  nn;
  97         __le16                  oncs;
  98         __le16                  fuses;
  99         __u8                    fna;
 100         __u8                    vwc;
 101         __le16                  awun;
 102         __le16                  awupf;
 103         __u8                    rsvd530[1518];
 104         struct nvme_id_power_state      psd[32];
 105         __u8                    vs[1024];
 106 };
 107
 108 struct nvme_lbaf {
 109         __le16                  ms;
 110         __u8                    ds;
 111         __u8                    rp;
 112 };
 113
 114 struct nvme_id_ns {
 115         __le64                  nsze;
 116         __le64                  ncap;
 117         __le64                  nuse;
 118         __u8                    nsfeat;
 119         __u8                    nlbaf;
 120         __u8                    flbas;
 121         __u8                    mc;
 122         __u8                    dpc;
 123         __u8                    dps;
 124         __u8                    rsvd30[98];
 125         struct nvme_lbaf        lbaf[16];
 126         __u8                    rsvd192[192];
 127         __u8                    vs[3712];
 128 };
 129
 130 enum {
 131         NVME_NS_FEAT_THIN       = 1 << 0,
 132         NVME_LBAF_RP_BEST       = 0,
 133         NVME_LBAF_RP_BETTER     = 1,
 134         NVME_LBAF_RP_GOOD       = 2,
 135         NVME_LBAF_RP_DEGRADED   = 3,
 136 };
 137
 138 struct nvme_lba_range_type {
 139         __u8                    type;
 140         __u8                    attributes;
 141         __u8                    rsvd2[14];
 142         __u64                   slba;
 143         __u64                   nlb;
 144         __u8                    guid[16];
 145         __u8                    rsvd48[16];
 146 };
 147
 148 enum {
 149         NVME_LBART_TYPE_FS      = 0x01,
 150         NVME_LBART_TYPE_RAID    = 0x02,
 151         NVME_LBART_TYPE_CACHE   = 0x03,
 152         NVME_LBART_TYPE_SWAP    = 0x04,
 153
 154         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 155         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 156 };
 157
 158 /* I/O commands */
 159
 160 enum nvme_opcode {
 161         nvme_cmd_flush          = 0x00,
 162         nvme_cmd_write          = 0x01,
 163         nvme_cmd_read           = 0x02,
 164         nvme_cmd_write_uncor    = 0x04,
 165         nvme_cmd_compare        = 0x05,
 166         nvme_cmd_dsm            = 0x09,
 167 };
 168
 169 struct nvme_common_command {
 170         __u8                    opcode;
 171         __u8                    flags;
 172         __u16                   command_id;
 173         __le32                  nsid;
 174         __u32                   cdw2[2];
 175         __le64                  metadata;
 176         __le64                  prp1;
 177         __le64                  prp2;
 178         __u32                   cdw10[6];
 179 };
 180
 181 struct nvme_rw_command {
 182         __u8                    opcode;
 183         __u8                    flags;
 184         __u16                   command_id;
 185         __le32                  nsid;
 186         __u64                   rsvd2;
 187         __le64                  metadata;
 188         __le64                  prp1;
 189         __le64                  prp2;
 190         __le64                  slba;
 191         __le16                  length;
 192         __le16                  control;
 193         __le32                  dsmgmt;
 194         __le32                  reftag;
 195         __le16                  apptag;
 196         __le16                  appmask;
 197 };
 198
 199 enum {
 200         NVME_RW_LR                      = 1 << 15,
 201         NVME_RW_FUA                     = 1 << 14,
 202         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 203         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 204         NVME_RW_DSM_FREQ_RARE           = 2,
 205         NVME_RW_DSM_FREQ_READS          = 3,
 206         NVME_RW_DSM_FREQ_WRITES         = 4,
 207         NVME_RW_DSM_FREQ_RW             = 5,
 208         NVME_RW_DSM_FREQ_ONCE           = 6,
 209         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 210         NVME_RW_DSM_FREQ_TEMP           = 8,
 211         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 212         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 213         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 214         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 215         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 216         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 217 };
 218
 219 /* Admin commands */
 220
 221 enum nvme_admin_opcode {
 222         nvme_admin_delete_sq            = 0x00,
 223         nvme_admin_create_sq            = 0x01,
 224         nvme_admin_get_log_page         = 0x02,
 225         nvme_admin_delete_cq            = 0x04,
 226         nvme_admin_create_cq            = 0x05,
 227         nvme_admin_identify             = 0x06,
 228         nvme_admin_abort_cmd            = 0x08,
 229         nvme_admin_set_features         = 0x09,
 230         nvme_admin_get_features         = 0x0a,
 231         nvme_admin_async_event          = 0x0c,
 232         nvme_admin_activate_fw          = 0x10,
 233         nvme_admin_download_fw          = 0x11,
 234         nvme_admin_format_nvm           = 0x80,
 235         nvme_admin_security_send        = 0x81,
 236         nvme_admin_security_recv        = 0x82,
 237 };
 238
 239 enum {
 240         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
 241         NVME_CQ_IRQ_ENABLED     = (1 << 1),
 242         NVME_SQ_PRIO_URGENT     = (0 << 1),
 243         NVME_SQ_PRIO_HIGH       = (1 << 1),
 244         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
 245         NVME_SQ_PRIO_LOW        = (3 << 1),
 246         NVME_FEAT_ARBITRATION   = 0x01,
 247         NVME_FEAT_POWER_MGMT    = 0x02,
 248         NVME_FEAT_LBA_RANGE     = 0x03,
 249         NVME_FEAT_TEMP_THRESH   = 0x04,
 250         NVME_FEAT_ERR_RECOVERY  = 0x05,
 251         NVME_FEAT_VOLATILE_WC   = 0x06,
 252         NVME_FEAT_NUM_QUEUES    = 0x07,
 253         NVME_FEAT_IRQ_COALESCE  = 0x08,
 254         NVME_FEAT_IRQ_CONFIG    = 0x09,
 255         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
 256         NVME_FEAT_ASYNC_EVENT   = 0x0b,
 257         NVME_FEAT_SW_PROGRESS   = 0x0c,
 258 };
 259
 260 struct nvme_identify {
 261         __u8                    opcode;
 262         __u8                    flags;
 263         __u16                   command_id;
 264         __le32                  nsid;
 265         __u64                   rsvd2[2];
 266         __le64                  prp1;
 267         __le64                  prp2;
 268         __le32                  cns;
 269         __u32                   rsvd11[5];
 270 };
 271
 272 struct nvme_features {
 273         __u8                    opcode;
 274         __u8                    flags;
 275         __u16                   command_id;
 276         __le32                  nsid;
 277         __u64                   rsvd2[2];
 278         __le64                  prp1;
 279         __le64                  prp2;
 280         __le32                  fid;
 281         __le32                  dword11;
 282         __u32                   rsvd12[4];
 283 };
 284
 285 struct nvme_create_cq {
 286         __u8                    opcode;
 287         __u8                    flags;
 288         __u16                   command_id;
 289         __u32                   rsvd1[5];
 290         __le64                  prp1;
 291         __u64                   rsvd8;
 292         __le16                  cqid;
 293         __le16                  qsize;
 294         __le16                  cq_flags;
 295         __le16                  irq_vector;
 296         __u32                   rsvd12[4];
 297 };
 298
 299 struct nvme_create_sq {
 300         __u8                    opcode;
 301         __u8                    flags;
 302         __u16                   command_id;
 303         __u32                   rsvd1[5];
 304         __le64                  prp1;
 305         __u64                   rsvd8;
 306         __le16                  sqid;
 307         __le16                  qsize;
 308         __le16                  sq_flags;
 309         __le16                  cqid;
 310         __u32                   rsvd12[4];
 311 };
 312
 313 struct nvme_delete_queue {
 314         __u8                    opcode;
 315         __u8                    flags;
 316         __u16                   command_id;
 317         __u32                   rsvd1[9];
 318         __le16                  qid;
 319         __u16                   rsvd10;
 320         __u32                   rsvd11[5];
 321 };
 322
 323 struct nvme_download_firmware {
 324         __u8                    opcode;
 325         __u8                    flags;
 326         __u16                   command_id;
 327         __u32                   rsvd1[5];
 328         __le64                  prp1;
 329         __le64                  prp2;
 330         __le32                  numd;
 331         __le32                  offset;
 332         __u32                   rsvd12[4];
 333 };
 334
 335 struct nvme_command {
 336         union {
 337                 struct nvme_common_command common;
 338                 struct nvme_rw_command rw;
 339                 struct nvme_identify identify;
 340                 struct nvme_features features;
 341                 struct nvme_create_cq create_cq;
 342                 struct nvme_create_sq create_sq;
 343                 struct nvme_delete_queue delete_queue;
 344                 struct nvme_download_firmware dlfw;
 345         };
 346 };
 347
 348 enum {
 349         NVME_SC_SUCCESS                 = 0x0,
 350         NVME_SC_INVALID_OPCODE          = 0x1,
 351         NVME_SC_INVALID_FIELD           = 0x2,
 352         NVME_SC_CMDID_CONFLICT          = 0x3,
 353         NVME_SC_DATA_XFER_ERROR         = 0x4,
 354         NVME_SC_POWER_LOSS              = 0x5,
 355         NVME_SC_INTERNAL                = 0x6,
 356         NVME_SC_ABORT_REQ               = 0x7,
 357         NVME_SC_ABORT_QUEUE             = 0x8,
 358         NVME_SC_FUSED_FAIL              = 0x9,
 359         NVME_SC_FUSED_MISSING           = 0xa,
 360         NVME_SC_INVALID_NS              = 0xb,
 361         NVME_SC_LBA_RANGE               = 0x80,
 362         NVME_SC_CAP_EXCEEDED            = 0x81,
 363         NVME_SC_NS_NOT_READY            = 0x82,
 364         NVME_SC_CQ_INVALID              = 0x100,
 365         NVME_SC_QID_INVALID             = 0x101,
 366         NVME_SC_QUEUE_SIZE              = 0x102,
 367         NVME_SC_ABORT_LIMIT             = 0x103,
 368         NVME_SC_ABORT_MISSING           = 0x104,
 369         NVME_SC_ASYNC_LIMIT             = 0x105,
 370         NVME_SC_FIRMWARE_SLOT           = 0x106,
 371         NVME_SC_FIRMWARE_IMAGE          = 0x107,
 372         NVME_SC_INVALID_VECTOR          = 0x108,
 373         NVME_SC_INVALID_LOG_PAGE        = 0x109,
 374         NVME_SC_INVALID_FORMAT          = 0x10a,
 375         NVME_SC_BAD_ATTRIBUTES          = 0x180,
 376         NVME_SC_WRITE_FAULT             = 0x280,
 377         NVME_SC_READ_ERROR              = 0x281,
 378         NVME_SC_GUARD_CHECK             = 0x282,
 379         NVME_SC_APPTAG_CHECK            = 0x283,
 380         NVME_SC_REFTAG_CHECK            = 0x284,
 381         NVME_SC_COMPARE_FAILED          = 0x285,
 382         NVME_SC_ACCESS_DENIED           = 0x286,
 383 };
 384
 385 struct nvme_completion {
 386         __le32  result;         /* Used by admin commands to return data */
 387         __u32   rsvd;
 388         __le16  sq_head;        /* how much of this queue may be reclaimed */
 389         __le16  sq_id;          /* submission queue that generated this entry */
 390         __u16   command_id;     /* of the command which completed */
 391         __le16  status;         /* did the command fail, and if so, why? */
 392 };
 393
 394 struct nvme_user_io {
 395         __u8    opcode;
 396         __u8    flags;
 397         __u16   control;
 398         __u16   nblocks;
 399         __u16   rsvd;
 400         __u64   metadata;
 401         __u64   addr;
 402         __u64   slba;
 403         __u32   dsmgmt;
 404         __u32   reftag;
 405         __u16   apptag;
 406         __u16   appmask;
 407 };
 408
 409 struct nvme_admin_cmd {
 410         __u8    opcode;
 411         __u8    flags;
 412         __u16   rsvd1;
 413         __u32   nsid;
 414         __u32   cdw2;
 415         __u32   cdw3;
 416         __u64   metadata;
 417         __u64   addr;
 418         __u32   metadata_len;
 419         __u32   data_len;
 420         __u32   cdw10;
 421         __u32   cdw11;
 422         __u32   cdw12;
 423         __u32   cdw13;
 424         __u32   cdw14;
 425         __u32   cdw15;
 426         __u32   timeout_ms;
 427         __u32   result;
 428 };
 429
 430 #define NVME_IOCTL_ID           _IO('N', 0x40)
 431 #define NVME_IOCTL_ADMIN_CMD    _IOWR('N', 0x41, struct nvme_admin_cmd)
 432 #define NVME_IOCTL_SUBMIT_IO    _IOW('N', 0x42, struct nvme_user_io)
 433
 434 #endif /* _LINUX_NVME_H */