include/linux/nvme.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Definitions for the NVM Express interface
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #ifndef _LINUX_NVME_H
   8 #define _LINUX_NVME_H
   9
  10 #include <linux/bits.h>
  11 #include <linux/types.h>
  12 #include <linux/uuid.h>
  13
  14 /* NQN names in commands fields specified one size */
  15 #define NVMF_NQN_FIELD_LEN      256
  16
  17 /* However the max length of a qualified name is another size */
  18 #define NVMF_NQN_SIZE           223
  19
  20 #define NVMF_TRSVCID_SIZE       32
  21 #define NVMF_TRADDR_SIZE        256
  22 #define NVMF_TSAS_SIZE          256
  23 #define NVMF_AUTH_HASH_LEN      64
  24
  25 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  26
  27 #define NVME_RDMA_IP_PORT       4420
  28
  29 #define NVME_NSID_ALL           0xffffffff
  30
  31 enum nvme_subsys_type {
  32         /* Referral to another discovery type target subsystem */
  33         NVME_NQN_DISC   = 1,
  34
  35         /* NVME type target subsystem */
  36         NVME_NQN_NVME   = 2,
  37
  38         /* Current discovery type target subsystem */
  39         NVME_NQN_CURR   = 3,
  40 };
  41
  42 enum nvme_ctrl_type {
  43         NVME_CTRL_IO    = 1,            /* I/O controller */
  44         NVME_CTRL_DISC  = 2,            /* Discovery controller */
  45         NVME_CTRL_ADMIN = 3,            /* Administrative controller */
  46 };
  47
  48 enum nvme_dctype {
  49         NVME_DCTYPE_NOT_REPORTED        = 0,
  50         NVME_DCTYPE_DDC                 = 1, /* Direct Discovery Controller */
  51         NVME_DCTYPE_CDC                 = 2, /* Central Discovery Controller */
  52 };
  53
  54 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  55 enum {
  56         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  57         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  58         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  59         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  60         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  61         NVMF_ADDR_FAMILY_LOOP   = 254,  /* Reserved for host usage */
  62         NVMF_ADDR_FAMILY_MAX,
  63 };
  64
  65 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  66 enum {
  67         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  68         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  69         NVMF_TRTYPE_TCP         = 3,    /* TCP/IP */
  70         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  71         NVMF_TRTYPE_MAX,
  72 };
  73
  74 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  75 enum {
  76         NVMF_TREQ_NOT_SPECIFIED = 0,            /* Not specified */
  77         NVMF_TREQ_REQUIRED      = 1,            /* Required */
  78         NVMF_TREQ_NOT_REQUIRED  = 2,            /* Not Required */
  79 #define NVME_TREQ_SECURE_CHANNEL_MASK \
  80         (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
  81
  82         NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),    /* Supports SQ flow control disable */
  83 };
  84
  85 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  86  * RDMA_QPTYPE field
  87  */
  88 enum {
  89         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
  90         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
  91 };
  92
  93 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  94  * RDMA_QPTYPE field
  95  */
  96 enum {
  97         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
  98         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
  99         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
 100         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
 101         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
 102 };
 103
 104 /* RDMA Connection Management Service Type codes for Discovery Log Page
 105  * entry TSAS RDMA_CMS field
 106  */
 107 enum {
 108         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
 109 };
 110
 111 #define NVME_AQ_DEPTH           32
 112 #define NVME_NR_AEN_COMMANDS    1
 113 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
 114
 115 /*
 116  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
 117  * NVM-Express 1.2 specification, section 4.1.2.
 118  */
 119 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
 120
 121 enum {
 122         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
 123         NVME_REG_VS     = 0x0008,       /* Version */
 124         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
 125         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
 126         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
 127         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
 128         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
 129         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 130         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 131         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 132         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 133         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 134         NVME_REG_BPINFO = 0x0040,       /* Boot Partition Information */
 135         NVME_REG_BPRSEL = 0x0044,       /* Boot Partition Read Select */
 136         NVME_REG_BPMBL  = 0x0048,       /* Boot Partition Memory Buffer
 137                                          * Location
 138                                          */
 139         NVME_REG_CMBMSC = 0x0050,       /* Controller Memory Buffer Memory
 140                                          * Space Control
 141                                          */
 142         NVME_REG_CRTO   = 0x0068,       /* Controller Ready Timeouts */
 143         NVME_REG_PMRCAP = 0x0e00,       /* Persistent Memory Capabilities */
 144         NVME_REG_PMRCTL = 0x0e04,       /* Persistent Memory Region Control */
 145         NVME_REG_PMRSTS = 0x0e08,       /* Persistent Memory Region Status */
 146         NVME_REG_PMREBS = 0x0e0c,       /* Persistent Memory Region Elasticity
 147                                          * Buffer Size
 148                                          */
 149         NVME_REG_PMRSWTP = 0x0e10,      /* Persistent Memory Region Sustained
 150                                          * Write Throughput
 151                                          */
 152         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
 153 };
 154
 155 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 156 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 157 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 158 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 159 #define NVME_CAP_CSS(cap)       (((cap) >> 37) & 0xff)
 160 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 161 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 162 #define NVME_CAP_CMBS(cap)      (((cap) >> 57) & 0x1)
 163
 164 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 165 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 166
 167 #define NVME_CRTO_CRIMT(crto)   ((crto) >> 16)
 168 #define NVME_CRTO_CRWMT(crto)   ((crto) & 0xffff)
 169
 170 enum {
 171         NVME_CMBSZ_SQS          = 1 << 0,
 172         NVME_CMBSZ_CQS          = 1 << 1,
 173         NVME_CMBSZ_LISTS        = 1 << 2,
 174         NVME_CMBSZ_RDS          = 1 << 3,
 175         NVME_CMBSZ_WDS          = 1 << 4,
 176
 177         NVME_CMBSZ_SZ_SHIFT     = 12,
 178         NVME_CMBSZ_SZ_MASK      = 0xfffff,
 179
 180         NVME_CMBSZ_SZU_SHIFT    = 8,
 181         NVME_CMBSZ_SZU_MASK     = 0xf,
 182 };
 183
 184 /*
 185  * Submission and Completion Queue Entry Sizes for the NVM command set.
 186  * (In bytes and specified as a power of two (2^n)).
 187  */
 188 #define NVME_ADM_SQES       6
 189 #define NVME_NVM_IOSQES         6
 190 #define NVME_NVM_IOCQES         4
 191
 192 enum {
 193         NVME_CC_ENABLE          = 1 << 0,
 194         NVME_CC_EN_SHIFT        = 0,
 195         NVME_CC_CSS_SHIFT       = 4,
 196         NVME_CC_MPS_SHIFT       = 7,
 197         NVME_CC_AMS_SHIFT       = 11,
 198         NVME_CC_SHN_SHIFT       = 14,
 199         NVME_CC_IOSQES_SHIFT    = 16,
 200         NVME_CC_IOCQES_SHIFT    = 20,
 201         NVME_CC_CSS_NVM         = 0 << NVME_CC_CSS_SHIFT,
 202         NVME_CC_CSS_CSI         = 6 << NVME_CC_CSS_SHIFT,
 203         NVME_CC_CSS_MASK        = 7 << NVME_CC_CSS_SHIFT,
 204         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
 205         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
 206         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
 207         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
 208         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
 209         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
 210         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
 211         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
 212         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
 213         NVME_CC_CRIME           = 1 << 24,
 214 };
 215
 216 enum {
 217         NVME_CSTS_RDY           = 1 << 0,
 218         NVME_CSTS_CFS           = 1 << 1,
 219         NVME_CSTS_NSSRO         = 1 << 4,
 220         NVME_CSTS_PP            = 1 << 5,
 221         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 222         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 223         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 224         NVME_CSTS_SHST_MASK     = 3 << 2,
 225 };
 226
 227 enum {
 228         NVME_CMBMSC_CRE         = 1 << 0,
 229         NVME_CMBMSC_CMSE        = 1 << 1,
 230 };
 231
 232 enum {
 233         NVME_CAP_CSS_NVM        = 1 << 0,
 234         NVME_CAP_CSS_CSI        = 1 << 6,
 235 };
 236
 237 enum {
 238         NVME_CAP_CRMS_CRWMS     = 1ULL << 59,
 239         NVME_CAP_CRMS_CRIMS     = 1ULL << 60,
 240 };
 241
 242 struct nvme_id_power_state {
 243         __le16                  max_power;      /* centiwatts */
 244         __u8                    rsvd2;
 245         __u8                    flags;
 246         __le32                  entry_lat;      /* microseconds */
 247         __le32                  exit_lat;       /* microseconds */
 248         __u8                    read_tput;
 249         __u8                    read_lat;
 250         __u8                    write_tput;
 251         __u8                    write_lat;
 252         __le16                  idle_power;
 253         __u8                    idle_scale;
 254         __u8                    rsvd19;
 255         __le16                  active_power;
 256         __u8                    active_work_scale;
 257         __u8                    rsvd23[9];
 258 };
 259
 260 enum {
 261         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 262         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 263 };
 264
 265 enum nvme_ctrl_attr {
 266         NVME_CTRL_ATTR_HID_128_BIT      = (1 << 0),
 267         NVME_CTRL_ATTR_TBKAS            = (1 << 6),
 268         NVME_CTRL_ATTR_ELBAS            = (1 << 15),
 269 };
 270
 271 struct nvme_id_ctrl {
 272         __le16                  vid;
 273         __le16                  ssvid;
 274         char                    sn[20];
 275         char                    mn[40];
 276         char                    fr[8];
 277         __u8                    rab;
 278         __u8                    ieee[3];
 279         __u8                    cmic;
 280         __u8                    mdts;
 281         __le16                  cntlid;
 282         __le32                  ver;
 283         __le32                  rtd3r;
 284         __le32                  rtd3e;
 285         __le32                  oaes;
 286         __le32                  ctratt;
 287         __u8                    rsvd100[11];
 288         __u8                    cntrltype;
 289         __u8                    fguid[16];
 290         __le16                  crdt1;
 291         __le16                  crdt2;
 292         __le16                  crdt3;
 293         __u8                    rsvd134[122];
 294         __le16                  oacs;
 295         __u8                    acl;
 296         __u8                    aerl;
 297         __u8                    frmw;
 298         __u8                    lpa;
 299         __u8                    elpe;
 300         __u8                    npss;
 301         __u8                    avscc;
 302         __u8                    apsta;
 303         __le16                  wctemp;
 304         __le16                  cctemp;
 305         __le16                  mtfa;
 306         __le32                  hmpre;
 307         __le32                  hmmin;
 308         __u8                    tnvmcap[16];
 309         __u8                    unvmcap[16];
 310         __le32                  rpmbs;
 311         __le16                  edstt;
 312         __u8                    dsto;
 313         __u8                    fwug;
 314         __le16                  kas;
 315         __le16                  hctma;
 316         __le16                  mntmt;
 317         __le16                  mxtmt;
 318         __le32                  sanicap;
 319         __le32                  hmminds;
 320         __le16                  hmmaxd;
 321         __u8                    rsvd338[4];
 322         __u8                    anatt;
 323         __u8                    anacap;
 324         __le32                  anagrpmax;
 325         __le32                  nanagrpid;
 326         __u8                    rsvd352[160];
 327         __u8                    sqes;
 328         __u8                    cqes;
 329         __le16                  maxcmd;
 330         __le32                  nn;
 331         __le16                  oncs;
 332         __le16                  fuses;
 333         __u8                    fna;
 334         __u8                    vwc;
 335         __le16                  awun;
 336         __le16                  awupf;
 337         __u8                    nvscc;
 338         __u8                    nwpc;
 339         __le16                  acwu;
 340         __u8                    rsvd534[2];
 341         __le32                  sgls;
 342         __le32                  mnan;
 343         __u8                    rsvd544[224];
 344         char                    subnqn[256];
 345         __u8                    rsvd1024[768];
 346         __le32                  ioccsz;
 347         __le32                  iorcsz;
 348         __le16                  icdoff;
 349         __u8                    ctrattr;
 350         __u8                    msdbd;
 351         __u8                    rsvd1804[2];
 352         __u8                    dctype;
 353         __u8                    rsvd1807[241];
 354         struct nvme_id_power_state      psd[32];
 355         __u8                    vs[1024];
 356 };
 357
 358 enum {
 359         NVME_CTRL_CMIC_MULTI_PORT               = 1 << 0,
 360         NVME_CTRL_CMIC_MULTI_CTRL               = 1 << 1,
 361         NVME_CTRL_CMIC_ANA                      = 1 << 3,
 362         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 363         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 364         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 365         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 366         NVME_CTRL_ONCS_RESERVATIONS             = 1 << 5,
 367         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
 368         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 369         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
 370         NVME_CTRL_OACS_NS_MNGT_SUPP             = 1 << 3,
 371         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
 372         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
 373         NVME_CTRL_LPA_CMD_EFFECTS_LOG           = 1 << 1,
 374         NVME_CTRL_CTRATT_128_ID                 = 1 << 0,
 375         NVME_CTRL_CTRATT_NON_OP_PSP             = 1 << 1,
 376         NVME_CTRL_CTRATT_NVM_SETS               = 1 << 2,
 377         NVME_CTRL_CTRATT_READ_RECV_LVLS         = 1 << 3,
 378         NVME_CTRL_CTRATT_ENDURANCE_GROUPS       = 1 << 4,
 379         NVME_CTRL_CTRATT_PREDICTABLE_LAT        = 1 << 5,
 380         NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY  = 1 << 7,
 381         NVME_CTRL_CTRATT_UUID_LIST              = 1 << 9,
 382 };
 383
 384 struct nvme_lbaf {
 385         __le16                  ms;
 386         __u8                    ds;
 387         __u8                    rp;
 388 };
 389
 390 struct nvme_id_ns {
 391         __le64                  nsze;
 392         __le64                  ncap;
 393         __le64                  nuse;
 394         __u8                    nsfeat;
 395         __u8                    nlbaf;
 396         __u8                    flbas;
 397         __u8                    mc;
 398         __u8                    dpc;
 399         __u8                    dps;
 400         __u8                    nmic;
 401         __u8                    rescap;
 402         __u8                    fpi;
 403         __u8                    dlfeat;
 404         __le16                  nawun;
 405         __le16                  nawupf;
 406         __le16                  nacwu;
 407         __le16                  nabsn;
 408         __le16                  nabo;
 409         __le16                  nabspf;
 410         __le16                  noiob;
 411         __u8                    nvmcap[16];
 412         __le16                  npwg;
 413         __le16                  npwa;
 414         __le16                  npdg;
 415         __le16                  npda;
 416         __le16                  nows;
 417         __u8                    rsvd74[18];
 418         __le32                  anagrpid;
 419         __u8                    rsvd96[3];
 420         __u8                    nsattr;
 421         __le16                  nvmsetid;
 422         __le16                  endgid;
 423         __u8                    nguid[16];
 424         __u8                    eui64[8];
 425         struct nvme_lbaf        lbaf[64];
 426         __u8                    vs[3712];
 427 };
 428
 429 /* I/O Command Set Independent Identify Namespace Data Structure */
 430 struct nvme_id_ns_cs_indep {
 431         __u8                    nsfeat;
 432         __u8                    nmic;
 433         __u8                    rescap;
 434         __u8                    fpi;
 435         __le32                  anagrpid;
 436         __u8                    nsattr;
 437         __u8                    rsvd9;
 438         __le16                  nvmsetid;
 439         __le16                  endgid;
 440         __u8                    nstat;
 441         __u8                    rsvd15[4081];
 442 };
 443
 444 struct nvme_zns_lbafe {
 445         __le64                  zsze;
 446         __u8                    zdes;
 447         __u8                    rsvd9[7];
 448 };
 449
 450 struct nvme_id_ns_zns {
 451         __le16                  zoc;
 452         __le16                  ozcs;
 453         __le32                  mar;
 454         __le32                  mor;
 455         __le32                  rrl;
 456         __le32                  frl;
 457         __u8                    rsvd20[2796];
 458         struct nvme_zns_lbafe   lbafe[64];
 459         __u8                    vs[256];
 460 };
 461
 462 struct nvme_id_ctrl_zns {
 463         __u8    zasl;
 464         __u8    rsvd1[4095];
 465 };
 466
 467 struct nvme_id_ns_nvm {
 468         __le64  lbstm;
 469         __u8    pic;
 470         __u8    rsvd9[3];
 471         __le32  elbaf[64];
 472         __u8    rsvd268[3828];
 473 };
 474
 475 enum {
 476         NVME_ID_NS_NVM_STS_MASK         = 0x7f,
 477         NVME_ID_NS_NVM_GUARD_SHIFT      = 7,
 478         NVME_ID_NS_NVM_GUARD_MASK       = 0x3,
 479 };
 480
 481 static inline __u8 nvme_elbaf_sts(__u32 elbaf)
 482 {
 483         return elbaf & NVME_ID_NS_NVM_STS_MASK;
 484 }
 485
 486 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
 487 {
 488         return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
 489 }
 490
 491 struct nvme_id_ctrl_nvm {
 492         __u8    vsl;
 493         __u8    wzsl;
 494         __u8    wusl;
 495         __u8    dmrl;
 496         __le32  dmrsl;
 497         __le64  dmsl;
 498         __u8    rsvd16[4080];
 499 };
 500
 501 enum {
 502         NVME_ID_CNS_NS                  = 0x00,
 503         NVME_ID_CNS_CTRL                = 0x01,
 504         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 505         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
 506         NVME_ID_CNS_CS_NS               = 0x05,
 507         NVME_ID_CNS_CS_CTRL             = 0x06,
 508         NVME_ID_CNS_NS_CS_INDEP         = 0x08,
 509         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 510         NVME_ID_CNS_NS_PRESENT          = 0x11,
 511         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 512         NVME_ID_CNS_CTRL_LIST           = 0x13,
 513         NVME_ID_CNS_SCNDRY_CTRL_LIST    = 0x15,
 514         NVME_ID_CNS_NS_GRANULARITY      = 0x16,
 515         NVME_ID_CNS_UUID_LIST           = 0x17,
 516 };
 517
 518 enum {
 519         NVME_CSI_NVM                    = 0,
 520         NVME_CSI_ZNS                    = 2,
 521 };
 522
 523 enum {
 524         NVME_DIR_IDENTIFY               = 0x00,
 525         NVME_DIR_STREAMS                = 0x01,
 526         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
 527         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
 528         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
 529         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
 530         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
 531         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
 532         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
 533         NVME_DIR_ENDIR                  = 0x01,
 534 };
 535
 536 enum {
 537         NVME_NS_FEAT_THIN       = 1 << 0,
 538         NVME_NS_FEAT_ATOMICS    = 1 << 1,
 539         NVME_NS_FEAT_IO_OPT     = 1 << 4,
 540         NVME_NS_ATTR_RO         = 1 << 0,
 541         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 542         NVME_NS_FLBAS_LBA_UMASK = 0x60,
 543         NVME_NS_FLBAS_LBA_SHIFT = 1,
 544         NVME_NS_FLBAS_META_EXT  = 0x10,
 545         NVME_NS_NMIC_SHARED     = 1 << 0,
 546         NVME_LBAF_RP_BEST       = 0,
 547         NVME_LBAF_RP_BETTER     = 1,
 548         NVME_LBAF_RP_GOOD       = 2,
 549         NVME_LBAF_RP_DEGRADED   = 3,
 550         NVME_NS_DPC_PI_LAST     = 1 << 4,
 551         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 552         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 553         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 554         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 555         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 556         NVME_NS_DPS_PI_MASK     = 0x7,
 557         NVME_NS_DPS_PI_TYPE1    = 1,
 558         NVME_NS_DPS_PI_TYPE2    = 2,
 559         NVME_NS_DPS_PI_TYPE3    = 3,
 560 };
 561
 562 enum {
 563         NVME_NSTAT_NRDY         = 1 << 0,
 564 };
 565
 566 enum {
 567         NVME_NVM_NS_16B_GUARD   = 0,
 568         NVME_NVM_NS_32B_GUARD   = 1,
 569         NVME_NVM_NS_64B_GUARD   = 2,
 570 };
 571
 572 static inline __u8 nvme_lbaf_index(__u8 flbas)
 573 {
 574         return (flbas & NVME_NS_FLBAS_LBA_MASK) |
 575                 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
 576 }
 577
 578 /* Identify Namespace Metadata Capabilities (MC): */
 579 enum {
 580         NVME_MC_EXTENDED_LBA    = (1 << 0),
 581         NVME_MC_METADATA_PTR    = (1 << 1),
 582 };
 583
 584 struct nvme_ns_id_desc {
 585         __u8 nidt;
 586         __u8 nidl;
 587         __le16 reserved;
 588 };
 589
 590 #define NVME_NIDT_EUI64_LEN     8
 591 #define NVME_NIDT_NGUID_LEN     16
 592 #define NVME_NIDT_UUID_LEN      16
 593 #define NVME_NIDT_CSI_LEN       1
 594
 595 enum {
 596         NVME_NIDT_EUI64         = 0x01,
 597         NVME_NIDT_NGUID         = 0x02,
 598         NVME_NIDT_UUID          = 0x03,
 599         NVME_NIDT_CSI           = 0x04,
 600 };
 601
 602 struct nvme_smart_log {
 603         __u8                    critical_warning;
 604         __u8                    temperature[2];
 605         __u8                    avail_spare;
 606         __u8                    spare_thresh;
 607         __u8                    percent_used;
 608         __u8                    endu_grp_crit_warn_sumry;
 609         __u8                    rsvd7[25];
 610         __u8                    data_units_read[16];
 611         __u8                    data_units_written[16];
 612         __u8                    host_reads[16];
 613         __u8                    host_writes[16];
 614         __u8                    ctrl_busy_time[16];
 615         __u8                    power_cycles[16];
 616         __u8                    power_on_hours[16];
 617         __u8                    unsafe_shutdowns[16];
 618         __u8                    media_errors[16];
 619         __u8                    num_err_log_entries[16];
 620         __le32                  warning_temp_time;
 621         __le32                  critical_comp_time;
 622         __le16                  temp_sensor[8];
 623         __le32                  thm_temp1_trans_count;
 624         __le32                  thm_temp2_trans_count;
 625         __le32                  thm_temp1_total_time;
 626         __le32                  thm_temp2_total_time;
 627         __u8                    rsvd232[280];
 628 };
 629
 630 struct nvme_fw_slot_info_log {
 631         __u8                    afi;
 632         __u8                    rsvd1[7];
 633         __le64                  frs[7];
 634         __u8                    rsvd64[448];
 635 };
 636
 637 enum {
 638         NVME_CMD_EFFECTS_CSUPP          = 1 << 0,
 639         NVME_CMD_EFFECTS_LBCC           = 1 << 1,
 640         NVME_CMD_EFFECTS_NCC            = 1 << 2,
 641         NVME_CMD_EFFECTS_NIC            = 1 << 3,
 642         NVME_CMD_EFFECTS_CCC            = 1 << 4,
 643         NVME_CMD_EFFECTS_CSE_MASK       = GENMASK(18, 16),
 644         NVME_CMD_EFFECTS_UUID_SEL       = 1 << 19,
 645         NVME_CMD_EFFECTS_SCOPE_MASK     = GENMASK(31, 20),
 646 };
 647
 648 struct nvme_effects_log {
 649         __le32 acs[256];
 650         __le32 iocs[256];
 651         __u8   resv[2048];
 652 };
 653
 654 enum nvme_ana_state {
 655         NVME_ANA_OPTIMIZED              = 0x01,
 656         NVME_ANA_NONOPTIMIZED           = 0x02,
 657         NVME_ANA_INACCESSIBLE           = 0x03,
 658         NVME_ANA_PERSISTENT_LOSS        = 0x04,
 659         NVME_ANA_CHANGE                 = 0x0f,
 660 };
 661
 662 struct nvme_ana_group_desc {
 663         __le32  grpid;
 664         __le32  nnsids;
 665         __le64  chgcnt;
 666         __u8    state;
 667         __u8    rsvd17[15];
 668         __le32  nsids[];
 669 };
 670
 671 /* flag for the log specific field of the ANA log */
 672 #define NVME_ANA_LOG_RGO        (1 << 0)
 673
 674 struct nvme_ana_rsp_hdr {
 675         __le64  chgcnt;
 676         __le16  ngrps;
 677         __le16  rsvd10[3];
 678 };
 679
 680 struct nvme_zone_descriptor {
 681         __u8            zt;
 682         __u8            zs;
 683         __u8            za;
 684         __u8            rsvd3[5];
 685         __le64          zcap;
 686         __le64          zslba;
 687         __le64          wp;
 688         __u8            rsvd32[32];
 689 };
 690
 691 enum {
 692         NVME_ZONE_TYPE_SEQWRITE_REQ     = 0x2,
 693 };
 694
 695 struct nvme_zone_report {
 696         __le64          nr_zones;
 697         __u8            resv8[56];
 698         struct nvme_zone_descriptor entries[];
 699 };
 700
 701 enum {
 702         NVME_SMART_CRIT_SPARE           = 1 << 0,
 703         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 704         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 705         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 706         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 707 };
 708
 709 enum {
 710         NVME_AER_ERROR                  = 0,
 711         NVME_AER_SMART                  = 1,
 712         NVME_AER_NOTICE                 = 2,
 713         NVME_AER_CSS                    = 6,
 714         NVME_AER_VS                     = 7,
 715 };
 716
 717 enum {
 718         NVME_AER_ERROR_PERSIST_INT_ERR  = 0x03,
 719 };
 720
 721 enum {
 722         NVME_AER_NOTICE_NS_CHANGED      = 0x00,
 723         NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
 724         NVME_AER_NOTICE_ANA             = 0x03,
 725         NVME_AER_NOTICE_DISC_CHANGED    = 0xf0,
 726 };
 727
 728 enum {
 729         NVME_AEN_BIT_NS_ATTR            = 8,
 730         NVME_AEN_BIT_FW_ACT             = 9,
 731         NVME_AEN_BIT_ANA_CHANGE         = 11,
 732         NVME_AEN_BIT_DISC_CHANGE        = 31,
 733 };
 734
 735 enum {
 736         NVME_AEN_CFG_NS_ATTR            = 1 << NVME_AEN_BIT_NS_ATTR,
 737         NVME_AEN_CFG_FW_ACT             = 1 << NVME_AEN_BIT_FW_ACT,
 738         NVME_AEN_CFG_ANA_CHANGE         = 1 << NVME_AEN_BIT_ANA_CHANGE,
 739         NVME_AEN_CFG_DISC_CHANGE        = 1 << NVME_AEN_BIT_DISC_CHANGE,
 740 };
 741
 742 struct nvme_lba_range_type {
 743         __u8                    type;
 744         __u8                    attributes;
 745         __u8                    rsvd2[14];
 746         __le64                  slba;
 747         __le64                  nlb;
 748         __u8                    guid[16];
 749         __u8                    rsvd48[16];
 750 };
 751
 752 enum {
 753         NVME_LBART_TYPE_FS      = 0x01,
 754         NVME_LBART_TYPE_RAID    = 0x02,
 755         NVME_LBART_TYPE_CACHE   = 0x03,
 756         NVME_LBART_TYPE_SWAP    = 0x04,
 757
 758         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 759         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 760 };
 761
 762 enum nvme_pr_type {
 763         NVME_PR_WRITE_EXCLUSIVE                 = 1,
 764         NVME_PR_EXCLUSIVE_ACCESS                = 2,
 765         NVME_PR_WRITE_EXCLUSIVE_REG_ONLY        = 3,
 766         NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY       = 4,
 767         NVME_PR_WRITE_EXCLUSIVE_ALL_REGS        = 5,
 768         NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS       = 6,
 769 };
 770
 771 enum nvme_eds {
 772         NVME_EXTENDED_DATA_STRUCT       = 0x1,
 773 };
 774
 775 struct nvme_registered_ctrl {
 776         __le16  cntlid;
 777         __u8    rcsts;
 778         __u8    rsvd3[5];
 779         __le64  hostid;
 780         __le64  rkey;
 781 };
 782
 783 struct nvme_reservation_status {
 784         __le32  gen;
 785         __u8    rtype;
 786         __u8    regctl[2];
 787         __u8    resv5[2];
 788         __u8    ptpls;
 789         __u8    resv10[14];
 790         struct nvme_registered_ctrl regctl_ds[];
 791 };
 792
 793 struct nvme_registered_ctrl_ext {
 794         __le16  cntlid;
 795         __u8    rcsts;
 796         __u8    rsvd3[5];
 797         __le64  rkey;
 798         __u8    hostid[16];
 799         __u8    rsvd32[32];
 800 };
 801
 802 struct nvme_reservation_status_ext {
 803         __le32  gen;
 804         __u8    rtype;
 805         __u8    regctl[2];
 806         __u8    resv5[2];
 807         __u8    ptpls;
 808         __u8    resv10[14];
 809         __u8    rsvd24[40];
 810         struct nvme_registered_ctrl_ext regctl_eds[];
 811 };
 812
 813 enum nvme_async_event_type {
 814         NVME_AER_TYPE_ERROR     = 0,
 815         NVME_AER_TYPE_SMART     = 1,
 816         NVME_AER_TYPE_NOTICE    = 2,
 817 };
 818
 819 /* I/O commands */
 820
 821 enum nvme_opcode {
 822         nvme_cmd_flush          = 0x00,
 823         nvme_cmd_write          = 0x01,
 824         nvme_cmd_read           = 0x02,
 825         nvme_cmd_write_uncor    = 0x04,
 826         nvme_cmd_compare        = 0x05,
 827         nvme_cmd_write_zeroes   = 0x08,
 828         nvme_cmd_dsm            = 0x09,
 829         nvme_cmd_verify         = 0x0c,
 830         nvme_cmd_resv_register  = 0x0d,
 831         nvme_cmd_resv_report    = 0x0e,
 832         nvme_cmd_resv_acquire   = 0x11,
 833         nvme_cmd_resv_release   = 0x15,
 834         nvme_cmd_zone_mgmt_send = 0x79,
 835         nvme_cmd_zone_mgmt_recv = 0x7a,
 836         nvme_cmd_zone_append    = 0x7d,
 837         nvme_cmd_vendor_start   = 0x80,
 838 };
 839
 840 #define nvme_opcode_name(opcode)        { opcode, #opcode }
 841 #define show_nvm_opcode_name(val)                               \
 842         __print_symbolic(val,                                   \
 843                 nvme_opcode_name(nvme_cmd_flush),               \
 844                 nvme_opcode_name(nvme_cmd_write),               \
 845                 nvme_opcode_name(nvme_cmd_read),                \
 846                 nvme_opcode_name(nvme_cmd_write_uncor),         \
 847                 nvme_opcode_name(nvme_cmd_compare),             \
 848                 nvme_opcode_name(nvme_cmd_write_zeroes),        \
 849                 nvme_opcode_name(nvme_cmd_dsm),                 \
 850                 nvme_opcode_name(nvme_cmd_verify),              \
 851                 nvme_opcode_name(nvme_cmd_resv_register),       \
 852                 nvme_opcode_name(nvme_cmd_resv_report),         \
 853                 nvme_opcode_name(nvme_cmd_resv_acquire),        \
 854                 nvme_opcode_name(nvme_cmd_resv_release),        \
 855                 nvme_opcode_name(nvme_cmd_zone_mgmt_send),      \
 856                 nvme_opcode_name(nvme_cmd_zone_mgmt_recv),      \
 857                 nvme_opcode_name(nvme_cmd_zone_append))
 858
 859
 860
 861 /*
 862  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 863  *
 864  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 865  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 866  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
 867  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 868  *                            request subtype
 869  */
 870 enum {
 871         NVME_SGL_FMT_ADDRESS            = 0x00,
 872         NVME_SGL_FMT_OFFSET             = 0x01,
 873         NVME_SGL_FMT_TRANSPORT_A        = 0x0A,
 874         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 875 };
 876
 877 /*
 878  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 879  *
 880  * For struct nvme_sgl_desc:
 881  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 882  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 883  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 884  *
 885  * For struct nvme_keyed_sgl_desc:
 886  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 887  *
 888  * Transport-specific SGL types:
 889  *   @NVME_TRANSPORT_SGL_DATA_DESC:     Transport SGL data dlock descriptor
 890  */
 891 enum {
 892         NVME_SGL_FMT_DATA_DESC          = 0x00,
 893         NVME_SGL_FMT_SEG_DESC           = 0x02,
 894         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 895         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 896         NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
 897 };
 898
 899 struct nvme_sgl_desc {
 900         __le64  addr;
 901         __le32  length;
 902         __u8    rsvd[3];
 903         __u8    type;
 904 };
 905
 906 struct nvme_keyed_sgl_desc {
 907         __le64  addr;
 908         __u8    length[3];
 909         __u8    key[4];
 910         __u8    type;
 911 };
 912
 913 union nvme_data_ptr {
 914         struct {
 915                 __le64  prp1;
 916                 __le64  prp2;
 917         };
 918         struct nvme_sgl_desc    sgl;
 919         struct nvme_keyed_sgl_desc ksgl;
 920 };
 921
 922 /*
 923  * Lowest two bits of our flags field (FUSE field in the spec):
 924  *
 925  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 926  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 927  *
 928  * Highest two bits in our flags field (PSDT field in the spec):
 929  *
 930  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 931  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 932  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 933  *      If used, MPTR contains an address of an SGL segment containing
 934  *      exactly 1 SGL descriptor (qword aligned).
 935  */
 936 enum {
 937         NVME_CMD_FUSE_FIRST     = (1 << 0),
 938         NVME_CMD_FUSE_SECOND    = (1 << 1),
 939
 940         NVME_CMD_SGL_METABUF    = (1 << 6),
 941         NVME_CMD_SGL_METASEG    = (1 << 7),
 942         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 943 };
 944
 945 struct nvme_common_command {
 946         __u8                    opcode;
 947         __u8                    flags;
 948         __u16                   command_id;
 949         __le32                  nsid;
 950         __le32                  cdw2[2];
 951         __le64                  metadata;
 952         union nvme_data_ptr     dptr;
 953         struct_group(cdws,
 954         __le32                  cdw10;
 955         __le32                  cdw11;
 956         __le32                  cdw12;
 957         __le32                  cdw13;
 958         __le32                  cdw14;
 959         __le32                  cdw15;
 960         );
 961 };
 962
 963 struct nvme_rw_command {
 964         __u8                    opcode;
 965         __u8                    flags;
 966         __u16                   command_id;
 967         __le32                  nsid;
 968         __le32                  cdw2;
 969         __le32                  cdw3;
 970         __le64                  metadata;
 971         union nvme_data_ptr     dptr;
 972         __le64                  slba;
 973         __le16                  length;
 974         __le16                  control;
 975         __le32                  dsmgmt;
 976         __le32                  reftag;
 977         __le16                  apptag;
 978         __le16                  appmask;
 979 };
 980
 981 enum {
 982         NVME_RW_LR                      = 1 << 15,
 983         NVME_RW_FUA                     = 1 << 14,
 984         NVME_RW_APPEND_PIREMAP          = 1 << 9,
 985         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 986         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 987         NVME_RW_DSM_FREQ_RARE           = 2,
 988         NVME_RW_DSM_FREQ_READS          = 3,
 989         NVME_RW_DSM_FREQ_WRITES         = 4,
 990         NVME_RW_DSM_FREQ_RW             = 5,
 991         NVME_RW_DSM_FREQ_ONCE           = 6,
 992         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 993         NVME_RW_DSM_FREQ_TEMP           = 8,
 994         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 995         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 996         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 997         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 998         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 999         NVME_RW_DSM_COMPRESSED          = 1 << 7,
1000         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
1001         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
1002         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
1003         NVME_RW_PRINFO_PRACT            = 1 << 13,
1004         NVME_RW_DTYPE_STREAMS           = 1 << 4,
1005         NVME_WZ_DEAC                    = 1 << 9,
1006 };
1007
1008 struct nvme_dsm_cmd {
1009         __u8                    opcode;
1010         __u8                    flags;
1011         __u16                   command_id;
1012         __le32                  nsid;
1013         __u64                   rsvd2[2];
1014         union nvme_data_ptr     dptr;
1015         __le32                  nr;
1016         __le32                  attributes;
1017         __u32                   rsvd12[4];
1018 };
1019
1020 enum {
1021         NVME_DSMGMT_IDR         = 1 << 0,
1022         NVME_DSMGMT_IDW         = 1 << 1,
1023         NVME_DSMGMT_AD          = 1 << 2,
1024 };
1025
1026 #define NVME_DSM_MAX_RANGES     256
1027
1028 struct nvme_dsm_range {
1029         __le32                  cattr;
1030         __le32                  nlb;
1031         __le64                  slba;
1032 };
1033
1034 struct nvme_write_zeroes_cmd {
1035         __u8                    opcode;
1036         __u8                    flags;
1037         __u16                   command_id;
1038         __le32                  nsid;
1039         __u64                   rsvd2;
1040         __le64                  metadata;
1041         union nvme_data_ptr     dptr;
1042         __le64                  slba;
1043         __le16                  length;
1044         __le16                  control;
1045         __le32                  dsmgmt;
1046         __le32                  reftag;
1047         __le16                  apptag;
1048         __le16                  appmask;
1049 };
1050
1051 enum nvme_zone_mgmt_action {
1052         NVME_ZONE_CLOSE         = 0x1,
1053         NVME_ZONE_FINISH        = 0x2,
1054         NVME_ZONE_OPEN          = 0x3,
1055         NVME_ZONE_RESET         = 0x4,
1056         NVME_ZONE_OFFLINE       = 0x5,
1057         NVME_ZONE_SET_DESC_EXT  = 0x10,
1058 };
1059
1060 struct nvme_zone_mgmt_send_cmd {
1061         __u8                    opcode;
1062         __u8                    flags;
1063         __u16                   command_id;
1064         __le32                  nsid;
1065         __le32                  cdw2[2];
1066         __le64                  metadata;
1067         union nvme_data_ptr     dptr;
1068         __le64                  slba;
1069         __le32                  cdw12;
1070         __u8                    zsa;
1071         __u8                    select_all;
1072         __u8                    rsvd13[2];
1073         __le32                  cdw14[2];
1074 };
1075
1076 struct nvme_zone_mgmt_recv_cmd {
1077         __u8                    opcode;
1078         __u8                    flags;
1079         __u16                   command_id;
1080         __le32                  nsid;
1081         __le64                  rsvd2[2];
1082         union nvme_data_ptr     dptr;
1083         __le64                  slba;
1084         __le32                  numd;
1085         __u8                    zra;
1086         __u8                    zrasf;
1087         __u8                    pr;
1088         __u8                    rsvd13;
1089         __le32                  cdw14[2];
1090 };
1091
1092 enum {
1093         NVME_ZRA_ZONE_REPORT            = 0,
1094         NVME_ZRASF_ZONE_REPORT_ALL      = 0,
1095         NVME_ZRASF_ZONE_STATE_EMPTY     = 0x01,
1096         NVME_ZRASF_ZONE_STATE_IMP_OPEN  = 0x02,
1097         NVME_ZRASF_ZONE_STATE_EXP_OPEN  = 0x03,
1098         NVME_ZRASF_ZONE_STATE_CLOSED    = 0x04,
1099         NVME_ZRASF_ZONE_STATE_READONLY  = 0x05,
1100         NVME_ZRASF_ZONE_STATE_FULL      = 0x06,
1101         NVME_ZRASF_ZONE_STATE_OFFLINE   = 0x07,
1102         NVME_REPORT_ZONE_PARTIAL        = 1,
1103 };
1104
1105 /* Features */
1106
1107 enum {
1108         NVME_TEMP_THRESH_MASK           = 0xffff,
1109         NVME_TEMP_THRESH_SELECT_SHIFT   = 16,
1110         NVME_TEMP_THRESH_TYPE_UNDER     = 0x100000,
1111 };
1112
1113 struct nvme_feat_auto_pst {
1114         __le64 entries[32];
1115 };
1116
1117 enum {
1118         NVME_HOST_MEM_ENABLE    = (1 << 0),
1119         NVME_HOST_MEM_RETURN    = (1 << 1),
1120 };
1121
1122 struct nvme_feat_host_behavior {
1123         __u8 acre;
1124         __u8 etdas;
1125         __u8 lbafee;
1126         __u8 resv1[509];
1127 };
1128
1129 enum {
1130         NVME_ENABLE_ACRE        = 1,
1131         NVME_ENABLE_LBAFEE      = 1,
1132 };
1133
1134 /* Admin commands */
1135
1136 enum nvme_admin_opcode {
1137         nvme_admin_delete_sq            = 0x00,
1138         nvme_admin_create_sq            = 0x01,
1139         nvme_admin_get_log_page         = 0x02,
1140         nvme_admin_delete_cq            = 0x04,
1141         nvme_admin_create_cq            = 0x05,
1142         nvme_admin_identify             = 0x06,
1143         nvme_admin_abort_cmd            = 0x08,
1144         nvme_admin_set_features         = 0x09,
1145         nvme_admin_get_features         = 0x0a,
1146         nvme_admin_async_event          = 0x0c,
1147         nvme_admin_ns_mgmt              = 0x0d,
1148         nvme_admin_activate_fw          = 0x10,
1149         nvme_admin_download_fw          = 0x11,
1150         nvme_admin_dev_self_test        = 0x14,
1151         nvme_admin_ns_attach            = 0x15,
1152         nvme_admin_keep_alive           = 0x18,
1153         nvme_admin_directive_send       = 0x19,
1154         nvme_admin_directive_recv       = 0x1a,
1155         nvme_admin_virtual_mgmt         = 0x1c,
1156         nvme_admin_nvme_mi_send         = 0x1d,
1157         nvme_admin_nvme_mi_recv         = 0x1e,
1158         nvme_admin_dbbuf                = 0x7C,
1159         nvme_admin_format_nvm           = 0x80,
1160         nvme_admin_security_send        = 0x81,
1161         nvme_admin_security_recv        = 0x82,
1162         nvme_admin_sanitize_nvm         = 0x84,
1163         nvme_admin_get_lba_status       = 0x86,
1164         nvme_admin_vendor_start         = 0xC0,
1165 };
1166
1167 #define nvme_admin_opcode_name(opcode)  { opcode, #opcode }
1168 #define show_admin_opcode_name(val)                                     \
1169         __print_symbolic(val,                                           \
1170                 nvme_admin_opcode_name(nvme_admin_delete_sq),           \
1171                 nvme_admin_opcode_name(nvme_admin_create_sq),           \
1172                 nvme_admin_opcode_name(nvme_admin_get_log_page),        \
1173                 nvme_admin_opcode_name(nvme_admin_delete_cq),           \
1174                 nvme_admin_opcode_name(nvme_admin_create_cq),           \
1175                 nvme_admin_opcode_name(nvme_admin_identify),            \
1176                 nvme_admin_opcode_name(nvme_admin_abort_cmd),           \
1177                 nvme_admin_opcode_name(nvme_admin_set_features),        \
1178                 nvme_admin_opcode_name(nvme_admin_get_features),        \
1179                 nvme_admin_opcode_name(nvme_admin_async_event),         \
1180                 nvme_admin_opcode_name(nvme_admin_ns_mgmt),             \
1181                 nvme_admin_opcode_name(nvme_admin_activate_fw),         \
1182                 nvme_admin_opcode_name(nvme_admin_download_fw),         \
1183                 nvme_admin_opcode_name(nvme_admin_dev_self_test),       \
1184                 nvme_admin_opcode_name(nvme_admin_ns_attach),           \
1185                 nvme_admin_opcode_name(nvme_admin_keep_alive),          \
1186                 nvme_admin_opcode_name(nvme_admin_directive_send),      \
1187                 nvme_admin_opcode_name(nvme_admin_directive_recv),      \
1188                 nvme_admin_opcode_name(nvme_admin_virtual_mgmt),        \
1189                 nvme_admin_opcode_name(nvme_admin_nvme_mi_send),        \
1190                 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv),        \
1191                 nvme_admin_opcode_name(nvme_admin_dbbuf),               \
1192                 nvme_admin_opcode_name(nvme_admin_format_nvm),          \
1193                 nvme_admin_opcode_name(nvme_admin_security_send),       \
1194                 nvme_admin_opcode_name(nvme_admin_security_recv),       \
1195                 nvme_admin_opcode_name(nvme_admin_sanitize_nvm),        \
1196                 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1197
1198 enum {
1199         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
1200         NVME_CQ_IRQ_ENABLED     = (1 << 1),
1201         NVME_SQ_PRIO_URGENT     = (0 << 1),
1202         NVME_SQ_PRIO_HIGH       = (1 << 1),
1203         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
1204         NVME_SQ_PRIO_LOW        = (3 << 1),
1205         NVME_FEAT_ARBITRATION   = 0x01,
1206         NVME_FEAT_POWER_MGMT    = 0x02,
1207         NVME_FEAT_LBA_RANGE     = 0x03,
1208         NVME_FEAT_TEMP_THRESH   = 0x04,
1209         NVME_FEAT_ERR_RECOVERY  = 0x05,
1210         NVME_FEAT_VOLATILE_WC   = 0x06,
1211         NVME_FEAT_NUM_QUEUES    = 0x07,
1212         NVME_FEAT_IRQ_COALESCE  = 0x08,
1213         NVME_FEAT_IRQ_CONFIG    = 0x09,
1214         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
1215         NVME_FEAT_ASYNC_EVENT   = 0x0b,
1216         NVME_FEAT_AUTO_PST      = 0x0c,
1217         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
1218         NVME_FEAT_TIMESTAMP     = 0x0e,
1219         NVME_FEAT_KATO          = 0x0f,
1220         NVME_FEAT_HCTM          = 0x10,
1221         NVME_FEAT_NOPSC         = 0x11,
1222         NVME_FEAT_RRL           = 0x12,
1223         NVME_FEAT_PLM_CONFIG    = 0x13,
1224         NVME_FEAT_PLM_WINDOW    = 0x14,
1225         NVME_FEAT_HOST_BEHAVIOR = 0x16,
1226         NVME_FEAT_SANITIZE      = 0x17,
1227         NVME_FEAT_SW_PROGRESS   = 0x80,
1228         NVME_FEAT_HOST_ID       = 0x81,
1229         NVME_FEAT_RESV_MASK     = 0x82,
1230         NVME_FEAT_RESV_PERSIST  = 0x83,
1231         NVME_FEAT_WRITE_PROTECT = 0x84,
1232         NVME_FEAT_VENDOR_START  = 0xC0,
1233         NVME_FEAT_VENDOR_END    = 0xFF,
1234         NVME_LOG_ERROR          = 0x01,
1235         NVME_LOG_SMART          = 0x02,
1236         NVME_LOG_FW_SLOT        = 0x03,
1237         NVME_LOG_CHANGED_NS     = 0x04,
1238         NVME_LOG_CMD_EFFECTS    = 0x05,
1239         NVME_LOG_DEVICE_SELF_TEST = 0x06,
1240         NVME_LOG_TELEMETRY_HOST = 0x07,
1241         NVME_LOG_TELEMETRY_CTRL = 0x08,
1242         NVME_LOG_ENDURANCE_GROUP = 0x09,
1243         NVME_LOG_ANA            = 0x0c,
1244         NVME_LOG_DISC           = 0x70,
1245         NVME_LOG_RESERVATION    = 0x80,
1246         NVME_FWACT_REPL         = (0 << 3),
1247         NVME_FWACT_REPL_ACTV    = (1 << 3),
1248         NVME_FWACT_ACTV         = (2 << 3),
1249 };
1250
1251 /* NVMe Namespace Write Protect State */
1252 enum {
1253         NVME_NS_NO_WRITE_PROTECT = 0,
1254         NVME_NS_WRITE_PROTECT,
1255         NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1256         NVME_NS_WRITE_PROTECT_PERMANENT,
1257 };
1258
1259 #define NVME_MAX_CHANGED_NAMESPACES     1024
1260
1261 struct nvme_identify {
1262         __u8                    opcode;
1263         __u8                    flags;
1264         __u16                   command_id;
1265         __le32                  nsid;
1266         __u64                   rsvd2[2];
1267         union nvme_data_ptr     dptr;
1268         __u8                    cns;
1269         __u8                    rsvd3;
1270         __le16                  ctrlid;
1271         __u8                    rsvd11[3];
1272         __u8                    csi;
1273         __u32                   rsvd12[4];
1274 };
1275
1276 #define NVME_IDENTIFY_DATA_SIZE 4096
1277
1278 struct nvme_features {
1279         __u8                    opcode;
1280         __u8                    flags;
1281         __u16                   command_id;
1282         __le32                  nsid;
1283         __u64                   rsvd2[2];
1284         union nvme_data_ptr     dptr;
1285         __le32                  fid;
1286         __le32                  dword11;
1287         __le32                  dword12;
1288         __le32                  dword13;
1289         __le32                  dword14;
1290         __le32                  dword15;
1291 };
1292
1293 struct nvme_host_mem_buf_desc {
1294         __le64                  addr;
1295         __le32                  size;
1296         __u32                   rsvd;
1297 };
1298
1299 struct nvme_create_cq {
1300         __u8                    opcode;
1301         __u8                    flags;
1302         __u16                   command_id;
1303         __u32                   rsvd1[5];
1304         __le64                  prp1;
1305         __u64                   rsvd8;
1306         __le16                  cqid;
1307         __le16                  qsize;
1308         __le16                  cq_flags;
1309         __le16                  irq_vector;
1310         __u32                   rsvd12[4];
1311 };
1312
1313 struct nvme_create_sq {
1314         __u8                    opcode;
1315         __u8                    flags;
1316         __u16                   command_id;
1317         __u32                   rsvd1[5];
1318         __le64                  prp1;
1319         __u64                   rsvd8;
1320         __le16                  sqid;
1321         __le16                  qsize;
1322         __le16                  sq_flags;
1323         __le16                  cqid;
1324         __u32                   rsvd12[4];
1325 };
1326
1327 struct nvme_delete_queue {
1328         __u8                    opcode;
1329         __u8                    flags;
1330         __u16                   command_id;
1331         __u32                   rsvd1[9];
1332         __le16                  qid;
1333         __u16                   rsvd10;
1334         __u32                   rsvd11[5];
1335 };
1336
1337 struct nvme_abort_cmd {
1338         __u8                    opcode;
1339         __u8                    flags;
1340         __u16                   command_id;
1341         __u32                   rsvd1[9];
1342         __le16                  sqid;
1343         __u16                   cid;
1344         __u32                   rsvd11[5];
1345 };
1346
1347 struct nvme_download_firmware {
1348         __u8                    opcode;
1349         __u8                    flags;
1350         __u16                   command_id;
1351         __u32                   rsvd1[5];
1352         union nvme_data_ptr     dptr;
1353         __le32                  numd;
1354         __le32                  offset;
1355         __u32                   rsvd12[4];
1356 };
1357
1358 struct nvme_format_cmd {
1359         __u8                    opcode;
1360         __u8                    flags;
1361         __u16                   command_id;
1362         __le32                  nsid;
1363         __u64                   rsvd2[4];
1364         __le32                  cdw10;
1365         __u32                   rsvd11[5];
1366 };
1367
1368 struct nvme_get_log_page_command {
1369         __u8                    opcode;
1370         __u8                    flags;
1371         __u16                   command_id;
1372         __le32                  nsid;
1373         __u64                   rsvd2[2];
1374         union nvme_data_ptr     dptr;
1375         __u8                    lid;
1376         __u8                    lsp; /* upper 4 bits reserved */
1377         __le16                  numdl;
1378         __le16                  numdu;
1379         __u16                   rsvd11;
1380         union {
1381                 struct {
1382                         __le32 lpol;
1383                         __le32 lpou;
1384                 };
1385                 __le64 lpo;
1386         };
1387         __u8                    rsvd14[3];
1388         __u8                    csi;
1389         __u32                   rsvd15;
1390 };
1391
1392 struct nvme_directive_cmd {
1393         __u8                    opcode;
1394         __u8                    flags;
1395         __u16                   command_id;
1396         __le32                  nsid;
1397         __u64                   rsvd2[2];
1398         union nvme_data_ptr     dptr;
1399         __le32                  numd;
1400         __u8                    doper;
1401         __u8                    dtype;
1402         __le16                  dspec;
1403         __u8                    endir;
1404         __u8                    tdtype;
1405         __u16                   rsvd15;
1406
1407         __u32                   rsvd16[3];
1408 };
1409
1410 /*
1411  * Fabrics subcommands.
1412  */
1413 enum nvmf_fabrics_opcode {
1414         nvme_fabrics_command            = 0x7f,
1415 };
1416
1417 enum nvmf_capsule_command {
1418         nvme_fabrics_type_property_set  = 0x00,
1419         nvme_fabrics_type_connect       = 0x01,
1420         nvme_fabrics_type_property_get  = 0x04,
1421         nvme_fabrics_type_auth_send     = 0x05,
1422         nvme_fabrics_type_auth_receive  = 0x06,
1423 };
1424
1425 #define nvme_fabrics_type_name(type)   { type, #type }
1426 #define show_fabrics_type_name(type)                                    \
1427         __print_symbolic(type,                                          \
1428                 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1429                 nvme_fabrics_type_name(nvme_fabrics_type_connect),      \
1430                 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1431                 nvme_fabrics_type_name(nvme_fabrics_type_auth_send),    \
1432                 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
1433
1434 /*
1435  * If not fabrics command, fctype will be ignored.
1436  */
1437 #define show_opcode_name(qid, opcode, fctype)                   \
1438         ((opcode) == nvme_fabrics_command ?                     \
1439          show_fabrics_type_name(fctype) :                       \
1440         ((qid) ?                                                \
1441          show_nvm_opcode_name(opcode) :                         \
1442          show_admin_opcode_name(opcode)))
1443
1444 struct nvmf_common_command {
1445         __u8    opcode;
1446         __u8    resv1;
1447         __u16   command_id;
1448         __u8    fctype;
1449         __u8    resv2[35];
1450         __u8    ts[24];
1451 };
1452
1453 /*
1454  * The legal cntlid range a NVMe Target will provide.
1455  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1456  * Devices based on earlier specs did not have the subsystem concept;
1457  * therefore, those devices had their cntlid value set to 0 as a result.
1458  */
1459 #define NVME_CNTLID_MIN         1
1460 #define NVME_CNTLID_MAX         0xffef
1461 #define NVME_CNTLID_DYNAMIC     0xffff
1462
1463 #define MAX_DISC_LOGS   255
1464
1465 /* Discovery log page entry flags (EFLAGS): */
1466 enum {
1467         NVME_DISC_EFLAGS_EPCSD          = (1 << 1),
1468         NVME_DISC_EFLAGS_DUPRETINFO     = (1 << 0),
1469 };
1470
1471 /* Discovery log page entry */
1472 struct nvmf_disc_rsp_page_entry {
1473         __u8            trtype;
1474         __u8            adrfam;
1475         __u8            subtype;
1476         __u8            treq;
1477         __le16          portid;
1478         __le16          cntlid;
1479         __le16          asqsz;
1480         __le16          eflags;
1481         __u8            resv10[20];
1482         char            trsvcid[NVMF_TRSVCID_SIZE];
1483         __u8            resv64[192];
1484         char            subnqn[NVMF_NQN_FIELD_LEN];
1485         char            traddr[NVMF_TRADDR_SIZE];
1486         union tsas {
1487                 char            common[NVMF_TSAS_SIZE];
1488                 struct rdma {
1489                         __u8    qptype;
1490                         __u8    prtype;
1491                         __u8    cms;
1492                         __u8    resv3[5];
1493                         __u16   pkey;
1494                         __u8    resv10[246];
1495                 } rdma;
1496         } tsas;
1497 };
1498
1499 /* Discovery log page header */
1500 struct nvmf_disc_rsp_page_hdr {
1501         __le64          genctr;
1502         __le64          numrec;
1503         __le16          recfmt;
1504         __u8            resv14[1006];
1505         struct nvmf_disc_rsp_page_entry entries[];
1506 };
1507
1508 enum {
1509         NVME_CONNECT_DISABLE_SQFLOW     = (1 << 2),
1510 };
1511
1512 struct nvmf_connect_command {
1513         __u8            opcode;
1514         __u8            resv1;
1515         __u16           command_id;
1516         __u8            fctype;
1517         __u8            resv2[19];
1518         union nvme_data_ptr dptr;
1519         __le16          recfmt;
1520         __le16          qid;
1521         __le16          sqsize;
1522         __u8            cattr;
1523         __u8            resv3;
1524         __le32          kato;
1525         __u8            resv4[12];
1526 };
1527
1528 enum {
1529         NVME_CONNECT_AUTHREQ_ASCR       = (1U << 18),
1530         NVME_CONNECT_AUTHREQ_ATR        = (1U << 17),
1531 };
1532
1533 struct nvmf_connect_data {
1534         uuid_t          hostid;
1535         __le16          cntlid;
1536         char            resv4[238];
1537         char            subsysnqn[NVMF_NQN_FIELD_LEN];
1538         char            hostnqn[NVMF_NQN_FIELD_LEN];
1539         char            resv5[256];
1540 };
1541
1542 struct nvmf_property_set_command {
1543         __u8            opcode;
1544         __u8            resv1;
1545         __u16           command_id;
1546         __u8            fctype;
1547         __u8            resv2[35];
1548         __u8            attrib;
1549         __u8            resv3[3];
1550         __le32          offset;
1551         __le64          value;
1552         __u8            resv4[8];
1553 };
1554
1555 struct nvmf_property_get_command {
1556         __u8            opcode;
1557         __u8            resv1;
1558         __u16           command_id;
1559         __u8            fctype;
1560         __u8            resv2[35];
1561         __u8            attrib;
1562         __u8            resv3[3];
1563         __le32          offset;
1564         __u8            resv4[16];
1565 };
1566
1567 struct nvmf_auth_common_command {
1568         __u8            opcode;
1569         __u8            resv1;
1570         __u16           command_id;
1571         __u8            fctype;
1572         __u8            resv2[19];
1573         union nvme_data_ptr dptr;
1574         __u8            resv3;
1575         __u8            spsp0;
1576         __u8            spsp1;
1577         __u8            secp;
1578         __le32          al_tl;
1579         __u8            resv4[16];
1580 };
1581
1582 struct nvmf_auth_send_command {
1583         __u8            opcode;
1584         __u8            resv1;
1585         __u16           command_id;
1586         __u8            fctype;
1587         __u8            resv2[19];
1588         union nvme_data_ptr dptr;
1589         __u8            resv3;
1590         __u8            spsp0;
1591         __u8            spsp1;
1592         __u8            secp;
1593         __le32          tl;
1594         __u8            resv4[16];
1595 };
1596
1597 struct nvmf_auth_receive_command {
1598         __u8            opcode;
1599         __u8            resv1;
1600         __u16           command_id;
1601         __u8            fctype;
1602         __u8            resv2[19];
1603         union nvme_data_ptr dptr;
1604         __u8            resv3;
1605         __u8            spsp0;
1606         __u8            spsp1;
1607         __u8            secp;
1608         __le32          al;
1609         __u8            resv4[16];
1610 };
1611
1612 /* Value for secp */
1613 enum {
1614         NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER    = 0xe9,
1615 };
1616
1617 /* Defined value for auth_type */
1618 enum {
1619         NVME_AUTH_COMMON_MESSAGES       = 0x00,
1620         NVME_AUTH_DHCHAP_MESSAGES       = 0x01,
1621 };
1622
1623 /* Defined messages for auth_id */
1624 enum {
1625         NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE      = 0x00,
1626         NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE      = 0x01,
1627         NVME_AUTH_DHCHAP_MESSAGE_REPLY          = 0x02,
1628         NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1       = 0x03,
1629         NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2       = 0x04,
1630         NVME_AUTH_DHCHAP_MESSAGE_FAILURE2       = 0xf0,
1631         NVME_AUTH_DHCHAP_MESSAGE_FAILURE1       = 0xf1,
1632 };
1633
1634 struct nvmf_auth_dhchap_protocol_descriptor {
1635         __u8            authid;
1636         __u8            rsvd;
1637         __u8            halen;
1638         __u8            dhlen;
1639         __u8            idlist[60];
1640 };
1641
1642 enum {
1643         NVME_AUTH_DHCHAP_AUTH_ID        = 0x01,
1644 };
1645
1646 /* Defined hash functions for DH-HMAC-CHAP authentication */
1647 enum {
1648         NVME_AUTH_HASH_SHA256   = 0x01,
1649         NVME_AUTH_HASH_SHA384   = 0x02,
1650         NVME_AUTH_HASH_SHA512   = 0x03,
1651         NVME_AUTH_HASH_INVALID  = 0xff,
1652 };
1653
1654 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1655 enum {
1656         NVME_AUTH_DHGROUP_NULL          = 0x00,
1657         NVME_AUTH_DHGROUP_2048          = 0x01,
1658         NVME_AUTH_DHGROUP_3072          = 0x02,
1659         NVME_AUTH_DHGROUP_4096          = 0x03,
1660         NVME_AUTH_DHGROUP_6144          = 0x04,
1661         NVME_AUTH_DHGROUP_8192          = 0x05,
1662         NVME_AUTH_DHGROUP_INVALID       = 0xff,
1663 };
1664
1665 union nvmf_auth_protocol {
1666         struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1667 };
1668
1669 struct nvmf_auth_dhchap_negotiate_data {
1670         __u8            auth_type;
1671         __u8            auth_id;
1672         __le16          rsvd;
1673         __le16          t_id;
1674         __u8            sc_c;
1675         __u8            napd;
1676         union nvmf_auth_protocol auth_protocol[];
1677 };
1678
1679 struct nvmf_auth_dhchap_challenge_data {
1680         __u8            auth_type;
1681         __u8            auth_id;
1682         __u16           rsvd1;
1683         __le16          t_id;
1684         __u8            hl;
1685         __u8            rsvd2;
1686         __u8            hashid;
1687         __u8            dhgid;
1688         __le16          dhvlen;
1689         __le32          seqnum;
1690         /* 'hl' bytes of challenge value */
1691         __u8            cval[];
1692         /* followed by 'dhvlen' bytes of DH value */
1693 };
1694
1695 struct nvmf_auth_dhchap_reply_data {
1696         __u8            auth_type;
1697         __u8            auth_id;
1698         __le16          rsvd1;
1699         __le16          t_id;
1700         __u8            hl;
1701         __u8            rsvd2;
1702         __u8            cvalid;
1703         __u8            rsvd3;
1704         __le16          dhvlen;
1705         __le32          seqnum;
1706         /* 'hl' bytes of response data */
1707         __u8            rval[];
1708         /* followed by 'hl' bytes of Challenge value */
1709         /* followed by 'dhvlen' bytes of DH value */
1710 };
1711
1712 enum {
1713         NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1714 };
1715
1716 struct nvmf_auth_dhchap_success1_data {
1717         __u8            auth_type;
1718         __u8            auth_id;
1719         __le16          rsvd1;
1720         __le16          t_id;
1721         __u8            hl;
1722         __u8            rsvd2;
1723         __u8            rvalid;
1724         __u8            rsvd3[7];
1725         /* 'hl' bytes of response value if 'rvalid' is set */
1726         __u8            rval[];
1727 };
1728
1729 struct nvmf_auth_dhchap_success2_data {
1730         __u8            auth_type;
1731         __u8            auth_id;
1732         __le16          rsvd1;
1733         __le16          t_id;
1734         __u8            rsvd2[10];
1735 };
1736
1737 struct nvmf_auth_dhchap_failure_data {
1738         __u8            auth_type;
1739         __u8            auth_id;
1740         __le16          rsvd1;
1741         __le16          t_id;
1742         __u8            rescode;
1743         __u8            rescode_exp;
1744 };
1745
1746 enum {
1747         NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED  = 0x01,
1748 };
1749
1750 enum {
1751         NVME_AUTH_DHCHAP_FAILURE_FAILED                 = 0x01,
1752         NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE             = 0x02,
1753         NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH        = 0x03,
1754         NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE          = 0x04,
1755         NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE       = 0x05,
1756         NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD      = 0x06,
1757         NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE      = 0x07,
1758 };
1759
1760
1761 struct nvme_dbbuf {
1762         __u8                    opcode;
1763         __u8                    flags;
1764         __u16                   command_id;
1765         __u32                   rsvd1[5];
1766         __le64                  prp1;
1767         __le64                  prp2;
1768         __u32                   rsvd12[6];
1769 };
1770
1771 struct streams_directive_params {
1772         __le16  msl;
1773         __le16  nssa;
1774         __le16  nsso;
1775         __u8    rsvd[10];
1776         __le32  sws;
1777         __le16  sgs;
1778         __le16  nsa;
1779         __le16  nso;
1780         __u8    rsvd2[6];
1781 };
1782
1783 struct nvme_command {
1784         union {
1785                 struct nvme_common_command common;
1786                 struct nvme_rw_command rw;
1787                 struct nvme_identify identify;
1788                 struct nvme_features features;
1789                 struct nvme_create_cq create_cq;
1790                 struct nvme_create_sq create_sq;
1791                 struct nvme_delete_queue delete_queue;
1792                 struct nvme_download_firmware dlfw;
1793                 struct nvme_format_cmd format;
1794                 struct nvme_dsm_cmd dsm;
1795                 struct nvme_write_zeroes_cmd write_zeroes;
1796                 struct nvme_zone_mgmt_send_cmd zms;
1797                 struct nvme_zone_mgmt_recv_cmd zmr;
1798                 struct nvme_abort_cmd abort;
1799                 struct nvme_get_log_page_command get_log_page;
1800                 struct nvmf_common_command fabrics;
1801                 struct nvmf_connect_command connect;
1802                 struct nvmf_property_set_command prop_set;
1803                 struct nvmf_property_get_command prop_get;
1804                 struct nvmf_auth_common_command auth_common;
1805                 struct nvmf_auth_send_command auth_send;
1806                 struct nvmf_auth_receive_command auth_receive;
1807                 struct nvme_dbbuf dbbuf;
1808                 struct nvme_directive_cmd directive;
1809         };
1810 };
1811
1812 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1813 {
1814         return cmd->common.opcode == nvme_fabrics_command;
1815 }
1816
1817 struct nvme_error_slot {
1818         __le64          error_count;
1819         __le16          sqid;
1820         __le16          cmdid;
1821         __le16          status_field;
1822         __le16          param_error_location;
1823         __le64          lba;
1824         __le32          nsid;
1825         __u8            vs;
1826         __u8            resv[3];
1827         __le64          cs;
1828         __u8            resv2[24];
1829 };
1830
1831 static inline bool nvme_is_write(struct nvme_command *cmd)
1832 {
1833         /*
1834          * What a mess...
1835          *
1836          * Why can't we simply have a Fabrics In and Fabrics out command?
1837          */
1838         if (unlikely(nvme_is_fabrics(cmd)))
1839                 return cmd->fabrics.fctype & 1;
1840         return cmd->common.opcode & 1;
1841 }
1842
1843 enum {
1844         /*
1845          * Generic Command Status:
1846          */
1847         NVME_SC_SUCCESS                 = 0x0,
1848         NVME_SC_INVALID_OPCODE          = 0x1,
1849         NVME_SC_INVALID_FIELD           = 0x2,
1850         NVME_SC_CMDID_CONFLICT          = 0x3,
1851         NVME_SC_DATA_XFER_ERROR         = 0x4,
1852         NVME_SC_POWER_LOSS              = 0x5,
1853         NVME_SC_INTERNAL                = 0x6,
1854         NVME_SC_ABORT_REQ               = 0x7,
1855         NVME_SC_ABORT_QUEUE             = 0x8,
1856         NVME_SC_FUSED_FAIL              = 0x9,
1857         NVME_SC_FUSED_MISSING           = 0xa,
1858         NVME_SC_INVALID_NS              = 0xb,
1859         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1860         NVME_SC_SGL_INVALID_LAST        = 0xd,
1861         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1862         NVME_SC_SGL_INVALID_DATA        = 0xf,
1863         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1864         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1865         NVME_SC_CMB_INVALID_USE         = 0x12,
1866         NVME_SC_PRP_INVALID_OFFSET      = 0x13,
1867         NVME_SC_ATOMIC_WU_EXCEEDED      = 0x14,
1868         NVME_SC_OP_DENIED               = 0x15,
1869         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1870         NVME_SC_RESERVED                = 0x17,
1871         NVME_SC_HOST_ID_INCONSIST       = 0x18,
1872         NVME_SC_KA_TIMEOUT_EXPIRED      = 0x19,
1873         NVME_SC_KA_TIMEOUT_INVALID      = 0x1A,
1874         NVME_SC_ABORTED_PREEMPT_ABORT   = 0x1B,
1875         NVME_SC_SANITIZE_FAILED         = 0x1C,
1876         NVME_SC_SANITIZE_IN_PROGRESS    = 0x1D,
1877         NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1878         NVME_SC_CMD_NOT_SUP_CMB_QUEUE   = 0x1F,
1879         NVME_SC_NS_WRITE_PROTECTED      = 0x20,
1880         NVME_SC_CMD_INTERRUPTED         = 0x21,
1881         NVME_SC_TRANSIENT_TR_ERR        = 0x22,
1882         NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
1883         NVME_SC_INVALID_IO_CMD_SET      = 0x2C,
1884
1885         NVME_SC_LBA_RANGE               = 0x80,
1886         NVME_SC_CAP_EXCEEDED            = 0x81,
1887         NVME_SC_NS_NOT_READY            = 0x82,
1888         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1889         NVME_SC_FORMAT_IN_PROGRESS      = 0x84,
1890
1891         /*
1892          * Command Specific Status:
1893          */
1894         NVME_SC_CQ_INVALID              = 0x100,
1895         NVME_SC_QID_INVALID             = 0x101,
1896         NVME_SC_QUEUE_SIZE              = 0x102,
1897         NVME_SC_ABORT_LIMIT             = 0x103,
1898         NVME_SC_ABORT_MISSING           = 0x104,
1899         NVME_SC_ASYNC_LIMIT             = 0x105,
1900         NVME_SC_FIRMWARE_SLOT           = 0x106,
1901         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1902         NVME_SC_INVALID_VECTOR          = 0x108,
1903         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1904         NVME_SC_INVALID_FORMAT          = 0x10a,
1905         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1906         NVME_SC_INVALID_QUEUE           = 0x10c,
1907         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1908         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1909         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1910         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1911         NVME_SC_FW_NEEDS_RESET          = 0x111,
1912         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1913         NVME_SC_FW_ACTIVATE_PROHIBITED  = 0x113,
1914         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1915         NVME_SC_NS_INSUFFICIENT_CAP     = 0x115,
1916         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1917         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1918         NVME_SC_NS_IS_PRIVATE           = 0x119,
1919         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1920         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1921         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1922         NVME_SC_SELT_TEST_IN_PROGRESS   = 0x11d,
1923         NVME_SC_BP_WRITE_PROHIBITED     = 0x11e,
1924         NVME_SC_CTRL_ID_INVALID         = 0x11f,
1925         NVME_SC_SEC_CTRL_STATE_INVALID  = 0x120,
1926         NVME_SC_CTRL_RES_NUM_INVALID    = 0x121,
1927         NVME_SC_RES_ID_INVALID          = 0x122,
1928         NVME_SC_PMR_SAN_PROHIBITED      = 0x123,
1929         NVME_SC_ANA_GROUP_ID_INVALID    = 0x124,
1930         NVME_SC_ANA_ATTACH_FAILED       = 0x125,
1931
1932         /*
1933          * I/O Command Set Specific - NVM commands:
1934          */
1935         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1936         NVME_SC_INVALID_PI              = 0x181,
1937         NVME_SC_READ_ONLY               = 0x182,
1938         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1939
1940         /*
1941          * I/O Command Set Specific - Fabrics commands:
1942          */
1943         NVME_SC_CONNECT_FORMAT          = 0x180,
1944         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1945         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1946         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1947         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1948
1949         NVME_SC_DISCOVERY_RESTART       = 0x190,
1950         NVME_SC_AUTH_REQUIRED           = 0x191,
1951
1952         /*
1953          * I/O Command Set Specific - Zoned commands:
1954          */
1955         NVME_SC_ZONE_BOUNDARY_ERROR     = 0x1b8,
1956         NVME_SC_ZONE_FULL               = 0x1b9,
1957         NVME_SC_ZONE_READ_ONLY          = 0x1ba,
1958         NVME_SC_ZONE_OFFLINE            = 0x1bb,
1959         NVME_SC_ZONE_INVALID_WRITE      = 0x1bc,
1960         NVME_SC_ZONE_TOO_MANY_ACTIVE    = 0x1bd,
1961         NVME_SC_ZONE_TOO_MANY_OPEN      = 0x1be,
1962         NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1963
1964         /*
1965          * Media and Data Integrity Errors:
1966          */
1967         NVME_SC_WRITE_FAULT             = 0x280,
1968         NVME_SC_READ_ERROR              = 0x281,
1969         NVME_SC_GUARD_CHECK             = 0x282,
1970         NVME_SC_APPTAG_CHECK            = 0x283,
1971         NVME_SC_REFTAG_CHECK            = 0x284,
1972         NVME_SC_COMPARE_FAILED          = 0x285,
1973         NVME_SC_ACCESS_DENIED           = 0x286,
1974         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1975
1976         /*
1977          * Path-related Errors:
1978          */
1979         NVME_SC_INTERNAL_PATH_ERROR     = 0x300,
1980         NVME_SC_ANA_PERSISTENT_LOSS     = 0x301,
1981         NVME_SC_ANA_INACCESSIBLE        = 0x302,
1982         NVME_SC_ANA_TRANSITION          = 0x303,
1983         NVME_SC_CTRL_PATH_ERROR         = 0x360,
1984         NVME_SC_HOST_PATH_ERROR         = 0x370,
1985         NVME_SC_HOST_ABORTED_CMD        = 0x371,
1986
1987         NVME_SC_CRD                     = 0x1800,
1988         NVME_SC_MORE                    = 0x2000,
1989         NVME_SC_DNR                     = 0x4000,
1990 };
1991
1992 struct nvme_completion {
1993         /*
1994          * Used by Admin and Fabrics commands to return data:
1995          */
1996         union nvme_result {
1997                 __le16  u16;
1998                 __le32  u32;
1999                 __le64  u64;
2000         } result;
2001         __le16  sq_head;        /* how much of this queue may be reclaimed */
2002         __le16  sq_id;          /* submission queue that generated this entry */
2003         __u16   command_id;     /* of the command which completed */
2004         __le16  status;         /* did the command fail, and if so, why? */
2005 };
2006
2007 #define NVME_VS(major, minor, tertiary) \
2008         (((major) << 16) | ((minor) << 8) | (tertiary))
2009
2010 #define NVME_MAJOR(ver)         ((ver) >> 16)
2011 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
2012 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
2013
2014 #endif /* _LINUX_NVME_H */