1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Synced from Linux v4.19
7 #ifndef __LINUX_MTD_SPI_NOR_H
8 #define __LINUX_MTD_SPI_NOR_H
10 #include <linux/bitops.h>
11 #include <linux/mtd/cfi.h>
12 #include <linux/mtd/mtd.h>
17 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
18 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
20 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
21 #define SNOR_MFR_GIGADEVICE 0xc8
22 #define SNOR_MFR_INTEL CFI_MFR_INTEL
23 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
24 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
25 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
26 #define SNOR_MFR_SPANSION CFI_MFR_AMD
27 #define SNOR_MFR_SST CFI_MFR_SST
28 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
31 * Note on opcode nomenclature: some opcodes have a format like
32 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
33 * of I/O lines used for the opcode, address, and data (respectively). The
34 * FUNCTION has an optional suffix of '4', to represent an opcode which
35 * requires a 4-byte (32-bit) address.
39 #define SPINOR_OP_WREN 0x06 /* Write enable */
40 #define SPINOR_OP_RDSR 0x05 /* Read status register */
41 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
42 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
43 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
44 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
45 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
46 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
47 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
48 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
49 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
50 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
51 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
52 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
53 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
54 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
55 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
56 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
57 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
58 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
59 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
60 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
61 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
62 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
63 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
64 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
65 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
66 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
67 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
68 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
70 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
71 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
72 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
73 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
74 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
75 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
76 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
77 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
78 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
79 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
80 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
81 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
82 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
83 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
84 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
85 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
86 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
88 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
89 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
90 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
91 #define SPINOR_OP_READ_1_4_4_DTR 0xed
93 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
94 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
95 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
97 /* Used for SST flashes only. */
98 #define SPINOR_OP_BP 0x02 /* Byte program */
99 #define SPINOR_OP_WRDI 0x04 /* Write disable */
100 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
102 /* Used for SST26* flashes only. */
103 #define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
104 #define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
106 /* Used for S3AN flashes only */
107 #define SPINOR_OP_XSE 0x50 /* Sector erase */
108 #define SPINOR_OP_XPP 0x82 /* Page program */
109 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
111 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
112 #define XSR_RDY BIT(7) /* Ready */
114 /* Used for Macronix and Winbond flashes. */
115 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
116 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
118 /* Used for Spansion flashes only. */
119 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
120 #define SPINOR_OP_BRRD 0x16 /* Bank register read */
121 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
123 /* Used for Micron flashes only. */
124 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
125 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
127 /* Status Register bits. */
128 #define SR_WIP BIT(0) /* Write in progress */
129 #define SR_WEL BIT(1) /* Write enable latch */
130 /* meaning of other SR_* bits may differ between vendors */
131 #define SR_BP0 BIT(2) /* Block protect 0 */
132 #define SR_BP1 BIT(3) /* Block protect 1 */
133 #define SR_BP2 BIT(4) /* Block protect 2 */
134 #define SR_TB BIT(5) /* Top/Bottom protect */
135 #define SR_SRWD BIT(7) /* SR write protect */
136 /* Spansion/Cypress specific status bits */
137 #define SR_E_ERR BIT(5)
138 #define SR_P_ERR BIT(6)
140 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
142 /* Enhanced Volatile Configuration Register bits */
143 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
145 /* Flag Status Register bits */
146 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
147 #define FSR_E_ERR BIT(5) /* Erase operation status */
148 #define FSR_P_ERR BIT(4) /* Program operation status */
149 #define FSR_PT_ERR BIT(1) /* Protection error bit */
151 /* Configuration Register bits. */
152 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
154 /* Status Register 2 bits. */
155 #define SR2_QUAD_EN_BIT7 BIT(7)
157 /* Supported SPI protocols */
158 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
159 #define SNOR_PROTO_INST_SHIFT 16
160 #define SNOR_PROTO_INST(_nbits) \
161 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
162 SNOR_PROTO_INST_MASK)
164 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
165 #define SNOR_PROTO_ADDR_SHIFT 8
166 #define SNOR_PROTO_ADDR(_nbits) \
167 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
168 SNOR_PROTO_ADDR_MASK)
170 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
171 #define SNOR_PROTO_DATA_SHIFT 0
172 #define SNOR_PROTO_DATA(_nbits) \
173 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
174 SNOR_PROTO_DATA_MASK)
176 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
178 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
179 (SNOR_PROTO_INST(_inst_nbits) | \
180 SNOR_PROTO_ADDR(_addr_nbits) | \
181 SNOR_PROTO_DATA(_data_nbits))
182 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
183 (SNOR_PROTO_IS_DTR | \
184 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
186 enum spi_nor_protocol {
187 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
188 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
189 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
190 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
191 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
192 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
193 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
194 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
195 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
196 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
198 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
199 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
200 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
201 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
204 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
206 return !!(proto & SNOR_PROTO_IS_DTR);
209 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
211 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
212 SNOR_PROTO_INST_SHIFT;
215 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
217 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
218 SNOR_PROTO_ADDR_SHIFT;
221 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
223 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
224 SNOR_PROTO_DATA_SHIFT;
227 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
229 return spi_nor_get_protocol_data_nbits(proto);
232 #define SPI_NOR_MAX_CMD_SIZE 8
234 SPI_NOR_OPS_READ = 0,
241 enum spi_nor_option_flags {
242 SNOR_F_USE_FSR = BIT(0),
243 SNOR_F_HAS_SR_TB = BIT(1),
244 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
245 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
246 SNOR_F_READY_XSR_RDY = BIT(4),
247 SNOR_F_USE_CLSR = BIT(5),
248 SNOR_F_BROKEN_RESET = BIT(6),
252 * struct flash_info - Forward declaration of a structure used internally by
258 * TODO: Remove, once all users of spi_flash interface are moved to MTD
261 * Defined below (keep this text to enable searching for spi_flash decl)
264 #define spi_flash spi_nor
267 * struct spi_nor - Structure for defining a the SPI NOR layer
268 * @mtd: point to a mtd_info structure
269 * @lock: the lock for the read/write/erase/lock/unlock operations
270 * @dev: point to a spi device, or a spi nor controller device.
271 * @info: spi-nor part JDEC MFR id and other info
272 * @manufacturer_sfdp: manufacturer specific SFDP table
273 * @page_size: the page size of the SPI NOR
274 * @addr_width: number of address bytes
275 * @erase_opcode: the opcode for erasing a sector
276 * @read_opcode: the read opcode
277 * @read_dummy: the dummy needed by the read operation
278 * @program_opcode: the program opcode
279 * @bank_read_cmd: Bank read cmd
280 * @bank_write_cmd: Bank write cmd
281 * @bank_curr: Current flash bank
282 * @sst_write_second: used by the SST write operation
283 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
284 * @read_proto: the SPI protocol for read operations
285 * @write_proto: the SPI protocol for write operations
286 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
287 * @cmd_buf: used by the write_reg
288 * @prepare: [OPTIONAL] do some preparations for the
289 * read/write/erase/lock/unlock operations
290 * @unprepare: [OPTIONAL] do some post work after the
291 * read/write/erase/lock/unlock operations
292 * @read_reg: [DRIVER-SPECIFIC] read out the register
293 * @write_reg: [DRIVER-SPECIFIC] write data to the register
294 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
295 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
296 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
297 * at the offset @offs; if not provided by the driver,
298 * spi-nor will send the erase opcode via write_reg()
299 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
300 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
301 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
302 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
304 * @priv: the private data
309 struct spi_slave *spi;
310 const struct flash_info *info;
311 u8 *manufacturer_sfdp;
318 #ifdef CONFIG_SPI_FLASH_BAR
323 enum spi_nor_protocol read_proto;
324 enum spi_nor_protocol write_proto;
325 enum spi_nor_protocol reg_proto;
326 bool sst_write_second;
328 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
330 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
331 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
332 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
333 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
335 ssize_t (*read)(struct spi_nor *nor, loff_t from,
336 size_t len, u_char *read_buf);
337 ssize_t (*write)(struct spi_nor *nor, loff_t to,
338 size_t len, const u_char *write_buf);
339 int (*erase)(struct spi_nor *nor, loff_t offs);
341 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
342 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
343 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
344 int (*quad_enable)(struct spi_nor *nor);
347 /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
354 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
355 const struct device_node *np)
357 mtd_set_of_node(&nor->mtd, np);
360 static inline const struct
361 device_node *spi_nor_get_flash_node(struct spi_nor *nor)
363 return mtd_get_of_node(&nor->mtd);
367 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
368 * supported by the SPI controller (bus master).
369 * @mask: the bitmask listing all the supported hw capabilies
371 struct spi_nor_hwcaps {
376 *(Fast) Read capabilities.
377 * MUST be ordered by priority: the higher bit position, the higher priority.
378 * As a matter of performances, it is relevant to use Octo SPI protocols first,
379 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
382 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
383 #define SNOR_HWCAPS_READ BIT(0)
384 #define SNOR_HWCAPS_READ_FAST BIT(1)
385 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
387 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
388 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
389 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
390 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
391 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
393 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
394 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
395 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
396 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
397 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
399 #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
400 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
401 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
402 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
403 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
406 * Page Program capabilities.
407 * MUST be ordered by priority: the higher bit position, the higher priority.
408 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
409 * legacy SPI 1-1-1 protocol.
410 * Note that Dual Page Programs are not supported because there is no existing
411 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
412 * implements such commands.
414 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
415 #define SNOR_HWCAPS_PP BIT(16)
417 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
418 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
419 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
420 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
422 #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
423 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
424 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
425 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
428 * spi_nor_scan() - scan the SPI NOR
429 * @nor: the spi_nor structure
431 * The drivers can use this function to scan the SPI NOR.
432 * In the scanning, it will try to get all the necessary information to
433 * fill the mtd_info{} and the spi_nor{}.
435 * Return: 0 for success, others for failure.
437 int spi_nor_scan(struct spi_nor *nor);