1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Synced from Linux v4.19
7 #ifndef __LINUX_MTD_SPI_NOR_H
8 #define __LINUX_MTD_SPI_NOR_H
11 #include <linux/bitops.h>
12 #include <linux/mtd/cfi.h>
13 #include <linux/mtd/mtd.h>
18 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
19 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
21 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
22 #define SNOR_MFR_GIGADEVICE 0xc8
23 #define SNOR_MFR_INTEL CFI_MFR_INTEL
24 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
25 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
26 #define SNOR_MFR_ISSI CFI_MFR_PMC
27 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
28 #define SNOR_MFR_SPANSION CFI_MFR_AMD
29 #define SNOR_MFR_SST CFI_MFR_SST
30 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
31 #define SNOR_MFR_CYPRESS 0x34
34 * Note on opcode nomenclature: some opcodes have a format like
35 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
36 * of I/O lines used for the opcode, address, and data (respectively). The
37 * FUNCTION has an optional suffix of '4', to represent an opcode which
38 * requires a 4-byte (32-bit) address.
42 #define SPINOR_OP_WREN 0x06 /* Write enable */
43 #define SPINOR_OP_RDSR 0x05 /* Read status register */
44 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
45 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
46 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
47 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
48 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
49 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
50 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
51 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
52 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
53 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
54 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
55 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
56 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
57 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
58 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
59 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
60 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
61 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
62 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
63 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
64 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
65 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
66 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
67 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
68 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
69 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
70 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
71 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
72 #define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
73 #define SPINOR_OP_SRST 0x99 /* Software Reset */
75 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
76 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
77 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
78 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
79 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
80 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
81 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
82 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
83 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
84 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
85 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
86 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
87 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
88 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
89 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
90 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
91 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
93 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
94 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
95 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
96 #define SPINOR_OP_READ_1_4_4_DTR 0xed
98 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
99 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
100 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
102 /* Used for SST flashes only. */
103 #define SPINOR_OP_BP 0x02 /* Byte program */
104 #define SPINOR_OP_WRDI 0x04 /* Write disable */
105 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
107 /* Used for SST26* flashes only. */
108 #define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
109 #define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
111 /* Used for S3AN flashes only */
112 #define SPINOR_OP_XSE 0x50 /* Sector erase */
113 #define SPINOR_OP_XPP 0x82 /* Page program */
114 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
116 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
117 #define XSR_RDY BIT(7) /* Ready */
119 /* Used for Macronix and Winbond flashes. */
120 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
121 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
122 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
123 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
124 #define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */
125 #define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */
126 #define SPINOR_OP_MXIC_DTR_RD 0xee /* Fast Read opcode in DTR mode */
127 #define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */
128 #define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */
129 #define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* For setting dummy cycles */
130 #define SPINOR_REG_MXIC_DC_20 0x0 /* Setting dummy cycles to 20 */
131 #define MXIC_MAX_DC 20 /* Maximum value of dummy cycles */
133 /* Used for Spansion flashes only. */
134 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
135 #define SPINOR_OP_BRRD 0x16 /* Bank register read */
136 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
137 #define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */
138 #define SPINOR_OP_RDAR 0x65 /* Read any register */
139 #define SPINOR_OP_WRAR 0x71 /* Write any register */
140 #define SPINOR_REG_ADDR_STR1V 0x00800000
141 #define SPINOR_REG_ADDR_CFR1V 0x00800002
142 #define SPINOR_REG_ADDR_CFR3V 0x00800004
143 #define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */
144 #define CFR3V_PGMBUF BIT(4) /* Program buffer size */
146 /* Used for Micron flashes only. */
147 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
148 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
149 #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
150 #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
151 #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
152 #define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */
153 #define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */
154 #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR with DQS. */
156 /* Status Register bits. */
157 #define SR_WIP BIT(0) /* Write in progress */
158 #define SR_WEL BIT(1) /* Write enable latch */
159 /* meaning of other SR_* bits may differ between vendors */
160 #define SR_BP0 BIT(2) /* Block protect 0 */
161 #define SR_BP1 BIT(3) /* Block protect 1 */
162 #define SR_BP2 BIT(4) /* Block protect 2 */
163 #define SR_TB BIT(5) /* Top/Bottom protect */
164 #define SR_SRWD BIT(7) /* SR write protect */
165 /* Spansion/Cypress specific status bits */
166 #define SR_E_ERR BIT(5)
167 #define SR_P_ERR BIT(6)
169 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
171 /* Enhanced Volatile Configuration Register bits */
172 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
174 /* Flag Status Register bits */
175 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
176 #define FSR_E_ERR BIT(5) /* Erase operation status */
177 #define FSR_P_ERR BIT(4) /* Program operation status */
178 #define FSR_PT_ERR BIT(1) /* Protection error bit */
180 /* Configuration Register bits. */
181 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
183 /* Status Register 2 bits. */
184 #define SR2_QUAD_EN_BIT7 BIT(7)
186 /* For Cypress flash. */
187 #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
188 #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
189 #define SPINOR_OP_S28_SE_4K 0x21
190 #define SPINOR_REG_CYPRESS_CFR2V 0x00800003
191 #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb
192 #define SPINOR_REG_CYPRESS_CFR3V 0x00800004
193 #define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */
194 #define SPINOR_REG_CYPRESS_CFR3V_UNISECT BIT(3) /* Uniform sector mode */
195 #define SPINOR_REG_CYPRESS_CFR5V 0x00800006
196 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3
197 #define SPINOR_OP_CYPRESS_RD_FAST 0xee
199 /* Supported SPI protocols */
200 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
201 #define SNOR_PROTO_INST_SHIFT 16
202 #define SNOR_PROTO_INST(_nbits) \
203 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
204 SNOR_PROTO_INST_MASK)
206 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
207 #define SNOR_PROTO_ADDR_SHIFT 8
208 #define SNOR_PROTO_ADDR(_nbits) \
209 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
210 SNOR_PROTO_ADDR_MASK)
212 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
213 #define SNOR_PROTO_DATA_SHIFT 0
214 #define SNOR_PROTO_DATA(_nbits) \
215 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
216 SNOR_PROTO_DATA_MASK)
218 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
220 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
221 (SNOR_PROTO_INST(_inst_nbits) | \
222 SNOR_PROTO_ADDR(_addr_nbits) | \
223 SNOR_PROTO_DATA(_data_nbits))
224 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
225 (SNOR_PROTO_IS_DTR | \
226 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
228 enum spi_nor_protocol {
229 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
230 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
231 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
232 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
233 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
234 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
235 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
236 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
237 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
238 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
240 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
241 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
242 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
243 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
244 SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
247 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
249 return !!(proto & SNOR_PROTO_IS_DTR);
252 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
254 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
255 SNOR_PROTO_INST_SHIFT;
258 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
260 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
261 SNOR_PROTO_ADDR_SHIFT;
264 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
266 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
267 SNOR_PROTO_DATA_SHIFT;
270 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
272 return spi_nor_get_protocol_data_nbits(proto);
275 #define SPI_NOR_MAX_CMD_SIZE 8
277 SPI_NOR_OPS_READ = 0,
284 enum spi_nor_option_flags {
285 SNOR_F_USE_FSR = BIT(0),
286 SNOR_F_HAS_SR_TB = BIT(1),
287 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
288 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
289 SNOR_F_READY_XSR_RDY = BIT(4),
290 SNOR_F_USE_CLSR = BIT(5),
291 SNOR_F_BROKEN_RESET = BIT(6),
292 SNOR_F_SOFT_RESET = BIT(7),
293 SNOR_F_IO_MODE_EN_VOLATILE = BIT(8),
299 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
300 * supported by the SPI controller (bus master).
301 * @mask: the bitmask listing all the supported hw capabilies
303 struct spi_nor_hwcaps {
308 *(Fast) Read capabilities.
309 * MUST be ordered by priority: the higher bit position, the higher priority.
310 * As a matter of performances, it is relevant to use Octo SPI protocols first,
311 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
314 #define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)
315 #define SNOR_HWCAPS_READ BIT(0)
316 #define SNOR_HWCAPS_READ_FAST BIT(1)
317 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
319 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
320 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
321 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
322 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
323 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
325 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
326 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
327 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
328 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
329 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
331 #define SNOR_HWCPAS_READ_OCTO GENMASK(15, 11)
332 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
333 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
334 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
335 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
336 #define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15)
339 * Page Program capabilities.
340 * MUST be ordered by priority: the higher bit position, the higher priority.
341 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
342 * legacy SPI 1-1-1 protocol.
343 * Note that Dual Page Programs are not supported because there is no existing
344 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
345 * implements such commands.
347 #define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)
348 #define SNOR_HWCAPS_PP BIT(16)
350 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
351 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
352 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
353 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
355 #define SNOR_HWCAPS_PP_OCTO GENMASK(23, 20)
356 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
357 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
358 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
359 #define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
361 #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
362 SNOR_HWCAPS_READ_4_4_4 | \
363 SNOR_HWCAPS_READ_8_8_8 | \
364 SNOR_HWCAPS_PP_4_4_4 | \
365 SNOR_HWCAPS_PP_8_8_8)
367 #define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \
368 SNOR_HWCAPS_PP_8_8_8_DTR)
370 #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
371 SNOR_HWCAPS_READ_1_2_2_DTR | \
372 SNOR_HWCAPS_READ_1_4_4_DTR | \
373 SNOR_HWCAPS_READ_1_8_8_DTR)
375 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
378 struct spi_nor_read_command {
382 enum spi_nor_protocol proto;
385 struct spi_nor_pp_command {
387 enum spi_nor_protocol proto;
390 enum spi_nor_read_command_index {
393 SNOR_CMD_READ_1_1_1_DTR,
399 SNOR_CMD_READ_1_2_2_DTR,
405 SNOR_CMD_READ_1_4_4_DTR,
411 SNOR_CMD_READ_1_8_8_DTR,
412 SNOR_CMD_READ_8_8_8_DTR,
417 enum spi_nor_pp_command_index {
429 SNOR_CMD_PP_8_8_8_DTR,
434 struct spi_nor_flash_parameter {
440 struct spi_nor_hwcaps hwcaps;
441 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
442 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
444 int (*quad_enable)(struct spi_nor *nor);
448 * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode
449 * @SPI_MEM_NOR_NONE: no extension. This is the default, and is used in Legacy
451 * @SPI_MEM_NOR_REPEAT: the extension is same as the opcode
452 * @SPI_MEM_NOR_INVERT: the extension is the bitwise inverse of the opcode
453 * @SPI_MEM_NOR_HEX: the extension is any hex value. The command and opcode
454 * combine to form a 16-bit opcode.
456 enum spi_nor_cmd_ext {
457 SPI_NOR_EXT_NONE = 0,
464 * struct flash_info - Forward declaration of a structure used internally by
470 * TODO: Remove, once all users of spi_flash interface are moved to MTD
473 * Defined below (keep this text to enable searching for spi_flash decl)
477 #define spi_flash spi_nor
481 * struct spi_nor - Structure for defining a the SPI NOR layer
482 * @mtd: point to a mtd_info structure
483 * @lock: the lock for the read/write/erase/lock/unlock operations
484 * @dev: point to a spi device, or a spi nor controller device.
485 * @info: spi-nor part JDEC MFR id and other info
486 * @manufacturer_sfdp: manufacturer specific SFDP table
487 * @page_size: the page size of the SPI NOR
488 * @addr_width: number of address bytes
489 * @erase_opcode: the opcode for erasing a sector
490 * @read_opcode: the read opcode
491 * @read_dummy: the dummy needed by the read operation
492 * @program_opcode: the program opcode
493 * @rdsr_dummy dummy cycles needed for Read Status Register command.
494 * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register
496 * @bank_read_cmd: Bank read cmd
497 * @bank_write_cmd: Bank write cmd
498 * @bank_curr: Current flash bank
499 * @sst_write_second: used by the SST write operation
500 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
501 * @read_proto: the SPI protocol for read operations
502 * @write_proto: the SPI protocol for write operations
503 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
504 * @cmd_buf: used by the write_reg
505 * @cmd_ext_type: the command opcode extension for DTR mode.
506 * @fixups: flash-specific fixup hooks.
507 * @prepare: [OPTIONAL] do some preparations for the
508 * read/write/erase/lock/unlock operations
509 * @unprepare: [OPTIONAL] do some post work after the
510 * read/write/erase/lock/unlock operations
511 * @read_reg: [DRIVER-SPECIFIC] read out the register
512 * @write_reg: [DRIVER-SPECIFIC] write data to the register
513 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
514 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
515 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
516 * at the offset @offs; if not provided by the driver,
517 * spi-nor will send the erase opcode via write_reg()
518 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
519 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
520 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
522 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
523 * @octal_dtr_enable: [FLASH-SPECIFIC] enables SPI NOR octal DTR mode.
524 * @ready: [FLASH-SPECIFIC] check if the flash is ready
525 * @priv: the private data
530 struct spi_slave *spi;
531 const struct flash_info *info;
532 u8 *manufacturer_sfdp;
541 #ifdef CONFIG_SPI_FLASH_BAR
546 enum spi_nor_protocol read_proto;
547 enum spi_nor_protocol write_proto;
548 enum spi_nor_protocol reg_proto;
549 bool sst_write_second;
551 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
552 enum spi_nor_cmd_ext cmd_ext_type;
553 struct spi_nor_fixups *fixups;
555 int (*setup)(struct spi_nor *nor, const struct flash_info *info,
556 const struct spi_nor_flash_parameter *params);
557 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
558 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
559 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
560 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
562 ssize_t (*read)(struct spi_nor *nor, loff_t from,
563 size_t len, u_char *read_buf);
564 ssize_t (*write)(struct spi_nor *nor, loff_t to,
565 size_t len, const u_char *write_buf);
566 int (*erase)(struct spi_nor *nor, loff_t offs);
568 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
569 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
570 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
571 int (*quad_enable)(struct spi_nor *nor);
572 int (*octal_dtr_enable)(struct spi_nor *nor);
573 int (*ready)(struct spi_nor *nor);
576 char mtd_name[MTD_NAME_SIZE(MTD_DEV_TYPE_NOR)];
577 /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
585 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
586 const struct device_node *np)
588 mtd_set_of_node(&nor->mtd, np);
591 static inline const struct
592 device_node *spi_nor_get_flash_node(struct spi_nor *nor)
594 return mtd_get_of_node(&nor->mtd);
596 #endif /* __UBOOT__ */
599 * spi_nor_scan() - scan the SPI NOR
600 * @nor: the spi_nor structure
602 * The drivers can use this function to scan the SPI NOR.
603 * In the scanning, it will try to get all the necessary information to
604 * fill the mtd_info{} and the spi_nor{}.
606 * Return: 0 for success, others for failure.
608 int spi_nor_scan(struct spi_nor *nor);
610 #if CONFIG_IS_ENABLED(SPI_FLASH_TINY)
611 static inline int spi_nor_remove(struct spi_nor *nor)
617 * spi_nor_remove() - perform cleanup before booting to the next stage
618 * @nor: the spi_nor structure
620 * Return: 0 for success, -errno for failure.
622 int spi_nor_remove(struct spi_nor *nor);