2 * linux/include/linux/mtd/nand.h
4 * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
23 #include <linux/wait.h>
24 #include <linux/spinlock.h>
25 #include <linux/mtd/mtd.h>
30 #include "linux/mtd/compat.h"
31 #include "linux/mtd/mtd.h"
32 #include "linux/mtd/bbm.h"
36 /* Scan and identify a NAND device */
37 extern int nand_scan (struct mtd_info *mtd, int max_chips);
38 /* Separate phases of nand_scan(), allowing board driver to intervene
39 * and override command or ECC setup according to flash type */
40 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
41 extern int nand_scan_tail(struct mtd_info *mtd);
43 /* Free resources held by the NAND device */
44 extern void nand_release (struct mtd_info *mtd);
46 /* Internal helper for board drivers which need to override command function */
47 extern void nand_wait_ready(struct mtd_info *mtd);
49 /* This constant declares the max. oobsize / page, which
50 * is supported now. If you add a chip with bigger oobsize/page
51 * adjust this accordingly.
53 #define NAND_MAX_OOBSIZE 218
54 #define NAND_MAX_PAGESIZE 4096
57 * Constants for hardware specific CLE/ALE/NCE function
59 * These are bits which can be or'ed to set/clear multiple
62 /* Select the chip by setting nCE to low */
64 /* Select the command latch by setting CLE to high */
66 /* Select the address latch by setting ALE to high */
69 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
70 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
71 #define NAND_CTRL_CHANGE 0x80
74 * Standard NAND flash commands
76 #define NAND_CMD_READ0 0
77 #define NAND_CMD_READ1 1
78 #define NAND_CMD_RNDOUT 5
79 #define NAND_CMD_PAGEPROG 0x10
80 #define NAND_CMD_READOOB 0x50
81 #define NAND_CMD_ERASE1 0x60
82 #define NAND_CMD_STATUS 0x70
83 #define NAND_CMD_STATUS_MULTI 0x71
84 #define NAND_CMD_SEQIN 0x80
85 #define NAND_CMD_RNDIN 0x85
86 #define NAND_CMD_READID 0x90
87 #define NAND_CMD_PARAM 0xec
88 #define NAND_CMD_ERASE2 0xd0
89 #define NAND_CMD_RESET 0xff
91 /* Extended commands for large page devices */
92 #define NAND_CMD_READSTART 0x30
93 #define NAND_CMD_RNDOUTSTART 0xE0
94 #define NAND_CMD_CACHEDPROG 0x15
96 /* Extended commands for AG-AND device */
98 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
99 * there is no way to distinguish that from NAND_CMD_READ0
100 * until the remaining sequence of commands has been completed
101 * so add a high order bit and mask it off in the command.
103 #define NAND_CMD_DEPLETE1 0x100
104 #define NAND_CMD_DEPLETE2 0x38
105 #define NAND_CMD_STATUS_MULTI 0x71
106 #define NAND_CMD_STATUS_ERROR 0x72
107 /* multi-bank error status (banks 0-3) */
108 #define NAND_CMD_STATUS_ERROR0 0x73
109 #define NAND_CMD_STATUS_ERROR1 0x74
110 #define NAND_CMD_STATUS_ERROR2 0x75
111 #define NAND_CMD_STATUS_ERROR3 0x76
112 #define NAND_CMD_STATUS_RESET 0x7f
113 #define NAND_CMD_STATUS_CLEAR 0xff
115 #define NAND_CMD_NONE -1
118 #define NAND_STATUS_FAIL 0x01
119 #define NAND_STATUS_FAIL_N1 0x02
120 #define NAND_STATUS_TRUE_READY 0x20
121 #define NAND_STATUS_READY 0x40
122 #define NAND_STATUS_WP 0x80
125 * Constants for ECC_MODES
131 NAND_ECC_HW_SYNDROME,
132 NAND_ECC_HW_OOB_FIRST,
136 * Constants for Hardware ECC
138 /* Reset Hardware ECC for read */
139 #define NAND_ECC_READ 0
140 /* Reset Hardware ECC for write */
141 #define NAND_ECC_WRITE 1
142 /* Enable Hardware ECC before syndrom is read back from flash */
143 #define NAND_ECC_READSYN 2
145 /* Bit mask for flags passed to do_nand_read_ecc */
146 #define NAND_GET_DEVICE 0x80
149 /* Option constants for bizarre disfunctionality and real
152 /* Chip can not auto increment pages */
153 #define NAND_NO_AUTOINCR 0x00000001
154 /* Buswitdh is 16 bit */
155 #define NAND_BUSWIDTH_16 0x00000002
156 /* Device supports partial programming without padding */
157 #define NAND_NO_PADDING 0x00000004
158 /* Chip has cache program function */
159 #define NAND_CACHEPRG 0x00000008
160 /* Chip has copy back function */
161 #define NAND_COPYBACK 0x00000010
162 /* AND Chip which has 4 banks and a confusing page / block
163 * assignment. See Renesas datasheet for further information */
164 #define NAND_IS_AND 0x00000020
165 /* Chip has a array of 4 pages which can be read without
166 * additional ready /busy waits */
167 #define NAND_4PAGE_ARRAY 0x00000040
168 /* Chip requires that BBT is periodically rewritten to prevent
169 * bits from adjacent blocks from 'leaking' in altering data.
170 * This happens with the Renesas AG-AND chips, possibly others. */
171 #define BBT_AUTO_REFRESH 0x00000080
172 /* Chip does not require ready check on read. True
173 * for all large page devices, as they do not support
175 #define NAND_NO_READRDY 0x00000100
176 /* Chip does not allow subpage writes */
177 #define NAND_NO_SUBPAGE_WRITE 0x00000200
180 /* Options valid for Samsung large page devices */
181 #define NAND_SAMSUNG_LP_OPTIONS \
182 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
184 /* Macros to identify the above */
185 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
186 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
187 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
188 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
189 /* Large page NAND with SOFT_ECC should support subpage reads */
190 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
191 && (chip->page_shift > 9))
193 /* Mask to zero out the chip options, which come from the id table */
194 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
196 /* Non chip related options */
197 /* Use a flash based bad block table. This option is passed to the
198 * default bad block table function. */
199 #define NAND_USE_FLASH_BBT 0x00010000
200 /* This option skips the bbt scan during initialization. */
201 #define NAND_SKIP_BBTSCAN 0x00020000
202 /* This option is defined if the board driver allocates its own buffers
203 (e.g. because it needs them DMA-coherent */
204 #define NAND_OWN_BUFFERS 0x00040000
205 /* Options set by nand scan */
206 /* bbt has already been read */
207 #define NAND_BBT_SCANNED 0x40000000
208 /* Nand scan has allocated controller struct */
209 #define NAND_CONTROLLER_ALLOC 0x80000000
211 /* Cell info constants */
212 #define NAND_CI_CHIPNR_MSK 0x03
213 #define NAND_CI_CELLTYPE_MSK 0x0C
219 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
220 * @lock: protection lock
221 * @active: the mtd device which holds the controller currently
222 * @wq: wait queue to sleep on if a NAND operation is in progress
223 * used instead of the per chip wait queue when a hw controller is available
225 struct nand_hw_control {
229 wait_queue_head_t wq;
231 struct nand_chip *active;
235 * struct nand_ecc_ctrl - Control structure for ecc
237 * @steps: number of ecc steps per page
238 * @size: data bytes per ecc step
239 * @bytes: ecc bytes per step
240 * @total: total number of ecc bytes per page
241 * @prepad: padding information for syndrome based ecc generators
242 * @postpad: padding information for syndrome based ecc generators
243 * @layout: ECC layout control struct pointer
244 * @hwctl: function to control hardware ecc generator. Must only
245 * be provided if an hardware ECC is available
246 * @calculate: function for ecc calculation or readback from ecc hardware
247 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
248 * @read_page_raw: function to read a raw page without ECC
249 * @write_page_raw: function to write a raw page without ECC
250 * @read_page: function to read a page according to the ecc generator requirements
251 * @write_page: function to write a page according to the ecc generator requirements
252 * @read_oob: function to read chip OOB data
253 * @write_oob: function to write chip OOB data
255 struct nand_ecc_ctrl {
256 nand_ecc_modes_t mode;
263 struct nand_ecclayout *layout;
264 void (*hwctl)(struct mtd_info *mtd, int mode);
265 int (*calculate)(struct mtd_info *mtd,
268 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
271 int (*read_page_raw)(struct mtd_info *mtd,
272 struct nand_chip *chip,
273 uint8_t *buf, int page);
274 void (*write_page_raw)(struct mtd_info *mtd,
275 struct nand_chip *chip,
277 int (*read_page)(struct mtd_info *mtd,
278 struct nand_chip *chip,
279 uint8_t *buf, int page);
280 int (*read_subpage)(struct mtd_info *mtd,
281 struct nand_chip *chip,
282 uint32_t offs, uint32_t len,
284 void (*write_page)(struct mtd_info *mtd,
285 struct nand_chip *chip,
287 int (*read_oob)(struct mtd_info *mtd,
288 struct nand_chip *chip,
291 int (*write_oob)(struct mtd_info *mtd,
292 struct nand_chip *chip,
297 * struct nand_buffers - buffer structure for read/write
298 * @ecccalc: buffer for calculated ecc
299 * @ecccode: buffer for ecc read from flash
300 * @databuf: buffer for data - dynamically sized
302 * Do not change the order of buffers. databuf and oobrbuf must be in
305 struct nand_buffers {
306 uint8_t ecccalc[NAND_MAX_OOBSIZE];
307 uint8_t ecccode[NAND_MAX_OOBSIZE];
308 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
312 * struct nand_chip - NAND Private Flash Chip Data
313 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
314 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
315 * @read_byte: [REPLACEABLE] read one byte from the chip
316 * @read_word: [REPLACEABLE] read one word from the chip
317 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
318 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
319 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
320 * @select_chip: [REPLACEABLE] select chip nr
321 * @block_bad: [REPLACEABLE] check, if the block is bad
322 * @block_markbad: [REPLACEABLE] mark the block bad
323 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
324 * ALE/CLE/nCE. Also used to write command and address
325 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
326 * If set to NULL no access to ready/busy is available and the ready/busy information
327 * is read from the chip status register
328 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
329 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
330 * @ecc: [BOARDSPECIFIC] ecc control ctructure
331 * @buffers: buffer structure for read/write
332 * @hwcontrol: platform-specific hardware control structure
333 * @ops: oob operation operands
334 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
335 * @scan_bbt: [REPLACEABLE] function to scan bad block table
336 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
337 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
338 * @state: [INTERN] the current state of the NAND device
339 * @oob_poi: poison value buffer
340 * @page_shift: [INTERN] number of address bits in a page (column address bits)
341 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
342 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
343 * @chip_shift: [INTERN] number of address bits in one chip
344 * @datbuf: [INTERN] internal buffer for one page + oob
345 * @oobbuf: [INTERN] oob buffer for one eraseblock
346 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
347 * @data_poi: [INTERN] pointer to a data buffer
348 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
349 * special functionality. See the defines for further explanation
350 * @badblockpos: [INTERN] position of the bad block marker in the oob area
351 * @cellinfo: [INTERN] MLC/multichip data from chip ident
352 * @numchips: [INTERN] number of physical chips
353 * @chipsize: [INTERN] the size of one chip for multichip arrays
354 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
355 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
356 * @subpagesize: [INTERN] holds the subpagesize
357 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
358 * @bbt: [INTERN] bad block table pointer
359 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
360 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
361 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
362 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
363 * which is shared among multiple independend devices
364 * @priv: [OPTIONAL] pointer to private chip date
365 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
366 * (determine if errors are correctable)
367 * @write_page: [REPLACEABLE] High-level page write function
371 void __iomem *IO_ADDR_R;
372 void __iomem *IO_ADDR_W;
374 uint8_t (*read_byte)(struct mtd_info *mtd);
375 u16 (*read_word)(struct mtd_info *mtd);
376 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
377 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
378 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
379 void (*select_chip)(struct mtd_info *mtd, int chip);
380 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
381 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
382 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
384 int (*dev_ready)(struct mtd_info *mtd);
385 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
386 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
387 void (*erase_cmd)(struct mtd_info *mtd, int page);
388 int (*scan_bbt)(struct mtd_info *mtd);
389 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
390 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
391 const uint8_t *buf, int page, int cached, int raw);
394 unsigned int options;
397 int phys_erase_shift;
411 struct nand_hw_control *controller;
412 struct nand_ecclayout *ecclayout;
414 struct nand_ecc_ctrl ecc;
415 struct nand_buffers *buffers;
417 struct nand_hw_control hwcontrol;
419 struct mtd_oob_ops ops;
422 struct nand_bbt_descr *bbt_td;
423 struct nand_bbt_descr *bbt_md;
425 struct nand_bbt_descr *badblock_pattern;
431 * NAND Flash Manufacturer ID Codes
433 #define NAND_MFR_TOSHIBA 0x98
434 #define NAND_MFR_SAMSUNG 0xec
435 #define NAND_MFR_FUJITSU 0x04
436 #define NAND_MFR_NATIONAL 0x8f
437 #define NAND_MFR_RENESAS 0x07
438 #define NAND_MFR_STMICRO 0x20
439 #define NAND_MFR_HYNIX 0xad
440 #define NAND_MFR_MICRON 0x2c
441 #define NAND_MFR_AMD 0x01
444 * struct nand_flash_dev - NAND Flash Device ID Structure
445 * @name: Identify the device type
446 * @id: device ID code
447 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
448 * If the pagesize is 0, then the real pagesize
449 * and the eraseize are determined from the
450 * extended id bytes in the chip
451 * @erasesize: Size of an erase block in the flash device.
452 * @chipsize: Total chipsize in Mega Bytes
453 * @options: Bitfield to store chip relevant options
455 struct nand_flash_dev {
458 unsigned long pagesize;
459 unsigned long chipsize;
460 unsigned long erasesize;
461 unsigned long options;
465 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
466 * @name: Manufacturer name
467 * @id: manufacturer ID code of device.
469 struct nand_manufacturers {
474 extern const struct nand_flash_dev nand_flash_ids[];
475 extern const struct nand_manufacturers nand_manuf_ids[];
477 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
478 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
479 extern int nand_default_bbt(struct mtd_info *mtd);
480 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
481 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
483 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
484 size_t * retlen, uint8_t * buf);
487 * Constants for oob configuration
489 #define NAND_SMALL_BADBLOCK_POS 5
490 #define NAND_LARGE_BADBLOCK_POS 0
493 * struct platform_nand_chip - chip level device structure
494 * @nr_chips: max. number of chips to scan for
495 * @chip_offset: chip number offset
496 * @nr_partitions: number of partitions pointed to by partitions (or zero)
497 * @partitions: mtd partition list
498 * @chip_delay: R/B delay value in us
499 * @options: Option flags, e.g. 16bit buswidth
500 * @ecclayout: ecc layout info structure
501 * @part_probe_types: NULL-terminated array of probe types
502 * @priv: hardware controller specific settings
504 struct platform_nand_chip {
508 struct mtd_partition *partitions;
509 struct nand_ecclayout *ecclayout;
511 unsigned int options;
512 const char **part_probe_types;
517 * struct platform_nand_ctrl - controller level device structure
518 * @hwcontrol: platform specific hardware control structure
519 * @dev_ready: platform specific function to read ready/busy pin
520 * @select_chip: platform specific chip select function
521 * @cmd_ctrl: platform specific function for controlling
522 * ALE/CLE/nCE. Also used to write command and address
523 * @priv: private data to transport driver specific settings
525 * All fields are optional and depend on the hardware driver requirements
527 struct platform_nand_ctrl {
528 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
529 int (*dev_ready)(struct mtd_info *mtd);
530 void (*select_chip)(struct mtd_info *mtd, int chip);
531 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
537 * struct platform_nand_data - container structure for platform-specific data
538 * @chip: chip level chip structure
539 * @ctrl: controller level device structure
541 struct platform_nand_data {
542 struct platform_nand_chip chip;
543 struct platform_nand_ctrl ctrl;
546 /* Some helpers to access the data structures */
548 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
550 struct nand_chip *chip = mtd->priv;
555 #endif /* __LINUX_MTD_NAND_H */