2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 struct nand_flash_dev;
29 /* Scan and identify a NAND device */
30 extern int nand_scan(struct mtd_info *mtd, int max_chips);
32 * Separate phases of nand_scan(), allowing board driver to intervene
33 * and override command or ECC setup according to flash type.
35 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
36 struct nand_flash_dev *table);
37 extern int nand_scan_tail(struct mtd_info *mtd);
39 /* Free resources held by the NAND device */
40 extern void nand_release(struct mtd_info *mtd);
42 /* Internal helper for board drivers which need to override command function */
43 extern void nand_wait_ready(struct mtd_info *mtd);
45 /* locks all blocks present in the device */
46 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
48 /* unlocks specified locked blocks */
49 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
51 /* The maximum number of NAND chips in an array */
52 #define NAND_MAX_CHIPS 8
55 * This constant declares the max. oobsize / page, which
56 * is supported now. If you add a chip with bigger oobsize/page
57 * adjust this accordingly.
59 #define NAND_MAX_OOBSIZE 640
60 #define NAND_MAX_PAGESIZE 8192
63 * Constants for hardware specific CLE/ALE/NCE function
65 * These are bits which can be or'ed to set/clear multiple
68 /* Select the chip by setting nCE to low */
70 /* Select the command latch by setting CLE to high */
72 /* Select the address latch by setting ALE to high */
75 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
76 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
77 #define NAND_CTRL_CHANGE 0x80
80 * Standard NAND flash commands
82 #define NAND_CMD_READ0 0
83 #define NAND_CMD_READ1 1
84 #define NAND_CMD_RNDOUT 5
85 #define NAND_CMD_PAGEPROG 0x10
86 #define NAND_CMD_READOOB 0x50
87 #define NAND_CMD_ERASE1 0x60
88 #define NAND_CMD_STATUS 0x70
89 #define NAND_CMD_SEQIN 0x80
90 #define NAND_CMD_RNDIN 0x85
91 #define NAND_CMD_READID 0x90
92 #define NAND_CMD_ERASE2 0xd0
93 #define NAND_CMD_PARAM 0xec
94 #define NAND_CMD_GET_FEATURES 0xee
95 #define NAND_CMD_SET_FEATURES 0xef
96 #define NAND_CMD_RESET 0xff
98 #define NAND_CMD_LOCK 0x2a
99 #define NAND_CMD_UNLOCK1 0x23
100 #define NAND_CMD_UNLOCK2 0x24
102 /* Extended commands for large page devices */
103 #define NAND_CMD_READSTART 0x30
104 #define NAND_CMD_RNDOUTSTART 0xE0
105 #define NAND_CMD_CACHEDPROG 0x15
107 #define NAND_CMD_NONE -1
110 #define NAND_STATUS_FAIL 0x01
111 #define NAND_STATUS_FAIL_N1 0x02
112 #define NAND_STATUS_TRUE_READY 0x20
113 #define NAND_STATUS_READY 0x40
114 #define NAND_STATUS_WP 0x80
117 * Constants for ECC_MODES
123 NAND_ECC_HW_SYNDROME,
124 NAND_ECC_HW_OOB_FIRST,
129 * Constants for Hardware ECC
131 /* Reset Hardware ECC for read */
132 #define NAND_ECC_READ 0
133 /* Reset Hardware ECC for write */
134 #define NAND_ECC_WRITE 1
135 /* Enable Hardware ECC before syndrome is read back from flash */
136 #define NAND_ECC_READSYN 2
138 /* Bit mask for flags passed to do_nand_read_ecc */
139 #define NAND_GET_DEVICE 0x80
143 * Option constants for bizarre disfunctionality and real
146 /* Buswidth is 16 bit */
147 #define NAND_BUSWIDTH_16 0x00000002
148 /* Device supports partial programming without padding */
149 #define NAND_NO_PADDING 0x00000004
150 /* Chip has cache program function */
151 #define NAND_CACHEPRG 0x00000008
152 /* Chip has copy back function */
153 #define NAND_COPYBACK 0x00000010
155 * Chip requires ready check on read (for auto-incremented sequential read).
156 * True only for small page devices; large page devices do not support
159 #define NAND_NEED_READRDY 0x00000100
161 /* Chip does not allow subpage writes */
162 #define NAND_NO_SUBPAGE_WRITE 0x00000200
164 /* Device is one of 'new' xD cards that expose fake nand command set */
165 #define NAND_BROKEN_XD 0x00000400
167 /* Device behaves just like nand, but is readonly */
168 #define NAND_ROM 0x00000800
170 /* Device supports subpage reads */
171 #define NAND_SUBPAGE_READ 0x00001000
173 /* Options valid for Samsung large page devices */
174 #define NAND_SAMSUNG_LP_OPTIONS \
175 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
177 /* Macros to identify the above */
178 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
179 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
180 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
181 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
183 /* Non chip related options */
184 /* This option skips the bbt scan during initialization. */
185 #define NAND_SKIP_BBTSCAN 0x00010000
187 * This option is defined if the board driver allocates its own buffers
188 * (e.g. because it needs them DMA-coherent).
190 #define NAND_OWN_BUFFERS 0x00020000
191 /* Chip may not exist, so silence any errors in scan */
192 #define NAND_SCAN_SILENT_NODEV 0x00040000
194 * Autodetect nand buswidth with readid/onfi.
195 * This suppose the driver will configure the hardware in 8 bits mode
196 * when calling nand_scan_ident, and update its configuration
197 * before calling nand_scan_tail.
199 #define NAND_BUSWIDTH_AUTO 0x00080000
201 /* Options set by nand scan */
202 /* Nand scan has allocated controller struct */
203 #define NAND_CONTROLLER_ALLOC 0x80000000
205 /* Cell info constants */
206 #define NAND_CI_CHIPNR_MSK 0x03
207 #define NAND_CI_CELLTYPE_MSK 0x0C
212 /* ONFI timing mode, used in both asynchronous and synchronous mode */
213 #define ONFI_TIMING_MODE_0 (1 << 0)
214 #define ONFI_TIMING_MODE_1 (1 << 1)
215 #define ONFI_TIMING_MODE_2 (1 << 2)
216 #define ONFI_TIMING_MODE_3 (1 << 3)
217 #define ONFI_TIMING_MODE_4 (1 << 4)
218 #define ONFI_TIMING_MODE_5 (1 << 5)
219 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
221 /* ONFI feature address */
222 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
224 /* ONFI subfeature parameters length */
225 #define ONFI_SUBFEATURE_PARAM_LEN 4
227 struct nand_onfi_params {
228 /* rev info and features block */
229 /* 'O' 'N' 'F' 'I' */
236 /* manufacturer information block */
237 char manufacturer[12];
243 /* memory organization block */
244 __le32 byte_per_page;
245 __le16 spare_bytes_per_page;
246 __le32 data_bytes_per_ppage;
247 __le16 spare_bytes_per_ppage;
248 __le32 pages_per_block;
249 __le32 blocks_per_lun;
254 __le16 block_endurance;
255 u8 guaranteed_good_blocks;
256 __le16 guaranteed_block_endurance;
257 u8 programs_per_page;
264 /* electrical parameter block */
265 u8 io_pin_capacitance_max;
266 __le16 async_timing_mode;
267 __le16 program_cache_timing_mode;
272 __le16 src_sync_timing_mode;
273 __le16 src_ssync_features;
274 __le16 clk_pin_capacitance_typ;
275 __le16 io_pin_capacitance_typ;
276 __le16 input_pin_capacitance_typ;
277 u8 input_pin_capacitance_max;
278 u8 driver_strenght_support;
287 } __attribute__((packed));
289 #define ONFI_CRC_BASE 0x4F4E
292 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
293 * @lock: protection lock
294 * @active: the mtd device which holds the controller currently
295 * @wq: wait queue to sleep on if a NAND operation is in
296 * progress used instead of the per chip wait queue
297 * when a hw controller is available.
299 struct nand_hw_control {
301 struct nand_chip *active;
302 wait_queue_head_t wq;
306 * struct nand_ecc_ctrl - Control structure for ECC
308 * @steps: number of ECC steps per page
309 * @size: data bytes per ECC step
310 * @bytes: ECC bytes per step
311 * @strength: max number of correctible bits per ECC step
312 * @total: total number of ECC bytes per page
313 * @prepad: padding information for syndrome based ECC generators
314 * @postpad: padding information for syndrome based ECC generators
315 * @layout: ECC layout control struct pointer
316 * @priv: pointer to private ECC control data
317 * @hwctl: function to control hardware ECC generator. Must only
318 * be provided if an hardware ECC is available
319 * @calculate: function for ECC calculation or readback from ECC hardware
320 * @correct: function for ECC correction, matching to ECC generator (sw/hw)
321 * @read_page_raw: function to read a raw page without ECC
322 * @write_page_raw: function to write a raw page without ECC
323 * @read_page: function to read a page according to the ECC generator
324 * requirements; returns maximum number of bitflips corrected in
325 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
326 * @read_subpage: function to read parts of the page covered by ECC;
327 * returns same as read_page()
328 * @write_page: function to write a page according to the ECC generator
330 * @write_oob_raw: function to write chip OOB data without ECC
331 * @read_oob_raw: function to read chip OOB data without ECC
332 * @read_oob: function to read chip OOB data
333 * @write_oob: function to write chip OOB data
335 struct nand_ecc_ctrl {
336 nand_ecc_modes_t mode;
344 struct nand_ecclayout *layout;
346 void (*hwctl)(struct mtd_info *mtd, int mode);
347 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
349 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
351 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
352 uint8_t *buf, int oob_required, int page);
353 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
354 const uint8_t *buf, int oob_required);
355 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
356 uint8_t *buf, int oob_required, int page);
357 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
358 uint32_t offs, uint32_t len, uint8_t *buf);
359 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
360 const uint8_t *buf, int oob_required);
361 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
363 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
365 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
366 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
371 * struct nand_buffers - buffer structure for read/write
372 * @ecccalc: buffer for calculated ECC
373 * @ecccode: buffer for ECC read from flash
374 * @databuf: buffer for data - dynamically sized
376 * Do not change the order of buffers. databuf and oobrbuf must be in
379 struct nand_buffers {
380 uint8_t ecccalc[NAND_MAX_OOBSIZE];
381 uint8_t ecccode[NAND_MAX_OOBSIZE];
382 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
386 * struct nand_chip - NAND Private Flash Chip Data
387 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
389 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
391 * @read_byte: [REPLACEABLE] read one byte from the chip
392 * @read_word: [REPLACEABLE] read one word from the chip
393 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
394 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
395 * @select_chip: [REPLACEABLE] select chip nr
396 * @block_bad: [REPLACEABLE] check, if the block is bad
397 * @block_markbad: [REPLACEABLE] mark the block bad
398 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
399 * ALE/CLE/nCE. Also used to write command and address
400 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
401 * mtd->oobsize, mtd->writesize and so on.
402 * @id_data contains the 8 bytes values of NAND_CMD_READID.
403 * Return with the bus width.
404 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
405 * device ready/busy line. If set to NULL no access to
406 * ready/busy is available and the ready/busy information
407 * is read from the chip status register.
408 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
409 * commands to the chip.
410 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
412 * @ecc: [BOARDSPECIFIC] ECC control structure
413 * @buffers: buffer structure for read/write
414 * @hwcontrol: platform-specific hardware control structure
415 * @erase_cmd: [INTERN] erase command write function, selectable due
417 * @scan_bbt: [REPLACEABLE] function to scan bad block table
418 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
419 * data from array to read regs (tR).
420 * @state: [INTERN] the current state of the NAND device
421 * @oob_poi: "poison value buffer," used for laying out OOB data
423 * @page_shift: [INTERN] number of address bits in a page (column
425 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
426 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
427 * @chip_shift: [INTERN] number of address bits in one chip
428 * @options: [BOARDSPECIFIC] various chip options. They can partly
429 * be set to inform nand_scan about special functionality.
430 * See the defines for further explanation.
431 * @bbt_options: [INTERN] bad block specific options. All options used
432 * here must come from bbm.h. By default, these options
433 * will be copied to the appropriate nand_bbt_descr's.
434 * @badblockpos: [INTERN] position of the bad block marker in the oob
436 * @badblockbits: [INTERN] minimum number of set bits in a good block's
437 * bad block marker position; i.e., BBM == 11110111b is
438 * not bad when badblockbits == 7
439 * @cellinfo: [INTERN] MLC/multichip data from chip ident
440 * @numchips: [INTERN] number of physical chips
441 * @chipsize: [INTERN] the size of one chip for multichip arrays
442 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
443 * @pagebuf: [INTERN] holds the pagenumber which is currently in
445 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
446 * currently in data_buf.
447 * @subpagesize: [INTERN] holds the subpagesize
448 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
449 * non 0 if ONFI supported.
450 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
451 * supported, 0 otherwise.
452 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
453 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
454 * @ecclayout: [REPLACEABLE] the default ECC placement scheme
455 * @bbt: [INTERN] bad block table pointer
456 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
458 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
459 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
461 * @controller: [REPLACEABLE] a pointer to a hardware controller
462 * structure which is shared among multiple independent
464 * @priv: [OPTIONAL] pointer to private chip data
465 * @errstat: [OPTIONAL] hardware specific function to perform
466 * additional error status checks (determine if errors are
468 * @write_page: [REPLACEABLE] High-level page write function
472 void __iomem *IO_ADDR_R;
473 void __iomem *IO_ADDR_W;
475 uint8_t (*read_byte)(struct mtd_info *mtd);
476 u16 (*read_word)(struct mtd_info *mtd);
477 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
478 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
479 void (*select_chip)(struct mtd_info *mtd, int chip);
480 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
481 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
482 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
483 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
485 int (*dev_ready)(struct mtd_info *mtd);
486 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
488 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
489 void (*erase_cmd)(struct mtd_info *mtd, int page);
490 int (*scan_bbt)(struct mtd_info *mtd);
491 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
492 int status, int page);
493 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
494 const uint8_t *buf, int oob_required, int page,
495 int cached, int raw);
496 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
497 int feature_addr, uint8_t *subfeature_para);
498 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
499 int feature_addr, uint8_t *subfeature_para);
502 unsigned int options;
503 unsigned int bbt_options;
506 int phys_erase_shift;
513 unsigned int pagebuf_bitflips;
520 struct nand_onfi_params onfi_params;
525 struct nand_hw_control *controller;
526 struct nand_ecclayout *ecclayout;
528 struct nand_ecc_ctrl ecc;
529 struct nand_buffers *buffers;
530 struct nand_hw_control hwcontrol;
533 struct nand_bbt_descr *bbt_td;
534 struct nand_bbt_descr *bbt_md;
536 struct nand_bbt_descr *badblock_pattern;
542 * NAND Flash Manufacturer ID Codes
544 #define NAND_MFR_TOSHIBA 0x98
545 #define NAND_MFR_SAMSUNG 0xec
546 #define NAND_MFR_FUJITSU 0x04
547 #define NAND_MFR_NATIONAL 0x8f
548 #define NAND_MFR_RENESAS 0x07
549 #define NAND_MFR_STMICRO 0x20
550 #define NAND_MFR_HYNIX 0xad
551 #define NAND_MFR_MICRON 0x2c
552 #define NAND_MFR_AMD 0x01
553 #define NAND_MFR_MACRONIX 0xc2
554 #define NAND_MFR_EON 0x92
557 * struct nand_flash_dev - NAND Flash Device ID Structure
558 * @name: Identify the device type
559 * @id: device ID code
560 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
561 * If the pagesize is 0, then the real pagesize
562 * and the eraseize are determined from the
563 * extended id bytes in the chip
564 * @erasesize: Size of an erase block in the flash device.
565 * @chipsize: Total chipsize in Mega Bytes
566 * @options: Bitfield to store chip relevant options
568 struct nand_flash_dev {
571 unsigned long pagesize;
572 unsigned long chipsize;
573 unsigned long erasesize;
574 unsigned long options;
578 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
579 * @name: Manufacturer name
580 * @id: manufacturer ID code of device.
582 struct nand_manufacturers {
587 extern struct nand_flash_dev nand_flash_ids[];
588 extern struct nand_manufacturers nand_manuf_ids[];
590 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
591 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
592 extern int nand_default_bbt(struct mtd_info *mtd);
593 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
594 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
596 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
597 size_t *retlen, uint8_t *buf);
600 * struct platform_nand_chip - chip level device structure
601 * @nr_chips: max. number of chips to scan for
602 * @chip_offset: chip number offset
603 * @nr_partitions: number of partitions pointed to by partitions (or zero)
604 * @partitions: mtd partition list
605 * @chip_delay: R/B delay value in us
606 * @options: Option flags, e.g. 16bit buswidth
607 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
608 * @ecclayout: ECC layout info structure
609 * @part_probe_types: NULL-terminated array of probe types
611 struct platform_nand_chip {
615 struct mtd_partition *partitions;
616 struct nand_ecclayout *ecclayout;
618 unsigned int options;
619 unsigned int bbt_options;
620 const char **part_probe_types;
624 struct platform_device;
627 * struct platform_nand_ctrl - controller level device structure
628 * @probe: platform specific function to probe/setup hardware
629 * @remove: platform specific function to remove/teardown hardware
630 * @hwcontrol: platform specific hardware control structure
631 * @dev_ready: platform specific function to read ready/busy pin
632 * @select_chip: platform specific chip select function
633 * @cmd_ctrl: platform specific function for controlling
634 * ALE/CLE/nCE. Also used to write command and address
635 * @write_buf: platform specific function for write buffer
636 * @read_buf: platform specific function for read buffer
637 * @read_byte: platform specific function to read one byte from chip
638 * @priv: private data to transport driver specific settings
640 * All fields are optional and depend on the hardware driver requirements
642 struct platform_nand_ctrl {
643 int (*probe)(struct platform_device *pdev);
644 void (*remove)(struct platform_device *pdev);
645 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
646 int (*dev_ready)(struct mtd_info *mtd);
647 void (*select_chip)(struct mtd_info *mtd, int chip);
648 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
649 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
650 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
651 unsigned char (*read_byte)(struct mtd_info *mtd);
656 * struct platform_nand_data - container structure for platform-specific data
657 * @chip: chip level chip structure
658 * @ctrl: controller level device structure
660 struct platform_nand_data {
661 struct platform_nand_chip chip;
662 struct platform_nand_ctrl ctrl;
665 /* Some helpers to access the data structures */
667 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
669 struct nand_chip *chip = mtd->priv;
674 /* return the supported asynchronous timing mode. */
675 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
677 if (!chip->onfi_version)
678 return ONFI_TIMING_MODE_UNKNOWN;
679 return le16_to_cpu(chip->onfi_params.async_timing_mode);
682 /* return the supported synchronous timing mode. */
683 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
685 if (!chip->onfi_version)
686 return ONFI_TIMING_MODE_UNKNOWN;
687 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
690 #endif /* __LINUX_MTD_NAND_H */