2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 struct nand_flash_dev;
29 /* Scan and identify a NAND device */
30 extern int nand_scan(struct mtd_info *mtd, int max_chips);
32 * Separate phases of nand_scan(), allowing board driver to intervene
33 * and override command or ECC setup according to flash type.
35 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
36 struct nand_flash_dev *table);
37 extern int nand_scan_tail(struct mtd_info *mtd);
39 /* Free resources held by the NAND device */
40 extern void nand_release(struct mtd_info *mtd);
42 /* Internal helper for board drivers which need to override command function */
43 extern void nand_wait_ready(struct mtd_info *mtd);
45 /* locks all blocks present in the device */
46 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
48 /* unlocks specified locked blocks */
49 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
51 /* The maximum number of NAND chips in an array */
52 #define NAND_MAX_CHIPS 8
55 * This constant declares the max. oobsize / page, which
56 * is supported now. If you add a chip with bigger oobsize/page
57 * adjust this accordingly.
59 #define NAND_MAX_OOBSIZE 640
60 #define NAND_MAX_PAGESIZE 8192
63 * Constants for hardware specific CLE/ALE/NCE function
65 * These are bits which can be or'ed to set/clear multiple
68 /* Select the chip by setting nCE to low */
70 /* Select the command latch by setting CLE to high */
72 /* Select the address latch by setting ALE to high */
75 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
76 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
77 #define NAND_CTRL_CHANGE 0x80
80 * Standard NAND flash commands
82 #define NAND_CMD_READ0 0
83 #define NAND_CMD_READ1 1
84 #define NAND_CMD_RNDOUT 5
85 #define NAND_CMD_PAGEPROG 0x10
86 #define NAND_CMD_READOOB 0x50
87 #define NAND_CMD_ERASE1 0x60
88 #define NAND_CMD_STATUS 0x70
89 #define NAND_CMD_SEQIN 0x80
90 #define NAND_CMD_RNDIN 0x85
91 #define NAND_CMD_READID 0x90
92 #define NAND_CMD_ERASE2 0xd0
93 #define NAND_CMD_PARAM 0xec
94 #define NAND_CMD_GET_FEATURES 0xee
95 #define NAND_CMD_SET_FEATURES 0xef
96 #define NAND_CMD_RESET 0xff
98 #define NAND_CMD_LOCK 0x2a
99 #define NAND_CMD_UNLOCK1 0x23
100 #define NAND_CMD_UNLOCK2 0x24
102 /* Extended commands for large page devices */
103 #define NAND_CMD_READSTART 0x30
104 #define NAND_CMD_RNDOUTSTART 0xE0
105 #define NAND_CMD_CACHEDPROG 0x15
107 #define NAND_CMD_NONE -1
110 #define NAND_STATUS_FAIL 0x01
111 #define NAND_STATUS_FAIL_N1 0x02
112 #define NAND_STATUS_TRUE_READY 0x20
113 #define NAND_STATUS_READY 0x40
114 #define NAND_STATUS_WP 0x80
117 * Constants for ECC_MODES
123 NAND_ECC_HW_SYNDROME,
124 NAND_ECC_HW_OOB_FIRST,
129 * Constants for Hardware ECC
131 /* Reset Hardware ECC for read */
132 #define NAND_ECC_READ 0
133 /* Reset Hardware ECC for write */
134 #define NAND_ECC_WRITE 1
135 /* Enable Hardware ECC before syndrome is read back from flash */
136 #define NAND_ECC_READSYN 2
138 /* Bit mask for flags passed to do_nand_read_ecc */
139 #define NAND_GET_DEVICE 0x80
143 * Option constants for bizarre disfunctionality and real
146 /* Buswidth is 16 bit */
147 #define NAND_BUSWIDTH_16 0x00000002
148 /* Chip has cache program function */
149 #define NAND_CACHEPRG 0x00000008
150 /* Chip has copy back function */
151 #define NAND_COPYBACK 0x00000010
153 * Chip requires ready check on read (for auto-incremented sequential read).
154 * True only for small page devices; large page devices do not support
157 #define NAND_NEED_READRDY 0x00000100
159 /* Chip does not allow subpage writes */
160 #define NAND_NO_SUBPAGE_WRITE 0x00000200
162 /* Device is one of 'new' xD cards that expose fake nand command set */
163 #define NAND_BROKEN_XD 0x00000400
165 /* Device behaves just like nand, but is readonly */
166 #define NAND_ROM 0x00000800
168 /* Device supports subpage reads */
169 #define NAND_SUBPAGE_READ 0x00001000
171 /* Options valid for Samsung large page devices */
172 #define NAND_SAMSUNG_LP_OPTIONS (NAND_CACHEPRG | NAND_COPYBACK)
174 /* Macros to identify the above */
175 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
176 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
177 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
179 /* Non chip related options */
180 /* This option skips the bbt scan during initialization. */
181 #define NAND_SKIP_BBTSCAN 0x00010000
183 * This option is defined if the board driver allocates its own buffers
184 * (e.g. because it needs them DMA-coherent).
186 #define NAND_OWN_BUFFERS 0x00020000
187 /* Chip may not exist, so silence any errors in scan */
188 #define NAND_SCAN_SILENT_NODEV 0x00040000
190 * Autodetect nand buswidth with readid/onfi.
191 * This suppose the driver will configure the hardware in 8 bits mode
192 * when calling nand_scan_ident, and update its configuration
193 * before calling nand_scan_tail.
195 #define NAND_BUSWIDTH_AUTO 0x00080000
197 /* Options set by nand scan */
198 /* Nand scan has allocated controller struct */
199 #define NAND_CONTROLLER_ALLOC 0x80000000
201 /* Cell info constants */
202 #define NAND_CI_CHIPNR_MSK 0x03
203 #define NAND_CI_CELLTYPE_MSK 0x0C
208 /* ONFI timing mode, used in both asynchronous and synchronous mode */
209 #define ONFI_TIMING_MODE_0 (1 << 0)
210 #define ONFI_TIMING_MODE_1 (1 << 1)
211 #define ONFI_TIMING_MODE_2 (1 << 2)
212 #define ONFI_TIMING_MODE_3 (1 << 3)
213 #define ONFI_TIMING_MODE_4 (1 << 4)
214 #define ONFI_TIMING_MODE_5 (1 << 5)
215 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
217 /* ONFI feature address */
218 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
220 /* ONFI subfeature parameters length */
221 #define ONFI_SUBFEATURE_PARAM_LEN 4
223 struct nand_onfi_params {
224 /* rev info and features block */
225 /* 'O' 'N' 'F' 'I' */
232 /* manufacturer information block */
233 char manufacturer[12];
239 /* memory organization block */
240 __le32 byte_per_page;
241 __le16 spare_bytes_per_page;
242 __le32 data_bytes_per_ppage;
243 __le16 spare_bytes_per_ppage;
244 __le32 pages_per_block;
245 __le32 blocks_per_lun;
250 __le16 block_endurance;
251 u8 guaranteed_good_blocks;
252 __le16 guaranteed_block_endurance;
253 u8 programs_per_page;
260 /* electrical parameter block */
261 u8 io_pin_capacitance_max;
262 __le16 async_timing_mode;
263 __le16 program_cache_timing_mode;
268 __le16 src_sync_timing_mode;
269 __le16 src_ssync_features;
270 __le16 clk_pin_capacitance_typ;
271 __le16 io_pin_capacitance_typ;
272 __le16 input_pin_capacitance_typ;
273 u8 input_pin_capacitance_max;
274 u8 driver_strenght_support;
283 } __attribute__((packed));
285 #define ONFI_CRC_BASE 0x4F4E
288 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
289 * @lock: protection lock
290 * @active: the mtd device which holds the controller currently
291 * @wq: wait queue to sleep on if a NAND operation is in
292 * progress used instead of the per chip wait queue
293 * when a hw controller is available.
295 struct nand_hw_control {
297 struct nand_chip *active;
298 wait_queue_head_t wq;
302 * struct nand_ecc_ctrl - Control structure for ECC
304 * @steps: number of ECC steps per page
305 * @size: data bytes per ECC step
306 * @bytes: ECC bytes per step
307 * @strength: max number of correctible bits per ECC step
308 * @total: total number of ECC bytes per page
309 * @prepad: padding information for syndrome based ECC generators
310 * @postpad: padding information for syndrome based ECC generators
311 * @layout: ECC layout control struct pointer
312 * @priv: pointer to private ECC control data
313 * @hwctl: function to control hardware ECC generator. Must only
314 * be provided if an hardware ECC is available
315 * @calculate: function for ECC calculation or readback from ECC hardware
316 * @correct: function for ECC correction, matching to ECC generator (sw/hw)
317 * @read_page_raw: function to read a raw page without ECC
318 * @write_page_raw: function to write a raw page without ECC
319 * @read_page: function to read a page according to the ECC generator
320 * requirements; returns maximum number of bitflips corrected in
321 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
322 * @read_subpage: function to read parts of the page covered by ECC;
323 * returns same as read_page()
324 * @write_page: function to write a page according to the ECC generator
326 * @write_oob_raw: function to write chip OOB data without ECC
327 * @read_oob_raw: function to read chip OOB data without ECC
328 * @read_oob: function to read chip OOB data
329 * @write_oob: function to write chip OOB data
331 struct nand_ecc_ctrl {
332 nand_ecc_modes_t mode;
340 struct nand_ecclayout *layout;
342 void (*hwctl)(struct mtd_info *mtd, int mode);
343 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
345 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
347 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
348 uint8_t *buf, int oob_required, int page);
349 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
350 const uint8_t *buf, int oob_required);
351 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
352 uint8_t *buf, int oob_required, int page);
353 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
354 uint32_t offs, uint32_t len, uint8_t *buf);
355 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
356 const uint8_t *buf, int oob_required);
357 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
359 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
361 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
362 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
367 * struct nand_buffers - buffer structure for read/write
368 * @ecccalc: buffer for calculated ECC
369 * @ecccode: buffer for ECC read from flash
370 * @databuf: buffer for data - dynamically sized
372 * Do not change the order of buffers. databuf and oobrbuf must be in
375 struct nand_buffers {
376 uint8_t ecccalc[NAND_MAX_OOBSIZE];
377 uint8_t ecccode[NAND_MAX_OOBSIZE];
378 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
382 * struct nand_chip - NAND Private Flash Chip Data
383 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
385 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
387 * @read_byte: [REPLACEABLE] read one byte from the chip
388 * @read_word: [REPLACEABLE] read one word from the chip
389 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
390 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
391 * @select_chip: [REPLACEABLE] select chip nr
392 * @block_bad: [REPLACEABLE] check, if the block is bad
393 * @block_markbad: [REPLACEABLE] mark the block bad
394 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
395 * ALE/CLE/nCE. Also used to write command and address
396 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
397 * mtd->oobsize, mtd->writesize and so on.
398 * @id_data contains the 8 bytes values of NAND_CMD_READID.
399 * Return with the bus width.
400 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
401 * device ready/busy line. If set to NULL no access to
402 * ready/busy is available and the ready/busy information
403 * is read from the chip status register.
404 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
405 * commands to the chip.
406 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
408 * @ecc: [BOARDSPECIFIC] ECC control structure
409 * @buffers: buffer structure for read/write
410 * @hwcontrol: platform-specific hardware control structure
411 * @erase_cmd: [INTERN] erase command write function, selectable due
413 * @scan_bbt: [REPLACEABLE] function to scan bad block table
414 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
415 * data from array to read regs (tR).
416 * @state: [INTERN] the current state of the NAND device
417 * @oob_poi: "poison value buffer," used for laying out OOB data
419 * @page_shift: [INTERN] number of address bits in a page (column
421 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
422 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
423 * @chip_shift: [INTERN] number of address bits in one chip
424 * @options: [BOARDSPECIFIC] various chip options. They can partly
425 * be set to inform nand_scan about special functionality.
426 * See the defines for further explanation.
427 * @bbt_options: [INTERN] bad block specific options. All options used
428 * here must come from bbm.h. By default, these options
429 * will be copied to the appropriate nand_bbt_descr's.
430 * @badblockpos: [INTERN] position of the bad block marker in the oob
432 * @badblockbits: [INTERN] minimum number of set bits in a good block's
433 * bad block marker position; i.e., BBM == 11110111b is
434 * not bad when badblockbits == 7
435 * @cellinfo: [INTERN] MLC/multichip data from chip ident
436 * @numchips: [INTERN] number of physical chips
437 * @chipsize: [INTERN] the size of one chip for multichip arrays
438 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
439 * @pagebuf: [INTERN] holds the pagenumber which is currently in
441 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
442 * currently in data_buf.
443 * @subpagesize: [INTERN] holds the subpagesize
444 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
445 * non 0 if ONFI supported.
446 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
447 * supported, 0 otherwise.
448 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
449 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
450 * @ecclayout: [REPLACEABLE] the default ECC placement scheme
451 * @bbt: [INTERN] bad block table pointer
452 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
454 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
455 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
457 * @controller: [REPLACEABLE] a pointer to a hardware controller
458 * structure which is shared among multiple independent
460 * @priv: [OPTIONAL] pointer to private chip data
461 * @errstat: [OPTIONAL] hardware specific function to perform
462 * additional error status checks (determine if errors are
464 * @write_page: [REPLACEABLE] High-level page write function
468 void __iomem *IO_ADDR_R;
469 void __iomem *IO_ADDR_W;
471 uint8_t (*read_byte)(struct mtd_info *mtd);
472 u16 (*read_word)(struct mtd_info *mtd);
473 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
474 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
475 void (*select_chip)(struct mtd_info *mtd, int chip);
476 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
477 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
478 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
479 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
481 int (*dev_ready)(struct mtd_info *mtd);
482 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
484 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
485 void (*erase_cmd)(struct mtd_info *mtd, int page);
486 int (*scan_bbt)(struct mtd_info *mtd);
487 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
488 int status, int page);
489 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
490 const uint8_t *buf, int oob_required, int page,
491 int cached, int raw);
492 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
493 int feature_addr, uint8_t *subfeature_para);
494 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
495 int feature_addr, uint8_t *subfeature_para);
498 unsigned int options;
499 unsigned int bbt_options;
502 int phys_erase_shift;
509 unsigned int pagebuf_bitflips;
516 struct nand_onfi_params onfi_params;
521 struct nand_hw_control *controller;
522 struct nand_ecclayout *ecclayout;
524 struct nand_ecc_ctrl ecc;
525 struct nand_buffers *buffers;
526 struct nand_hw_control hwcontrol;
529 struct nand_bbt_descr *bbt_td;
530 struct nand_bbt_descr *bbt_md;
532 struct nand_bbt_descr *badblock_pattern;
538 * NAND Flash Manufacturer ID Codes
540 #define NAND_MFR_TOSHIBA 0x98
541 #define NAND_MFR_SAMSUNG 0xec
542 #define NAND_MFR_FUJITSU 0x04
543 #define NAND_MFR_NATIONAL 0x8f
544 #define NAND_MFR_RENESAS 0x07
545 #define NAND_MFR_STMICRO 0x20
546 #define NAND_MFR_HYNIX 0xad
547 #define NAND_MFR_MICRON 0x2c
548 #define NAND_MFR_AMD 0x01
549 #define NAND_MFR_MACRONIX 0xc2
550 #define NAND_MFR_EON 0x92
553 * struct nand_flash_dev - NAND Flash Device ID Structure
554 * @name: Identify the device type
555 * @id: device ID code
556 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
557 * If the pagesize is 0, then the real pagesize
558 * and the eraseize are determined from the
559 * extended id bytes in the chip
560 * @erasesize: Size of an erase block in the flash device.
561 * @chipsize: Total chipsize in Mega Bytes
562 * @options: Bitfield to store chip relevant options
564 struct nand_flash_dev {
567 unsigned long pagesize;
568 unsigned long chipsize;
569 unsigned long erasesize;
570 unsigned long options;
574 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
575 * @name: Manufacturer name
576 * @id: manufacturer ID code of device.
578 struct nand_manufacturers {
583 extern struct nand_flash_dev nand_flash_ids[];
584 extern struct nand_manufacturers nand_manuf_ids[];
586 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
587 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
588 extern int nand_default_bbt(struct mtd_info *mtd);
589 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
590 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
592 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
593 size_t *retlen, uint8_t *buf);
596 * struct platform_nand_chip - chip level device structure
597 * @nr_chips: max. number of chips to scan for
598 * @chip_offset: chip number offset
599 * @nr_partitions: number of partitions pointed to by partitions (or zero)
600 * @partitions: mtd partition list
601 * @chip_delay: R/B delay value in us
602 * @options: Option flags, e.g. 16bit buswidth
603 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
604 * @ecclayout: ECC layout info structure
605 * @part_probe_types: NULL-terminated array of probe types
607 struct platform_nand_chip {
611 struct mtd_partition *partitions;
612 struct nand_ecclayout *ecclayout;
614 unsigned int options;
615 unsigned int bbt_options;
616 const char **part_probe_types;
620 struct platform_device;
623 * struct platform_nand_ctrl - controller level device structure
624 * @probe: platform specific function to probe/setup hardware
625 * @remove: platform specific function to remove/teardown hardware
626 * @hwcontrol: platform specific hardware control structure
627 * @dev_ready: platform specific function to read ready/busy pin
628 * @select_chip: platform specific chip select function
629 * @cmd_ctrl: platform specific function for controlling
630 * ALE/CLE/nCE. Also used to write command and address
631 * @write_buf: platform specific function for write buffer
632 * @read_buf: platform specific function for read buffer
633 * @read_byte: platform specific function to read one byte from chip
634 * @priv: private data to transport driver specific settings
636 * All fields are optional and depend on the hardware driver requirements
638 struct platform_nand_ctrl {
639 int (*probe)(struct platform_device *pdev);
640 void (*remove)(struct platform_device *pdev);
641 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
642 int (*dev_ready)(struct mtd_info *mtd);
643 void (*select_chip)(struct mtd_info *mtd, int chip);
644 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
645 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
646 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
647 unsigned char (*read_byte)(struct mtd_info *mtd);
652 * struct platform_nand_data - container structure for platform-specific data
653 * @chip: chip level chip structure
654 * @ctrl: controller level device structure
656 struct platform_nand_data {
657 struct platform_nand_chip chip;
658 struct platform_nand_ctrl ctrl;
661 /* Some helpers to access the data structures */
663 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
665 struct nand_chip *chip = mtd->priv;
670 /* return the supported asynchronous timing mode. */
671 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
673 if (!chip->onfi_version)
674 return ONFI_TIMING_MODE_UNKNOWN;
675 return le16_to_cpu(chip->onfi_params.async_timing_mode);
678 /* return the supported synchronous timing mode. */
679 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
681 if (!chip->onfi_version)
682 return ONFI_TIMING_MODE_UNKNOWN;
683 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
686 #endif /* __LINUX_MTD_NAND_H */