include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  68         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  69         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  70         MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
  71 };
  72
  73 enum {
  74         MLX5_SHARED_RESOURCE_UID = 0xffff,
  75 };
  76
  77 enum {
  78         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  79 };
  80
  81 enum {
  82         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  83         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  84         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  85 };
  86
  87 enum {
  88         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  89         MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
  90         MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
  91         MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
  92         MLX5_OBJ_TYPE_MKEY = 0xff01,
  93         MLX5_OBJ_TYPE_QP = 0xff02,
  94         MLX5_OBJ_TYPE_PSV = 0xff03,
  95         MLX5_OBJ_TYPE_RMP = 0xff04,
  96         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
  97         MLX5_OBJ_TYPE_RQ = 0xff06,
  98         MLX5_OBJ_TYPE_SQ = 0xff07,
  99         MLX5_OBJ_TYPE_TIR = 0xff08,
 100         MLX5_OBJ_TYPE_TIS = 0xff09,
 101         MLX5_OBJ_TYPE_DCT = 0xff0a,
 102         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 103         MLX5_OBJ_TYPE_RQT = 0xff0e,
 104         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 105         MLX5_OBJ_TYPE_CQ = 0xff10,
 106 };
 107
 108 enum {
 109         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 110         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 111         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 112         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 113         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 114         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 115         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 116         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 117         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 118         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 119         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 120         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 121         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 122         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 123         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 124         MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
 125         MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
 126         MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
 127         MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
 128         MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
 129         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 130         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 131         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 132         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 133         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 134         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 135         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 136         MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
 137         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 138         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 139         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 140         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 141         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 142         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 143         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 144         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 145         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 146         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 147         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 148         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 149         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 150         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 151         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 152         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 153         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 154         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 155         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 156         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 157         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 158         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 159         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 160         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 161         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 162         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 163         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 164         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 165         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 166         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 167         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 168         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 169         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 170         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 171         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 172         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 173         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 174         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 175         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 176         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 177         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 178         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 179         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 180         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 181         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 182         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 183         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 184         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 185         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 186         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 187         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 188         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 189         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 190         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 191         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 192         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 193         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 194         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 195         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 196         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 197         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 198         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 199         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 200         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 201         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 202         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 203         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 204         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 205         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 206         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 207         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 208         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 209         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 210         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 211         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 212         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 213         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 214         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 215         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 216         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 217         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 218         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 219         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 220         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 221         MLX5_CMD_OP_NOP                           = 0x80d,
 222         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 223         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 224         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 225         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 226         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 227         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 228         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 229         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 230         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 231         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 232         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 233         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 234         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 235         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 236         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 237         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 238         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 239         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 240         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 241         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 242         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 243         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 244         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 245         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 246         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 247         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 248         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 249         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 250         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 251         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 252         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 253         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 254         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 255         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 256         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 257         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 258         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 259         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 260         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 261         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 262         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 263         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 264         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 265         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 266         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 267         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 268         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 269         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 270         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 271         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 272         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 273         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 274         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 275         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 276         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 277         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 278         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 279         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 280         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 281         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 282         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 283         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 284         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 285         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 286         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 287         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 288         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 289         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 290         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 291         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 292         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 293         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 294         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 295         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 296         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 297         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 298         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 299         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 300         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 301         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 302         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 303         MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
 304         MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
 305         MLX5_CMD_OP_MAX
 306 };
 307
 308 /* Valid range for general commands that don't work over an object */
 309 enum {
 310         MLX5_CMD_OP_GENERAL_START = 0xb00,
 311         MLX5_CMD_OP_GENERAL_END = 0xd00,
 312 };
 313
 314 struct mlx5_ifc_flow_table_fields_supported_bits {
 315         u8         outer_dmac[0x1];
 316         u8         outer_smac[0x1];
 317         u8         outer_ether_type[0x1];
 318         u8         outer_ip_version[0x1];
 319         u8         outer_first_prio[0x1];
 320         u8         outer_first_cfi[0x1];
 321         u8         outer_first_vid[0x1];
 322         u8         outer_ipv4_ttl[0x1];
 323         u8         outer_second_prio[0x1];
 324         u8         outer_second_cfi[0x1];
 325         u8         outer_second_vid[0x1];
 326         u8         reserved_at_b[0x1];
 327         u8         outer_sip[0x1];
 328         u8         outer_dip[0x1];
 329         u8         outer_frag[0x1];
 330         u8         outer_ip_protocol[0x1];
 331         u8         outer_ip_ecn[0x1];
 332         u8         outer_ip_dscp[0x1];
 333         u8         outer_udp_sport[0x1];
 334         u8         outer_udp_dport[0x1];
 335         u8         outer_tcp_sport[0x1];
 336         u8         outer_tcp_dport[0x1];
 337         u8         outer_tcp_flags[0x1];
 338         u8         outer_gre_protocol[0x1];
 339         u8         outer_gre_key[0x1];
 340         u8         outer_vxlan_vni[0x1];
 341         u8         outer_geneve_vni[0x1];
 342         u8         outer_geneve_oam[0x1];
 343         u8         outer_geneve_protocol_type[0x1];
 344         u8         outer_geneve_opt_len[0x1];
 345         u8         source_vhca_port[0x1];
 346         u8         source_eswitch_port[0x1];
 347
 348         u8         inner_dmac[0x1];
 349         u8         inner_smac[0x1];
 350         u8         inner_ether_type[0x1];
 351         u8         inner_ip_version[0x1];
 352         u8         inner_first_prio[0x1];
 353         u8         inner_first_cfi[0x1];
 354         u8         inner_first_vid[0x1];
 355         u8         reserved_at_27[0x1];
 356         u8         inner_second_prio[0x1];
 357         u8         inner_second_cfi[0x1];
 358         u8         inner_second_vid[0x1];
 359         u8         reserved_at_2b[0x1];
 360         u8         inner_sip[0x1];
 361         u8         inner_dip[0x1];
 362         u8         inner_frag[0x1];
 363         u8         inner_ip_protocol[0x1];
 364         u8         inner_ip_ecn[0x1];
 365         u8         inner_ip_dscp[0x1];
 366         u8         inner_udp_sport[0x1];
 367         u8         inner_udp_dport[0x1];
 368         u8         inner_tcp_sport[0x1];
 369         u8         inner_tcp_dport[0x1];
 370         u8         inner_tcp_flags[0x1];
 371         u8         reserved_at_37[0x9];
 372
 373         u8         geneve_tlv_option_0_data[0x1];
 374         u8         geneve_tlv_option_0_exist[0x1];
 375         u8         reserved_at_42[0x3];
 376         u8         outer_first_mpls_over_udp[0x4];
 377         u8         outer_first_mpls_over_gre[0x4];
 378         u8         inner_first_mpls[0x4];
 379         u8         outer_first_mpls[0x4];
 380         u8         reserved_at_55[0x2];
 381         u8         outer_esp_spi[0x1];
 382         u8         reserved_at_58[0x2];
 383         u8         bth_dst_qp[0x1];
 384         u8         reserved_at_5b[0x5];
 385
 386         u8         reserved_at_60[0x18];
 387         u8         metadata_reg_c_7[0x1];
 388         u8         metadata_reg_c_6[0x1];
 389         u8         metadata_reg_c_5[0x1];
 390         u8         metadata_reg_c_4[0x1];
 391         u8         metadata_reg_c_3[0x1];
 392         u8         metadata_reg_c_2[0x1];
 393         u8         metadata_reg_c_1[0x1];
 394         u8         metadata_reg_c_0[0x1];
 395 };
 396
 397 struct mlx5_ifc_flow_table_fields_supported_2_bits {
 398         u8         reserved_at_0[0xe];
 399         u8         bth_opcode[0x1];
 400         u8         reserved_at_f[0x11];
 401
 402         u8         reserved_at_20[0x60];
 403 };
 404
 405 struct mlx5_ifc_flow_table_prop_layout_bits {
 406         u8         ft_support[0x1];
 407         u8         reserved_at_1[0x1];
 408         u8         flow_counter[0x1];
 409         u8         flow_modify_en[0x1];
 410         u8         modify_root[0x1];
 411         u8         identified_miss_table_mode[0x1];
 412         u8         flow_table_modify[0x1];
 413         u8         reformat[0x1];
 414         u8         decap[0x1];
 415         u8         reserved_at_9[0x1];
 416         u8         pop_vlan[0x1];
 417         u8         push_vlan[0x1];
 418         u8         reserved_at_c[0x1];
 419         u8         pop_vlan_2[0x1];
 420         u8         push_vlan_2[0x1];
 421         u8         reformat_and_vlan_action[0x1];
 422         u8         reserved_at_10[0x1];
 423         u8         sw_owner[0x1];
 424         u8         reformat_l3_tunnel_to_l2[0x1];
 425         u8         reformat_l2_to_l3_tunnel[0x1];
 426         u8         reformat_and_modify_action[0x1];
 427         u8         ignore_flow_level[0x1];
 428         u8         reserved_at_16[0x1];
 429         u8         table_miss_action_domain[0x1];
 430         u8         termination_table[0x1];
 431         u8         reformat_and_fwd_to_table[0x1];
 432         u8         reserved_at_1a[0x2];
 433         u8         ipsec_encrypt[0x1];
 434         u8         ipsec_decrypt[0x1];
 435         u8         sw_owner_v2[0x1];
 436         u8         reserved_at_1f[0x1];
 437
 438         u8         termination_table_raw_traffic[0x1];
 439         u8         reserved_at_21[0x1];
 440         u8         log_max_ft_size[0x6];
 441         u8         log_max_modify_header_context[0x8];
 442         u8         max_modify_header_actions[0x8];
 443         u8         max_ft_level[0x8];
 444
 445         u8         reserved_at_40[0x6];
 446         u8         execute_aso[0x1];
 447         u8         reserved_at_47[0x19];
 448
 449         u8         reserved_at_60[0x2];
 450         u8         reformat_insert[0x1];
 451         u8         reformat_remove[0x1];
 452         u8         reserver_at_64[0x14];
 453         u8         log_max_ft_num[0x8];
 454
 455         u8         reserved_at_80[0x10];
 456         u8         log_max_flow_counter[0x8];
 457         u8         log_max_destination[0x8];
 458
 459         u8         reserved_at_a0[0x18];
 460         u8         log_max_flow[0x8];
 461
 462         u8         reserved_at_c0[0x40];
 463
 464         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 465
 466         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 467 };
 468
 469 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 470         u8         send[0x1];
 471         u8         receive[0x1];
 472         u8         write[0x1];
 473         u8         read[0x1];
 474         u8         atomic[0x1];
 475         u8         srq_receive[0x1];
 476         u8         reserved_at_6[0x1a];
 477 };
 478
 479 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 480         u8         smac_47_16[0x20];
 481
 482         u8         smac_15_0[0x10];
 483         u8         ethertype[0x10];
 484
 485         u8         dmac_47_16[0x20];
 486
 487         u8         dmac_15_0[0x10];
 488         u8         first_prio[0x3];
 489         u8         first_cfi[0x1];
 490         u8         first_vid[0xc];
 491
 492         u8         ip_protocol[0x8];
 493         u8         ip_dscp[0x6];
 494         u8         ip_ecn[0x2];
 495         u8         cvlan_tag[0x1];
 496         u8         svlan_tag[0x1];
 497         u8         frag[0x1];
 498         u8         ip_version[0x4];
 499         u8         tcp_flags[0x9];
 500
 501         u8         tcp_sport[0x10];
 502         u8         tcp_dport[0x10];
 503
 504         u8         reserved_at_c0[0x10];
 505         u8         ipv4_ihl[0x4];
 506         u8         reserved_at_c4[0x4];
 507
 508         u8         ttl_hoplimit[0x8];
 509
 510         u8         udp_sport[0x10];
 511         u8         udp_dport[0x10];
 512
 513         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 514
 515         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 516 };
 517
 518 struct mlx5_ifc_nvgre_key_bits {
 519         u8 hi[0x18];
 520         u8 lo[0x8];
 521 };
 522
 523 union mlx5_ifc_gre_key_bits {
 524         struct mlx5_ifc_nvgre_key_bits nvgre;
 525         u8 key[0x20];
 526 };
 527
 528 struct mlx5_ifc_fte_match_set_misc_bits {
 529         u8         gre_c_present[0x1];
 530         u8         reserved_at_1[0x1];
 531         u8         gre_k_present[0x1];
 532         u8         gre_s_present[0x1];
 533         u8         source_vhca_port[0x4];
 534         u8         source_sqn[0x18];
 535
 536         u8         source_eswitch_owner_vhca_id[0x10];
 537         u8         source_port[0x10];
 538
 539         u8         outer_second_prio[0x3];
 540         u8         outer_second_cfi[0x1];
 541         u8         outer_second_vid[0xc];
 542         u8         inner_second_prio[0x3];
 543         u8         inner_second_cfi[0x1];
 544         u8         inner_second_vid[0xc];
 545
 546         u8         outer_second_cvlan_tag[0x1];
 547         u8         inner_second_cvlan_tag[0x1];
 548         u8         outer_second_svlan_tag[0x1];
 549         u8         inner_second_svlan_tag[0x1];
 550         u8         reserved_at_64[0xc];
 551         u8         gre_protocol[0x10];
 552
 553         union mlx5_ifc_gre_key_bits gre_key;
 554
 555         u8         vxlan_vni[0x18];
 556         u8         bth_opcode[0x8];
 557
 558         u8         geneve_vni[0x18];
 559         u8         reserved_at_d8[0x6];
 560         u8         geneve_tlv_option_0_exist[0x1];
 561         u8         geneve_oam[0x1];
 562
 563         u8         reserved_at_e0[0xc];
 564         u8         outer_ipv6_flow_label[0x14];
 565
 566         u8         reserved_at_100[0xc];
 567         u8         inner_ipv6_flow_label[0x14];
 568
 569         u8         reserved_at_120[0xa];
 570         u8         geneve_opt_len[0x6];
 571         u8         geneve_protocol_type[0x10];
 572
 573         u8         reserved_at_140[0x8];
 574         u8         bth_dst_qp[0x18];
 575         u8         reserved_at_160[0x20];
 576         u8         outer_esp_spi[0x20];
 577         u8         reserved_at_1a0[0x60];
 578 };
 579
 580 struct mlx5_ifc_fte_match_mpls_bits {
 581         u8         mpls_label[0x14];
 582         u8         mpls_exp[0x3];
 583         u8         mpls_s_bos[0x1];
 584         u8         mpls_ttl[0x8];
 585 };
 586
 587 struct mlx5_ifc_fte_match_set_misc2_bits {
 588         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 589
 590         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 591
 592         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 593
 594         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 595
 596         u8         metadata_reg_c_7[0x20];
 597
 598         u8         metadata_reg_c_6[0x20];
 599
 600         u8         metadata_reg_c_5[0x20];
 601
 602         u8         metadata_reg_c_4[0x20];
 603
 604         u8         metadata_reg_c_3[0x20];
 605
 606         u8         metadata_reg_c_2[0x20];
 607
 608         u8         metadata_reg_c_1[0x20];
 609
 610         u8         metadata_reg_c_0[0x20];
 611
 612         u8         metadata_reg_a[0x20];
 613
 614         u8         reserved_at_1a0[0x60];
 615 };
 616
 617 struct mlx5_ifc_fte_match_set_misc3_bits {
 618         u8         inner_tcp_seq_num[0x20];
 619
 620         u8         outer_tcp_seq_num[0x20];
 621
 622         u8         inner_tcp_ack_num[0x20];
 623
 624         u8         outer_tcp_ack_num[0x20];
 625
 626         u8         reserved_at_80[0x8];
 627         u8         outer_vxlan_gpe_vni[0x18];
 628
 629         u8         outer_vxlan_gpe_next_protocol[0x8];
 630         u8         outer_vxlan_gpe_flags[0x8];
 631         u8         reserved_at_b0[0x10];
 632
 633         u8         icmp_header_data[0x20];
 634
 635         u8         icmpv6_header_data[0x20];
 636
 637         u8         icmp_type[0x8];
 638         u8         icmp_code[0x8];
 639         u8         icmpv6_type[0x8];
 640         u8         icmpv6_code[0x8];
 641
 642         u8         geneve_tlv_option_0_data[0x20];
 643
 644         u8         gtpu_teid[0x20];
 645
 646         u8         gtpu_msg_type[0x8];
 647         u8         gtpu_msg_flags[0x8];
 648         u8         reserved_at_170[0x10];
 649
 650         u8         gtpu_dw_2[0x20];
 651
 652         u8         gtpu_first_ext_dw_0[0x20];
 653
 654         u8         gtpu_dw_0[0x20];
 655
 656         u8         reserved_at_1e0[0x20];
 657 };
 658
 659 struct mlx5_ifc_fte_match_set_misc4_bits {
 660         u8         prog_sample_field_value_0[0x20];
 661
 662         u8         prog_sample_field_id_0[0x20];
 663
 664         u8         prog_sample_field_value_1[0x20];
 665
 666         u8         prog_sample_field_id_1[0x20];
 667
 668         u8         prog_sample_field_value_2[0x20];
 669
 670         u8         prog_sample_field_id_2[0x20];
 671
 672         u8         prog_sample_field_value_3[0x20];
 673
 674         u8         prog_sample_field_id_3[0x20];
 675
 676         u8         reserved_at_100[0x100];
 677 };
 678
 679 struct mlx5_ifc_fte_match_set_misc5_bits {
 680         u8         macsec_tag_0[0x20];
 681
 682         u8         macsec_tag_1[0x20];
 683
 684         u8         macsec_tag_2[0x20];
 685
 686         u8         macsec_tag_3[0x20];
 687
 688         u8         tunnel_header_0[0x20];
 689
 690         u8         tunnel_header_1[0x20];
 691
 692         u8         tunnel_header_2[0x20];
 693
 694         u8         tunnel_header_3[0x20];
 695
 696         u8         reserved_at_100[0x100];
 697 };
 698
 699 struct mlx5_ifc_cmd_pas_bits {
 700         u8         pa_h[0x20];
 701
 702         u8         pa_l[0x14];
 703         u8         reserved_at_34[0xc];
 704 };
 705
 706 struct mlx5_ifc_uint64_bits {
 707         u8         hi[0x20];
 708
 709         u8         lo[0x20];
 710 };
 711
 712 enum {
 713         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 714         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 715         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 716         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 717         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 718         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 719         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 720         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 721         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 722         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 723 };
 724
 725 struct mlx5_ifc_ads_bits {
 726         u8         fl[0x1];
 727         u8         free_ar[0x1];
 728         u8         reserved_at_2[0xe];
 729         u8         pkey_index[0x10];
 730
 731         u8         reserved_at_20[0x8];
 732         u8         grh[0x1];
 733         u8         mlid[0x7];
 734         u8         rlid[0x10];
 735
 736         u8         ack_timeout[0x5];
 737         u8         reserved_at_45[0x3];
 738         u8         src_addr_index[0x8];
 739         u8         reserved_at_50[0x4];
 740         u8         stat_rate[0x4];
 741         u8         hop_limit[0x8];
 742
 743         u8         reserved_at_60[0x4];
 744         u8         tclass[0x8];
 745         u8         flow_label[0x14];
 746
 747         u8         rgid_rip[16][0x8];
 748
 749         u8         reserved_at_100[0x4];
 750         u8         f_dscp[0x1];
 751         u8         f_ecn[0x1];
 752         u8         reserved_at_106[0x1];
 753         u8         f_eth_prio[0x1];
 754         u8         ecn[0x2];
 755         u8         dscp[0x6];
 756         u8         udp_sport[0x10];
 757
 758         u8         dei_cfi[0x1];
 759         u8         eth_prio[0x3];
 760         u8         sl[0x4];
 761         u8         vhca_port_num[0x8];
 762         u8         rmac_47_32[0x10];
 763
 764         u8         rmac_31_0[0x20];
 765 };
 766
 767 struct mlx5_ifc_flow_table_nic_cap_bits {
 768         u8         nic_rx_multi_path_tirs[0x1];
 769         u8         nic_rx_multi_path_tirs_fts[0x1];
 770         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 771         u8         reserved_at_3[0x4];
 772         u8         sw_owner_reformat_supported[0x1];
 773         u8         reserved_at_8[0x18];
 774
 775         u8         encap_general_header[0x1];
 776         u8         reserved_at_21[0xa];
 777         u8         log_max_packet_reformat_context[0x5];
 778         u8         reserved_at_30[0x6];
 779         u8         max_encap_header_size[0xa];
 780         u8         reserved_at_40[0x1c0];
 781
 782         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 783
 784         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 785
 786         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 787
 788         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 789
 790         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 791
 792         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 793
 794         u8         reserved_at_e00[0x700];
 795
 796         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
 797
 798         u8         reserved_at_1580[0x280];
 799
 800         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
 801
 802         u8         reserved_at_1880[0x780];
 803
 804         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 805
 806         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 807
 808         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 809
 810         u8         reserved_at_20c0[0x5f40];
 811 };
 812
 813 struct mlx5_ifc_port_selection_cap_bits {
 814         u8         reserved_at_0[0x10];
 815         u8         port_select_flow_table[0x1];
 816         u8         reserved_at_11[0xf];
 817
 818         u8         reserved_at_20[0x1e0];
 819
 820         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
 821
 822         u8         reserved_at_400[0x7c00];
 823 };
 824
 825 enum {
 826         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 827         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 828         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 829         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 830         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 831         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 832         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 833         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 834 };
 835
 836 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 837         u8      fdb_to_vport_reg_c_id[0x8];
 838         u8      reserved_at_8[0xd];
 839         u8      fdb_modify_header_fwd_to_table[0x1];
 840         u8      fdb_ipv4_ttl_modify[0x1];
 841         u8      flow_source[0x1];
 842         u8      reserved_at_18[0x2];
 843         u8      multi_fdb_encap[0x1];
 844         u8      egress_acl_forward_to_vport[0x1];
 845         u8      fdb_multi_path_to_table[0x1];
 846         u8      reserved_at_1d[0x3];
 847
 848         u8      reserved_at_20[0x1e0];
 849
 850         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 851
 852         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 853
 854         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 855
 856         u8      reserved_at_800[0x1000];
 857
 858         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 859
 860         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 861
 862         u8      sw_steering_uplink_icm_address_rx[0x40];
 863
 864         u8      sw_steering_uplink_icm_address_tx[0x40];
 865
 866         u8      reserved_at_1900[0x6700];
 867 };
 868
 869 enum {
 870         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 871         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 872 };
 873
 874 struct mlx5_ifc_e_switch_cap_bits {
 875         u8         vport_svlan_strip[0x1];
 876         u8         vport_cvlan_strip[0x1];
 877         u8         vport_svlan_insert[0x1];
 878         u8         vport_cvlan_insert_if_not_exist[0x1];
 879         u8         vport_cvlan_insert_overwrite[0x1];
 880         u8         reserved_at_5[0x2];
 881         u8         esw_shared_ingress_acl[0x1];
 882         u8         esw_uplink_ingress_acl[0x1];
 883         u8         root_ft_on_other_esw[0x1];
 884         u8         reserved_at_a[0xf];
 885         u8         esw_functions_changed[0x1];
 886         u8         reserved_at_1a[0x1];
 887         u8         ecpf_vport_exists[0x1];
 888         u8         counter_eswitch_affinity[0x1];
 889         u8         merged_eswitch[0x1];
 890         u8         nic_vport_node_guid_modify[0x1];
 891         u8         nic_vport_port_guid_modify[0x1];
 892
 893         u8         vxlan_encap_decap[0x1];
 894         u8         nvgre_encap_decap[0x1];
 895         u8         reserved_at_22[0x1];
 896         u8         log_max_fdb_encap_uplink[0x5];
 897         u8         reserved_at_21[0x3];
 898         u8         log_max_packet_reformat_context[0x5];
 899         u8         reserved_2b[0x6];
 900         u8         max_encap_header_size[0xa];
 901
 902         u8         reserved_at_40[0xb];
 903         u8         log_max_esw_sf[0x5];
 904         u8         esw_sf_base_id[0x10];
 905
 906         u8         reserved_at_60[0x7a0];
 907
 908 };
 909
 910 struct mlx5_ifc_qos_cap_bits {
 911         u8         packet_pacing[0x1];
 912         u8         esw_scheduling[0x1];
 913         u8         esw_bw_share[0x1];
 914         u8         esw_rate_limit[0x1];
 915         u8         reserved_at_4[0x1];
 916         u8         packet_pacing_burst_bound[0x1];
 917         u8         packet_pacing_typical_size[0x1];
 918         u8         reserved_at_7[0x1];
 919         u8         nic_sq_scheduling[0x1];
 920         u8         nic_bw_share[0x1];
 921         u8         nic_rate_limit[0x1];
 922         u8         packet_pacing_uid[0x1];
 923         u8         log_esw_max_sched_depth[0x4];
 924         u8         reserved_at_10[0x10];
 925
 926         u8         reserved_at_20[0xb];
 927         u8         log_max_qos_nic_queue_group[0x5];
 928         u8         reserved_at_30[0x10];
 929
 930         u8         packet_pacing_max_rate[0x20];
 931
 932         u8         packet_pacing_min_rate[0x20];
 933
 934         u8         reserved_at_80[0x10];
 935         u8         packet_pacing_rate_table_size[0x10];
 936
 937         u8         esw_element_type[0x10];
 938         u8         esw_tsar_type[0x10];
 939
 940         u8         reserved_at_c0[0x10];
 941         u8         max_qos_para_vport[0x10];
 942
 943         u8         max_tsar_bw_share[0x20];
 944
 945         u8         reserved_at_100[0x20];
 946
 947         u8         reserved_at_120[0x3];
 948         u8         log_meter_aso_granularity[0x5];
 949         u8         reserved_at_128[0x3];
 950         u8         log_meter_aso_max_alloc[0x5];
 951         u8         reserved_at_130[0x3];
 952         u8         log_max_num_meter_aso[0x5];
 953         u8         reserved_at_138[0x8];
 954
 955         u8         reserved_at_140[0x6c0];
 956 };
 957
 958 struct mlx5_ifc_debug_cap_bits {
 959         u8         core_dump_general[0x1];
 960         u8         core_dump_qp[0x1];
 961         u8         reserved_at_2[0x7];
 962         u8         resource_dump[0x1];
 963         u8         reserved_at_a[0x16];
 964
 965         u8         reserved_at_20[0x2];
 966         u8         stall_detect[0x1];
 967         u8         reserved_at_23[0x1d];
 968
 969         u8         reserved_at_40[0x7c0];
 970 };
 971
 972 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 973         u8         csum_cap[0x1];
 974         u8         vlan_cap[0x1];
 975         u8         lro_cap[0x1];
 976         u8         lro_psh_flag[0x1];
 977         u8         lro_time_stamp[0x1];
 978         u8         reserved_at_5[0x2];
 979         u8         wqe_vlan_insert[0x1];
 980         u8         self_lb_en_modifiable[0x1];
 981         u8         reserved_at_9[0x2];
 982         u8         max_lso_cap[0x5];
 983         u8         multi_pkt_send_wqe[0x2];
 984         u8         wqe_inline_mode[0x2];
 985         u8         rss_ind_tbl_cap[0x4];
 986         u8         reg_umr_sq[0x1];
 987         u8         scatter_fcs[0x1];
 988         u8         enhanced_multi_pkt_send_wqe[0x1];
 989         u8         tunnel_lso_const_out_ip_id[0x1];
 990         u8         tunnel_lro_gre[0x1];
 991         u8         tunnel_lro_vxlan[0x1];
 992         u8         tunnel_stateless_gre[0x1];
 993         u8         tunnel_stateless_vxlan[0x1];
 994
 995         u8         swp[0x1];
 996         u8         swp_csum[0x1];
 997         u8         swp_lso[0x1];
 998         u8         cqe_checksum_full[0x1];
 999         u8         tunnel_stateless_geneve_tx[0x1];
1000         u8         tunnel_stateless_mpls_over_udp[0x1];
1001         u8         tunnel_stateless_mpls_over_gre[0x1];
1002         u8         tunnel_stateless_vxlan_gpe[0x1];
1003         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1004         u8         tunnel_stateless_ip_over_ip[0x1];
1005         u8         insert_trailer[0x1];
1006         u8         reserved_at_2b[0x1];
1007         u8         tunnel_stateless_ip_over_ip_rx[0x1];
1008         u8         tunnel_stateless_ip_over_ip_tx[0x1];
1009         u8         reserved_at_2e[0x2];
1010         u8         max_vxlan_udp_ports[0x8];
1011         u8         reserved_at_38[0x6];
1012         u8         max_geneve_opt_len[0x1];
1013         u8         tunnel_stateless_geneve_rx[0x1];
1014
1015         u8         reserved_at_40[0x10];
1016         u8         lro_min_mss_size[0x10];
1017
1018         u8         reserved_at_60[0x120];
1019
1020         u8         lro_timer_supported_periods[4][0x20];
1021
1022         u8         reserved_at_200[0x600];
1023 };
1024
1025 enum {
1026         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1027         MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1028         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1029 };
1030
1031 struct mlx5_ifc_roce_cap_bits {
1032         u8         roce_apm[0x1];
1033         u8         reserved_at_1[0x3];
1034         u8         sw_r_roce_src_udp_port[0x1];
1035         u8         fl_rc_qp_when_roce_disabled[0x1];
1036         u8         fl_rc_qp_when_roce_enabled[0x1];
1037         u8         reserved_at_7[0x17];
1038         u8         qp_ts_format[0x2];
1039
1040         u8         reserved_at_20[0x60];
1041
1042         u8         reserved_at_80[0xc];
1043         u8         l3_type[0x4];
1044         u8         reserved_at_90[0x8];
1045         u8         roce_version[0x8];
1046
1047         u8         reserved_at_a0[0x10];
1048         u8         r_roce_dest_udp_port[0x10];
1049
1050         u8         r_roce_max_src_udp_port[0x10];
1051         u8         r_roce_min_src_udp_port[0x10];
1052
1053         u8         reserved_at_e0[0x10];
1054         u8         roce_address_table_size[0x10];
1055
1056         u8         reserved_at_100[0x700];
1057 };
1058
1059 struct mlx5_ifc_sync_steering_in_bits {
1060         u8         opcode[0x10];
1061         u8         uid[0x10];
1062
1063         u8         reserved_at_20[0x10];
1064         u8         op_mod[0x10];
1065
1066         u8         reserved_at_40[0xc0];
1067 };
1068
1069 struct mlx5_ifc_sync_steering_out_bits {
1070         u8         status[0x8];
1071         u8         reserved_at_8[0x18];
1072
1073         u8         syndrome[0x20];
1074
1075         u8         reserved_at_40[0x40];
1076 };
1077
1078 struct mlx5_ifc_device_mem_cap_bits {
1079         u8         memic[0x1];
1080         u8         reserved_at_1[0x1f];
1081
1082         u8         reserved_at_20[0xb];
1083         u8         log_min_memic_alloc_size[0x5];
1084         u8         reserved_at_30[0x8];
1085         u8         log_max_memic_addr_alignment[0x8];
1086
1087         u8         memic_bar_start_addr[0x40];
1088
1089         u8         memic_bar_size[0x20];
1090
1091         u8         max_memic_size[0x20];
1092
1093         u8         steering_sw_icm_start_address[0x40];
1094
1095         u8         reserved_at_100[0x8];
1096         u8         log_header_modify_sw_icm_size[0x8];
1097         u8         reserved_at_110[0x2];
1098         u8         log_sw_icm_alloc_granularity[0x6];
1099         u8         log_steering_sw_icm_size[0x8];
1100
1101         u8         reserved_at_120[0x18];
1102         u8         log_header_modify_pattern_sw_icm_size[0x8];
1103
1104         u8         header_modify_sw_icm_start_address[0x40];
1105
1106         u8         reserved_at_180[0x40];
1107
1108         u8         header_modify_pattern_sw_icm_start_address[0x40];
1109
1110         u8         memic_operations[0x20];
1111
1112         u8         reserved_at_220[0x5e0];
1113 };
1114
1115 struct mlx5_ifc_device_event_cap_bits {
1116         u8         user_affiliated_events[4][0x40];
1117
1118         u8         user_unaffiliated_events[4][0x40];
1119 };
1120
1121 struct mlx5_ifc_virtio_emulation_cap_bits {
1122         u8         desc_tunnel_offload_type[0x1];
1123         u8         eth_frame_offload_type[0x1];
1124         u8         virtio_version_1_0[0x1];
1125         u8         device_features_bits_mask[0xd];
1126         u8         event_mode[0x8];
1127         u8         virtio_queue_type[0x8];
1128
1129         u8         max_tunnel_desc[0x10];
1130         u8         reserved_at_30[0x3];
1131         u8         log_doorbell_stride[0x5];
1132         u8         reserved_at_38[0x3];
1133         u8         log_doorbell_bar_size[0x5];
1134
1135         u8         doorbell_bar_offset[0x40];
1136
1137         u8         max_emulated_devices[0x8];
1138         u8         max_num_virtio_queues[0x18];
1139
1140         u8         reserved_at_a0[0x60];
1141
1142         u8         umem_1_buffer_param_a[0x20];
1143
1144         u8         umem_1_buffer_param_b[0x20];
1145
1146         u8         umem_2_buffer_param_a[0x20];
1147
1148         u8         umem_2_buffer_param_b[0x20];
1149
1150         u8         umem_3_buffer_param_a[0x20];
1151
1152         u8         umem_3_buffer_param_b[0x20];
1153
1154         u8         reserved_at_1c0[0x640];
1155 };
1156
1157 enum {
1158         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1159         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1160         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1161         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1162         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1163         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1164         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1165         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1166         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1167 };
1168
1169 enum {
1170         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1171         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1172         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1173         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1174         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1175         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1176         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1177         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1178         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1179 };
1180
1181 struct mlx5_ifc_atomic_caps_bits {
1182         u8         reserved_at_0[0x40];
1183
1184         u8         atomic_req_8B_endianness_mode[0x2];
1185         u8         reserved_at_42[0x4];
1186         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1187
1188         u8         reserved_at_47[0x19];
1189
1190         u8         reserved_at_60[0x20];
1191
1192         u8         reserved_at_80[0x10];
1193         u8         atomic_operations[0x10];
1194
1195         u8         reserved_at_a0[0x10];
1196         u8         atomic_size_qp[0x10];
1197
1198         u8         reserved_at_c0[0x10];
1199         u8         atomic_size_dc[0x10];
1200
1201         u8         reserved_at_e0[0x720];
1202 };
1203
1204 struct mlx5_ifc_odp_cap_bits {
1205         u8         reserved_at_0[0x40];
1206
1207         u8         sig[0x1];
1208         u8         reserved_at_41[0x1f];
1209
1210         u8         reserved_at_60[0x20];
1211
1212         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1213
1214         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1215
1216         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1217
1218         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1219
1220         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1221
1222         u8         reserved_at_120[0x6E0];
1223 };
1224
1225 struct mlx5_ifc_calc_op {
1226         u8        reserved_at_0[0x10];
1227         u8        reserved_at_10[0x9];
1228         u8        op_swap_endianness[0x1];
1229         u8        op_min[0x1];
1230         u8        op_xor[0x1];
1231         u8        op_or[0x1];
1232         u8        op_and[0x1];
1233         u8        op_max[0x1];
1234         u8        op_add[0x1];
1235 };
1236
1237 struct mlx5_ifc_vector_calc_cap_bits {
1238         u8         calc_matrix[0x1];
1239         u8         reserved_at_1[0x1f];
1240         u8         reserved_at_20[0x8];
1241         u8         max_vec_count[0x8];
1242         u8         reserved_at_30[0xd];
1243         u8         max_chunk_size[0x3];
1244         struct mlx5_ifc_calc_op calc0;
1245         struct mlx5_ifc_calc_op calc1;
1246         struct mlx5_ifc_calc_op calc2;
1247         struct mlx5_ifc_calc_op calc3;
1248
1249         u8         reserved_at_c0[0x720];
1250 };
1251
1252 struct mlx5_ifc_tls_cap_bits {
1253         u8         tls_1_2_aes_gcm_128[0x1];
1254         u8         tls_1_3_aes_gcm_128[0x1];
1255         u8         tls_1_2_aes_gcm_256[0x1];
1256         u8         tls_1_3_aes_gcm_256[0x1];
1257         u8         reserved_at_4[0x1c];
1258
1259         u8         reserved_at_20[0x7e0];
1260 };
1261
1262 struct mlx5_ifc_ipsec_cap_bits {
1263         u8         ipsec_full_offload[0x1];
1264         u8         ipsec_crypto_offload[0x1];
1265         u8         ipsec_esn[0x1];
1266         u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1267         u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1268         u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1269         u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1270         u8         reserved_at_7[0x4];
1271         u8         log_max_ipsec_offload[0x5];
1272         u8         reserved_at_10[0x10];
1273
1274         u8         min_log_ipsec_full_replay_window[0x8];
1275         u8         max_log_ipsec_full_replay_window[0x8];
1276         u8         reserved_at_30[0x7d0];
1277 };
1278
1279 enum {
1280         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1281         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1282         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1283         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1284 };
1285
1286 enum {
1287         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1288         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1289 };
1290
1291 enum {
1292         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1293         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1294         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1295         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1296         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1297 };
1298
1299 enum {
1300         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1301         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1302         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1303         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1304         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1305         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1306 };
1307
1308 enum {
1309         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1310         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1311 };
1312
1313 enum {
1314         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1315         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1316         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1317 };
1318
1319 enum {
1320         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1321         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1322 };
1323
1324 enum {
1325         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1326         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1327         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1328 };
1329
1330 enum {
1331         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1332         MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED  = 1 << 4,
1333         MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED  = 1 << 5,
1334         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1335         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1336         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1337         MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1338         MLX5_FLEX_PARSER_GTPU_ENABLED           = 1 << 11,
1339         MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED      = 1 << 16,
1340         MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1341         MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED      = 1 << 18,
1342         MLX5_FLEX_PARSER_GTPU_TEID_ENABLED      = 1 << 19,
1343 };
1344
1345 enum {
1346         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1347         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1348 };
1349
1350 #define MLX5_FC_BULK_SIZE_FACTOR 128
1351
1352 enum mlx5_fc_bulk_alloc_bitmask {
1353         MLX5_FC_BULK_128   = (1 << 0),
1354         MLX5_FC_BULK_256   = (1 << 1),
1355         MLX5_FC_BULK_512   = (1 << 2),
1356         MLX5_FC_BULK_1024  = (1 << 3),
1357         MLX5_FC_BULK_2048  = (1 << 4),
1358         MLX5_FC_BULK_4096  = (1 << 5),
1359         MLX5_FC_BULK_8192  = (1 << 6),
1360         MLX5_FC_BULK_16384 = (1 << 7),
1361 };
1362
1363 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1364
1365 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1366
1367 enum {
1368         MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1369         MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1370         MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1371 };
1372
1373 struct mlx5_ifc_cmd_hca_cap_bits {
1374         u8         reserved_at_0[0x1f];
1375         u8         vhca_resource_manager[0x1];
1376
1377         u8         hca_cap_2[0x1];
1378         u8         create_lag_when_not_master_up[0x1];
1379         u8         dtor[0x1];
1380         u8         event_on_vhca_state_teardown_request[0x1];
1381         u8         event_on_vhca_state_in_use[0x1];
1382         u8         event_on_vhca_state_active[0x1];
1383         u8         event_on_vhca_state_allocated[0x1];
1384         u8         event_on_vhca_state_invalid[0x1];
1385         u8         reserved_at_28[0x8];
1386         u8         vhca_id[0x10];
1387
1388         u8         reserved_at_40[0x40];
1389
1390         u8         log_max_srq_sz[0x8];
1391         u8         log_max_qp_sz[0x8];
1392         u8         event_cap[0x1];
1393         u8         reserved_at_91[0x2];
1394         u8         isolate_vl_tc_new[0x1];
1395         u8         reserved_at_94[0x4];
1396         u8         prio_tag_required[0x1];
1397         u8         reserved_at_99[0x2];
1398         u8         log_max_qp[0x5];
1399
1400         u8         reserved_at_a0[0x3];
1401         u8         ece_support[0x1];
1402         u8         reserved_at_a4[0x5];
1403         u8         reg_c_preserve[0x1];
1404         u8         reserved_at_aa[0x1];
1405         u8         log_max_srq[0x5];
1406         u8         reserved_at_b0[0x1];
1407         u8         uplink_follow[0x1];
1408         u8         ts_cqe_to_dest_cqn[0x1];
1409         u8         reserved_at_b3[0x7];
1410         u8         shampo[0x1];
1411         u8         reserved_at_bb[0x5];
1412
1413         u8         max_sgl_for_optimized_performance[0x8];
1414         u8         log_max_cq_sz[0x8];
1415         u8         relaxed_ordering_write_umr[0x1];
1416         u8         relaxed_ordering_read_umr[0x1];
1417         u8         reserved_at_d2[0x7];
1418         u8         virtio_net_device_emualtion_manager[0x1];
1419         u8         virtio_blk_device_emualtion_manager[0x1];
1420         u8         log_max_cq[0x5];
1421
1422         u8         log_max_eq_sz[0x8];
1423         u8         relaxed_ordering_write[0x1];
1424         u8         relaxed_ordering_read[0x1];
1425         u8         log_max_mkey[0x6];
1426         u8         reserved_at_f0[0x8];
1427         u8         dump_fill_mkey[0x1];
1428         u8         reserved_at_f9[0x2];
1429         u8         fast_teardown[0x1];
1430         u8         log_max_eq[0x4];
1431
1432         u8         max_indirection[0x8];
1433         u8         fixed_buffer_size[0x1];
1434         u8         log_max_mrw_sz[0x7];
1435         u8         force_teardown[0x1];
1436         u8         reserved_at_111[0x1];
1437         u8         log_max_bsf_list_size[0x6];
1438         u8         umr_extended_translation_offset[0x1];
1439         u8         null_mkey[0x1];
1440         u8         log_max_klm_list_size[0x6];
1441
1442         u8         reserved_at_120[0xa];
1443         u8         log_max_ra_req_dc[0x6];
1444         u8         reserved_at_130[0xa];
1445         u8         log_max_ra_res_dc[0x6];
1446
1447         u8         reserved_at_140[0x5];
1448         u8         release_all_pages[0x1];
1449         u8         must_not_use[0x1];
1450         u8         reserved_at_147[0x2];
1451         u8         roce_accl[0x1];
1452         u8         log_max_ra_req_qp[0x6];
1453         u8         reserved_at_150[0xa];
1454         u8         log_max_ra_res_qp[0x6];
1455
1456         u8         end_pad[0x1];
1457         u8         cc_query_allowed[0x1];
1458         u8         cc_modify_allowed[0x1];
1459         u8         start_pad[0x1];
1460         u8         cache_line_128byte[0x1];
1461         u8         reserved_at_165[0x4];
1462         u8         rts2rts_qp_counters_set_id[0x1];
1463         u8         reserved_at_16a[0x2];
1464         u8         vnic_env_int_rq_oob[0x1];
1465         u8         sbcam_reg[0x1];
1466         u8         reserved_at_16e[0x1];
1467         u8         qcam_reg[0x1];
1468         u8         gid_table_size[0x10];
1469
1470         u8         out_of_seq_cnt[0x1];
1471         u8         vport_counters[0x1];
1472         u8         retransmission_q_counters[0x1];
1473         u8         debug[0x1];
1474         u8         modify_rq_counter_set_id[0x1];
1475         u8         rq_delay_drop[0x1];
1476         u8         max_qp_cnt[0xa];
1477         u8         pkey_table_size[0x10];
1478
1479         u8         vport_group_manager[0x1];
1480         u8         vhca_group_manager[0x1];
1481         u8         ib_virt[0x1];
1482         u8         eth_virt[0x1];
1483         u8         vnic_env_queue_counters[0x1];
1484         u8         ets[0x1];
1485         u8         nic_flow_table[0x1];
1486         u8         eswitch_manager[0x1];
1487         u8         device_memory[0x1];
1488         u8         mcam_reg[0x1];
1489         u8         pcam_reg[0x1];
1490         u8         local_ca_ack_delay[0x5];
1491         u8         port_module_event[0x1];
1492         u8         enhanced_error_q_counters[0x1];
1493         u8         ports_check[0x1];
1494         u8         reserved_at_1b3[0x1];
1495         u8         disable_link_up[0x1];
1496         u8         beacon_led[0x1];
1497         u8         port_type[0x2];
1498         u8         num_ports[0x8];
1499
1500         u8         reserved_at_1c0[0x1];
1501         u8         pps[0x1];
1502         u8         pps_modify[0x1];
1503         u8         log_max_msg[0x5];
1504         u8         reserved_at_1c8[0x4];
1505         u8         max_tc[0x4];
1506         u8         temp_warn_event[0x1];
1507         u8         dcbx[0x1];
1508         u8         general_notification_event[0x1];
1509         u8         reserved_at_1d3[0x2];
1510         u8         fpga[0x1];
1511         u8         rol_s[0x1];
1512         u8         rol_g[0x1];
1513         u8         reserved_at_1d8[0x1];
1514         u8         wol_s[0x1];
1515         u8         wol_g[0x1];
1516         u8         wol_a[0x1];
1517         u8         wol_b[0x1];
1518         u8         wol_m[0x1];
1519         u8         wol_u[0x1];
1520         u8         wol_p[0x1];
1521
1522         u8         stat_rate_support[0x10];
1523         u8         reserved_at_1f0[0x1];
1524         u8         pci_sync_for_fw_update_event[0x1];
1525         u8         reserved_at_1f2[0x6];
1526         u8         init2_lag_tx_port_affinity[0x1];
1527         u8         reserved_at_1fa[0x3];
1528         u8         cqe_version[0x4];
1529
1530         u8         compact_address_vector[0x1];
1531         u8         striding_rq[0x1];
1532         u8         reserved_at_202[0x1];
1533         u8         ipoib_enhanced_offloads[0x1];
1534         u8         ipoib_basic_offloads[0x1];
1535         u8         reserved_at_205[0x1];
1536         u8         repeated_block_disabled[0x1];
1537         u8         umr_modify_entity_size_disabled[0x1];
1538         u8         umr_modify_atomic_disabled[0x1];
1539         u8         umr_indirect_mkey_disabled[0x1];
1540         u8         umr_fence[0x2];
1541         u8         dc_req_scat_data_cqe[0x1];
1542         u8         reserved_at_20d[0x2];
1543         u8         drain_sigerr[0x1];
1544         u8         cmdif_checksum[0x2];
1545         u8         sigerr_cqe[0x1];
1546         u8         reserved_at_213[0x1];
1547         u8         wq_signature[0x1];
1548         u8         sctr_data_cqe[0x1];
1549         u8         reserved_at_216[0x1];
1550         u8         sho[0x1];
1551         u8         tph[0x1];
1552         u8         rf[0x1];
1553         u8         dct[0x1];
1554         u8         qos[0x1];
1555         u8         eth_net_offloads[0x1];
1556         u8         roce[0x1];
1557         u8         atomic[0x1];
1558         u8         reserved_at_21f[0x1];
1559
1560         u8         cq_oi[0x1];
1561         u8         cq_resize[0x1];
1562         u8         cq_moderation[0x1];
1563         u8         reserved_at_223[0x3];
1564         u8         cq_eq_remap[0x1];
1565         u8         pg[0x1];
1566         u8         block_lb_mc[0x1];
1567         u8         reserved_at_229[0x1];
1568         u8         scqe_break_moderation[0x1];
1569         u8         cq_period_start_from_cqe[0x1];
1570         u8         cd[0x1];
1571         u8         reserved_at_22d[0x1];
1572         u8         apm[0x1];
1573         u8         vector_calc[0x1];
1574         u8         umr_ptr_rlky[0x1];
1575         u8         imaicl[0x1];
1576         u8         qp_packet_based[0x1];
1577         u8         reserved_at_233[0x3];
1578         u8         qkv[0x1];
1579         u8         pkv[0x1];
1580         u8         set_deth_sqpn[0x1];
1581         u8         reserved_at_239[0x3];
1582         u8         xrc[0x1];
1583         u8         ud[0x1];
1584         u8         uc[0x1];
1585         u8         rc[0x1];
1586
1587         u8         uar_4k[0x1];
1588         u8         reserved_at_241[0x9];
1589         u8         uar_sz[0x6];
1590         u8         port_selection_cap[0x1];
1591         u8         reserved_at_248[0x1];
1592         u8         umem_uid_0[0x1];
1593         u8         reserved_at_250[0x5];
1594         u8         log_pg_sz[0x8];
1595
1596         u8         bf[0x1];
1597         u8         driver_version[0x1];
1598         u8         pad_tx_eth_packet[0x1];
1599         u8         reserved_at_263[0x3];
1600         u8         mkey_by_name[0x1];
1601         u8         reserved_at_267[0x4];
1602
1603         u8         log_bf_reg_size[0x5];
1604
1605         u8         reserved_at_270[0x6];
1606         u8         lag_dct[0x2];
1607         u8         lag_tx_port_affinity[0x1];
1608         u8         lag_native_fdb_selection[0x1];
1609         u8         reserved_at_27a[0x1];
1610         u8         lag_master[0x1];
1611         u8         num_lag_ports[0x4];
1612
1613         u8         reserved_at_280[0x10];
1614         u8         max_wqe_sz_sq[0x10];
1615
1616         u8         reserved_at_2a0[0x10];
1617         u8         max_wqe_sz_rq[0x10];
1618
1619         u8         max_flow_counter_31_16[0x10];
1620         u8         max_wqe_sz_sq_dc[0x10];
1621
1622         u8         reserved_at_2e0[0x7];
1623         u8         max_qp_mcg[0x19];
1624
1625         u8         reserved_at_300[0x10];
1626         u8         flow_counter_bulk_alloc[0x8];
1627         u8         log_max_mcg[0x8];
1628
1629         u8         reserved_at_320[0x3];
1630         u8         log_max_transport_domain[0x5];
1631         u8         reserved_at_328[0x3];
1632         u8         log_max_pd[0x5];
1633         u8         reserved_at_330[0xb];
1634         u8         log_max_xrcd[0x5];
1635
1636         u8         nic_receive_steering_discard[0x1];
1637         u8         receive_discard_vport_down[0x1];
1638         u8         transmit_discard_vport_down[0x1];
1639         u8         reserved_at_343[0x5];
1640         u8         log_max_flow_counter_bulk[0x8];
1641         u8         max_flow_counter_15_0[0x10];
1642
1643
1644         u8         reserved_at_360[0x3];
1645         u8         log_max_rq[0x5];
1646         u8         reserved_at_368[0x3];
1647         u8         log_max_sq[0x5];
1648         u8         reserved_at_370[0x3];
1649         u8         log_max_tir[0x5];
1650         u8         reserved_at_378[0x3];
1651         u8         log_max_tis[0x5];
1652
1653         u8         basic_cyclic_rcv_wqe[0x1];
1654         u8         reserved_at_381[0x2];
1655         u8         log_max_rmp[0x5];
1656         u8         reserved_at_388[0x3];
1657         u8         log_max_rqt[0x5];
1658         u8         reserved_at_390[0x3];
1659         u8         log_max_rqt_size[0x5];
1660         u8         reserved_at_398[0x3];
1661         u8         log_max_tis_per_sq[0x5];
1662
1663         u8         ext_stride_num_range[0x1];
1664         u8         roce_rw_supported[0x1];
1665         u8         log_max_current_uc_list_wr_supported[0x1];
1666         u8         log_max_stride_sz_rq[0x5];
1667         u8         reserved_at_3a8[0x3];
1668         u8         log_min_stride_sz_rq[0x5];
1669         u8         reserved_at_3b0[0x3];
1670         u8         log_max_stride_sz_sq[0x5];
1671         u8         reserved_at_3b8[0x3];
1672         u8         log_min_stride_sz_sq[0x5];
1673
1674         u8         hairpin[0x1];
1675         u8         reserved_at_3c1[0x2];
1676         u8         log_max_hairpin_queues[0x5];
1677         u8         reserved_at_3c8[0x3];
1678         u8         log_max_hairpin_wq_data_sz[0x5];
1679         u8         reserved_at_3d0[0x3];
1680         u8         log_max_hairpin_num_packets[0x5];
1681         u8         reserved_at_3d8[0x3];
1682         u8         log_max_wq_sz[0x5];
1683
1684         u8         nic_vport_change_event[0x1];
1685         u8         disable_local_lb_uc[0x1];
1686         u8         disable_local_lb_mc[0x1];
1687         u8         log_min_hairpin_wq_data_sz[0x5];
1688         u8         reserved_at_3e8[0x2];
1689         u8         vhca_state[0x1];
1690         u8         log_max_vlan_list[0x5];
1691         u8         reserved_at_3f0[0x3];
1692         u8         log_max_current_mc_list[0x5];
1693         u8         reserved_at_3f8[0x3];
1694         u8         log_max_current_uc_list[0x5];
1695
1696         u8         general_obj_types[0x40];
1697
1698         u8         sq_ts_format[0x2];
1699         u8         rq_ts_format[0x2];
1700         u8         steering_format_version[0x4];
1701         u8         create_qp_start_hint[0x18];
1702
1703         u8         reserved_at_460[0x3];
1704         u8         log_max_uctx[0x5];
1705         u8         reserved_at_468[0x2];
1706         u8         ipsec_offload[0x1];
1707         u8         log_max_umem[0x5];
1708         u8         max_num_eqs[0x10];
1709
1710         u8         reserved_at_480[0x1];
1711         u8         tls_tx[0x1];
1712         u8         tls_rx[0x1];
1713         u8         log_max_l2_table[0x5];
1714         u8         reserved_at_488[0x8];
1715         u8         log_uar_page_sz[0x10];
1716
1717         u8         reserved_at_4a0[0x20];
1718         u8         device_frequency_mhz[0x20];
1719         u8         device_frequency_khz[0x20];
1720
1721         u8         reserved_at_500[0x20];
1722         u8         num_of_uars_per_page[0x20];
1723
1724         u8         flex_parser_protocols[0x20];
1725
1726         u8         max_geneve_tlv_options[0x8];
1727         u8         reserved_at_568[0x3];
1728         u8         max_geneve_tlv_option_data_len[0x5];
1729         u8         reserved_at_570[0x10];
1730
1731         u8         reserved_at_580[0xb];
1732         u8         log_max_dci_stream_channels[0x5];
1733         u8         reserved_at_590[0x3];
1734         u8         log_max_dci_errored_streams[0x5];
1735         u8         reserved_at_598[0x8];
1736
1737         u8         reserved_at_5a0[0x13];
1738         u8         log_max_dek[0x5];
1739         u8         reserved_at_5b8[0x4];
1740         u8         mini_cqe_resp_stride_index[0x1];
1741         u8         cqe_128_always[0x1];
1742         u8         cqe_compression_128[0x1];
1743         u8         cqe_compression[0x1];
1744
1745         u8         cqe_compression_timeout[0x10];
1746         u8         cqe_compression_max_num[0x10];
1747
1748         u8         reserved_at_5e0[0x8];
1749         u8         flex_parser_id_gtpu_dw_0[0x4];
1750         u8         reserved_at_5ec[0x4];
1751         u8         tag_matching[0x1];
1752         u8         rndv_offload_rc[0x1];
1753         u8         rndv_offload_dc[0x1];
1754         u8         log_tag_matching_list_sz[0x5];
1755         u8         reserved_at_5f8[0x3];
1756         u8         log_max_xrq[0x5];
1757
1758         u8         affiliate_nic_vport_criteria[0x8];
1759         u8         native_port_num[0x8];
1760         u8         num_vhca_ports[0x8];
1761         u8         flex_parser_id_gtpu_teid[0x4];
1762         u8         reserved_at_61c[0x2];
1763         u8         sw_owner_id[0x1];
1764         u8         reserved_at_61f[0x1];
1765
1766         u8         max_num_of_monitor_counters[0x10];
1767         u8         num_ppcnt_monitor_counters[0x10];
1768
1769         u8         max_num_sf[0x10];
1770         u8         num_q_monitor_counters[0x10];
1771
1772         u8         reserved_at_660[0x20];
1773
1774         u8         sf[0x1];
1775         u8         sf_set_partition[0x1];
1776         u8         reserved_at_682[0x1];
1777         u8         log_max_sf[0x5];
1778         u8         apu[0x1];
1779         u8         reserved_at_689[0x4];
1780         u8         migration[0x1];
1781         u8         reserved_at_68e[0x2];
1782         u8         log_min_sf_size[0x8];
1783         u8         max_num_sf_partitions[0x8];
1784
1785         u8         uctx_cap[0x20];
1786
1787         u8         reserved_at_6c0[0x4];
1788         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1789         u8         flex_parser_id_icmp_dw1[0x4];
1790         u8         flex_parser_id_icmp_dw0[0x4];
1791         u8         flex_parser_id_icmpv6_dw1[0x4];
1792         u8         flex_parser_id_icmpv6_dw0[0x4];
1793         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1794         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1795
1796         u8         max_num_match_definer[0x10];
1797         u8         sf_base_id[0x10];
1798
1799         u8         flex_parser_id_gtpu_dw_2[0x4];
1800         u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1801         u8         num_total_dynamic_vf_msix[0x18];
1802         u8         reserved_at_720[0x14];
1803         u8         dynamic_msix_table_size[0xc];
1804         u8         reserved_at_740[0xc];
1805         u8         min_dynamic_vf_msix_table_size[0x4];
1806         u8         reserved_at_750[0x4];
1807         u8         max_dynamic_vf_msix_table_size[0xc];
1808
1809         u8         reserved_at_760[0x20];
1810         u8         vhca_tunnel_commands[0x40];
1811         u8         match_definer_format_supported[0x40];
1812 };
1813
1814 struct mlx5_ifc_cmd_hca_cap_2_bits {
1815         u8         reserved_at_0[0xa0];
1816
1817         u8         max_reformat_insert_size[0x8];
1818         u8         max_reformat_insert_offset[0x8];
1819         u8         max_reformat_remove_size[0x8];
1820         u8         max_reformat_remove_offset[0x8];
1821
1822         u8         reserved_at_c0[0x740];
1823 };
1824
1825 enum mlx5_ifc_flow_destination_type {
1826         MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1827         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1828         MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1829         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1830         MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
1831 };
1832
1833 enum mlx5_flow_table_miss_action {
1834         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1835         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1836         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1837 };
1838
1839 struct mlx5_ifc_dest_format_struct_bits {
1840         u8         destination_type[0x8];
1841         u8         destination_id[0x18];
1842
1843         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1844         u8         packet_reformat[0x1];
1845         u8         reserved_at_22[0xe];
1846         u8         destination_eswitch_owner_vhca_id[0x10];
1847 };
1848
1849 struct mlx5_ifc_flow_counter_list_bits {
1850         u8         flow_counter_id[0x20];
1851
1852         u8         reserved_at_20[0x20];
1853 };
1854
1855 struct mlx5_ifc_extended_dest_format_bits {
1856         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1857
1858         u8         packet_reformat_id[0x20];
1859
1860         u8         reserved_at_60[0x20];
1861 };
1862
1863 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1864         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1865         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1866 };
1867
1868 struct mlx5_ifc_fte_match_param_bits {
1869         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1870
1871         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1872
1873         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1874
1875         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1876
1877         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1878
1879         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1880
1881         struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1882
1883         u8         reserved_at_e00[0x200];
1884 };
1885
1886 enum {
1887         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1888         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1889         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1890         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1891         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1892 };
1893
1894 struct mlx5_ifc_rx_hash_field_select_bits {
1895         u8         l3_prot_type[0x1];
1896         u8         l4_prot_type[0x1];
1897         u8         selected_fields[0x1e];
1898 };
1899
1900 enum {
1901         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1902         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1903 };
1904
1905 enum {
1906         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1907         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1908 };
1909
1910 struct mlx5_ifc_wq_bits {
1911         u8         wq_type[0x4];
1912         u8         wq_signature[0x1];
1913         u8         end_padding_mode[0x2];
1914         u8         cd_slave[0x1];
1915         u8         reserved_at_8[0x18];
1916
1917         u8         hds_skip_first_sge[0x1];
1918         u8         log2_hds_buf_size[0x3];
1919         u8         reserved_at_24[0x7];
1920         u8         page_offset[0x5];
1921         u8         lwm[0x10];
1922
1923         u8         reserved_at_40[0x8];
1924         u8         pd[0x18];
1925
1926         u8         reserved_at_60[0x8];
1927         u8         uar_page[0x18];
1928
1929         u8         dbr_addr[0x40];
1930
1931         u8         hw_counter[0x20];
1932
1933         u8         sw_counter[0x20];
1934
1935         u8         reserved_at_100[0xc];
1936         u8         log_wq_stride[0x4];
1937         u8         reserved_at_110[0x3];
1938         u8         log_wq_pg_sz[0x5];
1939         u8         reserved_at_118[0x3];
1940         u8         log_wq_sz[0x5];
1941
1942         u8         dbr_umem_valid[0x1];
1943         u8         wq_umem_valid[0x1];
1944         u8         reserved_at_122[0x1];
1945         u8         log_hairpin_num_packets[0x5];
1946         u8         reserved_at_128[0x3];
1947         u8         log_hairpin_data_sz[0x5];
1948
1949         u8         reserved_at_130[0x4];
1950         u8         log_wqe_num_of_strides[0x4];
1951         u8         two_byte_shift_en[0x1];
1952         u8         reserved_at_139[0x4];
1953         u8         log_wqe_stride_size[0x3];
1954
1955         u8         reserved_at_140[0x80];
1956
1957         u8         headers_mkey[0x20];
1958
1959         u8         shampo_enable[0x1];
1960         u8         reserved_at_1e1[0x4];
1961         u8         log_reservation_size[0x3];
1962         u8         reserved_at_1e8[0x5];
1963         u8         log_max_num_of_packets_per_reservation[0x3];
1964         u8         reserved_at_1f0[0x6];
1965         u8         log_headers_entry_size[0x2];
1966         u8         reserved_at_1f8[0x4];
1967         u8         log_headers_buffer_entry_num[0x4];
1968
1969         u8         reserved_at_200[0x400];
1970
1971         struct mlx5_ifc_cmd_pas_bits pas[];
1972 };
1973
1974 struct mlx5_ifc_rq_num_bits {
1975         u8         reserved_at_0[0x8];
1976         u8         rq_num[0x18];
1977 };
1978
1979 struct mlx5_ifc_mac_address_layout_bits {
1980         u8         reserved_at_0[0x10];
1981         u8         mac_addr_47_32[0x10];
1982
1983         u8         mac_addr_31_0[0x20];
1984 };
1985
1986 struct mlx5_ifc_vlan_layout_bits {
1987         u8         reserved_at_0[0x14];
1988         u8         vlan[0x0c];
1989
1990         u8         reserved_at_20[0x20];
1991 };
1992
1993 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1994         u8         reserved_at_0[0xa0];
1995
1996         u8         min_time_between_cnps[0x20];
1997
1998         u8         reserved_at_c0[0x12];
1999         u8         cnp_dscp[0x6];
2000         u8         reserved_at_d8[0x4];
2001         u8         cnp_prio_mode[0x1];
2002         u8         cnp_802p_prio[0x3];
2003
2004         u8         reserved_at_e0[0x720];
2005 };
2006
2007 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2008         u8         reserved_at_0[0x60];
2009
2010         u8         reserved_at_60[0x4];
2011         u8         clamp_tgt_rate[0x1];
2012         u8         reserved_at_65[0x3];
2013         u8         clamp_tgt_rate_after_time_inc[0x1];
2014         u8         reserved_at_69[0x17];
2015
2016         u8         reserved_at_80[0x20];
2017
2018         u8         rpg_time_reset[0x20];
2019
2020         u8         rpg_byte_reset[0x20];
2021
2022         u8         rpg_threshold[0x20];
2023
2024         u8         rpg_max_rate[0x20];
2025
2026         u8         rpg_ai_rate[0x20];
2027
2028         u8         rpg_hai_rate[0x20];
2029
2030         u8         rpg_gd[0x20];
2031
2032         u8         rpg_min_dec_fac[0x20];
2033
2034         u8         rpg_min_rate[0x20];
2035
2036         u8         reserved_at_1c0[0xe0];
2037
2038         u8         rate_to_set_on_first_cnp[0x20];
2039
2040         u8         dce_tcp_g[0x20];
2041
2042         u8         dce_tcp_rtt[0x20];
2043
2044         u8         rate_reduce_monitor_period[0x20];
2045
2046         u8         reserved_at_320[0x20];
2047
2048         u8         initial_alpha_value[0x20];
2049
2050         u8         reserved_at_360[0x4a0];
2051 };
2052
2053 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2054         u8         reserved_at_0[0x80];
2055
2056         u8         rppp_max_rps[0x20];
2057
2058         u8         rpg_time_reset[0x20];
2059
2060         u8         rpg_byte_reset[0x20];
2061
2062         u8         rpg_threshold[0x20];
2063
2064         u8         rpg_max_rate[0x20];
2065
2066         u8         rpg_ai_rate[0x20];
2067
2068         u8         rpg_hai_rate[0x20];
2069
2070         u8         rpg_gd[0x20];
2071
2072         u8         rpg_min_dec_fac[0x20];
2073
2074         u8         rpg_min_rate[0x20];
2075
2076         u8         reserved_at_1c0[0x640];
2077 };
2078
2079 enum {
2080         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2081         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2082         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2083 };
2084
2085 struct mlx5_ifc_resize_field_select_bits {
2086         u8         resize_field_select[0x20];
2087 };
2088
2089 struct mlx5_ifc_resource_dump_bits {
2090         u8         more_dump[0x1];
2091         u8         inline_dump[0x1];
2092         u8         reserved_at_2[0xa];
2093         u8         seq_num[0x4];
2094         u8         segment_type[0x10];
2095
2096         u8         reserved_at_20[0x10];
2097         u8         vhca_id[0x10];
2098
2099         u8         index1[0x20];
2100
2101         u8         index2[0x20];
2102
2103         u8         num_of_obj1[0x10];
2104         u8         num_of_obj2[0x10];
2105
2106         u8         reserved_at_a0[0x20];
2107
2108         u8         device_opaque[0x40];
2109
2110         u8         mkey[0x20];
2111
2112         u8         size[0x20];
2113
2114         u8         address[0x40];
2115
2116         u8         inline_data[52][0x20];
2117 };
2118
2119 struct mlx5_ifc_resource_dump_menu_record_bits {
2120         u8         reserved_at_0[0x4];
2121         u8         num_of_obj2_supports_active[0x1];
2122         u8         num_of_obj2_supports_all[0x1];
2123         u8         must_have_num_of_obj2[0x1];
2124         u8         support_num_of_obj2[0x1];
2125         u8         num_of_obj1_supports_active[0x1];
2126         u8         num_of_obj1_supports_all[0x1];
2127         u8         must_have_num_of_obj1[0x1];
2128         u8         support_num_of_obj1[0x1];
2129         u8         must_have_index2[0x1];
2130         u8         support_index2[0x1];
2131         u8         must_have_index1[0x1];
2132         u8         support_index1[0x1];
2133         u8         segment_type[0x10];
2134
2135         u8         segment_name[4][0x20];
2136
2137         u8         index1_name[4][0x20];
2138
2139         u8         index2_name[4][0x20];
2140 };
2141
2142 struct mlx5_ifc_resource_dump_segment_header_bits {
2143         u8         length_dw[0x10];
2144         u8         segment_type[0x10];
2145 };
2146
2147 struct mlx5_ifc_resource_dump_command_segment_bits {
2148         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2149
2150         u8         segment_called[0x10];
2151         u8         vhca_id[0x10];
2152
2153         u8         index1[0x20];
2154
2155         u8         index2[0x20];
2156
2157         u8         num_of_obj1[0x10];
2158         u8         num_of_obj2[0x10];
2159 };
2160
2161 struct mlx5_ifc_resource_dump_error_segment_bits {
2162         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2163
2164         u8         reserved_at_20[0x10];
2165         u8         syndrome_id[0x10];
2166
2167         u8         reserved_at_40[0x40];
2168
2169         u8         error[8][0x20];
2170 };
2171
2172 struct mlx5_ifc_resource_dump_info_segment_bits {
2173         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2174
2175         u8         reserved_at_20[0x18];
2176         u8         dump_version[0x8];
2177
2178         u8         hw_version[0x20];
2179
2180         u8         fw_version[0x20];
2181 };
2182
2183 struct mlx5_ifc_resource_dump_menu_segment_bits {
2184         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2185
2186         u8         reserved_at_20[0x10];
2187         u8         num_of_records[0x10];
2188
2189         struct mlx5_ifc_resource_dump_menu_record_bits record[];
2190 };
2191
2192 struct mlx5_ifc_resource_dump_resource_segment_bits {
2193         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2194
2195         u8         reserved_at_20[0x20];
2196
2197         u8         index1[0x20];
2198
2199         u8         index2[0x20];
2200
2201         u8         payload[][0x20];
2202 };
2203
2204 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2205         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2206 };
2207
2208 struct mlx5_ifc_menu_resource_dump_response_bits {
2209         struct mlx5_ifc_resource_dump_info_segment_bits info;
2210         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2211         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2212         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2213 };
2214
2215 enum {
2216         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2217         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2218         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2219         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2220 };
2221
2222 struct mlx5_ifc_modify_field_select_bits {
2223         u8         modify_field_select[0x20];
2224 };
2225
2226 struct mlx5_ifc_field_select_r_roce_np_bits {
2227         u8         field_select_r_roce_np[0x20];
2228 };
2229
2230 struct mlx5_ifc_field_select_r_roce_rp_bits {
2231         u8         field_select_r_roce_rp[0x20];
2232 };
2233
2234 enum {
2235         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2236         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2237         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2238         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2239         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2240         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2241         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2242         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2243         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2244         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2245 };
2246
2247 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2248         u8         field_select_8021qaurp[0x20];
2249 };
2250
2251 struct mlx5_ifc_phys_layer_cntrs_bits {
2252         u8         time_since_last_clear_high[0x20];
2253
2254         u8         time_since_last_clear_low[0x20];
2255
2256         u8         symbol_errors_high[0x20];
2257
2258         u8         symbol_errors_low[0x20];
2259
2260         u8         sync_headers_errors_high[0x20];
2261
2262         u8         sync_headers_errors_low[0x20];
2263
2264         u8         edpl_bip_errors_lane0_high[0x20];
2265
2266         u8         edpl_bip_errors_lane0_low[0x20];
2267
2268         u8         edpl_bip_errors_lane1_high[0x20];
2269
2270         u8         edpl_bip_errors_lane1_low[0x20];
2271
2272         u8         edpl_bip_errors_lane2_high[0x20];
2273
2274         u8         edpl_bip_errors_lane2_low[0x20];
2275
2276         u8         edpl_bip_errors_lane3_high[0x20];
2277
2278         u8         edpl_bip_errors_lane3_low[0x20];
2279
2280         u8         fc_fec_corrected_blocks_lane0_high[0x20];
2281
2282         u8         fc_fec_corrected_blocks_lane0_low[0x20];
2283
2284         u8         fc_fec_corrected_blocks_lane1_high[0x20];
2285
2286         u8         fc_fec_corrected_blocks_lane1_low[0x20];
2287
2288         u8         fc_fec_corrected_blocks_lane2_high[0x20];
2289
2290         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2291
2292         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2293
2294         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2295
2296         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2297
2298         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2299
2300         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2301
2302         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2303
2304         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2305
2306         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2307
2308         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2309
2310         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2311
2312         u8         rs_fec_corrected_blocks_high[0x20];
2313
2314         u8         rs_fec_corrected_blocks_low[0x20];
2315
2316         u8         rs_fec_uncorrectable_blocks_high[0x20];
2317
2318         u8         rs_fec_uncorrectable_blocks_low[0x20];
2319
2320         u8         rs_fec_no_errors_blocks_high[0x20];
2321
2322         u8         rs_fec_no_errors_blocks_low[0x20];
2323
2324         u8         rs_fec_single_error_blocks_high[0x20];
2325
2326         u8         rs_fec_single_error_blocks_low[0x20];
2327
2328         u8         rs_fec_corrected_symbols_total_high[0x20];
2329
2330         u8         rs_fec_corrected_symbols_total_low[0x20];
2331
2332         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2333
2334         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2335
2336         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2337
2338         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2339
2340         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2341
2342         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2343
2344         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2345
2346         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2347
2348         u8         link_down_events[0x20];
2349
2350         u8         successful_recovery_events[0x20];
2351
2352         u8         reserved_at_640[0x180];
2353 };
2354
2355 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2356         u8         time_since_last_clear_high[0x20];
2357
2358         u8         time_since_last_clear_low[0x20];
2359
2360         u8         phy_received_bits_high[0x20];
2361
2362         u8         phy_received_bits_low[0x20];
2363
2364         u8         phy_symbol_errors_high[0x20];
2365
2366         u8         phy_symbol_errors_low[0x20];
2367
2368         u8         phy_corrected_bits_high[0x20];
2369
2370         u8         phy_corrected_bits_low[0x20];
2371
2372         u8         phy_corrected_bits_lane0_high[0x20];
2373
2374         u8         phy_corrected_bits_lane0_low[0x20];
2375
2376         u8         phy_corrected_bits_lane1_high[0x20];
2377
2378         u8         phy_corrected_bits_lane1_low[0x20];
2379
2380         u8         phy_corrected_bits_lane2_high[0x20];
2381
2382         u8         phy_corrected_bits_lane2_low[0x20];
2383
2384         u8         phy_corrected_bits_lane3_high[0x20];
2385
2386         u8         phy_corrected_bits_lane3_low[0x20];
2387
2388         u8         reserved_at_200[0x5c0];
2389 };
2390
2391 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2392         u8         symbol_error_counter[0x10];
2393
2394         u8         link_error_recovery_counter[0x8];
2395
2396         u8         link_downed_counter[0x8];
2397
2398         u8         port_rcv_errors[0x10];
2399
2400         u8         port_rcv_remote_physical_errors[0x10];
2401
2402         u8         port_rcv_switch_relay_errors[0x10];
2403
2404         u8         port_xmit_discards[0x10];
2405
2406         u8         port_xmit_constraint_errors[0x8];
2407
2408         u8         port_rcv_constraint_errors[0x8];
2409
2410         u8         reserved_at_70[0x8];
2411
2412         u8         link_overrun_errors[0x8];
2413
2414         u8         reserved_at_80[0x10];
2415
2416         u8         vl_15_dropped[0x10];
2417
2418         u8         reserved_at_a0[0x80];
2419
2420         u8         port_xmit_wait[0x20];
2421 };
2422
2423 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2424         u8         transmit_queue_high[0x20];
2425
2426         u8         transmit_queue_low[0x20];
2427
2428         u8         no_buffer_discard_uc_high[0x20];
2429
2430         u8         no_buffer_discard_uc_low[0x20];
2431
2432         u8         reserved_at_80[0x740];
2433 };
2434
2435 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2436         u8         wred_discard_high[0x20];
2437
2438         u8         wred_discard_low[0x20];
2439
2440         u8         ecn_marked_tc_high[0x20];
2441
2442         u8         ecn_marked_tc_low[0x20];
2443
2444         u8         reserved_at_80[0x740];
2445 };
2446
2447 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2448         u8         rx_octets_high[0x20];
2449
2450         u8         rx_octets_low[0x20];
2451
2452         u8         reserved_at_40[0xc0];
2453
2454         u8         rx_frames_high[0x20];
2455
2456         u8         rx_frames_low[0x20];
2457
2458         u8         tx_octets_high[0x20];
2459
2460         u8         tx_octets_low[0x20];
2461
2462         u8         reserved_at_180[0xc0];
2463
2464         u8         tx_frames_high[0x20];
2465
2466         u8         tx_frames_low[0x20];
2467
2468         u8         rx_pause_high[0x20];
2469
2470         u8         rx_pause_low[0x20];
2471
2472         u8         rx_pause_duration_high[0x20];
2473
2474         u8         rx_pause_duration_low[0x20];
2475
2476         u8         tx_pause_high[0x20];
2477
2478         u8         tx_pause_low[0x20];
2479
2480         u8         tx_pause_duration_high[0x20];
2481
2482         u8         tx_pause_duration_low[0x20];
2483
2484         u8         rx_pause_transition_high[0x20];
2485
2486         u8         rx_pause_transition_low[0x20];
2487
2488         u8         rx_discards_high[0x20];
2489
2490         u8         rx_discards_low[0x20];
2491
2492         u8         device_stall_minor_watermark_cnt_high[0x20];
2493
2494         u8         device_stall_minor_watermark_cnt_low[0x20];
2495
2496         u8         device_stall_critical_watermark_cnt_high[0x20];
2497
2498         u8         device_stall_critical_watermark_cnt_low[0x20];
2499
2500         u8         reserved_at_480[0x340];
2501 };
2502
2503 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2504         u8         port_transmit_wait_high[0x20];
2505
2506         u8         port_transmit_wait_low[0x20];
2507
2508         u8         reserved_at_40[0x100];
2509
2510         u8         rx_buffer_almost_full_high[0x20];
2511
2512         u8         rx_buffer_almost_full_low[0x20];
2513
2514         u8         rx_buffer_full_high[0x20];
2515
2516         u8         rx_buffer_full_low[0x20];
2517
2518         u8         rx_icrc_encapsulated_high[0x20];
2519
2520         u8         rx_icrc_encapsulated_low[0x20];
2521
2522         u8         reserved_at_200[0x5c0];
2523 };
2524
2525 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2526         u8         dot3stats_alignment_errors_high[0x20];
2527
2528         u8         dot3stats_alignment_errors_low[0x20];
2529
2530         u8         dot3stats_fcs_errors_high[0x20];
2531
2532         u8         dot3stats_fcs_errors_low[0x20];
2533
2534         u8         dot3stats_single_collision_frames_high[0x20];
2535
2536         u8         dot3stats_single_collision_frames_low[0x20];
2537
2538         u8         dot3stats_multiple_collision_frames_high[0x20];
2539
2540         u8         dot3stats_multiple_collision_frames_low[0x20];
2541
2542         u8         dot3stats_sqe_test_errors_high[0x20];
2543
2544         u8         dot3stats_sqe_test_errors_low[0x20];
2545
2546         u8         dot3stats_deferred_transmissions_high[0x20];
2547
2548         u8         dot3stats_deferred_transmissions_low[0x20];
2549
2550         u8         dot3stats_late_collisions_high[0x20];
2551
2552         u8         dot3stats_late_collisions_low[0x20];
2553
2554         u8         dot3stats_excessive_collisions_high[0x20];
2555
2556         u8         dot3stats_excessive_collisions_low[0x20];
2557
2558         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2559
2560         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2561
2562         u8         dot3stats_carrier_sense_errors_high[0x20];
2563
2564         u8         dot3stats_carrier_sense_errors_low[0x20];
2565
2566         u8         dot3stats_frame_too_longs_high[0x20];
2567
2568         u8         dot3stats_frame_too_longs_low[0x20];
2569
2570         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2571
2572         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2573
2574         u8         dot3stats_symbol_errors_high[0x20];
2575
2576         u8         dot3stats_symbol_errors_low[0x20];
2577
2578         u8         dot3control_in_unknown_opcodes_high[0x20];
2579
2580         u8         dot3control_in_unknown_opcodes_low[0x20];
2581
2582         u8         dot3in_pause_frames_high[0x20];
2583
2584         u8         dot3in_pause_frames_low[0x20];
2585
2586         u8         dot3out_pause_frames_high[0x20];
2587
2588         u8         dot3out_pause_frames_low[0x20];
2589
2590         u8         reserved_at_400[0x3c0];
2591 };
2592
2593 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2594         u8         ether_stats_drop_events_high[0x20];
2595
2596         u8         ether_stats_drop_events_low[0x20];
2597
2598         u8         ether_stats_octets_high[0x20];
2599
2600         u8         ether_stats_octets_low[0x20];
2601
2602         u8         ether_stats_pkts_high[0x20];
2603
2604         u8         ether_stats_pkts_low[0x20];
2605
2606         u8         ether_stats_broadcast_pkts_high[0x20];
2607
2608         u8         ether_stats_broadcast_pkts_low[0x20];
2609
2610         u8         ether_stats_multicast_pkts_high[0x20];
2611
2612         u8         ether_stats_multicast_pkts_low[0x20];
2613
2614         u8         ether_stats_crc_align_errors_high[0x20];
2615
2616         u8         ether_stats_crc_align_errors_low[0x20];
2617
2618         u8         ether_stats_undersize_pkts_high[0x20];
2619
2620         u8         ether_stats_undersize_pkts_low[0x20];
2621
2622         u8         ether_stats_oversize_pkts_high[0x20];
2623
2624         u8         ether_stats_oversize_pkts_low[0x20];
2625
2626         u8         ether_stats_fragments_high[0x20];
2627
2628         u8         ether_stats_fragments_low[0x20];
2629
2630         u8         ether_stats_jabbers_high[0x20];
2631
2632         u8         ether_stats_jabbers_low[0x20];
2633
2634         u8         ether_stats_collisions_high[0x20];
2635
2636         u8         ether_stats_collisions_low[0x20];
2637
2638         u8         ether_stats_pkts64octets_high[0x20];
2639
2640         u8         ether_stats_pkts64octets_low[0x20];
2641
2642         u8         ether_stats_pkts65to127octets_high[0x20];
2643
2644         u8         ether_stats_pkts65to127octets_low[0x20];
2645
2646         u8         ether_stats_pkts128to255octets_high[0x20];
2647
2648         u8         ether_stats_pkts128to255octets_low[0x20];
2649
2650         u8         ether_stats_pkts256to511octets_high[0x20];
2651
2652         u8         ether_stats_pkts256to511octets_low[0x20];
2653
2654         u8         ether_stats_pkts512to1023octets_high[0x20];
2655
2656         u8         ether_stats_pkts512to1023octets_low[0x20];
2657
2658         u8         ether_stats_pkts1024to1518octets_high[0x20];
2659
2660         u8         ether_stats_pkts1024to1518octets_low[0x20];
2661
2662         u8         ether_stats_pkts1519to2047octets_high[0x20];
2663
2664         u8         ether_stats_pkts1519to2047octets_low[0x20];
2665
2666         u8         ether_stats_pkts2048to4095octets_high[0x20];
2667
2668         u8         ether_stats_pkts2048to4095octets_low[0x20];
2669
2670         u8         ether_stats_pkts4096to8191octets_high[0x20];
2671
2672         u8         ether_stats_pkts4096to8191octets_low[0x20];
2673
2674         u8         ether_stats_pkts8192to10239octets_high[0x20];
2675
2676         u8         ether_stats_pkts8192to10239octets_low[0x20];
2677
2678         u8         reserved_at_540[0x280];
2679 };
2680
2681 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2682         u8         if_in_octets_high[0x20];
2683
2684         u8         if_in_octets_low[0x20];
2685
2686         u8         if_in_ucast_pkts_high[0x20];
2687
2688         u8         if_in_ucast_pkts_low[0x20];
2689
2690         u8         if_in_discards_high[0x20];
2691
2692         u8         if_in_discards_low[0x20];
2693
2694         u8         if_in_errors_high[0x20];
2695
2696         u8         if_in_errors_low[0x20];
2697
2698         u8         if_in_unknown_protos_high[0x20];
2699
2700         u8         if_in_unknown_protos_low[0x20];
2701
2702         u8         if_out_octets_high[0x20];
2703
2704         u8         if_out_octets_low[0x20];
2705
2706         u8         if_out_ucast_pkts_high[0x20];
2707
2708         u8         if_out_ucast_pkts_low[0x20];
2709
2710         u8         if_out_discards_high[0x20];
2711
2712         u8         if_out_discards_low[0x20];
2713
2714         u8         if_out_errors_high[0x20];
2715
2716         u8         if_out_errors_low[0x20];
2717
2718         u8         if_in_multicast_pkts_high[0x20];
2719
2720         u8         if_in_multicast_pkts_low[0x20];
2721
2722         u8         if_in_broadcast_pkts_high[0x20];
2723
2724         u8         if_in_broadcast_pkts_low[0x20];
2725
2726         u8         if_out_multicast_pkts_high[0x20];
2727
2728         u8         if_out_multicast_pkts_low[0x20];
2729
2730         u8         if_out_broadcast_pkts_high[0x20];
2731
2732         u8         if_out_broadcast_pkts_low[0x20];
2733
2734         u8         reserved_at_340[0x480];
2735 };
2736
2737 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2738         u8         a_frames_transmitted_ok_high[0x20];
2739
2740         u8         a_frames_transmitted_ok_low[0x20];
2741
2742         u8         a_frames_received_ok_high[0x20];
2743
2744         u8         a_frames_received_ok_low[0x20];
2745
2746         u8         a_frame_check_sequence_errors_high[0x20];
2747
2748         u8         a_frame_check_sequence_errors_low[0x20];
2749
2750         u8         a_alignment_errors_high[0x20];
2751
2752         u8         a_alignment_errors_low[0x20];
2753
2754         u8         a_octets_transmitted_ok_high[0x20];
2755
2756         u8         a_octets_transmitted_ok_low[0x20];
2757
2758         u8         a_octets_received_ok_high[0x20];
2759
2760         u8         a_octets_received_ok_low[0x20];
2761
2762         u8         a_multicast_frames_xmitted_ok_high[0x20];
2763
2764         u8         a_multicast_frames_xmitted_ok_low[0x20];
2765
2766         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2767
2768         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2769
2770         u8         a_multicast_frames_received_ok_high[0x20];
2771
2772         u8         a_multicast_frames_received_ok_low[0x20];
2773
2774         u8         a_broadcast_frames_received_ok_high[0x20];
2775
2776         u8         a_broadcast_frames_received_ok_low[0x20];
2777
2778         u8         a_in_range_length_errors_high[0x20];
2779
2780         u8         a_in_range_length_errors_low[0x20];
2781
2782         u8         a_out_of_range_length_field_high[0x20];
2783
2784         u8         a_out_of_range_length_field_low[0x20];
2785
2786         u8         a_frame_too_long_errors_high[0x20];
2787
2788         u8         a_frame_too_long_errors_low[0x20];
2789
2790         u8         a_symbol_error_during_carrier_high[0x20];
2791
2792         u8         a_symbol_error_during_carrier_low[0x20];
2793
2794         u8         a_mac_control_frames_transmitted_high[0x20];
2795
2796         u8         a_mac_control_frames_transmitted_low[0x20];
2797
2798         u8         a_mac_control_frames_received_high[0x20];
2799
2800         u8         a_mac_control_frames_received_low[0x20];
2801
2802         u8         a_unsupported_opcodes_received_high[0x20];
2803
2804         u8         a_unsupported_opcodes_received_low[0x20];
2805
2806         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2807
2808         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2809
2810         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2811
2812         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2813
2814         u8         reserved_at_4c0[0x300];
2815 };
2816
2817 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2818         u8         life_time_counter_high[0x20];
2819
2820         u8         life_time_counter_low[0x20];
2821
2822         u8         rx_errors[0x20];
2823
2824         u8         tx_errors[0x20];
2825
2826         u8         l0_to_recovery_eieos[0x20];
2827
2828         u8         l0_to_recovery_ts[0x20];
2829
2830         u8         l0_to_recovery_framing[0x20];
2831
2832         u8         l0_to_recovery_retrain[0x20];
2833
2834         u8         crc_error_dllp[0x20];
2835
2836         u8         crc_error_tlp[0x20];
2837
2838         u8         tx_overflow_buffer_pkt_high[0x20];
2839
2840         u8         tx_overflow_buffer_pkt_low[0x20];
2841
2842         u8         outbound_stalled_reads[0x20];
2843
2844         u8         outbound_stalled_writes[0x20];
2845
2846         u8         outbound_stalled_reads_events[0x20];
2847
2848         u8         outbound_stalled_writes_events[0x20];
2849
2850         u8         reserved_at_200[0x5c0];
2851 };
2852
2853 struct mlx5_ifc_cmd_inter_comp_event_bits {
2854         u8         command_completion_vector[0x20];
2855
2856         u8         reserved_at_20[0xc0];
2857 };
2858
2859 struct mlx5_ifc_stall_vl_event_bits {
2860         u8         reserved_at_0[0x18];
2861         u8         port_num[0x1];
2862         u8         reserved_at_19[0x3];
2863         u8         vl[0x4];
2864
2865         u8         reserved_at_20[0xa0];
2866 };
2867
2868 struct mlx5_ifc_db_bf_congestion_event_bits {
2869         u8         event_subtype[0x8];
2870         u8         reserved_at_8[0x8];
2871         u8         congestion_level[0x8];
2872         u8         reserved_at_18[0x8];
2873
2874         u8         reserved_at_20[0xa0];
2875 };
2876
2877 struct mlx5_ifc_gpio_event_bits {
2878         u8         reserved_at_0[0x60];
2879
2880         u8         gpio_event_hi[0x20];
2881
2882         u8         gpio_event_lo[0x20];
2883
2884         u8         reserved_at_a0[0x40];
2885 };
2886
2887 struct mlx5_ifc_port_state_change_event_bits {
2888         u8         reserved_at_0[0x40];
2889
2890         u8         port_num[0x4];
2891         u8         reserved_at_44[0x1c];
2892
2893         u8         reserved_at_60[0x80];
2894 };
2895
2896 struct mlx5_ifc_dropped_packet_logged_bits {
2897         u8         reserved_at_0[0xe0];
2898 };
2899
2900 struct mlx5_ifc_default_timeout_bits {
2901         u8         to_multiplier[0x3];
2902         u8         reserved_at_3[0x9];
2903         u8         to_value[0x14];
2904 };
2905
2906 struct mlx5_ifc_dtor_reg_bits {
2907         u8         reserved_at_0[0x20];
2908
2909         struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
2910
2911         u8         reserved_at_40[0x60];
2912
2913         struct mlx5_ifc_default_timeout_bits health_poll_to;
2914
2915         struct mlx5_ifc_default_timeout_bits full_crdump_to;
2916
2917         struct mlx5_ifc_default_timeout_bits fw_reset_to;
2918
2919         struct mlx5_ifc_default_timeout_bits flush_on_err_to;
2920
2921         struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
2922
2923         struct mlx5_ifc_default_timeout_bits tear_down_to;
2924
2925         struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
2926
2927         struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
2928
2929         struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
2930
2931         u8         reserved_at_1c0[0x40];
2932 };
2933
2934 enum {
2935         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2936         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2937 };
2938
2939 struct mlx5_ifc_cq_error_bits {
2940         u8         reserved_at_0[0x8];
2941         u8         cqn[0x18];
2942
2943         u8         reserved_at_20[0x20];
2944
2945         u8         reserved_at_40[0x18];
2946         u8         syndrome[0x8];
2947
2948         u8         reserved_at_60[0x80];
2949 };
2950
2951 struct mlx5_ifc_rdma_page_fault_event_bits {
2952         u8         bytes_committed[0x20];
2953
2954         u8         r_key[0x20];
2955
2956         u8         reserved_at_40[0x10];
2957         u8         packet_len[0x10];
2958
2959         u8         rdma_op_len[0x20];
2960
2961         u8         rdma_va[0x40];
2962
2963         u8         reserved_at_c0[0x5];
2964         u8         rdma[0x1];
2965         u8         write[0x1];
2966         u8         requestor[0x1];
2967         u8         qp_number[0x18];
2968 };
2969
2970 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2971         u8         bytes_committed[0x20];
2972
2973         u8         reserved_at_20[0x10];
2974         u8         wqe_index[0x10];
2975
2976         u8         reserved_at_40[0x10];
2977         u8         len[0x10];
2978
2979         u8         reserved_at_60[0x60];
2980
2981         u8         reserved_at_c0[0x5];
2982         u8         rdma[0x1];
2983         u8         write_read[0x1];
2984         u8         requestor[0x1];
2985         u8         qpn[0x18];
2986 };
2987
2988 struct mlx5_ifc_qp_events_bits {
2989         u8         reserved_at_0[0xa0];
2990
2991         u8         type[0x8];
2992         u8         reserved_at_a8[0x18];
2993
2994         u8         reserved_at_c0[0x8];
2995         u8         qpn_rqn_sqn[0x18];
2996 };
2997
2998 struct mlx5_ifc_dct_events_bits {
2999         u8         reserved_at_0[0xc0];
3000
3001         u8         reserved_at_c0[0x8];
3002         u8         dct_number[0x18];
3003 };
3004
3005 struct mlx5_ifc_comp_event_bits {
3006         u8         reserved_at_0[0xc0];
3007
3008         u8         reserved_at_c0[0x8];
3009         u8         cq_number[0x18];
3010 };
3011
3012 enum {
3013         MLX5_QPC_STATE_RST        = 0x0,
3014         MLX5_QPC_STATE_INIT       = 0x1,
3015         MLX5_QPC_STATE_RTR        = 0x2,
3016         MLX5_QPC_STATE_RTS        = 0x3,
3017         MLX5_QPC_STATE_SQER       = 0x4,
3018         MLX5_QPC_STATE_ERR        = 0x6,
3019         MLX5_QPC_STATE_SQD        = 0x7,
3020         MLX5_QPC_STATE_SUSPENDED  = 0x9,
3021 };
3022
3023 enum {
3024         MLX5_QPC_ST_RC            = 0x0,
3025         MLX5_QPC_ST_UC            = 0x1,
3026         MLX5_QPC_ST_UD            = 0x2,
3027         MLX5_QPC_ST_XRC           = 0x3,
3028         MLX5_QPC_ST_DCI           = 0x5,
3029         MLX5_QPC_ST_QP0           = 0x7,
3030         MLX5_QPC_ST_QP1           = 0x8,
3031         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3032         MLX5_QPC_ST_REG_UMR       = 0xc,
3033 };
3034
3035 enum {
3036         MLX5_QPC_PM_STATE_ARMED     = 0x0,
3037         MLX5_QPC_PM_STATE_REARM     = 0x1,
3038         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3039         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3040 };
3041
3042 enum {
3043         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3044 };
3045
3046 enum {
3047         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3048         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3049 };
3050
3051 enum {
3052         MLX5_QPC_MTU_256_BYTES        = 0x1,
3053         MLX5_QPC_MTU_512_BYTES        = 0x2,
3054         MLX5_QPC_MTU_1K_BYTES         = 0x3,
3055         MLX5_QPC_MTU_2K_BYTES         = 0x4,
3056         MLX5_QPC_MTU_4K_BYTES         = 0x5,
3057         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3058 };
3059
3060 enum {
3061         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3062         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3063         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3064         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3065         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3066         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3067         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3068         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3069 };
3070
3071 enum {
3072         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3073         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3074         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3075 };
3076
3077 enum {
3078         MLX5_QPC_CS_RES_DISABLE    = 0x0,
3079         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3080         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3081 };
3082
3083 enum {
3084         MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3085         MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3086         MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3087 };
3088
3089 struct mlx5_ifc_qpc_bits {
3090         u8         state[0x4];
3091         u8         lag_tx_port_affinity[0x4];
3092         u8         st[0x8];
3093         u8         reserved_at_10[0x2];
3094         u8         isolate_vl_tc[0x1];
3095         u8         pm_state[0x2];
3096         u8         reserved_at_15[0x1];
3097         u8         req_e2e_credit_mode[0x2];
3098         u8         offload_type[0x4];
3099         u8         end_padding_mode[0x2];
3100         u8         reserved_at_1e[0x2];
3101
3102         u8         wq_signature[0x1];
3103         u8         block_lb_mc[0x1];
3104         u8         atomic_like_write_en[0x1];
3105         u8         latency_sensitive[0x1];
3106         u8         reserved_at_24[0x1];
3107         u8         drain_sigerr[0x1];
3108         u8         reserved_at_26[0x2];
3109         u8         pd[0x18];
3110
3111         u8         mtu[0x3];
3112         u8         log_msg_max[0x5];
3113         u8         reserved_at_48[0x1];
3114         u8         log_rq_size[0x4];
3115         u8         log_rq_stride[0x3];
3116         u8         no_sq[0x1];
3117         u8         log_sq_size[0x4];
3118         u8         reserved_at_55[0x3];
3119         u8         ts_format[0x2];
3120         u8         reserved_at_5a[0x1];
3121         u8         rlky[0x1];
3122         u8         ulp_stateless_offload_mode[0x4];
3123
3124         u8         counter_set_id[0x8];
3125         u8         uar_page[0x18];
3126
3127         u8         reserved_at_80[0x8];
3128         u8         user_index[0x18];
3129
3130         u8         reserved_at_a0[0x3];
3131         u8         log_page_size[0x5];
3132         u8         remote_qpn[0x18];
3133
3134         struct mlx5_ifc_ads_bits primary_address_path;
3135
3136         struct mlx5_ifc_ads_bits secondary_address_path;
3137
3138         u8         log_ack_req_freq[0x4];
3139         u8         reserved_at_384[0x4];
3140         u8         log_sra_max[0x3];
3141         u8         reserved_at_38b[0x2];
3142         u8         retry_count[0x3];
3143         u8         rnr_retry[0x3];
3144         u8         reserved_at_393[0x1];
3145         u8         fre[0x1];
3146         u8         cur_rnr_retry[0x3];
3147         u8         cur_retry_count[0x3];
3148         u8         reserved_at_39b[0x5];
3149
3150         u8         reserved_at_3a0[0x20];
3151
3152         u8         reserved_at_3c0[0x8];
3153         u8         next_send_psn[0x18];
3154
3155         u8         reserved_at_3e0[0x3];
3156         u8         log_num_dci_stream_channels[0x5];
3157         u8         cqn_snd[0x18];
3158
3159         u8         reserved_at_400[0x3];
3160         u8         log_num_dci_errored_streams[0x5];
3161         u8         deth_sqpn[0x18];
3162
3163         u8         reserved_at_420[0x20];
3164
3165         u8         reserved_at_440[0x8];
3166         u8         last_acked_psn[0x18];
3167
3168         u8         reserved_at_460[0x8];
3169         u8         ssn[0x18];
3170
3171         u8         reserved_at_480[0x8];
3172         u8         log_rra_max[0x3];
3173         u8         reserved_at_48b[0x1];
3174         u8         atomic_mode[0x4];
3175         u8         rre[0x1];
3176         u8         rwe[0x1];
3177         u8         rae[0x1];
3178         u8         reserved_at_493[0x1];
3179         u8         page_offset[0x6];
3180         u8         reserved_at_49a[0x3];
3181         u8         cd_slave_receive[0x1];
3182         u8         cd_slave_send[0x1];
3183         u8         cd_master[0x1];
3184
3185         u8         reserved_at_4a0[0x3];
3186         u8         min_rnr_nak[0x5];
3187         u8         next_rcv_psn[0x18];
3188
3189         u8         reserved_at_4c0[0x8];
3190         u8         xrcd[0x18];
3191
3192         u8         reserved_at_4e0[0x8];
3193         u8         cqn_rcv[0x18];
3194
3195         u8         dbr_addr[0x40];
3196
3197         u8         q_key[0x20];
3198
3199         u8         reserved_at_560[0x5];
3200         u8         rq_type[0x3];
3201         u8         srqn_rmpn_xrqn[0x18];
3202
3203         u8         reserved_at_580[0x8];
3204         u8         rmsn[0x18];
3205
3206         u8         hw_sq_wqebb_counter[0x10];
3207         u8         sw_sq_wqebb_counter[0x10];
3208
3209         u8         hw_rq_counter[0x20];
3210
3211         u8         sw_rq_counter[0x20];
3212
3213         u8         reserved_at_600[0x20];
3214
3215         u8         reserved_at_620[0xf];
3216         u8         cgs[0x1];
3217         u8         cs_req[0x8];
3218         u8         cs_res[0x8];
3219
3220         u8         dc_access_key[0x40];
3221
3222         u8         reserved_at_680[0x3];
3223         u8         dbr_umem_valid[0x1];
3224
3225         u8         reserved_at_684[0xbc];
3226 };
3227
3228 struct mlx5_ifc_roce_addr_layout_bits {
3229         u8         source_l3_address[16][0x8];
3230
3231         u8         reserved_at_80[0x3];
3232         u8         vlan_valid[0x1];
3233         u8         vlan_id[0xc];
3234         u8         source_mac_47_32[0x10];
3235
3236         u8         source_mac_31_0[0x20];
3237
3238         u8         reserved_at_c0[0x14];
3239         u8         roce_l3_type[0x4];
3240         u8         roce_version[0x8];
3241
3242         u8         reserved_at_e0[0x20];
3243 };
3244
3245 struct mlx5_ifc_shampo_cap_bits {
3246         u8    reserved_at_0[0x3];
3247         u8    shampo_log_max_reservation_size[0x5];
3248         u8    reserved_at_8[0x3];
3249         u8    shampo_log_min_reservation_size[0x5];
3250         u8    shampo_min_mss_size[0x10];
3251
3252         u8    reserved_at_20[0x3];
3253         u8    shampo_max_log_headers_entry_size[0x5];
3254         u8    reserved_at_28[0x18];
3255
3256         u8    reserved_at_40[0x7c0];
3257 };
3258
3259 union mlx5_ifc_hca_cap_union_bits {
3260         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3261         struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3262         struct mlx5_ifc_odp_cap_bits odp_cap;
3263         struct mlx5_ifc_atomic_caps_bits atomic_caps;
3264         struct mlx5_ifc_roce_cap_bits roce_cap;
3265         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3266         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3267         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3268         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3269         struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3270         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3271         struct mlx5_ifc_qos_cap_bits qos_cap;
3272         struct mlx5_ifc_debug_cap_bits debug_cap;
3273         struct mlx5_ifc_fpga_cap_bits fpga_cap;
3274         struct mlx5_ifc_tls_cap_bits tls_cap;
3275         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3276         struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3277         struct mlx5_ifc_shampo_cap_bits shampo_cap;
3278         u8         reserved_at_0[0x8000];
3279 };
3280
3281 enum {
3282         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3283         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3284         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3285         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3286         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3287         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3288         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3289         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3290         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3291         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3292         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3293         MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3294         MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3295         MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3296 };
3297
3298 enum {
3299         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3300         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3301         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3302 };
3303
3304 struct mlx5_ifc_vlan_bits {
3305         u8         ethtype[0x10];
3306         u8         prio[0x3];
3307         u8         cfi[0x1];
3308         u8         vid[0xc];
3309 };
3310
3311 enum {
3312         MLX5_FLOW_METER_COLOR_RED       = 0x0,
3313         MLX5_FLOW_METER_COLOR_YELLOW    = 0x1,
3314         MLX5_FLOW_METER_COLOR_GREEN     = 0x2,
3315         MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3316 };
3317
3318 enum {
3319         MLX5_EXE_ASO_FLOW_METER         = 0x2,
3320 };
3321
3322 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3323         u8        return_reg_id[0x4];
3324         u8        aso_type[0x4];
3325         u8        reserved_at_8[0x14];
3326         u8        action[0x1];
3327         u8        init_color[0x2];
3328         u8        meter_id[0x1];
3329 };
3330
3331 union mlx5_ifc_exe_aso_ctrl {
3332         struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3333 };
3334
3335 struct mlx5_ifc_execute_aso_bits {
3336         u8        valid[0x1];
3337         u8        reserved_at_1[0x7];
3338         u8        aso_object_id[0x18];
3339
3340         union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3341 };
3342
3343 struct mlx5_ifc_flow_context_bits {
3344         struct mlx5_ifc_vlan_bits push_vlan;
3345
3346         u8         group_id[0x20];
3347
3348         u8         reserved_at_40[0x8];
3349         u8         flow_tag[0x18];
3350
3351         u8         reserved_at_60[0x10];
3352         u8         action[0x10];
3353
3354         u8         extended_destination[0x1];
3355         u8         reserved_at_81[0x1];
3356         u8         flow_source[0x2];
3357         u8         reserved_at_84[0x4];
3358         u8         destination_list_size[0x18];
3359
3360         u8         reserved_at_a0[0x8];
3361         u8         flow_counter_list_size[0x18];
3362
3363         u8         packet_reformat_id[0x20];
3364
3365         u8         modify_header_id[0x20];
3366
3367         struct mlx5_ifc_vlan_bits push_vlan_2;
3368
3369         u8         ipsec_obj_id[0x20];
3370         u8         reserved_at_140[0xc0];
3371
3372         struct mlx5_ifc_fte_match_param_bits match_value;
3373
3374         struct mlx5_ifc_execute_aso_bits execute_aso[4];
3375
3376         u8         reserved_at_1300[0x500];
3377
3378         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3379 };
3380
3381 enum {
3382         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3383         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3384 };
3385
3386 struct mlx5_ifc_xrc_srqc_bits {
3387         u8         state[0x4];
3388         u8         log_xrc_srq_size[0x4];
3389         u8         reserved_at_8[0x18];
3390
3391         u8         wq_signature[0x1];
3392         u8         cont_srq[0x1];
3393         u8         reserved_at_22[0x1];
3394         u8         rlky[0x1];
3395         u8         basic_cyclic_rcv_wqe[0x1];
3396         u8         log_rq_stride[0x3];
3397         u8         xrcd[0x18];
3398
3399         u8         page_offset[0x6];
3400         u8         reserved_at_46[0x1];
3401         u8         dbr_umem_valid[0x1];
3402         u8         cqn[0x18];
3403
3404         u8         reserved_at_60[0x20];
3405
3406         u8         user_index_equal_xrc_srqn[0x1];
3407         u8         reserved_at_81[0x1];
3408         u8         log_page_size[0x6];
3409         u8         user_index[0x18];
3410
3411         u8         reserved_at_a0[0x20];
3412
3413         u8         reserved_at_c0[0x8];
3414         u8         pd[0x18];
3415
3416         u8         lwm[0x10];
3417         u8         wqe_cnt[0x10];
3418
3419         u8         reserved_at_100[0x40];
3420
3421         u8         db_record_addr_h[0x20];
3422
3423         u8         db_record_addr_l[0x1e];
3424         u8         reserved_at_17e[0x2];
3425
3426         u8         reserved_at_180[0x80];
3427 };
3428
3429 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3430         u8         counter_error_queues[0x20];
3431
3432         u8         total_error_queues[0x20];
3433
3434         u8         send_queue_priority_update_flow[0x20];
3435
3436         u8         reserved_at_60[0x20];
3437
3438         u8         nic_receive_steering_discard[0x40];
3439
3440         u8         receive_discard_vport_down[0x40];
3441
3442         u8         transmit_discard_vport_down[0x40];
3443
3444         u8         reserved_at_140[0xa0];
3445
3446         u8         internal_rq_out_of_buffer[0x20];
3447
3448         u8         reserved_at_200[0xe00];
3449 };
3450
3451 struct mlx5_ifc_traffic_counter_bits {
3452         u8         packets[0x40];
3453
3454         u8         octets[0x40];
3455 };
3456
3457 struct mlx5_ifc_tisc_bits {
3458         u8         strict_lag_tx_port_affinity[0x1];
3459         u8         tls_en[0x1];
3460         u8         reserved_at_2[0x2];
3461         u8         lag_tx_port_affinity[0x04];
3462
3463         u8         reserved_at_8[0x4];
3464         u8         prio[0x4];
3465         u8         reserved_at_10[0x10];
3466
3467         u8         reserved_at_20[0x100];
3468
3469         u8         reserved_at_120[0x8];
3470         u8         transport_domain[0x18];
3471
3472         u8         reserved_at_140[0x8];
3473         u8         underlay_qpn[0x18];
3474
3475         u8         reserved_at_160[0x8];
3476         u8         pd[0x18];
3477
3478         u8         reserved_at_180[0x380];
3479 };
3480
3481 enum {
3482         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3483         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3484 };
3485
3486 enum {
3487         MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3488         MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3489 };
3490
3491 enum {
3492         MLX5_RX_HASH_FN_NONE           = 0x0,
3493         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3494         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3495 };
3496
3497 enum {
3498         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3499         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3500 };
3501
3502 struct mlx5_ifc_tirc_bits {
3503         u8         reserved_at_0[0x20];
3504
3505         u8         disp_type[0x4];
3506         u8         tls_en[0x1];
3507         u8         reserved_at_25[0x1b];
3508
3509         u8         reserved_at_40[0x40];
3510
3511         u8         reserved_at_80[0x4];
3512         u8         lro_timeout_period_usecs[0x10];
3513         u8         packet_merge_mask[0x4];
3514         u8         lro_max_ip_payload_size[0x8];
3515
3516         u8         reserved_at_a0[0x40];
3517
3518         u8         reserved_at_e0[0x8];
3519         u8         inline_rqn[0x18];
3520
3521         u8         rx_hash_symmetric[0x1];
3522         u8         reserved_at_101[0x1];
3523         u8         tunneled_offload_en[0x1];
3524         u8         reserved_at_103[0x5];
3525         u8         indirect_table[0x18];
3526
3527         u8         rx_hash_fn[0x4];
3528         u8         reserved_at_124[0x2];
3529         u8         self_lb_block[0x2];
3530         u8         transport_domain[0x18];
3531
3532         u8         rx_hash_toeplitz_key[10][0x20];
3533
3534         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3535
3536         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3537
3538         u8         reserved_at_2c0[0x4c0];
3539 };
3540
3541 enum {
3542         MLX5_SRQC_STATE_GOOD   = 0x0,
3543         MLX5_SRQC_STATE_ERROR  = 0x1,
3544 };
3545
3546 struct mlx5_ifc_srqc_bits {
3547         u8         state[0x4];
3548         u8         log_srq_size[0x4];
3549         u8         reserved_at_8[0x18];
3550
3551         u8         wq_signature[0x1];
3552         u8         cont_srq[0x1];
3553         u8         reserved_at_22[0x1];
3554         u8         rlky[0x1];
3555         u8         reserved_at_24[0x1];
3556         u8         log_rq_stride[0x3];
3557         u8         xrcd[0x18];
3558
3559         u8         page_offset[0x6];
3560         u8         reserved_at_46[0x2];
3561         u8         cqn[0x18];
3562
3563         u8         reserved_at_60[0x20];
3564
3565         u8         reserved_at_80[0x2];
3566         u8         log_page_size[0x6];
3567         u8         reserved_at_88[0x18];
3568
3569         u8         reserved_at_a0[0x20];
3570
3571         u8         reserved_at_c0[0x8];
3572         u8         pd[0x18];
3573
3574         u8         lwm[0x10];
3575         u8         wqe_cnt[0x10];
3576
3577         u8         reserved_at_100[0x40];
3578
3579         u8         dbr_addr[0x40];
3580
3581         u8         reserved_at_180[0x80];
3582 };
3583
3584 enum {
3585         MLX5_SQC_STATE_RST  = 0x0,
3586         MLX5_SQC_STATE_RDY  = 0x1,
3587         MLX5_SQC_STATE_ERR  = 0x3,
3588 };
3589
3590 struct mlx5_ifc_sqc_bits {
3591         u8         rlky[0x1];
3592         u8         cd_master[0x1];
3593         u8         fre[0x1];
3594         u8         flush_in_error_en[0x1];
3595         u8         allow_multi_pkt_send_wqe[0x1];
3596         u8         min_wqe_inline_mode[0x3];
3597         u8         state[0x4];
3598         u8         reg_umr[0x1];
3599         u8         allow_swp[0x1];
3600         u8         hairpin[0x1];
3601         u8         reserved_at_f[0xb];
3602         u8         ts_format[0x2];
3603         u8         reserved_at_1c[0x4];
3604
3605         u8         reserved_at_20[0x8];
3606         u8         user_index[0x18];
3607
3608         u8         reserved_at_40[0x8];
3609         u8         cqn[0x18];
3610
3611         u8         reserved_at_60[0x8];
3612         u8         hairpin_peer_rq[0x18];
3613
3614         u8         reserved_at_80[0x10];
3615         u8         hairpin_peer_vhca[0x10];
3616
3617         u8         reserved_at_a0[0x20];
3618
3619         u8         reserved_at_c0[0x8];
3620         u8         ts_cqe_to_dest_cqn[0x18];
3621
3622         u8         reserved_at_e0[0x10];
3623         u8         packet_pacing_rate_limit_index[0x10];
3624         u8         tis_lst_sz[0x10];
3625         u8         qos_queue_group_id[0x10];
3626
3627         u8         reserved_at_120[0x40];
3628
3629         u8         reserved_at_160[0x8];
3630         u8         tis_num_0[0x18];
3631
3632         struct mlx5_ifc_wq_bits wq;
3633 };
3634
3635 enum {
3636         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3637         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3638         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3639         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3640         SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3641 };
3642
3643 enum {
3644         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3645         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3646         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3647         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3648 };
3649
3650 struct mlx5_ifc_scheduling_context_bits {
3651         u8         element_type[0x8];
3652         u8         reserved_at_8[0x18];
3653
3654         u8         element_attributes[0x20];
3655
3656         u8         parent_element_id[0x20];
3657
3658         u8         reserved_at_60[0x40];
3659
3660         u8         bw_share[0x20];
3661
3662         u8         max_average_bw[0x20];
3663
3664         u8         reserved_at_e0[0x120];
3665 };
3666
3667 struct mlx5_ifc_rqtc_bits {
3668         u8    reserved_at_0[0xa0];
3669
3670         u8    reserved_at_a0[0x5];
3671         u8    list_q_type[0x3];
3672         u8    reserved_at_a8[0x8];
3673         u8    rqt_max_size[0x10];
3674
3675         u8    rq_vhca_id_format[0x1];
3676         u8    reserved_at_c1[0xf];
3677         u8    rqt_actual_size[0x10];
3678
3679         u8    reserved_at_e0[0x6a0];
3680
3681         struct mlx5_ifc_rq_num_bits rq_num[];
3682 };
3683
3684 enum {
3685         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3686         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3687 };
3688
3689 enum {
3690         MLX5_RQC_STATE_RST  = 0x0,
3691         MLX5_RQC_STATE_RDY  = 0x1,
3692         MLX5_RQC_STATE_ERR  = 0x3,
3693 };
3694
3695 enum {
3696         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
3697         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
3698         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
3699 };
3700
3701 enum {
3702         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
3703         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
3704         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
3705 };
3706
3707 struct mlx5_ifc_rqc_bits {
3708         u8         rlky[0x1];
3709         u8         delay_drop_en[0x1];
3710         u8         scatter_fcs[0x1];
3711         u8         vsd[0x1];
3712         u8         mem_rq_type[0x4];
3713         u8         state[0x4];
3714         u8         reserved_at_c[0x1];
3715         u8         flush_in_error_en[0x1];
3716         u8         hairpin[0x1];
3717         u8         reserved_at_f[0xb];
3718         u8         ts_format[0x2];
3719         u8         reserved_at_1c[0x4];
3720
3721         u8         reserved_at_20[0x8];
3722         u8         user_index[0x18];
3723
3724         u8         reserved_at_40[0x8];
3725         u8         cqn[0x18];
3726
3727         u8         counter_set_id[0x8];
3728         u8         reserved_at_68[0x18];
3729
3730         u8         reserved_at_80[0x8];
3731         u8         rmpn[0x18];
3732
3733         u8         reserved_at_a0[0x8];
3734         u8         hairpin_peer_sq[0x18];
3735
3736         u8         reserved_at_c0[0x10];
3737         u8         hairpin_peer_vhca[0x10];
3738
3739         u8         reserved_at_e0[0x46];
3740         u8         shampo_no_match_alignment_granularity[0x2];
3741         u8         reserved_at_128[0x6];
3742         u8         shampo_match_criteria_type[0x2];
3743         u8         reservation_timeout[0x10];
3744
3745         u8         reserved_at_140[0x40];
3746
3747         struct mlx5_ifc_wq_bits wq;
3748 };
3749
3750 enum {
3751         MLX5_RMPC_STATE_RDY  = 0x1,
3752         MLX5_RMPC_STATE_ERR  = 0x3,
3753 };
3754
3755 struct mlx5_ifc_rmpc_bits {
3756         u8         reserved_at_0[0x8];
3757         u8         state[0x4];
3758         u8         reserved_at_c[0x14];
3759
3760         u8         basic_cyclic_rcv_wqe[0x1];
3761         u8         reserved_at_21[0x1f];
3762
3763         u8         reserved_at_40[0x140];
3764
3765         struct mlx5_ifc_wq_bits wq;
3766 };
3767
3768 struct mlx5_ifc_nic_vport_context_bits {
3769         u8         reserved_at_0[0x5];
3770         u8         min_wqe_inline_mode[0x3];
3771         u8         reserved_at_8[0x15];
3772         u8         disable_mc_local_lb[0x1];
3773         u8         disable_uc_local_lb[0x1];
3774         u8         roce_en[0x1];
3775
3776         u8         arm_change_event[0x1];
3777         u8         reserved_at_21[0x1a];
3778         u8         event_on_mtu[0x1];
3779         u8         event_on_promisc_change[0x1];
3780         u8         event_on_vlan_change[0x1];
3781         u8         event_on_mc_address_change[0x1];
3782         u8         event_on_uc_address_change[0x1];
3783
3784         u8         reserved_at_40[0xc];
3785
3786         u8         affiliation_criteria[0x4];
3787         u8         affiliated_vhca_id[0x10];
3788
3789         u8         reserved_at_60[0xd0];
3790
3791         u8         mtu[0x10];
3792
3793         u8         system_image_guid[0x40];
3794         u8         port_guid[0x40];
3795         u8         node_guid[0x40];
3796
3797         u8         reserved_at_200[0x140];
3798         u8         qkey_violation_counter[0x10];
3799         u8         reserved_at_350[0x430];
3800
3801         u8         promisc_uc[0x1];
3802         u8         promisc_mc[0x1];
3803         u8         promisc_all[0x1];
3804         u8         reserved_at_783[0x2];
3805         u8         allowed_list_type[0x3];
3806         u8         reserved_at_788[0xc];
3807         u8         allowed_list_size[0xc];
3808
3809         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3810
3811         u8         reserved_at_7e0[0x20];
3812
3813         u8         current_uc_mac_address[][0x40];
3814 };
3815
3816 enum {
3817         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3818         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3819         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3820         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3821         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3822         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3823 };
3824
3825 struct mlx5_ifc_mkc_bits {
3826         u8         reserved_at_0[0x1];
3827         u8         free[0x1];
3828         u8         reserved_at_2[0x1];
3829         u8         access_mode_4_2[0x3];
3830         u8         reserved_at_6[0x7];
3831         u8         relaxed_ordering_write[0x1];
3832         u8         reserved_at_e[0x1];
3833         u8         small_fence_on_rdma_read_response[0x1];
3834         u8         umr_en[0x1];
3835         u8         a[0x1];
3836         u8         rw[0x1];
3837         u8         rr[0x1];
3838         u8         lw[0x1];
3839         u8         lr[0x1];
3840         u8         access_mode_1_0[0x2];
3841         u8         reserved_at_18[0x8];
3842
3843         u8         qpn[0x18];
3844         u8         mkey_7_0[0x8];
3845
3846         u8         reserved_at_40[0x20];
3847
3848         u8         length64[0x1];
3849         u8         bsf_en[0x1];
3850         u8         sync_umr[0x1];
3851         u8         reserved_at_63[0x2];
3852         u8         expected_sigerr_count[0x1];
3853         u8         reserved_at_66[0x1];
3854         u8         en_rinval[0x1];
3855         u8         pd[0x18];
3856
3857         u8         start_addr[0x40];
3858
3859         u8         len[0x40];
3860
3861         u8         bsf_octword_size[0x20];
3862
3863         u8         reserved_at_120[0x80];
3864
3865         u8         translations_octword_size[0x20];
3866
3867         u8         reserved_at_1c0[0x19];
3868         u8         relaxed_ordering_read[0x1];
3869         u8         reserved_at_1d9[0x1];
3870         u8         log_page_size[0x5];
3871
3872         u8         reserved_at_1e0[0x20];
3873 };
3874
3875 struct mlx5_ifc_pkey_bits {
3876         u8         reserved_at_0[0x10];
3877         u8         pkey[0x10];
3878 };
3879
3880 struct mlx5_ifc_array128_auto_bits {
3881         u8         array128_auto[16][0x8];
3882 };
3883
3884 struct mlx5_ifc_hca_vport_context_bits {
3885         u8         field_select[0x20];
3886
3887         u8         reserved_at_20[0xe0];
3888
3889         u8         sm_virt_aware[0x1];
3890         u8         has_smi[0x1];
3891         u8         has_raw[0x1];
3892         u8         grh_required[0x1];
3893         u8         reserved_at_104[0xc];
3894         u8         port_physical_state[0x4];
3895         u8         vport_state_policy[0x4];
3896         u8         port_state[0x4];
3897         u8         vport_state[0x4];
3898
3899         u8         reserved_at_120[0x20];
3900
3901         u8         system_image_guid[0x40];
3902
3903         u8         port_guid[0x40];
3904
3905         u8         node_guid[0x40];
3906
3907         u8         cap_mask1[0x20];
3908
3909         u8         cap_mask1_field_select[0x20];
3910
3911         u8         cap_mask2[0x20];
3912
3913         u8         cap_mask2_field_select[0x20];
3914
3915         u8         reserved_at_280[0x80];
3916
3917         u8         lid[0x10];
3918         u8         reserved_at_310[0x4];
3919         u8         init_type_reply[0x4];
3920         u8         lmc[0x3];
3921         u8         subnet_timeout[0x5];
3922
3923         u8         sm_lid[0x10];
3924         u8         sm_sl[0x4];
3925         u8         reserved_at_334[0xc];
3926
3927         u8         qkey_violation_counter[0x10];
3928         u8         pkey_violation_counter[0x10];
3929
3930         u8         reserved_at_360[0xca0];
3931 };
3932
3933 struct mlx5_ifc_esw_vport_context_bits {
3934         u8         fdb_to_vport_reg_c[0x1];
3935         u8         reserved_at_1[0x2];
3936         u8         vport_svlan_strip[0x1];
3937         u8         vport_cvlan_strip[0x1];
3938         u8         vport_svlan_insert[0x1];
3939         u8         vport_cvlan_insert[0x2];
3940         u8         fdb_to_vport_reg_c_id[0x8];
3941         u8         reserved_at_10[0x10];
3942
3943         u8         reserved_at_20[0x20];
3944
3945         u8         svlan_cfi[0x1];
3946         u8         svlan_pcp[0x3];
3947         u8         svlan_id[0xc];
3948         u8         cvlan_cfi[0x1];
3949         u8         cvlan_pcp[0x3];
3950         u8         cvlan_id[0xc];
3951
3952         u8         reserved_at_60[0x720];
3953
3954         u8         sw_steering_vport_icm_address_rx[0x40];
3955
3956         u8         sw_steering_vport_icm_address_tx[0x40];
3957 };
3958
3959 enum {
3960         MLX5_EQC_STATUS_OK                = 0x0,
3961         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3962 };
3963
3964 enum {
3965         MLX5_EQC_ST_ARMED  = 0x9,
3966         MLX5_EQC_ST_FIRED  = 0xa,
3967 };
3968
3969 struct mlx5_ifc_eqc_bits {
3970         u8         status[0x4];
3971         u8         reserved_at_4[0x9];
3972         u8         ec[0x1];
3973         u8         oi[0x1];
3974         u8         reserved_at_f[0x5];
3975         u8         st[0x4];
3976         u8         reserved_at_18[0x8];
3977
3978         u8         reserved_at_20[0x20];
3979
3980         u8         reserved_at_40[0x14];
3981         u8         page_offset[0x6];
3982         u8         reserved_at_5a[0x6];
3983
3984         u8         reserved_at_60[0x3];
3985         u8         log_eq_size[0x5];
3986         u8         uar_page[0x18];
3987
3988         u8         reserved_at_80[0x20];
3989
3990         u8         reserved_at_a0[0x14];
3991         u8         intr[0xc];
3992
3993         u8         reserved_at_c0[0x3];
3994         u8         log_page_size[0x5];
3995         u8         reserved_at_c8[0x18];
3996
3997         u8         reserved_at_e0[0x60];
3998
3999         u8         reserved_at_140[0x8];
4000         u8         consumer_counter[0x18];
4001
4002         u8         reserved_at_160[0x8];
4003         u8         producer_counter[0x18];
4004
4005         u8         reserved_at_180[0x80];
4006 };
4007
4008 enum {
4009         MLX5_DCTC_STATE_ACTIVE    = 0x0,
4010         MLX5_DCTC_STATE_DRAINING  = 0x1,
4011         MLX5_DCTC_STATE_DRAINED   = 0x2,
4012 };
4013
4014 enum {
4015         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4016         MLX5_DCTC_CS_RES_NA         = 0x1,
4017         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4018 };
4019
4020 enum {
4021         MLX5_DCTC_MTU_256_BYTES  = 0x1,
4022         MLX5_DCTC_MTU_512_BYTES  = 0x2,
4023         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4024         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4025         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4026 };
4027
4028 struct mlx5_ifc_dctc_bits {
4029         u8         reserved_at_0[0x4];
4030         u8         state[0x4];
4031         u8         reserved_at_8[0x18];
4032
4033         u8         reserved_at_20[0x8];
4034         u8         user_index[0x18];
4035
4036         u8         reserved_at_40[0x8];
4037         u8         cqn[0x18];
4038
4039         u8         counter_set_id[0x8];
4040         u8         atomic_mode[0x4];
4041         u8         rre[0x1];
4042         u8         rwe[0x1];
4043         u8         rae[0x1];
4044         u8         atomic_like_write_en[0x1];
4045         u8         latency_sensitive[0x1];
4046         u8         rlky[0x1];
4047         u8         free_ar[0x1];
4048         u8         reserved_at_73[0xd];
4049
4050         u8         reserved_at_80[0x8];
4051         u8         cs_res[0x8];
4052         u8         reserved_at_90[0x3];
4053         u8         min_rnr_nak[0x5];
4054         u8         reserved_at_98[0x8];
4055
4056         u8         reserved_at_a0[0x8];
4057         u8         srqn_xrqn[0x18];
4058
4059         u8         reserved_at_c0[0x8];
4060         u8         pd[0x18];
4061
4062         u8         tclass[0x8];
4063         u8         reserved_at_e8[0x4];
4064         u8         flow_label[0x14];
4065
4066         u8         dc_access_key[0x40];
4067
4068         u8         reserved_at_140[0x5];
4069         u8         mtu[0x3];
4070         u8         port[0x8];
4071         u8         pkey_index[0x10];
4072
4073         u8         reserved_at_160[0x8];
4074         u8         my_addr_index[0x8];
4075         u8         reserved_at_170[0x8];
4076         u8         hop_limit[0x8];
4077
4078         u8         dc_access_key_violation_count[0x20];
4079
4080         u8         reserved_at_1a0[0x14];
4081         u8         dei_cfi[0x1];
4082         u8         eth_prio[0x3];
4083         u8         ecn[0x2];
4084         u8         dscp[0x6];
4085
4086         u8         reserved_at_1c0[0x20];
4087         u8         ece[0x20];
4088 };
4089
4090 enum {
4091         MLX5_CQC_STATUS_OK             = 0x0,
4092         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4093         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4094 };
4095
4096 enum {
4097         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4098         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4099 };
4100
4101 enum {
4102         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4103         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4104         MLX5_CQC_ST_FIRED                                 = 0xa,
4105 };
4106
4107 enum {
4108         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4109         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4110         MLX5_CQ_PERIOD_NUM_MODES
4111 };
4112
4113 struct mlx5_ifc_cqc_bits {
4114         u8         status[0x4];
4115         u8         reserved_at_4[0x2];
4116         u8         dbr_umem_valid[0x1];
4117         u8         apu_cq[0x1];
4118         u8         cqe_sz[0x3];
4119         u8         cc[0x1];
4120         u8         reserved_at_c[0x1];
4121         u8         scqe_break_moderation_en[0x1];
4122         u8         oi[0x1];
4123         u8         cq_period_mode[0x2];
4124         u8         cqe_comp_en[0x1];
4125         u8         mini_cqe_res_format[0x2];
4126         u8         st[0x4];
4127         u8         reserved_at_18[0x8];
4128
4129         u8         reserved_at_20[0x20];
4130
4131         u8         reserved_at_40[0x14];
4132         u8         page_offset[0x6];
4133         u8         reserved_at_5a[0x6];
4134
4135         u8         reserved_at_60[0x3];
4136         u8         log_cq_size[0x5];
4137         u8         uar_page[0x18];
4138
4139         u8         reserved_at_80[0x4];
4140         u8         cq_period[0xc];
4141         u8         cq_max_count[0x10];
4142
4143         u8         c_eqn_or_apu_element[0x20];
4144
4145         u8         reserved_at_c0[0x3];
4146         u8         log_page_size[0x5];
4147         u8         reserved_at_c8[0x18];
4148
4149         u8         reserved_at_e0[0x20];
4150
4151         u8         reserved_at_100[0x8];
4152         u8         last_notified_index[0x18];
4153
4154         u8         reserved_at_120[0x8];
4155         u8         last_solicit_index[0x18];
4156
4157         u8         reserved_at_140[0x8];
4158         u8         consumer_counter[0x18];
4159
4160         u8         reserved_at_160[0x8];
4161         u8         producer_counter[0x18];
4162
4163         u8         reserved_at_180[0x40];
4164
4165         u8         dbr_addr[0x40];
4166 };
4167
4168 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4169         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4170         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4171         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4172         u8         reserved_at_0[0x800];
4173 };
4174
4175 struct mlx5_ifc_query_adapter_param_block_bits {
4176         u8         reserved_at_0[0xc0];
4177
4178         u8         reserved_at_c0[0x8];
4179         u8         ieee_vendor_id[0x18];
4180
4181         u8         reserved_at_e0[0x10];
4182         u8         vsd_vendor_id[0x10];
4183
4184         u8         vsd[208][0x8];
4185
4186         u8         vsd_contd_psid[16][0x8];
4187 };
4188
4189 enum {
4190         MLX5_XRQC_STATE_GOOD   = 0x0,
4191         MLX5_XRQC_STATE_ERROR  = 0x1,
4192 };
4193
4194 enum {
4195         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4196         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4197 };
4198
4199 enum {
4200         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4201 };
4202
4203 struct mlx5_ifc_tag_matching_topology_context_bits {
4204         u8         log_matching_list_sz[0x4];
4205         u8         reserved_at_4[0xc];
4206         u8         append_next_index[0x10];
4207
4208         u8         sw_phase_cnt[0x10];
4209         u8         hw_phase_cnt[0x10];
4210
4211         u8         reserved_at_40[0x40];
4212 };
4213
4214 struct mlx5_ifc_xrqc_bits {
4215         u8         state[0x4];
4216         u8         rlkey[0x1];
4217         u8         reserved_at_5[0xf];
4218         u8         topology[0x4];
4219         u8         reserved_at_18[0x4];
4220         u8         offload[0x4];
4221
4222         u8         reserved_at_20[0x8];
4223         u8         user_index[0x18];
4224
4225         u8         reserved_at_40[0x8];
4226         u8         cqn[0x18];
4227
4228         u8         reserved_at_60[0xa0];
4229
4230         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4231
4232         u8         reserved_at_180[0x280];
4233
4234         struct mlx5_ifc_wq_bits wq;
4235 };
4236
4237 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4238         struct mlx5_ifc_modify_field_select_bits modify_field_select;
4239         struct mlx5_ifc_resize_field_select_bits resize_field_select;
4240         u8         reserved_at_0[0x20];
4241 };
4242
4243 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4244         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4245         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4246         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4247         u8         reserved_at_0[0x20];
4248 };
4249
4250 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4251         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4252         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4253         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4254         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4255         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4256         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4257         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4258         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4259         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4260         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4261         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4262         u8         reserved_at_0[0x7c0];
4263 };
4264
4265 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4266         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4267         u8         reserved_at_0[0x7c0];
4268 };
4269
4270 union mlx5_ifc_event_auto_bits {
4271         struct mlx5_ifc_comp_event_bits comp_event;
4272         struct mlx5_ifc_dct_events_bits dct_events;
4273         struct mlx5_ifc_qp_events_bits qp_events;
4274         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4275         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4276         struct mlx5_ifc_cq_error_bits cq_error;
4277         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4278         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4279         struct mlx5_ifc_gpio_event_bits gpio_event;
4280         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4281         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4282         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4283         u8         reserved_at_0[0xe0];
4284 };
4285
4286 struct mlx5_ifc_health_buffer_bits {
4287         u8         reserved_at_0[0x100];
4288
4289         u8         assert_existptr[0x20];
4290
4291         u8         assert_callra[0x20];
4292
4293         u8         reserved_at_140[0x20];
4294
4295         u8         time[0x20];
4296
4297         u8         fw_version[0x20];
4298
4299         u8         hw_id[0x20];
4300
4301         u8         rfr[0x1];
4302         u8         reserved_at_1c1[0x3];
4303         u8         valid[0x1];
4304         u8         severity[0x3];
4305         u8         reserved_at_1c8[0x18];
4306
4307         u8         irisc_index[0x8];
4308         u8         synd[0x8];
4309         u8         ext_synd[0x10];
4310 };
4311
4312 struct mlx5_ifc_register_loopback_control_bits {
4313         u8         no_lb[0x1];
4314         u8         reserved_at_1[0x7];
4315         u8         port[0x8];
4316         u8         reserved_at_10[0x10];
4317
4318         u8         reserved_at_20[0x60];
4319 };
4320
4321 struct mlx5_ifc_vport_tc_element_bits {
4322         u8         traffic_class[0x4];
4323         u8         reserved_at_4[0xc];
4324         u8         vport_number[0x10];
4325 };
4326
4327 struct mlx5_ifc_vport_element_bits {
4328         u8         reserved_at_0[0x10];
4329         u8         vport_number[0x10];
4330 };
4331
4332 enum {
4333         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4334         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4335         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4336 };
4337
4338 struct mlx5_ifc_tsar_element_bits {
4339         u8         reserved_at_0[0x8];
4340         u8         tsar_type[0x8];
4341         u8         reserved_at_10[0x10];
4342 };
4343
4344 enum {
4345         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4346         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4347 };
4348
4349 struct mlx5_ifc_teardown_hca_out_bits {
4350         u8         status[0x8];
4351         u8         reserved_at_8[0x18];
4352
4353         u8         syndrome[0x20];
4354
4355         u8         reserved_at_40[0x3f];
4356
4357         u8         state[0x1];
4358 };
4359
4360 enum {
4361         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4362         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4363         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4364 };
4365
4366 struct mlx5_ifc_teardown_hca_in_bits {
4367         u8         opcode[0x10];
4368         u8         reserved_at_10[0x10];
4369
4370         u8         reserved_at_20[0x10];
4371         u8         op_mod[0x10];
4372
4373         u8         reserved_at_40[0x10];
4374         u8         profile[0x10];
4375
4376         u8         reserved_at_60[0x20];
4377 };
4378
4379 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4380         u8         status[0x8];
4381         u8         reserved_at_8[0x18];
4382
4383         u8         syndrome[0x20];
4384
4385         u8         reserved_at_40[0x40];
4386 };
4387
4388 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4389         u8         opcode[0x10];
4390         u8         uid[0x10];
4391
4392         u8         reserved_at_20[0x10];
4393         u8         op_mod[0x10];
4394
4395         u8         reserved_at_40[0x8];
4396         u8         qpn[0x18];
4397
4398         u8         reserved_at_60[0x20];
4399
4400         u8         opt_param_mask[0x20];
4401
4402         u8         reserved_at_a0[0x20];
4403
4404         struct mlx5_ifc_qpc_bits qpc;
4405
4406         u8         reserved_at_800[0x80];
4407 };
4408
4409 struct mlx5_ifc_sqd2rts_qp_out_bits {
4410         u8         status[0x8];
4411         u8         reserved_at_8[0x18];
4412
4413         u8         syndrome[0x20];
4414
4415         u8         reserved_at_40[0x40];
4416 };
4417
4418 struct mlx5_ifc_sqd2rts_qp_in_bits {
4419         u8         opcode[0x10];
4420         u8         uid[0x10];
4421
4422         u8         reserved_at_20[0x10];
4423         u8         op_mod[0x10];
4424
4425         u8         reserved_at_40[0x8];
4426         u8         qpn[0x18];
4427
4428         u8         reserved_at_60[0x20];
4429
4430         u8         opt_param_mask[0x20];
4431
4432         u8         reserved_at_a0[0x20];
4433
4434         struct mlx5_ifc_qpc_bits qpc;
4435
4436         u8         reserved_at_800[0x80];
4437 };
4438
4439 struct mlx5_ifc_set_roce_address_out_bits {
4440         u8         status[0x8];
4441         u8         reserved_at_8[0x18];
4442
4443         u8         syndrome[0x20];
4444
4445         u8         reserved_at_40[0x40];
4446 };
4447
4448 struct mlx5_ifc_set_roce_address_in_bits {
4449         u8         opcode[0x10];
4450         u8         reserved_at_10[0x10];
4451
4452         u8         reserved_at_20[0x10];
4453         u8         op_mod[0x10];
4454
4455         u8         roce_address_index[0x10];
4456         u8         reserved_at_50[0xc];
4457         u8         vhca_port_num[0x4];
4458
4459         u8         reserved_at_60[0x20];
4460
4461         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4462 };
4463
4464 struct mlx5_ifc_set_mad_demux_out_bits {
4465         u8         status[0x8];
4466         u8         reserved_at_8[0x18];
4467
4468         u8         syndrome[0x20];
4469
4470         u8         reserved_at_40[0x40];
4471 };
4472
4473 enum {
4474         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4475         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4476 };
4477
4478 struct mlx5_ifc_set_mad_demux_in_bits {
4479         u8         opcode[0x10];
4480         u8         reserved_at_10[0x10];
4481
4482         u8         reserved_at_20[0x10];
4483         u8         op_mod[0x10];
4484
4485         u8         reserved_at_40[0x20];
4486
4487         u8         reserved_at_60[0x6];
4488         u8         demux_mode[0x2];
4489         u8         reserved_at_68[0x18];
4490 };
4491
4492 struct mlx5_ifc_set_l2_table_entry_out_bits {
4493         u8         status[0x8];
4494         u8         reserved_at_8[0x18];
4495
4496         u8         syndrome[0x20];
4497
4498         u8         reserved_at_40[0x40];
4499 };
4500
4501 struct mlx5_ifc_set_l2_table_entry_in_bits {
4502         u8         opcode[0x10];
4503         u8         reserved_at_10[0x10];
4504
4505         u8         reserved_at_20[0x10];
4506         u8         op_mod[0x10];
4507
4508         u8         reserved_at_40[0x60];
4509
4510         u8         reserved_at_a0[0x8];
4511         u8         table_index[0x18];
4512
4513         u8         reserved_at_c0[0x20];
4514
4515         u8         reserved_at_e0[0x13];
4516         u8         vlan_valid[0x1];
4517         u8         vlan[0xc];
4518
4519         struct mlx5_ifc_mac_address_layout_bits mac_address;
4520
4521         u8         reserved_at_140[0xc0];
4522 };
4523
4524 struct mlx5_ifc_set_issi_out_bits {
4525         u8         status[0x8];
4526         u8         reserved_at_8[0x18];
4527
4528         u8         syndrome[0x20];
4529
4530         u8         reserved_at_40[0x40];
4531 };
4532
4533 struct mlx5_ifc_set_issi_in_bits {
4534         u8         opcode[0x10];
4535         u8         reserved_at_10[0x10];
4536
4537         u8         reserved_at_20[0x10];
4538         u8         op_mod[0x10];
4539
4540         u8         reserved_at_40[0x10];
4541         u8         current_issi[0x10];
4542
4543         u8         reserved_at_60[0x20];
4544 };
4545
4546 struct mlx5_ifc_set_hca_cap_out_bits {
4547         u8         status[0x8];
4548         u8         reserved_at_8[0x18];
4549
4550         u8         syndrome[0x20];
4551
4552         u8         reserved_at_40[0x40];
4553 };
4554
4555 struct mlx5_ifc_set_hca_cap_in_bits {
4556         u8         opcode[0x10];
4557         u8         reserved_at_10[0x10];
4558
4559         u8         reserved_at_20[0x10];
4560         u8         op_mod[0x10];
4561
4562         u8         other_function[0x1];
4563         u8         reserved_at_41[0xf];
4564         u8         function_id[0x10];
4565
4566         u8         reserved_at_60[0x20];
4567
4568         union mlx5_ifc_hca_cap_union_bits capability;
4569 };
4570
4571 enum {
4572         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4573         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4574         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4575         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4576         MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4577 };
4578
4579 struct mlx5_ifc_set_fte_out_bits {
4580         u8         status[0x8];
4581         u8         reserved_at_8[0x18];
4582
4583         u8         syndrome[0x20];
4584
4585         u8         reserved_at_40[0x40];
4586 };
4587
4588 struct mlx5_ifc_set_fte_in_bits {
4589         u8         opcode[0x10];
4590         u8         reserved_at_10[0x10];
4591
4592         u8         reserved_at_20[0x10];
4593         u8         op_mod[0x10];
4594
4595         u8         other_vport[0x1];
4596         u8         reserved_at_41[0xf];
4597         u8         vport_number[0x10];
4598
4599         u8         reserved_at_60[0x20];
4600
4601         u8         table_type[0x8];
4602         u8         reserved_at_88[0x18];
4603
4604         u8         reserved_at_a0[0x8];
4605         u8         table_id[0x18];
4606
4607         u8         ignore_flow_level[0x1];
4608         u8         reserved_at_c1[0x17];
4609         u8         modify_enable_mask[0x8];
4610
4611         u8         reserved_at_e0[0x20];
4612
4613         u8         flow_index[0x20];
4614
4615         u8         reserved_at_120[0xe0];
4616
4617         struct mlx5_ifc_flow_context_bits flow_context;
4618 };
4619
4620 struct mlx5_ifc_rts2rts_qp_out_bits {
4621         u8         status[0x8];
4622         u8         reserved_at_8[0x18];
4623
4624         u8         syndrome[0x20];
4625
4626         u8         reserved_at_40[0x20];
4627         u8         ece[0x20];
4628 };
4629
4630 struct mlx5_ifc_rts2rts_qp_in_bits {
4631         u8         opcode[0x10];
4632         u8         uid[0x10];
4633
4634         u8         reserved_at_20[0x10];
4635         u8         op_mod[0x10];
4636
4637         u8         reserved_at_40[0x8];
4638         u8         qpn[0x18];
4639
4640         u8         reserved_at_60[0x20];
4641
4642         u8         opt_param_mask[0x20];
4643
4644         u8         ece[0x20];
4645
4646         struct mlx5_ifc_qpc_bits qpc;
4647
4648         u8         reserved_at_800[0x80];
4649 };
4650
4651 struct mlx5_ifc_rtr2rts_qp_out_bits {
4652         u8         status[0x8];
4653         u8         reserved_at_8[0x18];
4654
4655         u8         syndrome[0x20];
4656
4657         u8         reserved_at_40[0x20];
4658         u8         ece[0x20];
4659 };
4660
4661 struct mlx5_ifc_rtr2rts_qp_in_bits {
4662         u8         opcode[0x10];
4663         u8         uid[0x10];
4664
4665         u8         reserved_at_20[0x10];
4666         u8         op_mod[0x10];
4667
4668         u8         reserved_at_40[0x8];
4669         u8         qpn[0x18];
4670
4671         u8         reserved_at_60[0x20];
4672
4673         u8         opt_param_mask[0x20];
4674
4675         u8         ece[0x20];
4676
4677         struct mlx5_ifc_qpc_bits qpc;
4678
4679         u8         reserved_at_800[0x80];
4680 };
4681
4682 struct mlx5_ifc_rst2init_qp_out_bits {
4683         u8         status[0x8];
4684         u8         reserved_at_8[0x18];
4685
4686         u8         syndrome[0x20];
4687
4688         u8         reserved_at_40[0x20];
4689         u8         ece[0x20];
4690 };
4691
4692 struct mlx5_ifc_rst2init_qp_in_bits {
4693         u8         opcode[0x10];
4694         u8         uid[0x10];
4695
4696         u8         reserved_at_20[0x10];
4697         u8         op_mod[0x10];
4698
4699         u8         reserved_at_40[0x8];
4700         u8         qpn[0x18];
4701
4702         u8         reserved_at_60[0x20];
4703
4704         u8         opt_param_mask[0x20];
4705
4706         u8         ece[0x20];
4707
4708         struct mlx5_ifc_qpc_bits qpc;
4709
4710         u8         reserved_at_800[0x80];
4711 };
4712
4713 struct mlx5_ifc_query_xrq_out_bits {
4714         u8         status[0x8];
4715         u8         reserved_at_8[0x18];
4716
4717         u8         syndrome[0x20];
4718
4719         u8         reserved_at_40[0x40];
4720
4721         struct mlx5_ifc_xrqc_bits xrq_context;
4722 };
4723
4724 struct mlx5_ifc_query_xrq_in_bits {
4725         u8         opcode[0x10];
4726         u8         reserved_at_10[0x10];
4727
4728         u8         reserved_at_20[0x10];
4729         u8         op_mod[0x10];
4730
4731         u8         reserved_at_40[0x8];
4732         u8         xrqn[0x18];
4733
4734         u8         reserved_at_60[0x20];
4735 };
4736
4737 struct mlx5_ifc_query_xrc_srq_out_bits {
4738         u8         status[0x8];
4739         u8         reserved_at_8[0x18];
4740
4741         u8         syndrome[0x20];
4742
4743         u8         reserved_at_40[0x40];
4744
4745         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4746
4747         u8         reserved_at_280[0x600];
4748
4749         u8         pas[][0x40];
4750 };
4751
4752 struct mlx5_ifc_query_xrc_srq_in_bits {
4753         u8         opcode[0x10];
4754         u8         reserved_at_10[0x10];
4755
4756         u8         reserved_at_20[0x10];
4757         u8         op_mod[0x10];
4758
4759         u8         reserved_at_40[0x8];
4760         u8         xrc_srqn[0x18];
4761
4762         u8         reserved_at_60[0x20];
4763 };
4764
4765 enum {
4766         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4767         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4768 };
4769
4770 struct mlx5_ifc_query_vport_state_out_bits {
4771         u8         status[0x8];
4772         u8         reserved_at_8[0x18];
4773
4774         u8         syndrome[0x20];
4775
4776         u8         reserved_at_40[0x20];
4777
4778         u8         reserved_at_60[0x18];
4779         u8         admin_state[0x4];
4780         u8         state[0x4];
4781 };
4782
4783 enum {
4784         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4785         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4786         MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4787 };
4788
4789 struct mlx5_ifc_arm_monitor_counter_in_bits {
4790         u8         opcode[0x10];
4791         u8         uid[0x10];
4792
4793         u8         reserved_at_20[0x10];
4794         u8         op_mod[0x10];
4795
4796         u8         reserved_at_40[0x20];
4797
4798         u8         reserved_at_60[0x20];
4799 };
4800
4801 struct mlx5_ifc_arm_monitor_counter_out_bits {
4802         u8         status[0x8];
4803         u8         reserved_at_8[0x18];
4804
4805         u8         syndrome[0x20];
4806
4807         u8         reserved_at_40[0x40];
4808 };
4809
4810 enum {
4811         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4812         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4813 };
4814
4815 enum mlx5_monitor_counter_ppcnt {
4816         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4817         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4818         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4819         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4820         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4821         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4822 };
4823
4824 enum {
4825         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4826 };
4827
4828 struct mlx5_ifc_monitor_counter_output_bits {
4829         u8         reserved_at_0[0x4];
4830         u8         type[0x4];
4831         u8         reserved_at_8[0x8];
4832         u8         counter[0x10];
4833
4834         u8         counter_group_id[0x20];
4835 };
4836
4837 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4838 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4839 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4840                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4841
4842 struct mlx5_ifc_set_monitor_counter_in_bits {
4843         u8         opcode[0x10];
4844         u8         uid[0x10];
4845
4846         u8         reserved_at_20[0x10];
4847         u8         op_mod[0x10];
4848
4849         u8         reserved_at_40[0x10];
4850         u8         num_of_counters[0x10];
4851
4852         u8         reserved_at_60[0x20];
4853
4854         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4855 };
4856
4857 struct mlx5_ifc_set_monitor_counter_out_bits {
4858         u8         status[0x8];
4859         u8         reserved_at_8[0x18];
4860
4861         u8         syndrome[0x20];
4862
4863         u8         reserved_at_40[0x40];
4864 };
4865
4866 struct mlx5_ifc_query_vport_state_in_bits {
4867         u8         opcode[0x10];
4868         u8         reserved_at_10[0x10];
4869
4870         u8         reserved_at_20[0x10];
4871         u8         op_mod[0x10];
4872
4873         u8         other_vport[0x1];
4874         u8         reserved_at_41[0xf];
4875         u8         vport_number[0x10];
4876
4877         u8         reserved_at_60[0x20];
4878 };
4879
4880 struct mlx5_ifc_query_vnic_env_out_bits {
4881         u8         status[0x8];
4882         u8         reserved_at_8[0x18];
4883
4884         u8         syndrome[0x20];
4885
4886         u8         reserved_at_40[0x40];
4887
4888         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4889 };
4890
4891 enum {
4892         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4893 };
4894
4895 struct mlx5_ifc_query_vnic_env_in_bits {
4896         u8         opcode[0x10];
4897         u8         reserved_at_10[0x10];
4898
4899         u8         reserved_at_20[0x10];
4900         u8         op_mod[0x10];
4901
4902         u8         other_vport[0x1];
4903         u8         reserved_at_41[0xf];
4904         u8         vport_number[0x10];
4905
4906         u8         reserved_at_60[0x20];
4907 };
4908
4909 struct mlx5_ifc_query_vport_counter_out_bits {
4910         u8         status[0x8];
4911         u8         reserved_at_8[0x18];
4912
4913         u8         syndrome[0x20];
4914
4915         u8         reserved_at_40[0x40];
4916
4917         struct mlx5_ifc_traffic_counter_bits received_errors;
4918
4919         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4920
4921         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4922
4923         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4924
4925         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4926
4927         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4928
4929         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4930
4931         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4932
4933         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4934
4935         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4936
4937         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4938
4939         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4940
4941         u8         reserved_at_680[0xa00];
4942 };
4943
4944 enum {
4945         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4946 };
4947
4948 struct mlx5_ifc_query_vport_counter_in_bits {
4949         u8         opcode[0x10];
4950         u8         reserved_at_10[0x10];
4951
4952         u8         reserved_at_20[0x10];
4953         u8         op_mod[0x10];
4954
4955         u8         other_vport[0x1];
4956         u8         reserved_at_41[0xb];
4957         u8         port_num[0x4];
4958         u8         vport_number[0x10];
4959
4960         u8         reserved_at_60[0x60];
4961
4962         u8         clear[0x1];
4963         u8         reserved_at_c1[0x1f];
4964
4965         u8         reserved_at_e0[0x20];
4966 };
4967
4968 struct mlx5_ifc_query_tis_out_bits {
4969         u8         status[0x8];
4970         u8         reserved_at_8[0x18];
4971
4972         u8         syndrome[0x20];
4973
4974         u8         reserved_at_40[0x40];
4975
4976         struct mlx5_ifc_tisc_bits tis_context;
4977 };
4978
4979 struct mlx5_ifc_query_tis_in_bits {
4980         u8         opcode[0x10];
4981         u8         reserved_at_10[0x10];
4982
4983         u8         reserved_at_20[0x10];
4984         u8         op_mod[0x10];
4985
4986         u8         reserved_at_40[0x8];
4987         u8         tisn[0x18];
4988
4989         u8         reserved_at_60[0x20];
4990 };
4991
4992 struct mlx5_ifc_query_tir_out_bits {
4993         u8         status[0x8];
4994         u8         reserved_at_8[0x18];
4995
4996         u8         syndrome[0x20];
4997
4998         u8         reserved_at_40[0xc0];
4999
5000         struct mlx5_ifc_tirc_bits tir_context;
5001 };
5002
5003 struct mlx5_ifc_query_tir_in_bits {
5004         u8         opcode[0x10];
5005         u8         reserved_at_10[0x10];
5006
5007         u8         reserved_at_20[0x10];
5008         u8         op_mod[0x10];
5009
5010         u8         reserved_at_40[0x8];
5011         u8         tirn[0x18];
5012
5013         u8         reserved_at_60[0x20];
5014 };
5015
5016 struct mlx5_ifc_query_srq_out_bits {
5017         u8         status[0x8];
5018         u8         reserved_at_8[0x18];
5019
5020         u8         syndrome[0x20];
5021
5022         u8         reserved_at_40[0x40];
5023
5024         struct mlx5_ifc_srqc_bits srq_context_entry;
5025
5026         u8         reserved_at_280[0x600];
5027
5028         u8         pas[][0x40];
5029 };
5030
5031 struct mlx5_ifc_query_srq_in_bits {
5032         u8         opcode[0x10];
5033         u8         reserved_at_10[0x10];
5034
5035         u8         reserved_at_20[0x10];
5036         u8         op_mod[0x10];
5037
5038         u8         reserved_at_40[0x8];
5039         u8         srqn[0x18];
5040
5041         u8         reserved_at_60[0x20];
5042 };
5043
5044 struct mlx5_ifc_query_sq_out_bits {
5045         u8         status[0x8];
5046         u8         reserved_at_8[0x18];
5047
5048         u8         syndrome[0x20];
5049
5050         u8         reserved_at_40[0xc0];
5051
5052         struct mlx5_ifc_sqc_bits sq_context;
5053 };
5054
5055 struct mlx5_ifc_query_sq_in_bits {
5056         u8         opcode[0x10];
5057         u8         reserved_at_10[0x10];
5058
5059         u8         reserved_at_20[0x10];
5060         u8         op_mod[0x10];
5061
5062         u8         reserved_at_40[0x8];
5063         u8         sqn[0x18];
5064
5065         u8         reserved_at_60[0x20];
5066 };
5067
5068 struct mlx5_ifc_query_special_contexts_out_bits {
5069         u8         status[0x8];
5070         u8         reserved_at_8[0x18];
5071
5072         u8         syndrome[0x20];
5073
5074         u8         dump_fill_mkey[0x20];
5075
5076         u8         resd_lkey[0x20];
5077
5078         u8         null_mkey[0x20];
5079
5080         u8         reserved_at_a0[0x60];
5081 };
5082
5083 struct mlx5_ifc_query_special_contexts_in_bits {
5084         u8         opcode[0x10];
5085         u8         reserved_at_10[0x10];
5086
5087         u8         reserved_at_20[0x10];
5088         u8         op_mod[0x10];
5089
5090         u8         reserved_at_40[0x40];
5091 };
5092
5093 struct mlx5_ifc_query_scheduling_element_out_bits {
5094         u8         opcode[0x10];
5095         u8         reserved_at_10[0x10];
5096
5097         u8         reserved_at_20[0x10];
5098         u8         op_mod[0x10];
5099
5100         u8         reserved_at_40[0xc0];
5101
5102         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5103
5104         u8         reserved_at_300[0x100];
5105 };
5106
5107 enum {
5108         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5109         SCHEDULING_HIERARCHY_NIC = 0x3,
5110 };
5111
5112 struct mlx5_ifc_query_scheduling_element_in_bits {
5113         u8         opcode[0x10];
5114         u8         reserved_at_10[0x10];
5115
5116         u8         reserved_at_20[0x10];
5117         u8         op_mod[0x10];
5118
5119         u8         scheduling_hierarchy[0x8];
5120         u8         reserved_at_48[0x18];
5121
5122         u8         scheduling_element_id[0x20];
5123
5124         u8         reserved_at_80[0x180];
5125 };
5126
5127 struct mlx5_ifc_query_rqt_out_bits {
5128         u8         status[0x8];
5129         u8         reserved_at_8[0x18];
5130
5131         u8         syndrome[0x20];
5132
5133         u8         reserved_at_40[0xc0];
5134
5135         struct mlx5_ifc_rqtc_bits rqt_context;
5136 };
5137
5138 struct mlx5_ifc_query_rqt_in_bits {
5139         u8         opcode[0x10];
5140         u8         reserved_at_10[0x10];
5141
5142         u8         reserved_at_20[0x10];
5143         u8         op_mod[0x10];
5144
5145         u8         reserved_at_40[0x8];
5146         u8         rqtn[0x18];
5147
5148         u8         reserved_at_60[0x20];
5149 };
5150
5151 struct mlx5_ifc_query_rq_out_bits {
5152         u8         status[0x8];
5153         u8         reserved_at_8[0x18];
5154
5155         u8         syndrome[0x20];
5156
5157         u8         reserved_at_40[0xc0];
5158
5159         struct mlx5_ifc_rqc_bits rq_context;
5160 };
5161
5162 struct mlx5_ifc_query_rq_in_bits {
5163         u8         opcode[0x10];
5164         u8         reserved_at_10[0x10];
5165
5166         u8         reserved_at_20[0x10];
5167         u8         op_mod[0x10];
5168
5169         u8         reserved_at_40[0x8];
5170         u8         rqn[0x18];
5171
5172         u8         reserved_at_60[0x20];
5173 };
5174
5175 struct mlx5_ifc_query_roce_address_out_bits {
5176         u8         status[0x8];
5177         u8         reserved_at_8[0x18];
5178
5179         u8         syndrome[0x20];
5180
5181         u8         reserved_at_40[0x40];
5182
5183         struct mlx5_ifc_roce_addr_layout_bits roce_address;
5184 };
5185
5186 struct mlx5_ifc_query_roce_address_in_bits {
5187         u8         opcode[0x10];
5188         u8         reserved_at_10[0x10];
5189
5190         u8         reserved_at_20[0x10];
5191         u8         op_mod[0x10];
5192
5193         u8         roce_address_index[0x10];
5194         u8         reserved_at_50[0xc];
5195         u8         vhca_port_num[0x4];
5196
5197         u8         reserved_at_60[0x20];
5198 };
5199
5200 struct mlx5_ifc_query_rmp_out_bits {
5201         u8         status[0x8];
5202         u8         reserved_at_8[0x18];
5203
5204         u8         syndrome[0x20];
5205
5206         u8         reserved_at_40[0xc0];
5207
5208         struct mlx5_ifc_rmpc_bits rmp_context;
5209 };
5210
5211 struct mlx5_ifc_query_rmp_in_bits {
5212         u8         opcode[0x10];
5213         u8         reserved_at_10[0x10];
5214
5215         u8         reserved_at_20[0x10];
5216         u8         op_mod[0x10];
5217
5218         u8         reserved_at_40[0x8];
5219         u8         rmpn[0x18];
5220
5221         u8         reserved_at_60[0x20];
5222 };
5223
5224 struct mlx5_ifc_query_qp_out_bits {
5225         u8         status[0x8];
5226         u8         reserved_at_8[0x18];
5227
5228         u8         syndrome[0x20];
5229
5230         u8         reserved_at_40[0x40];
5231
5232         u8         opt_param_mask[0x20];
5233
5234         u8         ece[0x20];
5235
5236         struct mlx5_ifc_qpc_bits qpc;
5237
5238         u8         reserved_at_800[0x80];
5239
5240         u8         pas[][0x40];
5241 };
5242
5243 struct mlx5_ifc_query_qp_in_bits {
5244         u8         opcode[0x10];
5245         u8         reserved_at_10[0x10];
5246
5247         u8         reserved_at_20[0x10];
5248         u8         op_mod[0x10];
5249
5250         u8         reserved_at_40[0x8];
5251         u8         qpn[0x18];
5252
5253         u8         reserved_at_60[0x20];
5254 };
5255
5256 struct mlx5_ifc_query_q_counter_out_bits {
5257         u8         status[0x8];
5258         u8         reserved_at_8[0x18];
5259
5260         u8         syndrome[0x20];
5261
5262         u8         reserved_at_40[0x40];
5263
5264         u8         rx_write_requests[0x20];
5265
5266         u8         reserved_at_a0[0x20];
5267
5268         u8         rx_read_requests[0x20];
5269
5270         u8         reserved_at_e0[0x20];
5271
5272         u8         rx_atomic_requests[0x20];
5273
5274         u8         reserved_at_120[0x20];
5275
5276         u8         rx_dct_connect[0x20];
5277
5278         u8         reserved_at_160[0x20];
5279
5280         u8         out_of_buffer[0x20];
5281
5282         u8         reserved_at_1a0[0x20];
5283
5284         u8         out_of_sequence[0x20];
5285
5286         u8         reserved_at_1e0[0x20];
5287
5288         u8         duplicate_request[0x20];
5289
5290         u8         reserved_at_220[0x20];
5291
5292         u8         rnr_nak_retry_err[0x20];
5293
5294         u8         reserved_at_260[0x20];
5295
5296         u8         packet_seq_err[0x20];
5297
5298         u8         reserved_at_2a0[0x20];
5299
5300         u8         implied_nak_seq_err[0x20];
5301
5302         u8         reserved_at_2e0[0x20];
5303
5304         u8         local_ack_timeout_err[0x20];
5305
5306         u8         reserved_at_320[0xa0];
5307
5308         u8         resp_local_length_error[0x20];
5309
5310         u8         req_local_length_error[0x20];
5311
5312         u8         resp_local_qp_error[0x20];
5313
5314         u8         local_operation_error[0x20];
5315
5316         u8         resp_local_protection[0x20];
5317
5318         u8         req_local_protection[0x20];
5319
5320         u8         resp_cqe_error[0x20];
5321
5322         u8         req_cqe_error[0x20];
5323
5324         u8         req_mw_binding[0x20];
5325
5326         u8         req_bad_response[0x20];
5327
5328         u8         req_remote_invalid_request[0x20];
5329
5330         u8         resp_remote_invalid_request[0x20];
5331
5332         u8         req_remote_access_errors[0x20];
5333
5334         u8         resp_remote_access_errors[0x20];
5335
5336         u8         req_remote_operation_errors[0x20];
5337
5338         u8         req_transport_retries_exceeded[0x20];
5339
5340         u8         cq_overflow[0x20];
5341
5342         u8         resp_cqe_flush_error[0x20];
5343
5344         u8         req_cqe_flush_error[0x20];
5345
5346         u8         reserved_at_620[0x20];
5347
5348         u8         roce_adp_retrans[0x20];
5349
5350         u8         roce_adp_retrans_to[0x20];
5351
5352         u8         roce_slow_restart[0x20];
5353
5354         u8         roce_slow_restart_cnps[0x20];
5355
5356         u8         roce_slow_restart_trans[0x20];
5357
5358         u8         reserved_at_6e0[0x120];
5359 };
5360
5361 struct mlx5_ifc_query_q_counter_in_bits {
5362         u8         opcode[0x10];
5363         u8         reserved_at_10[0x10];
5364
5365         u8         reserved_at_20[0x10];
5366         u8         op_mod[0x10];
5367
5368         u8         reserved_at_40[0x80];
5369
5370         u8         clear[0x1];
5371         u8         reserved_at_c1[0x1f];
5372
5373         u8         reserved_at_e0[0x18];
5374         u8         counter_set_id[0x8];
5375 };
5376
5377 struct mlx5_ifc_query_pages_out_bits {
5378         u8         status[0x8];
5379         u8         reserved_at_8[0x18];
5380
5381         u8         syndrome[0x20];
5382
5383         u8         embedded_cpu_function[0x1];
5384         u8         reserved_at_41[0xf];
5385         u8         function_id[0x10];
5386
5387         u8         num_pages[0x20];
5388 };
5389
5390 enum {
5391         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5392         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5393         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5394 };
5395
5396 struct mlx5_ifc_query_pages_in_bits {
5397         u8         opcode[0x10];
5398         u8         reserved_at_10[0x10];
5399
5400         u8         reserved_at_20[0x10];
5401         u8         op_mod[0x10];
5402
5403         u8         embedded_cpu_function[0x1];
5404         u8         reserved_at_41[0xf];
5405         u8         function_id[0x10];
5406
5407         u8         reserved_at_60[0x20];
5408 };
5409
5410 struct mlx5_ifc_query_nic_vport_context_out_bits {
5411         u8         status[0x8];
5412         u8         reserved_at_8[0x18];
5413
5414         u8         syndrome[0x20];
5415
5416         u8         reserved_at_40[0x40];
5417
5418         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5419 };
5420
5421 struct mlx5_ifc_query_nic_vport_context_in_bits {
5422         u8         opcode[0x10];
5423         u8         reserved_at_10[0x10];
5424
5425         u8         reserved_at_20[0x10];
5426         u8         op_mod[0x10];
5427
5428         u8         other_vport[0x1];
5429         u8         reserved_at_41[0xf];
5430         u8         vport_number[0x10];
5431
5432         u8         reserved_at_60[0x5];
5433         u8         allowed_list_type[0x3];
5434         u8         reserved_at_68[0x18];
5435 };
5436
5437 struct mlx5_ifc_query_mkey_out_bits {
5438         u8         status[0x8];
5439         u8         reserved_at_8[0x18];
5440
5441         u8         syndrome[0x20];
5442
5443         u8         reserved_at_40[0x40];
5444
5445         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5446
5447         u8         reserved_at_280[0x600];
5448
5449         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5450
5451         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5452 };
5453
5454 struct mlx5_ifc_query_mkey_in_bits {
5455         u8         opcode[0x10];
5456         u8         reserved_at_10[0x10];
5457
5458         u8         reserved_at_20[0x10];
5459         u8         op_mod[0x10];
5460
5461         u8         reserved_at_40[0x8];
5462         u8         mkey_index[0x18];
5463
5464         u8         pg_access[0x1];
5465         u8         reserved_at_61[0x1f];
5466 };
5467
5468 struct mlx5_ifc_query_mad_demux_out_bits {
5469         u8         status[0x8];
5470         u8         reserved_at_8[0x18];
5471
5472         u8         syndrome[0x20];
5473
5474         u8         reserved_at_40[0x40];
5475
5476         u8         mad_dumux_parameters_block[0x20];
5477 };
5478
5479 struct mlx5_ifc_query_mad_demux_in_bits {
5480         u8         opcode[0x10];
5481         u8         reserved_at_10[0x10];
5482
5483         u8         reserved_at_20[0x10];
5484         u8         op_mod[0x10];
5485
5486         u8         reserved_at_40[0x40];
5487 };
5488
5489 struct mlx5_ifc_query_l2_table_entry_out_bits {
5490         u8         status[0x8];
5491         u8         reserved_at_8[0x18];
5492
5493         u8         syndrome[0x20];
5494
5495         u8         reserved_at_40[0xa0];
5496
5497         u8         reserved_at_e0[0x13];
5498         u8         vlan_valid[0x1];
5499         u8         vlan[0xc];
5500
5501         struct mlx5_ifc_mac_address_layout_bits mac_address;
5502
5503         u8         reserved_at_140[0xc0];
5504 };
5505
5506 struct mlx5_ifc_query_l2_table_entry_in_bits {
5507         u8         opcode[0x10];
5508         u8         reserved_at_10[0x10];
5509
5510         u8         reserved_at_20[0x10];
5511         u8         op_mod[0x10];
5512
5513         u8         reserved_at_40[0x60];
5514
5515         u8         reserved_at_a0[0x8];
5516         u8         table_index[0x18];
5517
5518         u8         reserved_at_c0[0x140];
5519 };
5520
5521 struct mlx5_ifc_query_issi_out_bits {
5522         u8         status[0x8];
5523         u8         reserved_at_8[0x18];
5524
5525         u8         syndrome[0x20];
5526
5527         u8         reserved_at_40[0x10];
5528         u8         current_issi[0x10];
5529
5530         u8         reserved_at_60[0xa0];
5531
5532         u8         reserved_at_100[76][0x8];
5533         u8         supported_issi_dw0[0x20];
5534 };
5535
5536 struct mlx5_ifc_query_issi_in_bits {
5537         u8         opcode[0x10];
5538         u8         reserved_at_10[0x10];
5539
5540         u8         reserved_at_20[0x10];
5541         u8         op_mod[0x10];
5542
5543         u8         reserved_at_40[0x40];
5544 };
5545
5546 struct mlx5_ifc_set_driver_version_out_bits {
5547         u8         status[0x8];
5548         u8         reserved_0[0x18];
5549
5550         u8         syndrome[0x20];
5551         u8         reserved_1[0x40];
5552 };
5553
5554 struct mlx5_ifc_set_driver_version_in_bits {
5555         u8         opcode[0x10];
5556         u8         reserved_0[0x10];
5557
5558         u8         reserved_1[0x10];
5559         u8         op_mod[0x10];
5560
5561         u8         reserved_2[0x40];
5562         u8         driver_version[64][0x8];
5563 };
5564
5565 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5566         u8         status[0x8];
5567         u8         reserved_at_8[0x18];
5568
5569         u8         syndrome[0x20];
5570
5571         u8         reserved_at_40[0x40];
5572
5573         struct mlx5_ifc_pkey_bits pkey[];
5574 };
5575
5576 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5577         u8         opcode[0x10];
5578         u8         reserved_at_10[0x10];
5579
5580         u8         reserved_at_20[0x10];
5581         u8         op_mod[0x10];
5582
5583         u8         other_vport[0x1];
5584         u8         reserved_at_41[0xb];
5585         u8         port_num[0x4];
5586         u8         vport_number[0x10];
5587
5588         u8         reserved_at_60[0x10];
5589         u8         pkey_index[0x10];
5590 };
5591
5592 enum {
5593         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5594         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5595         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5596 };
5597
5598 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5599         u8         status[0x8];
5600         u8         reserved_at_8[0x18];
5601
5602         u8         syndrome[0x20];
5603
5604         u8         reserved_at_40[0x20];
5605
5606         u8         gids_num[0x10];
5607         u8         reserved_at_70[0x10];
5608
5609         struct mlx5_ifc_array128_auto_bits gid[];
5610 };
5611
5612 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5613         u8         opcode[0x10];
5614         u8         reserved_at_10[0x10];
5615
5616         u8         reserved_at_20[0x10];
5617         u8         op_mod[0x10];
5618
5619         u8         other_vport[0x1];
5620         u8         reserved_at_41[0xb];
5621         u8         port_num[0x4];
5622         u8         vport_number[0x10];
5623
5624         u8         reserved_at_60[0x10];
5625         u8         gid_index[0x10];
5626 };
5627
5628 struct mlx5_ifc_query_hca_vport_context_out_bits {
5629         u8         status[0x8];
5630         u8         reserved_at_8[0x18];
5631
5632         u8         syndrome[0x20];
5633
5634         u8         reserved_at_40[0x40];
5635
5636         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5637 };
5638
5639 struct mlx5_ifc_query_hca_vport_context_in_bits {
5640         u8         opcode[0x10];
5641         u8         reserved_at_10[0x10];
5642
5643         u8         reserved_at_20[0x10];
5644         u8         op_mod[0x10];
5645
5646         u8         other_vport[0x1];
5647         u8         reserved_at_41[0xb];
5648         u8         port_num[0x4];
5649         u8         vport_number[0x10];
5650
5651         u8         reserved_at_60[0x20];
5652 };
5653
5654 struct mlx5_ifc_query_hca_cap_out_bits {
5655         u8         status[0x8];
5656         u8         reserved_at_8[0x18];
5657
5658         u8         syndrome[0x20];
5659
5660         u8         reserved_at_40[0x40];
5661
5662         union mlx5_ifc_hca_cap_union_bits capability;
5663 };
5664
5665 struct mlx5_ifc_query_hca_cap_in_bits {
5666         u8         opcode[0x10];
5667         u8         reserved_at_10[0x10];
5668
5669         u8         reserved_at_20[0x10];
5670         u8         op_mod[0x10];
5671
5672         u8         other_function[0x1];
5673         u8         reserved_at_41[0xf];
5674         u8         function_id[0x10];
5675
5676         u8         reserved_at_60[0x20];
5677 };
5678
5679 struct mlx5_ifc_other_hca_cap_bits {
5680         u8         roce[0x1];
5681         u8         reserved_at_1[0x27f];
5682 };
5683
5684 struct mlx5_ifc_query_other_hca_cap_out_bits {
5685         u8         status[0x8];
5686         u8         reserved_at_8[0x18];
5687
5688         u8         syndrome[0x20];
5689
5690         u8         reserved_at_40[0x40];
5691
5692         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5693 };
5694
5695 struct mlx5_ifc_query_other_hca_cap_in_bits {
5696         u8         opcode[0x10];
5697         u8         reserved_at_10[0x10];
5698
5699         u8         reserved_at_20[0x10];
5700         u8         op_mod[0x10];
5701
5702         u8         reserved_at_40[0x10];
5703         u8         function_id[0x10];
5704
5705         u8         reserved_at_60[0x20];
5706 };
5707
5708 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5709         u8         status[0x8];
5710         u8         reserved_at_8[0x18];
5711
5712         u8         syndrome[0x20];
5713
5714         u8         reserved_at_40[0x40];
5715 };
5716
5717 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5718         u8         opcode[0x10];
5719         u8         reserved_at_10[0x10];
5720
5721         u8         reserved_at_20[0x10];
5722         u8         op_mod[0x10];
5723
5724         u8         reserved_at_40[0x10];
5725         u8         function_id[0x10];
5726         u8         field_select[0x20];
5727
5728         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5729 };
5730
5731 struct mlx5_ifc_flow_table_context_bits {
5732         u8         reformat_en[0x1];
5733         u8         decap_en[0x1];
5734         u8         sw_owner[0x1];
5735         u8         termination_table[0x1];
5736         u8         table_miss_action[0x4];
5737         u8         level[0x8];
5738         u8         reserved_at_10[0x8];
5739         u8         log_size[0x8];
5740
5741         u8         reserved_at_20[0x8];
5742         u8         table_miss_id[0x18];
5743
5744         u8         reserved_at_40[0x8];
5745         u8         lag_master_next_table_id[0x18];
5746
5747         u8         reserved_at_60[0x60];
5748
5749         u8         sw_owner_icm_root_1[0x40];
5750
5751         u8         sw_owner_icm_root_0[0x40];
5752
5753 };
5754
5755 struct mlx5_ifc_query_flow_table_out_bits {
5756         u8         status[0x8];
5757         u8         reserved_at_8[0x18];
5758
5759         u8         syndrome[0x20];
5760
5761         u8         reserved_at_40[0x80];
5762
5763         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5764 };
5765
5766 struct mlx5_ifc_query_flow_table_in_bits {
5767         u8         opcode[0x10];
5768         u8         reserved_at_10[0x10];
5769
5770         u8         reserved_at_20[0x10];
5771         u8         op_mod[0x10];
5772
5773         u8         reserved_at_40[0x40];
5774
5775         u8         table_type[0x8];
5776         u8         reserved_at_88[0x18];
5777
5778         u8         reserved_at_a0[0x8];
5779         u8         table_id[0x18];
5780
5781         u8         reserved_at_c0[0x140];
5782 };
5783
5784 struct mlx5_ifc_query_fte_out_bits {
5785         u8         status[0x8];
5786         u8         reserved_at_8[0x18];
5787
5788         u8         syndrome[0x20];
5789
5790         u8         reserved_at_40[0x1c0];
5791
5792         struct mlx5_ifc_flow_context_bits flow_context;
5793 };
5794
5795 struct mlx5_ifc_query_fte_in_bits {
5796         u8         opcode[0x10];
5797         u8         reserved_at_10[0x10];
5798
5799         u8         reserved_at_20[0x10];
5800         u8         op_mod[0x10];
5801
5802         u8         reserved_at_40[0x40];
5803
5804         u8         table_type[0x8];
5805         u8         reserved_at_88[0x18];
5806
5807         u8         reserved_at_a0[0x8];
5808         u8         table_id[0x18];
5809
5810         u8         reserved_at_c0[0x40];
5811
5812         u8         flow_index[0x20];
5813
5814         u8         reserved_at_120[0xe0];
5815 };
5816
5817 struct mlx5_ifc_match_definer_format_0_bits {
5818         u8         reserved_at_0[0x100];
5819
5820         u8         metadata_reg_c_0[0x20];
5821
5822         u8         metadata_reg_c_1[0x20];
5823
5824         u8         outer_dmac_47_16[0x20];
5825
5826         u8         outer_dmac_15_0[0x10];
5827         u8         outer_ethertype[0x10];
5828
5829         u8         reserved_at_180[0x1];
5830         u8         sx_sniffer[0x1];
5831         u8         functional_lb[0x1];
5832         u8         outer_ip_frag[0x1];
5833         u8         outer_qp_type[0x2];
5834         u8         outer_encap_type[0x2];
5835         u8         port_number[0x2];
5836         u8         outer_l3_type[0x2];
5837         u8         outer_l4_type[0x2];
5838         u8         outer_first_vlan_type[0x2];
5839         u8         outer_first_vlan_prio[0x3];
5840         u8         outer_first_vlan_cfi[0x1];
5841         u8         outer_first_vlan_vid[0xc];
5842
5843         u8         outer_l4_type_ext[0x4];
5844         u8         reserved_at_1a4[0x2];
5845         u8         outer_ipsec_layer[0x2];
5846         u8         outer_l2_type[0x2];
5847         u8         force_lb[0x1];
5848         u8         outer_l2_ok[0x1];
5849         u8         outer_l3_ok[0x1];
5850         u8         outer_l4_ok[0x1];
5851         u8         outer_second_vlan_type[0x2];
5852         u8         outer_second_vlan_prio[0x3];
5853         u8         outer_second_vlan_cfi[0x1];
5854         u8         outer_second_vlan_vid[0xc];
5855
5856         u8         outer_smac_47_16[0x20];
5857
5858         u8         outer_smac_15_0[0x10];
5859         u8         inner_ipv4_checksum_ok[0x1];
5860         u8         inner_l4_checksum_ok[0x1];
5861         u8         outer_ipv4_checksum_ok[0x1];
5862         u8         outer_l4_checksum_ok[0x1];
5863         u8         inner_l3_ok[0x1];
5864         u8         inner_l4_ok[0x1];
5865         u8         outer_l3_ok_duplicate[0x1];
5866         u8         outer_l4_ok_duplicate[0x1];
5867         u8         outer_tcp_cwr[0x1];
5868         u8         outer_tcp_ece[0x1];
5869         u8         outer_tcp_urg[0x1];
5870         u8         outer_tcp_ack[0x1];
5871         u8         outer_tcp_psh[0x1];
5872         u8         outer_tcp_rst[0x1];
5873         u8         outer_tcp_syn[0x1];
5874         u8         outer_tcp_fin[0x1];
5875 };
5876
5877 struct mlx5_ifc_match_definer_format_22_bits {
5878         u8         reserved_at_0[0x100];
5879
5880         u8         outer_ip_src_addr[0x20];
5881
5882         u8         outer_ip_dest_addr[0x20];
5883
5884         u8         outer_l4_sport[0x10];
5885         u8         outer_l4_dport[0x10];
5886
5887         u8         reserved_at_160[0x1];
5888         u8         sx_sniffer[0x1];
5889         u8         functional_lb[0x1];
5890         u8         outer_ip_frag[0x1];
5891         u8         outer_qp_type[0x2];
5892         u8         outer_encap_type[0x2];
5893         u8         port_number[0x2];
5894         u8         outer_l3_type[0x2];
5895         u8         outer_l4_type[0x2];
5896         u8         outer_first_vlan_type[0x2];
5897         u8         outer_first_vlan_prio[0x3];
5898         u8         outer_first_vlan_cfi[0x1];
5899         u8         outer_first_vlan_vid[0xc];
5900
5901         u8         metadata_reg_c_0[0x20];
5902
5903         u8         outer_dmac_47_16[0x20];
5904
5905         u8         outer_smac_47_16[0x20];
5906
5907         u8         outer_smac_15_0[0x10];
5908         u8         outer_dmac_15_0[0x10];
5909 };
5910
5911 struct mlx5_ifc_match_definer_format_23_bits {
5912         u8         reserved_at_0[0x100];
5913
5914         u8         inner_ip_src_addr[0x20];
5915
5916         u8         inner_ip_dest_addr[0x20];
5917
5918         u8         inner_l4_sport[0x10];
5919         u8         inner_l4_dport[0x10];
5920
5921         u8         reserved_at_160[0x1];
5922         u8         sx_sniffer[0x1];
5923         u8         functional_lb[0x1];
5924         u8         inner_ip_frag[0x1];
5925         u8         inner_qp_type[0x2];
5926         u8         inner_encap_type[0x2];
5927         u8         port_number[0x2];
5928         u8         inner_l3_type[0x2];
5929         u8         inner_l4_type[0x2];
5930         u8         inner_first_vlan_type[0x2];
5931         u8         inner_first_vlan_prio[0x3];
5932         u8         inner_first_vlan_cfi[0x1];
5933         u8         inner_first_vlan_vid[0xc];
5934
5935         u8         tunnel_header_0[0x20];
5936
5937         u8         inner_dmac_47_16[0x20];
5938
5939         u8         inner_smac_47_16[0x20];
5940
5941         u8         inner_smac_15_0[0x10];
5942         u8         inner_dmac_15_0[0x10];
5943 };
5944
5945 struct mlx5_ifc_match_definer_format_29_bits {
5946         u8         reserved_at_0[0xc0];
5947
5948         u8         outer_ip_dest_addr[0x80];
5949
5950         u8         outer_ip_src_addr[0x80];
5951
5952         u8         outer_l4_sport[0x10];
5953         u8         outer_l4_dport[0x10];
5954
5955         u8         reserved_at_1e0[0x20];
5956 };
5957
5958 struct mlx5_ifc_match_definer_format_30_bits {
5959         u8         reserved_at_0[0xa0];
5960
5961         u8         outer_ip_dest_addr[0x80];
5962
5963         u8         outer_ip_src_addr[0x80];
5964
5965         u8         outer_dmac_47_16[0x20];
5966
5967         u8         outer_smac_47_16[0x20];
5968
5969         u8         outer_smac_15_0[0x10];
5970         u8         outer_dmac_15_0[0x10];
5971 };
5972
5973 struct mlx5_ifc_match_definer_format_31_bits {
5974         u8         reserved_at_0[0xc0];
5975
5976         u8         inner_ip_dest_addr[0x80];
5977
5978         u8         inner_ip_src_addr[0x80];
5979
5980         u8         inner_l4_sport[0x10];
5981         u8         inner_l4_dport[0x10];
5982
5983         u8         reserved_at_1e0[0x20];
5984 };
5985
5986 struct mlx5_ifc_match_definer_format_32_bits {
5987         u8         reserved_at_0[0xa0];
5988
5989         u8         inner_ip_dest_addr[0x80];
5990
5991         u8         inner_ip_src_addr[0x80];
5992
5993         u8         inner_dmac_47_16[0x20];
5994
5995         u8         inner_smac_47_16[0x20];
5996
5997         u8         inner_smac_15_0[0x10];
5998         u8         inner_dmac_15_0[0x10];
5999 };
6000
6001 struct mlx5_ifc_match_definer_bits {
6002         u8         modify_field_select[0x40];
6003
6004         u8         reserved_at_40[0x40];
6005
6006         u8         reserved_at_80[0x10];
6007         u8         format_id[0x10];
6008
6009         u8         reserved_at_a0[0x160];
6010
6011         u8         match_mask[16][0x20];
6012 };
6013
6014 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6015         u8         opcode[0x10];
6016         u8         uid[0x10];
6017
6018         u8         vhca_tunnel_id[0x10];
6019         u8         obj_type[0x10];
6020
6021         u8         obj_id[0x20];
6022
6023         u8         reserved_at_60[0x3];
6024         u8         log_obj_range[0x5];
6025         u8         reserved_at_68[0x18];
6026 };
6027
6028 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6029         u8         status[0x8];
6030         u8         reserved_at_8[0x18];
6031
6032         u8         syndrome[0x20];
6033
6034         u8         obj_id[0x20];
6035
6036         u8         reserved_at_60[0x20];
6037 };
6038
6039 struct mlx5_ifc_create_match_definer_in_bits {
6040         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6041
6042         struct mlx5_ifc_match_definer_bits obj_context;
6043 };
6044
6045 struct mlx5_ifc_create_match_definer_out_bits {
6046         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6047 };
6048
6049 enum {
6050         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6051         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6052         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6053         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6054         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6055         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6056         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6057 };
6058
6059 struct mlx5_ifc_query_flow_group_out_bits {
6060         u8         status[0x8];
6061         u8         reserved_at_8[0x18];
6062
6063         u8         syndrome[0x20];
6064
6065         u8         reserved_at_40[0xa0];
6066
6067         u8         start_flow_index[0x20];
6068
6069         u8         reserved_at_100[0x20];
6070
6071         u8         end_flow_index[0x20];
6072
6073         u8         reserved_at_140[0xa0];
6074
6075         u8         reserved_at_1e0[0x18];
6076         u8         match_criteria_enable[0x8];
6077
6078         struct mlx5_ifc_fte_match_param_bits match_criteria;
6079
6080         u8         reserved_at_1200[0xe00];
6081 };
6082
6083 struct mlx5_ifc_query_flow_group_in_bits {
6084         u8         opcode[0x10];
6085         u8         reserved_at_10[0x10];
6086
6087         u8         reserved_at_20[0x10];
6088         u8         op_mod[0x10];
6089
6090         u8         reserved_at_40[0x40];
6091
6092         u8         table_type[0x8];
6093         u8         reserved_at_88[0x18];
6094
6095         u8         reserved_at_a0[0x8];
6096         u8         table_id[0x18];
6097
6098         u8         group_id[0x20];
6099
6100         u8         reserved_at_e0[0x120];
6101 };
6102
6103 struct mlx5_ifc_query_flow_counter_out_bits {
6104         u8         status[0x8];
6105         u8         reserved_at_8[0x18];
6106
6107         u8         syndrome[0x20];
6108
6109         u8         reserved_at_40[0x40];
6110
6111         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6112 };
6113
6114 struct mlx5_ifc_query_flow_counter_in_bits {
6115         u8         opcode[0x10];
6116         u8         reserved_at_10[0x10];
6117
6118         u8         reserved_at_20[0x10];
6119         u8         op_mod[0x10];
6120
6121         u8         reserved_at_40[0x80];
6122
6123         u8         clear[0x1];
6124         u8         reserved_at_c1[0xf];
6125         u8         num_of_counters[0x10];
6126
6127         u8         flow_counter_id[0x20];
6128 };
6129
6130 struct mlx5_ifc_query_esw_vport_context_out_bits {
6131         u8         status[0x8];
6132         u8         reserved_at_8[0x18];
6133
6134         u8         syndrome[0x20];
6135
6136         u8         reserved_at_40[0x40];
6137
6138         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6139 };
6140
6141 struct mlx5_ifc_query_esw_vport_context_in_bits {
6142         u8         opcode[0x10];
6143         u8         reserved_at_10[0x10];
6144
6145         u8         reserved_at_20[0x10];
6146         u8         op_mod[0x10];
6147
6148         u8         other_vport[0x1];
6149         u8         reserved_at_41[0xf];
6150         u8         vport_number[0x10];
6151
6152         u8         reserved_at_60[0x20];
6153 };
6154
6155 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6156         u8         status[0x8];
6157         u8         reserved_at_8[0x18];
6158
6159         u8         syndrome[0x20];
6160
6161         u8         reserved_at_40[0x40];
6162 };
6163
6164 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6165         u8         reserved_at_0[0x1b];
6166         u8         fdb_to_vport_reg_c_id[0x1];
6167         u8         vport_cvlan_insert[0x1];
6168         u8         vport_svlan_insert[0x1];
6169         u8         vport_cvlan_strip[0x1];
6170         u8         vport_svlan_strip[0x1];
6171 };
6172
6173 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6174         u8         opcode[0x10];
6175         u8         reserved_at_10[0x10];
6176
6177         u8         reserved_at_20[0x10];
6178         u8         op_mod[0x10];
6179
6180         u8         other_vport[0x1];
6181         u8         reserved_at_41[0xf];
6182         u8         vport_number[0x10];
6183
6184         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6185
6186         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6187 };
6188
6189 struct mlx5_ifc_query_eq_out_bits {
6190         u8         status[0x8];
6191         u8         reserved_at_8[0x18];
6192
6193         u8         syndrome[0x20];
6194
6195         u8         reserved_at_40[0x40];
6196
6197         struct mlx5_ifc_eqc_bits eq_context_entry;
6198
6199         u8         reserved_at_280[0x40];
6200
6201         u8         event_bitmask[0x40];
6202
6203         u8         reserved_at_300[0x580];
6204
6205         u8         pas[][0x40];
6206 };
6207
6208 struct mlx5_ifc_query_eq_in_bits {
6209         u8         opcode[0x10];
6210         u8         reserved_at_10[0x10];
6211
6212         u8         reserved_at_20[0x10];
6213         u8         op_mod[0x10];
6214
6215         u8         reserved_at_40[0x18];
6216         u8         eq_number[0x8];
6217
6218         u8         reserved_at_60[0x20];
6219 };
6220
6221 struct mlx5_ifc_packet_reformat_context_in_bits {
6222         u8         reformat_type[0x8];
6223         u8         reserved_at_8[0x4];
6224         u8         reformat_param_0[0x4];
6225         u8         reserved_at_10[0x6];
6226         u8         reformat_data_size[0xa];
6227
6228         u8         reformat_param_1[0x8];
6229         u8         reserved_at_28[0x8];
6230         u8         reformat_data[2][0x8];
6231
6232         u8         more_reformat_data[][0x8];
6233 };
6234
6235 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6236         u8         status[0x8];
6237         u8         reserved_at_8[0x18];
6238
6239         u8         syndrome[0x20];
6240
6241         u8         reserved_at_40[0xa0];
6242
6243         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6244 };
6245
6246 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6247         u8         opcode[0x10];
6248         u8         reserved_at_10[0x10];
6249
6250         u8         reserved_at_20[0x10];
6251         u8         op_mod[0x10];
6252
6253         u8         packet_reformat_id[0x20];
6254
6255         u8         reserved_at_60[0xa0];
6256 };
6257
6258 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6259         u8         status[0x8];
6260         u8         reserved_at_8[0x18];
6261
6262         u8         syndrome[0x20];
6263
6264         u8         packet_reformat_id[0x20];
6265
6266         u8         reserved_at_60[0x20];
6267 };
6268
6269 enum {
6270         MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6271         MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6272         MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6273 };
6274
6275 enum mlx5_reformat_ctx_type {
6276         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6277         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6278         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6279         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6280         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6281         MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6282         MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6283 };
6284
6285 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6286         u8         opcode[0x10];
6287         u8         reserved_at_10[0x10];
6288
6289         u8         reserved_at_20[0x10];
6290         u8         op_mod[0x10];
6291
6292         u8         reserved_at_40[0xa0];
6293
6294         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6295 };
6296
6297 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6298         u8         status[0x8];
6299         u8         reserved_at_8[0x18];
6300
6301         u8         syndrome[0x20];
6302
6303         u8         reserved_at_40[0x40];
6304 };
6305
6306 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6307         u8         opcode[0x10];
6308         u8         reserved_at_10[0x10];
6309
6310         u8         reserved_20[0x10];
6311         u8         op_mod[0x10];
6312
6313         u8         packet_reformat_id[0x20];
6314
6315         u8         reserved_60[0x20];
6316 };
6317
6318 struct mlx5_ifc_set_action_in_bits {
6319         u8         action_type[0x4];
6320         u8         field[0xc];
6321         u8         reserved_at_10[0x3];
6322         u8         offset[0x5];
6323         u8         reserved_at_18[0x3];
6324         u8         length[0x5];
6325
6326         u8         data[0x20];
6327 };
6328
6329 struct mlx5_ifc_add_action_in_bits {
6330         u8         action_type[0x4];
6331         u8         field[0xc];
6332         u8         reserved_at_10[0x10];
6333
6334         u8         data[0x20];
6335 };
6336
6337 struct mlx5_ifc_copy_action_in_bits {
6338         u8         action_type[0x4];
6339         u8         src_field[0xc];
6340         u8         reserved_at_10[0x3];
6341         u8         src_offset[0x5];
6342         u8         reserved_at_18[0x3];
6343         u8         length[0x5];
6344
6345         u8         reserved_at_20[0x4];
6346         u8         dst_field[0xc];
6347         u8         reserved_at_30[0x3];
6348         u8         dst_offset[0x5];
6349         u8         reserved_at_38[0x8];
6350 };
6351
6352 union mlx5_ifc_set_add_copy_action_in_auto_bits {
6353         struct mlx5_ifc_set_action_in_bits  set_action_in;
6354         struct mlx5_ifc_add_action_in_bits  add_action_in;
6355         struct mlx5_ifc_copy_action_in_bits copy_action_in;
6356         u8         reserved_at_0[0x40];
6357 };
6358
6359 enum {
6360         MLX5_ACTION_TYPE_SET   = 0x1,
6361         MLX5_ACTION_TYPE_ADD   = 0x2,
6362         MLX5_ACTION_TYPE_COPY  = 0x3,
6363 };
6364
6365 enum {
6366         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
6367         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
6368         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
6369         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
6370         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
6371         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
6372         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
6373         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
6374         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
6375         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
6376         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
6377         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
6378         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
6379         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
6380         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
6381         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
6382         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
6383         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
6384         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
6385         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
6386         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
6387         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
6388         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
6389         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6390         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
6391         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
6392         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
6393         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
6394         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
6395         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6396         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6397         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6398         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6399         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6400         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6401         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6402         MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6403         MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6404         MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6405 };
6406
6407 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6408         u8         status[0x8];
6409         u8         reserved_at_8[0x18];
6410
6411         u8         syndrome[0x20];
6412
6413         u8         modify_header_id[0x20];
6414
6415         u8         reserved_at_60[0x20];
6416 };
6417
6418 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6419         u8         opcode[0x10];
6420         u8         reserved_at_10[0x10];
6421
6422         u8         reserved_at_20[0x10];
6423         u8         op_mod[0x10];
6424
6425         u8         reserved_at_40[0x20];
6426
6427         u8         table_type[0x8];
6428         u8         reserved_at_68[0x10];
6429         u8         num_of_actions[0x8];
6430
6431         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6432 };
6433
6434 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6435         u8         status[0x8];
6436         u8         reserved_at_8[0x18];
6437
6438         u8         syndrome[0x20];
6439
6440         u8         reserved_at_40[0x40];
6441 };
6442
6443 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6444         u8         opcode[0x10];
6445         u8         reserved_at_10[0x10];
6446
6447         u8         reserved_at_20[0x10];
6448         u8         op_mod[0x10];
6449
6450         u8         modify_header_id[0x20];
6451
6452         u8         reserved_at_60[0x20];
6453 };
6454
6455 struct mlx5_ifc_query_modify_header_context_in_bits {
6456         u8         opcode[0x10];
6457         u8         uid[0x10];
6458
6459         u8         reserved_at_20[0x10];
6460         u8         op_mod[0x10];
6461
6462         u8         modify_header_id[0x20];
6463
6464         u8         reserved_at_60[0xa0];
6465 };
6466
6467 struct mlx5_ifc_query_dct_out_bits {
6468         u8         status[0x8];
6469         u8         reserved_at_8[0x18];
6470
6471         u8         syndrome[0x20];
6472
6473         u8         reserved_at_40[0x40];
6474
6475         struct mlx5_ifc_dctc_bits dct_context_entry;
6476
6477         u8         reserved_at_280[0x180];
6478 };
6479
6480 struct mlx5_ifc_query_dct_in_bits {
6481         u8         opcode[0x10];
6482         u8         reserved_at_10[0x10];
6483
6484         u8         reserved_at_20[0x10];
6485         u8         op_mod[0x10];
6486
6487         u8         reserved_at_40[0x8];
6488         u8         dctn[0x18];
6489
6490         u8         reserved_at_60[0x20];
6491 };
6492
6493 struct mlx5_ifc_query_cq_out_bits {
6494         u8         status[0x8];
6495         u8         reserved_at_8[0x18];
6496
6497         u8         syndrome[0x20];
6498
6499         u8         reserved_at_40[0x40];
6500
6501         struct mlx5_ifc_cqc_bits cq_context;
6502
6503         u8         reserved_at_280[0x600];
6504
6505         u8         pas[][0x40];
6506 };
6507
6508 struct mlx5_ifc_query_cq_in_bits {
6509         u8         opcode[0x10];
6510         u8         reserved_at_10[0x10];
6511
6512         u8         reserved_at_20[0x10];
6513         u8         op_mod[0x10];
6514
6515         u8         reserved_at_40[0x8];
6516         u8         cqn[0x18];
6517
6518         u8         reserved_at_60[0x20];
6519 };
6520
6521 struct mlx5_ifc_query_cong_status_out_bits {
6522         u8         status[0x8];
6523         u8         reserved_at_8[0x18];
6524
6525         u8         syndrome[0x20];
6526
6527         u8         reserved_at_40[0x20];
6528
6529         u8         enable[0x1];
6530         u8         tag_enable[0x1];
6531         u8         reserved_at_62[0x1e];
6532 };
6533
6534 struct mlx5_ifc_query_cong_status_in_bits {
6535         u8         opcode[0x10];
6536         u8         reserved_at_10[0x10];
6537
6538         u8         reserved_at_20[0x10];
6539         u8         op_mod[0x10];
6540
6541         u8         reserved_at_40[0x18];
6542         u8         priority[0x4];
6543         u8         cong_protocol[0x4];
6544
6545         u8         reserved_at_60[0x20];
6546 };
6547
6548 struct mlx5_ifc_query_cong_statistics_out_bits {
6549         u8         status[0x8];
6550         u8         reserved_at_8[0x18];
6551
6552         u8         syndrome[0x20];
6553
6554         u8         reserved_at_40[0x40];
6555
6556         u8         rp_cur_flows[0x20];
6557
6558         u8         sum_flows[0x20];
6559
6560         u8         rp_cnp_ignored_high[0x20];
6561
6562         u8         rp_cnp_ignored_low[0x20];
6563
6564         u8         rp_cnp_handled_high[0x20];
6565
6566         u8         rp_cnp_handled_low[0x20];
6567
6568         u8         reserved_at_140[0x100];
6569
6570         u8         time_stamp_high[0x20];
6571
6572         u8         time_stamp_low[0x20];
6573
6574         u8         accumulators_period[0x20];
6575
6576         u8         np_ecn_marked_roce_packets_high[0x20];
6577
6578         u8         np_ecn_marked_roce_packets_low[0x20];
6579
6580         u8         np_cnp_sent_high[0x20];
6581
6582         u8         np_cnp_sent_low[0x20];
6583
6584         u8         reserved_at_320[0x560];
6585 };
6586
6587 struct mlx5_ifc_query_cong_statistics_in_bits {
6588         u8         opcode[0x10];
6589         u8         reserved_at_10[0x10];
6590
6591         u8         reserved_at_20[0x10];
6592         u8         op_mod[0x10];
6593
6594         u8         clear[0x1];
6595         u8         reserved_at_41[0x1f];
6596
6597         u8         reserved_at_60[0x20];
6598 };
6599
6600 struct mlx5_ifc_query_cong_params_out_bits {
6601         u8         status[0x8];
6602         u8         reserved_at_8[0x18];
6603
6604         u8         syndrome[0x20];
6605
6606         u8         reserved_at_40[0x40];
6607
6608         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6609 };
6610
6611 struct mlx5_ifc_query_cong_params_in_bits {
6612         u8         opcode[0x10];
6613         u8         reserved_at_10[0x10];
6614
6615         u8         reserved_at_20[0x10];
6616         u8         op_mod[0x10];
6617
6618         u8         reserved_at_40[0x1c];
6619         u8         cong_protocol[0x4];
6620
6621         u8         reserved_at_60[0x20];
6622 };
6623
6624 struct mlx5_ifc_query_adapter_out_bits {
6625         u8         status[0x8];
6626         u8         reserved_at_8[0x18];
6627
6628         u8         syndrome[0x20];
6629
6630         u8         reserved_at_40[0x40];
6631
6632         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6633 };
6634
6635 struct mlx5_ifc_query_adapter_in_bits {
6636         u8         opcode[0x10];
6637         u8         reserved_at_10[0x10];
6638
6639         u8         reserved_at_20[0x10];
6640         u8         op_mod[0x10];
6641
6642         u8         reserved_at_40[0x40];
6643 };
6644
6645 struct mlx5_ifc_qp_2rst_out_bits {
6646         u8         status[0x8];
6647         u8         reserved_at_8[0x18];
6648
6649         u8         syndrome[0x20];
6650
6651         u8         reserved_at_40[0x40];
6652 };
6653
6654 struct mlx5_ifc_qp_2rst_in_bits {
6655         u8         opcode[0x10];
6656         u8         uid[0x10];
6657
6658         u8         reserved_at_20[0x10];
6659         u8         op_mod[0x10];
6660
6661         u8         reserved_at_40[0x8];
6662         u8         qpn[0x18];
6663
6664         u8         reserved_at_60[0x20];
6665 };
6666
6667 struct mlx5_ifc_qp_2err_out_bits {
6668         u8         status[0x8];
6669         u8         reserved_at_8[0x18];
6670
6671         u8         syndrome[0x20];
6672
6673         u8         reserved_at_40[0x40];
6674 };
6675
6676 struct mlx5_ifc_qp_2err_in_bits {
6677         u8         opcode[0x10];
6678         u8         uid[0x10];
6679
6680         u8         reserved_at_20[0x10];
6681         u8         op_mod[0x10];
6682
6683         u8         reserved_at_40[0x8];
6684         u8         qpn[0x18];
6685
6686         u8         reserved_at_60[0x20];
6687 };
6688
6689 struct mlx5_ifc_page_fault_resume_out_bits {
6690         u8         status[0x8];
6691         u8         reserved_at_8[0x18];
6692
6693         u8         syndrome[0x20];
6694
6695         u8         reserved_at_40[0x40];
6696 };
6697
6698 struct mlx5_ifc_page_fault_resume_in_bits {
6699         u8         opcode[0x10];
6700         u8         reserved_at_10[0x10];
6701
6702         u8         reserved_at_20[0x10];
6703         u8         op_mod[0x10];
6704
6705         u8         error[0x1];
6706         u8         reserved_at_41[0x4];
6707         u8         page_fault_type[0x3];
6708         u8         wq_number[0x18];
6709
6710         u8         reserved_at_60[0x8];
6711         u8         token[0x18];
6712 };
6713
6714 struct mlx5_ifc_nop_out_bits {
6715         u8         status[0x8];
6716         u8         reserved_at_8[0x18];
6717
6718         u8         syndrome[0x20];
6719
6720         u8         reserved_at_40[0x40];
6721 };
6722
6723 struct mlx5_ifc_nop_in_bits {
6724         u8         opcode[0x10];
6725         u8         reserved_at_10[0x10];
6726
6727         u8         reserved_at_20[0x10];
6728         u8         op_mod[0x10];
6729
6730         u8         reserved_at_40[0x40];
6731 };
6732
6733 struct mlx5_ifc_modify_vport_state_out_bits {
6734         u8         status[0x8];
6735         u8         reserved_at_8[0x18];
6736
6737         u8         syndrome[0x20];
6738
6739         u8         reserved_at_40[0x40];
6740 };
6741
6742 struct mlx5_ifc_modify_vport_state_in_bits {
6743         u8         opcode[0x10];
6744         u8         reserved_at_10[0x10];
6745
6746         u8         reserved_at_20[0x10];
6747         u8         op_mod[0x10];
6748
6749         u8         other_vport[0x1];
6750         u8         reserved_at_41[0xf];
6751         u8         vport_number[0x10];
6752
6753         u8         reserved_at_60[0x18];
6754         u8         admin_state[0x4];
6755         u8         reserved_at_7c[0x4];
6756 };
6757
6758 struct mlx5_ifc_modify_tis_out_bits {
6759         u8         status[0x8];
6760         u8         reserved_at_8[0x18];
6761
6762         u8         syndrome[0x20];
6763
6764         u8         reserved_at_40[0x40];
6765 };
6766
6767 struct mlx5_ifc_modify_tis_bitmask_bits {
6768         u8         reserved_at_0[0x20];
6769
6770         u8         reserved_at_20[0x1d];
6771         u8         lag_tx_port_affinity[0x1];
6772         u8         strict_lag_tx_port_affinity[0x1];
6773         u8         prio[0x1];
6774 };
6775
6776 struct mlx5_ifc_modify_tis_in_bits {
6777         u8         opcode[0x10];
6778         u8         uid[0x10];
6779
6780         u8         reserved_at_20[0x10];
6781         u8         op_mod[0x10];
6782
6783         u8         reserved_at_40[0x8];
6784         u8         tisn[0x18];
6785
6786         u8         reserved_at_60[0x20];
6787
6788         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6789
6790         u8         reserved_at_c0[0x40];
6791
6792         struct mlx5_ifc_tisc_bits ctx;
6793 };
6794
6795 struct mlx5_ifc_modify_tir_bitmask_bits {
6796         u8         reserved_at_0[0x20];
6797
6798         u8         reserved_at_20[0x1b];
6799         u8         self_lb_en[0x1];
6800         u8         reserved_at_3c[0x1];
6801         u8         hash[0x1];
6802         u8         reserved_at_3e[0x1];
6803         u8         packet_merge[0x1];
6804 };
6805
6806 struct mlx5_ifc_modify_tir_out_bits {
6807         u8         status[0x8];
6808         u8         reserved_at_8[0x18];
6809
6810         u8         syndrome[0x20];
6811
6812         u8         reserved_at_40[0x40];
6813 };
6814
6815 struct mlx5_ifc_modify_tir_in_bits {
6816         u8         opcode[0x10];
6817         u8         uid[0x10];
6818
6819         u8         reserved_at_20[0x10];
6820         u8         op_mod[0x10];
6821
6822         u8         reserved_at_40[0x8];
6823         u8         tirn[0x18];
6824
6825         u8         reserved_at_60[0x20];
6826
6827         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6828
6829         u8         reserved_at_c0[0x40];
6830
6831         struct mlx5_ifc_tirc_bits ctx;
6832 };
6833
6834 struct mlx5_ifc_modify_sq_out_bits {
6835         u8         status[0x8];
6836         u8         reserved_at_8[0x18];
6837
6838         u8         syndrome[0x20];
6839
6840         u8         reserved_at_40[0x40];
6841 };
6842
6843 struct mlx5_ifc_modify_sq_in_bits {
6844         u8         opcode[0x10];
6845         u8         uid[0x10];
6846
6847         u8         reserved_at_20[0x10];
6848         u8         op_mod[0x10];
6849
6850         u8         sq_state[0x4];
6851         u8         reserved_at_44[0x4];
6852         u8         sqn[0x18];
6853
6854         u8         reserved_at_60[0x20];
6855
6856         u8         modify_bitmask[0x40];
6857
6858         u8         reserved_at_c0[0x40];
6859
6860         struct mlx5_ifc_sqc_bits ctx;
6861 };
6862
6863 struct mlx5_ifc_modify_scheduling_element_out_bits {
6864         u8         status[0x8];
6865         u8         reserved_at_8[0x18];
6866
6867         u8         syndrome[0x20];
6868
6869         u8         reserved_at_40[0x1c0];
6870 };
6871
6872 enum {
6873         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6874         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6875 };
6876
6877 struct mlx5_ifc_modify_scheduling_element_in_bits {
6878         u8         opcode[0x10];
6879         u8         reserved_at_10[0x10];
6880
6881         u8         reserved_at_20[0x10];
6882         u8         op_mod[0x10];
6883
6884         u8         scheduling_hierarchy[0x8];
6885         u8         reserved_at_48[0x18];
6886
6887         u8         scheduling_element_id[0x20];
6888
6889         u8         reserved_at_80[0x20];
6890
6891         u8         modify_bitmask[0x20];
6892
6893         u8         reserved_at_c0[0x40];
6894
6895         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6896
6897         u8         reserved_at_300[0x100];
6898 };
6899
6900 struct mlx5_ifc_modify_rqt_out_bits {
6901         u8         status[0x8];
6902         u8         reserved_at_8[0x18];
6903
6904         u8         syndrome[0x20];
6905
6906         u8         reserved_at_40[0x40];
6907 };
6908
6909 struct mlx5_ifc_rqt_bitmask_bits {
6910         u8         reserved_at_0[0x20];
6911
6912         u8         reserved_at_20[0x1f];
6913         u8         rqn_list[0x1];
6914 };
6915
6916 struct mlx5_ifc_modify_rqt_in_bits {
6917         u8         opcode[0x10];
6918         u8         uid[0x10];
6919
6920         u8         reserved_at_20[0x10];
6921         u8         op_mod[0x10];
6922
6923         u8         reserved_at_40[0x8];
6924         u8         rqtn[0x18];
6925
6926         u8         reserved_at_60[0x20];
6927
6928         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6929
6930         u8         reserved_at_c0[0x40];
6931
6932         struct mlx5_ifc_rqtc_bits ctx;
6933 };
6934
6935 struct mlx5_ifc_modify_rq_out_bits {
6936         u8         status[0x8];
6937         u8         reserved_at_8[0x18];
6938
6939         u8         syndrome[0x20];
6940
6941         u8         reserved_at_40[0x40];
6942 };
6943
6944 enum {
6945         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6946         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6947         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6948 };
6949
6950 struct mlx5_ifc_modify_rq_in_bits {
6951         u8         opcode[0x10];
6952         u8         uid[0x10];
6953
6954         u8         reserved_at_20[0x10];
6955         u8         op_mod[0x10];
6956
6957         u8         rq_state[0x4];
6958         u8         reserved_at_44[0x4];
6959         u8         rqn[0x18];
6960
6961         u8         reserved_at_60[0x20];
6962
6963         u8         modify_bitmask[0x40];
6964
6965         u8         reserved_at_c0[0x40];
6966
6967         struct mlx5_ifc_rqc_bits ctx;
6968 };
6969
6970 struct mlx5_ifc_modify_rmp_out_bits {
6971         u8         status[0x8];
6972         u8         reserved_at_8[0x18];
6973
6974         u8         syndrome[0x20];
6975
6976         u8         reserved_at_40[0x40];
6977 };
6978
6979 struct mlx5_ifc_rmp_bitmask_bits {
6980         u8         reserved_at_0[0x20];
6981
6982         u8         reserved_at_20[0x1f];
6983         u8         lwm[0x1];
6984 };
6985
6986 struct mlx5_ifc_modify_rmp_in_bits {
6987         u8         opcode[0x10];
6988         u8         uid[0x10];
6989
6990         u8         reserved_at_20[0x10];
6991         u8         op_mod[0x10];
6992
6993         u8         rmp_state[0x4];
6994         u8         reserved_at_44[0x4];
6995         u8         rmpn[0x18];
6996
6997         u8         reserved_at_60[0x20];
6998
6999         struct mlx5_ifc_rmp_bitmask_bits bitmask;
7000
7001         u8         reserved_at_c0[0x40];
7002
7003         struct mlx5_ifc_rmpc_bits ctx;
7004 };
7005
7006 struct mlx5_ifc_modify_nic_vport_context_out_bits {
7007         u8         status[0x8];
7008         u8         reserved_at_8[0x18];
7009
7010         u8         syndrome[0x20];
7011
7012         u8         reserved_at_40[0x40];
7013 };
7014
7015 struct mlx5_ifc_modify_nic_vport_field_select_bits {
7016         u8         reserved_at_0[0x12];
7017         u8         affiliation[0x1];
7018         u8         reserved_at_13[0x1];
7019         u8         disable_uc_local_lb[0x1];
7020         u8         disable_mc_local_lb[0x1];
7021         u8         node_guid[0x1];
7022         u8         port_guid[0x1];
7023         u8         min_inline[0x1];
7024         u8         mtu[0x1];
7025         u8         change_event[0x1];
7026         u8         promisc[0x1];
7027         u8         permanent_address[0x1];
7028         u8         addresses_list[0x1];
7029         u8         roce_en[0x1];
7030         u8         reserved_at_1f[0x1];
7031 };
7032
7033 struct mlx5_ifc_modify_nic_vport_context_in_bits {
7034         u8         opcode[0x10];
7035         u8         reserved_at_10[0x10];
7036
7037         u8         reserved_at_20[0x10];
7038         u8         op_mod[0x10];
7039
7040         u8         other_vport[0x1];
7041         u8         reserved_at_41[0xf];
7042         u8         vport_number[0x10];
7043
7044         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7045
7046         u8         reserved_at_80[0x780];
7047
7048         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7049 };
7050
7051 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7052         u8         status[0x8];
7053         u8         reserved_at_8[0x18];
7054
7055         u8         syndrome[0x20];
7056
7057         u8         reserved_at_40[0x40];
7058 };
7059
7060 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7061         u8         opcode[0x10];
7062         u8         reserved_at_10[0x10];
7063
7064         u8         reserved_at_20[0x10];
7065         u8         op_mod[0x10];
7066
7067         u8         other_vport[0x1];
7068         u8         reserved_at_41[0xb];
7069         u8         port_num[0x4];
7070         u8         vport_number[0x10];
7071
7072         u8         reserved_at_60[0x20];
7073
7074         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7075 };
7076
7077 struct mlx5_ifc_modify_cq_out_bits {
7078         u8         status[0x8];
7079         u8         reserved_at_8[0x18];
7080
7081         u8         syndrome[0x20];
7082
7083         u8         reserved_at_40[0x40];
7084 };
7085
7086 enum {
7087         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7088         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7089 };
7090
7091 struct mlx5_ifc_modify_cq_in_bits {
7092         u8         opcode[0x10];
7093         u8         uid[0x10];
7094
7095         u8         reserved_at_20[0x10];
7096         u8         op_mod[0x10];
7097
7098         u8         reserved_at_40[0x8];
7099         u8         cqn[0x18];
7100
7101         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7102
7103         struct mlx5_ifc_cqc_bits cq_context;
7104
7105         u8         reserved_at_280[0x60];
7106
7107         u8         cq_umem_valid[0x1];
7108         u8         reserved_at_2e1[0x1f];
7109
7110         u8         reserved_at_300[0x580];
7111
7112         u8         pas[][0x40];
7113 };
7114
7115 struct mlx5_ifc_modify_cong_status_out_bits {
7116         u8         status[0x8];
7117         u8         reserved_at_8[0x18];
7118
7119         u8         syndrome[0x20];
7120
7121         u8         reserved_at_40[0x40];
7122 };
7123
7124 struct mlx5_ifc_modify_cong_status_in_bits {
7125         u8         opcode[0x10];
7126         u8         reserved_at_10[0x10];
7127
7128         u8         reserved_at_20[0x10];
7129         u8         op_mod[0x10];
7130
7131         u8         reserved_at_40[0x18];
7132         u8         priority[0x4];
7133         u8         cong_protocol[0x4];
7134
7135         u8         enable[0x1];
7136         u8         tag_enable[0x1];
7137         u8         reserved_at_62[0x1e];
7138 };
7139
7140 struct mlx5_ifc_modify_cong_params_out_bits {
7141         u8         status[0x8];
7142         u8         reserved_at_8[0x18];
7143
7144         u8         syndrome[0x20];
7145
7146         u8         reserved_at_40[0x40];
7147 };
7148
7149 struct mlx5_ifc_modify_cong_params_in_bits {
7150         u8         opcode[0x10];
7151         u8         reserved_at_10[0x10];
7152
7153         u8         reserved_at_20[0x10];
7154         u8         op_mod[0x10];
7155
7156         u8         reserved_at_40[0x1c];
7157         u8         cong_protocol[0x4];
7158
7159         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7160
7161         u8         reserved_at_80[0x80];
7162
7163         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7164 };
7165
7166 struct mlx5_ifc_manage_pages_out_bits {
7167         u8         status[0x8];
7168         u8         reserved_at_8[0x18];
7169
7170         u8         syndrome[0x20];
7171
7172         u8         output_num_entries[0x20];
7173
7174         u8         reserved_at_60[0x20];
7175
7176         u8         pas[][0x40];
7177 };
7178
7179 enum {
7180         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7181         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7182         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7183 };
7184
7185 struct mlx5_ifc_manage_pages_in_bits {
7186         u8         opcode[0x10];
7187         u8         reserved_at_10[0x10];
7188
7189         u8         reserved_at_20[0x10];
7190         u8         op_mod[0x10];
7191
7192         u8         embedded_cpu_function[0x1];
7193         u8         reserved_at_41[0xf];
7194         u8         function_id[0x10];
7195
7196         u8         input_num_entries[0x20];
7197
7198         u8         pas[][0x40];
7199 };
7200
7201 struct mlx5_ifc_mad_ifc_out_bits {
7202         u8         status[0x8];
7203         u8         reserved_at_8[0x18];
7204
7205         u8         syndrome[0x20];
7206
7207         u8         reserved_at_40[0x40];
7208
7209         u8         response_mad_packet[256][0x8];
7210 };
7211
7212 struct mlx5_ifc_mad_ifc_in_bits {
7213         u8         opcode[0x10];
7214         u8         reserved_at_10[0x10];
7215
7216         u8         reserved_at_20[0x10];
7217         u8         op_mod[0x10];
7218
7219         u8         remote_lid[0x10];
7220         u8         reserved_at_50[0x8];
7221         u8         port[0x8];
7222
7223         u8         reserved_at_60[0x20];
7224
7225         u8         mad[256][0x8];
7226 };
7227
7228 struct mlx5_ifc_init_hca_out_bits {
7229         u8         status[0x8];
7230         u8         reserved_at_8[0x18];
7231
7232         u8         syndrome[0x20];
7233
7234         u8         reserved_at_40[0x40];
7235 };
7236
7237 struct mlx5_ifc_init_hca_in_bits {
7238         u8         opcode[0x10];
7239         u8         reserved_at_10[0x10];
7240
7241         u8         reserved_at_20[0x10];
7242         u8         op_mod[0x10];
7243
7244         u8         reserved_at_40[0x40];
7245         u8         sw_owner_id[4][0x20];
7246 };
7247
7248 struct mlx5_ifc_init2rtr_qp_out_bits {
7249         u8         status[0x8];
7250         u8         reserved_at_8[0x18];
7251
7252         u8         syndrome[0x20];
7253
7254         u8         reserved_at_40[0x20];
7255         u8         ece[0x20];
7256 };
7257
7258 struct mlx5_ifc_init2rtr_qp_in_bits {
7259         u8         opcode[0x10];
7260         u8         uid[0x10];
7261
7262         u8         reserved_at_20[0x10];
7263         u8         op_mod[0x10];
7264
7265         u8         reserved_at_40[0x8];
7266         u8         qpn[0x18];
7267
7268         u8         reserved_at_60[0x20];
7269
7270         u8         opt_param_mask[0x20];
7271
7272         u8         ece[0x20];
7273
7274         struct mlx5_ifc_qpc_bits qpc;
7275
7276         u8         reserved_at_800[0x80];
7277 };
7278
7279 struct mlx5_ifc_init2init_qp_out_bits {
7280         u8         status[0x8];
7281         u8         reserved_at_8[0x18];
7282
7283         u8         syndrome[0x20];
7284
7285         u8         reserved_at_40[0x20];
7286         u8         ece[0x20];
7287 };
7288
7289 struct mlx5_ifc_init2init_qp_in_bits {
7290         u8         opcode[0x10];
7291         u8         uid[0x10];
7292
7293         u8         reserved_at_20[0x10];
7294         u8         op_mod[0x10];
7295
7296         u8         reserved_at_40[0x8];
7297         u8         qpn[0x18];
7298
7299         u8         reserved_at_60[0x20];
7300
7301         u8         opt_param_mask[0x20];
7302
7303         u8         ece[0x20];
7304
7305         struct mlx5_ifc_qpc_bits qpc;
7306
7307         u8         reserved_at_800[0x80];
7308 };
7309
7310 struct mlx5_ifc_get_dropped_packet_log_out_bits {
7311         u8         status[0x8];
7312         u8         reserved_at_8[0x18];
7313
7314         u8         syndrome[0x20];
7315
7316         u8         reserved_at_40[0x40];
7317
7318         u8         packet_headers_log[128][0x8];
7319
7320         u8         packet_syndrome[64][0x8];
7321 };
7322
7323 struct mlx5_ifc_get_dropped_packet_log_in_bits {
7324         u8         opcode[0x10];
7325         u8         reserved_at_10[0x10];
7326
7327         u8         reserved_at_20[0x10];
7328         u8         op_mod[0x10];
7329
7330         u8         reserved_at_40[0x40];
7331 };
7332
7333 struct mlx5_ifc_gen_eqe_in_bits {
7334         u8         opcode[0x10];
7335         u8         reserved_at_10[0x10];
7336
7337         u8         reserved_at_20[0x10];
7338         u8         op_mod[0x10];
7339
7340         u8         reserved_at_40[0x18];
7341         u8         eq_number[0x8];
7342
7343         u8         reserved_at_60[0x20];
7344
7345         u8         eqe[64][0x8];
7346 };
7347
7348 struct mlx5_ifc_gen_eq_out_bits {
7349         u8         status[0x8];
7350         u8         reserved_at_8[0x18];
7351
7352         u8         syndrome[0x20];
7353
7354         u8         reserved_at_40[0x40];
7355 };
7356
7357 struct mlx5_ifc_enable_hca_out_bits {
7358         u8         status[0x8];
7359         u8         reserved_at_8[0x18];
7360
7361         u8         syndrome[0x20];
7362
7363         u8         reserved_at_40[0x20];
7364 };
7365
7366 struct mlx5_ifc_enable_hca_in_bits {
7367         u8         opcode[0x10];
7368         u8         reserved_at_10[0x10];
7369
7370         u8         reserved_at_20[0x10];
7371         u8         op_mod[0x10];
7372
7373         u8         embedded_cpu_function[0x1];
7374         u8         reserved_at_41[0xf];
7375         u8         function_id[0x10];
7376
7377         u8         reserved_at_60[0x20];
7378 };
7379
7380 struct mlx5_ifc_drain_dct_out_bits {
7381         u8         status[0x8];
7382         u8         reserved_at_8[0x18];
7383
7384         u8         syndrome[0x20];
7385
7386         u8         reserved_at_40[0x40];
7387 };
7388
7389 struct mlx5_ifc_drain_dct_in_bits {
7390         u8         opcode[0x10];
7391         u8         uid[0x10];
7392
7393         u8         reserved_at_20[0x10];
7394         u8         op_mod[0x10];
7395
7396         u8         reserved_at_40[0x8];
7397         u8         dctn[0x18];
7398
7399         u8         reserved_at_60[0x20];
7400 };
7401
7402 struct mlx5_ifc_disable_hca_out_bits {
7403         u8         status[0x8];
7404         u8         reserved_at_8[0x18];
7405
7406         u8         syndrome[0x20];
7407
7408         u8         reserved_at_40[0x20];
7409 };
7410
7411 struct mlx5_ifc_disable_hca_in_bits {
7412         u8         opcode[0x10];
7413         u8         reserved_at_10[0x10];
7414
7415         u8         reserved_at_20[0x10];
7416         u8         op_mod[0x10];
7417
7418         u8         embedded_cpu_function[0x1];
7419         u8         reserved_at_41[0xf];
7420         u8         function_id[0x10];
7421
7422         u8         reserved_at_60[0x20];
7423 };
7424
7425 struct mlx5_ifc_detach_from_mcg_out_bits {
7426         u8         status[0x8];
7427         u8         reserved_at_8[0x18];
7428
7429         u8         syndrome[0x20];
7430
7431         u8         reserved_at_40[0x40];
7432 };
7433
7434 struct mlx5_ifc_detach_from_mcg_in_bits {
7435         u8         opcode[0x10];
7436         u8         uid[0x10];
7437
7438         u8         reserved_at_20[0x10];
7439         u8         op_mod[0x10];
7440
7441         u8         reserved_at_40[0x8];
7442         u8         qpn[0x18];
7443
7444         u8         reserved_at_60[0x20];
7445
7446         u8         multicast_gid[16][0x8];
7447 };
7448
7449 struct mlx5_ifc_destroy_xrq_out_bits {
7450         u8         status[0x8];
7451         u8         reserved_at_8[0x18];
7452
7453         u8         syndrome[0x20];
7454
7455         u8         reserved_at_40[0x40];
7456 };
7457
7458 struct mlx5_ifc_destroy_xrq_in_bits {
7459         u8         opcode[0x10];
7460         u8         uid[0x10];
7461
7462         u8         reserved_at_20[0x10];
7463         u8         op_mod[0x10];
7464
7465         u8         reserved_at_40[0x8];
7466         u8         xrqn[0x18];
7467
7468         u8         reserved_at_60[0x20];
7469 };
7470
7471 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7472         u8         status[0x8];
7473         u8         reserved_at_8[0x18];
7474
7475         u8         syndrome[0x20];
7476
7477         u8         reserved_at_40[0x40];
7478 };
7479
7480 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7481         u8         opcode[0x10];
7482         u8         uid[0x10];
7483
7484         u8         reserved_at_20[0x10];
7485         u8         op_mod[0x10];
7486
7487         u8         reserved_at_40[0x8];
7488         u8         xrc_srqn[0x18];
7489
7490         u8         reserved_at_60[0x20];
7491 };
7492
7493 struct mlx5_ifc_destroy_tis_out_bits {
7494         u8         status[0x8];
7495         u8         reserved_at_8[0x18];
7496
7497         u8         syndrome[0x20];
7498
7499         u8         reserved_at_40[0x40];
7500 };
7501
7502 struct mlx5_ifc_destroy_tis_in_bits {
7503         u8         opcode[0x10];
7504         u8         uid[0x10];
7505
7506         u8         reserved_at_20[0x10];
7507         u8         op_mod[0x10];
7508
7509         u8         reserved_at_40[0x8];
7510         u8         tisn[0x18];
7511
7512         u8         reserved_at_60[0x20];
7513 };
7514
7515 struct mlx5_ifc_destroy_tir_out_bits {
7516         u8         status[0x8];
7517         u8         reserved_at_8[0x18];
7518
7519         u8         syndrome[0x20];
7520
7521         u8         reserved_at_40[0x40];
7522 };
7523
7524 struct mlx5_ifc_destroy_tir_in_bits {
7525         u8         opcode[0x10];
7526         u8         uid[0x10];
7527
7528         u8         reserved_at_20[0x10];
7529         u8         op_mod[0x10];
7530
7531         u8         reserved_at_40[0x8];
7532         u8         tirn[0x18];
7533
7534         u8         reserved_at_60[0x20];
7535 };
7536
7537 struct mlx5_ifc_destroy_srq_out_bits {
7538         u8         status[0x8];
7539         u8         reserved_at_8[0x18];
7540
7541         u8         syndrome[0x20];
7542
7543         u8         reserved_at_40[0x40];
7544 };
7545
7546 struct mlx5_ifc_destroy_srq_in_bits {
7547         u8         opcode[0x10];
7548         u8         uid[0x10];
7549
7550         u8         reserved_at_20[0x10];
7551         u8         op_mod[0x10];
7552
7553         u8         reserved_at_40[0x8];
7554         u8         srqn[0x18];
7555
7556         u8         reserved_at_60[0x20];
7557 };
7558
7559 struct mlx5_ifc_destroy_sq_out_bits {
7560         u8         status[0x8];
7561         u8         reserved_at_8[0x18];
7562
7563         u8         syndrome[0x20];
7564
7565         u8         reserved_at_40[0x40];
7566 };
7567
7568 struct mlx5_ifc_destroy_sq_in_bits {
7569         u8         opcode[0x10];
7570         u8         uid[0x10];
7571
7572         u8         reserved_at_20[0x10];
7573         u8         op_mod[0x10];
7574
7575         u8         reserved_at_40[0x8];
7576         u8         sqn[0x18];
7577
7578         u8         reserved_at_60[0x20];
7579 };
7580
7581 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7582         u8         status[0x8];
7583         u8         reserved_at_8[0x18];
7584
7585         u8         syndrome[0x20];
7586
7587         u8         reserved_at_40[0x1c0];
7588 };
7589
7590 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7591         u8         opcode[0x10];
7592         u8         reserved_at_10[0x10];
7593
7594         u8         reserved_at_20[0x10];
7595         u8         op_mod[0x10];
7596
7597         u8         scheduling_hierarchy[0x8];
7598         u8         reserved_at_48[0x18];
7599
7600         u8         scheduling_element_id[0x20];
7601
7602         u8         reserved_at_80[0x180];
7603 };
7604
7605 struct mlx5_ifc_destroy_rqt_out_bits {
7606         u8         status[0x8];
7607         u8         reserved_at_8[0x18];
7608
7609         u8         syndrome[0x20];
7610
7611         u8         reserved_at_40[0x40];
7612 };
7613
7614 struct mlx5_ifc_destroy_rqt_in_bits {
7615         u8         opcode[0x10];
7616         u8         uid[0x10];
7617
7618         u8         reserved_at_20[0x10];
7619         u8         op_mod[0x10];
7620
7621         u8         reserved_at_40[0x8];
7622         u8         rqtn[0x18];
7623
7624         u8         reserved_at_60[0x20];
7625 };
7626
7627 struct mlx5_ifc_destroy_rq_out_bits {
7628         u8         status[0x8];
7629         u8         reserved_at_8[0x18];
7630
7631         u8         syndrome[0x20];
7632
7633         u8         reserved_at_40[0x40];
7634 };
7635
7636 struct mlx5_ifc_destroy_rq_in_bits {
7637         u8         opcode[0x10];
7638         u8         uid[0x10];
7639
7640         u8         reserved_at_20[0x10];
7641         u8         op_mod[0x10];
7642
7643         u8         reserved_at_40[0x8];
7644         u8         rqn[0x18];
7645
7646         u8         reserved_at_60[0x20];
7647 };
7648
7649 struct mlx5_ifc_set_delay_drop_params_in_bits {
7650         u8         opcode[0x10];
7651         u8         reserved_at_10[0x10];
7652
7653         u8         reserved_at_20[0x10];
7654         u8         op_mod[0x10];
7655
7656         u8         reserved_at_40[0x20];
7657
7658         u8         reserved_at_60[0x10];
7659         u8         delay_drop_timeout[0x10];
7660 };
7661
7662 struct mlx5_ifc_set_delay_drop_params_out_bits {
7663         u8         status[0x8];
7664         u8         reserved_at_8[0x18];
7665
7666         u8         syndrome[0x20];
7667
7668         u8         reserved_at_40[0x40];
7669 };
7670
7671 struct mlx5_ifc_destroy_rmp_out_bits {
7672         u8         status[0x8];
7673         u8         reserved_at_8[0x18];
7674
7675         u8         syndrome[0x20];
7676
7677         u8         reserved_at_40[0x40];
7678 };
7679
7680 struct mlx5_ifc_destroy_rmp_in_bits {
7681         u8         opcode[0x10];
7682         u8         uid[0x10];
7683
7684         u8         reserved_at_20[0x10];
7685         u8         op_mod[0x10];
7686
7687         u8         reserved_at_40[0x8];
7688         u8         rmpn[0x18];
7689
7690         u8         reserved_at_60[0x20];
7691 };
7692
7693 struct mlx5_ifc_destroy_qp_out_bits {
7694         u8         status[0x8];
7695         u8         reserved_at_8[0x18];
7696
7697         u8         syndrome[0x20];
7698
7699         u8         reserved_at_40[0x40];
7700 };
7701
7702 struct mlx5_ifc_destroy_qp_in_bits {
7703         u8         opcode[0x10];
7704         u8         uid[0x10];
7705
7706         u8         reserved_at_20[0x10];
7707         u8         op_mod[0x10];
7708
7709         u8         reserved_at_40[0x8];
7710         u8         qpn[0x18];
7711
7712         u8         reserved_at_60[0x20];
7713 };
7714
7715 struct mlx5_ifc_destroy_psv_out_bits {
7716         u8         status[0x8];
7717         u8         reserved_at_8[0x18];
7718
7719         u8         syndrome[0x20];
7720
7721         u8         reserved_at_40[0x40];
7722 };
7723
7724 struct mlx5_ifc_destroy_psv_in_bits {
7725         u8         opcode[0x10];
7726         u8         reserved_at_10[0x10];
7727
7728         u8         reserved_at_20[0x10];
7729         u8         op_mod[0x10];
7730
7731         u8         reserved_at_40[0x8];
7732         u8         psvn[0x18];
7733
7734         u8         reserved_at_60[0x20];
7735 };
7736
7737 struct mlx5_ifc_destroy_mkey_out_bits {
7738         u8         status[0x8];
7739         u8         reserved_at_8[0x18];
7740
7741         u8         syndrome[0x20];
7742
7743         u8         reserved_at_40[0x40];
7744 };
7745
7746 struct mlx5_ifc_destroy_mkey_in_bits {
7747         u8         opcode[0x10];
7748         u8         uid[0x10];
7749
7750         u8         reserved_at_20[0x10];
7751         u8         op_mod[0x10];
7752
7753         u8         reserved_at_40[0x8];
7754         u8         mkey_index[0x18];
7755
7756         u8         reserved_at_60[0x20];
7757 };
7758
7759 struct mlx5_ifc_destroy_flow_table_out_bits {
7760         u8         status[0x8];
7761         u8         reserved_at_8[0x18];
7762
7763         u8         syndrome[0x20];
7764
7765         u8         reserved_at_40[0x40];
7766 };
7767
7768 struct mlx5_ifc_destroy_flow_table_in_bits {
7769         u8         opcode[0x10];
7770         u8         reserved_at_10[0x10];
7771
7772         u8         reserved_at_20[0x10];
7773         u8         op_mod[0x10];
7774
7775         u8         other_vport[0x1];
7776         u8         reserved_at_41[0xf];
7777         u8         vport_number[0x10];
7778
7779         u8         reserved_at_60[0x20];
7780
7781         u8         table_type[0x8];
7782         u8         reserved_at_88[0x18];
7783
7784         u8         reserved_at_a0[0x8];
7785         u8         table_id[0x18];
7786
7787         u8         reserved_at_c0[0x140];
7788 };
7789
7790 struct mlx5_ifc_destroy_flow_group_out_bits {
7791         u8         status[0x8];
7792         u8         reserved_at_8[0x18];
7793
7794         u8         syndrome[0x20];
7795
7796         u8         reserved_at_40[0x40];
7797 };
7798
7799 struct mlx5_ifc_destroy_flow_group_in_bits {
7800         u8         opcode[0x10];
7801         u8         reserved_at_10[0x10];
7802
7803         u8         reserved_at_20[0x10];
7804         u8         op_mod[0x10];
7805
7806         u8         other_vport[0x1];
7807         u8         reserved_at_41[0xf];
7808         u8         vport_number[0x10];
7809
7810         u8         reserved_at_60[0x20];
7811
7812         u8         table_type[0x8];
7813         u8         reserved_at_88[0x18];
7814
7815         u8         reserved_at_a0[0x8];
7816         u8         table_id[0x18];
7817
7818         u8         group_id[0x20];
7819
7820         u8         reserved_at_e0[0x120];
7821 };
7822
7823 struct mlx5_ifc_destroy_eq_out_bits {
7824         u8         status[0x8];
7825         u8         reserved_at_8[0x18];
7826
7827         u8         syndrome[0x20];
7828
7829         u8         reserved_at_40[0x40];
7830 };
7831
7832 struct mlx5_ifc_destroy_eq_in_bits {
7833         u8         opcode[0x10];
7834         u8         reserved_at_10[0x10];
7835
7836         u8         reserved_at_20[0x10];
7837         u8         op_mod[0x10];
7838
7839         u8         reserved_at_40[0x18];
7840         u8         eq_number[0x8];
7841
7842         u8         reserved_at_60[0x20];
7843 };
7844
7845 struct mlx5_ifc_destroy_dct_out_bits {
7846         u8         status[0x8];
7847         u8         reserved_at_8[0x18];
7848
7849         u8         syndrome[0x20];
7850
7851         u8         reserved_at_40[0x40];
7852 };
7853
7854 struct mlx5_ifc_destroy_dct_in_bits {
7855         u8         opcode[0x10];
7856         u8         uid[0x10];
7857
7858         u8         reserved_at_20[0x10];
7859         u8         op_mod[0x10];
7860
7861         u8         reserved_at_40[0x8];
7862         u8         dctn[0x18];
7863
7864         u8         reserved_at_60[0x20];
7865 };
7866
7867 struct mlx5_ifc_destroy_cq_out_bits {
7868         u8         status[0x8];
7869         u8         reserved_at_8[0x18];
7870
7871         u8         syndrome[0x20];
7872
7873         u8         reserved_at_40[0x40];
7874 };
7875
7876 struct mlx5_ifc_destroy_cq_in_bits {
7877         u8         opcode[0x10];
7878         u8         uid[0x10];
7879
7880         u8         reserved_at_20[0x10];
7881         u8         op_mod[0x10];
7882
7883         u8         reserved_at_40[0x8];
7884         u8         cqn[0x18];
7885
7886         u8         reserved_at_60[0x20];
7887 };
7888
7889 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7890         u8         status[0x8];
7891         u8         reserved_at_8[0x18];
7892
7893         u8         syndrome[0x20];
7894
7895         u8         reserved_at_40[0x40];
7896 };
7897
7898 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7899         u8         opcode[0x10];
7900         u8         reserved_at_10[0x10];
7901
7902         u8         reserved_at_20[0x10];
7903         u8         op_mod[0x10];
7904
7905         u8         reserved_at_40[0x20];
7906
7907         u8         reserved_at_60[0x10];
7908         u8         vxlan_udp_port[0x10];
7909 };
7910
7911 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7912         u8         status[0x8];
7913         u8         reserved_at_8[0x18];
7914
7915         u8         syndrome[0x20];
7916
7917         u8         reserved_at_40[0x40];
7918 };
7919
7920 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7921         u8         opcode[0x10];
7922         u8         reserved_at_10[0x10];
7923
7924         u8         reserved_at_20[0x10];
7925         u8         op_mod[0x10];
7926
7927         u8         reserved_at_40[0x60];
7928
7929         u8         reserved_at_a0[0x8];
7930         u8         table_index[0x18];
7931
7932         u8         reserved_at_c0[0x140];
7933 };
7934
7935 struct mlx5_ifc_delete_fte_out_bits {
7936         u8         status[0x8];
7937         u8         reserved_at_8[0x18];
7938
7939         u8         syndrome[0x20];
7940
7941         u8         reserved_at_40[0x40];
7942 };
7943
7944 struct mlx5_ifc_delete_fte_in_bits {
7945         u8         opcode[0x10];
7946         u8         reserved_at_10[0x10];
7947
7948         u8         reserved_at_20[0x10];
7949         u8         op_mod[0x10];
7950
7951         u8         other_vport[0x1];
7952         u8         reserved_at_41[0xf];
7953         u8         vport_number[0x10];
7954
7955         u8         reserved_at_60[0x20];
7956
7957         u8         table_type[0x8];
7958         u8         reserved_at_88[0x18];
7959
7960         u8         reserved_at_a0[0x8];
7961         u8         table_id[0x18];
7962
7963         u8         reserved_at_c0[0x40];
7964
7965         u8         flow_index[0x20];
7966
7967         u8         reserved_at_120[0xe0];
7968 };
7969
7970 struct mlx5_ifc_dealloc_xrcd_out_bits {
7971         u8         status[0x8];
7972         u8         reserved_at_8[0x18];
7973
7974         u8         syndrome[0x20];
7975
7976         u8         reserved_at_40[0x40];
7977 };
7978
7979 struct mlx5_ifc_dealloc_xrcd_in_bits {
7980         u8         opcode[0x10];
7981         u8         uid[0x10];
7982
7983         u8         reserved_at_20[0x10];
7984         u8         op_mod[0x10];
7985
7986         u8         reserved_at_40[0x8];
7987         u8         xrcd[0x18];
7988
7989         u8         reserved_at_60[0x20];
7990 };
7991
7992 struct mlx5_ifc_dealloc_uar_out_bits {
7993         u8         status[0x8];
7994         u8         reserved_at_8[0x18];
7995
7996         u8         syndrome[0x20];
7997
7998         u8         reserved_at_40[0x40];
7999 };
8000
8001 struct mlx5_ifc_dealloc_uar_in_bits {
8002         u8         opcode[0x10];
8003         u8         uid[0x10];
8004
8005         u8         reserved_at_20[0x10];
8006         u8         op_mod[0x10];
8007
8008         u8         reserved_at_40[0x8];
8009         u8         uar[0x18];
8010
8011         u8         reserved_at_60[0x20];
8012 };
8013
8014 struct mlx5_ifc_dealloc_transport_domain_out_bits {
8015         u8         status[0x8];
8016         u8         reserved_at_8[0x18];
8017
8018         u8         syndrome[0x20];
8019
8020         u8         reserved_at_40[0x40];
8021 };
8022
8023 struct mlx5_ifc_dealloc_transport_domain_in_bits {
8024         u8         opcode[0x10];
8025         u8         uid[0x10];
8026
8027         u8         reserved_at_20[0x10];
8028         u8         op_mod[0x10];
8029
8030         u8         reserved_at_40[0x8];
8031         u8         transport_domain[0x18];
8032
8033         u8         reserved_at_60[0x20];
8034 };
8035
8036 struct mlx5_ifc_dealloc_q_counter_out_bits {
8037         u8         status[0x8];
8038         u8         reserved_at_8[0x18];
8039
8040         u8         syndrome[0x20];
8041
8042         u8         reserved_at_40[0x40];
8043 };
8044
8045 struct mlx5_ifc_dealloc_q_counter_in_bits {
8046         u8         opcode[0x10];
8047         u8         reserved_at_10[0x10];
8048
8049         u8         reserved_at_20[0x10];
8050         u8         op_mod[0x10];
8051
8052         u8         reserved_at_40[0x18];
8053         u8         counter_set_id[0x8];
8054
8055         u8         reserved_at_60[0x20];
8056 };
8057
8058 struct mlx5_ifc_dealloc_pd_out_bits {
8059         u8         status[0x8];
8060         u8         reserved_at_8[0x18];
8061
8062         u8         syndrome[0x20];
8063
8064         u8         reserved_at_40[0x40];
8065 };
8066
8067 struct mlx5_ifc_dealloc_pd_in_bits {
8068         u8         opcode[0x10];
8069         u8         uid[0x10];
8070
8071         u8         reserved_at_20[0x10];
8072         u8         op_mod[0x10];
8073
8074         u8         reserved_at_40[0x8];
8075         u8         pd[0x18];
8076
8077         u8         reserved_at_60[0x20];
8078 };
8079
8080 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8081         u8         status[0x8];
8082         u8         reserved_at_8[0x18];
8083
8084         u8         syndrome[0x20];
8085
8086         u8         reserved_at_40[0x40];
8087 };
8088
8089 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8090         u8         opcode[0x10];
8091         u8         reserved_at_10[0x10];
8092
8093         u8         reserved_at_20[0x10];
8094         u8         op_mod[0x10];
8095
8096         u8         flow_counter_id[0x20];
8097
8098         u8         reserved_at_60[0x20];
8099 };
8100
8101 struct mlx5_ifc_create_xrq_out_bits {
8102         u8         status[0x8];
8103         u8         reserved_at_8[0x18];
8104
8105         u8         syndrome[0x20];
8106
8107         u8         reserved_at_40[0x8];
8108         u8         xrqn[0x18];
8109
8110         u8         reserved_at_60[0x20];
8111 };
8112
8113 struct mlx5_ifc_create_xrq_in_bits {
8114         u8         opcode[0x10];
8115         u8         uid[0x10];
8116
8117         u8         reserved_at_20[0x10];
8118         u8         op_mod[0x10];
8119
8120         u8         reserved_at_40[0x40];
8121
8122         struct mlx5_ifc_xrqc_bits xrq_context;
8123 };
8124
8125 struct mlx5_ifc_create_xrc_srq_out_bits {
8126         u8         status[0x8];
8127         u8         reserved_at_8[0x18];
8128
8129         u8         syndrome[0x20];
8130
8131         u8         reserved_at_40[0x8];
8132         u8         xrc_srqn[0x18];
8133
8134         u8         reserved_at_60[0x20];
8135 };
8136
8137 struct mlx5_ifc_create_xrc_srq_in_bits {
8138         u8         opcode[0x10];
8139         u8         uid[0x10];
8140
8141         u8         reserved_at_20[0x10];
8142         u8         op_mod[0x10];
8143
8144         u8         reserved_at_40[0x40];
8145
8146         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8147
8148         u8         reserved_at_280[0x60];
8149
8150         u8         xrc_srq_umem_valid[0x1];
8151         u8         reserved_at_2e1[0x1f];
8152
8153         u8         reserved_at_300[0x580];
8154
8155         u8         pas[][0x40];
8156 };
8157
8158 struct mlx5_ifc_create_tis_out_bits {
8159         u8         status[0x8];
8160         u8         reserved_at_8[0x18];
8161
8162         u8         syndrome[0x20];
8163
8164         u8         reserved_at_40[0x8];
8165         u8         tisn[0x18];
8166
8167         u8         reserved_at_60[0x20];
8168 };
8169
8170 struct mlx5_ifc_create_tis_in_bits {
8171         u8         opcode[0x10];
8172         u8         uid[0x10];
8173
8174         u8         reserved_at_20[0x10];
8175         u8         op_mod[0x10];
8176
8177         u8         reserved_at_40[0xc0];
8178
8179         struct mlx5_ifc_tisc_bits ctx;
8180 };
8181
8182 struct mlx5_ifc_create_tir_out_bits {
8183         u8         status[0x8];
8184         u8         icm_address_63_40[0x18];
8185
8186         u8         syndrome[0x20];
8187
8188         u8         icm_address_39_32[0x8];
8189         u8         tirn[0x18];
8190
8191         u8         icm_address_31_0[0x20];
8192 };
8193
8194 struct mlx5_ifc_create_tir_in_bits {
8195         u8         opcode[0x10];
8196         u8         uid[0x10];
8197
8198         u8         reserved_at_20[0x10];
8199         u8         op_mod[0x10];
8200
8201         u8         reserved_at_40[0xc0];
8202
8203         struct mlx5_ifc_tirc_bits ctx;
8204 };
8205
8206 struct mlx5_ifc_create_srq_out_bits {
8207         u8         status[0x8];
8208         u8         reserved_at_8[0x18];
8209
8210         u8         syndrome[0x20];
8211
8212         u8         reserved_at_40[0x8];
8213         u8         srqn[0x18];
8214
8215         u8         reserved_at_60[0x20];
8216 };
8217
8218 struct mlx5_ifc_create_srq_in_bits {
8219         u8         opcode[0x10];
8220         u8         uid[0x10];
8221
8222         u8         reserved_at_20[0x10];
8223         u8         op_mod[0x10];
8224
8225         u8         reserved_at_40[0x40];
8226
8227         struct mlx5_ifc_srqc_bits srq_context_entry;
8228
8229         u8         reserved_at_280[0x600];
8230
8231         u8         pas[][0x40];
8232 };
8233
8234 struct mlx5_ifc_create_sq_out_bits {
8235         u8         status[0x8];
8236         u8         reserved_at_8[0x18];
8237
8238         u8         syndrome[0x20];
8239
8240         u8         reserved_at_40[0x8];
8241         u8         sqn[0x18];
8242
8243         u8         reserved_at_60[0x20];
8244 };
8245
8246 struct mlx5_ifc_create_sq_in_bits {
8247         u8         opcode[0x10];
8248         u8         uid[0x10];
8249
8250         u8         reserved_at_20[0x10];
8251         u8         op_mod[0x10];
8252
8253         u8         reserved_at_40[0xc0];
8254
8255         struct mlx5_ifc_sqc_bits ctx;
8256 };
8257
8258 struct mlx5_ifc_create_scheduling_element_out_bits {
8259         u8         status[0x8];
8260         u8         reserved_at_8[0x18];
8261
8262         u8         syndrome[0x20];
8263
8264         u8         reserved_at_40[0x40];
8265
8266         u8         scheduling_element_id[0x20];
8267
8268         u8         reserved_at_a0[0x160];
8269 };
8270
8271 struct mlx5_ifc_create_scheduling_element_in_bits {
8272         u8         opcode[0x10];
8273         u8         reserved_at_10[0x10];
8274
8275         u8         reserved_at_20[0x10];
8276         u8         op_mod[0x10];
8277
8278         u8         scheduling_hierarchy[0x8];
8279         u8         reserved_at_48[0x18];
8280
8281         u8         reserved_at_60[0xa0];
8282
8283         struct mlx5_ifc_scheduling_context_bits scheduling_context;
8284
8285         u8         reserved_at_300[0x100];
8286 };
8287
8288 struct mlx5_ifc_create_rqt_out_bits {
8289         u8         status[0x8];
8290         u8         reserved_at_8[0x18];
8291
8292         u8         syndrome[0x20];
8293
8294         u8         reserved_at_40[0x8];
8295         u8         rqtn[0x18];
8296
8297         u8         reserved_at_60[0x20];
8298 };
8299
8300 struct mlx5_ifc_create_rqt_in_bits {
8301         u8         opcode[0x10];
8302         u8         uid[0x10];
8303
8304         u8         reserved_at_20[0x10];
8305         u8         op_mod[0x10];
8306
8307         u8         reserved_at_40[0xc0];
8308
8309         struct mlx5_ifc_rqtc_bits rqt_context;
8310 };
8311
8312 struct mlx5_ifc_create_rq_out_bits {
8313         u8         status[0x8];
8314         u8         reserved_at_8[0x18];
8315
8316         u8         syndrome[0x20];
8317
8318         u8         reserved_at_40[0x8];
8319         u8         rqn[0x18];
8320
8321         u8         reserved_at_60[0x20];
8322 };
8323
8324 struct mlx5_ifc_create_rq_in_bits {
8325         u8         opcode[0x10];
8326         u8         uid[0x10];
8327
8328         u8         reserved_at_20[0x10];
8329         u8         op_mod[0x10];
8330
8331         u8         reserved_at_40[0xc0];
8332
8333         struct mlx5_ifc_rqc_bits ctx;
8334 };
8335
8336 struct mlx5_ifc_create_rmp_out_bits {
8337         u8         status[0x8];
8338         u8         reserved_at_8[0x18];
8339
8340         u8         syndrome[0x20];
8341
8342         u8         reserved_at_40[0x8];
8343         u8         rmpn[0x18];
8344
8345         u8         reserved_at_60[0x20];
8346 };
8347
8348 struct mlx5_ifc_create_rmp_in_bits {
8349         u8         opcode[0x10];
8350         u8         uid[0x10];
8351
8352         u8         reserved_at_20[0x10];
8353         u8         op_mod[0x10];
8354
8355         u8         reserved_at_40[0xc0];
8356
8357         struct mlx5_ifc_rmpc_bits ctx;
8358 };
8359
8360 struct mlx5_ifc_create_qp_out_bits {
8361         u8         status[0x8];
8362         u8         reserved_at_8[0x18];
8363
8364         u8         syndrome[0x20];
8365
8366         u8         reserved_at_40[0x8];
8367         u8         qpn[0x18];
8368
8369         u8         ece[0x20];
8370 };
8371
8372 struct mlx5_ifc_create_qp_in_bits {
8373         u8         opcode[0x10];
8374         u8         uid[0x10];
8375
8376         u8         reserved_at_20[0x10];
8377         u8         op_mod[0x10];
8378
8379         u8         reserved_at_40[0x8];
8380         u8         input_qpn[0x18];
8381
8382         u8         reserved_at_60[0x20];
8383         u8         opt_param_mask[0x20];
8384
8385         u8         ece[0x20];
8386
8387         struct mlx5_ifc_qpc_bits qpc;
8388
8389         u8         reserved_at_800[0x60];
8390
8391         u8         wq_umem_valid[0x1];
8392         u8         reserved_at_861[0x1f];
8393
8394         u8         pas[][0x40];
8395 };
8396
8397 struct mlx5_ifc_create_psv_out_bits {
8398         u8         status[0x8];
8399         u8         reserved_at_8[0x18];
8400
8401         u8         syndrome[0x20];
8402
8403         u8         reserved_at_40[0x40];
8404
8405         u8         reserved_at_80[0x8];
8406         u8         psv0_index[0x18];
8407
8408         u8         reserved_at_a0[0x8];
8409         u8         psv1_index[0x18];
8410
8411         u8         reserved_at_c0[0x8];
8412         u8         psv2_index[0x18];
8413
8414         u8         reserved_at_e0[0x8];
8415         u8         psv3_index[0x18];
8416 };
8417
8418 struct mlx5_ifc_create_psv_in_bits {
8419         u8         opcode[0x10];
8420         u8         reserved_at_10[0x10];
8421
8422         u8         reserved_at_20[0x10];
8423         u8         op_mod[0x10];
8424
8425         u8         num_psv[0x4];
8426         u8         reserved_at_44[0x4];
8427         u8         pd[0x18];
8428
8429         u8         reserved_at_60[0x20];
8430 };
8431
8432 struct mlx5_ifc_create_mkey_out_bits {
8433         u8         status[0x8];
8434         u8         reserved_at_8[0x18];
8435
8436         u8         syndrome[0x20];
8437
8438         u8         reserved_at_40[0x8];
8439         u8         mkey_index[0x18];
8440
8441         u8         reserved_at_60[0x20];
8442 };
8443
8444 struct mlx5_ifc_create_mkey_in_bits {
8445         u8         opcode[0x10];
8446         u8         uid[0x10];
8447
8448         u8         reserved_at_20[0x10];
8449         u8         op_mod[0x10];
8450
8451         u8         reserved_at_40[0x20];
8452
8453         u8         pg_access[0x1];
8454         u8         mkey_umem_valid[0x1];
8455         u8         reserved_at_62[0x1e];
8456
8457         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8458
8459         u8         reserved_at_280[0x80];
8460
8461         u8         translations_octword_actual_size[0x20];
8462
8463         u8         reserved_at_320[0x560];
8464
8465         u8         klm_pas_mtt[][0x20];
8466 };
8467
8468 enum {
8469         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
8470         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
8471         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
8472         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
8473         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
8474         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
8475         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
8476 };
8477
8478 struct mlx5_ifc_create_flow_table_out_bits {
8479         u8         status[0x8];
8480         u8         icm_address_63_40[0x18];
8481
8482         u8         syndrome[0x20];
8483
8484         u8         icm_address_39_32[0x8];
8485         u8         table_id[0x18];
8486
8487         u8         icm_address_31_0[0x20];
8488 };
8489
8490 struct mlx5_ifc_create_flow_table_in_bits {
8491         u8         opcode[0x10];
8492         u8         reserved_at_10[0x10];
8493
8494         u8         reserved_at_20[0x10];
8495         u8         op_mod[0x10];
8496
8497         u8         other_vport[0x1];
8498         u8         reserved_at_41[0xf];
8499         u8         vport_number[0x10];
8500
8501         u8         reserved_at_60[0x20];
8502
8503         u8         table_type[0x8];
8504         u8         reserved_at_88[0x18];
8505
8506         u8         reserved_at_a0[0x20];
8507
8508         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8509 };
8510
8511 struct mlx5_ifc_create_flow_group_out_bits {
8512         u8         status[0x8];
8513         u8         reserved_at_8[0x18];
8514
8515         u8         syndrome[0x20];
8516
8517         u8         reserved_at_40[0x8];
8518         u8         group_id[0x18];
8519
8520         u8         reserved_at_60[0x20];
8521 };
8522
8523 enum {
8524         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
8525         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
8526 };
8527
8528 enum {
8529         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8530         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8531         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8532         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8533 };
8534
8535 struct mlx5_ifc_create_flow_group_in_bits {
8536         u8         opcode[0x10];
8537         u8         reserved_at_10[0x10];
8538
8539         u8         reserved_at_20[0x10];
8540         u8         op_mod[0x10];
8541
8542         u8         other_vport[0x1];
8543         u8         reserved_at_41[0xf];
8544         u8         vport_number[0x10];
8545
8546         u8         reserved_at_60[0x20];
8547
8548         u8         table_type[0x8];
8549         u8         reserved_at_88[0x4];
8550         u8         group_type[0x4];
8551         u8         reserved_at_90[0x10];
8552
8553         u8         reserved_at_a0[0x8];
8554         u8         table_id[0x18];
8555
8556         u8         source_eswitch_owner_vhca_id_valid[0x1];
8557
8558         u8         reserved_at_c1[0x1f];
8559
8560         u8         start_flow_index[0x20];
8561
8562         u8         reserved_at_100[0x20];
8563
8564         u8         end_flow_index[0x20];
8565
8566         u8         reserved_at_140[0x10];
8567         u8         match_definer_id[0x10];
8568
8569         u8         reserved_at_160[0x80];
8570
8571         u8         reserved_at_1e0[0x18];
8572         u8         match_criteria_enable[0x8];
8573
8574         struct mlx5_ifc_fte_match_param_bits match_criteria;
8575
8576         u8         reserved_at_1200[0xe00];
8577 };
8578
8579 struct mlx5_ifc_create_eq_out_bits {
8580         u8         status[0x8];
8581         u8         reserved_at_8[0x18];
8582
8583         u8         syndrome[0x20];
8584
8585         u8         reserved_at_40[0x18];
8586         u8         eq_number[0x8];
8587
8588         u8         reserved_at_60[0x20];
8589 };
8590
8591 struct mlx5_ifc_create_eq_in_bits {
8592         u8         opcode[0x10];
8593         u8         uid[0x10];
8594
8595         u8         reserved_at_20[0x10];
8596         u8         op_mod[0x10];
8597
8598         u8         reserved_at_40[0x40];
8599
8600         struct mlx5_ifc_eqc_bits eq_context_entry;
8601
8602         u8         reserved_at_280[0x40];
8603
8604         u8         event_bitmask[4][0x40];
8605
8606         u8         reserved_at_3c0[0x4c0];
8607
8608         u8         pas[][0x40];
8609 };
8610
8611 struct mlx5_ifc_create_dct_out_bits {
8612         u8         status[0x8];
8613         u8         reserved_at_8[0x18];
8614
8615         u8         syndrome[0x20];
8616
8617         u8         reserved_at_40[0x8];
8618         u8         dctn[0x18];
8619
8620         u8         ece[0x20];
8621 };
8622
8623 struct mlx5_ifc_create_dct_in_bits {
8624         u8         opcode[0x10];
8625         u8         uid[0x10];
8626
8627         u8         reserved_at_20[0x10];
8628         u8         op_mod[0x10];
8629
8630         u8         reserved_at_40[0x40];
8631
8632         struct mlx5_ifc_dctc_bits dct_context_entry;
8633
8634         u8         reserved_at_280[0x180];
8635 };
8636
8637 struct mlx5_ifc_create_cq_out_bits {
8638         u8         status[0x8];
8639         u8         reserved_at_8[0x18];
8640
8641         u8         syndrome[0x20];
8642
8643         u8         reserved_at_40[0x8];
8644         u8         cqn[0x18];
8645
8646         u8         reserved_at_60[0x20];
8647 };
8648
8649 struct mlx5_ifc_create_cq_in_bits {
8650         u8         opcode[0x10];
8651         u8         uid[0x10];
8652
8653         u8         reserved_at_20[0x10];
8654         u8         op_mod[0x10];
8655
8656         u8         reserved_at_40[0x40];
8657
8658         struct mlx5_ifc_cqc_bits cq_context;
8659
8660         u8         reserved_at_280[0x60];
8661
8662         u8         cq_umem_valid[0x1];
8663         u8         reserved_at_2e1[0x59f];
8664
8665         u8         pas[][0x40];
8666 };
8667
8668 struct mlx5_ifc_config_int_moderation_out_bits {
8669         u8         status[0x8];
8670         u8         reserved_at_8[0x18];
8671
8672         u8         syndrome[0x20];
8673
8674         u8         reserved_at_40[0x4];
8675         u8         min_delay[0xc];
8676         u8         int_vector[0x10];
8677
8678         u8         reserved_at_60[0x20];
8679 };
8680
8681 enum {
8682         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8683         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8684 };
8685
8686 struct mlx5_ifc_config_int_moderation_in_bits {
8687         u8         opcode[0x10];
8688         u8         reserved_at_10[0x10];
8689
8690         u8         reserved_at_20[0x10];
8691         u8         op_mod[0x10];
8692
8693         u8         reserved_at_40[0x4];
8694         u8         min_delay[0xc];
8695         u8         int_vector[0x10];
8696
8697         u8         reserved_at_60[0x20];
8698 };
8699
8700 struct mlx5_ifc_attach_to_mcg_out_bits {
8701         u8         status[0x8];
8702         u8         reserved_at_8[0x18];
8703
8704         u8         syndrome[0x20];
8705
8706         u8         reserved_at_40[0x40];
8707 };
8708
8709 struct mlx5_ifc_attach_to_mcg_in_bits {
8710         u8         opcode[0x10];
8711         u8         uid[0x10];
8712
8713         u8         reserved_at_20[0x10];
8714         u8         op_mod[0x10];
8715
8716         u8         reserved_at_40[0x8];
8717         u8         qpn[0x18];
8718
8719         u8         reserved_at_60[0x20];
8720
8721         u8         multicast_gid[16][0x8];
8722 };
8723
8724 struct mlx5_ifc_arm_xrq_out_bits {
8725         u8         status[0x8];
8726         u8         reserved_at_8[0x18];
8727
8728         u8         syndrome[0x20];
8729
8730         u8         reserved_at_40[0x40];
8731 };
8732
8733 struct mlx5_ifc_arm_xrq_in_bits {
8734         u8         opcode[0x10];
8735         u8         reserved_at_10[0x10];
8736
8737         u8         reserved_at_20[0x10];
8738         u8         op_mod[0x10];
8739
8740         u8         reserved_at_40[0x8];
8741         u8         xrqn[0x18];
8742
8743         u8         reserved_at_60[0x10];
8744         u8         lwm[0x10];
8745 };
8746
8747 struct mlx5_ifc_arm_xrc_srq_out_bits {
8748         u8         status[0x8];
8749         u8         reserved_at_8[0x18];
8750
8751         u8         syndrome[0x20];
8752
8753         u8         reserved_at_40[0x40];
8754 };
8755
8756 enum {
8757         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8758 };
8759
8760 struct mlx5_ifc_arm_xrc_srq_in_bits {
8761         u8         opcode[0x10];
8762         u8         uid[0x10];
8763
8764         u8         reserved_at_20[0x10];
8765         u8         op_mod[0x10];
8766
8767         u8         reserved_at_40[0x8];
8768         u8         xrc_srqn[0x18];
8769
8770         u8         reserved_at_60[0x10];
8771         u8         lwm[0x10];
8772 };
8773
8774 struct mlx5_ifc_arm_rq_out_bits {
8775         u8         status[0x8];
8776         u8         reserved_at_8[0x18];
8777
8778         u8         syndrome[0x20];
8779
8780         u8         reserved_at_40[0x40];
8781 };
8782
8783 enum {
8784         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8785         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8786 };
8787
8788 struct mlx5_ifc_arm_rq_in_bits {
8789         u8         opcode[0x10];
8790         u8         uid[0x10];
8791
8792         u8         reserved_at_20[0x10];
8793         u8         op_mod[0x10];
8794
8795         u8         reserved_at_40[0x8];
8796         u8         srq_number[0x18];
8797
8798         u8         reserved_at_60[0x10];
8799         u8         lwm[0x10];
8800 };
8801
8802 struct mlx5_ifc_arm_dct_out_bits {
8803         u8         status[0x8];
8804         u8         reserved_at_8[0x18];
8805
8806         u8         syndrome[0x20];
8807
8808         u8         reserved_at_40[0x40];
8809 };
8810
8811 struct mlx5_ifc_arm_dct_in_bits {
8812         u8         opcode[0x10];
8813         u8         reserved_at_10[0x10];
8814
8815         u8         reserved_at_20[0x10];
8816         u8         op_mod[0x10];
8817
8818         u8         reserved_at_40[0x8];
8819         u8         dct_number[0x18];
8820
8821         u8         reserved_at_60[0x20];
8822 };
8823
8824 struct mlx5_ifc_alloc_xrcd_out_bits {
8825         u8         status[0x8];
8826         u8         reserved_at_8[0x18];
8827
8828         u8         syndrome[0x20];
8829
8830         u8         reserved_at_40[0x8];
8831         u8         xrcd[0x18];
8832
8833         u8         reserved_at_60[0x20];
8834 };
8835
8836 struct mlx5_ifc_alloc_xrcd_in_bits {
8837         u8         opcode[0x10];
8838         u8         uid[0x10];
8839
8840         u8         reserved_at_20[0x10];
8841         u8         op_mod[0x10];
8842
8843         u8         reserved_at_40[0x40];
8844 };
8845
8846 struct mlx5_ifc_alloc_uar_out_bits {
8847         u8         status[0x8];
8848         u8         reserved_at_8[0x18];
8849
8850         u8         syndrome[0x20];
8851
8852         u8         reserved_at_40[0x8];
8853         u8         uar[0x18];
8854
8855         u8         reserved_at_60[0x20];
8856 };
8857
8858 struct mlx5_ifc_alloc_uar_in_bits {
8859         u8         opcode[0x10];
8860         u8         uid[0x10];
8861
8862         u8         reserved_at_20[0x10];
8863         u8         op_mod[0x10];
8864
8865         u8         reserved_at_40[0x40];
8866 };
8867
8868 struct mlx5_ifc_alloc_transport_domain_out_bits {
8869         u8         status[0x8];
8870         u8         reserved_at_8[0x18];
8871
8872         u8         syndrome[0x20];
8873
8874         u8         reserved_at_40[0x8];
8875         u8         transport_domain[0x18];
8876
8877         u8         reserved_at_60[0x20];
8878 };
8879
8880 struct mlx5_ifc_alloc_transport_domain_in_bits {
8881         u8         opcode[0x10];
8882         u8         uid[0x10];
8883
8884         u8         reserved_at_20[0x10];
8885         u8         op_mod[0x10];
8886
8887         u8         reserved_at_40[0x40];
8888 };
8889
8890 struct mlx5_ifc_alloc_q_counter_out_bits {
8891         u8         status[0x8];
8892         u8         reserved_at_8[0x18];
8893
8894         u8         syndrome[0x20];
8895
8896         u8         reserved_at_40[0x18];
8897         u8         counter_set_id[0x8];
8898
8899         u8         reserved_at_60[0x20];
8900 };
8901
8902 struct mlx5_ifc_alloc_q_counter_in_bits {
8903         u8         opcode[0x10];
8904         u8         uid[0x10];
8905
8906         u8         reserved_at_20[0x10];
8907         u8         op_mod[0x10];
8908
8909         u8         reserved_at_40[0x40];
8910 };
8911
8912 struct mlx5_ifc_alloc_pd_out_bits {
8913         u8         status[0x8];
8914         u8         reserved_at_8[0x18];
8915
8916         u8         syndrome[0x20];
8917
8918         u8         reserved_at_40[0x8];
8919         u8         pd[0x18];
8920
8921         u8         reserved_at_60[0x20];
8922 };
8923
8924 struct mlx5_ifc_alloc_pd_in_bits {
8925         u8         opcode[0x10];
8926         u8         uid[0x10];
8927
8928         u8         reserved_at_20[0x10];
8929         u8         op_mod[0x10];
8930
8931         u8         reserved_at_40[0x40];
8932 };
8933
8934 struct mlx5_ifc_alloc_flow_counter_out_bits {
8935         u8         status[0x8];
8936         u8         reserved_at_8[0x18];
8937
8938         u8         syndrome[0x20];
8939
8940         u8         flow_counter_id[0x20];
8941
8942         u8         reserved_at_60[0x20];
8943 };
8944
8945 struct mlx5_ifc_alloc_flow_counter_in_bits {
8946         u8         opcode[0x10];
8947         u8         reserved_at_10[0x10];
8948
8949         u8         reserved_at_20[0x10];
8950         u8         op_mod[0x10];
8951
8952         u8         reserved_at_40[0x38];
8953         u8         flow_counter_bulk[0x8];
8954 };
8955
8956 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8957         u8         status[0x8];
8958         u8         reserved_at_8[0x18];
8959
8960         u8         syndrome[0x20];
8961
8962         u8         reserved_at_40[0x40];
8963 };
8964
8965 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8966         u8         opcode[0x10];
8967         u8         reserved_at_10[0x10];
8968
8969         u8         reserved_at_20[0x10];
8970         u8         op_mod[0x10];
8971
8972         u8         reserved_at_40[0x20];
8973
8974         u8         reserved_at_60[0x10];
8975         u8         vxlan_udp_port[0x10];
8976 };
8977
8978 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8979         u8         status[0x8];
8980         u8         reserved_at_8[0x18];
8981
8982         u8         syndrome[0x20];
8983
8984         u8         reserved_at_40[0x40];
8985 };
8986
8987 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8988         u8         rate_limit[0x20];
8989
8990         u8         burst_upper_bound[0x20];
8991
8992         u8         reserved_at_40[0x10];
8993         u8         typical_packet_size[0x10];
8994
8995         u8         reserved_at_60[0x120];
8996 };
8997
8998 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8999         u8         opcode[0x10];
9000         u8         uid[0x10];
9001
9002         u8         reserved_at_20[0x10];
9003         u8         op_mod[0x10];
9004
9005         u8         reserved_at_40[0x10];
9006         u8         rate_limit_index[0x10];
9007
9008         u8         reserved_at_60[0x20];
9009
9010         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9011 };
9012
9013 struct mlx5_ifc_access_register_out_bits {
9014         u8         status[0x8];
9015         u8         reserved_at_8[0x18];
9016
9017         u8         syndrome[0x20];
9018
9019         u8         reserved_at_40[0x40];
9020
9021         u8         register_data[][0x20];
9022 };
9023
9024 enum {
9025         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9026         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9027 };
9028
9029 struct mlx5_ifc_access_register_in_bits {
9030         u8         opcode[0x10];
9031         u8         reserved_at_10[0x10];
9032
9033         u8         reserved_at_20[0x10];
9034         u8         op_mod[0x10];
9035
9036         u8         reserved_at_40[0x10];
9037         u8         register_id[0x10];
9038
9039         u8         argument[0x20];
9040
9041         u8         register_data[][0x20];
9042 };
9043
9044 struct mlx5_ifc_sltp_reg_bits {
9045         u8         status[0x4];
9046         u8         version[0x4];
9047         u8         local_port[0x8];
9048         u8         pnat[0x2];
9049         u8         reserved_at_12[0x2];
9050         u8         lane[0x4];
9051         u8         reserved_at_18[0x8];
9052
9053         u8         reserved_at_20[0x20];
9054
9055         u8         reserved_at_40[0x7];
9056         u8         polarity[0x1];
9057         u8         ob_tap0[0x8];
9058         u8         ob_tap1[0x8];
9059         u8         ob_tap2[0x8];
9060
9061         u8         reserved_at_60[0xc];
9062         u8         ob_preemp_mode[0x4];
9063         u8         ob_reg[0x8];
9064         u8         ob_bias[0x8];
9065
9066         u8         reserved_at_80[0x20];
9067 };
9068
9069 struct mlx5_ifc_slrg_reg_bits {
9070         u8         status[0x4];
9071         u8         version[0x4];
9072         u8         local_port[0x8];
9073         u8         pnat[0x2];
9074         u8         reserved_at_12[0x2];
9075         u8         lane[0x4];
9076         u8         reserved_at_18[0x8];
9077
9078         u8         time_to_link_up[0x10];
9079         u8         reserved_at_30[0xc];
9080         u8         grade_lane_speed[0x4];
9081
9082         u8         grade_version[0x8];
9083         u8         grade[0x18];
9084
9085         u8         reserved_at_60[0x4];
9086         u8         height_grade_type[0x4];
9087         u8         height_grade[0x18];
9088
9089         u8         height_dz[0x10];
9090         u8         height_dv[0x10];
9091
9092         u8         reserved_at_a0[0x10];
9093         u8         height_sigma[0x10];
9094
9095         u8         reserved_at_c0[0x20];
9096
9097         u8         reserved_at_e0[0x4];
9098         u8         phase_grade_type[0x4];
9099         u8         phase_grade[0x18];
9100
9101         u8         reserved_at_100[0x8];
9102         u8         phase_eo_pos[0x8];
9103         u8         reserved_at_110[0x8];
9104         u8         phase_eo_neg[0x8];
9105
9106         u8         ffe_set_tested[0x10];
9107         u8         test_errors_per_lane[0x10];
9108 };
9109
9110 struct mlx5_ifc_pvlc_reg_bits {
9111         u8         reserved_at_0[0x8];
9112         u8         local_port[0x8];
9113         u8         reserved_at_10[0x10];
9114
9115         u8         reserved_at_20[0x1c];
9116         u8         vl_hw_cap[0x4];
9117
9118         u8         reserved_at_40[0x1c];
9119         u8         vl_admin[0x4];
9120
9121         u8         reserved_at_60[0x1c];
9122         u8         vl_operational[0x4];
9123 };
9124
9125 struct mlx5_ifc_pude_reg_bits {
9126         u8         swid[0x8];
9127         u8         local_port[0x8];
9128         u8         reserved_at_10[0x4];
9129         u8         admin_status[0x4];
9130         u8         reserved_at_18[0x4];
9131         u8         oper_status[0x4];
9132
9133         u8         reserved_at_20[0x60];
9134 };
9135
9136 struct mlx5_ifc_ptys_reg_bits {
9137         u8         reserved_at_0[0x1];
9138         u8         an_disable_admin[0x1];
9139         u8         an_disable_cap[0x1];
9140         u8         reserved_at_3[0x5];
9141         u8         local_port[0x8];
9142         u8         reserved_at_10[0xd];
9143         u8         proto_mask[0x3];
9144
9145         u8         an_status[0x4];
9146         u8         reserved_at_24[0xc];
9147         u8         data_rate_oper[0x10];
9148
9149         u8         ext_eth_proto_capability[0x20];
9150
9151         u8         eth_proto_capability[0x20];
9152
9153         u8         ib_link_width_capability[0x10];
9154         u8         ib_proto_capability[0x10];
9155
9156         u8         ext_eth_proto_admin[0x20];
9157
9158         u8         eth_proto_admin[0x20];
9159
9160         u8         ib_link_width_admin[0x10];
9161         u8         ib_proto_admin[0x10];
9162
9163         u8         ext_eth_proto_oper[0x20];
9164
9165         u8         eth_proto_oper[0x20];
9166
9167         u8         ib_link_width_oper[0x10];
9168         u8         ib_proto_oper[0x10];
9169
9170         u8         reserved_at_160[0x1c];
9171         u8         connector_type[0x4];
9172
9173         u8         eth_proto_lp_advertise[0x20];
9174
9175         u8         reserved_at_1a0[0x60];
9176 };
9177
9178 struct mlx5_ifc_mlcr_reg_bits {
9179         u8         reserved_at_0[0x8];
9180         u8         local_port[0x8];
9181         u8         reserved_at_10[0x20];
9182
9183         u8         beacon_duration[0x10];
9184         u8         reserved_at_40[0x10];
9185
9186         u8         beacon_remain[0x10];
9187 };
9188
9189 struct mlx5_ifc_ptas_reg_bits {
9190         u8         reserved_at_0[0x20];
9191
9192         u8         algorithm_options[0x10];
9193         u8         reserved_at_30[0x4];
9194         u8         repetitions_mode[0x4];
9195         u8         num_of_repetitions[0x8];
9196
9197         u8         grade_version[0x8];
9198         u8         height_grade_type[0x4];
9199         u8         phase_grade_type[0x4];
9200         u8         height_grade_weight[0x8];
9201         u8         phase_grade_weight[0x8];
9202
9203         u8         gisim_measure_bits[0x10];
9204         u8         adaptive_tap_measure_bits[0x10];
9205
9206         u8         ber_bath_high_error_threshold[0x10];
9207         u8         ber_bath_mid_error_threshold[0x10];
9208
9209         u8         ber_bath_low_error_threshold[0x10];
9210         u8         one_ratio_high_threshold[0x10];
9211
9212         u8         one_ratio_high_mid_threshold[0x10];
9213         u8         one_ratio_low_mid_threshold[0x10];
9214
9215         u8         one_ratio_low_threshold[0x10];
9216         u8         ndeo_error_threshold[0x10];
9217
9218         u8         mixer_offset_step_size[0x10];
9219         u8         reserved_at_110[0x8];
9220         u8         mix90_phase_for_voltage_bath[0x8];
9221
9222         u8         mixer_offset_start[0x10];
9223         u8         mixer_offset_end[0x10];
9224
9225         u8         reserved_at_140[0x15];
9226         u8         ber_test_time[0xb];
9227 };
9228
9229 struct mlx5_ifc_pspa_reg_bits {
9230         u8         swid[0x8];
9231         u8         local_port[0x8];
9232         u8         sub_port[0x8];
9233         u8         reserved_at_18[0x8];
9234
9235         u8         reserved_at_20[0x20];
9236 };
9237
9238 struct mlx5_ifc_pqdr_reg_bits {
9239         u8         reserved_at_0[0x8];
9240         u8         local_port[0x8];
9241         u8         reserved_at_10[0x5];
9242         u8         prio[0x3];
9243         u8         reserved_at_18[0x6];
9244         u8         mode[0x2];
9245
9246         u8         reserved_at_20[0x20];
9247
9248         u8         reserved_at_40[0x10];
9249         u8         min_threshold[0x10];
9250
9251         u8         reserved_at_60[0x10];
9252         u8         max_threshold[0x10];
9253
9254         u8         reserved_at_80[0x10];
9255         u8         mark_probability_denominator[0x10];
9256
9257         u8         reserved_at_a0[0x60];
9258 };
9259
9260 struct mlx5_ifc_ppsc_reg_bits {
9261         u8         reserved_at_0[0x8];
9262         u8         local_port[0x8];
9263         u8         reserved_at_10[0x10];
9264
9265         u8         reserved_at_20[0x60];
9266
9267         u8         reserved_at_80[0x1c];
9268         u8         wrps_admin[0x4];
9269
9270         u8         reserved_at_a0[0x1c];
9271         u8         wrps_status[0x4];
9272
9273         u8         reserved_at_c0[0x8];
9274         u8         up_threshold[0x8];
9275         u8         reserved_at_d0[0x8];
9276         u8         down_threshold[0x8];
9277
9278         u8         reserved_at_e0[0x20];
9279
9280         u8         reserved_at_100[0x1c];
9281         u8         srps_admin[0x4];
9282
9283         u8         reserved_at_120[0x1c];
9284         u8         srps_status[0x4];
9285
9286         u8         reserved_at_140[0x40];
9287 };
9288
9289 struct mlx5_ifc_pplr_reg_bits {
9290         u8         reserved_at_0[0x8];
9291         u8         local_port[0x8];
9292         u8         reserved_at_10[0x10];
9293
9294         u8         reserved_at_20[0x8];
9295         u8         lb_cap[0x8];
9296         u8         reserved_at_30[0x8];
9297         u8         lb_en[0x8];
9298 };
9299
9300 struct mlx5_ifc_pplm_reg_bits {
9301         u8         reserved_at_0[0x8];
9302         u8         local_port[0x8];
9303         u8         reserved_at_10[0x10];
9304
9305         u8         reserved_at_20[0x20];
9306
9307         u8         port_profile_mode[0x8];
9308         u8         static_port_profile[0x8];
9309         u8         active_port_profile[0x8];
9310         u8         reserved_at_58[0x8];
9311
9312         u8         retransmission_active[0x8];
9313         u8         fec_mode_active[0x18];
9314
9315         u8         rs_fec_correction_bypass_cap[0x4];
9316         u8         reserved_at_84[0x8];
9317         u8         fec_override_cap_56g[0x4];
9318         u8         fec_override_cap_100g[0x4];
9319         u8         fec_override_cap_50g[0x4];
9320         u8         fec_override_cap_25g[0x4];
9321         u8         fec_override_cap_10g_40g[0x4];
9322
9323         u8         rs_fec_correction_bypass_admin[0x4];
9324         u8         reserved_at_a4[0x8];
9325         u8         fec_override_admin_56g[0x4];
9326         u8         fec_override_admin_100g[0x4];
9327         u8         fec_override_admin_50g[0x4];
9328         u8         fec_override_admin_25g[0x4];
9329         u8         fec_override_admin_10g_40g[0x4];
9330
9331         u8         fec_override_cap_400g_8x[0x10];
9332         u8         fec_override_cap_200g_4x[0x10];
9333
9334         u8         fec_override_cap_100g_2x[0x10];
9335         u8         fec_override_cap_50g_1x[0x10];
9336
9337         u8         fec_override_admin_400g_8x[0x10];
9338         u8         fec_override_admin_200g_4x[0x10];
9339
9340         u8         fec_override_admin_100g_2x[0x10];
9341         u8         fec_override_admin_50g_1x[0x10];
9342
9343         u8         reserved_at_140[0x140];
9344 };
9345
9346 struct mlx5_ifc_ppcnt_reg_bits {
9347         u8         swid[0x8];
9348         u8         local_port[0x8];
9349         u8         pnat[0x2];
9350         u8         reserved_at_12[0x8];
9351         u8         grp[0x6];
9352
9353         u8         clr[0x1];
9354         u8         reserved_at_21[0x1c];
9355         u8         prio_tc[0x3];
9356
9357         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9358 };
9359
9360 struct mlx5_ifc_mpein_reg_bits {
9361         u8         reserved_at_0[0x2];
9362         u8         depth[0x6];
9363         u8         pcie_index[0x8];
9364         u8         node[0x8];
9365         u8         reserved_at_18[0x8];
9366
9367         u8         capability_mask[0x20];
9368
9369         u8         reserved_at_40[0x8];
9370         u8         link_width_enabled[0x8];
9371         u8         link_speed_enabled[0x10];
9372
9373         u8         lane0_physical_position[0x8];
9374         u8         link_width_active[0x8];
9375         u8         link_speed_active[0x10];
9376
9377         u8         num_of_pfs[0x10];
9378         u8         num_of_vfs[0x10];
9379
9380         u8         bdf0[0x10];
9381         u8         reserved_at_b0[0x10];
9382
9383         u8         max_read_request_size[0x4];
9384         u8         max_payload_size[0x4];
9385         u8         reserved_at_c8[0x5];
9386         u8         pwr_status[0x3];
9387         u8         port_type[0x4];
9388         u8         reserved_at_d4[0xb];
9389         u8         lane_reversal[0x1];
9390
9391         u8         reserved_at_e0[0x14];
9392         u8         pci_power[0xc];
9393
9394         u8         reserved_at_100[0x20];
9395
9396         u8         device_status[0x10];
9397         u8         port_state[0x8];
9398         u8         reserved_at_138[0x8];
9399
9400         u8         reserved_at_140[0x10];
9401         u8         receiver_detect_result[0x10];
9402
9403         u8         reserved_at_160[0x20];
9404 };
9405
9406 struct mlx5_ifc_mpcnt_reg_bits {
9407         u8         reserved_at_0[0x8];
9408         u8         pcie_index[0x8];
9409         u8         reserved_at_10[0xa];
9410         u8         grp[0x6];
9411
9412         u8         clr[0x1];
9413         u8         reserved_at_21[0x1f];
9414
9415         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9416 };
9417
9418 struct mlx5_ifc_ppad_reg_bits {
9419         u8         reserved_at_0[0x3];
9420         u8         single_mac[0x1];
9421         u8         reserved_at_4[0x4];
9422         u8         local_port[0x8];
9423         u8         mac_47_32[0x10];
9424
9425         u8         mac_31_0[0x20];
9426
9427         u8         reserved_at_40[0x40];
9428 };
9429
9430 struct mlx5_ifc_pmtu_reg_bits {
9431         u8         reserved_at_0[0x8];
9432         u8         local_port[0x8];
9433         u8         reserved_at_10[0x10];
9434
9435         u8         max_mtu[0x10];
9436         u8         reserved_at_30[0x10];
9437
9438         u8         admin_mtu[0x10];
9439         u8         reserved_at_50[0x10];
9440
9441         u8         oper_mtu[0x10];
9442         u8         reserved_at_70[0x10];
9443 };
9444
9445 struct mlx5_ifc_pmpr_reg_bits {
9446         u8         reserved_at_0[0x8];
9447         u8         module[0x8];
9448         u8         reserved_at_10[0x10];
9449
9450         u8         reserved_at_20[0x18];
9451         u8         attenuation_5g[0x8];
9452
9453         u8         reserved_at_40[0x18];
9454         u8         attenuation_7g[0x8];
9455
9456         u8         reserved_at_60[0x18];
9457         u8         attenuation_12g[0x8];
9458 };
9459
9460 struct mlx5_ifc_pmpe_reg_bits {
9461         u8         reserved_at_0[0x8];
9462         u8         module[0x8];
9463         u8         reserved_at_10[0xc];
9464         u8         module_status[0x4];
9465
9466         u8         reserved_at_20[0x60];
9467 };
9468
9469 struct mlx5_ifc_pmpc_reg_bits {
9470         u8         module_state_updated[32][0x8];
9471 };
9472
9473 struct mlx5_ifc_pmlpn_reg_bits {
9474         u8         reserved_at_0[0x4];
9475         u8         mlpn_status[0x4];
9476         u8         local_port[0x8];
9477         u8         reserved_at_10[0x10];
9478
9479         u8         e[0x1];
9480         u8         reserved_at_21[0x1f];
9481 };
9482
9483 struct mlx5_ifc_pmlp_reg_bits {
9484         u8         rxtx[0x1];
9485         u8         reserved_at_1[0x7];
9486         u8         local_port[0x8];
9487         u8         reserved_at_10[0x8];
9488         u8         width[0x8];
9489
9490         u8         lane0_module_mapping[0x20];
9491
9492         u8         lane1_module_mapping[0x20];
9493
9494         u8         lane2_module_mapping[0x20];
9495
9496         u8         lane3_module_mapping[0x20];
9497
9498         u8         reserved_at_a0[0x160];
9499 };
9500
9501 struct mlx5_ifc_pmaos_reg_bits {
9502         u8         reserved_at_0[0x8];
9503         u8         module[0x8];
9504         u8         reserved_at_10[0x4];
9505         u8         admin_status[0x4];
9506         u8         reserved_at_18[0x4];
9507         u8         oper_status[0x4];
9508
9509         u8         ase[0x1];
9510         u8         ee[0x1];
9511         u8         reserved_at_22[0x1c];
9512         u8         e[0x2];
9513
9514         u8         reserved_at_40[0x40];
9515 };
9516
9517 struct mlx5_ifc_plpc_reg_bits {
9518         u8         reserved_at_0[0x4];
9519         u8         profile_id[0xc];
9520         u8         reserved_at_10[0x4];
9521         u8         proto_mask[0x4];
9522         u8         reserved_at_18[0x8];
9523
9524         u8         reserved_at_20[0x10];
9525         u8         lane_speed[0x10];
9526
9527         u8         reserved_at_40[0x17];
9528         u8         lpbf[0x1];
9529         u8         fec_mode_policy[0x8];
9530
9531         u8         retransmission_capability[0x8];
9532         u8         fec_mode_capability[0x18];
9533
9534         u8         retransmission_support_admin[0x8];
9535         u8         fec_mode_support_admin[0x18];
9536
9537         u8         retransmission_request_admin[0x8];
9538         u8         fec_mode_request_admin[0x18];
9539
9540         u8         reserved_at_c0[0x80];
9541 };
9542
9543 struct mlx5_ifc_plib_reg_bits {
9544         u8         reserved_at_0[0x8];
9545         u8         local_port[0x8];
9546         u8         reserved_at_10[0x8];
9547         u8         ib_port[0x8];
9548
9549         u8         reserved_at_20[0x60];
9550 };
9551
9552 struct mlx5_ifc_plbf_reg_bits {
9553         u8         reserved_at_0[0x8];
9554         u8         local_port[0x8];
9555         u8         reserved_at_10[0xd];
9556         u8         lbf_mode[0x3];
9557
9558         u8         reserved_at_20[0x20];
9559 };
9560
9561 struct mlx5_ifc_pipg_reg_bits {
9562         u8         reserved_at_0[0x8];
9563         u8         local_port[0x8];
9564         u8         reserved_at_10[0x10];
9565
9566         u8         dic[0x1];
9567         u8         reserved_at_21[0x19];
9568         u8         ipg[0x4];
9569         u8         reserved_at_3e[0x2];
9570 };
9571
9572 struct mlx5_ifc_pifr_reg_bits {
9573         u8         reserved_at_0[0x8];
9574         u8         local_port[0x8];
9575         u8         reserved_at_10[0x10];
9576
9577         u8         reserved_at_20[0xe0];
9578
9579         u8         port_filter[8][0x20];
9580
9581         u8         port_filter_update_en[8][0x20];
9582 };
9583
9584 struct mlx5_ifc_pfcc_reg_bits {
9585         u8         reserved_at_0[0x8];
9586         u8         local_port[0x8];
9587         u8         reserved_at_10[0xb];
9588         u8         ppan_mask_n[0x1];
9589         u8         minor_stall_mask[0x1];
9590         u8         critical_stall_mask[0x1];
9591         u8         reserved_at_1e[0x2];
9592
9593         u8         ppan[0x4];
9594         u8         reserved_at_24[0x4];
9595         u8         prio_mask_tx[0x8];
9596         u8         reserved_at_30[0x8];
9597         u8         prio_mask_rx[0x8];
9598
9599         u8         pptx[0x1];
9600         u8         aptx[0x1];
9601         u8         pptx_mask_n[0x1];
9602         u8         reserved_at_43[0x5];
9603         u8         pfctx[0x8];
9604         u8         reserved_at_50[0x10];
9605
9606         u8         pprx[0x1];
9607         u8         aprx[0x1];
9608         u8         pprx_mask_n[0x1];
9609         u8         reserved_at_63[0x5];
9610         u8         pfcrx[0x8];
9611         u8         reserved_at_70[0x10];
9612
9613         u8         device_stall_minor_watermark[0x10];
9614         u8         device_stall_critical_watermark[0x10];
9615
9616         u8         reserved_at_a0[0x60];
9617 };
9618
9619 struct mlx5_ifc_pelc_reg_bits {
9620         u8         op[0x4];
9621         u8         reserved_at_4[0x4];
9622         u8         local_port[0x8];
9623         u8         reserved_at_10[0x10];
9624
9625         u8         op_admin[0x8];
9626         u8         op_capability[0x8];
9627         u8         op_request[0x8];
9628         u8         op_active[0x8];
9629
9630         u8         admin[0x40];
9631
9632         u8         capability[0x40];
9633
9634         u8         request[0x40];
9635
9636         u8         active[0x40];
9637
9638         u8         reserved_at_140[0x80];
9639 };
9640
9641 struct mlx5_ifc_peir_reg_bits {
9642         u8         reserved_at_0[0x8];
9643         u8         local_port[0x8];
9644         u8         reserved_at_10[0x10];
9645
9646         u8         reserved_at_20[0xc];
9647         u8         error_count[0x4];
9648         u8         reserved_at_30[0x10];
9649
9650         u8         reserved_at_40[0xc];
9651         u8         lane[0x4];
9652         u8         reserved_at_50[0x8];
9653         u8         error_type[0x8];
9654 };
9655
9656 struct mlx5_ifc_mpegc_reg_bits {
9657         u8         reserved_at_0[0x30];
9658         u8         field_select[0x10];
9659
9660         u8         tx_overflow_sense[0x1];
9661         u8         mark_cqe[0x1];
9662         u8         mark_cnp[0x1];
9663         u8         reserved_at_43[0x1b];
9664         u8         tx_lossy_overflow_oper[0x2];
9665
9666         u8         reserved_at_60[0x100];
9667 };
9668
9669 enum {
9670         MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
9671         MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
9672         MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
9673 };
9674
9675 struct mlx5_ifc_mtutc_reg_bits {
9676         u8         reserved_at_0[0x1c];
9677         u8         operation[0x4];
9678
9679         u8         freq_adjustment[0x20];
9680
9681         u8         reserved_at_40[0x40];
9682
9683         u8         utc_sec[0x20];
9684
9685         u8         reserved_at_a0[0x2];
9686         u8         utc_nsec[0x1e];
9687
9688         u8         time_adjustment[0x20];
9689 };
9690
9691 struct mlx5_ifc_pcam_enhanced_features_bits {
9692         u8         reserved_at_0[0x68];
9693         u8         fec_50G_per_lane_in_pplm[0x1];
9694         u8         reserved_at_69[0x4];
9695         u8         rx_icrc_encapsulated_counter[0x1];
9696         u8         reserved_at_6e[0x4];
9697         u8         ptys_extended_ethernet[0x1];
9698         u8         reserved_at_73[0x3];
9699         u8         pfcc_mask[0x1];
9700         u8         reserved_at_77[0x3];
9701         u8         per_lane_error_counters[0x1];
9702         u8         rx_buffer_fullness_counters[0x1];
9703         u8         ptys_connector_type[0x1];
9704         u8         reserved_at_7d[0x1];
9705         u8         ppcnt_discard_group[0x1];
9706         u8         ppcnt_statistical_group[0x1];
9707 };
9708
9709 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9710         u8         port_access_reg_cap_mask_127_to_96[0x20];
9711         u8         port_access_reg_cap_mask_95_to_64[0x20];
9712
9713         u8         port_access_reg_cap_mask_63_to_36[0x1c];
9714         u8         pplm[0x1];
9715         u8         port_access_reg_cap_mask_34_to_32[0x3];
9716
9717         u8         port_access_reg_cap_mask_31_to_13[0x13];
9718         u8         pbmc[0x1];
9719         u8         pptb[0x1];
9720         u8         port_access_reg_cap_mask_10_to_09[0x2];
9721         u8         ppcnt[0x1];
9722         u8         port_access_reg_cap_mask_07_to_00[0x8];
9723 };
9724
9725 struct mlx5_ifc_pcam_reg_bits {
9726         u8         reserved_at_0[0x8];
9727         u8         feature_group[0x8];
9728         u8         reserved_at_10[0x8];
9729         u8         access_reg_group[0x8];
9730
9731         u8         reserved_at_20[0x20];
9732
9733         union {
9734                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9735                 u8         reserved_at_0[0x80];
9736         } port_access_reg_cap_mask;
9737
9738         u8         reserved_at_c0[0x80];
9739
9740         union {
9741                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9742                 u8         reserved_at_0[0x80];
9743         } feature_cap_mask;
9744
9745         u8         reserved_at_1c0[0xc0];
9746 };
9747
9748 struct mlx5_ifc_mcam_enhanced_features_bits {
9749         u8         reserved_at_0[0x5d];
9750         u8         mcia_32dwords[0x1];
9751         u8         reserved_at_5e[0xc];
9752         u8         reset_state[0x1];
9753         u8         ptpcyc2realtime_modify[0x1];
9754         u8         reserved_at_6c[0x2];
9755         u8         pci_status_and_power[0x1];
9756         u8         reserved_at_6f[0x5];
9757         u8         mark_tx_action_cnp[0x1];
9758         u8         mark_tx_action_cqe[0x1];
9759         u8         dynamic_tx_overflow[0x1];
9760         u8         reserved_at_77[0x4];
9761         u8         pcie_outbound_stalled[0x1];
9762         u8         tx_overflow_buffer_pkt[0x1];
9763         u8         mtpps_enh_out_per_adj[0x1];
9764         u8         mtpps_fs[0x1];
9765         u8         pcie_performance_group[0x1];
9766 };
9767
9768 struct mlx5_ifc_mcam_access_reg_bits {
9769         u8         reserved_at_0[0x1c];
9770         u8         mcda[0x1];
9771         u8         mcc[0x1];
9772         u8         mcqi[0x1];
9773         u8         mcqs[0x1];
9774
9775         u8         regs_95_to_87[0x9];
9776         u8         mpegc[0x1];
9777         u8         mtutc[0x1];
9778         u8         regs_84_to_68[0x11];
9779         u8         tracer_registers[0x4];
9780
9781         u8         regs_63_to_46[0x12];
9782         u8         mrtc[0x1];
9783         u8         regs_44_to_32[0xd];
9784
9785         u8         regs_31_to_0[0x20];
9786 };
9787
9788 struct mlx5_ifc_mcam_access_reg_bits1 {
9789         u8         regs_127_to_96[0x20];
9790
9791         u8         regs_95_to_64[0x20];
9792
9793         u8         regs_63_to_32[0x20];
9794
9795         u8         regs_31_to_0[0x20];
9796 };
9797
9798 struct mlx5_ifc_mcam_access_reg_bits2 {
9799         u8         regs_127_to_99[0x1d];
9800         u8         mirc[0x1];
9801         u8         regs_97_to_96[0x2];
9802
9803         u8         regs_95_to_64[0x20];
9804
9805         u8         regs_63_to_32[0x20];
9806
9807         u8         regs_31_to_0[0x20];
9808 };
9809
9810 struct mlx5_ifc_mcam_reg_bits {
9811         u8         reserved_at_0[0x8];
9812         u8         feature_group[0x8];
9813         u8         reserved_at_10[0x8];
9814         u8         access_reg_group[0x8];
9815
9816         u8         reserved_at_20[0x20];
9817
9818         union {
9819                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9820                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9821                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9822                 u8         reserved_at_0[0x80];
9823         } mng_access_reg_cap_mask;
9824
9825         u8         reserved_at_c0[0x80];
9826
9827         union {
9828                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9829                 u8         reserved_at_0[0x80];
9830         } mng_feature_cap_mask;
9831
9832         u8         reserved_at_1c0[0x80];
9833 };
9834
9835 struct mlx5_ifc_qcam_access_reg_cap_mask {
9836         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9837         u8         qpdpm[0x1];
9838         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9839         u8         qdpm[0x1];
9840         u8         qpts[0x1];
9841         u8         qcap[0x1];
9842         u8         qcam_access_reg_cap_mask_0[0x1];
9843 };
9844
9845 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9846         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9847         u8         qpts_trust_both[0x1];
9848 };
9849
9850 struct mlx5_ifc_qcam_reg_bits {
9851         u8         reserved_at_0[0x8];
9852         u8         feature_group[0x8];
9853         u8         reserved_at_10[0x8];
9854         u8         access_reg_group[0x8];
9855         u8         reserved_at_20[0x20];
9856
9857         union {
9858                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9859                 u8  reserved_at_0[0x80];
9860         } qos_access_reg_cap_mask;
9861
9862         u8         reserved_at_c0[0x80];
9863
9864         union {
9865                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9866                 u8  reserved_at_0[0x80];
9867         } qos_feature_cap_mask;
9868
9869         u8         reserved_at_1c0[0x80];
9870 };
9871
9872 struct mlx5_ifc_core_dump_reg_bits {
9873         u8         reserved_at_0[0x18];
9874         u8         core_dump_type[0x8];
9875
9876         u8         reserved_at_20[0x30];
9877         u8         vhca_id[0x10];
9878
9879         u8         reserved_at_60[0x8];
9880         u8         qpn[0x18];
9881         u8         reserved_at_80[0x180];
9882 };
9883
9884 struct mlx5_ifc_pcap_reg_bits {
9885         u8         reserved_at_0[0x8];
9886         u8         local_port[0x8];
9887         u8         reserved_at_10[0x10];
9888
9889         u8         port_capability_mask[4][0x20];
9890 };
9891
9892 struct mlx5_ifc_paos_reg_bits {
9893         u8         swid[0x8];
9894         u8         local_port[0x8];
9895         u8         reserved_at_10[0x4];
9896         u8         admin_status[0x4];
9897         u8         reserved_at_18[0x4];
9898         u8         oper_status[0x4];
9899
9900         u8         ase[0x1];
9901         u8         ee[0x1];
9902         u8         reserved_at_22[0x1c];
9903         u8         e[0x2];
9904
9905         u8         reserved_at_40[0x40];
9906 };
9907
9908 struct mlx5_ifc_pamp_reg_bits {
9909         u8         reserved_at_0[0x8];
9910         u8         opamp_group[0x8];
9911         u8         reserved_at_10[0xc];
9912         u8         opamp_group_type[0x4];
9913
9914         u8         start_index[0x10];
9915         u8         reserved_at_30[0x4];
9916         u8         num_of_indices[0xc];
9917
9918         u8         index_data[18][0x10];
9919 };
9920
9921 struct mlx5_ifc_pcmr_reg_bits {
9922         u8         reserved_at_0[0x8];
9923         u8         local_port[0x8];
9924         u8         reserved_at_10[0x10];
9925
9926         u8         entropy_force_cap[0x1];
9927         u8         entropy_calc_cap[0x1];
9928         u8         entropy_gre_calc_cap[0x1];
9929         u8         reserved_at_23[0xf];
9930         u8         rx_ts_over_crc_cap[0x1];
9931         u8         reserved_at_33[0xb];
9932         u8         fcs_cap[0x1];
9933         u8         reserved_at_3f[0x1];
9934
9935         u8         entropy_force[0x1];
9936         u8         entropy_calc[0x1];
9937         u8         entropy_gre_calc[0x1];
9938         u8         reserved_at_43[0xf];
9939         u8         rx_ts_over_crc[0x1];
9940         u8         reserved_at_53[0xb];
9941         u8         fcs_chk[0x1];
9942         u8         reserved_at_5f[0x1];
9943 };
9944
9945 struct mlx5_ifc_lane_2_module_mapping_bits {
9946         u8         reserved_at_0[0x4];
9947         u8         rx_lane[0x4];
9948         u8         reserved_at_8[0x4];
9949         u8         tx_lane[0x4];
9950         u8         reserved_at_10[0x8];
9951         u8         module[0x8];
9952 };
9953
9954 struct mlx5_ifc_bufferx_reg_bits {
9955         u8         reserved_at_0[0x6];
9956         u8         lossy[0x1];
9957         u8         epsb[0x1];
9958         u8         reserved_at_8[0x8];
9959         u8         size[0x10];
9960
9961         u8         xoff_threshold[0x10];
9962         u8         xon_threshold[0x10];
9963 };
9964
9965 struct mlx5_ifc_set_node_in_bits {
9966         u8         node_description[64][0x8];
9967 };
9968
9969 struct mlx5_ifc_register_power_settings_bits {
9970         u8         reserved_at_0[0x18];
9971         u8         power_settings_level[0x8];
9972
9973         u8         reserved_at_20[0x60];
9974 };
9975
9976 struct mlx5_ifc_register_host_endianness_bits {
9977         u8         he[0x1];
9978         u8         reserved_at_1[0x1f];
9979
9980         u8         reserved_at_20[0x60];
9981 };
9982
9983 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9984         u8         reserved_at_0[0x20];
9985
9986         u8         mkey[0x20];
9987
9988         u8         addressh_63_32[0x20];
9989
9990         u8         addressl_31_0[0x20];
9991 };
9992
9993 struct mlx5_ifc_ud_adrs_vector_bits {
9994         u8         dc_key[0x40];
9995
9996         u8         ext[0x1];
9997         u8         reserved_at_41[0x7];
9998         u8         destination_qp_dct[0x18];
9999
10000         u8         static_rate[0x4];
10001         u8         sl_eth_prio[0x4];
10002         u8         fl[0x1];
10003         u8         mlid[0x7];
10004         u8         rlid_udp_sport[0x10];
10005
10006         u8         reserved_at_80[0x20];
10007
10008         u8         rmac_47_16[0x20];
10009
10010         u8         rmac_15_0[0x10];
10011         u8         tclass[0x8];
10012         u8         hop_limit[0x8];
10013
10014         u8         reserved_at_e0[0x1];
10015         u8         grh[0x1];
10016         u8         reserved_at_e2[0x2];
10017         u8         src_addr_index[0x8];
10018         u8         flow_label[0x14];
10019
10020         u8         rgid_rip[16][0x8];
10021 };
10022
10023 struct mlx5_ifc_pages_req_event_bits {
10024         u8         reserved_at_0[0x10];
10025         u8         function_id[0x10];
10026
10027         u8         num_pages[0x20];
10028
10029         u8         reserved_at_40[0xa0];
10030 };
10031
10032 struct mlx5_ifc_eqe_bits {
10033         u8         reserved_at_0[0x8];
10034         u8         event_type[0x8];
10035         u8         reserved_at_10[0x8];
10036         u8         event_sub_type[0x8];
10037
10038         u8         reserved_at_20[0xe0];
10039
10040         union mlx5_ifc_event_auto_bits event_data;
10041
10042         u8         reserved_at_1e0[0x10];
10043         u8         signature[0x8];
10044         u8         reserved_at_1f8[0x7];
10045         u8         owner[0x1];
10046 };
10047
10048 enum {
10049         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10050 };
10051
10052 struct mlx5_ifc_cmd_queue_entry_bits {
10053         u8         type[0x8];
10054         u8         reserved_at_8[0x18];
10055
10056         u8         input_length[0x20];
10057
10058         u8         input_mailbox_pointer_63_32[0x20];
10059
10060         u8         input_mailbox_pointer_31_9[0x17];
10061         u8         reserved_at_77[0x9];
10062
10063         u8         command_input_inline_data[16][0x8];
10064
10065         u8         command_output_inline_data[16][0x8];
10066
10067         u8         output_mailbox_pointer_63_32[0x20];
10068
10069         u8         output_mailbox_pointer_31_9[0x17];
10070         u8         reserved_at_1b7[0x9];
10071
10072         u8         output_length[0x20];
10073
10074         u8         token[0x8];
10075         u8         signature[0x8];
10076         u8         reserved_at_1f0[0x8];
10077         u8         status[0x7];
10078         u8         ownership[0x1];
10079 };
10080
10081 struct mlx5_ifc_cmd_out_bits {
10082         u8         status[0x8];
10083         u8         reserved_at_8[0x18];
10084
10085         u8         syndrome[0x20];
10086
10087         u8         command_output[0x20];
10088 };
10089
10090 struct mlx5_ifc_cmd_in_bits {
10091         u8         opcode[0x10];
10092         u8         reserved_at_10[0x10];
10093
10094         u8         reserved_at_20[0x10];
10095         u8         op_mod[0x10];
10096
10097         u8         command[][0x20];
10098 };
10099
10100 struct mlx5_ifc_cmd_if_box_bits {
10101         u8         mailbox_data[512][0x8];
10102
10103         u8         reserved_at_1000[0x180];
10104
10105         u8         next_pointer_63_32[0x20];
10106
10107         u8         next_pointer_31_10[0x16];
10108         u8         reserved_at_11b6[0xa];
10109
10110         u8         block_number[0x20];
10111
10112         u8         reserved_at_11e0[0x8];
10113         u8         token[0x8];
10114         u8         ctrl_signature[0x8];
10115         u8         signature[0x8];
10116 };
10117
10118 struct mlx5_ifc_mtt_bits {
10119         u8         ptag_63_32[0x20];
10120
10121         u8         ptag_31_8[0x18];
10122         u8         reserved_at_38[0x6];
10123         u8         wr_en[0x1];
10124         u8         rd_en[0x1];
10125 };
10126
10127 struct mlx5_ifc_query_wol_rol_out_bits {
10128         u8         status[0x8];
10129         u8         reserved_at_8[0x18];
10130
10131         u8         syndrome[0x20];
10132
10133         u8         reserved_at_40[0x10];
10134         u8         rol_mode[0x8];
10135         u8         wol_mode[0x8];
10136
10137         u8         reserved_at_60[0x20];
10138 };
10139
10140 struct mlx5_ifc_query_wol_rol_in_bits {
10141         u8         opcode[0x10];
10142         u8         reserved_at_10[0x10];
10143
10144         u8         reserved_at_20[0x10];
10145         u8         op_mod[0x10];
10146
10147         u8         reserved_at_40[0x40];
10148 };
10149
10150 struct mlx5_ifc_set_wol_rol_out_bits {
10151         u8         status[0x8];
10152         u8         reserved_at_8[0x18];
10153
10154         u8         syndrome[0x20];
10155
10156         u8         reserved_at_40[0x40];
10157 };
10158
10159 struct mlx5_ifc_set_wol_rol_in_bits {
10160         u8         opcode[0x10];
10161         u8         reserved_at_10[0x10];
10162
10163         u8         reserved_at_20[0x10];
10164         u8         op_mod[0x10];
10165
10166         u8         rol_mode_valid[0x1];
10167         u8         wol_mode_valid[0x1];
10168         u8         reserved_at_42[0xe];
10169         u8         rol_mode[0x8];
10170         u8         wol_mode[0x8];
10171
10172         u8         reserved_at_60[0x20];
10173 };
10174
10175 enum {
10176         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10177         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10178         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10179 };
10180
10181 enum {
10182         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10183         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10184         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10185 };
10186
10187 enum {
10188         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
10189         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
10190         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
10191         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
10192         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
10193         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
10194         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
10195         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
10196         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
10197         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
10198         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
10199 };
10200
10201 struct mlx5_ifc_initial_seg_bits {
10202         u8         fw_rev_minor[0x10];
10203         u8         fw_rev_major[0x10];
10204
10205         u8         cmd_interface_rev[0x10];
10206         u8         fw_rev_subminor[0x10];
10207
10208         u8         reserved_at_40[0x40];
10209
10210         u8         cmdq_phy_addr_63_32[0x20];
10211
10212         u8         cmdq_phy_addr_31_12[0x14];
10213         u8         reserved_at_b4[0x2];
10214         u8         nic_interface[0x2];
10215         u8         log_cmdq_size[0x4];
10216         u8         log_cmdq_stride[0x4];
10217
10218         u8         command_doorbell_vector[0x20];
10219
10220         u8         reserved_at_e0[0xf00];
10221
10222         u8         initializing[0x1];
10223         u8         reserved_at_fe1[0x4];
10224         u8         nic_interface_supported[0x3];
10225         u8         embedded_cpu[0x1];
10226         u8         reserved_at_fe9[0x17];
10227
10228         struct mlx5_ifc_health_buffer_bits health_buffer;
10229
10230         u8         no_dram_nic_offset[0x20];
10231
10232         u8         reserved_at_1220[0x6e40];
10233
10234         u8         reserved_at_8060[0x1f];
10235         u8         clear_int[0x1];
10236
10237         u8         health_syndrome[0x8];
10238         u8         health_counter[0x18];
10239
10240         u8         reserved_at_80a0[0x17fc0];
10241 };
10242
10243 struct mlx5_ifc_mtpps_reg_bits {
10244         u8         reserved_at_0[0xc];
10245         u8         cap_number_of_pps_pins[0x4];
10246         u8         reserved_at_10[0x4];
10247         u8         cap_max_num_of_pps_in_pins[0x4];
10248         u8         reserved_at_18[0x4];
10249         u8         cap_max_num_of_pps_out_pins[0x4];
10250
10251         u8         reserved_at_20[0x24];
10252         u8         cap_pin_3_mode[0x4];
10253         u8         reserved_at_48[0x4];
10254         u8         cap_pin_2_mode[0x4];
10255         u8         reserved_at_50[0x4];
10256         u8         cap_pin_1_mode[0x4];
10257         u8         reserved_at_58[0x4];
10258         u8         cap_pin_0_mode[0x4];
10259
10260         u8         reserved_at_60[0x4];
10261         u8         cap_pin_7_mode[0x4];
10262         u8         reserved_at_68[0x4];
10263         u8         cap_pin_6_mode[0x4];
10264         u8         reserved_at_70[0x4];
10265         u8         cap_pin_5_mode[0x4];
10266         u8         reserved_at_78[0x4];
10267         u8         cap_pin_4_mode[0x4];
10268
10269         u8         field_select[0x20];
10270         u8         reserved_at_a0[0x60];
10271
10272         u8         enable[0x1];
10273         u8         reserved_at_101[0xb];
10274         u8         pattern[0x4];
10275         u8         reserved_at_110[0x4];
10276         u8         pin_mode[0x4];
10277         u8         pin[0x8];
10278
10279         u8         reserved_at_120[0x20];
10280
10281         u8         time_stamp[0x40];
10282
10283         u8         out_pulse_duration[0x10];
10284         u8         out_periodic_adjustment[0x10];
10285         u8         enhanced_out_periodic_adjustment[0x20];
10286
10287         u8         reserved_at_1c0[0x20];
10288 };
10289
10290 struct mlx5_ifc_mtppse_reg_bits {
10291         u8         reserved_at_0[0x18];
10292         u8         pin[0x8];
10293         u8         event_arm[0x1];
10294         u8         reserved_at_21[0x1b];
10295         u8         event_generation_mode[0x4];
10296         u8         reserved_at_40[0x40];
10297 };
10298
10299 struct mlx5_ifc_mcqs_reg_bits {
10300         u8         last_index_flag[0x1];
10301         u8         reserved_at_1[0x7];
10302         u8         fw_device[0x8];
10303         u8         component_index[0x10];
10304
10305         u8         reserved_at_20[0x10];
10306         u8         identifier[0x10];
10307
10308         u8         reserved_at_40[0x17];
10309         u8         component_status[0x5];
10310         u8         component_update_state[0x4];
10311
10312         u8         last_update_state_changer_type[0x4];
10313         u8         last_update_state_changer_host_id[0x4];
10314         u8         reserved_at_68[0x18];
10315 };
10316
10317 struct mlx5_ifc_mcqi_cap_bits {
10318         u8         supported_info_bitmask[0x20];
10319
10320         u8         component_size[0x20];
10321
10322         u8         max_component_size[0x20];
10323
10324         u8         log_mcda_word_size[0x4];
10325         u8         reserved_at_64[0xc];
10326         u8         mcda_max_write_size[0x10];
10327
10328         u8         rd_en[0x1];
10329         u8         reserved_at_81[0x1];
10330         u8         match_chip_id[0x1];
10331         u8         match_psid[0x1];
10332         u8         check_user_timestamp[0x1];
10333         u8         match_base_guid_mac[0x1];
10334         u8         reserved_at_86[0x1a];
10335 };
10336
10337 struct mlx5_ifc_mcqi_version_bits {
10338         u8         reserved_at_0[0x2];
10339         u8         build_time_valid[0x1];
10340         u8         user_defined_time_valid[0x1];
10341         u8         reserved_at_4[0x14];
10342         u8         version_string_length[0x8];
10343
10344         u8         version[0x20];
10345
10346         u8         build_time[0x40];
10347
10348         u8         user_defined_time[0x40];
10349
10350         u8         build_tool_version[0x20];
10351
10352         u8         reserved_at_e0[0x20];
10353
10354         u8         version_string[92][0x8];
10355 };
10356
10357 struct mlx5_ifc_mcqi_activation_method_bits {
10358         u8         pending_server_ac_power_cycle[0x1];
10359         u8         pending_server_dc_power_cycle[0x1];
10360         u8         pending_server_reboot[0x1];
10361         u8         pending_fw_reset[0x1];
10362         u8         auto_activate[0x1];
10363         u8         all_hosts_sync[0x1];
10364         u8         device_hw_reset[0x1];
10365         u8         reserved_at_7[0x19];
10366 };
10367
10368 union mlx5_ifc_mcqi_reg_data_bits {
10369         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
10370         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
10371         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10372 };
10373
10374 struct mlx5_ifc_mcqi_reg_bits {
10375         u8         read_pending_component[0x1];
10376         u8         reserved_at_1[0xf];
10377         u8         component_index[0x10];
10378
10379         u8         reserved_at_20[0x20];
10380
10381         u8         reserved_at_40[0x1b];
10382         u8         info_type[0x5];
10383
10384         u8         info_size[0x20];
10385
10386         u8         offset[0x20];
10387
10388         u8         reserved_at_a0[0x10];
10389         u8         data_size[0x10];
10390
10391         union mlx5_ifc_mcqi_reg_data_bits data[];
10392 };
10393
10394 struct mlx5_ifc_mcc_reg_bits {
10395         u8         reserved_at_0[0x4];
10396         u8         time_elapsed_since_last_cmd[0xc];
10397         u8         reserved_at_10[0x8];
10398         u8         instruction[0x8];
10399
10400         u8         reserved_at_20[0x10];
10401         u8         component_index[0x10];
10402
10403         u8         reserved_at_40[0x8];
10404         u8         update_handle[0x18];
10405
10406         u8         handle_owner_type[0x4];
10407         u8         handle_owner_host_id[0x4];
10408         u8         reserved_at_68[0x1];
10409         u8         control_progress[0x7];
10410         u8         error_code[0x8];
10411         u8         reserved_at_78[0x4];
10412         u8         control_state[0x4];
10413
10414         u8         component_size[0x20];
10415
10416         u8         reserved_at_a0[0x60];
10417 };
10418
10419 struct mlx5_ifc_mcda_reg_bits {
10420         u8         reserved_at_0[0x8];
10421         u8         update_handle[0x18];
10422
10423         u8         offset[0x20];
10424
10425         u8         reserved_at_40[0x10];
10426         u8         size[0x10];
10427
10428         u8         reserved_at_60[0x20];
10429
10430         u8         data[][0x20];
10431 };
10432
10433 enum {
10434         MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10435         MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10436         MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10437         MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3,
10438         MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10439 };
10440
10441 enum {
10442         MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10443         MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10444 };
10445
10446 enum {
10447         MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10448         MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10449         MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10450 };
10451
10452 struct mlx5_ifc_mfrl_reg_bits {
10453         u8         reserved_at_0[0x20];
10454
10455         u8         reserved_at_20[0x2];
10456         u8         pci_sync_for_fw_update_start[0x1];
10457         u8         pci_sync_for_fw_update_resp[0x2];
10458         u8         rst_type_sel[0x3];
10459         u8         reserved_at_28[0x4];
10460         u8         reset_state[0x4];
10461         u8         reset_type[0x8];
10462         u8         reset_level[0x8];
10463 };
10464
10465 struct mlx5_ifc_mirc_reg_bits {
10466         u8         reserved_at_0[0x18];
10467         u8         status_code[0x8];
10468
10469         u8         reserved_at_20[0x20];
10470 };
10471
10472 struct mlx5_ifc_pddr_monitor_opcode_bits {
10473         u8         reserved_at_0[0x10];
10474         u8         monitor_opcode[0x10];
10475 };
10476
10477 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10478         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10479         u8         reserved_at_0[0x20];
10480 };
10481
10482 enum {
10483         /* Monitor opcodes */
10484         MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10485 };
10486
10487 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10488         u8         reserved_at_0[0x10];
10489         u8         group_opcode[0x10];
10490
10491         union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10492
10493         u8         reserved_at_40[0x20];
10494
10495         u8         status_message[59][0x20];
10496 };
10497
10498 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10499         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10500         u8         reserved_at_0[0x7c0];
10501 };
10502
10503 enum {
10504         MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10505 };
10506
10507 struct mlx5_ifc_pddr_reg_bits {
10508         u8         reserved_at_0[0x8];
10509         u8         local_port[0x8];
10510         u8         pnat[0x2];
10511         u8         reserved_at_12[0xe];
10512
10513         u8         reserved_at_20[0x18];
10514         u8         page_select[0x8];
10515
10516         union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10517 };
10518
10519 struct mlx5_ifc_mrtc_reg_bits {
10520         u8         time_synced[0x1];
10521         u8         reserved_at_1[0x1f];
10522
10523         u8         reserved_at_20[0x20];
10524
10525         u8         time_h[0x20];
10526
10527         u8         time_l[0x20];
10528 };
10529
10530 union mlx5_ifc_ports_control_registers_document_bits {
10531         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10532         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10533         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10534         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10535         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10536         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10537         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10538         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10539         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10540         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10541         struct mlx5_ifc_pamp_reg_bits pamp_reg;
10542         struct mlx5_ifc_paos_reg_bits paos_reg;
10543         struct mlx5_ifc_pcap_reg_bits pcap_reg;
10544         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10545         struct mlx5_ifc_pddr_reg_bits pddr_reg;
10546         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10547         struct mlx5_ifc_peir_reg_bits peir_reg;
10548         struct mlx5_ifc_pelc_reg_bits pelc_reg;
10549         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10550         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10551         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10552         struct mlx5_ifc_pifr_reg_bits pifr_reg;
10553         struct mlx5_ifc_pipg_reg_bits pipg_reg;
10554         struct mlx5_ifc_plbf_reg_bits plbf_reg;
10555         struct mlx5_ifc_plib_reg_bits plib_reg;
10556         struct mlx5_ifc_plpc_reg_bits plpc_reg;
10557         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10558         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10559         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10560         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10561         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10562         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10563         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10564         struct mlx5_ifc_ppad_reg_bits ppad_reg;
10565         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10566         struct mlx5_ifc_mpein_reg_bits mpein_reg;
10567         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10568         struct mlx5_ifc_pplm_reg_bits pplm_reg;
10569         struct mlx5_ifc_pplr_reg_bits pplr_reg;
10570         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10571         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10572         struct mlx5_ifc_pspa_reg_bits pspa_reg;
10573         struct mlx5_ifc_ptas_reg_bits ptas_reg;
10574         struct mlx5_ifc_ptys_reg_bits ptys_reg;
10575         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10576         struct mlx5_ifc_pude_reg_bits pude_reg;
10577         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10578         struct mlx5_ifc_slrg_reg_bits slrg_reg;
10579         struct mlx5_ifc_sltp_reg_bits sltp_reg;
10580         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10581         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
10582         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
10583         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10584         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
10585         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10586         struct mlx5_ifc_mcc_reg_bits mcc_reg;
10587         struct mlx5_ifc_mcda_reg_bits mcda_reg;
10588         struct mlx5_ifc_mirc_reg_bits mirc_reg;
10589         struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
10590         struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
10591         struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
10592         u8         reserved_at_0[0x60e0];
10593 };
10594
10595 union mlx5_ifc_debug_enhancements_document_bits {
10596         struct mlx5_ifc_health_buffer_bits health_buffer;
10597         u8         reserved_at_0[0x200];
10598 };
10599
10600 union mlx5_ifc_uplink_pci_interface_document_bits {
10601         struct mlx5_ifc_initial_seg_bits initial_seg;
10602         u8         reserved_at_0[0x20060];
10603 };
10604
10605 struct mlx5_ifc_set_flow_table_root_out_bits {
10606         u8         status[0x8];
10607         u8         reserved_at_8[0x18];
10608
10609         u8         syndrome[0x20];
10610
10611         u8         reserved_at_40[0x40];
10612 };
10613
10614 struct mlx5_ifc_set_flow_table_root_in_bits {
10615         u8         opcode[0x10];
10616         u8         reserved_at_10[0x10];
10617
10618         u8         reserved_at_20[0x10];
10619         u8         op_mod[0x10];
10620
10621         u8         other_vport[0x1];
10622         u8         reserved_at_41[0xf];
10623         u8         vport_number[0x10];
10624
10625         u8         reserved_at_60[0x20];
10626
10627         u8         table_type[0x8];
10628         u8         reserved_at_88[0x7];
10629         u8         table_of_other_vport[0x1];
10630         u8         table_vport_number[0x10];
10631
10632         u8         reserved_at_a0[0x8];
10633         u8         table_id[0x18];
10634
10635         u8         reserved_at_c0[0x8];
10636         u8         underlay_qpn[0x18];
10637         u8         table_eswitch_owner_vhca_id_valid[0x1];
10638         u8         reserved_at_e1[0xf];
10639         u8         table_eswitch_owner_vhca_id[0x10];
10640         u8         reserved_at_100[0x100];
10641 };
10642
10643 enum {
10644         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
10645         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
10646 };
10647
10648 struct mlx5_ifc_modify_flow_table_out_bits {
10649         u8         status[0x8];
10650         u8         reserved_at_8[0x18];
10651
10652         u8         syndrome[0x20];
10653
10654         u8         reserved_at_40[0x40];
10655 };
10656
10657 struct mlx5_ifc_modify_flow_table_in_bits {
10658         u8         opcode[0x10];
10659         u8         reserved_at_10[0x10];
10660
10661         u8         reserved_at_20[0x10];
10662         u8         op_mod[0x10];
10663
10664         u8         other_vport[0x1];
10665         u8         reserved_at_41[0xf];
10666         u8         vport_number[0x10];
10667
10668         u8         reserved_at_60[0x10];
10669         u8         modify_field_select[0x10];
10670
10671         u8         table_type[0x8];
10672         u8         reserved_at_88[0x18];
10673
10674         u8         reserved_at_a0[0x8];
10675         u8         table_id[0x18];
10676
10677         struct mlx5_ifc_flow_table_context_bits flow_table_context;
10678 };
10679
10680 struct mlx5_ifc_ets_tcn_config_reg_bits {
10681         u8         g[0x1];
10682         u8         b[0x1];
10683         u8         r[0x1];
10684         u8         reserved_at_3[0x9];
10685         u8         group[0x4];
10686         u8         reserved_at_10[0x9];
10687         u8         bw_allocation[0x7];
10688
10689         u8         reserved_at_20[0xc];
10690         u8         max_bw_units[0x4];
10691         u8         reserved_at_30[0x8];
10692         u8         max_bw_value[0x8];
10693 };
10694
10695 struct mlx5_ifc_ets_global_config_reg_bits {
10696         u8         reserved_at_0[0x2];
10697         u8         r[0x1];
10698         u8         reserved_at_3[0x1d];
10699
10700         u8         reserved_at_20[0xc];
10701         u8         max_bw_units[0x4];
10702         u8         reserved_at_30[0x8];
10703         u8         max_bw_value[0x8];
10704 };
10705
10706 struct mlx5_ifc_qetc_reg_bits {
10707         u8                                         reserved_at_0[0x8];
10708         u8                                         port_number[0x8];
10709         u8                                         reserved_at_10[0x30];
10710
10711         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
10712         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10713 };
10714
10715 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10716         u8         e[0x1];
10717         u8         reserved_at_01[0x0b];
10718         u8         prio[0x04];
10719 };
10720
10721 struct mlx5_ifc_qpdpm_reg_bits {
10722         u8                                     reserved_at_0[0x8];
10723         u8                                     local_port[0x8];
10724         u8                                     reserved_at_10[0x10];
10725         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10726 };
10727
10728 struct mlx5_ifc_qpts_reg_bits {
10729         u8         reserved_at_0[0x8];
10730         u8         local_port[0x8];
10731         u8         reserved_at_10[0x2d];
10732         u8         trust_state[0x3];
10733 };
10734
10735 struct mlx5_ifc_pptb_reg_bits {
10736         u8         reserved_at_0[0x2];
10737         u8         mm[0x2];
10738         u8         reserved_at_4[0x4];
10739         u8         local_port[0x8];
10740         u8         reserved_at_10[0x6];
10741         u8         cm[0x1];
10742         u8         um[0x1];
10743         u8         pm[0x8];
10744
10745         u8         prio_x_buff[0x20];
10746
10747         u8         pm_msb[0x8];
10748         u8         reserved_at_48[0x10];
10749         u8         ctrl_buff[0x4];
10750         u8         untagged_buff[0x4];
10751 };
10752
10753 struct mlx5_ifc_sbcam_reg_bits {
10754         u8         reserved_at_0[0x8];
10755         u8         feature_group[0x8];
10756         u8         reserved_at_10[0x8];
10757         u8         access_reg_group[0x8];
10758
10759         u8         reserved_at_20[0x20];
10760
10761         u8         sb_access_reg_cap_mask[4][0x20];
10762
10763         u8         reserved_at_c0[0x80];
10764
10765         u8         sb_feature_cap_mask[4][0x20];
10766
10767         u8         reserved_at_1c0[0x40];
10768
10769         u8         cap_total_buffer_size[0x20];
10770
10771         u8         cap_cell_size[0x10];
10772         u8         cap_max_pg_buffers[0x8];
10773         u8         cap_num_pool_supported[0x8];
10774
10775         u8         reserved_at_240[0x8];
10776         u8         cap_sbsr_stat_size[0x8];
10777         u8         cap_max_tclass_data[0x8];
10778         u8         cap_max_cpu_ingress_tclass_sb[0x8];
10779 };
10780
10781 struct mlx5_ifc_pbmc_reg_bits {
10782         u8         reserved_at_0[0x8];
10783         u8         local_port[0x8];
10784         u8         reserved_at_10[0x10];
10785
10786         u8         xoff_timer_value[0x10];
10787         u8         xoff_refresh[0x10];
10788
10789         u8         reserved_at_40[0x9];
10790         u8         fullness_threshold[0x7];
10791         u8         port_buffer_size[0x10];
10792
10793         struct mlx5_ifc_bufferx_reg_bits buffer[10];
10794
10795         u8         reserved_at_2e0[0x80];
10796 };
10797
10798 struct mlx5_ifc_qtct_reg_bits {
10799         u8         reserved_at_0[0x8];
10800         u8         port_number[0x8];
10801         u8         reserved_at_10[0xd];
10802         u8         prio[0x3];
10803
10804         u8         reserved_at_20[0x1d];
10805         u8         tclass[0x3];
10806 };
10807
10808 struct mlx5_ifc_mcia_reg_bits {
10809         u8         l[0x1];
10810         u8         reserved_at_1[0x7];
10811         u8         module[0x8];
10812         u8         reserved_at_10[0x8];
10813         u8         status[0x8];
10814
10815         u8         i2c_device_address[0x8];
10816         u8         page_number[0x8];
10817         u8         device_address[0x10];
10818
10819         u8         reserved_at_40[0x10];
10820         u8         size[0x10];
10821
10822         u8         reserved_at_60[0x20];
10823
10824         u8         dword_0[0x20];
10825         u8         dword_1[0x20];
10826         u8         dword_2[0x20];
10827         u8         dword_3[0x20];
10828         u8         dword_4[0x20];
10829         u8         dword_5[0x20];
10830         u8         dword_6[0x20];
10831         u8         dword_7[0x20];
10832         u8         dword_8[0x20];
10833         u8         dword_9[0x20];
10834         u8         dword_10[0x20];
10835         u8         dword_11[0x20];
10836 };
10837
10838 struct mlx5_ifc_dcbx_param_bits {
10839         u8         dcbx_cee_cap[0x1];
10840         u8         dcbx_ieee_cap[0x1];
10841         u8         dcbx_standby_cap[0x1];
10842         u8         reserved_at_3[0x5];
10843         u8         port_number[0x8];
10844         u8         reserved_at_10[0xa];
10845         u8         max_application_table_size[6];
10846         u8         reserved_at_20[0x15];
10847         u8         version_oper[0x3];
10848         u8         reserved_at_38[5];
10849         u8         version_admin[0x3];
10850         u8         willing_admin[0x1];
10851         u8         reserved_at_41[0x3];
10852         u8         pfc_cap_oper[0x4];
10853         u8         reserved_at_48[0x4];
10854         u8         pfc_cap_admin[0x4];
10855         u8         reserved_at_50[0x4];
10856         u8         num_of_tc_oper[0x4];
10857         u8         reserved_at_58[0x4];
10858         u8         num_of_tc_admin[0x4];
10859         u8         remote_willing[0x1];
10860         u8         reserved_at_61[3];
10861         u8         remote_pfc_cap[4];
10862         u8         reserved_at_68[0x14];
10863         u8         remote_num_of_tc[0x4];
10864         u8         reserved_at_80[0x18];
10865         u8         error[0x8];
10866         u8         reserved_at_a0[0x160];
10867 };
10868
10869 enum {
10870         MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
10871         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
10872         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
10873 };
10874
10875 struct mlx5_ifc_lagc_bits {
10876         u8         fdb_selection_mode[0x1];
10877         u8         reserved_at_1[0x14];
10878         u8         port_select_mode[0x3];
10879         u8         reserved_at_18[0x5];
10880         u8         lag_state[0x3];
10881
10882         u8         reserved_at_20[0x14];
10883         u8         tx_remap_affinity_2[0x4];
10884         u8         reserved_at_38[0x4];
10885         u8         tx_remap_affinity_1[0x4];
10886 };
10887
10888 struct mlx5_ifc_create_lag_out_bits {
10889         u8         status[0x8];
10890         u8         reserved_at_8[0x18];
10891
10892         u8         syndrome[0x20];
10893
10894         u8         reserved_at_40[0x40];
10895 };
10896
10897 struct mlx5_ifc_create_lag_in_bits {
10898         u8         opcode[0x10];
10899         u8         reserved_at_10[0x10];
10900
10901         u8         reserved_at_20[0x10];
10902         u8         op_mod[0x10];
10903
10904         struct mlx5_ifc_lagc_bits ctx;
10905 };
10906
10907 struct mlx5_ifc_modify_lag_out_bits {
10908         u8         status[0x8];
10909         u8         reserved_at_8[0x18];
10910
10911         u8         syndrome[0x20];
10912
10913         u8         reserved_at_40[0x40];
10914 };
10915
10916 struct mlx5_ifc_modify_lag_in_bits {
10917         u8         opcode[0x10];
10918         u8         reserved_at_10[0x10];
10919
10920         u8         reserved_at_20[0x10];
10921         u8         op_mod[0x10];
10922
10923         u8         reserved_at_40[0x20];
10924         u8         field_select[0x20];
10925
10926         struct mlx5_ifc_lagc_bits ctx;
10927 };
10928
10929 struct mlx5_ifc_query_lag_out_bits {
10930         u8         status[0x8];
10931         u8         reserved_at_8[0x18];
10932
10933         u8         syndrome[0x20];
10934
10935         struct mlx5_ifc_lagc_bits ctx;
10936 };
10937
10938 struct mlx5_ifc_query_lag_in_bits {
10939         u8         opcode[0x10];
10940         u8         reserved_at_10[0x10];
10941
10942         u8         reserved_at_20[0x10];
10943         u8         op_mod[0x10];
10944
10945         u8         reserved_at_40[0x40];
10946 };
10947
10948 struct mlx5_ifc_destroy_lag_out_bits {
10949         u8         status[0x8];
10950         u8         reserved_at_8[0x18];
10951
10952         u8         syndrome[0x20];
10953
10954         u8         reserved_at_40[0x40];
10955 };
10956
10957 struct mlx5_ifc_destroy_lag_in_bits {
10958         u8         opcode[0x10];
10959         u8         reserved_at_10[0x10];
10960
10961         u8         reserved_at_20[0x10];
10962         u8         op_mod[0x10];
10963
10964         u8         reserved_at_40[0x40];
10965 };
10966
10967 struct mlx5_ifc_create_vport_lag_out_bits {
10968         u8         status[0x8];
10969         u8         reserved_at_8[0x18];
10970
10971         u8         syndrome[0x20];
10972
10973         u8         reserved_at_40[0x40];
10974 };
10975
10976 struct mlx5_ifc_create_vport_lag_in_bits {
10977         u8         opcode[0x10];
10978         u8         reserved_at_10[0x10];
10979
10980         u8         reserved_at_20[0x10];
10981         u8         op_mod[0x10];
10982
10983         u8         reserved_at_40[0x40];
10984 };
10985
10986 struct mlx5_ifc_destroy_vport_lag_out_bits {
10987         u8         status[0x8];
10988         u8         reserved_at_8[0x18];
10989
10990         u8         syndrome[0x20];
10991
10992         u8         reserved_at_40[0x40];
10993 };
10994
10995 struct mlx5_ifc_destroy_vport_lag_in_bits {
10996         u8         opcode[0x10];
10997         u8         reserved_at_10[0x10];
10998
10999         u8         reserved_at_20[0x10];
11000         u8         op_mod[0x10];
11001
11002         u8         reserved_at_40[0x40];
11003 };
11004
11005 enum {
11006         MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11007         MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11008 };
11009
11010 struct mlx5_ifc_modify_memic_in_bits {
11011         u8         opcode[0x10];
11012         u8         uid[0x10];
11013
11014         u8         reserved_at_20[0x10];
11015         u8         op_mod[0x10];
11016
11017         u8         reserved_at_40[0x20];
11018
11019         u8         reserved_at_60[0x18];
11020         u8         memic_operation_type[0x8];
11021
11022         u8         memic_start_addr[0x40];
11023
11024         u8         reserved_at_c0[0x140];
11025 };
11026
11027 struct mlx5_ifc_modify_memic_out_bits {
11028         u8         status[0x8];
11029         u8         reserved_at_8[0x18];
11030
11031         u8         syndrome[0x20];
11032
11033         u8         reserved_at_40[0x40];
11034
11035         u8         memic_operation_addr[0x40];
11036
11037         u8         reserved_at_c0[0x140];
11038 };
11039
11040 struct mlx5_ifc_alloc_memic_in_bits {
11041         u8         opcode[0x10];
11042         u8         reserved_at_10[0x10];
11043
11044         u8         reserved_at_20[0x10];
11045         u8         op_mod[0x10];
11046
11047         u8         reserved_at_30[0x20];
11048
11049         u8         reserved_at_40[0x18];
11050         u8         log_memic_addr_alignment[0x8];
11051
11052         u8         range_start_addr[0x40];
11053
11054         u8         range_size[0x20];
11055
11056         u8         memic_size[0x20];
11057 };
11058
11059 struct mlx5_ifc_alloc_memic_out_bits {
11060         u8         status[0x8];
11061         u8         reserved_at_8[0x18];
11062
11063         u8         syndrome[0x20];
11064
11065         u8         memic_start_addr[0x40];
11066 };
11067
11068 struct mlx5_ifc_dealloc_memic_in_bits {
11069         u8         opcode[0x10];
11070         u8         reserved_at_10[0x10];
11071
11072         u8         reserved_at_20[0x10];
11073         u8         op_mod[0x10];
11074
11075         u8         reserved_at_40[0x40];
11076
11077         u8         memic_start_addr[0x40];
11078
11079         u8         memic_size[0x20];
11080
11081         u8         reserved_at_e0[0x20];
11082 };
11083
11084 struct mlx5_ifc_dealloc_memic_out_bits {
11085         u8         status[0x8];
11086         u8         reserved_at_8[0x18];
11087
11088         u8         syndrome[0x20];
11089
11090         u8         reserved_at_40[0x40];
11091 };
11092
11093 struct mlx5_ifc_umem_bits {
11094         u8         reserved_at_0[0x80];
11095
11096         u8         reserved_at_80[0x1b];
11097         u8         log_page_size[0x5];
11098
11099         u8         page_offset[0x20];
11100
11101         u8         num_of_mtt[0x40];
11102
11103         struct mlx5_ifc_mtt_bits  mtt[];
11104 };
11105
11106 struct mlx5_ifc_uctx_bits {
11107         u8         cap[0x20];
11108
11109         u8         reserved_at_20[0x160];
11110 };
11111
11112 struct mlx5_ifc_sw_icm_bits {
11113         u8         modify_field_select[0x40];
11114
11115         u8         reserved_at_40[0x18];
11116         u8         log_sw_icm_size[0x8];
11117
11118         u8         reserved_at_60[0x20];
11119
11120         u8         sw_icm_start_addr[0x40];
11121
11122         u8         reserved_at_c0[0x140];
11123 };
11124
11125 struct mlx5_ifc_geneve_tlv_option_bits {
11126         u8         modify_field_select[0x40];
11127
11128         u8         reserved_at_40[0x18];
11129         u8         geneve_option_fte_index[0x8];
11130
11131         u8         option_class[0x10];
11132         u8         option_type[0x8];
11133         u8         reserved_at_78[0x3];
11134         u8         option_data_length[0x5];
11135
11136         u8         reserved_at_80[0x180];
11137 };
11138
11139 struct mlx5_ifc_create_umem_in_bits {
11140         u8         opcode[0x10];
11141         u8         uid[0x10];
11142
11143         u8         reserved_at_20[0x10];
11144         u8         op_mod[0x10];
11145
11146         u8         reserved_at_40[0x40];
11147
11148         struct mlx5_ifc_umem_bits  umem;
11149 };
11150
11151 struct mlx5_ifc_create_umem_out_bits {
11152         u8         status[0x8];
11153         u8         reserved_at_8[0x18];
11154
11155         u8         syndrome[0x20];
11156
11157         u8         reserved_at_40[0x8];
11158         u8         umem_id[0x18];
11159
11160         u8         reserved_at_60[0x20];
11161 };
11162
11163 struct mlx5_ifc_destroy_umem_in_bits {
11164         u8        opcode[0x10];
11165         u8        uid[0x10];
11166
11167         u8        reserved_at_20[0x10];
11168         u8        op_mod[0x10];
11169
11170         u8        reserved_at_40[0x8];
11171         u8        umem_id[0x18];
11172
11173         u8        reserved_at_60[0x20];
11174 };
11175
11176 struct mlx5_ifc_destroy_umem_out_bits {
11177         u8        status[0x8];
11178         u8        reserved_at_8[0x18];
11179
11180         u8        syndrome[0x20];
11181
11182         u8        reserved_at_40[0x40];
11183 };
11184
11185 struct mlx5_ifc_create_uctx_in_bits {
11186         u8         opcode[0x10];
11187         u8         reserved_at_10[0x10];
11188
11189         u8         reserved_at_20[0x10];
11190         u8         op_mod[0x10];
11191
11192         u8         reserved_at_40[0x40];
11193
11194         struct mlx5_ifc_uctx_bits  uctx;
11195 };
11196
11197 struct mlx5_ifc_create_uctx_out_bits {
11198         u8         status[0x8];
11199         u8         reserved_at_8[0x18];
11200
11201         u8         syndrome[0x20];
11202
11203         u8         reserved_at_40[0x10];
11204         u8         uid[0x10];
11205
11206         u8         reserved_at_60[0x20];
11207 };
11208
11209 struct mlx5_ifc_destroy_uctx_in_bits {
11210         u8         opcode[0x10];
11211         u8         reserved_at_10[0x10];
11212
11213         u8         reserved_at_20[0x10];
11214         u8         op_mod[0x10];
11215
11216         u8         reserved_at_40[0x10];
11217         u8         uid[0x10];
11218
11219         u8         reserved_at_60[0x20];
11220 };
11221
11222 struct mlx5_ifc_destroy_uctx_out_bits {
11223         u8         status[0x8];
11224         u8         reserved_at_8[0x18];
11225
11226         u8         syndrome[0x20];
11227
11228         u8          reserved_at_40[0x40];
11229 };
11230
11231 struct mlx5_ifc_create_sw_icm_in_bits {
11232         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11233         struct mlx5_ifc_sw_icm_bits                   sw_icm;
11234 };
11235
11236 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11237         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11238         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
11239 };
11240
11241 struct mlx5_ifc_mtrc_string_db_param_bits {
11242         u8         string_db_base_address[0x20];
11243
11244         u8         reserved_at_20[0x8];
11245         u8         string_db_size[0x18];
11246 };
11247
11248 struct mlx5_ifc_mtrc_cap_bits {
11249         u8         trace_owner[0x1];
11250         u8         trace_to_memory[0x1];
11251         u8         reserved_at_2[0x4];
11252         u8         trc_ver[0x2];
11253         u8         reserved_at_8[0x14];
11254         u8         num_string_db[0x4];
11255
11256         u8         first_string_trace[0x8];
11257         u8         num_string_trace[0x8];
11258         u8         reserved_at_30[0x28];
11259
11260         u8         log_max_trace_buffer_size[0x8];
11261
11262         u8         reserved_at_60[0x20];
11263
11264         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11265
11266         u8         reserved_at_280[0x180];
11267 };
11268
11269 struct mlx5_ifc_mtrc_conf_bits {
11270         u8         reserved_at_0[0x1c];
11271         u8         trace_mode[0x4];
11272         u8         reserved_at_20[0x18];
11273         u8         log_trace_buffer_size[0x8];
11274         u8         trace_mkey[0x20];
11275         u8         reserved_at_60[0x3a0];
11276 };
11277
11278 struct mlx5_ifc_mtrc_stdb_bits {
11279         u8         string_db_index[0x4];
11280         u8         reserved_at_4[0x4];
11281         u8         read_size[0x18];
11282         u8         start_offset[0x20];
11283         u8         string_db_data[];
11284 };
11285
11286 struct mlx5_ifc_mtrc_ctrl_bits {
11287         u8         trace_status[0x2];
11288         u8         reserved_at_2[0x2];
11289         u8         arm_event[0x1];
11290         u8         reserved_at_5[0xb];
11291         u8         modify_field_select[0x10];
11292         u8         reserved_at_20[0x2b];
11293         u8         current_timestamp52_32[0x15];
11294         u8         current_timestamp31_0[0x20];
11295         u8         reserved_at_80[0x180];
11296 };
11297
11298 struct mlx5_ifc_host_params_context_bits {
11299         u8         host_number[0x8];
11300         u8         reserved_at_8[0x7];
11301         u8         host_pf_disabled[0x1];
11302         u8         host_num_of_vfs[0x10];
11303
11304         u8         host_total_vfs[0x10];
11305         u8         host_pci_bus[0x10];
11306
11307         u8         reserved_at_40[0x10];
11308         u8         host_pci_device[0x10];
11309
11310         u8         reserved_at_60[0x10];
11311         u8         host_pci_function[0x10];
11312
11313         u8         reserved_at_80[0x180];
11314 };
11315
11316 struct mlx5_ifc_query_esw_functions_in_bits {
11317         u8         opcode[0x10];
11318         u8         reserved_at_10[0x10];
11319
11320         u8         reserved_at_20[0x10];
11321         u8         op_mod[0x10];
11322
11323         u8         reserved_at_40[0x40];
11324 };
11325
11326 struct mlx5_ifc_query_esw_functions_out_bits {
11327         u8         status[0x8];
11328         u8         reserved_at_8[0x18];
11329
11330         u8         syndrome[0x20];
11331
11332         u8         reserved_at_40[0x40];
11333
11334         struct mlx5_ifc_host_params_context_bits host_params_context;
11335
11336         u8         reserved_at_280[0x180];
11337         u8         host_sf_enable[][0x40];
11338 };
11339
11340 struct mlx5_ifc_sf_partition_bits {
11341         u8         reserved_at_0[0x10];
11342         u8         log_num_sf[0x8];
11343         u8         log_sf_bar_size[0x8];
11344 };
11345
11346 struct mlx5_ifc_query_sf_partitions_out_bits {
11347         u8         status[0x8];
11348         u8         reserved_at_8[0x18];
11349
11350         u8         syndrome[0x20];
11351
11352         u8         reserved_at_40[0x18];
11353         u8         num_sf_partitions[0x8];
11354
11355         u8         reserved_at_60[0x20];
11356
11357         struct mlx5_ifc_sf_partition_bits sf_partition[];
11358 };
11359
11360 struct mlx5_ifc_query_sf_partitions_in_bits {
11361         u8         opcode[0x10];
11362         u8         reserved_at_10[0x10];
11363
11364         u8         reserved_at_20[0x10];
11365         u8         op_mod[0x10];
11366
11367         u8         reserved_at_40[0x40];
11368 };
11369
11370 struct mlx5_ifc_dealloc_sf_out_bits {
11371         u8         status[0x8];
11372         u8         reserved_at_8[0x18];
11373
11374         u8         syndrome[0x20];
11375
11376         u8         reserved_at_40[0x40];
11377 };
11378
11379 struct mlx5_ifc_dealloc_sf_in_bits {
11380         u8         opcode[0x10];
11381         u8         reserved_at_10[0x10];
11382
11383         u8         reserved_at_20[0x10];
11384         u8         op_mod[0x10];
11385
11386         u8         reserved_at_40[0x10];
11387         u8         function_id[0x10];
11388
11389         u8         reserved_at_60[0x20];
11390 };
11391
11392 struct mlx5_ifc_alloc_sf_out_bits {
11393         u8         status[0x8];
11394         u8         reserved_at_8[0x18];
11395
11396         u8         syndrome[0x20];
11397
11398         u8         reserved_at_40[0x40];
11399 };
11400
11401 struct mlx5_ifc_alloc_sf_in_bits {
11402         u8         opcode[0x10];
11403         u8         reserved_at_10[0x10];
11404
11405         u8         reserved_at_20[0x10];
11406         u8         op_mod[0x10];
11407
11408         u8         reserved_at_40[0x10];
11409         u8         function_id[0x10];
11410
11411         u8         reserved_at_60[0x20];
11412 };
11413
11414 struct mlx5_ifc_affiliated_event_header_bits {
11415         u8         reserved_at_0[0x10];
11416         u8         obj_type[0x10];
11417
11418         u8         obj_id[0x20];
11419 };
11420
11421 enum {
11422         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11423         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11424         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11425         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
11426 };
11427
11428 enum {
11429         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11430         MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11431         MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11432         MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
11433 };
11434
11435 enum {
11436         MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11437 };
11438
11439 struct mlx5_ifc_ipsec_obj_bits {
11440         u8         modify_field_select[0x40];
11441         u8         full_offload[0x1];
11442         u8         reserved_at_41[0x1];
11443         u8         esn_en[0x1];
11444         u8         esn_overlap[0x1];
11445         u8         reserved_at_44[0x2];
11446         u8         icv_length[0x2];
11447         u8         reserved_at_48[0x4];
11448         u8         aso_return_reg[0x4];
11449         u8         reserved_at_50[0x10];
11450
11451         u8         esn_msb[0x20];
11452
11453         u8         reserved_at_80[0x8];
11454         u8         dekn[0x18];
11455
11456         u8         salt[0x20];
11457
11458         u8         implicit_iv[0x40];
11459
11460         u8         reserved_at_100[0x700];
11461 };
11462
11463 struct mlx5_ifc_create_ipsec_obj_in_bits {
11464         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11465         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11466 };
11467
11468 enum {
11469         MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11470         MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11471 };
11472
11473 struct mlx5_ifc_query_ipsec_obj_out_bits {
11474         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11475         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11476 };
11477
11478 struct mlx5_ifc_modify_ipsec_obj_in_bits {
11479         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11480         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11481 };
11482
11483 struct mlx5_ifc_encryption_key_obj_bits {
11484         u8         modify_field_select[0x40];
11485
11486         u8         reserved_at_40[0x14];
11487         u8         key_size[0x4];
11488         u8         reserved_at_58[0x4];
11489         u8         key_type[0x4];
11490
11491         u8         reserved_at_60[0x8];
11492         u8         pd[0x18];
11493
11494         u8         reserved_at_80[0x180];
11495         u8         key[8][0x20];
11496
11497         u8         reserved_at_300[0x500];
11498 };
11499
11500 struct mlx5_ifc_create_encryption_key_in_bits {
11501         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11502         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11503 };
11504
11505 enum {
11506         MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH            = 0x0,
11507         MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2         = 0x1,
11508         MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG     = 0x2,
11509         MLX5_FLOW_METER_MODE_NUM_PACKETS                = 0x3,
11510 };
11511
11512 struct mlx5_ifc_flow_meter_parameters_bits {
11513         u8         valid[0x1];
11514         u8         bucket_overflow[0x1];
11515         u8         start_color[0x2];
11516         u8         both_buckets_on_green[0x1];
11517         u8         reserved_at_5[0x1];
11518         u8         meter_mode[0x2];
11519         u8         reserved_at_8[0x18];
11520
11521         u8         reserved_at_20[0x20];
11522
11523         u8         reserved_at_40[0x3];
11524         u8         cbs_exponent[0x5];
11525         u8         cbs_mantissa[0x8];
11526         u8         reserved_at_50[0x3];
11527         u8         cir_exponent[0x5];
11528         u8         cir_mantissa[0x8];
11529
11530         u8         reserved_at_60[0x20];
11531
11532         u8         reserved_at_80[0x3];
11533         u8         ebs_exponent[0x5];
11534         u8         ebs_mantissa[0x8];
11535         u8         reserved_at_90[0x3];
11536         u8         eir_exponent[0x5];
11537         u8         eir_mantissa[0x8];
11538
11539         u8         reserved_at_a0[0x60];
11540 };
11541
11542 struct mlx5_ifc_flow_meter_aso_obj_bits {
11543         u8         modify_field_select[0x40];
11544
11545         u8         reserved_at_40[0x40];
11546
11547         u8         reserved_at_80[0x8];
11548         u8         meter_aso_access_pd[0x18];
11549
11550         u8         reserved_at_a0[0x160];
11551
11552         struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
11553 };
11554
11555 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
11556         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11557         struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
11558 };
11559
11560 struct mlx5_ifc_sampler_obj_bits {
11561         u8         modify_field_select[0x40];
11562
11563         u8         table_type[0x8];
11564         u8         level[0x8];
11565         u8         reserved_at_50[0xf];
11566         u8         ignore_flow_level[0x1];
11567
11568         u8         sample_ratio[0x20];
11569
11570         u8         reserved_at_80[0x8];
11571         u8         sample_table_id[0x18];
11572
11573         u8         reserved_at_a0[0x8];
11574         u8         default_table_id[0x18];
11575
11576         u8         sw_steering_icm_address_rx[0x40];
11577         u8         sw_steering_icm_address_tx[0x40];
11578
11579         u8         reserved_at_140[0xa0];
11580 };
11581
11582 struct mlx5_ifc_create_sampler_obj_in_bits {
11583         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11584         struct mlx5_ifc_sampler_obj_bits sampler_object;
11585 };
11586
11587 struct mlx5_ifc_query_sampler_obj_out_bits {
11588         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11589         struct mlx5_ifc_sampler_obj_bits sampler_object;
11590 };
11591
11592 enum {
11593         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11594         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11595 };
11596
11597 enum {
11598         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11599         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
11600 };
11601
11602 struct mlx5_ifc_tls_static_params_bits {
11603         u8         const_2[0x2];
11604         u8         tls_version[0x4];
11605         u8         const_1[0x2];
11606         u8         reserved_at_8[0x14];
11607         u8         encryption_standard[0x4];
11608
11609         u8         reserved_at_20[0x20];
11610
11611         u8         initial_record_number[0x40];
11612
11613         u8         resync_tcp_sn[0x20];
11614
11615         u8         gcm_iv[0x20];
11616
11617         u8         implicit_iv[0x40];
11618
11619         u8         reserved_at_100[0x8];
11620         u8         dek_index[0x18];
11621
11622         u8         reserved_at_120[0xe0];
11623 };
11624
11625 struct mlx5_ifc_tls_progress_params_bits {
11626         u8         next_record_tcp_sn[0x20];
11627
11628         u8         hw_resync_tcp_sn[0x20];
11629
11630         u8         record_tracker_state[0x2];
11631         u8         auth_state[0x2];
11632         u8         reserved_at_44[0x4];
11633         u8         hw_offset_record_number[0x18];
11634 };
11635
11636 enum {
11637         MLX5_MTT_PERM_READ      = 1 << 0,
11638         MLX5_MTT_PERM_WRITE     = 1 << 1,
11639         MLX5_MTT_PERM_RW        = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11640 };
11641
11642 enum {
11643         MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
11644         MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
11645 };
11646
11647 struct mlx5_ifc_suspend_vhca_in_bits {
11648         u8         opcode[0x10];
11649         u8         uid[0x10];
11650
11651         u8         reserved_at_20[0x10];
11652         u8         op_mod[0x10];
11653
11654         u8         reserved_at_40[0x10];
11655         u8         vhca_id[0x10];
11656
11657         u8         reserved_at_60[0x20];
11658 };
11659
11660 struct mlx5_ifc_suspend_vhca_out_bits {
11661         u8         status[0x8];
11662         u8         reserved_at_8[0x18];
11663
11664         u8         syndrome[0x20];
11665
11666         u8         reserved_at_40[0x40];
11667 };
11668
11669 enum {
11670         MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
11671         MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
11672 };
11673
11674 struct mlx5_ifc_resume_vhca_in_bits {
11675         u8         opcode[0x10];
11676         u8         uid[0x10];
11677
11678         u8         reserved_at_20[0x10];
11679         u8         op_mod[0x10];
11680
11681         u8         reserved_at_40[0x10];
11682         u8         vhca_id[0x10];
11683
11684         u8         reserved_at_60[0x20];
11685 };
11686
11687 struct mlx5_ifc_resume_vhca_out_bits {
11688         u8         status[0x8];
11689         u8         reserved_at_8[0x18];
11690
11691         u8         syndrome[0x20];
11692
11693         u8         reserved_at_40[0x40];
11694 };
11695
11696 struct mlx5_ifc_query_vhca_migration_state_in_bits {
11697         u8         opcode[0x10];
11698         u8         uid[0x10];
11699
11700         u8         reserved_at_20[0x10];
11701         u8         op_mod[0x10];
11702
11703         u8         reserved_at_40[0x10];
11704         u8         vhca_id[0x10];
11705
11706         u8         reserved_at_60[0x20];
11707 };
11708
11709 struct mlx5_ifc_query_vhca_migration_state_out_bits {
11710         u8         status[0x8];
11711         u8         reserved_at_8[0x18];
11712
11713         u8         syndrome[0x20];
11714
11715         u8         reserved_at_40[0x40];
11716
11717         u8         required_umem_size[0x20];
11718
11719         u8         reserved_at_a0[0x160];
11720 };
11721
11722 struct mlx5_ifc_save_vhca_state_in_bits {
11723         u8         opcode[0x10];
11724         u8         uid[0x10];
11725
11726         u8         reserved_at_20[0x10];
11727         u8         op_mod[0x10];
11728
11729         u8         reserved_at_40[0x10];
11730         u8         vhca_id[0x10];
11731
11732         u8         reserved_at_60[0x20];
11733
11734         u8         va[0x40];
11735
11736         u8         mkey[0x20];
11737
11738         u8         size[0x20];
11739 };
11740
11741 struct mlx5_ifc_save_vhca_state_out_bits {
11742         u8         status[0x8];
11743         u8         reserved_at_8[0x18];
11744
11745         u8         syndrome[0x20];
11746
11747         u8         actual_image_size[0x20];
11748
11749         u8         reserved_at_60[0x20];
11750 };
11751
11752 struct mlx5_ifc_load_vhca_state_in_bits {
11753         u8         opcode[0x10];
11754         u8         uid[0x10];
11755
11756         u8         reserved_at_20[0x10];
11757         u8         op_mod[0x10];
11758
11759         u8         reserved_at_40[0x10];
11760         u8         vhca_id[0x10];
11761
11762         u8         reserved_at_60[0x20];
11763
11764         u8         va[0x40];
11765
11766         u8         mkey[0x20];
11767
11768         u8         size[0x20];
11769 };
11770
11771 struct mlx5_ifc_load_vhca_state_out_bits {
11772         u8         status[0x8];
11773         u8         reserved_at_8[0x18];
11774
11775         u8         syndrome[0x20];
11776
11777         u8         reserved_at_40[0x40];
11778 };
11779
11780 #endif /* MLX5_IFC_H */