include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  68         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  69         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  70         MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
  71 };
  72
  73 enum {
  74         MLX5_SHARED_RESOURCE_UID = 0xffff,
  75 };
  76
  77 enum {
  78         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  79 };
  80
  81 enum {
  82         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  83         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  84         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  85 };
  86
  87 enum {
  88         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  89         MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
  90         MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
  91         MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
  92         MLX5_OBJ_TYPE_MKEY = 0xff01,
  93         MLX5_OBJ_TYPE_QP = 0xff02,
  94         MLX5_OBJ_TYPE_PSV = 0xff03,
  95         MLX5_OBJ_TYPE_RMP = 0xff04,
  96         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
  97         MLX5_OBJ_TYPE_RQ = 0xff06,
  98         MLX5_OBJ_TYPE_SQ = 0xff07,
  99         MLX5_OBJ_TYPE_TIR = 0xff08,
 100         MLX5_OBJ_TYPE_TIS = 0xff09,
 101         MLX5_OBJ_TYPE_DCT = 0xff0a,
 102         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 103         MLX5_OBJ_TYPE_RQT = 0xff0e,
 104         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 105         MLX5_OBJ_TYPE_CQ = 0xff10,
 106 };
 107
 108 enum {
 109         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 110         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 111         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 112         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 113         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 114         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 115         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 116         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 117         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 118         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 119         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 120         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 121         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 122         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 123         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 124         MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
 125         MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
 126         MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
 127         MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
 128         MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
 129         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 130         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 131         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 132         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 133         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 134         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 135         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 136         MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
 137         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 138         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 139         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 140         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 141         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 142         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 143         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 144         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 145         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 146         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 147         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 148         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 149         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 150         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 151         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 152         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 153         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 154         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 155         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 156         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 157         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 158         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 159         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 160         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 161         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 162         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 163         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 164         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 165         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 166         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 167         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 168         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 169         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 170         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 171         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 172         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 173         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 174         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 175         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 176         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 177         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 178         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 179         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 180         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 181         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 182         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 183         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 184         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 185         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 186         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 187         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 188         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 189         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 190         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 191         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 192         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 193         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 194         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 195         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 196         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 197         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 198         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 199         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 200         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 201         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 202         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 203         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 204         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 205         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 206         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 207         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 208         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 209         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 210         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 211         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 212         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 213         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 214         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 215         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 216         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 217         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 218         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 219         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 220         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 221         MLX5_CMD_OP_NOP                           = 0x80d,
 222         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 223         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 224         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 225         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 226         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 227         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 228         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 229         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 230         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 231         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 232         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 233         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 234         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 235         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 236         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 237         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 238         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 239         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 240         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 241         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 242         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 243         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 244         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 245         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 246         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 247         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 248         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 249         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 250         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 251         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 252         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 253         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 254         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 255         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 256         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 257         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 258         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 259         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 260         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 261         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 262         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 263         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 264         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 265         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 266         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 267         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 268         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 269         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 270         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 271         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 272         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 273         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 274         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 275         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 276         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 277         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 278         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 279         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 280         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 281         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 282         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 283         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 284         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 285         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 286         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 287         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 288         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 289         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 290         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 291         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 292         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 293         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 294         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 295         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 296         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 297         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 298         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 299         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 300         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 301         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 302         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 303         MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
 304         MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
 305         MLX5_CMD_OP_MAX
 306 };
 307
 308 /* Valid range for general commands that don't work over an object */
 309 enum {
 310         MLX5_CMD_OP_GENERAL_START = 0xb00,
 311         MLX5_CMD_OP_GENERAL_END = 0xd00,
 312 };
 313
 314 struct mlx5_ifc_flow_table_fields_supported_bits {
 315         u8         outer_dmac[0x1];
 316         u8         outer_smac[0x1];
 317         u8         outer_ether_type[0x1];
 318         u8         outer_ip_version[0x1];
 319         u8         outer_first_prio[0x1];
 320         u8         outer_first_cfi[0x1];
 321         u8         outer_first_vid[0x1];
 322         u8         outer_ipv4_ttl[0x1];
 323         u8         outer_second_prio[0x1];
 324         u8         outer_second_cfi[0x1];
 325         u8         outer_second_vid[0x1];
 326         u8         reserved_at_b[0x1];
 327         u8         outer_sip[0x1];
 328         u8         outer_dip[0x1];
 329         u8         outer_frag[0x1];
 330         u8         outer_ip_protocol[0x1];
 331         u8         outer_ip_ecn[0x1];
 332         u8         outer_ip_dscp[0x1];
 333         u8         outer_udp_sport[0x1];
 334         u8         outer_udp_dport[0x1];
 335         u8         outer_tcp_sport[0x1];
 336         u8         outer_tcp_dport[0x1];
 337         u8         outer_tcp_flags[0x1];
 338         u8         outer_gre_protocol[0x1];
 339         u8         outer_gre_key[0x1];
 340         u8         outer_vxlan_vni[0x1];
 341         u8         outer_geneve_vni[0x1];
 342         u8         outer_geneve_oam[0x1];
 343         u8         outer_geneve_protocol_type[0x1];
 344         u8         outer_geneve_opt_len[0x1];
 345         u8         source_vhca_port[0x1];
 346         u8         source_eswitch_port[0x1];
 347
 348         u8         inner_dmac[0x1];
 349         u8         inner_smac[0x1];
 350         u8         inner_ether_type[0x1];
 351         u8         inner_ip_version[0x1];
 352         u8         inner_first_prio[0x1];
 353         u8         inner_first_cfi[0x1];
 354         u8         inner_first_vid[0x1];
 355         u8         reserved_at_27[0x1];
 356         u8         inner_second_prio[0x1];
 357         u8         inner_second_cfi[0x1];
 358         u8         inner_second_vid[0x1];
 359         u8         reserved_at_2b[0x1];
 360         u8         inner_sip[0x1];
 361         u8         inner_dip[0x1];
 362         u8         inner_frag[0x1];
 363         u8         inner_ip_protocol[0x1];
 364         u8         inner_ip_ecn[0x1];
 365         u8         inner_ip_dscp[0x1];
 366         u8         inner_udp_sport[0x1];
 367         u8         inner_udp_dport[0x1];
 368         u8         inner_tcp_sport[0x1];
 369         u8         inner_tcp_dport[0x1];
 370         u8         inner_tcp_flags[0x1];
 371         u8         reserved_at_37[0x9];
 372
 373         u8         geneve_tlv_option_0_data[0x1];
 374         u8         geneve_tlv_option_0_exist[0x1];
 375         u8         reserved_at_42[0x3];
 376         u8         outer_first_mpls_over_udp[0x4];
 377         u8         outer_first_mpls_over_gre[0x4];
 378         u8         inner_first_mpls[0x4];
 379         u8         outer_first_mpls[0x4];
 380         u8         reserved_at_55[0x2];
 381         u8         outer_esp_spi[0x1];
 382         u8         reserved_at_58[0x2];
 383         u8         bth_dst_qp[0x1];
 384         u8         reserved_at_5b[0x5];
 385
 386         u8         reserved_at_60[0x18];
 387         u8         metadata_reg_c_7[0x1];
 388         u8         metadata_reg_c_6[0x1];
 389         u8         metadata_reg_c_5[0x1];
 390         u8         metadata_reg_c_4[0x1];
 391         u8         metadata_reg_c_3[0x1];
 392         u8         metadata_reg_c_2[0x1];
 393         u8         metadata_reg_c_1[0x1];
 394         u8         metadata_reg_c_0[0x1];
 395 };
 396
 397 struct mlx5_ifc_flow_table_fields_supported_2_bits {
 398         u8         reserved_at_0[0xe];
 399         u8         bth_opcode[0x1];
 400         u8         reserved_at_f[0x11];
 401
 402         u8         reserved_at_20[0x60];
 403 };
 404
 405 struct mlx5_ifc_flow_table_prop_layout_bits {
 406         u8         ft_support[0x1];
 407         u8         reserved_at_1[0x1];
 408         u8         flow_counter[0x1];
 409         u8         flow_modify_en[0x1];
 410         u8         modify_root[0x1];
 411         u8         identified_miss_table_mode[0x1];
 412         u8         flow_table_modify[0x1];
 413         u8         reformat[0x1];
 414         u8         decap[0x1];
 415         u8         reserved_at_9[0x1];
 416         u8         pop_vlan[0x1];
 417         u8         push_vlan[0x1];
 418         u8         reserved_at_c[0x1];
 419         u8         pop_vlan_2[0x1];
 420         u8         push_vlan_2[0x1];
 421         u8         reformat_and_vlan_action[0x1];
 422         u8         reserved_at_10[0x1];
 423         u8         sw_owner[0x1];
 424         u8         reformat_l3_tunnel_to_l2[0x1];
 425         u8         reformat_l2_to_l3_tunnel[0x1];
 426         u8         reformat_and_modify_action[0x1];
 427         u8         ignore_flow_level[0x1];
 428         u8         reserved_at_16[0x1];
 429         u8         table_miss_action_domain[0x1];
 430         u8         termination_table[0x1];
 431         u8         reformat_and_fwd_to_table[0x1];
 432         u8         reserved_at_1a[0x2];
 433         u8         ipsec_encrypt[0x1];
 434         u8         ipsec_decrypt[0x1];
 435         u8         sw_owner_v2[0x1];
 436         u8         reserved_at_1f[0x1];
 437
 438         u8         termination_table_raw_traffic[0x1];
 439         u8         reserved_at_21[0x1];
 440         u8         log_max_ft_size[0x6];
 441         u8         log_max_modify_header_context[0x8];
 442         u8         max_modify_header_actions[0x8];
 443         u8         max_ft_level[0x8];
 444
 445         u8         reserved_at_40[0x20];
 446
 447         u8         reserved_at_60[0x2];
 448         u8         reformat_insert[0x1];
 449         u8         reformat_remove[0x1];
 450         u8         reserver_at_64[0x14];
 451         u8         log_max_ft_num[0x8];
 452
 453         u8         reserved_at_80[0x10];
 454         u8         log_max_flow_counter[0x8];
 455         u8         log_max_destination[0x8];
 456
 457         u8         reserved_at_a0[0x18];
 458         u8         log_max_flow[0x8];
 459
 460         u8         reserved_at_c0[0x40];
 461
 462         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 463
 464         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 465 };
 466
 467 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 468         u8         send[0x1];
 469         u8         receive[0x1];
 470         u8         write[0x1];
 471         u8         read[0x1];
 472         u8         atomic[0x1];
 473         u8         srq_receive[0x1];
 474         u8         reserved_at_6[0x1a];
 475 };
 476
 477 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 478         u8         smac_47_16[0x20];
 479
 480         u8         smac_15_0[0x10];
 481         u8         ethertype[0x10];
 482
 483         u8         dmac_47_16[0x20];
 484
 485         u8         dmac_15_0[0x10];
 486         u8         first_prio[0x3];
 487         u8         first_cfi[0x1];
 488         u8         first_vid[0xc];
 489
 490         u8         ip_protocol[0x8];
 491         u8         ip_dscp[0x6];
 492         u8         ip_ecn[0x2];
 493         u8         cvlan_tag[0x1];
 494         u8         svlan_tag[0x1];
 495         u8         frag[0x1];
 496         u8         ip_version[0x4];
 497         u8         tcp_flags[0x9];
 498
 499         u8         tcp_sport[0x10];
 500         u8         tcp_dport[0x10];
 501
 502         u8         reserved_at_c0[0x10];
 503         u8         ipv4_ihl[0x4];
 504         u8         reserved_at_c4[0x4];
 505
 506         u8         ttl_hoplimit[0x8];
 507
 508         u8         udp_sport[0x10];
 509         u8         udp_dport[0x10];
 510
 511         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 512
 513         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 514 };
 515
 516 struct mlx5_ifc_nvgre_key_bits {
 517         u8 hi[0x18];
 518         u8 lo[0x8];
 519 };
 520
 521 union mlx5_ifc_gre_key_bits {
 522         struct mlx5_ifc_nvgre_key_bits nvgre;
 523         u8 key[0x20];
 524 };
 525
 526 struct mlx5_ifc_fte_match_set_misc_bits {
 527         u8         gre_c_present[0x1];
 528         u8         reserved_at_1[0x1];
 529         u8         gre_k_present[0x1];
 530         u8         gre_s_present[0x1];
 531         u8         source_vhca_port[0x4];
 532         u8         source_sqn[0x18];
 533
 534         u8         source_eswitch_owner_vhca_id[0x10];
 535         u8         source_port[0x10];
 536
 537         u8         outer_second_prio[0x3];
 538         u8         outer_second_cfi[0x1];
 539         u8         outer_second_vid[0xc];
 540         u8         inner_second_prio[0x3];
 541         u8         inner_second_cfi[0x1];
 542         u8         inner_second_vid[0xc];
 543
 544         u8         outer_second_cvlan_tag[0x1];
 545         u8         inner_second_cvlan_tag[0x1];
 546         u8         outer_second_svlan_tag[0x1];
 547         u8         inner_second_svlan_tag[0x1];
 548         u8         reserved_at_64[0xc];
 549         u8         gre_protocol[0x10];
 550
 551         union mlx5_ifc_gre_key_bits gre_key;
 552
 553         u8         vxlan_vni[0x18];
 554         u8         bth_opcode[0x8];
 555
 556         u8         geneve_vni[0x18];
 557         u8         reserved_at_d8[0x6];
 558         u8         geneve_tlv_option_0_exist[0x1];
 559         u8         geneve_oam[0x1];
 560
 561         u8         reserved_at_e0[0xc];
 562         u8         outer_ipv6_flow_label[0x14];
 563
 564         u8         reserved_at_100[0xc];
 565         u8         inner_ipv6_flow_label[0x14];
 566
 567         u8         reserved_at_120[0xa];
 568         u8         geneve_opt_len[0x6];
 569         u8         geneve_protocol_type[0x10];
 570
 571         u8         reserved_at_140[0x8];
 572         u8         bth_dst_qp[0x18];
 573         u8         reserved_at_160[0x20];
 574         u8         outer_esp_spi[0x20];
 575         u8         reserved_at_1a0[0x60];
 576 };
 577
 578 struct mlx5_ifc_fte_match_mpls_bits {
 579         u8         mpls_label[0x14];
 580         u8         mpls_exp[0x3];
 581         u8         mpls_s_bos[0x1];
 582         u8         mpls_ttl[0x8];
 583 };
 584
 585 struct mlx5_ifc_fte_match_set_misc2_bits {
 586         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 587
 588         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 589
 590         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 591
 592         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 593
 594         u8         metadata_reg_c_7[0x20];
 595
 596         u8         metadata_reg_c_6[0x20];
 597
 598         u8         metadata_reg_c_5[0x20];
 599
 600         u8         metadata_reg_c_4[0x20];
 601
 602         u8         metadata_reg_c_3[0x20];
 603
 604         u8         metadata_reg_c_2[0x20];
 605
 606         u8         metadata_reg_c_1[0x20];
 607
 608         u8         metadata_reg_c_0[0x20];
 609
 610         u8         metadata_reg_a[0x20];
 611
 612         u8         reserved_at_1a0[0x60];
 613 };
 614
 615 struct mlx5_ifc_fte_match_set_misc3_bits {
 616         u8         inner_tcp_seq_num[0x20];
 617
 618         u8         outer_tcp_seq_num[0x20];
 619
 620         u8         inner_tcp_ack_num[0x20];
 621
 622         u8         outer_tcp_ack_num[0x20];
 623
 624         u8         reserved_at_80[0x8];
 625         u8         outer_vxlan_gpe_vni[0x18];
 626
 627         u8         outer_vxlan_gpe_next_protocol[0x8];
 628         u8         outer_vxlan_gpe_flags[0x8];
 629         u8         reserved_at_b0[0x10];
 630
 631         u8         icmp_header_data[0x20];
 632
 633         u8         icmpv6_header_data[0x20];
 634
 635         u8         icmp_type[0x8];
 636         u8         icmp_code[0x8];
 637         u8         icmpv6_type[0x8];
 638         u8         icmpv6_code[0x8];
 639
 640         u8         geneve_tlv_option_0_data[0x20];
 641
 642         u8         gtpu_teid[0x20];
 643
 644         u8         gtpu_msg_type[0x8];
 645         u8         gtpu_msg_flags[0x8];
 646         u8         reserved_at_170[0x10];
 647
 648         u8         gtpu_dw_2[0x20];
 649
 650         u8         gtpu_first_ext_dw_0[0x20];
 651
 652         u8         gtpu_dw_0[0x20];
 653
 654         u8         reserved_at_1e0[0x20];
 655 };
 656
 657 struct mlx5_ifc_fte_match_set_misc4_bits {
 658         u8         prog_sample_field_value_0[0x20];
 659
 660         u8         prog_sample_field_id_0[0x20];
 661
 662         u8         prog_sample_field_value_1[0x20];
 663
 664         u8         prog_sample_field_id_1[0x20];
 665
 666         u8         prog_sample_field_value_2[0x20];
 667
 668         u8         prog_sample_field_id_2[0x20];
 669
 670         u8         prog_sample_field_value_3[0x20];
 671
 672         u8         prog_sample_field_id_3[0x20];
 673
 674         u8         reserved_at_100[0x100];
 675 };
 676
 677 struct mlx5_ifc_fte_match_set_misc5_bits {
 678         u8         macsec_tag_0[0x20];
 679
 680         u8         macsec_tag_1[0x20];
 681
 682         u8         macsec_tag_2[0x20];
 683
 684         u8         macsec_tag_3[0x20];
 685
 686         u8         tunnel_header_0[0x20];
 687
 688         u8         tunnel_header_1[0x20];
 689
 690         u8         tunnel_header_2[0x20];
 691
 692         u8         tunnel_header_3[0x20];
 693
 694         u8         reserved_at_100[0x100];
 695 };
 696
 697 struct mlx5_ifc_cmd_pas_bits {
 698         u8         pa_h[0x20];
 699
 700         u8         pa_l[0x14];
 701         u8         reserved_at_34[0xc];
 702 };
 703
 704 struct mlx5_ifc_uint64_bits {
 705         u8         hi[0x20];
 706
 707         u8         lo[0x20];
 708 };
 709
 710 enum {
 711         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 712         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 713         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 714         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 715         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 716         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 717         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 718         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 719         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 720         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 721 };
 722
 723 struct mlx5_ifc_ads_bits {
 724         u8         fl[0x1];
 725         u8         free_ar[0x1];
 726         u8         reserved_at_2[0xe];
 727         u8         pkey_index[0x10];
 728
 729         u8         reserved_at_20[0x8];
 730         u8         grh[0x1];
 731         u8         mlid[0x7];
 732         u8         rlid[0x10];
 733
 734         u8         ack_timeout[0x5];
 735         u8         reserved_at_45[0x3];
 736         u8         src_addr_index[0x8];
 737         u8         reserved_at_50[0x4];
 738         u8         stat_rate[0x4];
 739         u8         hop_limit[0x8];
 740
 741         u8         reserved_at_60[0x4];
 742         u8         tclass[0x8];
 743         u8         flow_label[0x14];
 744
 745         u8         rgid_rip[16][0x8];
 746
 747         u8         reserved_at_100[0x4];
 748         u8         f_dscp[0x1];
 749         u8         f_ecn[0x1];
 750         u8         reserved_at_106[0x1];
 751         u8         f_eth_prio[0x1];
 752         u8         ecn[0x2];
 753         u8         dscp[0x6];
 754         u8         udp_sport[0x10];
 755
 756         u8         dei_cfi[0x1];
 757         u8         eth_prio[0x3];
 758         u8         sl[0x4];
 759         u8         vhca_port_num[0x8];
 760         u8         rmac_47_32[0x10];
 761
 762         u8         rmac_31_0[0x20];
 763 };
 764
 765 struct mlx5_ifc_flow_table_nic_cap_bits {
 766         u8         nic_rx_multi_path_tirs[0x1];
 767         u8         nic_rx_multi_path_tirs_fts[0x1];
 768         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 769         u8         reserved_at_3[0x4];
 770         u8         sw_owner_reformat_supported[0x1];
 771         u8         reserved_at_8[0x18];
 772
 773         u8         encap_general_header[0x1];
 774         u8         reserved_at_21[0xa];
 775         u8         log_max_packet_reformat_context[0x5];
 776         u8         reserved_at_30[0x6];
 777         u8         max_encap_header_size[0xa];
 778         u8         reserved_at_40[0x1c0];
 779
 780         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 781
 782         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 783
 784         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 785
 786         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 787
 788         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 789
 790         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 791
 792         u8         reserved_at_e00[0x700];
 793
 794         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
 795
 796         u8         reserved_at_1580[0x280];
 797
 798         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
 799
 800         u8         reserved_at_1880[0x780];
 801
 802         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 803
 804         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 805
 806         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 807
 808         u8         reserved_at_20c0[0x5f40];
 809 };
 810
 811 struct mlx5_ifc_port_selection_cap_bits {
 812         u8         reserved_at_0[0x10];
 813         u8         port_select_flow_table[0x1];
 814         u8         reserved_at_11[0xf];
 815
 816         u8         reserved_at_20[0x1e0];
 817
 818         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
 819
 820         u8         reserved_at_400[0x7c00];
 821 };
 822
 823 enum {
 824         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 825         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 826         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 827         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 828         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 829         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 830         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 831         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 832 };
 833
 834 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 835         u8      fdb_to_vport_reg_c_id[0x8];
 836         u8      reserved_at_8[0xd];
 837         u8      fdb_modify_header_fwd_to_table[0x1];
 838         u8      fdb_ipv4_ttl_modify[0x1];
 839         u8      flow_source[0x1];
 840         u8      reserved_at_18[0x2];
 841         u8      multi_fdb_encap[0x1];
 842         u8      egress_acl_forward_to_vport[0x1];
 843         u8      fdb_multi_path_to_table[0x1];
 844         u8      reserved_at_1d[0x3];
 845
 846         u8      reserved_at_20[0x1e0];
 847
 848         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 849
 850         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 851
 852         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 853
 854         u8      reserved_at_800[0x1000];
 855
 856         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 857
 858         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 859
 860         u8      sw_steering_uplink_icm_address_rx[0x40];
 861
 862         u8      sw_steering_uplink_icm_address_tx[0x40];
 863
 864         u8      reserved_at_1900[0x6700];
 865 };
 866
 867 enum {
 868         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 869         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 870 };
 871
 872 struct mlx5_ifc_e_switch_cap_bits {
 873         u8         vport_svlan_strip[0x1];
 874         u8         vport_cvlan_strip[0x1];
 875         u8         vport_svlan_insert[0x1];
 876         u8         vport_cvlan_insert_if_not_exist[0x1];
 877         u8         vport_cvlan_insert_overwrite[0x1];
 878         u8         reserved_at_5[0x2];
 879         u8         esw_shared_ingress_acl[0x1];
 880         u8         esw_uplink_ingress_acl[0x1];
 881         u8         root_ft_on_other_esw[0x1];
 882         u8         reserved_at_a[0xf];
 883         u8         esw_functions_changed[0x1];
 884         u8         reserved_at_1a[0x1];
 885         u8         ecpf_vport_exists[0x1];
 886         u8         counter_eswitch_affinity[0x1];
 887         u8         merged_eswitch[0x1];
 888         u8         nic_vport_node_guid_modify[0x1];
 889         u8         nic_vport_port_guid_modify[0x1];
 890
 891         u8         vxlan_encap_decap[0x1];
 892         u8         nvgre_encap_decap[0x1];
 893         u8         reserved_at_22[0x1];
 894         u8         log_max_fdb_encap_uplink[0x5];
 895         u8         reserved_at_21[0x3];
 896         u8         log_max_packet_reformat_context[0x5];
 897         u8         reserved_2b[0x6];
 898         u8         max_encap_header_size[0xa];
 899
 900         u8         reserved_at_40[0xb];
 901         u8         log_max_esw_sf[0x5];
 902         u8         esw_sf_base_id[0x10];
 903
 904         u8         reserved_at_60[0x7a0];
 905
 906 };
 907
 908 struct mlx5_ifc_qos_cap_bits {
 909         u8         packet_pacing[0x1];
 910         u8         esw_scheduling[0x1];
 911         u8         esw_bw_share[0x1];
 912         u8         esw_rate_limit[0x1];
 913         u8         reserved_at_4[0x1];
 914         u8         packet_pacing_burst_bound[0x1];
 915         u8         packet_pacing_typical_size[0x1];
 916         u8         reserved_at_7[0x1];
 917         u8         nic_sq_scheduling[0x1];
 918         u8         nic_bw_share[0x1];
 919         u8         nic_rate_limit[0x1];
 920         u8         packet_pacing_uid[0x1];
 921         u8         log_esw_max_sched_depth[0x4];
 922         u8         reserved_at_10[0x10];
 923
 924         u8         reserved_at_20[0xb];
 925         u8         log_max_qos_nic_queue_group[0x5];
 926         u8         reserved_at_30[0x10];
 927
 928         u8         packet_pacing_max_rate[0x20];
 929
 930         u8         packet_pacing_min_rate[0x20];
 931
 932         u8         reserved_at_80[0x10];
 933         u8         packet_pacing_rate_table_size[0x10];
 934
 935         u8         esw_element_type[0x10];
 936         u8         esw_tsar_type[0x10];
 937
 938         u8         reserved_at_c0[0x10];
 939         u8         max_qos_para_vport[0x10];
 940
 941         u8         max_tsar_bw_share[0x20];
 942
 943         u8         reserved_at_100[0x700];
 944 };
 945
 946 struct mlx5_ifc_debug_cap_bits {
 947         u8         core_dump_general[0x1];
 948         u8         core_dump_qp[0x1];
 949         u8         reserved_at_2[0x7];
 950         u8         resource_dump[0x1];
 951         u8         reserved_at_a[0x16];
 952
 953         u8         reserved_at_20[0x2];
 954         u8         stall_detect[0x1];
 955         u8         reserved_at_23[0x1d];
 956
 957         u8         reserved_at_40[0x7c0];
 958 };
 959
 960 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 961         u8         csum_cap[0x1];
 962         u8         vlan_cap[0x1];
 963         u8         lro_cap[0x1];
 964         u8         lro_psh_flag[0x1];
 965         u8         lro_time_stamp[0x1];
 966         u8         reserved_at_5[0x2];
 967         u8         wqe_vlan_insert[0x1];
 968         u8         self_lb_en_modifiable[0x1];
 969         u8         reserved_at_9[0x2];
 970         u8         max_lso_cap[0x5];
 971         u8         multi_pkt_send_wqe[0x2];
 972         u8         wqe_inline_mode[0x2];
 973         u8         rss_ind_tbl_cap[0x4];
 974         u8         reg_umr_sq[0x1];
 975         u8         scatter_fcs[0x1];
 976         u8         enhanced_multi_pkt_send_wqe[0x1];
 977         u8         tunnel_lso_const_out_ip_id[0x1];
 978         u8         tunnel_lro_gre[0x1];
 979         u8         tunnel_lro_vxlan[0x1];
 980         u8         tunnel_stateless_gre[0x1];
 981         u8         tunnel_stateless_vxlan[0x1];
 982
 983         u8         swp[0x1];
 984         u8         swp_csum[0x1];
 985         u8         swp_lso[0x1];
 986         u8         cqe_checksum_full[0x1];
 987         u8         tunnel_stateless_geneve_tx[0x1];
 988         u8         tunnel_stateless_mpls_over_udp[0x1];
 989         u8         tunnel_stateless_mpls_over_gre[0x1];
 990         u8         tunnel_stateless_vxlan_gpe[0x1];
 991         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
 992         u8         tunnel_stateless_ip_over_ip[0x1];
 993         u8         insert_trailer[0x1];
 994         u8         reserved_at_2b[0x1];
 995         u8         tunnel_stateless_ip_over_ip_rx[0x1];
 996         u8         tunnel_stateless_ip_over_ip_tx[0x1];
 997         u8         reserved_at_2e[0x2];
 998         u8         max_vxlan_udp_ports[0x8];
 999         u8         reserved_at_38[0x6];
1000         u8         max_geneve_opt_len[0x1];
1001         u8         tunnel_stateless_geneve_rx[0x1];
1002
1003         u8         reserved_at_40[0x10];
1004         u8         lro_min_mss_size[0x10];
1005
1006         u8         reserved_at_60[0x120];
1007
1008         u8         lro_timer_supported_periods[4][0x20];
1009
1010         u8         reserved_at_200[0x600];
1011 };
1012
1013 enum {
1014         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1015         MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1016         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1017 };
1018
1019 struct mlx5_ifc_roce_cap_bits {
1020         u8         roce_apm[0x1];
1021         u8         reserved_at_1[0x3];
1022         u8         sw_r_roce_src_udp_port[0x1];
1023         u8         fl_rc_qp_when_roce_disabled[0x1];
1024         u8         fl_rc_qp_when_roce_enabled[0x1];
1025         u8         reserved_at_7[0x17];
1026         u8         qp_ts_format[0x2];
1027
1028         u8         reserved_at_20[0x60];
1029
1030         u8         reserved_at_80[0xc];
1031         u8         l3_type[0x4];
1032         u8         reserved_at_90[0x8];
1033         u8         roce_version[0x8];
1034
1035         u8         reserved_at_a0[0x10];
1036         u8         r_roce_dest_udp_port[0x10];
1037
1038         u8         r_roce_max_src_udp_port[0x10];
1039         u8         r_roce_min_src_udp_port[0x10];
1040
1041         u8         reserved_at_e0[0x10];
1042         u8         roce_address_table_size[0x10];
1043
1044         u8         reserved_at_100[0x700];
1045 };
1046
1047 struct mlx5_ifc_sync_steering_in_bits {
1048         u8         opcode[0x10];
1049         u8         uid[0x10];
1050
1051         u8         reserved_at_20[0x10];
1052         u8         op_mod[0x10];
1053
1054         u8         reserved_at_40[0xc0];
1055 };
1056
1057 struct mlx5_ifc_sync_steering_out_bits {
1058         u8         status[0x8];
1059         u8         reserved_at_8[0x18];
1060
1061         u8         syndrome[0x20];
1062
1063         u8         reserved_at_40[0x40];
1064 };
1065
1066 struct mlx5_ifc_device_mem_cap_bits {
1067         u8         memic[0x1];
1068         u8         reserved_at_1[0x1f];
1069
1070         u8         reserved_at_20[0xb];
1071         u8         log_min_memic_alloc_size[0x5];
1072         u8         reserved_at_30[0x8];
1073         u8         log_max_memic_addr_alignment[0x8];
1074
1075         u8         memic_bar_start_addr[0x40];
1076
1077         u8         memic_bar_size[0x20];
1078
1079         u8         max_memic_size[0x20];
1080
1081         u8         steering_sw_icm_start_address[0x40];
1082
1083         u8         reserved_at_100[0x8];
1084         u8         log_header_modify_sw_icm_size[0x8];
1085         u8         reserved_at_110[0x2];
1086         u8         log_sw_icm_alloc_granularity[0x6];
1087         u8         log_steering_sw_icm_size[0x8];
1088
1089         u8         reserved_at_120[0x20];
1090
1091         u8         header_modify_sw_icm_start_address[0x40];
1092
1093         u8         reserved_at_180[0x80];
1094
1095         u8         memic_operations[0x20];
1096
1097         u8         reserved_at_220[0x5e0];
1098 };
1099
1100 struct mlx5_ifc_device_event_cap_bits {
1101         u8         user_affiliated_events[4][0x40];
1102
1103         u8         user_unaffiliated_events[4][0x40];
1104 };
1105
1106 struct mlx5_ifc_virtio_emulation_cap_bits {
1107         u8         desc_tunnel_offload_type[0x1];
1108         u8         eth_frame_offload_type[0x1];
1109         u8         virtio_version_1_0[0x1];
1110         u8         device_features_bits_mask[0xd];
1111         u8         event_mode[0x8];
1112         u8         virtio_queue_type[0x8];
1113
1114         u8         max_tunnel_desc[0x10];
1115         u8         reserved_at_30[0x3];
1116         u8         log_doorbell_stride[0x5];
1117         u8         reserved_at_38[0x3];
1118         u8         log_doorbell_bar_size[0x5];
1119
1120         u8         doorbell_bar_offset[0x40];
1121
1122         u8         max_emulated_devices[0x8];
1123         u8         max_num_virtio_queues[0x18];
1124
1125         u8         reserved_at_a0[0x60];
1126
1127         u8         umem_1_buffer_param_a[0x20];
1128
1129         u8         umem_1_buffer_param_b[0x20];
1130
1131         u8         umem_2_buffer_param_a[0x20];
1132
1133         u8         umem_2_buffer_param_b[0x20];
1134
1135         u8         umem_3_buffer_param_a[0x20];
1136
1137         u8         umem_3_buffer_param_b[0x20];
1138
1139         u8         reserved_at_1c0[0x640];
1140 };
1141
1142 enum {
1143         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1144         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1145         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1146         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1147         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1148         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1149         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1150         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1151         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1152 };
1153
1154 enum {
1155         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1156         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1157         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1158         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1159         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1160         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1161         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1162         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1163         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1164 };
1165
1166 struct mlx5_ifc_atomic_caps_bits {
1167         u8         reserved_at_0[0x40];
1168
1169         u8         atomic_req_8B_endianness_mode[0x2];
1170         u8         reserved_at_42[0x4];
1171         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1172
1173         u8         reserved_at_47[0x19];
1174
1175         u8         reserved_at_60[0x20];
1176
1177         u8         reserved_at_80[0x10];
1178         u8         atomic_operations[0x10];
1179
1180         u8         reserved_at_a0[0x10];
1181         u8         atomic_size_qp[0x10];
1182
1183         u8         reserved_at_c0[0x10];
1184         u8         atomic_size_dc[0x10];
1185
1186         u8         reserved_at_e0[0x720];
1187 };
1188
1189 struct mlx5_ifc_odp_cap_bits {
1190         u8         reserved_at_0[0x40];
1191
1192         u8         sig[0x1];
1193         u8         reserved_at_41[0x1f];
1194
1195         u8         reserved_at_60[0x20];
1196
1197         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1198
1199         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1200
1201         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1202
1203         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1204
1205         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1206
1207         u8         reserved_at_120[0x6E0];
1208 };
1209
1210 struct mlx5_ifc_calc_op {
1211         u8        reserved_at_0[0x10];
1212         u8        reserved_at_10[0x9];
1213         u8        op_swap_endianness[0x1];
1214         u8        op_min[0x1];
1215         u8        op_xor[0x1];
1216         u8        op_or[0x1];
1217         u8        op_and[0x1];
1218         u8        op_max[0x1];
1219         u8        op_add[0x1];
1220 };
1221
1222 struct mlx5_ifc_vector_calc_cap_bits {
1223         u8         calc_matrix[0x1];
1224         u8         reserved_at_1[0x1f];
1225         u8         reserved_at_20[0x8];
1226         u8         max_vec_count[0x8];
1227         u8         reserved_at_30[0xd];
1228         u8         max_chunk_size[0x3];
1229         struct mlx5_ifc_calc_op calc0;
1230         struct mlx5_ifc_calc_op calc1;
1231         struct mlx5_ifc_calc_op calc2;
1232         struct mlx5_ifc_calc_op calc3;
1233
1234         u8         reserved_at_c0[0x720];
1235 };
1236
1237 struct mlx5_ifc_tls_cap_bits {
1238         u8         tls_1_2_aes_gcm_128[0x1];
1239         u8         tls_1_3_aes_gcm_128[0x1];
1240         u8         tls_1_2_aes_gcm_256[0x1];
1241         u8         tls_1_3_aes_gcm_256[0x1];
1242         u8         reserved_at_4[0x1c];
1243
1244         u8         reserved_at_20[0x7e0];
1245 };
1246
1247 struct mlx5_ifc_ipsec_cap_bits {
1248         u8         ipsec_full_offload[0x1];
1249         u8         ipsec_crypto_offload[0x1];
1250         u8         ipsec_esn[0x1];
1251         u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1252         u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1253         u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1254         u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1255         u8         reserved_at_7[0x4];
1256         u8         log_max_ipsec_offload[0x5];
1257         u8         reserved_at_10[0x10];
1258
1259         u8         min_log_ipsec_full_replay_window[0x8];
1260         u8         max_log_ipsec_full_replay_window[0x8];
1261         u8         reserved_at_30[0x7d0];
1262 };
1263
1264 enum {
1265         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1266         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1267         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1268         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1269 };
1270
1271 enum {
1272         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1273         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1274 };
1275
1276 enum {
1277         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1278         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1279         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1280         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1281         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1282 };
1283
1284 enum {
1285         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1286         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1287         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1288         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1289         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1290         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1291 };
1292
1293 enum {
1294         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1295         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1296 };
1297
1298 enum {
1299         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1300         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1301         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1302 };
1303
1304 enum {
1305         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1306         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1307 };
1308
1309 enum {
1310         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1311         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1312         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1313 };
1314
1315 enum {
1316         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1317         MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED  = 1 << 4,
1318         MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED  = 1 << 5,
1319         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1320         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1321         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1322         MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1323         MLX5_FLEX_PARSER_GTPU_ENABLED           = 1 << 11,
1324         MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED      = 1 << 16,
1325         MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1326         MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED      = 1 << 18,
1327         MLX5_FLEX_PARSER_GTPU_TEID_ENABLED      = 1 << 19,
1328 };
1329
1330 enum {
1331         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1332         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1333 };
1334
1335 #define MLX5_FC_BULK_SIZE_FACTOR 128
1336
1337 enum mlx5_fc_bulk_alloc_bitmask {
1338         MLX5_FC_BULK_128   = (1 << 0),
1339         MLX5_FC_BULK_256   = (1 << 1),
1340         MLX5_FC_BULK_512   = (1 << 2),
1341         MLX5_FC_BULK_1024  = (1 << 3),
1342         MLX5_FC_BULK_2048  = (1 << 4),
1343         MLX5_FC_BULK_4096  = (1 << 5),
1344         MLX5_FC_BULK_8192  = (1 << 6),
1345         MLX5_FC_BULK_16384 = (1 << 7),
1346 };
1347
1348 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1349
1350 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1351
1352 enum {
1353         MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1354         MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1355         MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1356 };
1357
1358 struct mlx5_ifc_cmd_hca_cap_bits {
1359         u8         reserved_at_0[0x1f];
1360         u8         vhca_resource_manager[0x1];
1361
1362         u8         hca_cap_2[0x1];
1363         u8         create_lag_when_not_master_up[0x1];
1364         u8         dtor[0x1];
1365         u8         event_on_vhca_state_teardown_request[0x1];
1366         u8         event_on_vhca_state_in_use[0x1];
1367         u8         event_on_vhca_state_active[0x1];
1368         u8         event_on_vhca_state_allocated[0x1];
1369         u8         event_on_vhca_state_invalid[0x1];
1370         u8         reserved_at_28[0x8];
1371         u8         vhca_id[0x10];
1372
1373         u8         reserved_at_40[0x40];
1374
1375         u8         log_max_srq_sz[0x8];
1376         u8         log_max_qp_sz[0x8];
1377         u8         event_cap[0x1];
1378         u8         reserved_at_91[0x2];
1379         u8         isolate_vl_tc_new[0x1];
1380         u8         reserved_at_94[0x4];
1381         u8         prio_tag_required[0x1];
1382         u8         reserved_at_99[0x2];
1383         u8         log_max_qp[0x5];
1384
1385         u8         reserved_at_a0[0x3];
1386         u8         ece_support[0x1];
1387         u8         reserved_at_a4[0x5];
1388         u8         reg_c_preserve[0x1];
1389         u8         reserved_at_aa[0x1];
1390         u8         log_max_srq[0x5];
1391         u8         reserved_at_b0[0x1];
1392         u8         uplink_follow[0x1];
1393         u8         ts_cqe_to_dest_cqn[0x1];
1394         u8         reserved_at_b3[0x7];
1395         u8         shampo[0x1];
1396         u8         reserved_at_bb[0x5];
1397
1398         u8         max_sgl_for_optimized_performance[0x8];
1399         u8         log_max_cq_sz[0x8];
1400         u8         relaxed_ordering_write_umr[0x1];
1401         u8         relaxed_ordering_read_umr[0x1];
1402         u8         reserved_at_d2[0x7];
1403         u8         virtio_net_device_emualtion_manager[0x1];
1404         u8         virtio_blk_device_emualtion_manager[0x1];
1405         u8         log_max_cq[0x5];
1406
1407         u8         log_max_eq_sz[0x8];
1408         u8         relaxed_ordering_write[0x1];
1409         u8         relaxed_ordering_read[0x1];
1410         u8         log_max_mkey[0x6];
1411         u8         reserved_at_f0[0x8];
1412         u8         dump_fill_mkey[0x1];
1413         u8         reserved_at_f9[0x2];
1414         u8         fast_teardown[0x1];
1415         u8         log_max_eq[0x4];
1416
1417         u8         max_indirection[0x8];
1418         u8         fixed_buffer_size[0x1];
1419         u8         log_max_mrw_sz[0x7];
1420         u8         force_teardown[0x1];
1421         u8         reserved_at_111[0x1];
1422         u8         log_max_bsf_list_size[0x6];
1423         u8         umr_extended_translation_offset[0x1];
1424         u8         null_mkey[0x1];
1425         u8         log_max_klm_list_size[0x6];
1426
1427         u8         reserved_at_120[0xa];
1428         u8         log_max_ra_req_dc[0x6];
1429         u8         reserved_at_130[0xa];
1430         u8         log_max_ra_res_dc[0x6];
1431
1432         u8         reserved_at_140[0x5];
1433         u8         release_all_pages[0x1];
1434         u8         must_not_use[0x1];
1435         u8         reserved_at_147[0x2];
1436         u8         roce_accl[0x1];
1437         u8         log_max_ra_req_qp[0x6];
1438         u8         reserved_at_150[0xa];
1439         u8         log_max_ra_res_qp[0x6];
1440
1441         u8         end_pad[0x1];
1442         u8         cc_query_allowed[0x1];
1443         u8         cc_modify_allowed[0x1];
1444         u8         start_pad[0x1];
1445         u8         cache_line_128byte[0x1];
1446         u8         reserved_at_165[0x4];
1447         u8         rts2rts_qp_counters_set_id[0x1];
1448         u8         reserved_at_16a[0x2];
1449         u8         vnic_env_int_rq_oob[0x1];
1450         u8         sbcam_reg[0x1];
1451         u8         reserved_at_16e[0x1];
1452         u8         qcam_reg[0x1];
1453         u8         gid_table_size[0x10];
1454
1455         u8         out_of_seq_cnt[0x1];
1456         u8         vport_counters[0x1];
1457         u8         retransmission_q_counters[0x1];
1458         u8         debug[0x1];
1459         u8         modify_rq_counter_set_id[0x1];
1460         u8         rq_delay_drop[0x1];
1461         u8         max_qp_cnt[0xa];
1462         u8         pkey_table_size[0x10];
1463
1464         u8         vport_group_manager[0x1];
1465         u8         vhca_group_manager[0x1];
1466         u8         ib_virt[0x1];
1467         u8         eth_virt[0x1];
1468         u8         vnic_env_queue_counters[0x1];
1469         u8         ets[0x1];
1470         u8         nic_flow_table[0x1];
1471         u8         eswitch_manager[0x1];
1472         u8         device_memory[0x1];
1473         u8         mcam_reg[0x1];
1474         u8         pcam_reg[0x1];
1475         u8         local_ca_ack_delay[0x5];
1476         u8         port_module_event[0x1];
1477         u8         enhanced_error_q_counters[0x1];
1478         u8         ports_check[0x1];
1479         u8         reserved_at_1b3[0x1];
1480         u8         disable_link_up[0x1];
1481         u8         beacon_led[0x1];
1482         u8         port_type[0x2];
1483         u8         num_ports[0x8];
1484
1485         u8         reserved_at_1c0[0x1];
1486         u8         pps[0x1];
1487         u8         pps_modify[0x1];
1488         u8         log_max_msg[0x5];
1489         u8         reserved_at_1c8[0x4];
1490         u8         max_tc[0x4];
1491         u8         temp_warn_event[0x1];
1492         u8         dcbx[0x1];
1493         u8         general_notification_event[0x1];
1494         u8         reserved_at_1d3[0x2];
1495         u8         fpga[0x1];
1496         u8         rol_s[0x1];
1497         u8         rol_g[0x1];
1498         u8         reserved_at_1d8[0x1];
1499         u8         wol_s[0x1];
1500         u8         wol_g[0x1];
1501         u8         wol_a[0x1];
1502         u8         wol_b[0x1];
1503         u8         wol_m[0x1];
1504         u8         wol_u[0x1];
1505         u8         wol_p[0x1];
1506
1507         u8         stat_rate_support[0x10];
1508         u8         reserved_at_1f0[0x1];
1509         u8         pci_sync_for_fw_update_event[0x1];
1510         u8         reserved_at_1f2[0x6];
1511         u8         init2_lag_tx_port_affinity[0x1];
1512         u8         reserved_at_1fa[0x3];
1513         u8         cqe_version[0x4];
1514
1515         u8         compact_address_vector[0x1];
1516         u8         striding_rq[0x1];
1517         u8         reserved_at_202[0x1];
1518         u8         ipoib_enhanced_offloads[0x1];
1519         u8         ipoib_basic_offloads[0x1];
1520         u8         reserved_at_205[0x1];
1521         u8         repeated_block_disabled[0x1];
1522         u8         umr_modify_entity_size_disabled[0x1];
1523         u8         umr_modify_atomic_disabled[0x1];
1524         u8         umr_indirect_mkey_disabled[0x1];
1525         u8         umr_fence[0x2];
1526         u8         dc_req_scat_data_cqe[0x1];
1527         u8         reserved_at_20d[0x2];
1528         u8         drain_sigerr[0x1];
1529         u8         cmdif_checksum[0x2];
1530         u8         sigerr_cqe[0x1];
1531         u8         reserved_at_213[0x1];
1532         u8         wq_signature[0x1];
1533         u8         sctr_data_cqe[0x1];
1534         u8         reserved_at_216[0x1];
1535         u8         sho[0x1];
1536         u8         tph[0x1];
1537         u8         rf[0x1];
1538         u8         dct[0x1];
1539         u8         qos[0x1];
1540         u8         eth_net_offloads[0x1];
1541         u8         roce[0x1];
1542         u8         atomic[0x1];
1543         u8         reserved_at_21f[0x1];
1544
1545         u8         cq_oi[0x1];
1546         u8         cq_resize[0x1];
1547         u8         cq_moderation[0x1];
1548         u8         reserved_at_223[0x3];
1549         u8         cq_eq_remap[0x1];
1550         u8         pg[0x1];
1551         u8         block_lb_mc[0x1];
1552         u8         reserved_at_229[0x1];
1553         u8         scqe_break_moderation[0x1];
1554         u8         cq_period_start_from_cqe[0x1];
1555         u8         cd[0x1];
1556         u8         reserved_at_22d[0x1];
1557         u8         apm[0x1];
1558         u8         vector_calc[0x1];
1559         u8         umr_ptr_rlky[0x1];
1560         u8         imaicl[0x1];
1561         u8         qp_packet_based[0x1];
1562         u8         reserved_at_233[0x3];
1563         u8         qkv[0x1];
1564         u8         pkv[0x1];
1565         u8         set_deth_sqpn[0x1];
1566         u8         reserved_at_239[0x3];
1567         u8         xrc[0x1];
1568         u8         ud[0x1];
1569         u8         uc[0x1];
1570         u8         rc[0x1];
1571
1572         u8         uar_4k[0x1];
1573         u8         reserved_at_241[0x9];
1574         u8         uar_sz[0x6];
1575         u8         port_selection_cap[0x1];
1576         u8         reserved_at_248[0x1];
1577         u8         umem_uid_0[0x1];
1578         u8         reserved_at_250[0x5];
1579         u8         log_pg_sz[0x8];
1580
1581         u8         bf[0x1];
1582         u8         driver_version[0x1];
1583         u8         pad_tx_eth_packet[0x1];
1584         u8         reserved_at_263[0x3];
1585         u8         mkey_by_name[0x1];
1586         u8         reserved_at_267[0x4];
1587
1588         u8         log_bf_reg_size[0x5];
1589
1590         u8         reserved_at_270[0x6];
1591         u8         lag_dct[0x2];
1592         u8         lag_tx_port_affinity[0x1];
1593         u8         lag_native_fdb_selection[0x1];
1594         u8         reserved_at_27a[0x1];
1595         u8         lag_master[0x1];
1596         u8         num_lag_ports[0x4];
1597
1598         u8         reserved_at_280[0x10];
1599         u8         max_wqe_sz_sq[0x10];
1600
1601         u8         reserved_at_2a0[0x10];
1602         u8         max_wqe_sz_rq[0x10];
1603
1604         u8         max_flow_counter_31_16[0x10];
1605         u8         max_wqe_sz_sq_dc[0x10];
1606
1607         u8         reserved_at_2e0[0x7];
1608         u8         max_qp_mcg[0x19];
1609
1610         u8         reserved_at_300[0x10];
1611         u8         flow_counter_bulk_alloc[0x8];
1612         u8         log_max_mcg[0x8];
1613
1614         u8         reserved_at_320[0x3];
1615         u8         log_max_transport_domain[0x5];
1616         u8         reserved_at_328[0x3];
1617         u8         log_max_pd[0x5];
1618         u8         reserved_at_330[0xb];
1619         u8         log_max_xrcd[0x5];
1620
1621         u8         nic_receive_steering_discard[0x1];
1622         u8         receive_discard_vport_down[0x1];
1623         u8         transmit_discard_vport_down[0x1];
1624         u8         reserved_at_343[0x5];
1625         u8         log_max_flow_counter_bulk[0x8];
1626         u8         max_flow_counter_15_0[0x10];
1627
1628
1629         u8         reserved_at_360[0x3];
1630         u8         log_max_rq[0x5];
1631         u8         reserved_at_368[0x3];
1632         u8         log_max_sq[0x5];
1633         u8         reserved_at_370[0x3];
1634         u8         log_max_tir[0x5];
1635         u8         reserved_at_378[0x3];
1636         u8         log_max_tis[0x5];
1637
1638         u8         basic_cyclic_rcv_wqe[0x1];
1639         u8         reserved_at_381[0x2];
1640         u8         log_max_rmp[0x5];
1641         u8         reserved_at_388[0x3];
1642         u8         log_max_rqt[0x5];
1643         u8         reserved_at_390[0x3];
1644         u8         log_max_rqt_size[0x5];
1645         u8         reserved_at_398[0x3];
1646         u8         log_max_tis_per_sq[0x5];
1647
1648         u8         ext_stride_num_range[0x1];
1649         u8         roce_rw_supported[0x1];
1650         u8         log_max_current_uc_list_wr_supported[0x1];
1651         u8         log_max_stride_sz_rq[0x5];
1652         u8         reserved_at_3a8[0x3];
1653         u8         log_min_stride_sz_rq[0x5];
1654         u8         reserved_at_3b0[0x3];
1655         u8         log_max_stride_sz_sq[0x5];
1656         u8         reserved_at_3b8[0x3];
1657         u8         log_min_stride_sz_sq[0x5];
1658
1659         u8         hairpin[0x1];
1660         u8         reserved_at_3c1[0x2];
1661         u8         log_max_hairpin_queues[0x5];
1662         u8         reserved_at_3c8[0x3];
1663         u8         log_max_hairpin_wq_data_sz[0x5];
1664         u8         reserved_at_3d0[0x3];
1665         u8         log_max_hairpin_num_packets[0x5];
1666         u8         reserved_at_3d8[0x3];
1667         u8         log_max_wq_sz[0x5];
1668
1669         u8         nic_vport_change_event[0x1];
1670         u8         disable_local_lb_uc[0x1];
1671         u8         disable_local_lb_mc[0x1];
1672         u8         log_min_hairpin_wq_data_sz[0x5];
1673         u8         reserved_at_3e8[0x2];
1674         u8         vhca_state[0x1];
1675         u8         log_max_vlan_list[0x5];
1676         u8         reserved_at_3f0[0x3];
1677         u8         log_max_current_mc_list[0x5];
1678         u8         reserved_at_3f8[0x3];
1679         u8         log_max_current_uc_list[0x5];
1680
1681         u8         general_obj_types[0x40];
1682
1683         u8         sq_ts_format[0x2];
1684         u8         rq_ts_format[0x2];
1685         u8         steering_format_version[0x4];
1686         u8         create_qp_start_hint[0x18];
1687
1688         u8         reserved_at_460[0x3];
1689         u8         log_max_uctx[0x5];
1690         u8         reserved_at_468[0x2];
1691         u8         ipsec_offload[0x1];
1692         u8         log_max_umem[0x5];
1693         u8         max_num_eqs[0x10];
1694
1695         u8         reserved_at_480[0x1];
1696         u8         tls_tx[0x1];
1697         u8         tls_rx[0x1];
1698         u8         log_max_l2_table[0x5];
1699         u8         reserved_at_488[0x8];
1700         u8         log_uar_page_sz[0x10];
1701
1702         u8         reserved_at_4a0[0x20];
1703         u8         device_frequency_mhz[0x20];
1704         u8         device_frequency_khz[0x20];
1705
1706         u8         reserved_at_500[0x20];
1707         u8         num_of_uars_per_page[0x20];
1708
1709         u8         flex_parser_protocols[0x20];
1710
1711         u8         max_geneve_tlv_options[0x8];
1712         u8         reserved_at_568[0x3];
1713         u8         max_geneve_tlv_option_data_len[0x5];
1714         u8         reserved_at_570[0x10];
1715
1716         u8         reserved_at_580[0xb];
1717         u8         log_max_dci_stream_channels[0x5];
1718         u8         reserved_at_590[0x3];
1719         u8         log_max_dci_errored_streams[0x5];
1720         u8         reserved_at_598[0x8];
1721
1722         u8         reserved_at_5a0[0x13];
1723         u8         log_max_dek[0x5];
1724         u8         reserved_at_5b8[0x4];
1725         u8         mini_cqe_resp_stride_index[0x1];
1726         u8         cqe_128_always[0x1];
1727         u8         cqe_compression_128[0x1];
1728         u8         cqe_compression[0x1];
1729
1730         u8         cqe_compression_timeout[0x10];
1731         u8         cqe_compression_max_num[0x10];
1732
1733         u8         reserved_at_5e0[0x8];
1734         u8         flex_parser_id_gtpu_dw_0[0x4];
1735         u8         reserved_at_5ec[0x4];
1736         u8         tag_matching[0x1];
1737         u8         rndv_offload_rc[0x1];
1738         u8         rndv_offload_dc[0x1];
1739         u8         log_tag_matching_list_sz[0x5];
1740         u8         reserved_at_5f8[0x3];
1741         u8         log_max_xrq[0x5];
1742
1743         u8         affiliate_nic_vport_criteria[0x8];
1744         u8         native_port_num[0x8];
1745         u8         num_vhca_ports[0x8];
1746         u8         flex_parser_id_gtpu_teid[0x4];
1747         u8         reserved_at_61c[0x2];
1748         u8         sw_owner_id[0x1];
1749         u8         reserved_at_61f[0x1];
1750
1751         u8         max_num_of_monitor_counters[0x10];
1752         u8         num_ppcnt_monitor_counters[0x10];
1753
1754         u8         max_num_sf[0x10];
1755         u8         num_q_monitor_counters[0x10];
1756
1757         u8         reserved_at_660[0x20];
1758
1759         u8         sf[0x1];
1760         u8         sf_set_partition[0x1];
1761         u8         reserved_at_682[0x1];
1762         u8         log_max_sf[0x5];
1763         u8         apu[0x1];
1764         u8         reserved_at_689[0x4];
1765         u8         migration[0x1];
1766         u8         reserved_at_68e[0x2];
1767         u8         log_min_sf_size[0x8];
1768         u8         max_num_sf_partitions[0x8];
1769
1770         u8         uctx_cap[0x20];
1771
1772         u8         reserved_at_6c0[0x4];
1773         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1774         u8         flex_parser_id_icmp_dw1[0x4];
1775         u8         flex_parser_id_icmp_dw0[0x4];
1776         u8         flex_parser_id_icmpv6_dw1[0x4];
1777         u8         flex_parser_id_icmpv6_dw0[0x4];
1778         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1779         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1780
1781         u8         max_num_match_definer[0x10];
1782         u8         sf_base_id[0x10];
1783
1784         u8         flex_parser_id_gtpu_dw_2[0x4];
1785         u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1786         u8         num_total_dynamic_vf_msix[0x18];
1787         u8         reserved_at_720[0x14];
1788         u8         dynamic_msix_table_size[0xc];
1789         u8         reserved_at_740[0xc];
1790         u8         min_dynamic_vf_msix_table_size[0x4];
1791         u8         reserved_at_750[0x4];
1792         u8         max_dynamic_vf_msix_table_size[0xc];
1793
1794         u8         reserved_at_760[0x20];
1795         u8         vhca_tunnel_commands[0x40];
1796         u8         match_definer_format_supported[0x40];
1797 };
1798
1799 struct mlx5_ifc_cmd_hca_cap_2_bits {
1800         u8         reserved_at_0[0xa0];
1801
1802         u8         max_reformat_insert_size[0x8];
1803         u8         max_reformat_insert_offset[0x8];
1804         u8         max_reformat_remove_size[0x8];
1805         u8         max_reformat_remove_offset[0x8];
1806
1807         u8         reserved_at_c0[0x740];
1808 };
1809
1810 enum mlx5_ifc_flow_destination_type {
1811         MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1812         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1813         MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1814         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1815         MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
1816 };
1817
1818 enum mlx5_flow_table_miss_action {
1819         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1820         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1821         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1822 };
1823
1824 struct mlx5_ifc_dest_format_struct_bits {
1825         u8         destination_type[0x8];
1826         u8         destination_id[0x18];
1827
1828         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1829         u8         packet_reformat[0x1];
1830         u8         reserved_at_22[0xe];
1831         u8         destination_eswitch_owner_vhca_id[0x10];
1832 };
1833
1834 struct mlx5_ifc_flow_counter_list_bits {
1835         u8         flow_counter_id[0x20];
1836
1837         u8         reserved_at_20[0x20];
1838 };
1839
1840 struct mlx5_ifc_extended_dest_format_bits {
1841         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1842
1843         u8         packet_reformat_id[0x20];
1844
1845         u8         reserved_at_60[0x20];
1846 };
1847
1848 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1849         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1850         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1851 };
1852
1853 struct mlx5_ifc_fte_match_param_bits {
1854         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1855
1856         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1857
1858         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1859
1860         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1861
1862         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1863
1864         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1865
1866         struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1867
1868         u8         reserved_at_e00[0x200];
1869 };
1870
1871 enum {
1872         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1873         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1874         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1875         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1876         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1877 };
1878
1879 struct mlx5_ifc_rx_hash_field_select_bits {
1880         u8         l3_prot_type[0x1];
1881         u8         l4_prot_type[0x1];
1882         u8         selected_fields[0x1e];
1883 };
1884
1885 enum {
1886         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1887         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1888 };
1889
1890 enum {
1891         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1892         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1893 };
1894
1895 struct mlx5_ifc_wq_bits {
1896         u8         wq_type[0x4];
1897         u8         wq_signature[0x1];
1898         u8         end_padding_mode[0x2];
1899         u8         cd_slave[0x1];
1900         u8         reserved_at_8[0x18];
1901
1902         u8         hds_skip_first_sge[0x1];
1903         u8         log2_hds_buf_size[0x3];
1904         u8         reserved_at_24[0x7];
1905         u8         page_offset[0x5];
1906         u8         lwm[0x10];
1907
1908         u8         reserved_at_40[0x8];
1909         u8         pd[0x18];
1910
1911         u8         reserved_at_60[0x8];
1912         u8         uar_page[0x18];
1913
1914         u8         dbr_addr[0x40];
1915
1916         u8         hw_counter[0x20];
1917
1918         u8         sw_counter[0x20];
1919
1920         u8         reserved_at_100[0xc];
1921         u8         log_wq_stride[0x4];
1922         u8         reserved_at_110[0x3];
1923         u8         log_wq_pg_sz[0x5];
1924         u8         reserved_at_118[0x3];
1925         u8         log_wq_sz[0x5];
1926
1927         u8         dbr_umem_valid[0x1];
1928         u8         wq_umem_valid[0x1];
1929         u8         reserved_at_122[0x1];
1930         u8         log_hairpin_num_packets[0x5];
1931         u8         reserved_at_128[0x3];
1932         u8         log_hairpin_data_sz[0x5];
1933
1934         u8         reserved_at_130[0x4];
1935         u8         log_wqe_num_of_strides[0x4];
1936         u8         two_byte_shift_en[0x1];
1937         u8         reserved_at_139[0x4];
1938         u8         log_wqe_stride_size[0x3];
1939
1940         u8         reserved_at_140[0x80];
1941
1942         u8         headers_mkey[0x20];
1943
1944         u8         shampo_enable[0x1];
1945         u8         reserved_at_1e1[0x4];
1946         u8         log_reservation_size[0x3];
1947         u8         reserved_at_1e8[0x5];
1948         u8         log_max_num_of_packets_per_reservation[0x3];
1949         u8         reserved_at_1f0[0x6];
1950         u8         log_headers_entry_size[0x2];
1951         u8         reserved_at_1f8[0x4];
1952         u8         log_headers_buffer_entry_num[0x4];
1953
1954         u8         reserved_at_200[0x400];
1955
1956         struct mlx5_ifc_cmd_pas_bits pas[];
1957 };
1958
1959 struct mlx5_ifc_rq_num_bits {
1960         u8         reserved_at_0[0x8];
1961         u8         rq_num[0x18];
1962 };
1963
1964 struct mlx5_ifc_mac_address_layout_bits {
1965         u8         reserved_at_0[0x10];
1966         u8         mac_addr_47_32[0x10];
1967
1968         u8         mac_addr_31_0[0x20];
1969 };
1970
1971 struct mlx5_ifc_vlan_layout_bits {
1972         u8         reserved_at_0[0x14];
1973         u8         vlan[0x0c];
1974
1975         u8         reserved_at_20[0x20];
1976 };
1977
1978 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1979         u8         reserved_at_0[0xa0];
1980
1981         u8         min_time_between_cnps[0x20];
1982
1983         u8         reserved_at_c0[0x12];
1984         u8         cnp_dscp[0x6];
1985         u8         reserved_at_d8[0x4];
1986         u8         cnp_prio_mode[0x1];
1987         u8         cnp_802p_prio[0x3];
1988
1989         u8         reserved_at_e0[0x720];
1990 };
1991
1992 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1993         u8         reserved_at_0[0x60];
1994
1995         u8         reserved_at_60[0x4];
1996         u8         clamp_tgt_rate[0x1];
1997         u8         reserved_at_65[0x3];
1998         u8         clamp_tgt_rate_after_time_inc[0x1];
1999         u8         reserved_at_69[0x17];
2000
2001         u8         reserved_at_80[0x20];
2002
2003         u8         rpg_time_reset[0x20];
2004
2005         u8         rpg_byte_reset[0x20];
2006
2007         u8         rpg_threshold[0x20];
2008
2009         u8         rpg_max_rate[0x20];
2010
2011         u8         rpg_ai_rate[0x20];
2012
2013         u8         rpg_hai_rate[0x20];
2014
2015         u8         rpg_gd[0x20];
2016
2017         u8         rpg_min_dec_fac[0x20];
2018
2019         u8         rpg_min_rate[0x20];
2020
2021         u8         reserved_at_1c0[0xe0];
2022
2023         u8         rate_to_set_on_first_cnp[0x20];
2024
2025         u8         dce_tcp_g[0x20];
2026
2027         u8         dce_tcp_rtt[0x20];
2028
2029         u8         rate_reduce_monitor_period[0x20];
2030
2031         u8         reserved_at_320[0x20];
2032
2033         u8         initial_alpha_value[0x20];
2034
2035         u8         reserved_at_360[0x4a0];
2036 };
2037
2038 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2039         u8         reserved_at_0[0x80];
2040
2041         u8         rppp_max_rps[0x20];
2042
2043         u8         rpg_time_reset[0x20];
2044
2045         u8         rpg_byte_reset[0x20];
2046
2047         u8         rpg_threshold[0x20];
2048
2049         u8         rpg_max_rate[0x20];
2050
2051         u8         rpg_ai_rate[0x20];
2052
2053         u8         rpg_hai_rate[0x20];
2054
2055         u8         rpg_gd[0x20];
2056
2057         u8         rpg_min_dec_fac[0x20];
2058
2059         u8         rpg_min_rate[0x20];
2060
2061         u8         reserved_at_1c0[0x640];
2062 };
2063
2064 enum {
2065         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2066         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2067         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2068 };
2069
2070 struct mlx5_ifc_resize_field_select_bits {
2071         u8         resize_field_select[0x20];
2072 };
2073
2074 struct mlx5_ifc_resource_dump_bits {
2075         u8         more_dump[0x1];
2076         u8         inline_dump[0x1];
2077         u8         reserved_at_2[0xa];
2078         u8         seq_num[0x4];
2079         u8         segment_type[0x10];
2080
2081         u8         reserved_at_20[0x10];
2082         u8         vhca_id[0x10];
2083
2084         u8         index1[0x20];
2085
2086         u8         index2[0x20];
2087
2088         u8         num_of_obj1[0x10];
2089         u8         num_of_obj2[0x10];
2090
2091         u8         reserved_at_a0[0x20];
2092
2093         u8         device_opaque[0x40];
2094
2095         u8         mkey[0x20];
2096
2097         u8         size[0x20];
2098
2099         u8         address[0x40];
2100
2101         u8         inline_data[52][0x20];
2102 };
2103
2104 struct mlx5_ifc_resource_dump_menu_record_bits {
2105         u8         reserved_at_0[0x4];
2106         u8         num_of_obj2_supports_active[0x1];
2107         u8         num_of_obj2_supports_all[0x1];
2108         u8         must_have_num_of_obj2[0x1];
2109         u8         support_num_of_obj2[0x1];
2110         u8         num_of_obj1_supports_active[0x1];
2111         u8         num_of_obj1_supports_all[0x1];
2112         u8         must_have_num_of_obj1[0x1];
2113         u8         support_num_of_obj1[0x1];
2114         u8         must_have_index2[0x1];
2115         u8         support_index2[0x1];
2116         u8         must_have_index1[0x1];
2117         u8         support_index1[0x1];
2118         u8         segment_type[0x10];
2119
2120         u8         segment_name[4][0x20];
2121
2122         u8         index1_name[4][0x20];
2123
2124         u8         index2_name[4][0x20];
2125 };
2126
2127 struct mlx5_ifc_resource_dump_segment_header_bits {
2128         u8         length_dw[0x10];
2129         u8         segment_type[0x10];
2130 };
2131
2132 struct mlx5_ifc_resource_dump_command_segment_bits {
2133         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2134
2135         u8         segment_called[0x10];
2136         u8         vhca_id[0x10];
2137
2138         u8         index1[0x20];
2139
2140         u8         index2[0x20];
2141
2142         u8         num_of_obj1[0x10];
2143         u8         num_of_obj2[0x10];
2144 };
2145
2146 struct mlx5_ifc_resource_dump_error_segment_bits {
2147         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2148
2149         u8         reserved_at_20[0x10];
2150         u8         syndrome_id[0x10];
2151
2152         u8         reserved_at_40[0x40];
2153
2154         u8         error[8][0x20];
2155 };
2156
2157 struct mlx5_ifc_resource_dump_info_segment_bits {
2158         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2159
2160         u8         reserved_at_20[0x18];
2161         u8         dump_version[0x8];
2162
2163         u8         hw_version[0x20];
2164
2165         u8         fw_version[0x20];
2166 };
2167
2168 struct mlx5_ifc_resource_dump_menu_segment_bits {
2169         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2170
2171         u8         reserved_at_20[0x10];
2172         u8         num_of_records[0x10];
2173
2174         struct mlx5_ifc_resource_dump_menu_record_bits record[];
2175 };
2176
2177 struct mlx5_ifc_resource_dump_resource_segment_bits {
2178         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2179
2180         u8         reserved_at_20[0x20];
2181
2182         u8         index1[0x20];
2183
2184         u8         index2[0x20];
2185
2186         u8         payload[][0x20];
2187 };
2188
2189 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2190         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2191 };
2192
2193 struct mlx5_ifc_menu_resource_dump_response_bits {
2194         struct mlx5_ifc_resource_dump_info_segment_bits info;
2195         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2196         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2197         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2198 };
2199
2200 enum {
2201         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2202         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2203         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2204         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2205 };
2206
2207 struct mlx5_ifc_modify_field_select_bits {
2208         u8         modify_field_select[0x20];
2209 };
2210
2211 struct mlx5_ifc_field_select_r_roce_np_bits {
2212         u8         field_select_r_roce_np[0x20];
2213 };
2214
2215 struct mlx5_ifc_field_select_r_roce_rp_bits {
2216         u8         field_select_r_roce_rp[0x20];
2217 };
2218
2219 enum {
2220         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2221         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2222         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2223         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2224         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2225         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2226         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2227         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2228         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2229         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2230 };
2231
2232 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2233         u8         field_select_8021qaurp[0x20];
2234 };
2235
2236 struct mlx5_ifc_phys_layer_cntrs_bits {
2237         u8         time_since_last_clear_high[0x20];
2238
2239         u8         time_since_last_clear_low[0x20];
2240
2241         u8         symbol_errors_high[0x20];
2242
2243         u8         symbol_errors_low[0x20];
2244
2245         u8         sync_headers_errors_high[0x20];
2246
2247         u8         sync_headers_errors_low[0x20];
2248
2249         u8         edpl_bip_errors_lane0_high[0x20];
2250
2251         u8         edpl_bip_errors_lane0_low[0x20];
2252
2253         u8         edpl_bip_errors_lane1_high[0x20];
2254
2255         u8         edpl_bip_errors_lane1_low[0x20];
2256
2257         u8         edpl_bip_errors_lane2_high[0x20];
2258
2259         u8         edpl_bip_errors_lane2_low[0x20];
2260
2261         u8         edpl_bip_errors_lane3_high[0x20];
2262
2263         u8         edpl_bip_errors_lane3_low[0x20];
2264
2265         u8         fc_fec_corrected_blocks_lane0_high[0x20];
2266
2267         u8         fc_fec_corrected_blocks_lane0_low[0x20];
2268
2269         u8         fc_fec_corrected_blocks_lane1_high[0x20];
2270
2271         u8         fc_fec_corrected_blocks_lane1_low[0x20];
2272
2273         u8         fc_fec_corrected_blocks_lane2_high[0x20];
2274
2275         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2276
2277         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2278
2279         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2280
2281         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2282
2283         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2284
2285         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2286
2287         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2288
2289         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2290
2291         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2292
2293         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2294
2295         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2296
2297         u8         rs_fec_corrected_blocks_high[0x20];
2298
2299         u8         rs_fec_corrected_blocks_low[0x20];
2300
2301         u8         rs_fec_uncorrectable_blocks_high[0x20];
2302
2303         u8         rs_fec_uncorrectable_blocks_low[0x20];
2304
2305         u8         rs_fec_no_errors_blocks_high[0x20];
2306
2307         u8         rs_fec_no_errors_blocks_low[0x20];
2308
2309         u8         rs_fec_single_error_blocks_high[0x20];
2310
2311         u8         rs_fec_single_error_blocks_low[0x20];
2312
2313         u8         rs_fec_corrected_symbols_total_high[0x20];
2314
2315         u8         rs_fec_corrected_symbols_total_low[0x20];
2316
2317         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2318
2319         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2320
2321         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2322
2323         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2324
2325         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2326
2327         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2328
2329         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2330
2331         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2332
2333         u8         link_down_events[0x20];
2334
2335         u8         successful_recovery_events[0x20];
2336
2337         u8         reserved_at_640[0x180];
2338 };
2339
2340 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2341         u8         time_since_last_clear_high[0x20];
2342
2343         u8         time_since_last_clear_low[0x20];
2344
2345         u8         phy_received_bits_high[0x20];
2346
2347         u8         phy_received_bits_low[0x20];
2348
2349         u8         phy_symbol_errors_high[0x20];
2350
2351         u8         phy_symbol_errors_low[0x20];
2352
2353         u8         phy_corrected_bits_high[0x20];
2354
2355         u8         phy_corrected_bits_low[0x20];
2356
2357         u8         phy_corrected_bits_lane0_high[0x20];
2358
2359         u8         phy_corrected_bits_lane0_low[0x20];
2360
2361         u8         phy_corrected_bits_lane1_high[0x20];
2362
2363         u8         phy_corrected_bits_lane1_low[0x20];
2364
2365         u8         phy_corrected_bits_lane2_high[0x20];
2366
2367         u8         phy_corrected_bits_lane2_low[0x20];
2368
2369         u8         phy_corrected_bits_lane3_high[0x20];
2370
2371         u8         phy_corrected_bits_lane3_low[0x20];
2372
2373         u8         reserved_at_200[0x5c0];
2374 };
2375
2376 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2377         u8         symbol_error_counter[0x10];
2378
2379         u8         link_error_recovery_counter[0x8];
2380
2381         u8         link_downed_counter[0x8];
2382
2383         u8         port_rcv_errors[0x10];
2384
2385         u8         port_rcv_remote_physical_errors[0x10];
2386
2387         u8         port_rcv_switch_relay_errors[0x10];
2388
2389         u8         port_xmit_discards[0x10];
2390
2391         u8         port_xmit_constraint_errors[0x8];
2392
2393         u8         port_rcv_constraint_errors[0x8];
2394
2395         u8         reserved_at_70[0x8];
2396
2397         u8         link_overrun_errors[0x8];
2398
2399         u8         reserved_at_80[0x10];
2400
2401         u8         vl_15_dropped[0x10];
2402
2403         u8         reserved_at_a0[0x80];
2404
2405         u8         port_xmit_wait[0x20];
2406 };
2407
2408 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2409         u8         transmit_queue_high[0x20];
2410
2411         u8         transmit_queue_low[0x20];
2412
2413         u8         no_buffer_discard_uc_high[0x20];
2414
2415         u8         no_buffer_discard_uc_low[0x20];
2416
2417         u8         reserved_at_80[0x740];
2418 };
2419
2420 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2421         u8         wred_discard_high[0x20];
2422
2423         u8         wred_discard_low[0x20];
2424
2425         u8         ecn_marked_tc_high[0x20];
2426
2427         u8         ecn_marked_tc_low[0x20];
2428
2429         u8         reserved_at_80[0x740];
2430 };
2431
2432 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2433         u8         rx_octets_high[0x20];
2434
2435         u8         rx_octets_low[0x20];
2436
2437         u8         reserved_at_40[0xc0];
2438
2439         u8         rx_frames_high[0x20];
2440
2441         u8         rx_frames_low[0x20];
2442
2443         u8         tx_octets_high[0x20];
2444
2445         u8         tx_octets_low[0x20];
2446
2447         u8         reserved_at_180[0xc0];
2448
2449         u8         tx_frames_high[0x20];
2450
2451         u8         tx_frames_low[0x20];
2452
2453         u8         rx_pause_high[0x20];
2454
2455         u8         rx_pause_low[0x20];
2456
2457         u8         rx_pause_duration_high[0x20];
2458
2459         u8         rx_pause_duration_low[0x20];
2460
2461         u8         tx_pause_high[0x20];
2462
2463         u8         tx_pause_low[0x20];
2464
2465         u8         tx_pause_duration_high[0x20];
2466
2467         u8         tx_pause_duration_low[0x20];
2468
2469         u8         rx_pause_transition_high[0x20];
2470
2471         u8         rx_pause_transition_low[0x20];
2472
2473         u8         rx_discards_high[0x20];
2474
2475         u8         rx_discards_low[0x20];
2476
2477         u8         device_stall_minor_watermark_cnt_high[0x20];
2478
2479         u8         device_stall_minor_watermark_cnt_low[0x20];
2480
2481         u8         device_stall_critical_watermark_cnt_high[0x20];
2482
2483         u8         device_stall_critical_watermark_cnt_low[0x20];
2484
2485         u8         reserved_at_480[0x340];
2486 };
2487
2488 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2489         u8         port_transmit_wait_high[0x20];
2490
2491         u8         port_transmit_wait_low[0x20];
2492
2493         u8         reserved_at_40[0x100];
2494
2495         u8         rx_buffer_almost_full_high[0x20];
2496
2497         u8         rx_buffer_almost_full_low[0x20];
2498
2499         u8         rx_buffer_full_high[0x20];
2500
2501         u8         rx_buffer_full_low[0x20];
2502
2503         u8         rx_icrc_encapsulated_high[0x20];
2504
2505         u8         rx_icrc_encapsulated_low[0x20];
2506
2507         u8         reserved_at_200[0x5c0];
2508 };
2509
2510 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2511         u8         dot3stats_alignment_errors_high[0x20];
2512
2513         u8         dot3stats_alignment_errors_low[0x20];
2514
2515         u8         dot3stats_fcs_errors_high[0x20];
2516
2517         u8         dot3stats_fcs_errors_low[0x20];
2518
2519         u8         dot3stats_single_collision_frames_high[0x20];
2520
2521         u8         dot3stats_single_collision_frames_low[0x20];
2522
2523         u8         dot3stats_multiple_collision_frames_high[0x20];
2524
2525         u8         dot3stats_multiple_collision_frames_low[0x20];
2526
2527         u8         dot3stats_sqe_test_errors_high[0x20];
2528
2529         u8         dot3stats_sqe_test_errors_low[0x20];
2530
2531         u8         dot3stats_deferred_transmissions_high[0x20];
2532
2533         u8         dot3stats_deferred_transmissions_low[0x20];
2534
2535         u8         dot3stats_late_collisions_high[0x20];
2536
2537         u8         dot3stats_late_collisions_low[0x20];
2538
2539         u8         dot3stats_excessive_collisions_high[0x20];
2540
2541         u8         dot3stats_excessive_collisions_low[0x20];
2542
2543         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2544
2545         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2546
2547         u8         dot3stats_carrier_sense_errors_high[0x20];
2548
2549         u8         dot3stats_carrier_sense_errors_low[0x20];
2550
2551         u8         dot3stats_frame_too_longs_high[0x20];
2552
2553         u8         dot3stats_frame_too_longs_low[0x20];
2554
2555         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2556
2557         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2558
2559         u8         dot3stats_symbol_errors_high[0x20];
2560
2561         u8         dot3stats_symbol_errors_low[0x20];
2562
2563         u8         dot3control_in_unknown_opcodes_high[0x20];
2564
2565         u8         dot3control_in_unknown_opcodes_low[0x20];
2566
2567         u8         dot3in_pause_frames_high[0x20];
2568
2569         u8         dot3in_pause_frames_low[0x20];
2570
2571         u8         dot3out_pause_frames_high[0x20];
2572
2573         u8         dot3out_pause_frames_low[0x20];
2574
2575         u8         reserved_at_400[0x3c0];
2576 };
2577
2578 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2579         u8         ether_stats_drop_events_high[0x20];
2580
2581         u8         ether_stats_drop_events_low[0x20];
2582
2583         u8         ether_stats_octets_high[0x20];
2584
2585         u8         ether_stats_octets_low[0x20];
2586
2587         u8         ether_stats_pkts_high[0x20];
2588
2589         u8         ether_stats_pkts_low[0x20];
2590
2591         u8         ether_stats_broadcast_pkts_high[0x20];
2592
2593         u8         ether_stats_broadcast_pkts_low[0x20];
2594
2595         u8         ether_stats_multicast_pkts_high[0x20];
2596
2597         u8         ether_stats_multicast_pkts_low[0x20];
2598
2599         u8         ether_stats_crc_align_errors_high[0x20];
2600
2601         u8         ether_stats_crc_align_errors_low[0x20];
2602
2603         u8         ether_stats_undersize_pkts_high[0x20];
2604
2605         u8         ether_stats_undersize_pkts_low[0x20];
2606
2607         u8         ether_stats_oversize_pkts_high[0x20];
2608
2609         u8         ether_stats_oversize_pkts_low[0x20];
2610
2611         u8         ether_stats_fragments_high[0x20];
2612
2613         u8         ether_stats_fragments_low[0x20];
2614
2615         u8         ether_stats_jabbers_high[0x20];
2616
2617         u8         ether_stats_jabbers_low[0x20];
2618
2619         u8         ether_stats_collisions_high[0x20];
2620
2621         u8         ether_stats_collisions_low[0x20];
2622
2623         u8         ether_stats_pkts64octets_high[0x20];
2624
2625         u8         ether_stats_pkts64octets_low[0x20];
2626
2627         u8         ether_stats_pkts65to127octets_high[0x20];
2628
2629         u8         ether_stats_pkts65to127octets_low[0x20];
2630
2631         u8         ether_stats_pkts128to255octets_high[0x20];
2632
2633         u8         ether_stats_pkts128to255octets_low[0x20];
2634
2635         u8         ether_stats_pkts256to511octets_high[0x20];
2636
2637         u8         ether_stats_pkts256to511octets_low[0x20];
2638
2639         u8         ether_stats_pkts512to1023octets_high[0x20];
2640
2641         u8         ether_stats_pkts512to1023octets_low[0x20];
2642
2643         u8         ether_stats_pkts1024to1518octets_high[0x20];
2644
2645         u8         ether_stats_pkts1024to1518octets_low[0x20];
2646
2647         u8         ether_stats_pkts1519to2047octets_high[0x20];
2648
2649         u8         ether_stats_pkts1519to2047octets_low[0x20];
2650
2651         u8         ether_stats_pkts2048to4095octets_high[0x20];
2652
2653         u8         ether_stats_pkts2048to4095octets_low[0x20];
2654
2655         u8         ether_stats_pkts4096to8191octets_high[0x20];
2656
2657         u8         ether_stats_pkts4096to8191octets_low[0x20];
2658
2659         u8         ether_stats_pkts8192to10239octets_high[0x20];
2660
2661         u8         ether_stats_pkts8192to10239octets_low[0x20];
2662
2663         u8         reserved_at_540[0x280];
2664 };
2665
2666 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2667         u8         if_in_octets_high[0x20];
2668
2669         u8         if_in_octets_low[0x20];
2670
2671         u8         if_in_ucast_pkts_high[0x20];
2672
2673         u8         if_in_ucast_pkts_low[0x20];
2674
2675         u8         if_in_discards_high[0x20];
2676
2677         u8         if_in_discards_low[0x20];
2678
2679         u8         if_in_errors_high[0x20];
2680
2681         u8         if_in_errors_low[0x20];
2682
2683         u8         if_in_unknown_protos_high[0x20];
2684
2685         u8         if_in_unknown_protos_low[0x20];
2686
2687         u8         if_out_octets_high[0x20];
2688
2689         u8         if_out_octets_low[0x20];
2690
2691         u8         if_out_ucast_pkts_high[0x20];
2692
2693         u8         if_out_ucast_pkts_low[0x20];
2694
2695         u8         if_out_discards_high[0x20];
2696
2697         u8         if_out_discards_low[0x20];
2698
2699         u8         if_out_errors_high[0x20];
2700
2701         u8         if_out_errors_low[0x20];
2702
2703         u8         if_in_multicast_pkts_high[0x20];
2704
2705         u8         if_in_multicast_pkts_low[0x20];
2706
2707         u8         if_in_broadcast_pkts_high[0x20];
2708
2709         u8         if_in_broadcast_pkts_low[0x20];
2710
2711         u8         if_out_multicast_pkts_high[0x20];
2712
2713         u8         if_out_multicast_pkts_low[0x20];
2714
2715         u8         if_out_broadcast_pkts_high[0x20];
2716
2717         u8         if_out_broadcast_pkts_low[0x20];
2718
2719         u8         reserved_at_340[0x480];
2720 };
2721
2722 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2723         u8         a_frames_transmitted_ok_high[0x20];
2724
2725         u8         a_frames_transmitted_ok_low[0x20];
2726
2727         u8         a_frames_received_ok_high[0x20];
2728
2729         u8         a_frames_received_ok_low[0x20];
2730
2731         u8         a_frame_check_sequence_errors_high[0x20];
2732
2733         u8         a_frame_check_sequence_errors_low[0x20];
2734
2735         u8         a_alignment_errors_high[0x20];
2736
2737         u8         a_alignment_errors_low[0x20];
2738
2739         u8         a_octets_transmitted_ok_high[0x20];
2740
2741         u8         a_octets_transmitted_ok_low[0x20];
2742
2743         u8         a_octets_received_ok_high[0x20];
2744
2745         u8         a_octets_received_ok_low[0x20];
2746
2747         u8         a_multicast_frames_xmitted_ok_high[0x20];
2748
2749         u8         a_multicast_frames_xmitted_ok_low[0x20];
2750
2751         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2752
2753         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2754
2755         u8         a_multicast_frames_received_ok_high[0x20];
2756
2757         u8         a_multicast_frames_received_ok_low[0x20];
2758
2759         u8         a_broadcast_frames_received_ok_high[0x20];
2760
2761         u8         a_broadcast_frames_received_ok_low[0x20];
2762
2763         u8         a_in_range_length_errors_high[0x20];
2764
2765         u8         a_in_range_length_errors_low[0x20];
2766
2767         u8         a_out_of_range_length_field_high[0x20];
2768
2769         u8         a_out_of_range_length_field_low[0x20];
2770
2771         u8         a_frame_too_long_errors_high[0x20];
2772
2773         u8         a_frame_too_long_errors_low[0x20];
2774
2775         u8         a_symbol_error_during_carrier_high[0x20];
2776
2777         u8         a_symbol_error_during_carrier_low[0x20];
2778
2779         u8         a_mac_control_frames_transmitted_high[0x20];
2780
2781         u8         a_mac_control_frames_transmitted_low[0x20];
2782
2783         u8         a_mac_control_frames_received_high[0x20];
2784
2785         u8         a_mac_control_frames_received_low[0x20];
2786
2787         u8         a_unsupported_opcodes_received_high[0x20];
2788
2789         u8         a_unsupported_opcodes_received_low[0x20];
2790
2791         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2792
2793         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2794
2795         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2796
2797         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2798
2799         u8         reserved_at_4c0[0x300];
2800 };
2801
2802 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2803         u8         life_time_counter_high[0x20];
2804
2805         u8         life_time_counter_low[0x20];
2806
2807         u8         rx_errors[0x20];
2808
2809         u8         tx_errors[0x20];
2810
2811         u8         l0_to_recovery_eieos[0x20];
2812
2813         u8         l0_to_recovery_ts[0x20];
2814
2815         u8         l0_to_recovery_framing[0x20];
2816
2817         u8         l0_to_recovery_retrain[0x20];
2818
2819         u8         crc_error_dllp[0x20];
2820
2821         u8         crc_error_tlp[0x20];
2822
2823         u8         tx_overflow_buffer_pkt_high[0x20];
2824
2825         u8         tx_overflow_buffer_pkt_low[0x20];
2826
2827         u8         outbound_stalled_reads[0x20];
2828
2829         u8         outbound_stalled_writes[0x20];
2830
2831         u8         outbound_stalled_reads_events[0x20];
2832
2833         u8         outbound_stalled_writes_events[0x20];
2834
2835         u8         reserved_at_200[0x5c0];
2836 };
2837
2838 struct mlx5_ifc_cmd_inter_comp_event_bits {
2839         u8         command_completion_vector[0x20];
2840
2841         u8         reserved_at_20[0xc0];
2842 };
2843
2844 struct mlx5_ifc_stall_vl_event_bits {
2845         u8         reserved_at_0[0x18];
2846         u8         port_num[0x1];
2847         u8         reserved_at_19[0x3];
2848         u8         vl[0x4];
2849
2850         u8         reserved_at_20[0xa0];
2851 };
2852
2853 struct mlx5_ifc_db_bf_congestion_event_bits {
2854         u8         event_subtype[0x8];
2855         u8         reserved_at_8[0x8];
2856         u8         congestion_level[0x8];
2857         u8         reserved_at_18[0x8];
2858
2859         u8         reserved_at_20[0xa0];
2860 };
2861
2862 struct mlx5_ifc_gpio_event_bits {
2863         u8         reserved_at_0[0x60];
2864
2865         u8         gpio_event_hi[0x20];
2866
2867         u8         gpio_event_lo[0x20];
2868
2869         u8         reserved_at_a0[0x40];
2870 };
2871
2872 struct mlx5_ifc_port_state_change_event_bits {
2873         u8         reserved_at_0[0x40];
2874
2875         u8         port_num[0x4];
2876         u8         reserved_at_44[0x1c];
2877
2878         u8         reserved_at_60[0x80];
2879 };
2880
2881 struct mlx5_ifc_dropped_packet_logged_bits {
2882         u8         reserved_at_0[0xe0];
2883 };
2884
2885 struct mlx5_ifc_default_timeout_bits {
2886         u8         to_multiplier[0x3];
2887         u8         reserved_at_3[0x9];
2888         u8         to_value[0x14];
2889 };
2890
2891 struct mlx5_ifc_dtor_reg_bits {
2892         u8         reserved_at_0[0x20];
2893
2894         struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
2895
2896         u8         reserved_at_40[0x60];
2897
2898         struct mlx5_ifc_default_timeout_bits health_poll_to;
2899
2900         struct mlx5_ifc_default_timeout_bits full_crdump_to;
2901
2902         struct mlx5_ifc_default_timeout_bits fw_reset_to;
2903
2904         struct mlx5_ifc_default_timeout_bits flush_on_err_to;
2905
2906         struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
2907
2908         struct mlx5_ifc_default_timeout_bits tear_down_to;
2909
2910         struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
2911
2912         struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
2913
2914         struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
2915
2916         u8         reserved_at_1c0[0x40];
2917 };
2918
2919 enum {
2920         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2921         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2922 };
2923
2924 struct mlx5_ifc_cq_error_bits {
2925         u8         reserved_at_0[0x8];
2926         u8         cqn[0x18];
2927
2928         u8         reserved_at_20[0x20];
2929
2930         u8         reserved_at_40[0x18];
2931         u8         syndrome[0x8];
2932
2933         u8         reserved_at_60[0x80];
2934 };
2935
2936 struct mlx5_ifc_rdma_page_fault_event_bits {
2937         u8         bytes_committed[0x20];
2938
2939         u8         r_key[0x20];
2940
2941         u8         reserved_at_40[0x10];
2942         u8         packet_len[0x10];
2943
2944         u8         rdma_op_len[0x20];
2945
2946         u8         rdma_va[0x40];
2947
2948         u8         reserved_at_c0[0x5];
2949         u8         rdma[0x1];
2950         u8         write[0x1];
2951         u8         requestor[0x1];
2952         u8         qp_number[0x18];
2953 };
2954
2955 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2956         u8         bytes_committed[0x20];
2957
2958         u8         reserved_at_20[0x10];
2959         u8         wqe_index[0x10];
2960
2961         u8         reserved_at_40[0x10];
2962         u8         len[0x10];
2963
2964         u8         reserved_at_60[0x60];
2965
2966         u8         reserved_at_c0[0x5];
2967         u8         rdma[0x1];
2968         u8         write_read[0x1];
2969         u8         requestor[0x1];
2970         u8         qpn[0x18];
2971 };
2972
2973 struct mlx5_ifc_qp_events_bits {
2974         u8         reserved_at_0[0xa0];
2975
2976         u8         type[0x8];
2977         u8         reserved_at_a8[0x18];
2978
2979         u8         reserved_at_c0[0x8];
2980         u8         qpn_rqn_sqn[0x18];
2981 };
2982
2983 struct mlx5_ifc_dct_events_bits {
2984         u8         reserved_at_0[0xc0];
2985
2986         u8         reserved_at_c0[0x8];
2987         u8         dct_number[0x18];
2988 };
2989
2990 struct mlx5_ifc_comp_event_bits {
2991         u8         reserved_at_0[0xc0];
2992
2993         u8         reserved_at_c0[0x8];
2994         u8         cq_number[0x18];
2995 };
2996
2997 enum {
2998         MLX5_QPC_STATE_RST        = 0x0,
2999         MLX5_QPC_STATE_INIT       = 0x1,
3000         MLX5_QPC_STATE_RTR        = 0x2,
3001         MLX5_QPC_STATE_RTS        = 0x3,
3002         MLX5_QPC_STATE_SQER       = 0x4,
3003         MLX5_QPC_STATE_ERR        = 0x6,
3004         MLX5_QPC_STATE_SQD        = 0x7,
3005         MLX5_QPC_STATE_SUSPENDED  = 0x9,
3006 };
3007
3008 enum {
3009         MLX5_QPC_ST_RC            = 0x0,
3010         MLX5_QPC_ST_UC            = 0x1,
3011         MLX5_QPC_ST_UD            = 0x2,
3012         MLX5_QPC_ST_XRC           = 0x3,
3013         MLX5_QPC_ST_DCI           = 0x5,
3014         MLX5_QPC_ST_QP0           = 0x7,
3015         MLX5_QPC_ST_QP1           = 0x8,
3016         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3017         MLX5_QPC_ST_REG_UMR       = 0xc,
3018 };
3019
3020 enum {
3021         MLX5_QPC_PM_STATE_ARMED     = 0x0,
3022         MLX5_QPC_PM_STATE_REARM     = 0x1,
3023         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3024         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3025 };
3026
3027 enum {
3028         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3029 };
3030
3031 enum {
3032         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3033         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3034 };
3035
3036 enum {
3037         MLX5_QPC_MTU_256_BYTES        = 0x1,
3038         MLX5_QPC_MTU_512_BYTES        = 0x2,
3039         MLX5_QPC_MTU_1K_BYTES         = 0x3,
3040         MLX5_QPC_MTU_2K_BYTES         = 0x4,
3041         MLX5_QPC_MTU_4K_BYTES         = 0x5,
3042         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3043 };
3044
3045 enum {
3046         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3047         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3048         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3049         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3050         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3051         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3052         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3053         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3054 };
3055
3056 enum {
3057         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3058         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3059         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3060 };
3061
3062 enum {
3063         MLX5_QPC_CS_RES_DISABLE    = 0x0,
3064         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3065         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3066 };
3067
3068 enum {
3069         MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3070         MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3071         MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3072 };
3073
3074 struct mlx5_ifc_qpc_bits {
3075         u8         state[0x4];
3076         u8         lag_tx_port_affinity[0x4];
3077         u8         st[0x8];
3078         u8         reserved_at_10[0x2];
3079         u8         isolate_vl_tc[0x1];
3080         u8         pm_state[0x2];
3081         u8         reserved_at_15[0x1];
3082         u8         req_e2e_credit_mode[0x2];
3083         u8         offload_type[0x4];
3084         u8         end_padding_mode[0x2];
3085         u8         reserved_at_1e[0x2];
3086
3087         u8         wq_signature[0x1];
3088         u8         block_lb_mc[0x1];
3089         u8         atomic_like_write_en[0x1];
3090         u8         latency_sensitive[0x1];
3091         u8         reserved_at_24[0x1];
3092         u8         drain_sigerr[0x1];
3093         u8         reserved_at_26[0x2];
3094         u8         pd[0x18];
3095
3096         u8         mtu[0x3];
3097         u8         log_msg_max[0x5];
3098         u8         reserved_at_48[0x1];
3099         u8         log_rq_size[0x4];
3100         u8         log_rq_stride[0x3];
3101         u8         no_sq[0x1];
3102         u8         log_sq_size[0x4];
3103         u8         reserved_at_55[0x3];
3104         u8         ts_format[0x2];
3105         u8         reserved_at_5a[0x1];
3106         u8         rlky[0x1];
3107         u8         ulp_stateless_offload_mode[0x4];
3108
3109         u8         counter_set_id[0x8];
3110         u8         uar_page[0x18];
3111
3112         u8         reserved_at_80[0x8];
3113         u8         user_index[0x18];
3114
3115         u8         reserved_at_a0[0x3];
3116         u8         log_page_size[0x5];
3117         u8         remote_qpn[0x18];
3118
3119         struct mlx5_ifc_ads_bits primary_address_path;
3120
3121         struct mlx5_ifc_ads_bits secondary_address_path;
3122
3123         u8         log_ack_req_freq[0x4];
3124         u8         reserved_at_384[0x4];
3125         u8         log_sra_max[0x3];
3126         u8         reserved_at_38b[0x2];
3127         u8         retry_count[0x3];
3128         u8         rnr_retry[0x3];
3129         u8         reserved_at_393[0x1];
3130         u8         fre[0x1];
3131         u8         cur_rnr_retry[0x3];
3132         u8         cur_retry_count[0x3];
3133         u8         reserved_at_39b[0x5];
3134
3135         u8         reserved_at_3a0[0x20];
3136
3137         u8         reserved_at_3c0[0x8];
3138         u8         next_send_psn[0x18];
3139
3140         u8         reserved_at_3e0[0x3];
3141         u8         log_num_dci_stream_channels[0x5];
3142         u8         cqn_snd[0x18];
3143
3144         u8         reserved_at_400[0x3];
3145         u8         log_num_dci_errored_streams[0x5];
3146         u8         deth_sqpn[0x18];
3147
3148         u8         reserved_at_420[0x20];
3149
3150         u8         reserved_at_440[0x8];
3151         u8         last_acked_psn[0x18];
3152
3153         u8         reserved_at_460[0x8];
3154         u8         ssn[0x18];
3155
3156         u8         reserved_at_480[0x8];
3157         u8         log_rra_max[0x3];
3158         u8         reserved_at_48b[0x1];
3159         u8         atomic_mode[0x4];
3160         u8         rre[0x1];
3161         u8         rwe[0x1];
3162         u8         rae[0x1];
3163         u8         reserved_at_493[0x1];
3164         u8         page_offset[0x6];
3165         u8         reserved_at_49a[0x3];
3166         u8         cd_slave_receive[0x1];
3167         u8         cd_slave_send[0x1];
3168         u8         cd_master[0x1];
3169
3170         u8         reserved_at_4a0[0x3];
3171         u8         min_rnr_nak[0x5];
3172         u8         next_rcv_psn[0x18];
3173
3174         u8         reserved_at_4c0[0x8];
3175         u8         xrcd[0x18];
3176
3177         u8         reserved_at_4e0[0x8];
3178         u8         cqn_rcv[0x18];
3179
3180         u8         dbr_addr[0x40];
3181
3182         u8         q_key[0x20];
3183
3184         u8         reserved_at_560[0x5];
3185         u8         rq_type[0x3];
3186         u8         srqn_rmpn_xrqn[0x18];
3187
3188         u8         reserved_at_580[0x8];
3189         u8         rmsn[0x18];
3190
3191         u8         hw_sq_wqebb_counter[0x10];
3192         u8         sw_sq_wqebb_counter[0x10];
3193
3194         u8         hw_rq_counter[0x20];
3195
3196         u8         sw_rq_counter[0x20];
3197
3198         u8         reserved_at_600[0x20];
3199
3200         u8         reserved_at_620[0xf];
3201         u8         cgs[0x1];
3202         u8         cs_req[0x8];
3203         u8         cs_res[0x8];
3204
3205         u8         dc_access_key[0x40];
3206
3207         u8         reserved_at_680[0x3];
3208         u8         dbr_umem_valid[0x1];
3209
3210         u8         reserved_at_684[0xbc];
3211 };
3212
3213 struct mlx5_ifc_roce_addr_layout_bits {
3214         u8         source_l3_address[16][0x8];
3215
3216         u8         reserved_at_80[0x3];
3217         u8         vlan_valid[0x1];
3218         u8         vlan_id[0xc];
3219         u8         source_mac_47_32[0x10];
3220
3221         u8         source_mac_31_0[0x20];
3222
3223         u8         reserved_at_c0[0x14];
3224         u8         roce_l3_type[0x4];
3225         u8         roce_version[0x8];
3226
3227         u8         reserved_at_e0[0x20];
3228 };
3229
3230 struct mlx5_ifc_shampo_cap_bits {
3231         u8    reserved_at_0[0x3];
3232         u8    shampo_log_max_reservation_size[0x5];
3233         u8    reserved_at_8[0x3];
3234         u8    shampo_log_min_reservation_size[0x5];
3235         u8    shampo_min_mss_size[0x10];
3236
3237         u8    reserved_at_20[0x3];
3238         u8    shampo_max_log_headers_entry_size[0x5];
3239         u8    reserved_at_28[0x18];
3240
3241         u8    reserved_at_40[0x7c0];
3242 };
3243
3244 union mlx5_ifc_hca_cap_union_bits {
3245         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3246         struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3247         struct mlx5_ifc_odp_cap_bits odp_cap;
3248         struct mlx5_ifc_atomic_caps_bits atomic_caps;
3249         struct mlx5_ifc_roce_cap_bits roce_cap;
3250         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3251         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3252         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3253         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3254         struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3255         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3256         struct mlx5_ifc_qos_cap_bits qos_cap;
3257         struct mlx5_ifc_debug_cap_bits debug_cap;
3258         struct mlx5_ifc_fpga_cap_bits fpga_cap;
3259         struct mlx5_ifc_tls_cap_bits tls_cap;
3260         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3261         struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3262         struct mlx5_ifc_shampo_cap_bits shampo_cap;
3263         u8         reserved_at_0[0x8000];
3264 };
3265
3266 enum {
3267         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3268         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3269         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3270         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3271         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3272         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3273         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3274         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3275         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3276         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3277         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3278         MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3279         MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3280 };
3281
3282 enum {
3283         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3284         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3285         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3286 };
3287
3288 struct mlx5_ifc_vlan_bits {
3289         u8         ethtype[0x10];
3290         u8         prio[0x3];
3291         u8         cfi[0x1];
3292         u8         vid[0xc];
3293 };
3294
3295 struct mlx5_ifc_flow_context_bits {
3296         struct mlx5_ifc_vlan_bits push_vlan;
3297
3298         u8         group_id[0x20];
3299
3300         u8         reserved_at_40[0x8];
3301         u8         flow_tag[0x18];
3302
3303         u8         reserved_at_60[0x10];
3304         u8         action[0x10];
3305
3306         u8         extended_destination[0x1];
3307         u8         reserved_at_81[0x1];
3308         u8         flow_source[0x2];
3309         u8         reserved_at_84[0x4];
3310         u8         destination_list_size[0x18];
3311
3312         u8         reserved_at_a0[0x8];
3313         u8         flow_counter_list_size[0x18];
3314
3315         u8         packet_reformat_id[0x20];
3316
3317         u8         modify_header_id[0x20];
3318
3319         struct mlx5_ifc_vlan_bits push_vlan_2;
3320
3321         u8         ipsec_obj_id[0x20];
3322         u8         reserved_at_140[0xc0];
3323
3324         struct mlx5_ifc_fte_match_param_bits match_value;
3325
3326         u8         reserved_at_1200[0x600];
3327
3328         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3329 };
3330
3331 enum {
3332         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3333         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3334 };
3335
3336 struct mlx5_ifc_xrc_srqc_bits {
3337         u8         state[0x4];
3338         u8         log_xrc_srq_size[0x4];
3339         u8         reserved_at_8[0x18];
3340
3341         u8         wq_signature[0x1];
3342         u8         cont_srq[0x1];
3343         u8         reserved_at_22[0x1];
3344         u8         rlky[0x1];
3345         u8         basic_cyclic_rcv_wqe[0x1];
3346         u8         log_rq_stride[0x3];
3347         u8         xrcd[0x18];
3348
3349         u8         page_offset[0x6];
3350         u8         reserved_at_46[0x1];
3351         u8         dbr_umem_valid[0x1];
3352         u8         cqn[0x18];
3353
3354         u8         reserved_at_60[0x20];
3355
3356         u8         user_index_equal_xrc_srqn[0x1];
3357         u8         reserved_at_81[0x1];
3358         u8         log_page_size[0x6];
3359         u8         user_index[0x18];
3360
3361         u8         reserved_at_a0[0x20];
3362
3363         u8         reserved_at_c0[0x8];
3364         u8         pd[0x18];
3365
3366         u8         lwm[0x10];
3367         u8         wqe_cnt[0x10];
3368
3369         u8         reserved_at_100[0x40];
3370
3371         u8         db_record_addr_h[0x20];
3372
3373         u8         db_record_addr_l[0x1e];
3374         u8         reserved_at_17e[0x2];
3375
3376         u8         reserved_at_180[0x80];
3377 };
3378
3379 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3380         u8         counter_error_queues[0x20];
3381
3382         u8         total_error_queues[0x20];
3383
3384         u8         send_queue_priority_update_flow[0x20];
3385
3386         u8         reserved_at_60[0x20];
3387
3388         u8         nic_receive_steering_discard[0x40];
3389
3390         u8         receive_discard_vport_down[0x40];
3391
3392         u8         transmit_discard_vport_down[0x40];
3393
3394         u8         reserved_at_140[0xa0];
3395
3396         u8         internal_rq_out_of_buffer[0x20];
3397
3398         u8         reserved_at_200[0xe00];
3399 };
3400
3401 struct mlx5_ifc_traffic_counter_bits {
3402         u8         packets[0x40];
3403
3404         u8         octets[0x40];
3405 };
3406
3407 struct mlx5_ifc_tisc_bits {
3408         u8         strict_lag_tx_port_affinity[0x1];
3409         u8         tls_en[0x1];
3410         u8         reserved_at_2[0x2];
3411         u8         lag_tx_port_affinity[0x04];
3412
3413         u8         reserved_at_8[0x4];
3414         u8         prio[0x4];
3415         u8         reserved_at_10[0x10];
3416
3417         u8         reserved_at_20[0x100];
3418
3419         u8         reserved_at_120[0x8];
3420         u8         transport_domain[0x18];
3421
3422         u8         reserved_at_140[0x8];
3423         u8         underlay_qpn[0x18];
3424
3425         u8         reserved_at_160[0x8];
3426         u8         pd[0x18];
3427
3428         u8         reserved_at_180[0x380];
3429 };
3430
3431 enum {
3432         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3433         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3434 };
3435
3436 enum {
3437         MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3438         MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3439 };
3440
3441 enum {
3442         MLX5_RX_HASH_FN_NONE           = 0x0,
3443         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3444         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3445 };
3446
3447 enum {
3448         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3449         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3450 };
3451
3452 struct mlx5_ifc_tirc_bits {
3453         u8         reserved_at_0[0x20];
3454
3455         u8         disp_type[0x4];
3456         u8         tls_en[0x1];
3457         u8         reserved_at_25[0x1b];
3458
3459         u8         reserved_at_40[0x40];
3460
3461         u8         reserved_at_80[0x4];
3462         u8         lro_timeout_period_usecs[0x10];
3463         u8         packet_merge_mask[0x4];
3464         u8         lro_max_ip_payload_size[0x8];
3465
3466         u8         reserved_at_a0[0x40];
3467
3468         u8         reserved_at_e0[0x8];
3469         u8         inline_rqn[0x18];
3470
3471         u8         rx_hash_symmetric[0x1];
3472         u8         reserved_at_101[0x1];
3473         u8         tunneled_offload_en[0x1];
3474         u8         reserved_at_103[0x5];
3475         u8         indirect_table[0x18];
3476
3477         u8         rx_hash_fn[0x4];
3478         u8         reserved_at_124[0x2];
3479         u8         self_lb_block[0x2];
3480         u8         transport_domain[0x18];
3481
3482         u8         rx_hash_toeplitz_key[10][0x20];
3483
3484         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3485
3486         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3487
3488         u8         reserved_at_2c0[0x4c0];
3489 };
3490
3491 enum {
3492         MLX5_SRQC_STATE_GOOD   = 0x0,
3493         MLX5_SRQC_STATE_ERROR  = 0x1,
3494 };
3495
3496 struct mlx5_ifc_srqc_bits {
3497         u8         state[0x4];
3498         u8         log_srq_size[0x4];
3499         u8         reserved_at_8[0x18];
3500
3501         u8         wq_signature[0x1];
3502         u8         cont_srq[0x1];
3503         u8         reserved_at_22[0x1];
3504         u8         rlky[0x1];
3505         u8         reserved_at_24[0x1];
3506         u8         log_rq_stride[0x3];
3507         u8         xrcd[0x18];
3508
3509         u8         page_offset[0x6];
3510         u8         reserved_at_46[0x2];
3511         u8         cqn[0x18];
3512
3513         u8         reserved_at_60[0x20];
3514
3515         u8         reserved_at_80[0x2];
3516         u8         log_page_size[0x6];
3517         u8         reserved_at_88[0x18];
3518
3519         u8         reserved_at_a0[0x20];
3520
3521         u8         reserved_at_c0[0x8];
3522         u8         pd[0x18];
3523
3524         u8         lwm[0x10];
3525         u8         wqe_cnt[0x10];
3526
3527         u8         reserved_at_100[0x40];
3528
3529         u8         dbr_addr[0x40];
3530
3531         u8         reserved_at_180[0x80];
3532 };
3533
3534 enum {
3535         MLX5_SQC_STATE_RST  = 0x0,
3536         MLX5_SQC_STATE_RDY  = 0x1,
3537         MLX5_SQC_STATE_ERR  = 0x3,
3538 };
3539
3540 struct mlx5_ifc_sqc_bits {
3541         u8         rlky[0x1];
3542         u8         cd_master[0x1];
3543         u8         fre[0x1];
3544         u8         flush_in_error_en[0x1];
3545         u8         allow_multi_pkt_send_wqe[0x1];
3546         u8         min_wqe_inline_mode[0x3];
3547         u8         state[0x4];
3548         u8         reg_umr[0x1];
3549         u8         allow_swp[0x1];
3550         u8         hairpin[0x1];
3551         u8         reserved_at_f[0xb];
3552         u8         ts_format[0x2];
3553         u8         reserved_at_1c[0x4];
3554
3555         u8         reserved_at_20[0x8];
3556         u8         user_index[0x18];
3557
3558         u8         reserved_at_40[0x8];
3559         u8         cqn[0x18];
3560
3561         u8         reserved_at_60[0x8];
3562         u8         hairpin_peer_rq[0x18];
3563
3564         u8         reserved_at_80[0x10];
3565         u8         hairpin_peer_vhca[0x10];
3566
3567         u8         reserved_at_a0[0x20];
3568
3569         u8         reserved_at_c0[0x8];
3570         u8         ts_cqe_to_dest_cqn[0x18];
3571
3572         u8         reserved_at_e0[0x10];
3573         u8         packet_pacing_rate_limit_index[0x10];
3574         u8         tis_lst_sz[0x10];
3575         u8         qos_queue_group_id[0x10];
3576
3577         u8         reserved_at_120[0x40];
3578
3579         u8         reserved_at_160[0x8];
3580         u8         tis_num_0[0x18];
3581
3582         struct mlx5_ifc_wq_bits wq;
3583 };
3584
3585 enum {
3586         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3587         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3588         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3589         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3590         SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3591 };
3592
3593 enum {
3594         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3595         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3596         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3597         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3598 };
3599
3600 struct mlx5_ifc_scheduling_context_bits {
3601         u8         element_type[0x8];
3602         u8         reserved_at_8[0x18];
3603
3604         u8         element_attributes[0x20];
3605
3606         u8         parent_element_id[0x20];
3607
3608         u8         reserved_at_60[0x40];
3609
3610         u8         bw_share[0x20];
3611
3612         u8         max_average_bw[0x20];
3613
3614         u8         reserved_at_e0[0x120];
3615 };
3616
3617 struct mlx5_ifc_rqtc_bits {
3618         u8    reserved_at_0[0xa0];
3619
3620         u8    reserved_at_a0[0x5];
3621         u8    list_q_type[0x3];
3622         u8    reserved_at_a8[0x8];
3623         u8    rqt_max_size[0x10];
3624
3625         u8    rq_vhca_id_format[0x1];
3626         u8    reserved_at_c1[0xf];
3627         u8    rqt_actual_size[0x10];
3628
3629         u8    reserved_at_e0[0x6a0];
3630
3631         struct mlx5_ifc_rq_num_bits rq_num[];
3632 };
3633
3634 enum {
3635         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3636         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3637 };
3638
3639 enum {
3640         MLX5_RQC_STATE_RST  = 0x0,
3641         MLX5_RQC_STATE_RDY  = 0x1,
3642         MLX5_RQC_STATE_ERR  = 0x3,
3643 };
3644
3645 enum {
3646         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
3647         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
3648         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
3649 };
3650
3651 enum {
3652         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
3653         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
3654         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
3655 };
3656
3657 struct mlx5_ifc_rqc_bits {
3658         u8         rlky[0x1];
3659         u8         delay_drop_en[0x1];
3660         u8         scatter_fcs[0x1];
3661         u8         vsd[0x1];
3662         u8         mem_rq_type[0x4];
3663         u8         state[0x4];
3664         u8         reserved_at_c[0x1];
3665         u8         flush_in_error_en[0x1];
3666         u8         hairpin[0x1];
3667         u8         reserved_at_f[0xb];
3668         u8         ts_format[0x2];
3669         u8         reserved_at_1c[0x4];
3670
3671         u8         reserved_at_20[0x8];
3672         u8         user_index[0x18];
3673
3674         u8         reserved_at_40[0x8];
3675         u8         cqn[0x18];
3676
3677         u8         counter_set_id[0x8];
3678         u8         reserved_at_68[0x18];
3679
3680         u8         reserved_at_80[0x8];
3681         u8         rmpn[0x18];
3682
3683         u8         reserved_at_a0[0x8];
3684         u8         hairpin_peer_sq[0x18];
3685
3686         u8         reserved_at_c0[0x10];
3687         u8         hairpin_peer_vhca[0x10];
3688
3689         u8         reserved_at_e0[0x46];
3690         u8         shampo_no_match_alignment_granularity[0x2];
3691         u8         reserved_at_128[0x6];
3692         u8         shampo_match_criteria_type[0x2];
3693         u8         reservation_timeout[0x10];
3694
3695         u8         reserved_at_140[0x40];
3696
3697         struct mlx5_ifc_wq_bits wq;
3698 };
3699
3700 enum {
3701         MLX5_RMPC_STATE_RDY  = 0x1,
3702         MLX5_RMPC_STATE_ERR  = 0x3,
3703 };
3704
3705 struct mlx5_ifc_rmpc_bits {
3706         u8         reserved_at_0[0x8];
3707         u8         state[0x4];
3708         u8         reserved_at_c[0x14];
3709
3710         u8         basic_cyclic_rcv_wqe[0x1];
3711         u8         reserved_at_21[0x1f];
3712
3713         u8         reserved_at_40[0x140];
3714
3715         struct mlx5_ifc_wq_bits wq;
3716 };
3717
3718 struct mlx5_ifc_nic_vport_context_bits {
3719         u8         reserved_at_0[0x5];
3720         u8         min_wqe_inline_mode[0x3];
3721         u8         reserved_at_8[0x15];
3722         u8         disable_mc_local_lb[0x1];
3723         u8         disable_uc_local_lb[0x1];
3724         u8         roce_en[0x1];
3725
3726         u8         arm_change_event[0x1];
3727         u8         reserved_at_21[0x1a];
3728         u8         event_on_mtu[0x1];
3729         u8         event_on_promisc_change[0x1];
3730         u8         event_on_vlan_change[0x1];
3731         u8         event_on_mc_address_change[0x1];
3732         u8         event_on_uc_address_change[0x1];
3733
3734         u8         reserved_at_40[0xc];
3735
3736         u8         affiliation_criteria[0x4];
3737         u8         affiliated_vhca_id[0x10];
3738
3739         u8         reserved_at_60[0xd0];
3740
3741         u8         mtu[0x10];
3742
3743         u8         system_image_guid[0x40];
3744         u8         port_guid[0x40];
3745         u8         node_guid[0x40];
3746
3747         u8         reserved_at_200[0x140];
3748         u8         qkey_violation_counter[0x10];
3749         u8         reserved_at_350[0x430];
3750
3751         u8         promisc_uc[0x1];
3752         u8         promisc_mc[0x1];
3753         u8         promisc_all[0x1];
3754         u8         reserved_at_783[0x2];
3755         u8         allowed_list_type[0x3];
3756         u8         reserved_at_788[0xc];
3757         u8         allowed_list_size[0xc];
3758
3759         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3760
3761         u8         reserved_at_7e0[0x20];
3762
3763         u8         current_uc_mac_address[][0x40];
3764 };
3765
3766 enum {
3767         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3768         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3769         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3770         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3771         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3772         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3773 };
3774
3775 struct mlx5_ifc_mkc_bits {
3776         u8         reserved_at_0[0x1];
3777         u8         free[0x1];
3778         u8         reserved_at_2[0x1];
3779         u8         access_mode_4_2[0x3];
3780         u8         reserved_at_6[0x7];
3781         u8         relaxed_ordering_write[0x1];
3782         u8         reserved_at_e[0x1];
3783         u8         small_fence_on_rdma_read_response[0x1];
3784         u8         umr_en[0x1];
3785         u8         a[0x1];
3786         u8         rw[0x1];
3787         u8         rr[0x1];
3788         u8         lw[0x1];
3789         u8         lr[0x1];
3790         u8         access_mode_1_0[0x2];
3791         u8         reserved_at_18[0x8];
3792
3793         u8         qpn[0x18];
3794         u8         mkey_7_0[0x8];
3795
3796         u8         reserved_at_40[0x20];
3797
3798         u8         length64[0x1];
3799         u8         bsf_en[0x1];
3800         u8         sync_umr[0x1];
3801         u8         reserved_at_63[0x2];
3802         u8         expected_sigerr_count[0x1];
3803         u8         reserved_at_66[0x1];
3804         u8         en_rinval[0x1];
3805         u8         pd[0x18];
3806
3807         u8         start_addr[0x40];
3808
3809         u8         len[0x40];
3810
3811         u8         bsf_octword_size[0x20];
3812
3813         u8         reserved_at_120[0x80];
3814
3815         u8         translations_octword_size[0x20];
3816
3817         u8         reserved_at_1c0[0x19];
3818         u8         relaxed_ordering_read[0x1];
3819         u8         reserved_at_1d9[0x1];
3820         u8         log_page_size[0x5];
3821
3822         u8         reserved_at_1e0[0x20];
3823 };
3824
3825 struct mlx5_ifc_pkey_bits {
3826         u8         reserved_at_0[0x10];
3827         u8         pkey[0x10];
3828 };
3829
3830 struct mlx5_ifc_array128_auto_bits {
3831         u8         array128_auto[16][0x8];
3832 };
3833
3834 struct mlx5_ifc_hca_vport_context_bits {
3835         u8         field_select[0x20];
3836
3837         u8         reserved_at_20[0xe0];
3838
3839         u8         sm_virt_aware[0x1];
3840         u8         has_smi[0x1];
3841         u8         has_raw[0x1];
3842         u8         grh_required[0x1];
3843         u8         reserved_at_104[0xc];
3844         u8         port_physical_state[0x4];
3845         u8         vport_state_policy[0x4];
3846         u8         port_state[0x4];
3847         u8         vport_state[0x4];
3848
3849         u8         reserved_at_120[0x20];
3850
3851         u8         system_image_guid[0x40];
3852
3853         u8         port_guid[0x40];
3854
3855         u8         node_guid[0x40];
3856
3857         u8         cap_mask1[0x20];
3858
3859         u8         cap_mask1_field_select[0x20];
3860
3861         u8         cap_mask2[0x20];
3862
3863         u8         cap_mask2_field_select[0x20];
3864
3865         u8         reserved_at_280[0x80];
3866
3867         u8         lid[0x10];
3868         u8         reserved_at_310[0x4];
3869         u8         init_type_reply[0x4];
3870         u8         lmc[0x3];
3871         u8         subnet_timeout[0x5];
3872
3873         u8         sm_lid[0x10];
3874         u8         sm_sl[0x4];
3875         u8         reserved_at_334[0xc];
3876
3877         u8         qkey_violation_counter[0x10];
3878         u8         pkey_violation_counter[0x10];
3879
3880         u8         reserved_at_360[0xca0];
3881 };
3882
3883 struct mlx5_ifc_esw_vport_context_bits {
3884         u8         fdb_to_vport_reg_c[0x1];
3885         u8         reserved_at_1[0x2];
3886         u8         vport_svlan_strip[0x1];
3887         u8         vport_cvlan_strip[0x1];
3888         u8         vport_svlan_insert[0x1];
3889         u8         vport_cvlan_insert[0x2];
3890         u8         fdb_to_vport_reg_c_id[0x8];
3891         u8         reserved_at_10[0x10];
3892
3893         u8         reserved_at_20[0x20];
3894
3895         u8         svlan_cfi[0x1];
3896         u8         svlan_pcp[0x3];
3897         u8         svlan_id[0xc];
3898         u8         cvlan_cfi[0x1];
3899         u8         cvlan_pcp[0x3];
3900         u8         cvlan_id[0xc];
3901
3902         u8         reserved_at_60[0x720];
3903
3904         u8         sw_steering_vport_icm_address_rx[0x40];
3905
3906         u8         sw_steering_vport_icm_address_tx[0x40];
3907 };
3908
3909 enum {
3910         MLX5_EQC_STATUS_OK                = 0x0,
3911         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3912 };
3913
3914 enum {
3915         MLX5_EQC_ST_ARMED  = 0x9,
3916         MLX5_EQC_ST_FIRED  = 0xa,
3917 };
3918
3919 struct mlx5_ifc_eqc_bits {
3920         u8         status[0x4];
3921         u8         reserved_at_4[0x9];
3922         u8         ec[0x1];
3923         u8         oi[0x1];
3924         u8         reserved_at_f[0x5];
3925         u8         st[0x4];
3926         u8         reserved_at_18[0x8];
3927
3928         u8         reserved_at_20[0x20];
3929
3930         u8         reserved_at_40[0x14];
3931         u8         page_offset[0x6];
3932         u8         reserved_at_5a[0x6];
3933
3934         u8         reserved_at_60[0x3];
3935         u8         log_eq_size[0x5];
3936         u8         uar_page[0x18];
3937
3938         u8         reserved_at_80[0x20];
3939
3940         u8         reserved_at_a0[0x14];
3941         u8         intr[0xc];
3942
3943         u8         reserved_at_c0[0x3];
3944         u8         log_page_size[0x5];
3945         u8         reserved_at_c8[0x18];
3946
3947         u8         reserved_at_e0[0x60];
3948
3949         u8         reserved_at_140[0x8];
3950         u8         consumer_counter[0x18];
3951
3952         u8         reserved_at_160[0x8];
3953         u8         producer_counter[0x18];
3954
3955         u8         reserved_at_180[0x80];
3956 };
3957
3958 enum {
3959         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3960         MLX5_DCTC_STATE_DRAINING  = 0x1,
3961         MLX5_DCTC_STATE_DRAINED   = 0x2,
3962 };
3963
3964 enum {
3965         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3966         MLX5_DCTC_CS_RES_NA         = 0x1,
3967         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3968 };
3969
3970 enum {
3971         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3972         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3973         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3974         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3975         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3976 };
3977
3978 struct mlx5_ifc_dctc_bits {
3979         u8         reserved_at_0[0x4];
3980         u8         state[0x4];
3981         u8         reserved_at_8[0x18];
3982
3983         u8         reserved_at_20[0x8];
3984         u8         user_index[0x18];
3985
3986         u8         reserved_at_40[0x8];
3987         u8         cqn[0x18];
3988
3989         u8         counter_set_id[0x8];
3990         u8         atomic_mode[0x4];
3991         u8         rre[0x1];
3992         u8         rwe[0x1];
3993         u8         rae[0x1];
3994         u8         atomic_like_write_en[0x1];
3995         u8         latency_sensitive[0x1];
3996         u8         rlky[0x1];
3997         u8         free_ar[0x1];
3998         u8         reserved_at_73[0xd];
3999
4000         u8         reserved_at_80[0x8];
4001         u8         cs_res[0x8];
4002         u8         reserved_at_90[0x3];
4003         u8         min_rnr_nak[0x5];
4004         u8         reserved_at_98[0x8];
4005
4006         u8         reserved_at_a0[0x8];
4007         u8         srqn_xrqn[0x18];
4008
4009         u8         reserved_at_c0[0x8];
4010         u8         pd[0x18];
4011
4012         u8         tclass[0x8];
4013         u8         reserved_at_e8[0x4];
4014         u8         flow_label[0x14];
4015
4016         u8         dc_access_key[0x40];
4017
4018         u8         reserved_at_140[0x5];
4019         u8         mtu[0x3];
4020         u8         port[0x8];
4021         u8         pkey_index[0x10];
4022
4023         u8         reserved_at_160[0x8];
4024         u8         my_addr_index[0x8];
4025         u8         reserved_at_170[0x8];
4026         u8         hop_limit[0x8];
4027
4028         u8         dc_access_key_violation_count[0x20];
4029
4030         u8         reserved_at_1a0[0x14];
4031         u8         dei_cfi[0x1];
4032         u8         eth_prio[0x3];
4033         u8         ecn[0x2];
4034         u8         dscp[0x6];
4035
4036         u8         reserved_at_1c0[0x20];
4037         u8         ece[0x20];
4038 };
4039
4040 enum {
4041         MLX5_CQC_STATUS_OK             = 0x0,
4042         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4043         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4044 };
4045
4046 enum {
4047         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4048         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4049 };
4050
4051 enum {
4052         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4053         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4054         MLX5_CQC_ST_FIRED                                 = 0xa,
4055 };
4056
4057 enum {
4058         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4059         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4060         MLX5_CQ_PERIOD_NUM_MODES
4061 };
4062
4063 struct mlx5_ifc_cqc_bits {
4064         u8         status[0x4];
4065         u8         reserved_at_4[0x2];
4066         u8         dbr_umem_valid[0x1];
4067         u8         apu_cq[0x1];
4068         u8         cqe_sz[0x3];
4069         u8         cc[0x1];
4070         u8         reserved_at_c[0x1];
4071         u8         scqe_break_moderation_en[0x1];
4072         u8         oi[0x1];
4073         u8         cq_period_mode[0x2];
4074         u8         cqe_comp_en[0x1];
4075         u8         mini_cqe_res_format[0x2];
4076         u8         st[0x4];
4077         u8         reserved_at_18[0x8];
4078
4079         u8         reserved_at_20[0x20];
4080
4081         u8         reserved_at_40[0x14];
4082         u8         page_offset[0x6];
4083         u8         reserved_at_5a[0x6];
4084
4085         u8         reserved_at_60[0x3];
4086         u8         log_cq_size[0x5];
4087         u8         uar_page[0x18];
4088
4089         u8         reserved_at_80[0x4];
4090         u8         cq_period[0xc];
4091         u8         cq_max_count[0x10];
4092
4093         u8         c_eqn_or_apu_element[0x20];
4094
4095         u8         reserved_at_c0[0x3];
4096         u8         log_page_size[0x5];
4097         u8         reserved_at_c8[0x18];
4098
4099         u8         reserved_at_e0[0x20];
4100
4101         u8         reserved_at_100[0x8];
4102         u8         last_notified_index[0x18];
4103
4104         u8         reserved_at_120[0x8];
4105         u8         last_solicit_index[0x18];
4106
4107         u8         reserved_at_140[0x8];
4108         u8         consumer_counter[0x18];
4109
4110         u8         reserved_at_160[0x8];
4111         u8         producer_counter[0x18];
4112
4113         u8         reserved_at_180[0x40];
4114
4115         u8         dbr_addr[0x40];
4116 };
4117
4118 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4119         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4120         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4121         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4122         u8         reserved_at_0[0x800];
4123 };
4124
4125 struct mlx5_ifc_query_adapter_param_block_bits {
4126         u8         reserved_at_0[0xc0];
4127
4128         u8         reserved_at_c0[0x8];
4129         u8         ieee_vendor_id[0x18];
4130
4131         u8         reserved_at_e0[0x10];
4132         u8         vsd_vendor_id[0x10];
4133
4134         u8         vsd[208][0x8];
4135
4136         u8         vsd_contd_psid[16][0x8];
4137 };
4138
4139 enum {
4140         MLX5_XRQC_STATE_GOOD   = 0x0,
4141         MLX5_XRQC_STATE_ERROR  = 0x1,
4142 };
4143
4144 enum {
4145         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4146         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4147 };
4148
4149 enum {
4150         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4151 };
4152
4153 struct mlx5_ifc_tag_matching_topology_context_bits {
4154         u8         log_matching_list_sz[0x4];
4155         u8         reserved_at_4[0xc];
4156         u8         append_next_index[0x10];
4157
4158         u8         sw_phase_cnt[0x10];
4159         u8         hw_phase_cnt[0x10];
4160
4161         u8         reserved_at_40[0x40];
4162 };
4163
4164 struct mlx5_ifc_xrqc_bits {
4165         u8         state[0x4];
4166         u8         rlkey[0x1];
4167         u8         reserved_at_5[0xf];
4168         u8         topology[0x4];
4169         u8         reserved_at_18[0x4];
4170         u8         offload[0x4];
4171
4172         u8         reserved_at_20[0x8];
4173         u8         user_index[0x18];
4174
4175         u8         reserved_at_40[0x8];
4176         u8         cqn[0x18];
4177
4178         u8         reserved_at_60[0xa0];
4179
4180         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4181
4182         u8         reserved_at_180[0x280];
4183
4184         struct mlx5_ifc_wq_bits wq;
4185 };
4186
4187 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4188         struct mlx5_ifc_modify_field_select_bits modify_field_select;
4189         struct mlx5_ifc_resize_field_select_bits resize_field_select;
4190         u8         reserved_at_0[0x20];
4191 };
4192
4193 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4194         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4195         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4196         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4197         u8         reserved_at_0[0x20];
4198 };
4199
4200 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4201         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4202         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4203         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4204         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4205         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4206         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4207         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4208         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4209         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4210         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4211         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4212         u8         reserved_at_0[0x7c0];
4213 };
4214
4215 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4216         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4217         u8         reserved_at_0[0x7c0];
4218 };
4219
4220 union mlx5_ifc_event_auto_bits {
4221         struct mlx5_ifc_comp_event_bits comp_event;
4222         struct mlx5_ifc_dct_events_bits dct_events;
4223         struct mlx5_ifc_qp_events_bits qp_events;
4224         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4225         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4226         struct mlx5_ifc_cq_error_bits cq_error;
4227         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4228         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4229         struct mlx5_ifc_gpio_event_bits gpio_event;
4230         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4231         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4232         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4233         u8         reserved_at_0[0xe0];
4234 };
4235
4236 struct mlx5_ifc_health_buffer_bits {
4237         u8         reserved_at_0[0x100];
4238
4239         u8         assert_existptr[0x20];
4240
4241         u8         assert_callra[0x20];
4242
4243         u8         reserved_at_140[0x20];
4244
4245         u8         time[0x20];
4246
4247         u8         fw_version[0x20];
4248
4249         u8         hw_id[0x20];
4250
4251         u8         rfr[0x1];
4252         u8         reserved_at_1c1[0x3];
4253         u8         valid[0x1];
4254         u8         severity[0x3];
4255         u8         reserved_at_1c8[0x18];
4256
4257         u8         irisc_index[0x8];
4258         u8         synd[0x8];
4259         u8         ext_synd[0x10];
4260 };
4261
4262 struct mlx5_ifc_register_loopback_control_bits {
4263         u8         no_lb[0x1];
4264         u8         reserved_at_1[0x7];
4265         u8         port[0x8];
4266         u8         reserved_at_10[0x10];
4267
4268         u8         reserved_at_20[0x60];
4269 };
4270
4271 struct mlx5_ifc_vport_tc_element_bits {
4272         u8         traffic_class[0x4];
4273         u8         reserved_at_4[0xc];
4274         u8         vport_number[0x10];
4275 };
4276
4277 struct mlx5_ifc_vport_element_bits {
4278         u8         reserved_at_0[0x10];
4279         u8         vport_number[0x10];
4280 };
4281
4282 enum {
4283         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4284         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4285         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4286 };
4287
4288 struct mlx5_ifc_tsar_element_bits {
4289         u8         reserved_at_0[0x8];
4290         u8         tsar_type[0x8];
4291         u8         reserved_at_10[0x10];
4292 };
4293
4294 enum {
4295         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4296         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4297 };
4298
4299 struct mlx5_ifc_teardown_hca_out_bits {
4300         u8         status[0x8];
4301         u8         reserved_at_8[0x18];
4302
4303         u8         syndrome[0x20];
4304
4305         u8         reserved_at_40[0x3f];
4306
4307         u8         state[0x1];
4308 };
4309
4310 enum {
4311         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4312         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4313         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4314 };
4315
4316 struct mlx5_ifc_teardown_hca_in_bits {
4317         u8         opcode[0x10];
4318         u8         reserved_at_10[0x10];
4319
4320         u8         reserved_at_20[0x10];
4321         u8         op_mod[0x10];
4322
4323         u8         reserved_at_40[0x10];
4324         u8         profile[0x10];
4325
4326         u8         reserved_at_60[0x20];
4327 };
4328
4329 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4330         u8         status[0x8];
4331         u8         reserved_at_8[0x18];
4332
4333         u8         syndrome[0x20];
4334
4335         u8         reserved_at_40[0x40];
4336 };
4337
4338 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4339         u8         opcode[0x10];
4340         u8         uid[0x10];
4341
4342         u8         reserved_at_20[0x10];
4343         u8         op_mod[0x10];
4344
4345         u8         reserved_at_40[0x8];
4346         u8         qpn[0x18];
4347
4348         u8         reserved_at_60[0x20];
4349
4350         u8         opt_param_mask[0x20];
4351
4352         u8         reserved_at_a0[0x20];
4353
4354         struct mlx5_ifc_qpc_bits qpc;
4355
4356         u8         reserved_at_800[0x80];
4357 };
4358
4359 struct mlx5_ifc_sqd2rts_qp_out_bits {
4360         u8         status[0x8];
4361         u8         reserved_at_8[0x18];
4362
4363         u8         syndrome[0x20];
4364
4365         u8         reserved_at_40[0x40];
4366 };
4367
4368 struct mlx5_ifc_sqd2rts_qp_in_bits {
4369         u8         opcode[0x10];
4370         u8         uid[0x10];
4371
4372         u8         reserved_at_20[0x10];
4373         u8         op_mod[0x10];
4374
4375         u8         reserved_at_40[0x8];
4376         u8         qpn[0x18];
4377
4378         u8         reserved_at_60[0x20];
4379
4380         u8         opt_param_mask[0x20];
4381
4382         u8         reserved_at_a0[0x20];
4383
4384         struct mlx5_ifc_qpc_bits qpc;
4385
4386         u8         reserved_at_800[0x80];
4387 };
4388
4389 struct mlx5_ifc_set_roce_address_out_bits {
4390         u8         status[0x8];
4391         u8         reserved_at_8[0x18];
4392
4393         u8         syndrome[0x20];
4394
4395         u8         reserved_at_40[0x40];
4396 };
4397
4398 struct mlx5_ifc_set_roce_address_in_bits {
4399         u8         opcode[0x10];
4400         u8         reserved_at_10[0x10];
4401
4402         u8         reserved_at_20[0x10];
4403         u8         op_mod[0x10];
4404
4405         u8         roce_address_index[0x10];
4406         u8         reserved_at_50[0xc];
4407         u8         vhca_port_num[0x4];
4408
4409         u8         reserved_at_60[0x20];
4410
4411         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4412 };
4413
4414 struct mlx5_ifc_set_mad_demux_out_bits {
4415         u8         status[0x8];
4416         u8         reserved_at_8[0x18];
4417
4418         u8         syndrome[0x20];
4419
4420         u8         reserved_at_40[0x40];
4421 };
4422
4423 enum {
4424         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4425         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4426 };
4427
4428 struct mlx5_ifc_set_mad_demux_in_bits {
4429         u8         opcode[0x10];
4430         u8         reserved_at_10[0x10];
4431
4432         u8         reserved_at_20[0x10];
4433         u8         op_mod[0x10];
4434
4435         u8         reserved_at_40[0x20];
4436
4437         u8         reserved_at_60[0x6];
4438         u8         demux_mode[0x2];
4439         u8         reserved_at_68[0x18];
4440 };
4441
4442 struct mlx5_ifc_set_l2_table_entry_out_bits {
4443         u8         status[0x8];
4444         u8         reserved_at_8[0x18];
4445
4446         u8         syndrome[0x20];
4447
4448         u8         reserved_at_40[0x40];
4449 };
4450
4451 struct mlx5_ifc_set_l2_table_entry_in_bits {
4452         u8         opcode[0x10];
4453         u8         reserved_at_10[0x10];
4454
4455         u8         reserved_at_20[0x10];
4456         u8         op_mod[0x10];
4457
4458         u8         reserved_at_40[0x60];
4459
4460         u8         reserved_at_a0[0x8];
4461         u8         table_index[0x18];
4462
4463         u8         reserved_at_c0[0x20];
4464
4465         u8         reserved_at_e0[0x13];
4466         u8         vlan_valid[0x1];
4467         u8         vlan[0xc];
4468
4469         struct mlx5_ifc_mac_address_layout_bits mac_address;
4470
4471         u8         reserved_at_140[0xc0];
4472 };
4473
4474 struct mlx5_ifc_set_issi_out_bits {
4475         u8         status[0x8];
4476         u8         reserved_at_8[0x18];
4477
4478         u8         syndrome[0x20];
4479
4480         u8         reserved_at_40[0x40];
4481 };
4482
4483 struct mlx5_ifc_set_issi_in_bits {
4484         u8         opcode[0x10];
4485         u8         reserved_at_10[0x10];
4486
4487         u8         reserved_at_20[0x10];
4488         u8         op_mod[0x10];
4489
4490         u8         reserved_at_40[0x10];
4491         u8         current_issi[0x10];
4492
4493         u8         reserved_at_60[0x20];
4494 };
4495
4496 struct mlx5_ifc_set_hca_cap_out_bits {
4497         u8         status[0x8];
4498         u8         reserved_at_8[0x18];
4499
4500         u8         syndrome[0x20];
4501
4502         u8         reserved_at_40[0x40];
4503 };
4504
4505 struct mlx5_ifc_set_hca_cap_in_bits {
4506         u8         opcode[0x10];
4507         u8         reserved_at_10[0x10];
4508
4509         u8         reserved_at_20[0x10];
4510         u8         op_mod[0x10];
4511
4512         u8         other_function[0x1];
4513         u8         reserved_at_41[0xf];
4514         u8         function_id[0x10];
4515
4516         u8         reserved_at_60[0x20];
4517
4518         union mlx5_ifc_hca_cap_union_bits capability;
4519 };
4520
4521 enum {
4522         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4523         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4524         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4525         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4526         MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4527 };
4528
4529 struct mlx5_ifc_set_fte_out_bits {
4530         u8         status[0x8];
4531         u8         reserved_at_8[0x18];
4532
4533         u8         syndrome[0x20];
4534
4535         u8         reserved_at_40[0x40];
4536 };
4537
4538 struct mlx5_ifc_set_fte_in_bits {
4539         u8         opcode[0x10];
4540         u8         reserved_at_10[0x10];
4541
4542         u8         reserved_at_20[0x10];
4543         u8         op_mod[0x10];
4544
4545         u8         other_vport[0x1];
4546         u8         reserved_at_41[0xf];
4547         u8         vport_number[0x10];
4548
4549         u8         reserved_at_60[0x20];
4550
4551         u8         table_type[0x8];
4552         u8         reserved_at_88[0x18];
4553
4554         u8         reserved_at_a0[0x8];
4555         u8         table_id[0x18];
4556
4557         u8         ignore_flow_level[0x1];
4558         u8         reserved_at_c1[0x17];
4559         u8         modify_enable_mask[0x8];
4560
4561         u8         reserved_at_e0[0x20];
4562
4563         u8         flow_index[0x20];
4564
4565         u8         reserved_at_120[0xe0];
4566
4567         struct mlx5_ifc_flow_context_bits flow_context;
4568 };
4569
4570 struct mlx5_ifc_rts2rts_qp_out_bits {
4571         u8         status[0x8];
4572         u8         reserved_at_8[0x18];
4573
4574         u8         syndrome[0x20];
4575
4576         u8         reserved_at_40[0x20];
4577         u8         ece[0x20];
4578 };
4579
4580 struct mlx5_ifc_rts2rts_qp_in_bits {
4581         u8         opcode[0x10];
4582         u8         uid[0x10];
4583
4584         u8         reserved_at_20[0x10];
4585         u8         op_mod[0x10];
4586
4587         u8         reserved_at_40[0x8];
4588         u8         qpn[0x18];
4589
4590         u8         reserved_at_60[0x20];
4591
4592         u8         opt_param_mask[0x20];
4593
4594         u8         ece[0x20];
4595
4596         struct mlx5_ifc_qpc_bits qpc;
4597
4598         u8         reserved_at_800[0x80];
4599 };
4600
4601 struct mlx5_ifc_rtr2rts_qp_out_bits {
4602         u8         status[0x8];
4603         u8         reserved_at_8[0x18];
4604
4605         u8         syndrome[0x20];
4606
4607         u8         reserved_at_40[0x20];
4608         u8         ece[0x20];
4609 };
4610
4611 struct mlx5_ifc_rtr2rts_qp_in_bits {
4612         u8         opcode[0x10];
4613         u8         uid[0x10];
4614
4615         u8         reserved_at_20[0x10];
4616         u8         op_mod[0x10];
4617
4618         u8         reserved_at_40[0x8];
4619         u8         qpn[0x18];
4620
4621         u8         reserved_at_60[0x20];
4622
4623         u8         opt_param_mask[0x20];
4624
4625         u8         ece[0x20];
4626
4627         struct mlx5_ifc_qpc_bits qpc;
4628
4629         u8         reserved_at_800[0x80];
4630 };
4631
4632 struct mlx5_ifc_rst2init_qp_out_bits {
4633         u8         status[0x8];
4634         u8         reserved_at_8[0x18];
4635
4636         u8         syndrome[0x20];
4637
4638         u8         reserved_at_40[0x20];
4639         u8         ece[0x20];
4640 };
4641
4642 struct mlx5_ifc_rst2init_qp_in_bits {
4643         u8         opcode[0x10];
4644         u8         uid[0x10];
4645
4646         u8         reserved_at_20[0x10];
4647         u8         op_mod[0x10];
4648
4649         u8         reserved_at_40[0x8];
4650         u8         qpn[0x18];
4651
4652         u8         reserved_at_60[0x20];
4653
4654         u8         opt_param_mask[0x20];
4655
4656         u8         ece[0x20];
4657
4658         struct mlx5_ifc_qpc_bits qpc;
4659
4660         u8         reserved_at_800[0x80];
4661 };
4662
4663 struct mlx5_ifc_query_xrq_out_bits {
4664         u8         status[0x8];
4665         u8         reserved_at_8[0x18];
4666
4667         u8         syndrome[0x20];
4668
4669         u8         reserved_at_40[0x40];
4670
4671         struct mlx5_ifc_xrqc_bits xrq_context;
4672 };
4673
4674 struct mlx5_ifc_query_xrq_in_bits {
4675         u8         opcode[0x10];
4676         u8         reserved_at_10[0x10];
4677
4678         u8         reserved_at_20[0x10];
4679         u8         op_mod[0x10];
4680
4681         u8         reserved_at_40[0x8];
4682         u8         xrqn[0x18];
4683
4684         u8         reserved_at_60[0x20];
4685 };
4686
4687 struct mlx5_ifc_query_xrc_srq_out_bits {
4688         u8         status[0x8];
4689         u8         reserved_at_8[0x18];
4690
4691         u8         syndrome[0x20];
4692
4693         u8         reserved_at_40[0x40];
4694
4695         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4696
4697         u8         reserved_at_280[0x600];
4698
4699         u8         pas[][0x40];
4700 };
4701
4702 struct mlx5_ifc_query_xrc_srq_in_bits {
4703         u8         opcode[0x10];
4704         u8         reserved_at_10[0x10];
4705
4706         u8         reserved_at_20[0x10];
4707         u8         op_mod[0x10];
4708
4709         u8         reserved_at_40[0x8];
4710         u8         xrc_srqn[0x18];
4711
4712         u8         reserved_at_60[0x20];
4713 };
4714
4715 enum {
4716         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4717         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4718 };
4719
4720 struct mlx5_ifc_query_vport_state_out_bits {
4721         u8         status[0x8];
4722         u8         reserved_at_8[0x18];
4723
4724         u8         syndrome[0x20];
4725
4726         u8         reserved_at_40[0x20];
4727
4728         u8         reserved_at_60[0x18];
4729         u8         admin_state[0x4];
4730         u8         state[0x4];
4731 };
4732
4733 enum {
4734         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4735         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4736         MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4737 };
4738
4739 struct mlx5_ifc_arm_monitor_counter_in_bits {
4740         u8         opcode[0x10];
4741         u8         uid[0x10];
4742
4743         u8         reserved_at_20[0x10];
4744         u8         op_mod[0x10];
4745
4746         u8         reserved_at_40[0x20];
4747
4748         u8         reserved_at_60[0x20];
4749 };
4750
4751 struct mlx5_ifc_arm_monitor_counter_out_bits {
4752         u8         status[0x8];
4753         u8         reserved_at_8[0x18];
4754
4755         u8         syndrome[0x20];
4756
4757         u8         reserved_at_40[0x40];
4758 };
4759
4760 enum {
4761         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4762         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4763 };
4764
4765 enum mlx5_monitor_counter_ppcnt {
4766         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4767         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4768         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4769         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4770         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4771         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4772 };
4773
4774 enum {
4775         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4776 };
4777
4778 struct mlx5_ifc_monitor_counter_output_bits {
4779         u8         reserved_at_0[0x4];
4780         u8         type[0x4];
4781         u8         reserved_at_8[0x8];
4782         u8         counter[0x10];
4783
4784         u8         counter_group_id[0x20];
4785 };
4786
4787 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4788 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4789 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4790                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4791
4792 struct mlx5_ifc_set_monitor_counter_in_bits {
4793         u8         opcode[0x10];
4794         u8         uid[0x10];
4795
4796         u8         reserved_at_20[0x10];
4797         u8         op_mod[0x10];
4798
4799         u8         reserved_at_40[0x10];
4800         u8         num_of_counters[0x10];
4801
4802         u8         reserved_at_60[0x20];
4803
4804         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4805 };
4806
4807 struct mlx5_ifc_set_monitor_counter_out_bits {
4808         u8         status[0x8];
4809         u8         reserved_at_8[0x18];
4810
4811         u8         syndrome[0x20];
4812
4813         u8         reserved_at_40[0x40];
4814 };
4815
4816 struct mlx5_ifc_query_vport_state_in_bits {
4817         u8         opcode[0x10];
4818         u8         reserved_at_10[0x10];
4819
4820         u8         reserved_at_20[0x10];
4821         u8         op_mod[0x10];
4822
4823         u8         other_vport[0x1];
4824         u8         reserved_at_41[0xf];
4825         u8         vport_number[0x10];
4826
4827         u8         reserved_at_60[0x20];
4828 };
4829
4830 struct mlx5_ifc_query_vnic_env_out_bits {
4831         u8         status[0x8];
4832         u8         reserved_at_8[0x18];
4833
4834         u8         syndrome[0x20];
4835
4836         u8         reserved_at_40[0x40];
4837
4838         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4839 };
4840
4841 enum {
4842         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4843 };
4844
4845 struct mlx5_ifc_query_vnic_env_in_bits {
4846         u8         opcode[0x10];
4847         u8         reserved_at_10[0x10];
4848
4849         u8         reserved_at_20[0x10];
4850         u8         op_mod[0x10];
4851
4852         u8         other_vport[0x1];
4853         u8         reserved_at_41[0xf];
4854         u8         vport_number[0x10];
4855
4856         u8         reserved_at_60[0x20];
4857 };
4858
4859 struct mlx5_ifc_query_vport_counter_out_bits {
4860         u8         status[0x8];
4861         u8         reserved_at_8[0x18];
4862
4863         u8         syndrome[0x20];
4864
4865         u8         reserved_at_40[0x40];
4866
4867         struct mlx5_ifc_traffic_counter_bits received_errors;
4868
4869         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4870
4871         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4872
4873         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4874
4875         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4876
4877         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4878
4879         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4880
4881         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4882
4883         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4884
4885         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4886
4887         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4888
4889         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4890
4891         u8         reserved_at_680[0xa00];
4892 };
4893
4894 enum {
4895         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4896 };
4897
4898 struct mlx5_ifc_query_vport_counter_in_bits {
4899         u8         opcode[0x10];
4900         u8         reserved_at_10[0x10];
4901
4902         u8         reserved_at_20[0x10];
4903         u8         op_mod[0x10];
4904
4905         u8         other_vport[0x1];
4906         u8         reserved_at_41[0xb];
4907         u8         port_num[0x4];
4908         u8         vport_number[0x10];
4909
4910         u8         reserved_at_60[0x60];
4911
4912         u8         clear[0x1];
4913         u8         reserved_at_c1[0x1f];
4914
4915         u8         reserved_at_e0[0x20];
4916 };
4917
4918 struct mlx5_ifc_query_tis_out_bits {
4919         u8         status[0x8];
4920         u8         reserved_at_8[0x18];
4921
4922         u8         syndrome[0x20];
4923
4924         u8         reserved_at_40[0x40];
4925
4926         struct mlx5_ifc_tisc_bits tis_context;
4927 };
4928
4929 struct mlx5_ifc_query_tis_in_bits {
4930         u8         opcode[0x10];
4931         u8         reserved_at_10[0x10];
4932
4933         u8         reserved_at_20[0x10];
4934         u8         op_mod[0x10];
4935
4936         u8         reserved_at_40[0x8];
4937         u8         tisn[0x18];
4938
4939         u8         reserved_at_60[0x20];
4940 };
4941
4942 struct mlx5_ifc_query_tir_out_bits {
4943         u8         status[0x8];
4944         u8         reserved_at_8[0x18];
4945
4946         u8         syndrome[0x20];
4947
4948         u8         reserved_at_40[0xc0];
4949
4950         struct mlx5_ifc_tirc_bits tir_context;
4951 };
4952
4953 struct mlx5_ifc_query_tir_in_bits {
4954         u8         opcode[0x10];
4955         u8         reserved_at_10[0x10];
4956
4957         u8         reserved_at_20[0x10];
4958         u8         op_mod[0x10];
4959
4960         u8         reserved_at_40[0x8];
4961         u8         tirn[0x18];
4962
4963         u8         reserved_at_60[0x20];
4964 };
4965
4966 struct mlx5_ifc_query_srq_out_bits {
4967         u8         status[0x8];
4968         u8         reserved_at_8[0x18];
4969
4970         u8         syndrome[0x20];
4971
4972         u8         reserved_at_40[0x40];
4973
4974         struct mlx5_ifc_srqc_bits srq_context_entry;
4975
4976         u8         reserved_at_280[0x600];
4977
4978         u8         pas[][0x40];
4979 };
4980
4981 struct mlx5_ifc_query_srq_in_bits {
4982         u8         opcode[0x10];
4983         u8         reserved_at_10[0x10];
4984
4985         u8         reserved_at_20[0x10];
4986         u8         op_mod[0x10];
4987
4988         u8         reserved_at_40[0x8];
4989         u8         srqn[0x18];
4990
4991         u8         reserved_at_60[0x20];
4992 };
4993
4994 struct mlx5_ifc_query_sq_out_bits {
4995         u8         status[0x8];
4996         u8         reserved_at_8[0x18];
4997
4998         u8         syndrome[0x20];
4999
5000         u8         reserved_at_40[0xc0];
5001
5002         struct mlx5_ifc_sqc_bits sq_context;
5003 };
5004
5005 struct mlx5_ifc_query_sq_in_bits {
5006         u8         opcode[0x10];
5007         u8         reserved_at_10[0x10];
5008
5009         u8         reserved_at_20[0x10];
5010         u8         op_mod[0x10];
5011
5012         u8         reserved_at_40[0x8];
5013         u8         sqn[0x18];
5014
5015         u8         reserved_at_60[0x20];
5016 };
5017
5018 struct mlx5_ifc_query_special_contexts_out_bits {
5019         u8         status[0x8];
5020         u8         reserved_at_8[0x18];
5021
5022         u8         syndrome[0x20];
5023
5024         u8         dump_fill_mkey[0x20];
5025
5026         u8         resd_lkey[0x20];
5027
5028         u8         null_mkey[0x20];
5029
5030         u8         reserved_at_a0[0x60];
5031 };
5032
5033 struct mlx5_ifc_query_special_contexts_in_bits {
5034         u8         opcode[0x10];
5035         u8         reserved_at_10[0x10];
5036
5037         u8         reserved_at_20[0x10];
5038         u8         op_mod[0x10];
5039
5040         u8         reserved_at_40[0x40];
5041 };
5042
5043 struct mlx5_ifc_query_scheduling_element_out_bits {
5044         u8         opcode[0x10];
5045         u8         reserved_at_10[0x10];
5046
5047         u8         reserved_at_20[0x10];
5048         u8         op_mod[0x10];
5049
5050         u8         reserved_at_40[0xc0];
5051
5052         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5053
5054         u8         reserved_at_300[0x100];
5055 };
5056
5057 enum {
5058         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5059         SCHEDULING_HIERARCHY_NIC = 0x3,
5060 };
5061
5062 struct mlx5_ifc_query_scheduling_element_in_bits {
5063         u8         opcode[0x10];
5064         u8         reserved_at_10[0x10];
5065
5066         u8         reserved_at_20[0x10];
5067         u8         op_mod[0x10];
5068
5069         u8         scheduling_hierarchy[0x8];
5070         u8         reserved_at_48[0x18];
5071
5072         u8         scheduling_element_id[0x20];
5073
5074         u8         reserved_at_80[0x180];
5075 };
5076
5077 struct mlx5_ifc_query_rqt_out_bits {
5078         u8         status[0x8];
5079         u8         reserved_at_8[0x18];
5080
5081         u8         syndrome[0x20];
5082
5083         u8         reserved_at_40[0xc0];
5084
5085         struct mlx5_ifc_rqtc_bits rqt_context;
5086 };
5087
5088 struct mlx5_ifc_query_rqt_in_bits {
5089         u8         opcode[0x10];
5090         u8         reserved_at_10[0x10];
5091
5092         u8         reserved_at_20[0x10];
5093         u8         op_mod[0x10];
5094
5095         u8         reserved_at_40[0x8];
5096         u8         rqtn[0x18];
5097
5098         u8         reserved_at_60[0x20];
5099 };
5100
5101 struct mlx5_ifc_query_rq_out_bits {
5102         u8         status[0x8];
5103         u8         reserved_at_8[0x18];
5104
5105         u8         syndrome[0x20];
5106
5107         u8         reserved_at_40[0xc0];
5108
5109         struct mlx5_ifc_rqc_bits rq_context;
5110 };
5111
5112 struct mlx5_ifc_query_rq_in_bits {
5113         u8         opcode[0x10];
5114         u8         reserved_at_10[0x10];
5115
5116         u8         reserved_at_20[0x10];
5117         u8         op_mod[0x10];
5118
5119         u8         reserved_at_40[0x8];
5120         u8         rqn[0x18];
5121
5122         u8         reserved_at_60[0x20];
5123 };
5124
5125 struct mlx5_ifc_query_roce_address_out_bits {
5126         u8         status[0x8];
5127         u8         reserved_at_8[0x18];
5128
5129         u8         syndrome[0x20];
5130
5131         u8         reserved_at_40[0x40];
5132
5133         struct mlx5_ifc_roce_addr_layout_bits roce_address;
5134 };
5135
5136 struct mlx5_ifc_query_roce_address_in_bits {
5137         u8         opcode[0x10];
5138         u8         reserved_at_10[0x10];
5139
5140         u8         reserved_at_20[0x10];
5141         u8         op_mod[0x10];
5142
5143         u8         roce_address_index[0x10];
5144         u8         reserved_at_50[0xc];
5145         u8         vhca_port_num[0x4];
5146
5147         u8         reserved_at_60[0x20];
5148 };
5149
5150 struct mlx5_ifc_query_rmp_out_bits {
5151         u8         status[0x8];
5152         u8         reserved_at_8[0x18];
5153
5154         u8         syndrome[0x20];
5155
5156         u8         reserved_at_40[0xc0];
5157
5158         struct mlx5_ifc_rmpc_bits rmp_context;
5159 };
5160
5161 struct mlx5_ifc_query_rmp_in_bits {
5162         u8         opcode[0x10];
5163         u8         reserved_at_10[0x10];
5164
5165         u8         reserved_at_20[0x10];
5166         u8         op_mod[0x10];
5167
5168         u8         reserved_at_40[0x8];
5169         u8         rmpn[0x18];
5170
5171         u8         reserved_at_60[0x20];
5172 };
5173
5174 struct mlx5_ifc_query_qp_out_bits {
5175         u8         status[0x8];
5176         u8         reserved_at_8[0x18];
5177
5178         u8         syndrome[0x20];
5179
5180         u8         reserved_at_40[0x40];
5181
5182         u8         opt_param_mask[0x20];
5183
5184         u8         ece[0x20];
5185
5186         struct mlx5_ifc_qpc_bits qpc;
5187
5188         u8         reserved_at_800[0x80];
5189
5190         u8         pas[][0x40];
5191 };
5192
5193 struct mlx5_ifc_query_qp_in_bits {
5194         u8         opcode[0x10];
5195         u8         reserved_at_10[0x10];
5196
5197         u8         reserved_at_20[0x10];
5198         u8         op_mod[0x10];
5199
5200         u8         reserved_at_40[0x8];
5201         u8         qpn[0x18];
5202
5203         u8         reserved_at_60[0x20];
5204 };
5205
5206 struct mlx5_ifc_query_q_counter_out_bits {
5207         u8         status[0x8];
5208         u8         reserved_at_8[0x18];
5209
5210         u8         syndrome[0x20];
5211
5212         u8         reserved_at_40[0x40];
5213
5214         u8         rx_write_requests[0x20];
5215
5216         u8         reserved_at_a0[0x20];
5217
5218         u8         rx_read_requests[0x20];
5219
5220         u8         reserved_at_e0[0x20];
5221
5222         u8         rx_atomic_requests[0x20];
5223
5224         u8         reserved_at_120[0x20];
5225
5226         u8         rx_dct_connect[0x20];
5227
5228         u8         reserved_at_160[0x20];
5229
5230         u8         out_of_buffer[0x20];
5231
5232         u8         reserved_at_1a0[0x20];
5233
5234         u8         out_of_sequence[0x20];
5235
5236         u8         reserved_at_1e0[0x20];
5237
5238         u8         duplicate_request[0x20];
5239
5240         u8         reserved_at_220[0x20];
5241
5242         u8         rnr_nak_retry_err[0x20];
5243
5244         u8         reserved_at_260[0x20];
5245
5246         u8         packet_seq_err[0x20];
5247
5248         u8         reserved_at_2a0[0x20];
5249
5250         u8         implied_nak_seq_err[0x20];
5251
5252         u8         reserved_at_2e0[0x20];
5253
5254         u8         local_ack_timeout_err[0x20];
5255
5256         u8         reserved_at_320[0xa0];
5257
5258         u8         resp_local_length_error[0x20];
5259
5260         u8         req_local_length_error[0x20];
5261
5262         u8         resp_local_qp_error[0x20];
5263
5264         u8         local_operation_error[0x20];
5265
5266         u8         resp_local_protection[0x20];
5267
5268         u8         req_local_protection[0x20];
5269
5270         u8         resp_cqe_error[0x20];
5271
5272         u8         req_cqe_error[0x20];
5273
5274         u8         req_mw_binding[0x20];
5275
5276         u8         req_bad_response[0x20];
5277
5278         u8         req_remote_invalid_request[0x20];
5279
5280         u8         resp_remote_invalid_request[0x20];
5281
5282         u8         req_remote_access_errors[0x20];
5283
5284         u8         resp_remote_access_errors[0x20];
5285
5286         u8         req_remote_operation_errors[0x20];
5287
5288         u8         req_transport_retries_exceeded[0x20];
5289
5290         u8         cq_overflow[0x20];
5291
5292         u8         resp_cqe_flush_error[0x20];
5293
5294         u8         req_cqe_flush_error[0x20];
5295
5296         u8         reserved_at_620[0x20];
5297
5298         u8         roce_adp_retrans[0x20];
5299
5300         u8         roce_adp_retrans_to[0x20];
5301
5302         u8         roce_slow_restart[0x20];
5303
5304         u8         roce_slow_restart_cnps[0x20];
5305
5306         u8         roce_slow_restart_trans[0x20];
5307
5308         u8         reserved_at_6e0[0x120];
5309 };
5310
5311 struct mlx5_ifc_query_q_counter_in_bits {
5312         u8         opcode[0x10];
5313         u8         reserved_at_10[0x10];
5314
5315         u8         reserved_at_20[0x10];
5316         u8         op_mod[0x10];
5317
5318         u8         reserved_at_40[0x80];
5319
5320         u8         clear[0x1];
5321         u8         reserved_at_c1[0x1f];
5322
5323         u8         reserved_at_e0[0x18];
5324         u8         counter_set_id[0x8];
5325 };
5326
5327 struct mlx5_ifc_query_pages_out_bits {
5328         u8         status[0x8];
5329         u8         reserved_at_8[0x18];
5330
5331         u8         syndrome[0x20];
5332
5333         u8         embedded_cpu_function[0x1];
5334         u8         reserved_at_41[0xf];
5335         u8         function_id[0x10];
5336
5337         u8         num_pages[0x20];
5338 };
5339
5340 enum {
5341         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5342         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5343         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5344 };
5345
5346 struct mlx5_ifc_query_pages_in_bits {
5347         u8         opcode[0x10];
5348         u8         reserved_at_10[0x10];
5349
5350         u8         reserved_at_20[0x10];
5351         u8         op_mod[0x10];
5352
5353         u8         embedded_cpu_function[0x1];
5354         u8         reserved_at_41[0xf];
5355         u8         function_id[0x10];
5356
5357         u8         reserved_at_60[0x20];
5358 };
5359
5360 struct mlx5_ifc_query_nic_vport_context_out_bits {
5361         u8         status[0x8];
5362         u8         reserved_at_8[0x18];
5363
5364         u8         syndrome[0x20];
5365
5366         u8         reserved_at_40[0x40];
5367
5368         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5369 };
5370
5371 struct mlx5_ifc_query_nic_vport_context_in_bits {
5372         u8         opcode[0x10];
5373         u8         reserved_at_10[0x10];
5374
5375         u8         reserved_at_20[0x10];
5376         u8         op_mod[0x10];
5377
5378         u8         other_vport[0x1];
5379         u8         reserved_at_41[0xf];
5380         u8         vport_number[0x10];
5381
5382         u8         reserved_at_60[0x5];
5383         u8         allowed_list_type[0x3];
5384         u8         reserved_at_68[0x18];
5385 };
5386
5387 struct mlx5_ifc_query_mkey_out_bits {
5388         u8         status[0x8];
5389         u8         reserved_at_8[0x18];
5390
5391         u8         syndrome[0x20];
5392
5393         u8         reserved_at_40[0x40];
5394
5395         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5396
5397         u8         reserved_at_280[0x600];
5398
5399         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5400
5401         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5402 };
5403
5404 struct mlx5_ifc_query_mkey_in_bits {
5405         u8         opcode[0x10];
5406         u8         reserved_at_10[0x10];
5407
5408         u8         reserved_at_20[0x10];
5409         u8         op_mod[0x10];
5410
5411         u8         reserved_at_40[0x8];
5412         u8         mkey_index[0x18];
5413
5414         u8         pg_access[0x1];
5415         u8         reserved_at_61[0x1f];
5416 };
5417
5418 struct mlx5_ifc_query_mad_demux_out_bits {
5419         u8         status[0x8];
5420         u8         reserved_at_8[0x18];
5421
5422         u8         syndrome[0x20];
5423
5424         u8         reserved_at_40[0x40];
5425
5426         u8         mad_dumux_parameters_block[0x20];
5427 };
5428
5429 struct mlx5_ifc_query_mad_demux_in_bits {
5430         u8         opcode[0x10];
5431         u8         reserved_at_10[0x10];
5432
5433         u8         reserved_at_20[0x10];
5434         u8         op_mod[0x10];
5435
5436         u8         reserved_at_40[0x40];
5437 };
5438
5439 struct mlx5_ifc_query_l2_table_entry_out_bits {
5440         u8         status[0x8];
5441         u8         reserved_at_8[0x18];
5442
5443         u8         syndrome[0x20];
5444
5445         u8         reserved_at_40[0xa0];
5446
5447         u8         reserved_at_e0[0x13];
5448         u8         vlan_valid[0x1];
5449         u8         vlan[0xc];
5450
5451         struct mlx5_ifc_mac_address_layout_bits mac_address;
5452
5453         u8         reserved_at_140[0xc0];
5454 };
5455
5456 struct mlx5_ifc_query_l2_table_entry_in_bits {
5457         u8         opcode[0x10];
5458         u8         reserved_at_10[0x10];
5459
5460         u8         reserved_at_20[0x10];
5461         u8         op_mod[0x10];
5462
5463         u8         reserved_at_40[0x60];
5464
5465         u8         reserved_at_a0[0x8];
5466         u8         table_index[0x18];
5467
5468         u8         reserved_at_c0[0x140];
5469 };
5470
5471 struct mlx5_ifc_query_issi_out_bits {
5472         u8         status[0x8];
5473         u8         reserved_at_8[0x18];
5474
5475         u8         syndrome[0x20];
5476
5477         u8         reserved_at_40[0x10];
5478         u8         current_issi[0x10];
5479
5480         u8         reserved_at_60[0xa0];
5481
5482         u8         reserved_at_100[76][0x8];
5483         u8         supported_issi_dw0[0x20];
5484 };
5485
5486 struct mlx5_ifc_query_issi_in_bits {
5487         u8         opcode[0x10];
5488         u8         reserved_at_10[0x10];
5489
5490         u8         reserved_at_20[0x10];
5491         u8         op_mod[0x10];
5492
5493         u8         reserved_at_40[0x40];
5494 };
5495
5496 struct mlx5_ifc_set_driver_version_out_bits {
5497         u8         status[0x8];
5498         u8         reserved_0[0x18];
5499
5500         u8         syndrome[0x20];
5501         u8         reserved_1[0x40];
5502 };
5503
5504 struct mlx5_ifc_set_driver_version_in_bits {
5505         u8         opcode[0x10];
5506         u8         reserved_0[0x10];
5507
5508         u8         reserved_1[0x10];
5509         u8         op_mod[0x10];
5510
5511         u8         reserved_2[0x40];
5512         u8         driver_version[64][0x8];
5513 };
5514
5515 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5516         u8         status[0x8];
5517         u8         reserved_at_8[0x18];
5518
5519         u8         syndrome[0x20];
5520
5521         u8         reserved_at_40[0x40];
5522
5523         struct mlx5_ifc_pkey_bits pkey[];
5524 };
5525
5526 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5527         u8         opcode[0x10];
5528         u8         reserved_at_10[0x10];
5529
5530         u8         reserved_at_20[0x10];
5531         u8         op_mod[0x10];
5532
5533         u8         other_vport[0x1];
5534         u8         reserved_at_41[0xb];
5535         u8         port_num[0x4];
5536         u8         vport_number[0x10];
5537
5538         u8         reserved_at_60[0x10];
5539         u8         pkey_index[0x10];
5540 };
5541
5542 enum {
5543         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5544         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5545         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5546 };
5547
5548 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5549         u8         status[0x8];
5550         u8         reserved_at_8[0x18];
5551
5552         u8         syndrome[0x20];
5553
5554         u8         reserved_at_40[0x20];
5555
5556         u8         gids_num[0x10];
5557         u8         reserved_at_70[0x10];
5558
5559         struct mlx5_ifc_array128_auto_bits gid[];
5560 };
5561
5562 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5563         u8         opcode[0x10];
5564         u8         reserved_at_10[0x10];
5565
5566         u8         reserved_at_20[0x10];
5567         u8         op_mod[0x10];
5568
5569         u8         other_vport[0x1];
5570         u8         reserved_at_41[0xb];
5571         u8         port_num[0x4];
5572         u8         vport_number[0x10];
5573
5574         u8         reserved_at_60[0x10];
5575         u8         gid_index[0x10];
5576 };
5577
5578 struct mlx5_ifc_query_hca_vport_context_out_bits {
5579         u8         status[0x8];
5580         u8         reserved_at_8[0x18];
5581
5582         u8         syndrome[0x20];
5583
5584         u8         reserved_at_40[0x40];
5585
5586         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5587 };
5588
5589 struct mlx5_ifc_query_hca_vport_context_in_bits {
5590         u8         opcode[0x10];
5591         u8         reserved_at_10[0x10];
5592
5593         u8         reserved_at_20[0x10];
5594         u8         op_mod[0x10];
5595
5596         u8         other_vport[0x1];
5597         u8         reserved_at_41[0xb];
5598         u8         port_num[0x4];
5599         u8         vport_number[0x10];
5600
5601         u8         reserved_at_60[0x20];
5602 };
5603
5604 struct mlx5_ifc_query_hca_cap_out_bits {
5605         u8         status[0x8];
5606         u8         reserved_at_8[0x18];
5607
5608         u8         syndrome[0x20];
5609
5610         u8         reserved_at_40[0x40];
5611
5612         union mlx5_ifc_hca_cap_union_bits capability;
5613 };
5614
5615 struct mlx5_ifc_query_hca_cap_in_bits {
5616         u8         opcode[0x10];
5617         u8         reserved_at_10[0x10];
5618
5619         u8         reserved_at_20[0x10];
5620         u8         op_mod[0x10];
5621
5622         u8         other_function[0x1];
5623         u8         reserved_at_41[0xf];
5624         u8         function_id[0x10];
5625
5626         u8         reserved_at_60[0x20];
5627 };
5628
5629 struct mlx5_ifc_other_hca_cap_bits {
5630         u8         roce[0x1];
5631         u8         reserved_at_1[0x27f];
5632 };
5633
5634 struct mlx5_ifc_query_other_hca_cap_out_bits {
5635         u8         status[0x8];
5636         u8         reserved_at_8[0x18];
5637
5638         u8         syndrome[0x20];
5639
5640         u8         reserved_at_40[0x40];
5641
5642         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5643 };
5644
5645 struct mlx5_ifc_query_other_hca_cap_in_bits {
5646         u8         opcode[0x10];
5647         u8         reserved_at_10[0x10];
5648
5649         u8         reserved_at_20[0x10];
5650         u8         op_mod[0x10];
5651
5652         u8         reserved_at_40[0x10];
5653         u8         function_id[0x10];
5654
5655         u8         reserved_at_60[0x20];
5656 };
5657
5658 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5659         u8         status[0x8];
5660         u8         reserved_at_8[0x18];
5661
5662         u8         syndrome[0x20];
5663
5664         u8         reserved_at_40[0x40];
5665 };
5666
5667 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5668         u8         opcode[0x10];
5669         u8         reserved_at_10[0x10];
5670
5671         u8         reserved_at_20[0x10];
5672         u8         op_mod[0x10];
5673
5674         u8         reserved_at_40[0x10];
5675         u8         function_id[0x10];
5676         u8         field_select[0x20];
5677
5678         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5679 };
5680
5681 struct mlx5_ifc_flow_table_context_bits {
5682         u8         reformat_en[0x1];
5683         u8         decap_en[0x1];
5684         u8         sw_owner[0x1];
5685         u8         termination_table[0x1];
5686         u8         table_miss_action[0x4];
5687         u8         level[0x8];
5688         u8         reserved_at_10[0x8];
5689         u8         log_size[0x8];
5690
5691         u8         reserved_at_20[0x8];
5692         u8         table_miss_id[0x18];
5693
5694         u8         reserved_at_40[0x8];
5695         u8         lag_master_next_table_id[0x18];
5696
5697         u8         reserved_at_60[0x60];
5698
5699         u8         sw_owner_icm_root_1[0x40];
5700
5701         u8         sw_owner_icm_root_0[0x40];
5702
5703 };
5704
5705 struct mlx5_ifc_query_flow_table_out_bits {
5706         u8         status[0x8];
5707         u8         reserved_at_8[0x18];
5708
5709         u8         syndrome[0x20];
5710
5711         u8         reserved_at_40[0x80];
5712
5713         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5714 };
5715
5716 struct mlx5_ifc_query_flow_table_in_bits {
5717         u8         opcode[0x10];
5718         u8         reserved_at_10[0x10];
5719
5720         u8         reserved_at_20[0x10];
5721         u8         op_mod[0x10];
5722
5723         u8         reserved_at_40[0x40];
5724
5725         u8         table_type[0x8];
5726         u8         reserved_at_88[0x18];
5727
5728         u8         reserved_at_a0[0x8];
5729         u8         table_id[0x18];
5730
5731         u8         reserved_at_c0[0x140];
5732 };
5733
5734 struct mlx5_ifc_query_fte_out_bits {
5735         u8         status[0x8];
5736         u8         reserved_at_8[0x18];
5737
5738         u8         syndrome[0x20];
5739
5740         u8         reserved_at_40[0x1c0];
5741
5742         struct mlx5_ifc_flow_context_bits flow_context;
5743 };
5744
5745 struct mlx5_ifc_query_fte_in_bits {
5746         u8         opcode[0x10];
5747         u8         reserved_at_10[0x10];
5748
5749         u8         reserved_at_20[0x10];
5750         u8         op_mod[0x10];
5751
5752         u8         reserved_at_40[0x40];
5753
5754         u8         table_type[0x8];
5755         u8         reserved_at_88[0x18];
5756
5757         u8         reserved_at_a0[0x8];
5758         u8         table_id[0x18];
5759
5760         u8         reserved_at_c0[0x40];
5761
5762         u8         flow_index[0x20];
5763
5764         u8         reserved_at_120[0xe0];
5765 };
5766
5767 struct mlx5_ifc_match_definer_format_0_bits {
5768         u8         reserved_at_0[0x100];
5769
5770         u8         metadata_reg_c_0[0x20];
5771
5772         u8         metadata_reg_c_1[0x20];
5773
5774         u8         outer_dmac_47_16[0x20];
5775
5776         u8         outer_dmac_15_0[0x10];
5777         u8         outer_ethertype[0x10];
5778
5779         u8         reserved_at_180[0x1];
5780         u8         sx_sniffer[0x1];
5781         u8         functional_lb[0x1];
5782         u8         outer_ip_frag[0x1];
5783         u8         outer_qp_type[0x2];
5784         u8         outer_encap_type[0x2];
5785         u8         port_number[0x2];
5786         u8         outer_l3_type[0x2];
5787         u8         outer_l4_type[0x2];
5788         u8         outer_first_vlan_type[0x2];
5789         u8         outer_first_vlan_prio[0x3];
5790         u8         outer_first_vlan_cfi[0x1];
5791         u8         outer_first_vlan_vid[0xc];
5792
5793         u8         outer_l4_type_ext[0x4];
5794         u8         reserved_at_1a4[0x2];
5795         u8         outer_ipsec_layer[0x2];
5796         u8         outer_l2_type[0x2];
5797         u8         force_lb[0x1];
5798         u8         outer_l2_ok[0x1];
5799         u8         outer_l3_ok[0x1];
5800         u8         outer_l4_ok[0x1];
5801         u8         outer_second_vlan_type[0x2];
5802         u8         outer_second_vlan_prio[0x3];
5803         u8         outer_second_vlan_cfi[0x1];
5804         u8         outer_second_vlan_vid[0xc];
5805
5806         u8         outer_smac_47_16[0x20];
5807
5808         u8         outer_smac_15_0[0x10];
5809         u8         inner_ipv4_checksum_ok[0x1];
5810         u8         inner_l4_checksum_ok[0x1];
5811         u8         outer_ipv4_checksum_ok[0x1];
5812         u8         outer_l4_checksum_ok[0x1];
5813         u8         inner_l3_ok[0x1];
5814         u8         inner_l4_ok[0x1];
5815         u8         outer_l3_ok_duplicate[0x1];
5816         u8         outer_l4_ok_duplicate[0x1];
5817         u8         outer_tcp_cwr[0x1];
5818         u8         outer_tcp_ece[0x1];
5819         u8         outer_tcp_urg[0x1];
5820         u8         outer_tcp_ack[0x1];
5821         u8         outer_tcp_psh[0x1];
5822         u8         outer_tcp_rst[0x1];
5823         u8         outer_tcp_syn[0x1];
5824         u8         outer_tcp_fin[0x1];
5825 };
5826
5827 struct mlx5_ifc_match_definer_format_22_bits {
5828         u8         reserved_at_0[0x100];
5829
5830         u8         outer_ip_src_addr[0x20];
5831
5832         u8         outer_ip_dest_addr[0x20];
5833
5834         u8         outer_l4_sport[0x10];
5835         u8         outer_l4_dport[0x10];
5836
5837         u8         reserved_at_160[0x1];
5838         u8         sx_sniffer[0x1];
5839         u8         functional_lb[0x1];
5840         u8         outer_ip_frag[0x1];
5841         u8         outer_qp_type[0x2];
5842         u8         outer_encap_type[0x2];
5843         u8         port_number[0x2];
5844         u8         outer_l3_type[0x2];
5845         u8         outer_l4_type[0x2];
5846         u8         outer_first_vlan_type[0x2];
5847         u8         outer_first_vlan_prio[0x3];
5848         u8         outer_first_vlan_cfi[0x1];
5849         u8         outer_first_vlan_vid[0xc];
5850
5851         u8         metadata_reg_c_0[0x20];
5852
5853         u8         outer_dmac_47_16[0x20];
5854
5855         u8         outer_smac_47_16[0x20];
5856
5857         u8         outer_smac_15_0[0x10];
5858         u8         outer_dmac_15_0[0x10];
5859 };
5860
5861 struct mlx5_ifc_match_definer_format_23_bits {
5862         u8         reserved_at_0[0x100];
5863
5864         u8         inner_ip_src_addr[0x20];
5865
5866         u8         inner_ip_dest_addr[0x20];
5867
5868         u8         inner_l4_sport[0x10];
5869         u8         inner_l4_dport[0x10];
5870
5871         u8         reserved_at_160[0x1];
5872         u8         sx_sniffer[0x1];
5873         u8         functional_lb[0x1];
5874         u8         inner_ip_frag[0x1];
5875         u8         inner_qp_type[0x2];
5876         u8         inner_encap_type[0x2];
5877         u8         port_number[0x2];
5878         u8         inner_l3_type[0x2];
5879         u8         inner_l4_type[0x2];
5880         u8         inner_first_vlan_type[0x2];
5881         u8         inner_first_vlan_prio[0x3];
5882         u8         inner_first_vlan_cfi[0x1];
5883         u8         inner_first_vlan_vid[0xc];
5884
5885         u8         tunnel_header_0[0x20];
5886
5887         u8         inner_dmac_47_16[0x20];
5888
5889         u8         inner_smac_47_16[0x20];
5890
5891         u8         inner_smac_15_0[0x10];
5892         u8         inner_dmac_15_0[0x10];
5893 };
5894
5895 struct mlx5_ifc_match_definer_format_29_bits {
5896         u8         reserved_at_0[0xc0];
5897
5898         u8         outer_ip_dest_addr[0x80];
5899
5900         u8         outer_ip_src_addr[0x80];
5901
5902         u8         outer_l4_sport[0x10];
5903         u8         outer_l4_dport[0x10];
5904
5905         u8         reserved_at_1e0[0x20];
5906 };
5907
5908 struct mlx5_ifc_match_definer_format_30_bits {
5909         u8         reserved_at_0[0xa0];
5910
5911         u8         outer_ip_dest_addr[0x80];
5912
5913         u8         outer_ip_src_addr[0x80];
5914
5915         u8         outer_dmac_47_16[0x20];
5916
5917         u8         outer_smac_47_16[0x20];
5918
5919         u8         outer_smac_15_0[0x10];
5920         u8         outer_dmac_15_0[0x10];
5921 };
5922
5923 struct mlx5_ifc_match_definer_format_31_bits {
5924         u8         reserved_at_0[0xc0];
5925
5926         u8         inner_ip_dest_addr[0x80];
5927
5928         u8         inner_ip_src_addr[0x80];
5929
5930         u8         inner_l4_sport[0x10];
5931         u8         inner_l4_dport[0x10];
5932
5933         u8         reserved_at_1e0[0x20];
5934 };
5935
5936 struct mlx5_ifc_match_definer_format_32_bits {
5937         u8         reserved_at_0[0xa0];
5938
5939         u8         inner_ip_dest_addr[0x80];
5940
5941         u8         inner_ip_src_addr[0x80];
5942
5943         u8         inner_dmac_47_16[0x20];
5944
5945         u8         inner_smac_47_16[0x20];
5946
5947         u8         inner_smac_15_0[0x10];
5948         u8         inner_dmac_15_0[0x10];
5949 };
5950
5951 struct mlx5_ifc_match_definer_bits {
5952         u8         modify_field_select[0x40];
5953
5954         u8         reserved_at_40[0x40];
5955
5956         u8         reserved_at_80[0x10];
5957         u8         format_id[0x10];
5958
5959         u8         reserved_at_a0[0x160];
5960
5961         u8         match_mask[16][0x20];
5962 };
5963
5964 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
5965         u8         opcode[0x10];
5966         u8         uid[0x10];
5967
5968         u8         vhca_tunnel_id[0x10];
5969         u8         obj_type[0x10];
5970
5971         u8         obj_id[0x20];
5972
5973         u8         reserved_at_60[0x20];
5974 };
5975
5976 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
5977         u8         status[0x8];
5978         u8         reserved_at_8[0x18];
5979
5980         u8         syndrome[0x20];
5981
5982         u8         obj_id[0x20];
5983
5984         u8         reserved_at_60[0x20];
5985 };
5986
5987 struct mlx5_ifc_create_match_definer_in_bits {
5988         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
5989
5990         struct mlx5_ifc_match_definer_bits obj_context;
5991 };
5992
5993 struct mlx5_ifc_create_match_definer_out_bits {
5994         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
5995 };
5996
5997 enum {
5998         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5999         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6000         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6001         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6002         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6003         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6004         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6005 };
6006
6007 struct mlx5_ifc_query_flow_group_out_bits {
6008         u8         status[0x8];
6009         u8         reserved_at_8[0x18];
6010
6011         u8         syndrome[0x20];
6012
6013         u8         reserved_at_40[0xa0];
6014
6015         u8         start_flow_index[0x20];
6016
6017         u8         reserved_at_100[0x20];
6018
6019         u8         end_flow_index[0x20];
6020
6021         u8         reserved_at_140[0xa0];
6022
6023         u8         reserved_at_1e0[0x18];
6024         u8         match_criteria_enable[0x8];
6025
6026         struct mlx5_ifc_fte_match_param_bits match_criteria;
6027
6028         u8         reserved_at_1200[0xe00];
6029 };
6030
6031 struct mlx5_ifc_query_flow_group_in_bits {
6032         u8         opcode[0x10];
6033         u8         reserved_at_10[0x10];
6034
6035         u8         reserved_at_20[0x10];
6036         u8         op_mod[0x10];
6037
6038         u8         reserved_at_40[0x40];
6039
6040         u8         table_type[0x8];
6041         u8         reserved_at_88[0x18];
6042
6043         u8         reserved_at_a0[0x8];
6044         u8         table_id[0x18];
6045
6046         u8         group_id[0x20];
6047
6048         u8         reserved_at_e0[0x120];
6049 };
6050
6051 struct mlx5_ifc_query_flow_counter_out_bits {
6052         u8         status[0x8];
6053         u8         reserved_at_8[0x18];
6054
6055         u8         syndrome[0x20];
6056
6057         u8         reserved_at_40[0x40];
6058
6059         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6060 };
6061
6062 struct mlx5_ifc_query_flow_counter_in_bits {
6063         u8         opcode[0x10];
6064         u8         reserved_at_10[0x10];
6065
6066         u8         reserved_at_20[0x10];
6067         u8         op_mod[0x10];
6068
6069         u8         reserved_at_40[0x80];
6070
6071         u8         clear[0x1];
6072         u8         reserved_at_c1[0xf];
6073         u8         num_of_counters[0x10];
6074
6075         u8         flow_counter_id[0x20];
6076 };
6077
6078 struct mlx5_ifc_query_esw_vport_context_out_bits {
6079         u8         status[0x8];
6080         u8         reserved_at_8[0x18];
6081
6082         u8         syndrome[0x20];
6083
6084         u8         reserved_at_40[0x40];
6085
6086         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6087 };
6088
6089 struct mlx5_ifc_query_esw_vport_context_in_bits {
6090         u8         opcode[0x10];
6091         u8         reserved_at_10[0x10];
6092
6093         u8         reserved_at_20[0x10];
6094         u8         op_mod[0x10];
6095
6096         u8         other_vport[0x1];
6097         u8         reserved_at_41[0xf];
6098         u8         vport_number[0x10];
6099
6100         u8         reserved_at_60[0x20];
6101 };
6102
6103 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6104         u8         status[0x8];
6105         u8         reserved_at_8[0x18];
6106
6107         u8         syndrome[0x20];
6108
6109         u8         reserved_at_40[0x40];
6110 };
6111
6112 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6113         u8         reserved_at_0[0x1b];
6114         u8         fdb_to_vport_reg_c_id[0x1];
6115         u8         vport_cvlan_insert[0x1];
6116         u8         vport_svlan_insert[0x1];
6117         u8         vport_cvlan_strip[0x1];
6118         u8         vport_svlan_strip[0x1];
6119 };
6120
6121 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6122         u8         opcode[0x10];
6123         u8         reserved_at_10[0x10];
6124
6125         u8         reserved_at_20[0x10];
6126         u8         op_mod[0x10];
6127
6128         u8         other_vport[0x1];
6129         u8         reserved_at_41[0xf];
6130         u8         vport_number[0x10];
6131
6132         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6133
6134         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6135 };
6136
6137 struct mlx5_ifc_query_eq_out_bits {
6138         u8         status[0x8];
6139         u8         reserved_at_8[0x18];
6140
6141         u8         syndrome[0x20];
6142
6143         u8         reserved_at_40[0x40];
6144
6145         struct mlx5_ifc_eqc_bits eq_context_entry;
6146
6147         u8         reserved_at_280[0x40];
6148
6149         u8         event_bitmask[0x40];
6150
6151         u8         reserved_at_300[0x580];
6152
6153         u8         pas[][0x40];
6154 };
6155
6156 struct mlx5_ifc_query_eq_in_bits {
6157         u8         opcode[0x10];
6158         u8         reserved_at_10[0x10];
6159
6160         u8         reserved_at_20[0x10];
6161         u8         op_mod[0x10];
6162
6163         u8         reserved_at_40[0x18];
6164         u8         eq_number[0x8];
6165
6166         u8         reserved_at_60[0x20];
6167 };
6168
6169 struct mlx5_ifc_packet_reformat_context_in_bits {
6170         u8         reformat_type[0x8];
6171         u8         reserved_at_8[0x4];
6172         u8         reformat_param_0[0x4];
6173         u8         reserved_at_10[0x6];
6174         u8         reformat_data_size[0xa];
6175
6176         u8         reformat_param_1[0x8];
6177         u8         reserved_at_28[0x8];
6178         u8         reformat_data[2][0x8];
6179
6180         u8         more_reformat_data[][0x8];
6181 };
6182
6183 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6184         u8         status[0x8];
6185         u8         reserved_at_8[0x18];
6186
6187         u8         syndrome[0x20];
6188
6189         u8         reserved_at_40[0xa0];
6190
6191         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6192 };
6193
6194 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6195         u8         opcode[0x10];
6196         u8         reserved_at_10[0x10];
6197
6198         u8         reserved_at_20[0x10];
6199         u8         op_mod[0x10];
6200
6201         u8         packet_reformat_id[0x20];
6202
6203         u8         reserved_at_60[0xa0];
6204 };
6205
6206 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6207         u8         status[0x8];
6208         u8         reserved_at_8[0x18];
6209
6210         u8         syndrome[0x20];
6211
6212         u8         packet_reformat_id[0x20];
6213
6214         u8         reserved_at_60[0x20];
6215 };
6216
6217 enum {
6218         MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6219         MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6220         MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6221 };
6222
6223 enum mlx5_reformat_ctx_type {
6224         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6225         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6226         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6227         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6228         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6229         MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6230         MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6231 };
6232
6233 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6234         u8         opcode[0x10];
6235         u8         reserved_at_10[0x10];
6236
6237         u8         reserved_at_20[0x10];
6238         u8         op_mod[0x10];
6239
6240         u8         reserved_at_40[0xa0];
6241
6242         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6243 };
6244
6245 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6246         u8         status[0x8];
6247         u8         reserved_at_8[0x18];
6248
6249         u8         syndrome[0x20];
6250
6251         u8         reserved_at_40[0x40];
6252 };
6253
6254 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6255         u8         opcode[0x10];
6256         u8         reserved_at_10[0x10];
6257
6258         u8         reserved_20[0x10];
6259         u8         op_mod[0x10];
6260
6261         u8         packet_reformat_id[0x20];
6262
6263         u8         reserved_60[0x20];
6264 };
6265
6266 struct mlx5_ifc_set_action_in_bits {
6267         u8         action_type[0x4];
6268         u8         field[0xc];
6269         u8         reserved_at_10[0x3];
6270         u8         offset[0x5];
6271         u8         reserved_at_18[0x3];
6272         u8         length[0x5];
6273
6274         u8         data[0x20];
6275 };
6276
6277 struct mlx5_ifc_add_action_in_bits {
6278         u8         action_type[0x4];
6279         u8         field[0xc];
6280         u8         reserved_at_10[0x10];
6281
6282         u8         data[0x20];
6283 };
6284
6285 struct mlx5_ifc_copy_action_in_bits {
6286         u8         action_type[0x4];
6287         u8         src_field[0xc];
6288         u8         reserved_at_10[0x3];
6289         u8         src_offset[0x5];
6290         u8         reserved_at_18[0x3];
6291         u8         length[0x5];
6292
6293         u8         reserved_at_20[0x4];
6294         u8         dst_field[0xc];
6295         u8         reserved_at_30[0x3];
6296         u8         dst_offset[0x5];
6297         u8         reserved_at_38[0x8];
6298 };
6299
6300 union mlx5_ifc_set_add_copy_action_in_auto_bits {
6301         struct mlx5_ifc_set_action_in_bits  set_action_in;
6302         struct mlx5_ifc_add_action_in_bits  add_action_in;
6303         struct mlx5_ifc_copy_action_in_bits copy_action_in;
6304         u8         reserved_at_0[0x40];
6305 };
6306
6307 enum {
6308         MLX5_ACTION_TYPE_SET   = 0x1,
6309         MLX5_ACTION_TYPE_ADD   = 0x2,
6310         MLX5_ACTION_TYPE_COPY  = 0x3,
6311 };
6312
6313 enum {
6314         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
6315         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
6316         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
6317         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
6318         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
6319         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
6320         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
6321         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
6322         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
6323         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
6324         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
6325         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
6326         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
6327         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
6328         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
6329         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
6330         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
6331         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
6332         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
6333         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
6334         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
6335         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
6336         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
6337         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6338         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
6339         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
6340         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
6341         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
6342         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
6343         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6344         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6345         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6346         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6347         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6348         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6349         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6350         MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6351         MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6352         MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6353 };
6354
6355 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6356         u8         status[0x8];
6357         u8         reserved_at_8[0x18];
6358
6359         u8         syndrome[0x20];
6360
6361         u8         modify_header_id[0x20];
6362
6363         u8         reserved_at_60[0x20];
6364 };
6365
6366 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6367         u8         opcode[0x10];
6368         u8         reserved_at_10[0x10];
6369
6370         u8         reserved_at_20[0x10];
6371         u8         op_mod[0x10];
6372
6373         u8         reserved_at_40[0x20];
6374
6375         u8         table_type[0x8];
6376         u8         reserved_at_68[0x10];
6377         u8         num_of_actions[0x8];
6378
6379         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6380 };
6381
6382 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6383         u8         status[0x8];
6384         u8         reserved_at_8[0x18];
6385
6386         u8         syndrome[0x20];
6387
6388         u8         reserved_at_40[0x40];
6389 };
6390
6391 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6392         u8         opcode[0x10];
6393         u8         reserved_at_10[0x10];
6394
6395         u8         reserved_at_20[0x10];
6396         u8         op_mod[0x10];
6397
6398         u8         modify_header_id[0x20];
6399
6400         u8         reserved_at_60[0x20];
6401 };
6402
6403 struct mlx5_ifc_query_modify_header_context_in_bits {
6404         u8         opcode[0x10];
6405         u8         uid[0x10];
6406
6407         u8         reserved_at_20[0x10];
6408         u8         op_mod[0x10];
6409
6410         u8         modify_header_id[0x20];
6411
6412         u8         reserved_at_60[0xa0];
6413 };
6414
6415 struct mlx5_ifc_query_dct_out_bits {
6416         u8         status[0x8];
6417         u8         reserved_at_8[0x18];
6418
6419         u8         syndrome[0x20];
6420
6421         u8         reserved_at_40[0x40];
6422
6423         struct mlx5_ifc_dctc_bits dct_context_entry;
6424
6425         u8         reserved_at_280[0x180];
6426 };
6427
6428 struct mlx5_ifc_query_dct_in_bits {
6429         u8         opcode[0x10];
6430         u8         reserved_at_10[0x10];
6431
6432         u8         reserved_at_20[0x10];
6433         u8         op_mod[0x10];
6434
6435         u8         reserved_at_40[0x8];
6436         u8         dctn[0x18];
6437
6438         u8         reserved_at_60[0x20];
6439 };
6440
6441 struct mlx5_ifc_query_cq_out_bits {
6442         u8         status[0x8];
6443         u8         reserved_at_8[0x18];
6444
6445         u8         syndrome[0x20];
6446
6447         u8         reserved_at_40[0x40];
6448
6449         struct mlx5_ifc_cqc_bits cq_context;
6450
6451         u8         reserved_at_280[0x600];
6452
6453         u8         pas[][0x40];
6454 };
6455
6456 struct mlx5_ifc_query_cq_in_bits {
6457         u8         opcode[0x10];
6458         u8         reserved_at_10[0x10];
6459
6460         u8         reserved_at_20[0x10];
6461         u8         op_mod[0x10];
6462
6463         u8         reserved_at_40[0x8];
6464         u8         cqn[0x18];
6465
6466         u8         reserved_at_60[0x20];
6467 };
6468
6469 struct mlx5_ifc_query_cong_status_out_bits {
6470         u8         status[0x8];
6471         u8         reserved_at_8[0x18];
6472
6473         u8         syndrome[0x20];
6474
6475         u8         reserved_at_40[0x20];
6476
6477         u8         enable[0x1];
6478         u8         tag_enable[0x1];
6479         u8         reserved_at_62[0x1e];
6480 };
6481
6482 struct mlx5_ifc_query_cong_status_in_bits {
6483         u8         opcode[0x10];
6484         u8         reserved_at_10[0x10];
6485
6486         u8         reserved_at_20[0x10];
6487         u8         op_mod[0x10];
6488
6489         u8         reserved_at_40[0x18];
6490         u8         priority[0x4];
6491         u8         cong_protocol[0x4];
6492
6493         u8         reserved_at_60[0x20];
6494 };
6495
6496 struct mlx5_ifc_query_cong_statistics_out_bits {
6497         u8         status[0x8];
6498         u8         reserved_at_8[0x18];
6499
6500         u8         syndrome[0x20];
6501
6502         u8         reserved_at_40[0x40];
6503
6504         u8         rp_cur_flows[0x20];
6505
6506         u8         sum_flows[0x20];
6507
6508         u8         rp_cnp_ignored_high[0x20];
6509
6510         u8         rp_cnp_ignored_low[0x20];
6511
6512         u8         rp_cnp_handled_high[0x20];
6513
6514         u8         rp_cnp_handled_low[0x20];
6515
6516         u8         reserved_at_140[0x100];
6517
6518         u8         time_stamp_high[0x20];
6519
6520         u8         time_stamp_low[0x20];
6521
6522         u8         accumulators_period[0x20];
6523
6524         u8         np_ecn_marked_roce_packets_high[0x20];
6525
6526         u8         np_ecn_marked_roce_packets_low[0x20];
6527
6528         u8         np_cnp_sent_high[0x20];
6529
6530         u8         np_cnp_sent_low[0x20];
6531
6532         u8         reserved_at_320[0x560];
6533 };
6534
6535 struct mlx5_ifc_query_cong_statistics_in_bits {
6536         u8         opcode[0x10];
6537         u8         reserved_at_10[0x10];
6538
6539         u8         reserved_at_20[0x10];
6540         u8         op_mod[0x10];
6541
6542         u8         clear[0x1];
6543         u8         reserved_at_41[0x1f];
6544
6545         u8         reserved_at_60[0x20];
6546 };
6547
6548 struct mlx5_ifc_query_cong_params_out_bits {
6549         u8         status[0x8];
6550         u8         reserved_at_8[0x18];
6551
6552         u8         syndrome[0x20];
6553
6554         u8         reserved_at_40[0x40];
6555
6556         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6557 };
6558
6559 struct mlx5_ifc_query_cong_params_in_bits {
6560         u8         opcode[0x10];
6561         u8         reserved_at_10[0x10];
6562
6563         u8         reserved_at_20[0x10];
6564         u8         op_mod[0x10];
6565
6566         u8         reserved_at_40[0x1c];
6567         u8         cong_protocol[0x4];
6568
6569         u8         reserved_at_60[0x20];
6570 };
6571
6572 struct mlx5_ifc_query_adapter_out_bits {
6573         u8         status[0x8];
6574         u8         reserved_at_8[0x18];
6575
6576         u8         syndrome[0x20];
6577
6578         u8         reserved_at_40[0x40];
6579
6580         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6581 };
6582
6583 struct mlx5_ifc_query_adapter_in_bits {
6584         u8         opcode[0x10];
6585         u8         reserved_at_10[0x10];
6586
6587         u8         reserved_at_20[0x10];
6588         u8         op_mod[0x10];
6589
6590         u8         reserved_at_40[0x40];
6591 };
6592
6593 struct mlx5_ifc_qp_2rst_out_bits {
6594         u8         status[0x8];
6595         u8         reserved_at_8[0x18];
6596
6597         u8         syndrome[0x20];
6598
6599         u8         reserved_at_40[0x40];
6600 };
6601
6602 struct mlx5_ifc_qp_2rst_in_bits {
6603         u8         opcode[0x10];
6604         u8         uid[0x10];
6605
6606         u8         reserved_at_20[0x10];
6607         u8         op_mod[0x10];
6608
6609         u8         reserved_at_40[0x8];
6610         u8         qpn[0x18];
6611
6612         u8         reserved_at_60[0x20];
6613 };
6614
6615 struct mlx5_ifc_qp_2err_out_bits {
6616         u8         status[0x8];
6617         u8         reserved_at_8[0x18];
6618
6619         u8         syndrome[0x20];
6620
6621         u8         reserved_at_40[0x40];
6622 };
6623
6624 struct mlx5_ifc_qp_2err_in_bits {
6625         u8         opcode[0x10];
6626         u8         uid[0x10];
6627
6628         u8         reserved_at_20[0x10];
6629         u8         op_mod[0x10];
6630
6631         u8         reserved_at_40[0x8];
6632         u8         qpn[0x18];
6633
6634         u8         reserved_at_60[0x20];
6635 };
6636
6637 struct mlx5_ifc_page_fault_resume_out_bits {
6638         u8         status[0x8];
6639         u8         reserved_at_8[0x18];
6640
6641         u8         syndrome[0x20];
6642
6643         u8         reserved_at_40[0x40];
6644 };
6645
6646 struct mlx5_ifc_page_fault_resume_in_bits {
6647         u8         opcode[0x10];
6648         u8         reserved_at_10[0x10];
6649
6650         u8         reserved_at_20[0x10];
6651         u8         op_mod[0x10];
6652
6653         u8         error[0x1];
6654         u8         reserved_at_41[0x4];
6655         u8         page_fault_type[0x3];
6656         u8         wq_number[0x18];
6657
6658         u8         reserved_at_60[0x8];
6659         u8         token[0x18];
6660 };
6661
6662 struct mlx5_ifc_nop_out_bits {
6663         u8         status[0x8];
6664         u8         reserved_at_8[0x18];
6665
6666         u8         syndrome[0x20];
6667
6668         u8         reserved_at_40[0x40];
6669 };
6670
6671 struct mlx5_ifc_nop_in_bits {
6672         u8         opcode[0x10];
6673         u8         reserved_at_10[0x10];
6674
6675         u8         reserved_at_20[0x10];
6676         u8         op_mod[0x10];
6677
6678         u8         reserved_at_40[0x40];
6679 };
6680
6681 struct mlx5_ifc_modify_vport_state_out_bits {
6682         u8         status[0x8];
6683         u8         reserved_at_8[0x18];
6684
6685         u8         syndrome[0x20];
6686
6687         u8         reserved_at_40[0x40];
6688 };
6689
6690 struct mlx5_ifc_modify_vport_state_in_bits {
6691         u8         opcode[0x10];
6692         u8         reserved_at_10[0x10];
6693
6694         u8         reserved_at_20[0x10];
6695         u8         op_mod[0x10];
6696
6697         u8         other_vport[0x1];
6698         u8         reserved_at_41[0xf];
6699         u8         vport_number[0x10];
6700
6701         u8         reserved_at_60[0x18];
6702         u8         admin_state[0x4];
6703         u8         reserved_at_7c[0x4];
6704 };
6705
6706 struct mlx5_ifc_modify_tis_out_bits {
6707         u8         status[0x8];
6708         u8         reserved_at_8[0x18];
6709
6710         u8         syndrome[0x20];
6711
6712         u8         reserved_at_40[0x40];
6713 };
6714
6715 struct mlx5_ifc_modify_tis_bitmask_bits {
6716         u8         reserved_at_0[0x20];
6717
6718         u8         reserved_at_20[0x1d];
6719         u8         lag_tx_port_affinity[0x1];
6720         u8         strict_lag_tx_port_affinity[0x1];
6721         u8         prio[0x1];
6722 };
6723
6724 struct mlx5_ifc_modify_tis_in_bits {
6725         u8         opcode[0x10];
6726         u8         uid[0x10];
6727
6728         u8         reserved_at_20[0x10];
6729         u8         op_mod[0x10];
6730
6731         u8         reserved_at_40[0x8];
6732         u8         tisn[0x18];
6733
6734         u8         reserved_at_60[0x20];
6735
6736         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6737
6738         u8         reserved_at_c0[0x40];
6739
6740         struct mlx5_ifc_tisc_bits ctx;
6741 };
6742
6743 struct mlx5_ifc_modify_tir_bitmask_bits {
6744         u8         reserved_at_0[0x20];
6745
6746         u8         reserved_at_20[0x1b];
6747         u8         self_lb_en[0x1];
6748         u8         reserved_at_3c[0x1];
6749         u8         hash[0x1];
6750         u8         reserved_at_3e[0x1];
6751         u8         packet_merge[0x1];
6752 };
6753
6754 struct mlx5_ifc_modify_tir_out_bits {
6755         u8         status[0x8];
6756         u8         reserved_at_8[0x18];
6757
6758         u8         syndrome[0x20];
6759
6760         u8         reserved_at_40[0x40];
6761 };
6762
6763 struct mlx5_ifc_modify_tir_in_bits {
6764         u8         opcode[0x10];
6765         u8         uid[0x10];
6766
6767         u8         reserved_at_20[0x10];
6768         u8         op_mod[0x10];
6769
6770         u8         reserved_at_40[0x8];
6771         u8         tirn[0x18];
6772
6773         u8         reserved_at_60[0x20];
6774
6775         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6776
6777         u8         reserved_at_c0[0x40];
6778
6779         struct mlx5_ifc_tirc_bits ctx;
6780 };
6781
6782 struct mlx5_ifc_modify_sq_out_bits {
6783         u8         status[0x8];
6784         u8         reserved_at_8[0x18];
6785
6786         u8         syndrome[0x20];
6787
6788         u8         reserved_at_40[0x40];
6789 };
6790
6791 struct mlx5_ifc_modify_sq_in_bits {
6792         u8         opcode[0x10];
6793         u8         uid[0x10];
6794
6795         u8         reserved_at_20[0x10];
6796         u8         op_mod[0x10];
6797
6798         u8         sq_state[0x4];
6799         u8         reserved_at_44[0x4];
6800         u8         sqn[0x18];
6801
6802         u8         reserved_at_60[0x20];
6803
6804         u8         modify_bitmask[0x40];
6805
6806         u8         reserved_at_c0[0x40];
6807
6808         struct mlx5_ifc_sqc_bits ctx;
6809 };
6810
6811 struct mlx5_ifc_modify_scheduling_element_out_bits {
6812         u8         status[0x8];
6813         u8         reserved_at_8[0x18];
6814
6815         u8         syndrome[0x20];
6816
6817         u8         reserved_at_40[0x1c0];
6818 };
6819
6820 enum {
6821         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6822         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6823 };
6824
6825 struct mlx5_ifc_modify_scheduling_element_in_bits {
6826         u8         opcode[0x10];
6827         u8         reserved_at_10[0x10];
6828
6829         u8         reserved_at_20[0x10];
6830         u8         op_mod[0x10];
6831
6832         u8         scheduling_hierarchy[0x8];
6833         u8         reserved_at_48[0x18];
6834
6835         u8         scheduling_element_id[0x20];
6836
6837         u8         reserved_at_80[0x20];
6838
6839         u8         modify_bitmask[0x20];
6840
6841         u8         reserved_at_c0[0x40];
6842
6843         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6844
6845         u8         reserved_at_300[0x100];
6846 };
6847
6848 struct mlx5_ifc_modify_rqt_out_bits {
6849         u8         status[0x8];
6850         u8         reserved_at_8[0x18];
6851
6852         u8         syndrome[0x20];
6853
6854         u8         reserved_at_40[0x40];
6855 };
6856
6857 struct mlx5_ifc_rqt_bitmask_bits {
6858         u8         reserved_at_0[0x20];
6859
6860         u8         reserved_at_20[0x1f];
6861         u8         rqn_list[0x1];
6862 };
6863
6864 struct mlx5_ifc_modify_rqt_in_bits {
6865         u8         opcode[0x10];
6866         u8         uid[0x10];
6867
6868         u8         reserved_at_20[0x10];
6869         u8         op_mod[0x10];
6870
6871         u8         reserved_at_40[0x8];
6872         u8         rqtn[0x18];
6873
6874         u8         reserved_at_60[0x20];
6875
6876         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6877
6878         u8         reserved_at_c0[0x40];
6879
6880         struct mlx5_ifc_rqtc_bits ctx;
6881 };
6882
6883 struct mlx5_ifc_modify_rq_out_bits {
6884         u8         status[0x8];
6885         u8         reserved_at_8[0x18];
6886
6887         u8         syndrome[0x20];
6888
6889         u8         reserved_at_40[0x40];
6890 };
6891
6892 enum {
6893         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6894         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6895         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6896 };
6897
6898 struct mlx5_ifc_modify_rq_in_bits {
6899         u8         opcode[0x10];
6900         u8         uid[0x10];
6901
6902         u8         reserved_at_20[0x10];
6903         u8         op_mod[0x10];
6904
6905         u8         rq_state[0x4];
6906         u8         reserved_at_44[0x4];
6907         u8         rqn[0x18];
6908
6909         u8         reserved_at_60[0x20];
6910
6911         u8         modify_bitmask[0x40];
6912
6913         u8         reserved_at_c0[0x40];
6914
6915         struct mlx5_ifc_rqc_bits ctx;
6916 };
6917
6918 struct mlx5_ifc_modify_rmp_out_bits {
6919         u8         status[0x8];
6920         u8         reserved_at_8[0x18];
6921
6922         u8         syndrome[0x20];
6923
6924         u8         reserved_at_40[0x40];
6925 };
6926
6927 struct mlx5_ifc_rmp_bitmask_bits {
6928         u8         reserved_at_0[0x20];
6929
6930         u8         reserved_at_20[0x1f];
6931         u8         lwm[0x1];
6932 };
6933
6934 struct mlx5_ifc_modify_rmp_in_bits {
6935         u8         opcode[0x10];
6936         u8         uid[0x10];
6937
6938         u8         reserved_at_20[0x10];
6939         u8         op_mod[0x10];
6940
6941         u8         rmp_state[0x4];
6942         u8         reserved_at_44[0x4];
6943         u8         rmpn[0x18];
6944
6945         u8         reserved_at_60[0x20];
6946
6947         struct mlx5_ifc_rmp_bitmask_bits bitmask;
6948
6949         u8         reserved_at_c0[0x40];
6950
6951         struct mlx5_ifc_rmpc_bits ctx;
6952 };
6953
6954 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6955         u8         status[0x8];
6956         u8         reserved_at_8[0x18];
6957
6958         u8         syndrome[0x20];
6959
6960         u8         reserved_at_40[0x40];
6961 };
6962
6963 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6964         u8         reserved_at_0[0x12];
6965         u8         affiliation[0x1];
6966         u8         reserved_at_13[0x1];
6967         u8         disable_uc_local_lb[0x1];
6968         u8         disable_mc_local_lb[0x1];
6969         u8         node_guid[0x1];
6970         u8         port_guid[0x1];
6971         u8         min_inline[0x1];
6972         u8         mtu[0x1];
6973         u8         change_event[0x1];
6974         u8         promisc[0x1];
6975         u8         permanent_address[0x1];
6976         u8         addresses_list[0x1];
6977         u8         roce_en[0x1];
6978         u8         reserved_at_1f[0x1];
6979 };
6980
6981 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6982         u8         opcode[0x10];
6983         u8         reserved_at_10[0x10];
6984
6985         u8         reserved_at_20[0x10];
6986         u8         op_mod[0x10];
6987
6988         u8         other_vport[0x1];
6989         u8         reserved_at_41[0xf];
6990         u8         vport_number[0x10];
6991
6992         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6993
6994         u8         reserved_at_80[0x780];
6995
6996         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6997 };
6998
6999 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7000         u8         status[0x8];
7001         u8         reserved_at_8[0x18];
7002
7003         u8         syndrome[0x20];
7004
7005         u8         reserved_at_40[0x40];
7006 };
7007
7008 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7009         u8         opcode[0x10];
7010         u8         reserved_at_10[0x10];
7011
7012         u8         reserved_at_20[0x10];
7013         u8         op_mod[0x10];
7014
7015         u8         other_vport[0x1];
7016         u8         reserved_at_41[0xb];
7017         u8         port_num[0x4];
7018         u8         vport_number[0x10];
7019
7020         u8         reserved_at_60[0x20];
7021
7022         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7023 };
7024
7025 struct mlx5_ifc_modify_cq_out_bits {
7026         u8         status[0x8];
7027         u8         reserved_at_8[0x18];
7028
7029         u8         syndrome[0x20];
7030
7031         u8         reserved_at_40[0x40];
7032 };
7033
7034 enum {
7035         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7036         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7037 };
7038
7039 struct mlx5_ifc_modify_cq_in_bits {
7040         u8         opcode[0x10];
7041         u8         uid[0x10];
7042
7043         u8         reserved_at_20[0x10];
7044         u8         op_mod[0x10];
7045
7046         u8         reserved_at_40[0x8];
7047         u8         cqn[0x18];
7048
7049         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7050
7051         struct mlx5_ifc_cqc_bits cq_context;
7052
7053         u8         reserved_at_280[0x60];
7054
7055         u8         cq_umem_valid[0x1];
7056         u8         reserved_at_2e1[0x1f];
7057
7058         u8         reserved_at_300[0x580];
7059
7060         u8         pas[][0x40];
7061 };
7062
7063 struct mlx5_ifc_modify_cong_status_out_bits {
7064         u8         status[0x8];
7065         u8         reserved_at_8[0x18];
7066
7067         u8         syndrome[0x20];
7068
7069         u8         reserved_at_40[0x40];
7070 };
7071
7072 struct mlx5_ifc_modify_cong_status_in_bits {
7073         u8         opcode[0x10];
7074         u8         reserved_at_10[0x10];
7075
7076         u8         reserved_at_20[0x10];
7077         u8         op_mod[0x10];
7078
7079         u8         reserved_at_40[0x18];
7080         u8         priority[0x4];
7081         u8         cong_protocol[0x4];
7082
7083         u8         enable[0x1];
7084         u8         tag_enable[0x1];
7085         u8         reserved_at_62[0x1e];
7086 };
7087
7088 struct mlx5_ifc_modify_cong_params_out_bits {
7089         u8         status[0x8];
7090         u8         reserved_at_8[0x18];
7091
7092         u8         syndrome[0x20];
7093
7094         u8         reserved_at_40[0x40];
7095 };
7096
7097 struct mlx5_ifc_modify_cong_params_in_bits {
7098         u8         opcode[0x10];
7099         u8         reserved_at_10[0x10];
7100
7101         u8         reserved_at_20[0x10];
7102         u8         op_mod[0x10];
7103
7104         u8         reserved_at_40[0x1c];
7105         u8         cong_protocol[0x4];
7106
7107         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7108
7109         u8         reserved_at_80[0x80];
7110
7111         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7112 };
7113
7114 struct mlx5_ifc_manage_pages_out_bits {
7115         u8         status[0x8];
7116         u8         reserved_at_8[0x18];
7117
7118         u8         syndrome[0x20];
7119
7120         u8         output_num_entries[0x20];
7121
7122         u8         reserved_at_60[0x20];
7123
7124         u8         pas[][0x40];
7125 };
7126
7127 enum {
7128         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7129         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7130         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7131 };
7132
7133 struct mlx5_ifc_manage_pages_in_bits {
7134         u8         opcode[0x10];
7135         u8         reserved_at_10[0x10];
7136
7137         u8         reserved_at_20[0x10];
7138         u8         op_mod[0x10];
7139
7140         u8         embedded_cpu_function[0x1];
7141         u8         reserved_at_41[0xf];
7142         u8         function_id[0x10];
7143
7144         u8         input_num_entries[0x20];
7145
7146         u8         pas[][0x40];
7147 };
7148
7149 struct mlx5_ifc_mad_ifc_out_bits {
7150         u8         status[0x8];
7151         u8         reserved_at_8[0x18];
7152
7153         u8         syndrome[0x20];
7154
7155         u8         reserved_at_40[0x40];
7156
7157         u8         response_mad_packet[256][0x8];
7158 };
7159
7160 struct mlx5_ifc_mad_ifc_in_bits {
7161         u8         opcode[0x10];
7162         u8         reserved_at_10[0x10];
7163
7164         u8         reserved_at_20[0x10];
7165         u8         op_mod[0x10];
7166
7167         u8         remote_lid[0x10];
7168         u8         reserved_at_50[0x8];
7169         u8         port[0x8];
7170
7171         u8         reserved_at_60[0x20];
7172
7173         u8         mad[256][0x8];
7174 };
7175
7176 struct mlx5_ifc_init_hca_out_bits {
7177         u8         status[0x8];
7178         u8         reserved_at_8[0x18];
7179
7180         u8         syndrome[0x20];
7181
7182         u8         reserved_at_40[0x40];
7183 };
7184
7185 struct mlx5_ifc_init_hca_in_bits {
7186         u8         opcode[0x10];
7187         u8         reserved_at_10[0x10];
7188
7189         u8         reserved_at_20[0x10];
7190         u8         op_mod[0x10];
7191
7192         u8         reserved_at_40[0x40];
7193         u8         sw_owner_id[4][0x20];
7194 };
7195
7196 struct mlx5_ifc_init2rtr_qp_out_bits {
7197         u8         status[0x8];
7198         u8         reserved_at_8[0x18];
7199
7200         u8         syndrome[0x20];
7201
7202         u8         reserved_at_40[0x20];
7203         u8         ece[0x20];
7204 };
7205
7206 struct mlx5_ifc_init2rtr_qp_in_bits {
7207         u8         opcode[0x10];
7208         u8         uid[0x10];
7209
7210         u8         reserved_at_20[0x10];
7211         u8         op_mod[0x10];
7212
7213         u8         reserved_at_40[0x8];
7214         u8         qpn[0x18];
7215
7216         u8         reserved_at_60[0x20];
7217
7218         u8         opt_param_mask[0x20];
7219
7220         u8         ece[0x20];
7221
7222         struct mlx5_ifc_qpc_bits qpc;
7223
7224         u8         reserved_at_800[0x80];
7225 };
7226
7227 struct mlx5_ifc_init2init_qp_out_bits {
7228         u8         status[0x8];
7229         u8         reserved_at_8[0x18];
7230
7231         u8         syndrome[0x20];
7232
7233         u8         reserved_at_40[0x20];
7234         u8         ece[0x20];
7235 };
7236
7237 struct mlx5_ifc_init2init_qp_in_bits {
7238         u8         opcode[0x10];
7239         u8         uid[0x10];
7240
7241         u8         reserved_at_20[0x10];
7242         u8         op_mod[0x10];
7243
7244         u8         reserved_at_40[0x8];
7245         u8         qpn[0x18];
7246
7247         u8         reserved_at_60[0x20];
7248
7249         u8         opt_param_mask[0x20];
7250
7251         u8         ece[0x20];
7252
7253         struct mlx5_ifc_qpc_bits qpc;
7254
7255         u8         reserved_at_800[0x80];
7256 };
7257
7258 struct mlx5_ifc_get_dropped_packet_log_out_bits {
7259         u8         status[0x8];
7260         u8         reserved_at_8[0x18];
7261
7262         u8         syndrome[0x20];
7263
7264         u8         reserved_at_40[0x40];
7265
7266         u8         packet_headers_log[128][0x8];
7267
7268         u8         packet_syndrome[64][0x8];
7269 };
7270
7271 struct mlx5_ifc_get_dropped_packet_log_in_bits {
7272         u8         opcode[0x10];
7273         u8         reserved_at_10[0x10];
7274
7275         u8         reserved_at_20[0x10];
7276         u8         op_mod[0x10];
7277
7278         u8         reserved_at_40[0x40];
7279 };
7280
7281 struct mlx5_ifc_gen_eqe_in_bits {
7282         u8         opcode[0x10];
7283         u8         reserved_at_10[0x10];
7284
7285         u8         reserved_at_20[0x10];
7286         u8         op_mod[0x10];
7287
7288         u8         reserved_at_40[0x18];
7289         u8         eq_number[0x8];
7290
7291         u8         reserved_at_60[0x20];
7292
7293         u8         eqe[64][0x8];
7294 };
7295
7296 struct mlx5_ifc_gen_eq_out_bits {
7297         u8         status[0x8];
7298         u8         reserved_at_8[0x18];
7299
7300         u8         syndrome[0x20];
7301
7302         u8         reserved_at_40[0x40];
7303 };
7304
7305 struct mlx5_ifc_enable_hca_out_bits {
7306         u8         status[0x8];
7307         u8         reserved_at_8[0x18];
7308
7309         u8         syndrome[0x20];
7310
7311         u8         reserved_at_40[0x20];
7312 };
7313
7314 struct mlx5_ifc_enable_hca_in_bits {
7315         u8         opcode[0x10];
7316         u8         reserved_at_10[0x10];
7317
7318         u8         reserved_at_20[0x10];
7319         u8         op_mod[0x10];
7320
7321         u8         embedded_cpu_function[0x1];
7322         u8         reserved_at_41[0xf];
7323         u8         function_id[0x10];
7324
7325         u8         reserved_at_60[0x20];
7326 };
7327
7328 struct mlx5_ifc_drain_dct_out_bits {
7329         u8         status[0x8];
7330         u8         reserved_at_8[0x18];
7331
7332         u8         syndrome[0x20];
7333
7334         u8         reserved_at_40[0x40];
7335 };
7336
7337 struct mlx5_ifc_drain_dct_in_bits {
7338         u8         opcode[0x10];
7339         u8         uid[0x10];
7340
7341         u8         reserved_at_20[0x10];
7342         u8         op_mod[0x10];
7343
7344         u8         reserved_at_40[0x8];
7345         u8         dctn[0x18];
7346
7347         u8         reserved_at_60[0x20];
7348 };
7349
7350 struct mlx5_ifc_disable_hca_out_bits {
7351         u8         status[0x8];
7352         u8         reserved_at_8[0x18];
7353
7354         u8         syndrome[0x20];
7355
7356         u8         reserved_at_40[0x20];
7357 };
7358
7359 struct mlx5_ifc_disable_hca_in_bits {
7360         u8         opcode[0x10];
7361         u8         reserved_at_10[0x10];
7362
7363         u8         reserved_at_20[0x10];
7364         u8         op_mod[0x10];
7365
7366         u8         embedded_cpu_function[0x1];
7367         u8         reserved_at_41[0xf];
7368         u8         function_id[0x10];
7369
7370         u8         reserved_at_60[0x20];
7371 };
7372
7373 struct mlx5_ifc_detach_from_mcg_out_bits {
7374         u8         status[0x8];
7375         u8         reserved_at_8[0x18];
7376
7377         u8         syndrome[0x20];
7378
7379         u8         reserved_at_40[0x40];
7380 };
7381
7382 struct mlx5_ifc_detach_from_mcg_in_bits {
7383         u8         opcode[0x10];
7384         u8         uid[0x10];
7385
7386         u8         reserved_at_20[0x10];
7387         u8         op_mod[0x10];
7388
7389         u8         reserved_at_40[0x8];
7390         u8         qpn[0x18];
7391
7392         u8         reserved_at_60[0x20];
7393
7394         u8         multicast_gid[16][0x8];
7395 };
7396
7397 struct mlx5_ifc_destroy_xrq_out_bits {
7398         u8         status[0x8];
7399         u8         reserved_at_8[0x18];
7400
7401         u8         syndrome[0x20];
7402
7403         u8         reserved_at_40[0x40];
7404 };
7405
7406 struct mlx5_ifc_destroy_xrq_in_bits {
7407         u8         opcode[0x10];
7408         u8         uid[0x10];
7409
7410         u8         reserved_at_20[0x10];
7411         u8         op_mod[0x10];
7412
7413         u8         reserved_at_40[0x8];
7414         u8         xrqn[0x18];
7415
7416         u8         reserved_at_60[0x20];
7417 };
7418
7419 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7420         u8         status[0x8];
7421         u8         reserved_at_8[0x18];
7422
7423         u8         syndrome[0x20];
7424
7425         u8         reserved_at_40[0x40];
7426 };
7427
7428 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7429         u8         opcode[0x10];
7430         u8         uid[0x10];
7431
7432         u8         reserved_at_20[0x10];
7433         u8         op_mod[0x10];
7434
7435         u8         reserved_at_40[0x8];
7436         u8         xrc_srqn[0x18];
7437
7438         u8         reserved_at_60[0x20];
7439 };
7440
7441 struct mlx5_ifc_destroy_tis_out_bits {
7442         u8         status[0x8];
7443         u8         reserved_at_8[0x18];
7444
7445         u8         syndrome[0x20];
7446
7447         u8         reserved_at_40[0x40];
7448 };
7449
7450 struct mlx5_ifc_destroy_tis_in_bits {
7451         u8         opcode[0x10];
7452         u8         uid[0x10];
7453
7454         u8         reserved_at_20[0x10];
7455         u8         op_mod[0x10];
7456
7457         u8         reserved_at_40[0x8];
7458         u8         tisn[0x18];
7459
7460         u8         reserved_at_60[0x20];
7461 };
7462
7463 struct mlx5_ifc_destroy_tir_out_bits {
7464         u8         status[0x8];
7465         u8         reserved_at_8[0x18];
7466
7467         u8         syndrome[0x20];
7468
7469         u8         reserved_at_40[0x40];
7470 };
7471
7472 struct mlx5_ifc_destroy_tir_in_bits {
7473         u8         opcode[0x10];
7474         u8         uid[0x10];
7475
7476         u8         reserved_at_20[0x10];
7477         u8         op_mod[0x10];
7478
7479         u8         reserved_at_40[0x8];
7480         u8         tirn[0x18];
7481
7482         u8         reserved_at_60[0x20];
7483 };
7484
7485 struct mlx5_ifc_destroy_srq_out_bits {
7486         u8         status[0x8];
7487         u8         reserved_at_8[0x18];
7488
7489         u8         syndrome[0x20];
7490
7491         u8         reserved_at_40[0x40];
7492 };
7493
7494 struct mlx5_ifc_destroy_srq_in_bits {
7495         u8         opcode[0x10];
7496         u8         uid[0x10];
7497
7498         u8         reserved_at_20[0x10];
7499         u8         op_mod[0x10];
7500
7501         u8         reserved_at_40[0x8];
7502         u8         srqn[0x18];
7503
7504         u8         reserved_at_60[0x20];
7505 };
7506
7507 struct mlx5_ifc_destroy_sq_out_bits {
7508         u8         status[0x8];
7509         u8         reserved_at_8[0x18];
7510
7511         u8         syndrome[0x20];
7512
7513         u8         reserved_at_40[0x40];
7514 };
7515
7516 struct mlx5_ifc_destroy_sq_in_bits {
7517         u8         opcode[0x10];
7518         u8         uid[0x10];
7519
7520         u8         reserved_at_20[0x10];
7521         u8         op_mod[0x10];
7522
7523         u8         reserved_at_40[0x8];
7524         u8         sqn[0x18];
7525
7526         u8         reserved_at_60[0x20];
7527 };
7528
7529 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7530         u8         status[0x8];
7531         u8         reserved_at_8[0x18];
7532
7533         u8         syndrome[0x20];
7534
7535         u8         reserved_at_40[0x1c0];
7536 };
7537
7538 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7539         u8         opcode[0x10];
7540         u8         reserved_at_10[0x10];
7541
7542         u8         reserved_at_20[0x10];
7543         u8         op_mod[0x10];
7544
7545         u8         scheduling_hierarchy[0x8];
7546         u8         reserved_at_48[0x18];
7547
7548         u8         scheduling_element_id[0x20];
7549
7550         u8         reserved_at_80[0x180];
7551 };
7552
7553 struct mlx5_ifc_destroy_rqt_out_bits {
7554         u8         status[0x8];
7555         u8         reserved_at_8[0x18];
7556
7557         u8         syndrome[0x20];
7558
7559         u8         reserved_at_40[0x40];
7560 };
7561
7562 struct mlx5_ifc_destroy_rqt_in_bits {
7563         u8         opcode[0x10];
7564         u8         uid[0x10];
7565
7566         u8         reserved_at_20[0x10];
7567         u8         op_mod[0x10];
7568
7569         u8         reserved_at_40[0x8];
7570         u8         rqtn[0x18];
7571
7572         u8         reserved_at_60[0x20];
7573 };
7574
7575 struct mlx5_ifc_destroy_rq_out_bits {
7576         u8         status[0x8];
7577         u8         reserved_at_8[0x18];
7578
7579         u8         syndrome[0x20];
7580
7581         u8         reserved_at_40[0x40];
7582 };
7583
7584 struct mlx5_ifc_destroy_rq_in_bits {
7585         u8         opcode[0x10];
7586         u8         uid[0x10];
7587
7588         u8         reserved_at_20[0x10];
7589         u8         op_mod[0x10];
7590
7591         u8         reserved_at_40[0x8];
7592         u8         rqn[0x18];
7593
7594         u8         reserved_at_60[0x20];
7595 };
7596
7597 struct mlx5_ifc_set_delay_drop_params_in_bits {
7598         u8         opcode[0x10];
7599         u8         reserved_at_10[0x10];
7600
7601         u8         reserved_at_20[0x10];
7602         u8         op_mod[0x10];
7603
7604         u8         reserved_at_40[0x20];
7605
7606         u8         reserved_at_60[0x10];
7607         u8         delay_drop_timeout[0x10];
7608 };
7609
7610 struct mlx5_ifc_set_delay_drop_params_out_bits {
7611         u8         status[0x8];
7612         u8         reserved_at_8[0x18];
7613
7614         u8         syndrome[0x20];
7615
7616         u8         reserved_at_40[0x40];
7617 };
7618
7619 struct mlx5_ifc_destroy_rmp_out_bits {
7620         u8         status[0x8];
7621         u8         reserved_at_8[0x18];
7622
7623         u8         syndrome[0x20];
7624
7625         u8         reserved_at_40[0x40];
7626 };
7627
7628 struct mlx5_ifc_destroy_rmp_in_bits {
7629         u8         opcode[0x10];
7630         u8         uid[0x10];
7631
7632         u8         reserved_at_20[0x10];
7633         u8         op_mod[0x10];
7634
7635         u8         reserved_at_40[0x8];
7636         u8         rmpn[0x18];
7637
7638         u8         reserved_at_60[0x20];
7639 };
7640
7641 struct mlx5_ifc_destroy_qp_out_bits {
7642         u8         status[0x8];
7643         u8         reserved_at_8[0x18];
7644
7645         u8         syndrome[0x20];
7646
7647         u8         reserved_at_40[0x40];
7648 };
7649
7650 struct mlx5_ifc_destroy_qp_in_bits {
7651         u8         opcode[0x10];
7652         u8         uid[0x10];
7653
7654         u8         reserved_at_20[0x10];
7655         u8         op_mod[0x10];
7656
7657         u8         reserved_at_40[0x8];
7658         u8         qpn[0x18];
7659
7660         u8         reserved_at_60[0x20];
7661 };
7662
7663 struct mlx5_ifc_destroy_psv_out_bits {
7664         u8         status[0x8];
7665         u8         reserved_at_8[0x18];
7666
7667         u8         syndrome[0x20];
7668
7669         u8         reserved_at_40[0x40];
7670 };
7671
7672 struct mlx5_ifc_destroy_psv_in_bits {
7673         u8         opcode[0x10];
7674         u8         reserved_at_10[0x10];
7675
7676         u8         reserved_at_20[0x10];
7677         u8         op_mod[0x10];
7678
7679         u8         reserved_at_40[0x8];
7680         u8         psvn[0x18];
7681
7682         u8         reserved_at_60[0x20];
7683 };
7684
7685 struct mlx5_ifc_destroy_mkey_out_bits {
7686         u8         status[0x8];
7687         u8         reserved_at_8[0x18];
7688
7689         u8         syndrome[0x20];
7690
7691         u8         reserved_at_40[0x40];
7692 };
7693
7694 struct mlx5_ifc_destroy_mkey_in_bits {
7695         u8         opcode[0x10];
7696         u8         uid[0x10];
7697
7698         u8         reserved_at_20[0x10];
7699         u8         op_mod[0x10];
7700
7701         u8         reserved_at_40[0x8];
7702         u8         mkey_index[0x18];
7703
7704         u8         reserved_at_60[0x20];
7705 };
7706
7707 struct mlx5_ifc_destroy_flow_table_out_bits {
7708         u8         status[0x8];
7709         u8         reserved_at_8[0x18];
7710
7711         u8         syndrome[0x20];
7712
7713         u8         reserved_at_40[0x40];
7714 };
7715
7716 struct mlx5_ifc_destroy_flow_table_in_bits {
7717         u8         opcode[0x10];
7718         u8         reserved_at_10[0x10];
7719
7720         u8         reserved_at_20[0x10];
7721         u8         op_mod[0x10];
7722
7723         u8         other_vport[0x1];
7724         u8         reserved_at_41[0xf];
7725         u8         vport_number[0x10];
7726
7727         u8         reserved_at_60[0x20];
7728
7729         u8         table_type[0x8];
7730         u8         reserved_at_88[0x18];
7731
7732         u8         reserved_at_a0[0x8];
7733         u8         table_id[0x18];
7734
7735         u8         reserved_at_c0[0x140];
7736 };
7737
7738 struct mlx5_ifc_destroy_flow_group_out_bits {
7739         u8         status[0x8];
7740         u8         reserved_at_8[0x18];
7741
7742         u8         syndrome[0x20];
7743
7744         u8         reserved_at_40[0x40];
7745 };
7746
7747 struct mlx5_ifc_destroy_flow_group_in_bits {
7748         u8         opcode[0x10];
7749         u8         reserved_at_10[0x10];
7750
7751         u8         reserved_at_20[0x10];
7752         u8         op_mod[0x10];
7753
7754         u8         other_vport[0x1];
7755         u8         reserved_at_41[0xf];
7756         u8         vport_number[0x10];
7757
7758         u8         reserved_at_60[0x20];
7759
7760         u8         table_type[0x8];
7761         u8         reserved_at_88[0x18];
7762
7763         u8         reserved_at_a0[0x8];
7764         u8         table_id[0x18];
7765
7766         u8         group_id[0x20];
7767
7768         u8         reserved_at_e0[0x120];
7769 };
7770
7771 struct mlx5_ifc_destroy_eq_out_bits {
7772         u8         status[0x8];
7773         u8         reserved_at_8[0x18];
7774
7775         u8         syndrome[0x20];
7776
7777         u8         reserved_at_40[0x40];
7778 };
7779
7780 struct mlx5_ifc_destroy_eq_in_bits {
7781         u8         opcode[0x10];
7782         u8         reserved_at_10[0x10];
7783
7784         u8         reserved_at_20[0x10];
7785         u8         op_mod[0x10];
7786
7787         u8         reserved_at_40[0x18];
7788         u8         eq_number[0x8];
7789
7790         u8         reserved_at_60[0x20];
7791 };
7792
7793 struct mlx5_ifc_destroy_dct_out_bits {
7794         u8         status[0x8];
7795         u8         reserved_at_8[0x18];
7796
7797         u8         syndrome[0x20];
7798
7799         u8         reserved_at_40[0x40];
7800 };
7801
7802 struct mlx5_ifc_destroy_dct_in_bits {
7803         u8         opcode[0x10];
7804         u8         uid[0x10];
7805
7806         u8         reserved_at_20[0x10];
7807         u8         op_mod[0x10];
7808
7809         u8         reserved_at_40[0x8];
7810         u8         dctn[0x18];
7811
7812         u8         reserved_at_60[0x20];
7813 };
7814
7815 struct mlx5_ifc_destroy_cq_out_bits {
7816         u8         status[0x8];
7817         u8         reserved_at_8[0x18];
7818
7819         u8         syndrome[0x20];
7820
7821         u8         reserved_at_40[0x40];
7822 };
7823
7824 struct mlx5_ifc_destroy_cq_in_bits {
7825         u8         opcode[0x10];
7826         u8         uid[0x10];
7827
7828         u8         reserved_at_20[0x10];
7829         u8         op_mod[0x10];
7830
7831         u8         reserved_at_40[0x8];
7832         u8         cqn[0x18];
7833
7834         u8         reserved_at_60[0x20];
7835 };
7836
7837 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7838         u8         status[0x8];
7839         u8         reserved_at_8[0x18];
7840
7841         u8         syndrome[0x20];
7842
7843         u8         reserved_at_40[0x40];
7844 };
7845
7846 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7847         u8         opcode[0x10];
7848         u8         reserved_at_10[0x10];
7849
7850         u8         reserved_at_20[0x10];
7851         u8         op_mod[0x10];
7852
7853         u8         reserved_at_40[0x20];
7854
7855         u8         reserved_at_60[0x10];
7856         u8         vxlan_udp_port[0x10];
7857 };
7858
7859 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7860         u8         status[0x8];
7861         u8         reserved_at_8[0x18];
7862
7863         u8         syndrome[0x20];
7864
7865         u8         reserved_at_40[0x40];
7866 };
7867
7868 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7869         u8         opcode[0x10];
7870         u8         reserved_at_10[0x10];
7871
7872         u8         reserved_at_20[0x10];
7873         u8         op_mod[0x10];
7874
7875         u8         reserved_at_40[0x60];
7876
7877         u8         reserved_at_a0[0x8];
7878         u8         table_index[0x18];
7879
7880         u8         reserved_at_c0[0x140];
7881 };
7882
7883 struct mlx5_ifc_delete_fte_out_bits {
7884         u8         status[0x8];
7885         u8         reserved_at_8[0x18];
7886
7887         u8         syndrome[0x20];
7888
7889         u8         reserved_at_40[0x40];
7890 };
7891
7892 struct mlx5_ifc_delete_fte_in_bits {
7893         u8         opcode[0x10];
7894         u8         reserved_at_10[0x10];
7895
7896         u8         reserved_at_20[0x10];
7897         u8         op_mod[0x10];
7898
7899         u8         other_vport[0x1];
7900         u8         reserved_at_41[0xf];
7901         u8         vport_number[0x10];
7902
7903         u8         reserved_at_60[0x20];
7904
7905         u8         table_type[0x8];
7906         u8         reserved_at_88[0x18];
7907
7908         u8         reserved_at_a0[0x8];
7909         u8         table_id[0x18];
7910
7911         u8         reserved_at_c0[0x40];
7912
7913         u8         flow_index[0x20];
7914
7915         u8         reserved_at_120[0xe0];
7916 };
7917
7918 struct mlx5_ifc_dealloc_xrcd_out_bits {
7919         u8         status[0x8];
7920         u8         reserved_at_8[0x18];
7921
7922         u8         syndrome[0x20];
7923
7924         u8         reserved_at_40[0x40];
7925 };
7926
7927 struct mlx5_ifc_dealloc_xrcd_in_bits {
7928         u8         opcode[0x10];
7929         u8         uid[0x10];
7930
7931         u8         reserved_at_20[0x10];
7932         u8         op_mod[0x10];
7933
7934         u8         reserved_at_40[0x8];
7935         u8         xrcd[0x18];
7936
7937         u8         reserved_at_60[0x20];
7938 };
7939
7940 struct mlx5_ifc_dealloc_uar_out_bits {
7941         u8         status[0x8];
7942         u8         reserved_at_8[0x18];
7943
7944         u8         syndrome[0x20];
7945
7946         u8         reserved_at_40[0x40];
7947 };
7948
7949 struct mlx5_ifc_dealloc_uar_in_bits {
7950         u8         opcode[0x10];
7951         u8         uid[0x10];
7952
7953         u8         reserved_at_20[0x10];
7954         u8         op_mod[0x10];
7955
7956         u8         reserved_at_40[0x8];
7957         u8         uar[0x18];
7958
7959         u8         reserved_at_60[0x20];
7960 };
7961
7962 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7963         u8         status[0x8];
7964         u8         reserved_at_8[0x18];
7965
7966         u8         syndrome[0x20];
7967
7968         u8         reserved_at_40[0x40];
7969 };
7970
7971 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7972         u8         opcode[0x10];
7973         u8         uid[0x10];
7974
7975         u8         reserved_at_20[0x10];
7976         u8         op_mod[0x10];
7977
7978         u8         reserved_at_40[0x8];
7979         u8         transport_domain[0x18];
7980
7981         u8         reserved_at_60[0x20];
7982 };
7983
7984 struct mlx5_ifc_dealloc_q_counter_out_bits {
7985         u8         status[0x8];
7986         u8         reserved_at_8[0x18];
7987
7988         u8         syndrome[0x20];
7989
7990         u8         reserved_at_40[0x40];
7991 };
7992
7993 struct mlx5_ifc_dealloc_q_counter_in_bits {
7994         u8         opcode[0x10];
7995         u8         reserved_at_10[0x10];
7996
7997         u8         reserved_at_20[0x10];
7998         u8         op_mod[0x10];
7999
8000         u8         reserved_at_40[0x18];
8001         u8         counter_set_id[0x8];
8002
8003         u8         reserved_at_60[0x20];
8004 };
8005
8006 struct mlx5_ifc_dealloc_pd_out_bits {
8007         u8         status[0x8];
8008         u8         reserved_at_8[0x18];
8009
8010         u8         syndrome[0x20];
8011
8012         u8         reserved_at_40[0x40];
8013 };
8014
8015 struct mlx5_ifc_dealloc_pd_in_bits {
8016         u8         opcode[0x10];
8017         u8         uid[0x10];
8018
8019         u8         reserved_at_20[0x10];
8020         u8         op_mod[0x10];
8021
8022         u8         reserved_at_40[0x8];
8023         u8         pd[0x18];
8024
8025         u8         reserved_at_60[0x20];
8026 };
8027
8028 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8029         u8         status[0x8];
8030         u8         reserved_at_8[0x18];
8031
8032         u8         syndrome[0x20];
8033
8034         u8         reserved_at_40[0x40];
8035 };
8036
8037 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8038         u8         opcode[0x10];
8039         u8         reserved_at_10[0x10];
8040
8041         u8         reserved_at_20[0x10];
8042         u8         op_mod[0x10];
8043
8044         u8         flow_counter_id[0x20];
8045
8046         u8         reserved_at_60[0x20];
8047 };
8048
8049 struct mlx5_ifc_create_xrq_out_bits {
8050         u8         status[0x8];
8051         u8         reserved_at_8[0x18];
8052
8053         u8         syndrome[0x20];
8054
8055         u8         reserved_at_40[0x8];
8056         u8         xrqn[0x18];
8057
8058         u8         reserved_at_60[0x20];
8059 };
8060
8061 struct mlx5_ifc_create_xrq_in_bits {
8062         u8         opcode[0x10];
8063         u8         uid[0x10];
8064
8065         u8         reserved_at_20[0x10];
8066         u8         op_mod[0x10];
8067
8068         u8         reserved_at_40[0x40];
8069
8070         struct mlx5_ifc_xrqc_bits xrq_context;
8071 };
8072
8073 struct mlx5_ifc_create_xrc_srq_out_bits {
8074         u8         status[0x8];
8075         u8         reserved_at_8[0x18];
8076
8077         u8         syndrome[0x20];
8078
8079         u8         reserved_at_40[0x8];
8080         u8         xrc_srqn[0x18];
8081
8082         u8         reserved_at_60[0x20];
8083 };
8084
8085 struct mlx5_ifc_create_xrc_srq_in_bits {
8086         u8         opcode[0x10];
8087         u8         uid[0x10];
8088
8089         u8         reserved_at_20[0x10];
8090         u8         op_mod[0x10];
8091
8092         u8         reserved_at_40[0x40];
8093
8094         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8095
8096         u8         reserved_at_280[0x60];
8097
8098         u8         xrc_srq_umem_valid[0x1];
8099         u8         reserved_at_2e1[0x1f];
8100
8101         u8         reserved_at_300[0x580];
8102
8103         u8         pas[][0x40];
8104 };
8105
8106 struct mlx5_ifc_create_tis_out_bits {
8107         u8         status[0x8];
8108         u8         reserved_at_8[0x18];
8109
8110         u8         syndrome[0x20];
8111
8112         u8         reserved_at_40[0x8];
8113         u8         tisn[0x18];
8114
8115         u8         reserved_at_60[0x20];
8116 };
8117
8118 struct mlx5_ifc_create_tis_in_bits {
8119         u8         opcode[0x10];
8120         u8         uid[0x10];
8121
8122         u8         reserved_at_20[0x10];
8123         u8         op_mod[0x10];
8124
8125         u8         reserved_at_40[0xc0];
8126
8127         struct mlx5_ifc_tisc_bits ctx;
8128 };
8129
8130 struct mlx5_ifc_create_tir_out_bits {
8131         u8         status[0x8];
8132         u8         icm_address_63_40[0x18];
8133
8134         u8         syndrome[0x20];
8135
8136         u8         icm_address_39_32[0x8];
8137         u8         tirn[0x18];
8138
8139         u8         icm_address_31_0[0x20];
8140 };
8141
8142 struct mlx5_ifc_create_tir_in_bits {
8143         u8         opcode[0x10];
8144         u8         uid[0x10];
8145
8146         u8         reserved_at_20[0x10];
8147         u8         op_mod[0x10];
8148
8149         u8         reserved_at_40[0xc0];
8150
8151         struct mlx5_ifc_tirc_bits ctx;
8152 };
8153
8154 struct mlx5_ifc_create_srq_out_bits {
8155         u8         status[0x8];
8156         u8         reserved_at_8[0x18];
8157
8158         u8         syndrome[0x20];
8159
8160         u8         reserved_at_40[0x8];
8161         u8         srqn[0x18];
8162
8163         u8         reserved_at_60[0x20];
8164 };
8165
8166 struct mlx5_ifc_create_srq_in_bits {
8167         u8         opcode[0x10];
8168         u8         uid[0x10];
8169
8170         u8         reserved_at_20[0x10];
8171         u8         op_mod[0x10];
8172
8173         u8         reserved_at_40[0x40];
8174
8175         struct mlx5_ifc_srqc_bits srq_context_entry;
8176
8177         u8         reserved_at_280[0x600];
8178
8179         u8         pas[][0x40];
8180 };
8181
8182 struct mlx5_ifc_create_sq_out_bits {
8183         u8         status[0x8];
8184         u8         reserved_at_8[0x18];
8185
8186         u8         syndrome[0x20];
8187
8188         u8         reserved_at_40[0x8];
8189         u8         sqn[0x18];
8190
8191         u8         reserved_at_60[0x20];
8192 };
8193
8194 struct mlx5_ifc_create_sq_in_bits {
8195         u8         opcode[0x10];
8196         u8         uid[0x10];
8197
8198         u8         reserved_at_20[0x10];
8199         u8         op_mod[0x10];
8200
8201         u8         reserved_at_40[0xc0];
8202
8203         struct mlx5_ifc_sqc_bits ctx;
8204 };
8205
8206 struct mlx5_ifc_create_scheduling_element_out_bits {
8207         u8         status[0x8];
8208         u8         reserved_at_8[0x18];
8209
8210         u8         syndrome[0x20];
8211
8212         u8         reserved_at_40[0x40];
8213
8214         u8         scheduling_element_id[0x20];
8215
8216         u8         reserved_at_a0[0x160];
8217 };
8218
8219 struct mlx5_ifc_create_scheduling_element_in_bits {
8220         u8         opcode[0x10];
8221         u8         reserved_at_10[0x10];
8222
8223         u8         reserved_at_20[0x10];
8224         u8         op_mod[0x10];
8225
8226         u8         scheduling_hierarchy[0x8];
8227         u8         reserved_at_48[0x18];
8228
8229         u8         reserved_at_60[0xa0];
8230
8231         struct mlx5_ifc_scheduling_context_bits scheduling_context;
8232
8233         u8         reserved_at_300[0x100];
8234 };
8235
8236 struct mlx5_ifc_create_rqt_out_bits {
8237         u8         status[0x8];
8238         u8         reserved_at_8[0x18];
8239
8240         u8         syndrome[0x20];
8241
8242         u8         reserved_at_40[0x8];
8243         u8         rqtn[0x18];
8244
8245         u8         reserved_at_60[0x20];
8246 };
8247
8248 struct mlx5_ifc_create_rqt_in_bits {
8249         u8         opcode[0x10];
8250         u8         uid[0x10];
8251
8252         u8         reserved_at_20[0x10];
8253         u8         op_mod[0x10];
8254
8255         u8         reserved_at_40[0xc0];
8256
8257         struct mlx5_ifc_rqtc_bits rqt_context;
8258 };
8259
8260 struct mlx5_ifc_create_rq_out_bits {
8261         u8         status[0x8];
8262         u8         reserved_at_8[0x18];
8263
8264         u8         syndrome[0x20];
8265
8266         u8         reserved_at_40[0x8];
8267         u8         rqn[0x18];
8268
8269         u8         reserved_at_60[0x20];
8270 };
8271
8272 struct mlx5_ifc_create_rq_in_bits {
8273         u8         opcode[0x10];
8274         u8         uid[0x10];
8275
8276         u8         reserved_at_20[0x10];
8277         u8         op_mod[0x10];
8278
8279         u8         reserved_at_40[0xc0];
8280
8281         struct mlx5_ifc_rqc_bits ctx;
8282 };
8283
8284 struct mlx5_ifc_create_rmp_out_bits {
8285         u8         status[0x8];
8286         u8         reserved_at_8[0x18];
8287
8288         u8         syndrome[0x20];
8289
8290         u8         reserved_at_40[0x8];
8291         u8         rmpn[0x18];
8292
8293         u8         reserved_at_60[0x20];
8294 };
8295
8296 struct mlx5_ifc_create_rmp_in_bits {
8297         u8         opcode[0x10];
8298         u8         uid[0x10];
8299
8300         u8         reserved_at_20[0x10];
8301         u8         op_mod[0x10];
8302
8303         u8         reserved_at_40[0xc0];
8304
8305         struct mlx5_ifc_rmpc_bits ctx;
8306 };
8307
8308 struct mlx5_ifc_create_qp_out_bits {
8309         u8         status[0x8];
8310         u8         reserved_at_8[0x18];
8311
8312         u8         syndrome[0x20];
8313
8314         u8         reserved_at_40[0x8];
8315         u8         qpn[0x18];
8316
8317         u8         ece[0x20];
8318 };
8319
8320 struct mlx5_ifc_create_qp_in_bits {
8321         u8         opcode[0x10];
8322         u8         uid[0x10];
8323
8324         u8         reserved_at_20[0x10];
8325         u8         op_mod[0x10];
8326
8327         u8         reserved_at_40[0x8];
8328         u8         input_qpn[0x18];
8329
8330         u8         reserved_at_60[0x20];
8331         u8         opt_param_mask[0x20];
8332
8333         u8         ece[0x20];
8334
8335         struct mlx5_ifc_qpc_bits qpc;
8336
8337         u8         reserved_at_800[0x60];
8338
8339         u8         wq_umem_valid[0x1];
8340         u8         reserved_at_861[0x1f];
8341
8342         u8         pas[][0x40];
8343 };
8344
8345 struct mlx5_ifc_create_psv_out_bits {
8346         u8         status[0x8];
8347         u8         reserved_at_8[0x18];
8348
8349         u8         syndrome[0x20];
8350
8351         u8         reserved_at_40[0x40];
8352
8353         u8         reserved_at_80[0x8];
8354         u8         psv0_index[0x18];
8355
8356         u8         reserved_at_a0[0x8];
8357         u8         psv1_index[0x18];
8358
8359         u8         reserved_at_c0[0x8];
8360         u8         psv2_index[0x18];
8361
8362         u8         reserved_at_e0[0x8];
8363         u8         psv3_index[0x18];
8364 };
8365
8366 struct mlx5_ifc_create_psv_in_bits {
8367         u8         opcode[0x10];
8368         u8         reserved_at_10[0x10];
8369
8370         u8         reserved_at_20[0x10];
8371         u8         op_mod[0x10];
8372
8373         u8         num_psv[0x4];
8374         u8         reserved_at_44[0x4];
8375         u8         pd[0x18];
8376
8377         u8         reserved_at_60[0x20];
8378 };
8379
8380 struct mlx5_ifc_create_mkey_out_bits {
8381         u8         status[0x8];
8382         u8         reserved_at_8[0x18];
8383
8384         u8         syndrome[0x20];
8385
8386         u8         reserved_at_40[0x8];
8387         u8         mkey_index[0x18];
8388
8389         u8         reserved_at_60[0x20];
8390 };
8391
8392 struct mlx5_ifc_create_mkey_in_bits {
8393         u8         opcode[0x10];
8394         u8         uid[0x10];
8395
8396         u8         reserved_at_20[0x10];
8397         u8         op_mod[0x10];
8398
8399         u8         reserved_at_40[0x20];
8400
8401         u8         pg_access[0x1];
8402         u8         mkey_umem_valid[0x1];
8403         u8         reserved_at_62[0x1e];
8404
8405         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8406
8407         u8         reserved_at_280[0x80];
8408
8409         u8         translations_octword_actual_size[0x20];
8410
8411         u8         reserved_at_320[0x560];
8412
8413         u8         klm_pas_mtt[][0x20];
8414 };
8415
8416 enum {
8417         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
8418         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
8419         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
8420         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
8421         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
8422         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
8423         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
8424 };
8425
8426 struct mlx5_ifc_create_flow_table_out_bits {
8427         u8         status[0x8];
8428         u8         icm_address_63_40[0x18];
8429
8430         u8         syndrome[0x20];
8431
8432         u8         icm_address_39_32[0x8];
8433         u8         table_id[0x18];
8434
8435         u8         icm_address_31_0[0x20];
8436 };
8437
8438 struct mlx5_ifc_create_flow_table_in_bits {
8439         u8         opcode[0x10];
8440         u8         reserved_at_10[0x10];
8441
8442         u8         reserved_at_20[0x10];
8443         u8         op_mod[0x10];
8444
8445         u8         other_vport[0x1];
8446         u8         reserved_at_41[0xf];
8447         u8         vport_number[0x10];
8448
8449         u8         reserved_at_60[0x20];
8450
8451         u8         table_type[0x8];
8452         u8         reserved_at_88[0x18];
8453
8454         u8         reserved_at_a0[0x20];
8455
8456         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8457 };
8458
8459 struct mlx5_ifc_create_flow_group_out_bits {
8460         u8         status[0x8];
8461         u8         reserved_at_8[0x18];
8462
8463         u8         syndrome[0x20];
8464
8465         u8         reserved_at_40[0x8];
8466         u8         group_id[0x18];
8467
8468         u8         reserved_at_60[0x20];
8469 };
8470
8471 enum {
8472         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
8473         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
8474 };
8475
8476 enum {
8477         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8478         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8479         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8480         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8481 };
8482
8483 struct mlx5_ifc_create_flow_group_in_bits {
8484         u8         opcode[0x10];
8485         u8         reserved_at_10[0x10];
8486
8487         u8         reserved_at_20[0x10];
8488         u8         op_mod[0x10];
8489
8490         u8         other_vport[0x1];
8491         u8         reserved_at_41[0xf];
8492         u8         vport_number[0x10];
8493
8494         u8         reserved_at_60[0x20];
8495
8496         u8         table_type[0x8];
8497         u8         reserved_at_88[0x4];
8498         u8         group_type[0x4];
8499         u8         reserved_at_90[0x10];
8500
8501         u8         reserved_at_a0[0x8];
8502         u8         table_id[0x18];
8503
8504         u8         source_eswitch_owner_vhca_id_valid[0x1];
8505
8506         u8         reserved_at_c1[0x1f];
8507
8508         u8         start_flow_index[0x20];
8509
8510         u8         reserved_at_100[0x20];
8511
8512         u8         end_flow_index[0x20];
8513
8514         u8         reserved_at_140[0x10];
8515         u8         match_definer_id[0x10];
8516
8517         u8         reserved_at_160[0x80];
8518
8519         u8         reserved_at_1e0[0x18];
8520         u8         match_criteria_enable[0x8];
8521
8522         struct mlx5_ifc_fte_match_param_bits match_criteria;
8523
8524         u8         reserved_at_1200[0xe00];
8525 };
8526
8527 struct mlx5_ifc_create_eq_out_bits {
8528         u8         status[0x8];
8529         u8         reserved_at_8[0x18];
8530
8531         u8         syndrome[0x20];
8532
8533         u8         reserved_at_40[0x18];
8534         u8         eq_number[0x8];
8535
8536         u8         reserved_at_60[0x20];
8537 };
8538
8539 struct mlx5_ifc_create_eq_in_bits {
8540         u8         opcode[0x10];
8541         u8         uid[0x10];
8542
8543         u8         reserved_at_20[0x10];
8544         u8         op_mod[0x10];
8545
8546         u8         reserved_at_40[0x40];
8547
8548         struct mlx5_ifc_eqc_bits eq_context_entry;
8549
8550         u8         reserved_at_280[0x40];
8551
8552         u8         event_bitmask[4][0x40];
8553
8554         u8         reserved_at_3c0[0x4c0];
8555
8556         u8         pas[][0x40];
8557 };
8558
8559 struct mlx5_ifc_create_dct_out_bits {
8560         u8         status[0x8];
8561         u8         reserved_at_8[0x18];
8562
8563         u8         syndrome[0x20];
8564
8565         u8         reserved_at_40[0x8];
8566         u8         dctn[0x18];
8567
8568         u8         ece[0x20];
8569 };
8570
8571 struct mlx5_ifc_create_dct_in_bits {
8572         u8         opcode[0x10];
8573         u8         uid[0x10];
8574
8575         u8         reserved_at_20[0x10];
8576         u8         op_mod[0x10];
8577
8578         u8         reserved_at_40[0x40];
8579
8580         struct mlx5_ifc_dctc_bits dct_context_entry;
8581
8582         u8         reserved_at_280[0x180];
8583 };
8584
8585 struct mlx5_ifc_create_cq_out_bits {
8586         u8         status[0x8];
8587         u8         reserved_at_8[0x18];
8588
8589         u8         syndrome[0x20];
8590
8591         u8         reserved_at_40[0x8];
8592         u8         cqn[0x18];
8593
8594         u8         reserved_at_60[0x20];
8595 };
8596
8597 struct mlx5_ifc_create_cq_in_bits {
8598         u8         opcode[0x10];
8599         u8         uid[0x10];
8600
8601         u8         reserved_at_20[0x10];
8602         u8         op_mod[0x10];
8603
8604         u8         reserved_at_40[0x40];
8605
8606         struct mlx5_ifc_cqc_bits cq_context;
8607
8608         u8         reserved_at_280[0x60];
8609
8610         u8         cq_umem_valid[0x1];
8611         u8         reserved_at_2e1[0x59f];
8612
8613         u8         pas[][0x40];
8614 };
8615
8616 struct mlx5_ifc_config_int_moderation_out_bits {
8617         u8         status[0x8];
8618         u8         reserved_at_8[0x18];
8619
8620         u8         syndrome[0x20];
8621
8622         u8         reserved_at_40[0x4];
8623         u8         min_delay[0xc];
8624         u8         int_vector[0x10];
8625
8626         u8         reserved_at_60[0x20];
8627 };
8628
8629 enum {
8630         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8631         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8632 };
8633
8634 struct mlx5_ifc_config_int_moderation_in_bits {
8635         u8         opcode[0x10];
8636         u8         reserved_at_10[0x10];
8637
8638         u8         reserved_at_20[0x10];
8639         u8         op_mod[0x10];
8640
8641         u8         reserved_at_40[0x4];
8642         u8         min_delay[0xc];
8643         u8         int_vector[0x10];
8644
8645         u8         reserved_at_60[0x20];
8646 };
8647
8648 struct mlx5_ifc_attach_to_mcg_out_bits {
8649         u8         status[0x8];
8650         u8         reserved_at_8[0x18];
8651
8652         u8         syndrome[0x20];
8653
8654         u8         reserved_at_40[0x40];
8655 };
8656
8657 struct mlx5_ifc_attach_to_mcg_in_bits {
8658         u8         opcode[0x10];
8659         u8         uid[0x10];
8660
8661         u8         reserved_at_20[0x10];
8662         u8         op_mod[0x10];
8663
8664         u8         reserved_at_40[0x8];
8665         u8         qpn[0x18];
8666
8667         u8         reserved_at_60[0x20];
8668
8669         u8         multicast_gid[16][0x8];
8670 };
8671
8672 struct mlx5_ifc_arm_xrq_out_bits {
8673         u8         status[0x8];
8674         u8         reserved_at_8[0x18];
8675
8676         u8         syndrome[0x20];
8677
8678         u8         reserved_at_40[0x40];
8679 };
8680
8681 struct mlx5_ifc_arm_xrq_in_bits {
8682         u8         opcode[0x10];
8683         u8         reserved_at_10[0x10];
8684
8685         u8         reserved_at_20[0x10];
8686         u8         op_mod[0x10];
8687
8688         u8         reserved_at_40[0x8];
8689         u8         xrqn[0x18];
8690
8691         u8         reserved_at_60[0x10];
8692         u8         lwm[0x10];
8693 };
8694
8695 struct mlx5_ifc_arm_xrc_srq_out_bits {
8696         u8         status[0x8];
8697         u8         reserved_at_8[0x18];
8698
8699         u8         syndrome[0x20];
8700
8701         u8         reserved_at_40[0x40];
8702 };
8703
8704 enum {
8705         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8706 };
8707
8708 struct mlx5_ifc_arm_xrc_srq_in_bits {
8709         u8         opcode[0x10];
8710         u8         uid[0x10];
8711
8712         u8         reserved_at_20[0x10];
8713         u8         op_mod[0x10];
8714
8715         u8         reserved_at_40[0x8];
8716         u8         xrc_srqn[0x18];
8717
8718         u8         reserved_at_60[0x10];
8719         u8         lwm[0x10];
8720 };
8721
8722 struct mlx5_ifc_arm_rq_out_bits {
8723         u8         status[0x8];
8724         u8         reserved_at_8[0x18];
8725
8726         u8         syndrome[0x20];
8727
8728         u8         reserved_at_40[0x40];
8729 };
8730
8731 enum {
8732         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8733         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8734 };
8735
8736 struct mlx5_ifc_arm_rq_in_bits {
8737         u8         opcode[0x10];
8738         u8         uid[0x10];
8739
8740         u8         reserved_at_20[0x10];
8741         u8         op_mod[0x10];
8742
8743         u8         reserved_at_40[0x8];
8744         u8         srq_number[0x18];
8745
8746         u8         reserved_at_60[0x10];
8747         u8         lwm[0x10];
8748 };
8749
8750 struct mlx5_ifc_arm_dct_out_bits {
8751         u8         status[0x8];
8752         u8         reserved_at_8[0x18];
8753
8754         u8         syndrome[0x20];
8755
8756         u8         reserved_at_40[0x40];
8757 };
8758
8759 struct mlx5_ifc_arm_dct_in_bits {
8760         u8         opcode[0x10];
8761         u8         reserved_at_10[0x10];
8762
8763         u8         reserved_at_20[0x10];
8764         u8         op_mod[0x10];
8765
8766         u8         reserved_at_40[0x8];
8767         u8         dct_number[0x18];
8768
8769         u8         reserved_at_60[0x20];
8770 };
8771
8772 struct mlx5_ifc_alloc_xrcd_out_bits {
8773         u8         status[0x8];
8774         u8         reserved_at_8[0x18];
8775
8776         u8         syndrome[0x20];
8777
8778         u8         reserved_at_40[0x8];
8779         u8         xrcd[0x18];
8780
8781         u8         reserved_at_60[0x20];
8782 };
8783
8784 struct mlx5_ifc_alloc_xrcd_in_bits {
8785         u8         opcode[0x10];
8786         u8         uid[0x10];
8787
8788         u8         reserved_at_20[0x10];
8789         u8         op_mod[0x10];
8790
8791         u8         reserved_at_40[0x40];
8792 };
8793
8794 struct mlx5_ifc_alloc_uar_out_bits {
8795         u8         status[0x8];
8796         u8         reserved_at_8[0x18];
8797
8798         u8         syndrome[0x20];
8799
8800         u8         reserved_at_40[0x8];
8801         u8         uar[0x18];
8802
8803         u8         reserved_at_60[0x20];
8804 };
8805
8806 struct mlx5_ifc_alloc_uar_in_bits {
8807         u8         opcode[0x10];
8808         u8         uid[0x10];
8809
8810         u8         reserved_at_20[0x10];
8811         u8         op_mod[0x10];
8812
8813         u8         reserved_at_40[0x40];
8814 };
8815
8816 struct mlx5_ifc_alloc_transport_domain_out_bits {
8817         u8         status[0x8];
8818         u8         reserved_at_8[0x18];
8819
8820         u8         syndrome[0x20];
8821
8822         u8         reserved_at_40[0x8];
8823         u8         transport_domain[0x18];
8824
8825         u8         reserved_at_60[0x20];
8826 };
8827
8828 struct mlx5_ifc_alloc_transport_domain_in_bits {
8829         u8         opcode[0x10];
8830         u8         uid[0x10];
8831
8832         u8         reserved_at_20[0x10];
8833         u8         op_mod[0x10];
8834
8835         u8         reserved_at_40[0x40];
8836 };
8837
8838 struct mlx5_ifc_alloc_q_counter_out_bits {
8839         u8         status[0x8];
8840         u8         reserved_at_8[0x18];
8841
8842         u8         syndrome[0x20];
8843
8844         u8         reserved_at_40[0x18];
8845         u8         counter_set_id[0x8];
8846
8847         u8         reserved_at_60[0x20];
8848 };
8849
8850 struct mlx5_ifc_alloc_q_counter_in_bits {
8851         u8         opcode[0x10];
8852         u8         uid[0x10];
8853
8854         u8         reserved_at_20[0x10];
8855         u8         op_mod[0x10];
8856
8857         u8         reserved_at_40[0x40];
8858 };
8859
8860 struct mlx5_ifc_alloc_pd_out_bits {
8861         u8         status[0x8];
8862         u8         reserved_at_8[0x18];
8863
8864         u8         syndrome[0x20];
8865
8866         u8         reserved_at_40[0x8];
8867         u8         pd[0x18];
8868
8869         u8         reserved_at_60[0x20];
8870 };
8871
8872 struct mlx5_ifc_alloc_pd_in_bits {
8873         u8         opcode[0x10];
8874         u8         uid[0x10];
8875
8876         u8         reserved_at_20[0x10];
8877         u8         op_mod[0x10];
8878
8879         u8         reserved_at_40[0x40];
8880 };
8881
8882 struct mlx5_ifc_alloc_flow_counter_out_bits {
8883         u8         status[0x8];
8884         u8         reserved_at_8[0x18];
8885
8886         u8         syndrome[0x20];
8887
8888         u8         flow_counter_id[0x20];
8889
8890         u8         reserved_at_60[0x20];
8891 };
8892
8893 struct mlx5_ifc_alloc_flow_counter_in_bits {
8894         u8         opcode[0x10];
8895         u8         reserved_at_10[0x10];
8896
8897         u8         reserved_at_20[0x10];
8898         u8         op_mod[0x10];
8899
8900         u8         reserved_at_40[0x38];
8901         u8         flow_counter_bulk[0x8];
8902 };
8903
8904 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8905         u8         status[0x8];
8906         u8         reserved_at_8[0x18];
8907
8908         u8         syndrome[0x20];
8909
8910         u8         reserved_at_40[0x40];
8911 };
8912
8913 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8914         u8         opcode[0x10];
8915         u8         reserved_at_10[0x10];
8916
8917         u8         reserved_at_20[0x10];
8918         u8         op_mod[0x10];
8919
8920         u8         reserved_at_40[0x20];
8921
8922         u8         reserved_at_60[0x10];
8923         u8         vxlan_udp_port[0x10];
8924 };
8925
8926 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8927         u8         status[0x8];
8928         u8         reserved_at_8[0x18];
8929
8930         u8         syndrome[0x20];
8931
8932         u8         reserved_at_40[0x40];
8933 };
8934
8935 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8936         u8         rate_limit[0x20];
8937
8938         u8         burst_upper_bound[0x20];
8939
8940         u8         reserved_at_40[0x10];
8941         u8         typical_packet_size[0x10];
8942
8943         u8         reserved_at_60[0x120];
8944 };
8945
8946 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8947         u8         opcode[0x10];
8948         u8         uid[0x10];
8949
8950         u8         reserved_at_20[0x10];
8951         u8         op_mod[0x10];
8952
8953         u8         reserved_at_40[0x10];
8954         u8         rate_limit_index[0x10];
8955
8956         u8         reserved_at_60[0x20];
8957
8958         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8959 };
8960
8961 struct mlx5_ifc_access_register_out_bits {
8962         u8         status[0x8];
8963         u8         reserved_at_8[0x18];
8964
8965         u8         syndrome[0x20];
8966
8967         u8         reserved_at_40[0x40];
8968
8969         u8         register_data[][0x20];
8970 };
8971
8972 enum {
8973         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8974         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8975 };
8976
8977 struct mlx5_ifc_access_register_in_bits {
8978         u8         opcode[0x10];
8979         u8         reserved_at_10[0x10];
8980
8981         u8         reserved_at_20[0x10];
8982         u8         op_mod[0x10];
8983
8984         u8         reserved_at_40[0x10];
8985         u8         register_id[0x10];
8986
8987         u8         argument[0x20];
8988
8989         u8         register_data[][0x20];
8990 };
8991
8992 struct mlx5_ifc_sltp_reg_bits {
8993         u8         status[0x4];
8994         u8         version[0x4];
8995         u8         local_port[0x8];
8996         u8         pnat[0x2];
8997         u8         reserved_at_12[0x2];
8998         u8         lane[0x4];
8999         u8         reserved_at_18[0x8];
9000
9001         u8         reserved_at_20[0x20];
9002
9003         u8         reserved_at_40[0x7];
9004         u8         polarity[0x1];
9005         u8         ob_tap0[0x8];
9006         u8         ob_tap1[0x8];
9007         u8         ob_tap2[0x8];
9008
9009         u8         reserved_at_60[0xc];
9010         u8         ob_preemp_mode[0x4];
9011         u8         ob_reg[0x8];
9012         u8         ob_bias[0x8];
9013
9014         u8         reserved_at_80[0x20];
9015 };
9016
9017 struct mlx5_ifc_slrg_reg_bits {
9018         u8         status[0x4];
9019         u8         version[0x4];
9020         u8         local_port[0x8];
9021         u8         pnat[0x2];
9022         u8         reserved_at_12[0x2];
9023         u8         lane[0x4];
9024         u8         reserved_at_18[0x8];
9025
9026         u8         time_to_link_up[0x10];
9027         u8         reserved_at_30[0xc];
9028         u8         grade_lane_speed[0x4];
9029
9030         u8         grade_version[0x8];
9031         u8         grade[0x18];
9032
9033         u8         reserved_at_60[0x4];
9034         u8         height_grade_type[0x4];
9035         u8         height_grade[0x18];
9036
9037         u8         height_dz[0x10];
9038         u8         height_dv[0x10];
9039
9040         u8         reserved_at_a0[0x10];
9041         u8         height_sigma[0x10];
9042
9043         u8         reserved_at_c0[0x20];
9044
9045         u8         reserved_at_e0[0x4];
9046         u8         phase_grade_type[0x4];
9047         u8         phase_grade[0x18];
9048
9049         u8         reserved_at_100[0x8];
9050         u8         phase_eo_pos[0x8];
9051         u8         reserved_at_110[0x8];
9052         u8         phase_eo_neg[0x8];
9053
9054         u8         ffe_set_tested[0x10];
9055         u8         test_errors_per_lane[0x10];
9056 };
9057
9058 struct mlx5_ifc_pvlc_reg_bits {
9059         u8         reserved_at_0[0x8];
9060         u8         local_port[0x8];
9061         u8         reserved_at_10[0x10];
9062
9063         u8         reserved_at_20[0x1c];
9064         u8         vl_hw_cap[0x4];
9065
9066         u8         reserved_at_40[0x1c];
9067         u8         vl_admin[0x4];
9068
9069         u8         reserved_at_60[0x1c];
9070         u8         vl_operational[0x4];
9071 };
9072
9073 struct mlx5_ifc_pude_reg_bits {
9074         u8         swid[0x8];
9075         u8         local_port[0x8];
9076         u8         reserved_at_10[0x4];
9077         u8         admin_status[0x4];
9078         u8         reserved_at_18[0x4];
9079         u8         oper_status[0x4];
9080
9081         u8         reserved_at_20[0x60];
9082 };
9083
9084 struct mlx5_ifc_ptys_reg_bits {
9085         u8         reserved_at_0[0x1];
9086         u8         an_disable_admin[0x1];
9087         u8         an_disable_cap[0x1];
9088         u8         reserved_at_3[0x5];
9089         u8         local_port[0x8];
9090         u8         reserved_at_10[0xd];
9091         u8         proto_mask[0x3];
9092
9093         u8         an_status[0x4];
9094         u8         reserved_at_24[0xc];
9095         u8         data_rate_oper[0x10];
9096
9097         u8         ext_eth_proto_capability[0x20];
9098
9099         u8         eth_proto_capability[0x20];
9100
9101         u8         ib_link_width_capability[0x10];
9102         u8         ib_proto_capability[0x10];
9103
9104         u8         ext_eth_proto_admin[0x20];
9105
9106         u8         eth_proto_admin[0x20];
9107
9108         u8         ib_link_width_admin[0x10];
9109         u8         ib_proto_admin[0x10];
9110
9111         u8         ext_eth_proto_oper[0x20];
9112
9113         u8         eth_proto_oper[0x20];
9114
9115         u8         ib_link_width_oper[0x10];
9116         u8         ib_proto_oper[0x10];
9117
9118         u8         reserved_at_160[0x1c];
9119         u8         connector_type[0x4];
9120
9121         u8         eth_proto_lp_advertise[0x20];
9122
9123         u8         reserved_at_1a0[0x60];
9124 };
9125
9126 struct mlx5_ifc_mlcr_reg_bits {
9127         u8         reserved_at_0[0x8];
9128         u8         local_port[0x8];
9129         u8         reserved_at_10[0x20];
9130
9131         u8         beacon_duration[0x10];
9132         u8         reserved_at_40[0x10];
9133
9134         u8         beacon_remain[0x10];
9135 };
9136
9137 struct mlx5_ifc_ptas_reg_bits {
9138         u8         reserved_at_0[0x20];
9139
9140         u8         algorithm_options[0x10];
9141         u8         reserved_at_30[0x4];
9142         u8         repetitions_mode[0x4];
9143         u8         num_of_repetitions[0x8];
9144
9145         u8         grade_version[0x8];
9146         u8         height_grade_type[0x4];
9147         u8         phase_grade_type[0x4];
9148         u8         height_grade_weight[0x8];
9149         u8         phase_grade_weight[0x8];
9150
9151         u8         gisim_measure_bits[0x10];
9152         u8         adaptive_tap_measure_bits[0x10];
9153
9154         u8         ber_bath_high_error_threshold[0x10];
9155         u8         ber_bath_mid_error_threshold[0x10];
9156
9157         u8         ber_bath_low_error_threshold[0x10];
9158         u8         one_ratio_high_threshold[0x10];
9159
9160         u8         one_ratio_high_mid_threshold[0x10];
9161         u8         one_ratio_low_mid_threshold[0x10];
9162
9163         u8         one_ratio_low_threshold[0x10];
9164         u8         ndeo_error_threshold[0x10];
9165
9166         u8         mixer_offset_step_size[0x10];
9167         u8         reserved_at_110[0x8];
9168         u8         mix90_phase_for_voltage_bath[0x8];
9169
9170         u8         mixer_offset_start[0x10];
9171         u8         mixer_offset_end[0x10];
9172
9173         u8         reserved_at_140[0x15];
9174         u8         ber_test_time[0xb];
9175 };
9176
9177 struct mlx5_ifc_pspa_reg_bits {
9178         u8         swid[0x8];
9179         u8         local_port[0x8];
9180         u8         sub_port[0x8];
9181         u8         reserved_at_18[0x8];
9182
9183         u8         reserved_at_20[0x20];
9184 };
9185
9186 struct mlx5_ifc_pqdr_reg_bits {
9187         u8         reserved_at_0[0x8];
9188         u8         local_port[0x8];
9189         u8         reserved_at_10[0x5];
9190         u8         prio[0x3];
9191         u8         reserved_at_18[0x6];
9192         u8         mode[0x2];
9193
9194         u8         reserved_at_20[0x20];
9195
9196         u8         reserved_at_40[0x10];
9197         u8         min_threshold[0x10];
9198
9199         u8         reserved_at_60[0x10];
9200         u8         max_threshold[0x10];
9201
9202         u8         reserved_at_80[0x10];
9203         u8         mark_probability_denominator[0x10];
9204
9205         u8         reserved_at_a0[0x60];
9206 };
9207
9208 struct mlx5_ifc_ppsc_reg_bits {
9209         u8         reserved_at_0[0x8];
9210         u8         local_port[0x8];
9211         u8         reserved_at_10[0x10];
9212
9213         u8         reserved_at_20[0x60];
9214
9215         u8         reserved_at_80[0x1c];
9216         u8         wrps_admin[0x4];
9217
9218         u8         reserved_at_a0[0x1c];
9219         u8         wrps_status[0x4];
9220
9221         u8         reserved_at_c0[0x8];
9222         u8         up_threshold[0x8];
9223         u8         reserved_at_d0[0x8];
9224         u8         down_threshold[0x8];
9225
9226         u8         reserved_at_e0[0x20];
9227
9228         u8         reserved_at_100[0x1c];
9229         u8         srps_admin[0x4];
9230
9231         u8         reserved_at_120[0x1c];
9232         u8         srps_status[0x4];
9233
9234         u8         reserved_at_140[0x40];
9235 };
9236
9237 struct mlx5_ifc_pplr_reg_bits {
9238         u8         reserved_at_0[0x8];
9239         u8         local_port[0x8];
9240         u8         reserved_at_10[0x10];
9241
9242         u8         reserved_at_20[0x8];
9243         u8         lb_cap[0x8];
9244         u8         reserved_at_30[0x8];
9245         u8         lb_en[0x8];
9246 };
9247
9248 struct mlx5_ifc_pplm_reg_bits {
9249         u8         reserved_at_0[0x8];
9250         u8         local_port[0x8];
9251         u8         reserved_at_10[0x10];
9252
9253         u8         reserved_at_20[0x20];
9254
9255         u8         port_profile_mode[0x8];
9256         u8         static_port_profile[0x8];
9257         u8         active_port_profile[0x8];
9258         u8         reserved_at_58[0x8];
9259
9260         u8         retransmission_active[0x8];
9261         u8         fec_mode_active[0x18];
9262
9263         u8         rs_fec_correction_bypass_cap[0x4];
9264         u8         reserved_at_84[0x8];
9265         u8         fec_override_cap_56g[0x4];
9266         u8         fec_override_cap_100g[0x4];
9267         u8         fec_override_cap_50g[0x4];
9268         u8         fec_override_cap_25g[0x4];
9269         u8         fec_override_cap_10g_40g[0x4];
9270
9271         u8         rs_fec_correction_bypass_admin[0x4];
9272         u8         reserved_at_a4[0x8];
9273         u8         fec_override_admin_56g[0x4];
9274         u8         fec_override_admin_100g[0x4];
9275         u8         fec_override_admin_50g[0x4];
9276         u8         fec_override_admin_25g[0x4];
9277         u8         fec_override_admin_10g_40g[0x4];
9278
9279         u8         fec_override_cap_400g_8x[0x10];
9280         u8         fec_override_cap_200g_4x[0x10];
9281
9282         u8         fec_override_cap_100g_2x[0x10];
9283         u8         fec_override_cap_50g_1x[0x10];
9284
9285         u8         fec_override_admin_400g_8x[0x10];
9286         u8         fec_override_admin_200g_4x[0x10];
9287
9288         u8         fec_override_admin_100g_2x[0x10];
9289         u8         fec_override_admin_50g_1x[0x10];
9290
9291         u8         reserved_at_140[0x140];
9292 };
9293
9294 struct mlx5_ifc_ppcnt_reg_bits {
9295         u8         swid[0x8];
9296         u8         local_port[0x8];
9297         u8         pnat[0x2];
9298         u8         reserved_at_12[0x8];
9299         u8         grp[0x6];
9300
9301         u8         clr[0x1];
9302         u8         reserved_at_21[0x1c];
9303         u8         prio_tc[0x3];
9304
9305         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9306 };
9307
9308 struct mlx5_ifc_mpein_reg_bits {
9309         u8         reserved_at_0[0x2];
9310         u8         depth[0x6];
9311         u8         pcie_index[0x8];
9312         u8         node[0x8];
9313         u8         reserved_at_18[0x8];
9314
9315         u8         capability_mask[0x20];
9316
9317         u8         reserved_at_40[0x8];
9318         u8         link_width_enabled[0x8];
9319         u8         link_speed_enabled[0x10];
9320
9321         u8         lane0_physical_position[0x8];
9322         u8         link_width_active[0x8];
9323         u8         link_speed_active[0x10];
9324
9325         u8         num_of_pfs[0x10];
9326         u8         num_of_vfs[0x10];
9327
9328         u8         bdf0[0x10];
9329         u8         reserved_at_b0[0x10];
9330
9331         u8         max_read_request_size[0x4];
9332         u8         max_payload_size[0x4];
9333         u8         reserved_at_c8[0x5];
9334         u8         pwr_status[0x3];
9335         u8         port_type[0x4];
9336         u8         reserved_at_d4[0xb];
9337         u8         lane_reversal[0x1];
9338
9339         u8         reserved_at_e0[0x14];
9340         u8         pci_power[0xc];
9341
9342         u8         reserved_at_100[0x20];
9343
9344         u8         device_status[0x10];
9345         u8         port_state[0x8];
9346         u8         reserved_at_138[0x8];
9347
9348         u8         reserved_at_140[0x10];
9349         u8         receiver_detect_result[0x10];
9350
9351         u8         reserved_at_160[0x20];
9352 };
9353
9354 struct mlx5_ifc_mpcnt_reg_bits {
9355         u8         reserved_at_0[0x8];
9356         u8         pcie_index[0x8];
9357         u8         reserved_at_10[0xa];
9358         u8         grp[0x6];
9359
9360         u8         clr[0x1];
9361         u8         reserved_at_21[0x1f];
9362
9363         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9364 };
9365
9366 struct mlx5_ifc_ppad_reg_bits {
9367         u8         reserved_at_0[0x3];
9368         u8         single_mac[0x1];
9369         u8         reserved_at_4[0x4];
9370         u8         local_port[0x8];
9371         u8         mac_47_32[0x10];
9372
9373         u8         mac_31_0[0x20];
9374
9375         u8         reserved_at_40[0x40];
9376 };
9377
9378 struct mlx5_ifc_pmtu_reg_bits {
9379         u8         reserved_at_0[0x8];
9380         u8         local_port[0x8];
9381         u8         reserved_at_10[0x10];
9382
9383         u8         max_mtu[0x10];
9384         u8         reserved_at_30[0x10];
9385
9386         u8         admin_mtu[0x10];
9387         u8         reserved_at_50[0x10];
9388
9389         u8         oper_mtu[0x10];
9390         u8         reserved_at_70[0x10];
9391 };
9392
9393 struct mlx5_ifc_pmpr_reg_bits {
9394         u8         reserved_at_0[0x8];
9395         u8         module[0x8];
9396         u8         reserved_at_10[0x10];
9397
9398         u8         reserved_at_20[0x18];
9399         u8         attenuation_5g[0x8];
9400
9401         u8         reserved_at_40[0x18];
9402         u8         attenuation_7g[0x8];
9403
9404         u8         reserved_at_60[0x18];
9405         u8         attenuation_12g[0x8];
9406 };
9407
9408 struct mlx5_ifc_pmpe_reg_bits {
9409         u8         reserved_at_0[0x8];
9410         u8         module[0x8];
9411         u8         reserved_at_10[0xc];
9412         u8         module_status[0x4];
9413
9414         u8         reserved_at_20[0x60];
9415 };
9416
9417 struct mlx5_ifc_pmpc_reg_bits {
9418         u8         module_state_updated[32][0x8];
9419 };
9420
9421 struct mlx5_ifc_pmlpn_reg_bits {
9422         u8         reserved_at_0[0x4];
9423         u8         mlpn_status[0x4];
9424         u8         local_port[0x8];
9425         u8         reserved_at_10[0x10];
9426
9427         u8         e[0x1];
9428         u8         reserved_at_21[0x1f];
9429 };
9430
9431 struct mlx5_ifc_pmlp_reg_bits {
9432         u8         rxtx[0x1];
9433         u8         reserved_at_1[0x7];
9434         u8         local_port[0x8];
9435         u8         reserved_at_10[0x8];
9436         u8         width[0x8];
9437
9438         u8         lane0_module_mapping[0x20];
9439
9440         u8         lane1_module_mapping[0x20];
9441
9442         u8         lane2_module_mapping[0x20];
9443
9444         u8         lane3_module_mapping[0x20];
9445
9446         u8         reserved_at_a0[0x160];
9447 };
9448
9449 struct mlx5_ifc_pmaos_reg_bits {
9450         u8         reserved_at_0[0x8];
9451         u8         module[0x8];
9452         u8         reserved_at_10[0x4];
9453         u8         admin_status[0x4];
9454         u8         reserved_at_18[0x4];
9455         u8         oper_status[0x4];
9456
9457         u8         ase[0x1];
9458         u8         ee[0x1];
9459         u8         reserved_at_22[0x1c];
9460         u8         e[0x2];
9461
9462         u8         reserved_at_40[0x40];
9463 };
9464
9465 struct mlx5_ifc_plpc_reg_bits {
9466         u8         reserved_at_0[0x4];
9467         u8         profile_id[0xc];
9468         u8         reserved_at_10[0x4];
9469         u8         proto_mask[0x4];
9470         u8         reserved_at_18[0x8];
9471
9472         u8         reserved_at_20[0x10];
9473         u8         lane_speed[0x10];
9474
9475         u8         reserved_at_40[0x17];
9476         u8         lpbf[0x1];
9477         u8         fec_mode_policy[0x8];
9478
9479         u8         retransmission_capability[0x8];
9480         u8         fec_mode_capability[0x18];
9481
9482         u8         retransmission_support_admin[0x8];
9483         u8         fec_mode_support_admin[0x18];
9484
9485         u8         retransmission_request_admin[0x8];
9486         u8         fec_mode_request_admin[0x18];
9487
9488         u8         reserved_at_c0[0x80];
9489 };
9490
9491 struct mlx5_ifc_plib_reg_bits {
9492         u8         reserved_at_0[0x8];
9493         u8         local_port[0x8];
9494         u8         reserved_at_10[0x8];
9495         u8         ib_port[0x8];
9496
9497         u8         reserved_at_20[0x60];
9498 };
9499
9500 struct mlx5_ifc_plbf_reg_bits {
9501         u8         reserved_at_0[0x8];
9502         u8         local_port[0x8];
9503         u8         reserved_at_10[0xd];
9504         u8         lbf_mode[0x3];
9505
9506         u8         reserved_at_20[0x20];
9507 };
9508
9509 struct mlx5_ifc_pipg_reg_bits {
9510         u8         reserved_at_0[0x8];
9511         u8         local_port[0x8];
9512         u8         reserved_at_10[0x10];
9513
9514         u8         dic[0x1];
9515         u8         reserved_at_21[0x19];
9516         u8         ipg[0x4];
9517         u8         reserved_at_3e[0x2];
9518 };
9519
9520 struct mlx5_ifc_pifr_reg_bits {
9521         u8         reserved_at_0[0x8];
9522         u8         local_port[0x8];
9523         u8         reserved_at_10[0x10];
9524
9525         u8         reserved_at_20[0xe0];
9526
9527         u8         port_filter[8][0x20];
9528
9529         u8         port_filter_update_en[8][0x20];
9530 };
9531
9532 struct mlx5_ifc_pfcc_reg_bits {
9533         u8         reserved_at_0[0x8];
9534         u8         local_port[0x8];
9535         u8         reserved_at_10[0xb];
9536         u8         ppan_mask_n[0x1];
9537         u8         minor_stall_mask[0x1];
9538         u8         critical_stall_mask[0x1];
9539         u8         reserved_at_1e[0x2];
9540
9541         u8         ppan[0x4];
9542         u8         reserved_at_24[0x4];
9543         u8         prio_mask_tx[0x8];
9544         u8         reserved_at_30[0x8];
9545         u8         prio_mask_rx[0x8];
9546
9547         u8         pptx[0x1];
9548         u8         aptx[0x1];
9549         u8         pptx_mask_n[0x1];
9550         u8         reserved_at_43[0x5];
9551         u8         pfctx[0x8];
9552         u8         reserved_at_50[0x10];
9553
9554         u8         pprx[0x1];
9555         u8         aprx[0x1];
9556         u8         pprx_mask_n[0x1];
9557         u8         reserved_at_63[0x5];
9558         u8         pfcrx[0x8];
9559         u8         reserved_at_70[0x10];
9560
9561         u8         device_stall_minor_watermark[0x10];
9562         u8         device_stall_critical_watermark[0x10];
9563
9564         u8         reserved_at_a0[0x60];
9565 };
9566
9567 struct mlx5_ifc_pelc_reg_bits {
9568         u8         op[0x4];
9569         u8         reserved_at_4[0x4];
9570         u8         local_port[0x8];
9571         u8         reserved_at_10[0x10];
9572
9573         u8         op_admin[0x8];
9574         u8         op_capability[0x8];
9575         u8         op_request[0x8];
9576         u8         op_active[0x8];
9577
9578         u8         admin[0x40];
9579
9580         u8         capability[0x40];
9581
9582         u8         request[0x40];
9583
9584         u8         active[0x40];
9585
9586         u8         reserved_at_140[0x80];
9587 };
9588
9589 struct mlx5_ifc_peir_reg_bits {
9590         u8         reserved_at_0[0x8];
9591         u8         local_port[0x8];
9592         u8         reserved_at_10[0x10];
9593
9594         u8         reserved_at_20[0xc];
9595         u8         error_count[0x4];
9596         u8         reserved_at_30[0x10];
9597
9598         u8         reserved_at_40[0xc];
9599         u8         lane[0x4];
9600         u8         reserved_at_50[0x8];
9601         u8         error_type[0x8];
9602 };
9603
9604 struct mlx5_ifc_mpegc_reg_bits {
9605         u8         reserved_at_0[0x30];
9606         u8         field_select[0x10];
9607
9608         u8         tx_overflow_sense[0x1];
9609         u8         mark_cqe[0x1];
9610         u8         mark_cnp[0x1];
9611         u8         reserved_at_43[0x1b];
9612         u8         tx_lossy_overflow_oper[0x2];
9613
9614         u8         reserved_at_60[0x100];
9615 };
9616
9617 enum {
9618         MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
9619         MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
9620         MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
9621 };
9622
9623 struct mlx5_ifc_mtutc_reg_bits {
9624         u8         reserved_at_0[0x1c];
9625         u8         operation[0x4];
9626
9627         u8         freq_adjustment[0x20];
9628
9629         u8         reserved_at_40[0x40];
9630
9631         u8         utc_sec[0x20];
9632
9633         u8         reserved_at_a0[0x2];
9634         u8         utc_nsec[0x1e];
9635
9636         u8         time_adjustment[0x20];
9637 };
9638
9639 struct mlx5_ifc_pcam_enhanced_features_bits {
9640         u8         reserved_at_0[0x68];
9641         u8         fec_50G_per_lane_in_pplm[0x1];
9642         u8         reserved_at_69[0x4];
9643         u8         rx_icrc_encapsulated_counter[0x1];
9644         u8         reserved_at_6e[0x4];
9645         u8         ptys_extended_ethernet[0x1];
9646         u8         reserved_at_73[0x3];
9647         u8         pfcc_mask[0x1];
9648         u8         reserved_at_77[0x3];
9649         u8         per_lane_error_counters[0x1];
9650         u8         rx_buffer_fullness_counters[0x1];
9651         u8         ptys_connector_type[0x1];
9652         u8         reserved_at_7d[0x1];
9653         u8         ppcnt_discard_group[0x1];
9654         u8         ppcnt_statistical_group[0x1];
9655 };
9656
9657 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9658         u8         port_access_reg_cap_mask_127_to_96[0x20];
9659         u8         port_access_reg_cap_mask_95_to_64[0x20];
9660
9661         u8         port_access_reg_cap_mask_63_to_36[0x1c];
9662         u8         pplm[0x1];
9663         u8         port_access_reg_cap_mask_34_to_32[0x3];
9664
9665         u8         port_access_reg_cap_mask_31_to_13[0x13];
9666         u8         pbmc[0x1];
9667         u8         pptb[0x1];
9668         u8         port_access_reg_cap_mask_10_to_09[0x2];
9669         u8         ppcnt[0x1];
9670         u8         port_access_reg_cap_mask_07_to_00[0x8];
9671 };
9672
9673 struct mlx5_ifc_pcam_reg_bits {
9674         u8         reserved_at_0[0x8];
9675         u8         feature_group[0x8];
9676         u8         reserved_at_10[0x8];
9677         u8         access_reg_group[0x8];
9678
9679         u8         reserved_at_20[0x20];
9680
9681         union {
9682                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9683                 u8         reserved_at_0[0x80];
9684         } port_access_reg_cap_mask;
9685
9686         u8         reserved_at_c0[0x80];
9687
9688         union {
9689                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9690                 u8         reserved_at_0[0x80];
9691         } feature_cap_mask;
9692
9693         u8         reserved_at_1c0[0xc0];
9694 };
9695
9696 struct mlx5_ifc_mcam_enhanced_features_bits {
9697         u8         reserved_at_0[0x5d];
9698         u8         mcia_32dwords[0x1];
9699         u8         reserved_at_5e[0xc];
9700         u8         reset_state[0x1];
9701         u8         ptpcyc2realtime_modify[0x1];
9702         u8         reserved_at_6c[0x2];
9703         u8         pci_status_and_power[0x1];
9704         u8         reserved_at_6f[0x5];
9705         u8         mark_tx_action_cnp[0x1];
9706         u8         mark_tx_action_cqe[0x1];
9707         u8         dynamic_tx_overflow[0x1];
9708         u8         reserved_at_77[0x4];
9709         u8         pcie_outbound_stalled[0x1];
9710         u8         tx_overflow_buffer_pkt[0x1];
9711         u8         mtpps_enh_out_per_adj[0x1];
9712         u8         mtpps_fs[0x1];
9713         u8         pcie_performance_group[0x1];
9714 };
9715
9716 struct mlx5_ifc_mcam_access_reg_bits {
9717         u8         reserved_at_0[0x1c];
9718         u8         mcda[0x1];
9719         u8         mcc[0x1];
9720         u8         mcqi[0x1];
9721         u8         mcqs[0x1];
9722
9723         u8         regs_95_to_87[0x9];
9724         u8         mpegc[0x1];
9725         u8         mtutc[0x1];
9726         u8         regs_84_to_68[0x11];
9727         u8         tracer_registers[0x4];
9728
9729         u8         regs_63_to_46[0x12];
9730         u8         mrtc[0x1];
9731         u8         regs_44_to_32[0xd];
9732
9733         u8         regs_31_to_0[0x20];
9734 };
9735
9736 struct mlx5_ifc_mcam_access_reg_bits1 {
9737         u8         regs_127_to_96[0x20];
9738
9739         u8         regs_95_to_64[0x20];
9740
9741         u8         regs_63_to_32[0x20];
9742
9743         u8         regs_31_to_0[0x20];
9744 };
9745
9746 struct mlx5_ifc_mcam_access_reg_bits2 {
9747         u8         regs_127_to_99[0x1d];
9748         u8         mirc[0x1];
9749         u8         regs_97_to_96[0x2];
9750
9751         u8         regs_95_to_64[0x20];
9752
9753         u8         regs_63_to_32[0x20];
9754
9755         u8         regs_31_to_0[0x20];
9756 };
9757
9758 struct mlx5_ifc_mcam_reg_bits {
9759         u8         reserved_at_0[0x8];
9760         u8         feature_group[0x8];
9761         u8         reserved_at_10[0x8];
9762         u8         access_reg_group[0x8];
9763
9764         u8         reserved_at_20[0x20];
9765
9766         union {
9767                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9768                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9769                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9770                 u8         reserved_at_0[0x80];
9771         } mng_access_reg_cap_mask;
9772
9773         u8         reserved_at_c0[0x80];
9774
9775         union {
9776                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9777                 u8         reserved_at_0[0x80];
9778         } mng_feature_cap_mask;
9779
9780         u8         reserved_at_1c0[0x80];
9781 };
9782
9783 struct mlx5_ifc_qcam_access_reg_cap_mask {
9784         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9785         u8         qpdpm[0x1];
9786         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9787         u8         qdpm[0x1];
9788         u8         qpts[0x1];
9789         u8         qcap[0x1];
9790         u8         qcam_access_reg_cap_mask_0[0x1];
9791 };
9792
9793 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9794         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9795         u8         qpts_trust_both[0x1];
9796 };
9797
9798 struct mlx5_ifc_qcam_reg_bits {
9799         u8         reserved_at_0[0x8];
9800         u8         feature_group[0x8];
9801         u8         reserved_at_10[0x8];
9802         u8         access_reg_group[0x8];
9803         u8         reserved_at_20[0x20];
9804
9805         union {
9806                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9807                 u8  reserved_at_0[0x80];
9808         } qos_access_reg_cap_mask;
9809
9810         u8         reserved_at_c0[0x80];
9811
9812         union {
9813                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9814                 u8  reserved_at_0[0x80];
9815         } qos_feature_cap_mask;
9816
9817         u8         reserved_at_1c0[0x80];
9818 };
9819
9820 struct mlx5_ifc_core_dump_reg_bits {
9821         u8         reserved_at_0[0x18];
9822         u8         core_dump_type[0x8];
9823
9824         u8         reserved_at_20[0x30];
9825         u8         vhca_id[0x10];
9826
9827         u8         reserved_at_60[0x8];
9828         u8         qpn[0x18];
9829         u8         reserved_at_80[0x180];
9830 };
9831
9832 struct mlx5_ifc_pcap_reg_bits {
9833         u8         reserved_at_0[0x8];
9834         u8         local_port[0x8];
9835         u8         reserved_at_10[0x10];
9836
9837         u8         port_capability_mask[4][0x20];
9838 };
9839
9840 struct mlx5_ifc_paos_reg_bits {
9841         u8         swid[0x8];
9842         u8         local_port[0x8];
9843         u8         reserved_at_10[0x4];
9844         u8         admin_status[0x4];
9845         u8         reserved_at_18[0x4];
9846         u8         oper_status[0x4];
9847
9848         u8         ase[0x1];
9849         u8         ee[0x1];
9850         u8         reserved_at_22[0x1c];
9851         u8         e[0x2];
9852
9853         u8         reserved_at_40[0x40];
9854 };
9855
9856 struct mlx5_ifc_pamp_reg_bits {
9857         u8         reserved_at_0[0x8];
9858         u8         opamp_group[0x8];
9859         u8         reserved_at_10[0xc];
9860         u8         opamp_group_type[0x4];
9861
9862         u8         start_index[0x10];
9863         u8         reserved_at_30[0x4];
9864         u8         num_of_indices[0xc];
9865
9866         u8         index_data[18][0x10];
9867 };
9868
9869 struct mlx5_ifc_pcmr_reg_bits {
9870         u8         reserved_at_0[0x8];
9871         u8         local_port[0x8];
9872         u8         reserved_at_10[0x10];
9873
9874         u8         entropy_force_cap[0x1];
9875         u8         entropy_calc_cap[0x1];
9876         u8         entropy_gre_calc_cap[0x1];
9877         u8         reserved_at_23[0xf];
9878         u8         rx_ts_over_crc_cap[0x1];
9879         u8         reserved_at_33[0xb];
9880         u8         fcs_cap[0x1];
9881         u8         reserved_at_3f[0x1];
9882
9883         u8         entropy_force[0x1];
9884         u8         entropy_calc[0x1];
9885         u8         entropy_gre_calc[0x1];
9886         u8         reserved_at_43[0xf];
9887         u8         rx_ts_over_crc[0x1];
9888         u8         reserved_at_53[0xb];
9889         u8         fcs_chk[0x1];
9890         u8         reserved_at_5f[0x1];
9891 };
9892
9893 struct mlx5_ifc_lane_2_module_mapping_bits {
9894         u8         reserved_at_0[0x4];
9895         u8         rx_lane[0x4];
9896         u8         reserved_at_8[0x4];
9897         u8         tx_lane[0x4];
9898         u8         reserved_at_10[0x8];
9899         u8         module[0x8];
9900 };
9901
9902 struct mlx5_ifc_bufferx_reg_bits {
9903         u8         reserved_at_0[0x6];
9904         u8         lossy[0x1];
9905         u8         epsb[0x1];
9906         u8         reserved_at_8[0x8];
9907         u8         size[0x10];
9908
9909         u8         xoff_threshold[0x10];
9910         u8         xon_threshold[0x10];
9911 };
9912
9913 struct mlx5_ifc_set_node_in_bits {
9914         u8         node_description[64][0x8];
9915 };
9916
9917 struct mlx5_ifc_register_power_settings_bits {
9918         u8         reserved_at_0[0x18];
9919         u8         power_settings_level[0x8];
9920
9921         u8         reserved_at_20[0x60];
9922 };
9923
9924 struct mlx5_ifc_register_host_endianness_bits {
9925         u8         he[0x1];
9926         u8         reserved_at_1[0x1f];
9927
9928         u8         reserved_at_20[0x60];
9929 };
9930
9931 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9932         u8         reserved_at_0[0x20];
9933
9934         u8         mkey[0x20];
9935
9936         u8         addressh_63_32[0x20];
9937
9938         u8         addressl_31_0[0x20];
9939 };
9940
9941 struct mlx5_ifc_ud_adrs_vector_bits {
9942         u8         dc_key[0x40];
9943
9944         u8         ext[0x1];
9945         u8         reserved_at_41[0x7];
9946         u8         destination_qp_dct[0x18];
9947
9948         u8         static_rate[0x4];
9949         u8         sl_eth_prio[0x4];
9950         u8         fl[0x1];
9951         u8         mlid[0x7];
9952         u8         rlid_udp_sport[0x10];
9953
9954         u8         reserved_at_80[0x20];
9955
9956         u8         rmac_47_16[0x20];
9957
9958         u8         rmac_15_0[0x10];
9959         u8         tclass[0x8];
9960         u8         hop_limit[0x8];
9961
9962         u8         reserved_at_e0[0x1];
9963         u8         grh[0x1];
9964         u8         reserved_at_e2[0x2];
9965         u8         src_addr_index[0x8];
9966         u8         flow_label[0x14];
9967
9968         u8         rgid_rip[16][0x8];
9969 };
9970
9971 struct mlx5_ifc_pages_req_event_bits {
9972         u8         reserved_at_0[0x10];
9973         u8         function_id[0x10];
9974
9975         u8         num_pages[0x20];
9976
9977         u8         reserved_at_40[0xa0];
9978 };
9979
9980 struct mlx5_ifc_eqe_bits {
9981         u8         reserved_at_0[0x8];
9982         u8         event_type[0x8];
9983         u8         reserved_at_10[0x8];
9984         u8         event_sub_type[0x8];
9985
9986         u8         reserved_at_20[0xe0];
9987
9988         union mlx5_ifc_event_auto_bits event_data;
9989
9990         u8         reserved_at_1e0[0x10];
9991         u8         signature[0x8];
9992         u8         reserved_at_1f8[0x7];
9993         u8         owner[0x1];
9994 };
9995
9996 enum {
9997         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9998 };
9999
10000 struct mlx5_ifc_cmd_queue_entry_bits {
10001         u8         type[0x8];
10002         u8         reserved_at_8[0x18];
10003
10004         u8         input_length[0x20];
10005
10006         u8         input_mailbox_pointer_63_32[0x20];
10007
10008         u8         input_mailbox_pointer_31_9[0x17];
10009         u8         reserved_at_77[0x9];
10010
10011         u8         command_input_inline_data[16][0x8];
10012
10013         u8         command_output_inline_data[16][0x8];
10014
10015         u8         output_mailbox_pointer_63_32[0x20];
10016
10017         u8         output_mailbox_pointer_31_9[0x17];
10018         u8         reserved_at_1b7[0x9];
10019
10020         u8         output_length[0x20];
10021
10022         u8         token[0x8];
10023         u8         signature[0x8];
10024         u8         reserved_at_1f0[0x8];
10025         u8         status[0x7];
10026         u8         ownership[0x1];
10027 };
10028
10029 struct mlx5_ifc_cmd_out_bits {
10030         u8         status[0x8];
10031         u8         reserved_at_8[0x18];
10032
10033         u8         syndrome[0x20];
10034
10035         u8         command_output[0x20];
10036 };
10037
10038 struct mlx5_ifc_cmd_in_bits {
10039         u8         opcode[0x10];
10040         u8         reserved_at_10[0x10];
10041
10042         u8         reserved_at_20[0x10];
10043         u8         op_mod[0x10];
10044
10045         u8         command[][0x20];
10046 };
10047
10048 struct mlx5_ifc_cmd_if_box_bits {
10049         u8         mailbox_data[512][0x8];
10050
10051         u8         reserved_at_1000[0x180];
10052
10053         u8         next_pointer_63_32[0x20];
10054
10055         u8         next_pointer_31_10[0x16];
10056         u8         reserved_at_11b6[0xa];
10057
10058         u8         block_number[0x20];
10059
10060         u8         reserved_at_11e0[0x8];
10061         u8         token[0x8];
10062         u8         ctrl_signature[0x8];
10063         u8         signature[0x8];
10064 };
10065
10066 struct mlx5_ifc_mtt_bits {
10067         u8         ptag_63_32[0x20];
10068
10069         u8         ptag_31_8[0x18];
10070         u8         reserved_at_38[0x6];
10071         u8         wr_en[0x1];
10072         u8         rd_en[0x1];
10073 };
10074
10075 struct mlx5_ifc_query_wol_rol_out_bits {
10076         u8         status[0x8];
10077         u8         reserved_at_8[0x18];
10078
10079         u8         syndrome[0x20];
10080
10081         u8         reserved_at_40[0x10];
10082         u8         rol_mode[0x8];
10083         u8         wol_mode[0x8];
10084
10085         u8         reserved_at_60[0x20];
10086 };
10087
10088 struct mlx5_ifc_query_wol_rol_in_bits {
10089         u8         opcode[0x10];
10090         u8         reserved_at_10[0x10];
10091
10092         u8         reserved_at_20[0x10];
10093         u8         op_mod[0x10];
10094
10095         u8         reserved_at_40[0x40];
10096 };
10097
10098 struct mlx5_ifc_set_wol_rol_out_bits {
10099         u8         status[0x8];
10100         u8         reserved_at_8[0x18];
10101
10102         u8         syndrome[0x20];
10103
10104         u8         reserved_at_40[0x40];
10105 };
10106
10107 struct mlx5_ifc_set_wol_rol_in_bits {
10108         u8         opcode[0x10];
10109         u8         reserved_at_10[0x10];
10110
10111         u8         reserved_at_20[0x10];
10112         u8         op_mod[0x10];
10113
10114         u8         rol_mode_valid[0x1];
10115         u8         wol_mode_valid[0x1];
10116         u8         reserved_at_42[0xe];
10117         u8         rol_mode[0x8];
10118         u8         wol_mode[0x8];
10119
10120         u8         reserved_at_60[0x20];
10121 };
10122
10123 enum {
10124         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10125         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10126         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10127 };
10128
10129 enum {
10130         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10131         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10132         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10133 };
10134
10135 enum {
10136         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
10137         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
10138         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
10139         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
10140         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
10141         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
10142         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
10143         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
10144         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
10145         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
10146         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
10147 };
10148
10149 struct mlx5_ifc_initial_seg_bits {
10150         u8         fw_rev_minor[0x10];
10151         u8         fw_rev_major[0x10];
10152
10153         u8         cmd_interface_rev[0x10];
10154         u8         fw_rev_subminor[0x10];
10155
10156         u8         reserved_at_40[0x40];
10157
10158         u8         cmdq_phy_addr_63_32[0x20];
10159
10160         u8         cmdq_phy_addr_31_12[0x14];
10161         u8         reserved_at_b4[0x2];
10162         u8         nic_interface[0x2];
10163         u8         log_cmdq_size[0x4];
10164         u8         log_cmdq_stride[0x4];
10165
10166         u8         command_doorbell_vector[0x20];
10167
10168         u8         reserved_at_e0[0xf00];
10169
10170         u8         initializing[0x1];
10171         u8         reserved_at_fe1[0x4];
10172         u8         nic_interface_supported[0x3];
10173         u8         embedded_cpu[0x1];
10174         u8         reserved_at_fe9[0x17];
10175
10176         struct mlx5_ifc_health_buffer_bits health_buffer;
10177
10178         u8         no_dram_nic_offset[0x20];
10179
10180         u8         reserved_at_1220[0x6e40];
10181
10182         u8         reserved_at_8060[0x1f];
10183         u8         clear_int[0x1];
10184
10185         u8         health_syndrome[0x8];
10186         u8         health_counter[0x18];
10187
10188         u8         reserved_at_80a0[0x17fc0];
10189 };
10190
10191 struct mlx5_ifc_mtpps_reg_bits {
10192         u8         reserved_at_0[0xc];
10193         u8         cap_number_of_pps_pins[0x4];
10194         u8         reserved_at_10[0x4];
10195         u8         cap_max_num_of_pps_in_pins[0x4];
10196         u8         reserved_at_18[0x4];
10197         u8         cap_max_num_of_pps_out_pins[0x4];
10198
10199         u8         reserved_at_20[0x24];
10200         u8         cap_pin_3_mode[0x4];
10201         u8         reserved_at_48[0x4];
10202         u8         cap_pin_2_mode[0x4];
10203         u8         reserved_at_50[0x4];
10204         u8         cap_pin_1_mode[0x4];
10205         u8         reserved_at_58[0x4];
10206         u8         cap_pin_0_mode[0x4];
10207
10208         u8         reserved_at_60[0x4];
10209         u8         cap_pin_7_mode[0x4];
10210         u8         reserved_at_68[0x4];
10211         u8         cap_pin_6_mode[0x4];
10212         u8         reserved_at_70[0x4];
10213         u8         cap_pin_5_mode[0x4];
10214         u8         reserved_at_78[0x4];
10215         u8         cap_pin_4_mode[0x4];
10216
10217         u8         field_select[0x20];
10218         u8         reserved_at_a0[0x60];
10219
10220         u8         enable[0x1];
10221         u8         reserved_at_101[0xb];
10222         u8         pattern[0x4];
10223         u8         reserved_at_110[0x4];
10224         u8         pin_mode[0x4];
10225         u8         pin[0x8];
10226
10227         u8         reserved_at_120[0x20];
10228
10229         u8         time_stamp[0x40];
10230
10231         u8         out_pulse_duration[0x10];
10232         u8         out_periodic_adjustment[0x10];
10233         u8         enhanced_out_periodic_adjustment[0x20];
10234
10235         u8         reserved_at_1c0[0x20];
10236 };
10237
10238 struct mlx5_ifc_mtppse_reg_bits {
10239         u8         reserved_at_0[0x18];
10240         u8         pin[0x8];
10241         u8         event_arm[0x1];
10242         u8         reserved_at_21[0x1b];
10243         u8         event_generation_mode[0x4];
10244         u8         reserved_at_40[0x40];
10245 };
10246
10247 struct mlx5_ifc_mcqs_reg_bits {
10248         u8         last_index_flag[0x1];
10249         u8         reserved_at_1[0x7];
10250         u8         fw_device[0x8];
10251         u8         component_index[0x10];
10252
10253         u8         reserved_at_20[0x10];
10254         u8         identifier[0x10];
10255
10256         u8         reserved_at_40[0x17];
10257         u8         component_status[0x5];
10258         u8         component_update_state[0x4];
10259
10260         u8         last_update_state_changer_type[0x4];
10261         u8         last_update_state_changer_host_id[0x4];
10262         u8         reserved_at_68[0x18];
10263 };
10264
10265 struct mlx5_ifc_mcqi_cap_bits {
10266         u8         supported_info_bitmask[0x20];
10267
10268         u8         component_size[0x20];
10269
10270         u8         max_component_size[0x20];
10271
10272         u8         log_mcda_word_size[0x4];
10273         u8         reserved_at_64[0xc];
10274         u8         mcda_max_write_size[0x10];
10275
10276         u8         rd_en[0x1];
10277         u8         reserved_at_81[0x1];
10278         u8         match_chip_id[0x1];
10279         u8         match_psid[0x1];
10280         u8         check_user_timestamp[0x1];
10281         u8         match_base_guid_mac[0x1];
10282         u8         reserved_at_86[0x1a];
10283 };
10284
10285 struct mlx5_ifc_mcqi_version_bits {
10286         u8         reserved_at_0[0x2];
10287         u8         build_time_valid[0x1];
10288         u8         user_defined_time_valid[0x1];
10289         u8         reserved_at_4[0x14];
10290         u8         version_string_length[0x8];
10291
10292         u8         version[0x20];
10293
10294         u8         build_time[0x40];
10295
10296         u8         user_defined_time[0x40];
10297
10298         u8         build_tool_version[0x20];
10299
10300         u8         reserved_at_e0[0x20];
10301
10302         u8         version_string[92][0x8];
10303 };
10304
10305 struct mlx5_ifc_mcqi_activation_method_bits {
10306         u8         pending_server_ac_power_cycle[0x1];
10307         u8         pending_server_dc_power_cycle[0x1];
10308         u8         pending_server_reboot[0x1];
10309         u8         pending_fw_reset[0x1];
10310         u8         auto_activate[0x1];
10311         u8         all_hosts_sync[0x1];
10312         u8         device_hw_reset[0x1];
10313         u8         reserved_at_7[0x19];
10314 };
10315
10316 union mlx5_ifc_mcqi_reg_data_bits {
10317         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
10318         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
10319         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10320 };
10321
10322 struct mlx5_ifc_mcqi_reg_bits {
10323         u8         read_pending_component[0x1];
10324         u8         reserved_at_1[0xf];
10325         u8         component_index[0x10];
10326
10327         u8         reserved_at_20[0x20];
10328
10329         u8         reserved_at_40[0x1b];
10330         u8         info_type[0x5];
10331
10332         u8         info_size[0x20];
10333
10334         u8         offset[0x20];
10335
10336         u8         reserved_at_a0[0x10];
10337         u8         data_size[0x10];
10338
10339         union mlx5_ifc_mcqi_reg_data_bits data[];
10340 };
10341
10342 struct mlx5_ifc_mcc_reg_bits {
10343         u8         reserved_at_0[0x4];
10344         u8         time_elapsed_since_last_cmd[0xc];
10345         u8         reserved_at_10[0x8];
10346         u8         instruction[0x8];
10347
10348         u8         reserved_at_20[0x10];
10349         u8         component_index[0x10];
10350
10351         u8         reserved_at_40[0x8];
10352         u8         update_handle[0x18];
10353
10354         u8         handle_owner_type[0x4];
10355         u8         handle_owner_host_id[0x4];
10356         u8         reserved_at_68[0x1];
10357         u8         control_progress[0x7];
10358         u8         error_code[0x8];
10359         u8         reserved_at_78[0x4];
10360         u8         control_state[0x4];
10361
10362         u8         component_size[0x20];
10363
10364         u8         reserved_at_a0[0x60];
10365 };
10366
10367 struct mlx5_ifc_mcda_reg_bits {
10368         u8         reserved_at_0[0x8];
10369         u8         update_handle[0x18];
10370
10371         u8         offset[0x20];
10372
10373         u8         reserved_at_40[0x10];
10374         u8         size[0x10];
10375
10376         u8         reserved_at_60[0x20];
10377
10378         u8         data[][0x20];
10379 };
10380
10381 enum {
10382         MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10383         MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10384         MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10385         MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3,
10386         MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10387 };
10388
10389 enum {
10390         MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10391         MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10392 };
10393
10394 enum {
10395         MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10396         MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10397         MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10398 };
10399
10400 struct mlx5_ifc_mfrl_reg_bits {
10401         u8         reserved_at_0[0x20];
10402
10403         u8         reserved_at_20[0x2];
10404         u8         pci_sync_for_fw_update_start[0x1];
10405         u8         pci_sync_for_fw_update_resp[0x2];
10406         u8         rst_type_sel[0x3];
10407         u8         reserved_at_28[0x4];
10408         u8         reset_state[0x4];
10409         u8         reset_type[0x8];
10410         u8         reset_level[0x8];
10411 };
10412
10413 struct mlx5_ifc_mirc_reg_bits {
10414         u8         reserved_at_0[0x18];
10415         u8         status_code[0x8];
10416
10417         u8         reserved_at_20[0x20];
10418 };
10419
10420 struct mlx5_ifc_pddr_monitor_opcode_bits {
10421         u8         reserved_at_0[0x10];
10422         u8         monitor_opcode[0x10];
10423 };
10424
10425 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10426         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10427         u8         reserved_at_0[0x20];
10428 };
10429
10430 enum {
10431         /* Monitor opcodes */
10432         MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10433 };
10434
10435 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10436         u8         reserved_at_0[0x10];
10437         u8         group_opcode[0x10];
10438
10439         union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10440
10441         u8         reserved_at_40[0x20];
10442
10443         u8         status_message[59][0x20];
10444 };
10445
10446 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10447         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10448         u8         reserved_at_0[0x7c0];
10449 };
10450
10451 enum {
10452         MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10453 };
10454
10455 struct mlx5_ifc_pddr_reg_bits {
10456         u8         reserved_at_0[0x8];
10457         u8         local_port[0x8];
10458         u8         pnat[0x2];
10459         u8         reserved_at_12[0xe];
10460
10461         u8         reserved_at_20[0x18];
10462         u8         page_select[0x8];
10463
10464         union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10465 };
10466
10467 struct mlx5_ifc_mrtc_reg_bits {
10468         u8         time_synced[0x1];
10469         u8         reserved_at_1[0x1f];
10470
10471         u8         reserved_at_20[0x20];
10472
10473         u8         time_h[0x20];
10474
10475         u8         time_l[0x20];
10476 };
10477
10478 union mlx5_ifc_ports_control_registers_document_bits {
10479         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10480         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10481         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10482         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10483         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10484         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10485         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10486         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10487         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10488         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10489         struct mlx5_ifc_pamp_reg_bits pamp_reg;
10490         struct mlx5_ifc_paos_reg_bits paos_reg;
10491         struct mlx5_ifc_pcap_reg_bits pcap_reg;
10492         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10493         struct mlx5_ifc_pddr_reg_bits pddr_reg;
10494         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10495         struct mlx5_ifc_peir_reg_bits peir_reg;
10496         struct mlx5_ifc_pelc_reg_bits pelc_reg;
10497         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10498         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10499         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10500         struct mlx5_ifc_pifr_reg_bits pifr_reg;
10501         struct mlx5_ifc_pipg_reg_bits pipg_reg;
10502         struct mlx5_ifc_plbf_reg_bits plbf_reg;
10503         struct mlx5_ifc_plib_reg_bits plib_reg;
10504         struct mlx5_ifc_plpc_reg_bits plpc_reg;
10505         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10506         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10507         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10508         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10509         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10510         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10511         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10512         struct mlx5_ifc_ppad_reg_bits ppad_reg;
10513         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10514         struct mlx5_ifc_mpein_reg_bits mpein_reg;
10515         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10516         struct mlx5_ifc_pplm_reg_bits pplm_reg;
10517         struct mlx5_ifc_pplr_reg_bits pplr_reg;
10518         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10519         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10520         struct mlx5_ifc_pspa_reg_bits pspa_reg;
10521         struct mlx5_ifc_ptas_reg_bits ptas_reg;
10522         struct mlx5_ifc_ptys_reg_bits ptys_reg;
10523         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10524         struct mlx5_ifc_pude_reg_bits pude_reg;
10525         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10526         struct mlx5_ifc_slrg_reg_bits slrg_reg;
10527         struct mlx5_ifc_sltp_reg_bits sltp_reg;
10528         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10529         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
10530         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
10531         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10532         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
10533         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10534         struct mlx5_ifc_mcc_reg_bits mcc_reg;
10535         struct mlx5_ifc_mcda_reg_bits mcda_reg;
10536         struct mlx5_ifc_mirc_reg_bits mirc_reg;
10537         struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
10538         struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
10539         struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
10540         u8         reserved_at_0[0x60e0];
10541 };
10542
10543 union mlx5_ifc_debug_enhancements_document_bits {
10544         struct mlx5_ifc_health_buffer_bits health_buffer;
10545         u8         reserved_at_0[0x200];
10546 };
10547
10548 union mlx5_ifc_uplink_pci_interface_document_bits {
10549         struct mlx5_ifc_initial_seg_bits initial_seg;
10550         u8         reserved_at_0[0x20060];
10551 };
10552
10553 struct mlx5_ifc_set_flow_table_root_out_bits {
10554         u8         status[0x8];
10555         u8         reserved_at_8[0x18];
10556
10557         u8         syndrome[0x20];
10558
10559         u8         reserved_at_40[0x40];
10560 };
10561
10562 struct mlx5_ifc_set_flow_table_root_in_bits {
10563         u8         opcode[0x10];
10564         u8         reserved_at_10[0x10];
10565
10566         u8         reserved_at_20[0x10];
10567         u8         op_mod[0x10];
10568
10569         u8         other_vport[0x1];
10570         u8         reserved_at_41[0xf];
10571         u8         vport_number[0x10];
10572
10573         u8         reserved_at_60[0x20];
10574
10575         u8         table_type[0x8];
10576         u8         reserved_at_88[0x7];
10577         u8         table_of_other_vport[0x1];
10578         u8         table_vport_number[0x10];
10579
10580         u8         reserved_at_a0[0x8];
10581         u8         table_id[0x18];
10582
10583         u8         reserved_at_c0[0x8];
10584         u8         underlay_qpn[0x18];
10585         u8         table_eswitch_owner_vhca_id_valid[0x1];
10586         u8         reserved_at_e1[0xf];
10587         u8         table_eswitch_owner_vhca_id[0x10];
10588         u8         reserved_at_100[0x100];
10589 };
10590
10591 enum {
10592         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
10593         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
10594 };
10595
10596 struct mlx5_ifc_modify_flow_table_out_bits {
10597         u8         status[0x8];
10598         u8         reserved_at_8[0x18];
10599
10600         u8         syndrome[0x20];
10601
10602         u8         reserved_at_40[0x40];
10603 };
10604
10605 struct mlx5_ifc_modify_flow_table_in_bits {
10606         u8         opcode[0x10];
10607         u8         reserved_at_10[0x10];
10608
10609         u8         reserved_at_20[0x10];
10610         u8         op_mod[0x10];
10611
10612         u8         other_vport[0x1];
10613         u8         reserved_at_41[0xf];
10614         u8         vport_number[0x10];
10615
10616         u8         reserved_at_60[0x10];
10617         u8         modify_field_select[0x10];
10618
10619         u8         table_type[0x8];
10620         u8         reserved_at_88[0x18];
10621
10622         u8         reserved_at_a0[0x8];
10623         u8         table_id[0x18];
10624
10625         struct mlx5_ifc_flow_table_context_bits flow_table_context;
10626 };
10627
10628 struct mlx5_ifc_ets_tcn_config_reg_bits {
10629         u8         g[0x1];
10630         u8         b[0x1];
10631         u8         r[0x1];
10632         u8         reserved_at_3[0x9];
10633         u8         group[0x4];
10634         u8         reserved_at_10[0x9];
10635         u8         bw_allocation[0x7];
10636
10637         u8         reserved_at_20[0xc];
10638         u8         max_bw_units[0x4];
10639         u8         reserved_at_30[0x8];
10640         u8         max_bw_value[0x8];
10641 };
10642
10643 struct mlx5_ifc_ets_global_config_reg_bits {
10644         u8         reserved_at_0[0x2];
10645         u8         r[0x1];
10646         u8         reserved_at_3[0x1d];
10647
10648         u8         reserved_at_20[0xc];
10649         u8         max_bw_units[0x4];
10650         u8         reserved_at_30[0x8];
10651         u8         max_bw_value[0x8];
10652 };
10653
10654 struct mlx5_ifc_qetc_reg_bits {
10655         u8                                         reserved_at_0[0x8];
10656         u8                                         port_number[0x8];
10657         u8                                         reserved_at_10[0x30];
10658
10659         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
10660         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10661 };
10662
10663 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10664         u8         e[0x1];
10665         u8         reserved_at_01[0x0b];
10666         u8         prio[0x04];
10667 };
10668
10669 struct mlx5_ifc_qpdpm_reg_bits {
10670         u8                                     reserved_at_0[0x8];
10671         u8                                     local_port[0x8];
10672         u8                                     reserved_at_10[0x10];
10673         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10674 };
10675
10676 struct mlx5_ifc_qpts_reg_bits {
10677         u8         reserved_at_0[0x8];
10678         u8         local_port[0x8];
10679         u8         reserved_at_10[0x2d];
10680         u8         trust_state[0x3];
10681 };
10682
10683 struct mlx5_ifc_pptb_reg_bits {
10684         u8         reserved_at_0[0x2];
10685         u8         mm[0x2];
10686         u8         reserved_at_4[0x4];
10687         u8         local_port[0x8];
10688         u8         reserved_at_10[0x6];
10689         u8         cm[0x1];
10690         u8         um[0x1];
10691         u8         pm[0x8];
10692
10693         u8         prio_x_buff[0x20];
10694
10695         u8         pm_msb[0x8];
10696         u8         reserved_at_48[0x10];
10697         u8         ctrl_buff[0x4];
10698         u8         untagged_buff[0x4];
10699 };
10700
10701 struct mlx5_ifc_sbcam_reg_bits {
10702         u8         reserved_at_0[0x8];
10703         u8         feature_group[0x8];
10704         u8         reserved_at_10[0x8];
10705         u8         access_reg_group[0x8];
10706
10707         u8         reserved_at_20[0x20];
10708
10709         u8         sb_access_reg_cap_mask[4][0x20];
10710
10711         u8         reserved_at_c0[0x80];
10712
10713         u8         sb_feature_cap_mask[4][0x20];
10714
10715         u8         reserved_at_1c0[0x40];
10716
10717         u8         cap_total_buffer_size[0x20];
10718
10719         u8         cap_cell_size[0x10];
10720         u8         cap_max_pg_buffers[0x8];
10721         u8         cap_num_pool_supported[0x8];
10722
10723         u8         reserved_at_240[0x8];
10724         u8         cap_sbsr_stat_size[0x8];
10725         u8         cap_max_tclass_data[0x8];
10726         u8         cap_max_cpu_ingress_tclass_sb[0x8];
10727 };
10728
10729 struct mlx5_ifc_pbmc_reg_bits {
10730         u8         reserved_at_0[0x8];
10731         u8         local_port[0x8];
10732         u8         reserved_at_10[0x10];
10733
10734         u8         xoff_timer_value[0x10];
10735         u8         xoff_refresh[0x10];
10736
10737         u8         reserved_at_40[0x9];
10738         u8         fullness_threshold[0x7];
10739         u8         port_buffer_size[0x10];
10740
10741         struct mlx5_ifc_bufferx_reg_bits buffer[10];
10742
10743         u8         reserved_at_2e0[0x80];
10744 };
10745
10746 struct mlx5_ifc_qtct_reg_bits {
10747         u8         reserved_at_0[0x8];
10748         u8         port_number[0x8];
10749         u8         reserved_at_10[0xd];
10750         u8         prio[0x3];
10751
10752         u8         reserved_at_20[0x1d];
10753         u8         tclass[0x3];
10754 };
10755
10756 struct mlx5_ifc_mcia_reg_bits {
10757         u8         l[0x1];
10758         u8         reserved_at_1[0x7];
10759         u8         module[0x8];
10760         u8         reserved_at_10[0x8];
10761         u8         status[0x8];
10762
10763         u8         i2c_device_address[0x8];
10764         u8         page_number[0x8];
10765         u8         device_address[0x10];
10766
10767         u8         reserved_at_40[0x10];
10768         u8         size[0x10];
10769
10770         u8         reserved_at_60[0x20];
10771
10772         u8         dword_0[0x20];
10773         u8         dword_1[0x20];
10774         u8         dword_2[0x20];
10775         u8         dword_3[0x20];
10776         u8         dword_4[0x20];
10777         u8         dword_5[0x20];
10778         u8         dword_6[0x20];
10779         u8         dword_7[0x20];
10780         u8         dword_8[0x20];
10781         u8         dword_9[0x20];
10782         u8         dword_10[0x20];
10783         u8         dword_11[0x20];
10784 };
10785
10786 struct mlx5_ifc_dcbx_param_bits {
10787         u8         dcbx_cee_cap[0x1];
10788         u8         dcbx_ieee_cap[0x1];
10789         u8         dcbx_standby_cap[0x1];
10790         u8         reserved_at_3[0x5];
10791         u8         port_number[0x8];
10792         u8         reserved_at_10[0xa];
10793         u8         max_application_table_size[6];
10794         u8         reserved_at_20[0x15];
10795         u8         version_oper[0x3];
10796         u8         reserved_at_38[5];
10797         u8         version_admin[0x3];
10798         u8         willing_admin[0x1];
10799         u8         reserved_at_41[0x3];
10800         u8         pfc_cap_oper[0x4];
10801         u8         reserved_at_48[0x4];
10802         u8         pfc_cap_admin[0x4];
10803         u8         reserved_at_50[0x4];
10804         u8         num_of_tc_oper[0x4];
10805         u8         reserved_at_58[0x4];
10806         u8         num_of_tc_admin[0x4];
10807         u8         remote_willing[0x1];
10808         u8         reserved_at_61[3];
10809         u8         remote_pfc_cap[4];
10810         u8         reserved_at_68[0x14];
10811         u8         remote_num_of_tc[0x4];
10812         u8         reserved_at_80[0x18];
10813         u8         error[0x8];
10814         u8         reserved_at_a0[0x160];
10815 };
10816
10817 enum {
10818         MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
10819         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
10820         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
10821 };
10822
10823 struct mlx5_ifc_lagc_bits {
10824         u8         fdb_selection_mode[0x1];
10825         u8         reserved_at_1[0x14];
10826         u8         port_select_mode[0x3];
10827         u8         reserved_at_18[0x5];
10828         u8         lag_state[0x3];
10829
10830         u8         reserved_at_20[0x14];
10831         u8         tx_remap_affinity_2[0x4];
10832         u8         reserved_at_38[0x4];
10833         u8         tx_remap_affinity_1[0x4];
10834 };
10835
10836 struct mlx5_ifc_create_lag_out_bits {
10837         u8         status[0x8];
10838         u8         reserved_at_8[0x18];
10839
10840         u8         syndrome[0x20];
10841
10842         u8         reserved_at_40[0x40];
10843 };
10844
10845 struct mlx5_ifc_create_lag_in_bits {
10846         u8         opcode[0x10];
10847         u8         reserved_at_10[0x10];
10848
10849         u8         reserved_at_20[0x10];
10850         u8         op_mod[0x10];
10851
10852         struct mlx5_ifc_lagc_bits ctx;
10853 };
10854
10855 struct mlx5_ifc_modify_lag_out_bits {
10856         u8         status[0x8];
10857         u8         reserved_at_8[0x18];
10858
10859         u8         syndrome[0x20];
10860
10861         u8         reserved_at_40[0x40];
10862 };
10863
10864 struct mlx5_ifc_modify_lag_in_bits {
10865         u8         opcode[0x10];
10866         u8         reserved_at_10[0x10];
10867
10868         u8         reserved_at_20[0x10];
10869         u8         op_mod[0x10];
10870
10871         u8         reserved_at_40[0x20];
10872         u8         field_select[0x20];
10873
10874         struct mlx5_ifc_lagc_bits ctx;
10875 };
10876
10877 struct mlx5_ifc_query_lag_out_bits {
10878         u8         status[0x8];
10879         u8         reserved_at_8[0x18];
10880
10881         u8         syndrome[0x20];
10882
10883         struct mlx5_ifc_lagc_bits ctx;
10884 };
10885
10886 struct mlx5_ifc_query_lag_in_bits {
10887         u8         opcode[0x10];
10888         u8         reserved_at_10[0x10];
10889
10890         u8         reserved_at_20[0x10];
10891         u8         op_mod[0x10];
10892
10893         u8         reserved_at_40[0x40];
10894 };
10895
10896 struct mlx5_ifc_destroy_lag_out_bits {
10897         u8         status[0x8];
10898         u8         reserved_at_8[0x18];
10899
10900         u8         syndrome[0x20];
10901
10902         u8         reserved_at_40[0x40];
10903 };
10904
10905 struct mlx5_ifc_destroy_lag_in_bits {
10906         u8         opcode[0x10];
10907         u8         reserved_at_10[0x10];
10908
10909         u8         reserved_at_20[0x10];
10910         u8         op_mod[0x10];
10911
10912         u8         reserved_at_40[0x40];
10913 };
10914
10915 struct mlx5_ifc_create_vport_lag_out_bits {
10916         u8         status[0x8];
10917         u8         reserved_at_8[0x18];
10918
10919         u8         syndrome[0x20];
10920
10921         u8         reserved_at_40[0x40];
10922 };
10923
10924 struct mlx5_ifc_create_vport_lag_in_bits {
10925         u8         opcode[0x10];
10926         u8         reserved_at_10[0x10];
10927
10928         u8         reserved_at_20[0x10];
10929         u8         op_mod[0x10];
10930
10931         u8         reserved_at_40[0x40];
10932 };
10933
10934 struct mlx5_ifc_destroy_vport_lag_out_bits {
10935         u8         status[0x8];
10936         u8         reserved_at_8[0x18];
10937
10938         u8         syndrome[0x20];
10939
10940         u8         reserved_at_40[0x40];
10941 };
10942
10943 struct mlx5_ifc_destroy_vport_lag_in_bits {
10944         u8         opcode[0x10];
10945         u8         reserved_at_10[0x10];
10946
10947         u8         reserved_at_20[0x10];
10948         u8         op_mod[0x10];
10949
10950         u8         reserved_at_40[0x40];
10951 };
10952
10953 enum {
10954         MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
10955         MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
10956 };
10957
10958 struct mlx5_ifc_modify_memic_in_bits {
10959         u8         opcode[0x10];
10960         u8         uid[0x10];
10961
10962         u8         reserved_at_20[0x10];
10963         u8         op_mod[0x10];
10964
10965         u8         reserved_at_40[0x20];
10966
10967         u8         reserved_at_60[0x18];
10968         u8         memic_operation_type[0x8];
10969
10970         u8         memic_start_addr[0x40];
10971
10972         u8         reserved_at_c0[0x140];
10973 };
10974
10975 struct mlx5_ifc_modify_memic_out_bits {
10976         u8         status[0x8];
10977         u8         reserved_at_8[0x18];
10978
10979         u8         syndrome[0x20];
10980
10981         u8         reserved_at_40[0x40];
10982
10983         u8         memic_operation_addr[0x40];
10984
10985         u8         reserved_at_c0[0x140];
10986 };
10987
10988 struct mlx5_ifc_alloc_memic_in_bits {
10989         u8         opcode[0x10];
10990         u8         reserved_at_10[0x10];
10991
10992         u8         reserved_at_20[0x10];
10993         u8         op_mod[0x10];
10994
10995         u8         reserved_at_30[0x20];
10996
10997         u8         reserved_at_40[0x18];
10998         u8         log_memic_addr_alignment[0x8];
10999
11000         u8         range_start_addr[0x40];
11001
11002         u8         range_size[0x20];
11003
11004         u8         memic_size[0x20];
11005 };
11006
11007 struct mlx5_ifc_alloc_memic_out_bits {
11008         u8         status[0x8];
11009         u8         reserved_at_8[0x18];
11010
11011         u8         syndrome[0x20];
11012
11013         u8         memic_start_addr[0x40];
11014 };
11015
11016 struct mlx5_ifc_dealloc_memic_in_bits {
11017         u8         opcode[0x10];
11018         u8         reserved_at_10[0x10];
11019
11020         u8         reserved_at_20[0x10];
11021         u8         op_mod[0x10];
11022
11023         u8         reserved_at_40[0x40];
11024
11025         u8         memic_start_addr[0x40];
11026
11027         u8         memic_size[0x20];
11028
11029         u8         reserved_at_e0[0x20];
11030 };
11031
11032 struct mlx5_ifc_dealloc_memic_out_bits {
11033         u8         status[0x8];
11034         u8         reserved_at_8[0x18];
11035
11036         u8         syndrome[0x20];
11037
11038         u8         reserved_at_40[0x40];
11039 };
11040
11041 struct mlx5_ifc_umem_bits {
11042         u8         reserved_at_0[0x80];
11043
11044         u8         reserved_at_80[0x1b];
11045         u8         log_page_size[0x5];
11046
11047         u8         page_offset[0x20];
11048
11049         u8         num_of_mtt[0x40];
11050
11051         struct mlx5_ifc_mtt_bits  mtt[];
11052 };
11053
11054 struct mlx5_ifc_uctx_bits {
11055         u8         cap[0x20];
11056
11057         u8         reserved_at_20[0x160];
11058 };
11059
11060 struct mlx5_ifc_sw_icm_bits {
11061         u8         modify_field_select[0x40];
11062
11063         u8         reserved_at_40[0x18];
11064         u8         log_sw_icm_size[0x8];
11065
11066         u8         reserved_at_60[0x20];
11067
11068         u8         sw_icm_start_addr[0x40];
11069
11070         u8         reserved_at_c0[0x140];
11071 };
11072
11073 struct mlx5_ifc_geneve_tlv_option_bits {
11074         u8         modify_field_select[0x40];
11075
11076         u8         reserved_at_40[0x18];
11077         u8         geneve_option_fte_index[0x8];
11078
11079         u8         option_class[0x10];
11080         u8         option_type[0x8];
11081         u8         reserved_at_78[0x3];
11082         u8         option_data_length[0x5];
11083
11084         u8         reserved_at_80[0x180];
11085 };
11086
11087 struct mlx5_ifc_create_umem_in_bits {
11088         u8         opcode[0x10];
11089         u8         uid[0x10];
11090
11091         u8         reserved_at_20[0x10];
11092         u8         op_mod[0x10];
11093
11094         u8         reserved_at_40[0x40];
11095
11096         struct mlx5_ifc_umem_bits  umem;
11097 };
11098
11099 struct mlx5_ifc_create_umem_out_bits {
11100         u8         status[0x8];
11101         u8         reserved_at_8[0x18];
11102
11103         u8         syndrome[0x20];
11104
11105         u8         reserved_at_40[0x8];
11106         u8         umem_id[0x18];
11107
11108         u8         reserved_at_60[0x20];
11109 };
11110
11111 struct mlx5_ifc_destroy_umem_in_bits {
11112         u8        opcode[0x10];
11113         u8        uid[0x10];
11114
11115         u8        reserved_at_20[0x10];
11116         u8        op_mod[0x10];
11117
11118         u8        reserved_at_40[0x8];
11119         u8        umem_id[0x18];
11120
11121         u8        reserved_at_60[0x20];
11122 };
11123
11124 struct mlx5_ifc_destroy_umem_out_bits {
11125         u8        status[0x8];
11126         u8        reserved_at_8[0x18];
11127
11128         u8        syndrome[0x20];
11129
11130         u8        reserved_at_40[0x40];
11131 };
11132
11133 struct mlx5_ifc_create_uctx_in_bits {
11134         u8         opcode[0x10];
11135         u8         reserved_at_10[0x10];
11136
11137         u8         reserved_at_20[0x10];
11138         u8         op_mod[0x10];
11139
11140         u8         reserved_at_40[0x40];
11141
11142         struct mlx5_ifc_uctx_bits  uctx;
11143 };
11144
11145 struct mlx5_ifc_create_uctx_out_bits {
11146         u8         status[0x8];
11147         u8         reserved_at_8[0x18];
11148
11149         u8         syndrome[0x20];
11150
11151         u8         reserved_at_40[0x10];
11152         u8         uid[0x10];
11153
11154         u8         reserved_at_60[0x20];
11155 };
11156
11157 struct mlx5_ifc_destroy_uctx_in_bits {
11158         u8         opcode[0x10];
11159         u8         reserved_at_10[0x10];
11160
11161         u8         reserved_at_20[0x10];
11162         u8         op_mod[0x10];
11163
11164         u8         reserved_at_40[0x10];
11165         u8         uid[0x10];
11166
11167         u8         reserved_at_60[0x20];
11168 };
11169
11170 struct mlx5_ifc_destroy_uctx_out_bits {
11171         u8         status[0x8];
11172         u8         reserved_at_8[0x18];
11173
11174         u8         syndrome[0x20];
11175
11176         u8          reserved_at_40[0x40];
11177 };
11178
11179 struct mlx5_ifc_create_sw_icm_in_bits {
11180         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11181         struct mlx5_ifc_sw_icm_bits                   sw_icm;
11182 };
11183
11184 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11185         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11186         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
11187 };
11188
11189 struct mlx5_ifc_mtrc_string_db_param_bits {
11190         u8         string_db_base_address[0x20];
11191
11192         u8         reserved_at_20[0x8];
11193         u8         string_db_size[0x18];
11194 };
11195
11196 struct mlx5_ifc_mtrc_cap_bits {
11197         u8         trace_owner[0x1];
11198         u8         trace_to_memory[0x1];
11199         u8         reserved_at_2[0x4];
11200         u8         trc_ver[0x2];
11201         u8         reserved_at_8[0x14];
11202         u8         num_string_db[0x4];
11203
11204         u8         first_string_trace[0x8];
11205         u8         num_string_trace[0x8];
11206         u8         reserved_at_30[0x28];
11207
11208         u8         log_max_trace_buffer_size[0x8];
11209
11210         u8         reserved_at_60[0x20];
11211
11212         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11213
11214         u8         reserved_at_280[0x180];
11215 };
11216
11217 struct mlx5_ifc_mtrc_conf_bits {
11218         u8         reserved_at_0[0x1c];
11219         u8         trace_mode[0x4];
11220         u8         reserved_at_20[0x18];
11221         u8         log_trace_buffer_size[0x8];
11222         u8         trace_mkey[0x20];
11223         u8         reserved_at_60[0x3a0];
11224 };
11225
11226 struct mlx5_ifc_mtrc_stdb_bits {
11227         u8         string_db_index[0x4];
11228         u8         reserved_at_4[0x4];
11229         u8         read_size[0x18];
11230         u8         start_offset[0x20];
11231         u8         string_db_data[];
11232 };
11233
11234 struct mlx5_ifc_mtrc_ctrl_bits {
11235         u8         trace_status[0x2];
11236         u8         reserved_at_2[0x2];
11237         u8         arm_event[0x1];
11238         u8         reserved_at_5[0xb];
11239         u8         modify_field_select[0x10];
11240         u8         reserved_at_20[0x2b];
11241         u8         current_timestamp52_32[0x15];
11242         u8         current_timestamp31_0[0x20];
11243         u8         reserved_at_80[0x180];
11244 };
11245
11246 struct mlx5_ifc_host_params_context_bits {
11247         u8         host_number[0x8];
11248         u8         reserved_at_8[0x7];
11249         u8         host_pf_disabled[0x1];
11250         u8         host_num_of_vfs[0x10];
11251
11252         u8         host_total_vfs[0x10];
11253         u8         host_pci_bus[0x10];
11254
11255         u8         reserved_at_40[0x10];
11256         u8         host_pci_device[0x10];
11257
11258         u8         reserved_at_60[0x10];
11259         u8         host_pci_function[0x10];
11260
11261         u8         reserved_at_80[0x180];
11262 };
11263
11264 struct mlx5_ifc_query_esw_functions_in_bits {
11265         u8         opcode[0x10];
11266         u8         reserved_at_10[0x10];
11267
11268         u8         reserved_at_20[0x10];
11269         u8         op_mod[0x10];
11270
11271         u8         reserved_at_40[0x40];
11272 };
11273
11274 struct mlx5_ifc_query_esw_functions_out_bits {
11275         u8         status[0x8];
11276         u8         reserved_at_8[0x18];
11277
11278         u8         syndrome[0x20];
11279
11280         u8         reserved_at_40[0x40];
11281
11282         struct mlx5_ifc_host_params_context_bits host_params_context;
11283
11284         u8         reserved_at_280[0x180];
11285         u8         host_sf_enable[][0x40];
11286 };
11287
11288 struct mlx5_ifc_sf_partition_bits {
11289         u8         reserved_at_0[0x10];
11290         u8         log_num_sf[0x8];
11291         u8         log_sf_bar_size[0x8];
11292 };
11293
11294 struct mlx5_ifc_query_sf_partitions_out_bits {
11295         u8         status[0x8];
11296         u8         reserved_at_8[0x18];
11297
11298         u8         syndrome[0x20];
11299
11300         u8         reserved_at_40[0x18];
11301         u8         num_sf_partitions[0x8];
11302
11303         u8         reserved_at_60[0x20];
11304
11305         struct mlx5_ifc_sf_partition_bits sf_partition[];
11306 };
11307
11308 struct mlx5_ifc_query_sf_partitions_in_bits {
11309         u8         opcode[0x10];
11310         u8         reserved_at_10[0x10];
11311
11312         u8         reserved_at_20[0x10];
11313         u8         op_mod[0x10];
11314
11315         u8         reserved_at_40[0x40];
11316 };
11317
11318 struct mlx5_ifc_dealloc_sf_out_bits {
11319         u8         status[0x8];
11320         u8         reserved_at_8[0x18];
11321
11322         u8         syndrome[0x20];
11323
11324         u8         reserved_at_40[0x40];
11325 };
11326
11327 struct mlx5_ifc_dealloc_sf_in_bits {
11328         u8         opcode[0x10];
11329         u8         reserved_at_10[0x10];
11330
11331         u8         reserved_at_20[0x10];
11332         u8         op_mod[0x10];
11333
11334         u8         reserved_at_40[0x10];
11335         u8         function_id[0x10];
11336
11337         u8         reserved_at_60[0x20];
11338 };
11339
11340 struct mlx5_ifc_alloc_sf_out_bits {
11341         u8         status[0x8];
11342         u8         reserved_at_8[0x18];
11343
11344         u8         syndrome[0x20];
11345
11346         u8         reserved_at_40[0x40];
11347 };
11348
11349 struct mlx5_ifc_alloc_sf_in_bits {
11350         u8         opcode[0x10];
11351         u8         reserved_at_10[0x10];
11352
11353         u8         reserved_at_20[0x10];
11354         u8         op_mod[0x10];
11355
11356         u8         reserved_at_40[0x10];
11357         u8         function_id[0x10];
11358
11359         u8         reserved_at_60[0x20];
11360 };
11361
11362 struct mlx5_ifc_affiliated_event_header_bits {
11363         u8         reserved_at_0[0x10];
11364         u8         obj_type[0x10];
11365
11366         u8         obj_id[0x20];
11367 };
11368
11369 enum {
11370         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11371         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11372         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11373 };
11374
11375 enum {
11376         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11377         MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11378         MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11379 };
11380
11381 enum {
11382         MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11383 };
11384
11385 struct mlx5_ifc_ipsec_obj_bits {
11386         u8         modify_field_select[0x40];
11387         u8         full_offload[0x1];
11388         u8         reserved_at_41[0x1];
11389         u8         esn_en[0x1];
11390         u8         esn_overlap[0x1];
11391         u8         reserved_at_44[0x2];
11392         u8         icv_length[0x2];
11393         u8         reserved_at_48[0x4];
11394         u8         aso_return_reg[0x4];
11395         u8         reserved_at_50[0x10];
11396
11397         u8         esn_msb[0x20];
11398
11399         u8         reserved_at_80[0x8];
11400         u8         dekn[0x18];
11401
11402         u8         salt[0x20];
11403
11404         u8         implicit_iv[0x40];
11405
11406         u8         reserved_at_100[0x700];
11407 };
11408
11409 struct mlx5_ifc_create_ipsec_obj_in_bits {
11410         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11411         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11412 };
11413
11414 enum {
11415         MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11416         MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11417 };
11418
11419 struct mlx5_ifc_query_ipsec_obj_out_bits {
11420         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11421         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11422 };
11423
11424 struct mlx5_ifc_modify_ipsec_obj_in_bits {
11425         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11426         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11427 };
11428
11429 struct mlx5_ifc_encryption_key_obj_bits {
11430         u8         modify_field_select[0x40];
11431
11432         u8         reserved_at_40[0x14];
11433         u8         key_size[0x4];
11434         u8         reserved_at_58[0x4];
11435         u8         key_type[0x4];
11436
11437         u8         reserved_at_60[0x8];
11438         u8         pd[0x18];
11439
11440         u8         reserved_at_80[0x180];
11441         u8         key[8][0x20];
11442
11443         u8         reserved_at_300[0x500];
11444 };
11445
11446 struct mlx5_ifc_create_encryption_key_in_bits {
11447         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11448         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11449 };
11450
11451 struct mlx5_ifc_sampler_obj_bits {
11452         u8         modify_field_select[0x40];
11453
11454         u8         table_type[0x8];
11455         u8         level[0x8];
11456         u8         reserved_at_50[0xf];
11457         u8         ignore_flow_level[0x1];
11458
11459         u8         sample_ratio[0x20];
11460
11461         u8         reserved_at_80[0x8];
11462         u8         sample_table_id[0x18];
11463
11464         u8         reserved_at_a0[0x8];
11465         u8         default_table_id[0x18];
11466
11467         u8         sw_steering_icm_address_rx[0x40];
11468         u8         sw_steering_icm_address_tx[0x40];
11469
11470         u8         reserved_at_140[0xa0];
11471 };
11472
11473 struct mlx5_ifc_create_sampler_obj_in_bits {
11474         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11475         struct mlx5_ifc_sampler_obj_bits sampler_object;
11476 };
11477
11478 struct mlx5_ifc_query_sampler_obj_out_bits {
11479         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11480         struct mlx5_ifc_sampler_obj_bits sampler_object;
11481 };
11482
11483 enum {
11484         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11485         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11486 };
11487
11488 enum {
11489         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11490         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
11491 };
11492
11493 struct mlx5_ifc_tls_static_params_bits {
11494         u8         const_2[0x2];
11495         u8         tls_version[0x4];
11496         u8         const_1[0x2];
11497         u8         reserved_at_8[0x14];
11498         u8         encryption_standard[0x4];
11499
11500         u8         reserved_at_20[0x20];
11501
11502         u8         initial_record_number[0x40];
11503
11504         u8         resync_tcp_sn[0x20];
11505
11506         u8         gcm_iv[0x20];
11507
11508         u8         implicit_iv[0x40];
11509
11510         u8         reserved_at_100[0x8];
11511         u8         dek_index[0x18];
11512
11513         u8         reserved_at_120[0xe0];
11514 };
11515
11516 struct mlx5_ifc_tls_progress_params_bits {
11517         u8         next_record_tcp_sn[0x20];
11518
11519         u8         hw_resync_tcp_sn[0x20];
11520
11521         u8         record_tracker_state[0x2];
11522         u8         auth_state[0x2];
11523         u8         reserved_at_44[0x4];
11524         u8         hw_offset_record_number[0x18];
11525 };
11526
11527 enum {
11528         MLX5_MTT_PERM_READ      = 1 << 0,
11529         MLX5_MTT_PERM_WRITE     = 1 << 1,
11530         MLX5_MTT_PERM_RW        = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11531 };
11532
11533 enum {
11534         MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
11535         MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
11536 };
11537
11538 struct mlx5_ifc_suspend_vhca_in_bits {
11539         u8         opcode[0x10];
11540         u8         uid[0x10];
11541
11542         u8         reserved_at_20[0x10];
11543         u8         op_mod[0x10];
11544
11545         u8         reserved_at_40[0x10];
11546         u8         vhca_id[0x10];
11547
11548         u8         reserved_at_60[0x20];
11549 };
11550
11551 struct mlx5_ifc_suspend_vhca_out_bits {
11552         u8         status[0x8];
11553         u8         reserved_at_8[0x18];
11554
11555         u8         syndrome[0x20];
11556
11557         u8         reserved_at_40[0x40];
11558 };
11559
11560 enum {
11561         MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
11562         MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
11563 };
11564
11565 struct mlx5_ifc_resume_vhca_in_bits {
11566         u8         opcode[0x10];
11567         u8         uid[0x10];
11568
11569         u8         reserved_at_20[0x10];
11570         u8         op_mod[0x10];
11571
11572         u8         reserved_at_40[0x10];
11573         u8         vhca_id[0x10];
11574
11575         u8         reserved_at_60[0x20];
11576 };
11577
11578 struct mlx5_ifc_resume_vhca_out_bits {
11579         u8         status[0x8];
11580         u8         reserved_at_8[0x18];
11581
11582         u8         syndrome[0x20];
11583
11584         u8         reserved_at_40[0x40];
11585 };
11586
11587 struct mlx5_ifc_query_vhca_migration_state_in_bits {
11588         u8         opcode[0x10];
11589         u8         uid[0x10];
11590
11591         u8         reserved_at_20[0x10];
11592         u8         op_mod[0x10];
11593
11594         u8         reserved_at_40[0x10];
11595         u8         vhca_id[0x10];
11596
11597         u8         reserved_at_60[0x20];
11598 };
11599
11600 struct mlx5_ifc_query_vhca_migration_state_out_bits {
11601         u8         status[0x8];
11602         u8         reserved_at_8[0x18];
11603
11604         u8         syndrome[0x20];
11605
11606         u8         reserved_at_40[0x40];
11607
11608         u8         required_umem_size[0x20];
11609
11610         u8         reserved_at_a0[0x160];
11611 };
11612
11613 struct mlx5_ifc_save_vhca_state_in_bits {
11614         u8         opcode[0x10];
11615         u8         uid[0x10];
11616
11617         u8         reserved_at_20[0x10];
11618         u8         op_mod[0x10];
11619
11620         u8         reserved_at_40[0x10];
11621         u8         vhca_id[0x10];
11622
11623         u8         reserved_at_60[0x20];
11624
11625         u8         va[0x40];
11626
11627         u8         mkey[0x20];
11628
11629         u8         size[0x20];
11630 };
11631
11632 struct mlx5_ifc_save_vhca_state_out_bits {
11633         u8         status[0x8];
11634         u8         reserved_at_8[0x18];
11635
11636         u8         syndrome[0x20];
11637
11638         u8         actual_image_size[0x20];
11639
11640         u8         reserved_at_60[0x20];
11641 };
11642
11643 struct mlx5_ifc_load_vhca_state_in_bits {
11644         u8         opcode[0x10];
11645         u8         uid[0x10];
11646
11647         u8         reserved_at_20[0x10];
11648         u8         op_mod[0x10];
11649
11650         u8         reserved_at_40[0x10];
11651         u8         vhca_id[0x10];
11652
11653         u8         reserved_at_60[0x20];
11654
11655         u8         va[0x40];
11656
11657         u8         mkey[0x20];
11658
11659         u8         size[0x20];
11660 };
11661
11662 struct mlx5_ifc_load_vhca_state_out_bits {
11663         u8         status[0x8];
11664         u8         reserved_at_8[0x18];
11665
11666         u8         syndrome[0x20];
11667
11668         u8         reserved_at_40[0x40];
11669 };
11670
11671 #endif /* MLX5_IFC_H */