2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
74 MLX5_SHARED_RESOURCE_UID = 0xffff,
78 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
88 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
89 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
90 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
91 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
92 MLX5_OBJ_TYPE_MKEY = 0xff01,
93 MLX5_OBJ_TYPE_QP = 0xff02,
94 MLX5_OBJ_TYPE_PSV = 0xff03,
95 MLX5_OBJ_TYPE_RMP = 0xff04,
96 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
97 MLX5_OBJ_TYPE_RQ = 0xff06,
98 MLX5_OBJ_TYPE_SQ = 0xff07,
99 MLX5_OBJ_TYPE_TIR = 0xff08,
100 MLX5_OBJ_TYPE_TIS = 0xff09,
101 MLX5_OBJ_TYPE_DCT = 0xff0a,
102 MLX5_OBJ_TYPE_XRQ = 0xff0b,
103 MLX5_OBJ_TYPE_RQT = 0xff0e,
104 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
105 MLX5_OBJ_TYPE_CQ = 0xff10,
109 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
110 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
111 MLX5_CMD_OP_INIT_HCA = 0x102,
112 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
113 MLX5_CMD_OP_ENABLE_HCA = 0x104,
114 MLX5_CMD_OP_DISABLE_HCA = 0x105,
115 MLX5_CMD_OP_QUERY_PAGES = 0x107,
116 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
117 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
118 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
119 MLX5_CMD_OP_SET_ISSI = 0x10b,
120 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
121 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
122 MLX5_CMD_OP_ALLOC_SF = 0x113,
123 MLX5_CMD_OP_DEALLOC_SF = 0x114,
124 MLX5_CMD_OP_SUSPEND_VHCA = 0x115,
125 MLX5_CMD_OP_RESUME_VHCA = 0x116,
126 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117,
127 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118,
128 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119,
129 MLX5_CMD_OP_CREATE_MKEY = 0x200,
130 MLX5_CMD_OP_QUERY_MKEY = 0x201,
131 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
136 MLX5_CMD_OP_MODIFY_MEMIC = 0x207,
137 MLX5_CMD_OP_CREATE_EQ = 0x301,
138 MLX5_CMD_OP_DESTROY_EQ = 0x302,
139 MLX5_CMD_OP_QUERY_EQ = 0x303,
140 MLX5_CMD_OP_GEN_EQE = 0x304,
141 MLX5_CMD_OP_CREATE_CQ = 0x400,
142 MLX5_CMD_OP_DESTROY_CQ = 0x401,
143 MLX5_CMD_OP_QUERY_CQ = 0x402,
144 MLX5_CMD_OP_MODIFY_CQ = 0x403,
145 MLX5_CMD_OP_CREATE_QP = 0x500,
146 MLX5_CMD_OP_DESTROY_QP = 0x501,
147 MLX5_CMD_OP_RST2INIT_QP = 0x502,
148 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
149 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
150 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
151 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
152 MLX5_CMD_OP_2ERR_QP = 0x507,
153 MLX5_CMD_OP_2RST_QP = 0x50a,
154 MLX5_CMD_OP_QUERY_QP = 0x50b,
155 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
156 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
157 MLX5_CMD_OP_CREATE_PSV = 0x600,
158 MLX5_CMD_OP_DESTROY_PSV = 0x601,
159 MLX5_CMD_OP_CREATE_SRQ = 0x700,
160 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
161 MLX5_CMD_OP_QUERY_SRQ = 0x702,
162 MLX5_CMD_OP_ARM_RQ = 0x703,
163 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
164 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
165 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
166 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
167 MLX5_CMD_OP_CREATE_DCT = 0x710,
168 MLX5_CMD_OP_DESTROY_DCT = 0x711,
169 MLX5_CMD_OP_DRAIN_DCT = 0x712,
170 MLX5_CMD_OP_QUERY_DCT = 0x713,
171 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
172 MLX5_CMD_OP_CREATE_XRQ = 0x717,
173 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
174 MLX5_CMD_OP_QUERY_XRQ = 0x719,
175 MLX5_CMD_OP_ARM_XRQ = 0x71a,
176 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
177 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
178 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
179 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
180 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
181 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
182 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
183 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
184 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
185 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
186 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
187 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
188 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
189 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
190 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
191 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
192 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
193 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
194 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
195 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
196 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
197 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
198 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
199 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
200 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
201 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
202 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
203 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
204 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
205 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
206 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
207 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
208 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
209 MLX5_CMD_OP_ALLOC_PD = 0x800,
210 MLX5_CMD_OP_DEALLOC_PD = 0x801,
211 MLX5_CMD_OP_ALLOC_UAR = 0x802,
212 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
213 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
214 MLX5_CMD_OP_ACCESS_REG = 0x805,
215 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
216 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
217 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
218 MLX5_CMD_OP_MAD_IFC = 0x50d,
219 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
220 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
221 MLX5_CMD_OP_NOP = 0x80d,
222 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
223 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
224 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
225 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
226 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
227 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
228 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
229 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
230 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
231 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
232 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
233 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
234 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
235 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
236 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
237 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
238 MLX5_CMD_OP_CREATE_LAG = 0x840,
239 MLX5_CMD_OP_MODIFY_LAG = 0x841,
240 MLX5_CMD_OP_QUERY_LAG = 0x842,
241 MLX5_CMD_OP_DESTROY_LAG = 0x843,
242 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
243 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
244 MLX5_CMD_OP_CREATE_TIR = 0x900,
245 MLX5_CMD_OP_MODIFY_TIR = 0x901,
246 MLX5_CMD_OP_DESTROY_TIR = 0x902,
247 MLX5_CMD_OP_QUERY_TIR = 0x903,
248 MLX5_CMD_OP_CREATE_SQ = 0x904,
249 MLX5_CMD_OP_MODIFY_SQ = 0x905,
250 MLX5_CMD_OP_DESTROY_SQ = 0x906,
251 MLX5_CMD_OP_QUERY_SQ = 0x907,
252 MLX5_CMD_OP_CREATE_RQ = 0x908,
253 MLX5_CMD_OP_MODIFY_RQ = 0x909,
254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
255 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
256 MLX5_CMD_OP_QUERY_RQ = 0x90b,
257 MLX5_CMD_OP_CREATE_RMP = 0x90c,
258 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
259 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
260 MLX5_CMD_OP_QUERY_RMP = 0x90f,
261 MLX5_CMD_OP_CREATE_TIS = 0x912,
262 MLX5_CMD_OP_MODIFY_TIS = 0x913,
263 MLX5_CMD_OP_DESTROY_TIS = 0x914,
264 MLX5_CMD_OP_QUERY_TIS = 0x915,
265 MLX5_CMD_OP_CREATE_RQT = 0x916,
266 MLX5_CMD_OP_MODIFY_RQT = 0x917,
267 MLX5_CMD_OP_DESTROY_RQT = 0x918,
268 MLX5_CMD_OP_QUERY_RQT = 0x919,
269 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
270 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
271 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
272 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
273 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
274 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
275 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
276 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
277 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
278 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
279 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
280 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
281 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
282 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
283 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
284 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
285 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
286 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
287 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
288 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
289 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
290 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
291 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
292 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
293 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
295 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
296 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
297 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
298 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
299 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
300 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
301 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
302 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
303 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
304 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
308 /* Valid range for general commands that don't work over an object */
310 MLX5_CMD_OP_GENERAL_START = 0xb00,
311 MLX5_CMD_OP_GENERAL_END = 0xd00,
314 struct mlx5_ifc_flow_table_fields_supported_bits {
317 u8 outer_ether_type[0x1];
318 u8 outer_ip_version[0x1];
319 u8 outer_first_prio[0x1];
320 u8 outer_first_cfi[0x1];
321 u8 outer_first_vid[0x1];
322 u8 outer_ipv4_ttl[0x1];
323 u8 outer_second_prio[0x1];
324 u8 outer_second_cfi[0x1];
325 u8 outer_second_vid[0x1];
326 u8 reserved_at_b[0x1];
330 u8 outer_ip_protocol[0x1];
331 u8 outer_ip_ecn[0x1];
332 u8 outer_ip_dscp[0x1];
333 u8 outer_udp_sport[0x1];
334 u8 outer_udp_dport[0x1];
335 u8 outer_tcp_sport[0x1];
336 u8 outer_tcp_dport[0x1];
337 u8 outer_tcp_flags[0x1];
338 u8 outer_gre_protocol[0x1];
339 u8 outer_gre_key[0x1];
340 u8 outer_vxlan_vni[0x1];
341 u8 outer_geneve_vni[0x1];
342 u8 outer_geneve_oam[0x1];
343 u8 outer_geneve_protocol_type[0x1];
344 u8 outer_geneve_opt_len[0x1];
345 u8 source_vhca_port[0x1];
346 u8 source_eswitch_port[0x1];
350 u8 inner_ether_type[0x1];
351 u8 inner_ip_version[0x1];
352 u8 inner_first_prio[0x1];
353 u8 inner_first_cfi[0x1];
354 u8 inner_first_vid[0x1];
355 u8 reserved_at_27[0x1];
356 u8 inner_second_prio[0x1];
357 u8 inner_second_cfi[0x1];
358 u8 inner_second_vid[0x1];
359 u8 reserved_at_2b[0x1];
363 u8 inner_ip_protocol[0x1];
364 u8 inner_ip_ecn[0x1];
365 u8 inner_ip_dscp[0x1];
366 u8 inner_udp_sport[0x1];
367 u8 inner_udp_dport[0x1];
368 u8 inner_tcp_sport[0x1];
369 u8 inner_tcp_dport[0x1];
370 u8 inner_tcp_flags[0x1];
371 u8 reserved_at_37[0x9];
373 u8 geneve_tlv_option_0_data[0x1];
374 u8 geneve_tlv_option_0_exist[0x1];
375 u8 reserved_at_42[0x3];
376 u8 outer_first_mpls_over_udp[0x4];
377 u8 outer_first_mpls_over_gre[0x4];
378 u8 inner_first_mpls[0x4];
379 u8 outer_first_mpls[0x4];
380 u8 reserved_at_55[0x2];
381 u8 outer_esp_spi[0x1];
382 u8 reserved_at_58[0x2];
384 u8 reserved_at_5b[0x5];
386 u8 reserved_at_60[0x18];
387 u8 metadata_reg_c_7[0x1];
388 u8 metadata_reg_c_6[0x1];
389 u8 metadata_reg_c_5[0x1];
390 u8 metadata_reg_c_4[0x1];
391 u8 metadata_reg_c_3[0x1];
392 u8 metadata_reg_c_2[0x1];
393 u8 metadata_reg_c_1[0x1];
394 u8 metadata_reg_c_0[0x1];
397 struct mlx5_ifc_flow_table_fields_supported_2_bits {
398 u8 reserved_at_0[0xe];
400 u8 reserved_at_f[0x11];
402 u8 reserved_at_20[0x60];
405 struct mlx5_ifc_flow_table_prop_layout_bits {
407 u8 reserved_at_1[0x1];
408 u8 flow_counter[0x1];
409 u8 flow_modify_en[0x1];
411 u8 identified_miss_table_mode[0x1];
412 u8 flow_table_modify[0x1];
415 u8 reserved_at_9[0x1];
418 u8 reserved_at_c[0x1];
421 u8 reformat_and_vlan_action[0x1];
422 u8 reserved_at_10[0x1];
424 u8 reformat_l3_tunnel_to_l2[0x1];
425 u8 reformat_l2_to_l3_tunnel[0x1];
426 u8 reformat_and_modify_action[0x1];
427 u8 ignore_flow_level[0x1];
428 u8 reserved_at_16[0x1];
429 u8 table_miss_action_domain[0x1];
430 u8 termination_table[0x1];
431 u8 reformat_and_fwd_to_table[0x1];
432 u8 reserved_at_1a[0x2];
433 u8 ipsec_encrypt[0x1];
434 u8 ipsec_decrypt[0x1];
436 u8 reserved_at_1f[0x1];
438 u8 termination_table_raw_traffic[0x1];
439 u8 reserved_at_21[0x1];
440 u8 log_max_ft_size[0x6];
441 u8 log_max_modify_header_context[0x8];
442 u8 max_modify_header_actions[0x8];
443 u8 max_ft_level[0x8];
445 u8 reserved_at_40[0x20];
447 u8 reserved_at_60[0x2];
448 u8 reformat_insert[0x1];
449 u8 reformat_remove[0x1];
450 u8 reserver_at_64[0x14];
451 u8 log_max_ft_num[0x8];
453 u8 reserved_at_80[0x10];
454 u8 log_max_flow_counter[0x8];
455 u8 log_max_destination[0x8];
457 u8 reserved_at_a0[0x18];
458 u8 log_max_flow[0x8];
460 u8 reserved_at_c0[0x40];
462 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
464 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
467 struct mlx5_ifc_odp_per_transport_service_cap_bits {
474 u8 reserved_at_6[0x1a];
477 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
502 u8 reserved_at_c0[0x10];
504 u8 reserved_at_c4[0x4];
506 u8 ttl_hoplimit[0x8];
511 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
513 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
516 struct mlx5_ifc_nvgre_key_bits {
521 union mlx5_ifc_gre_key_bits {
522 struct mlx5_ifc_nvgre_key_bits nvgre;
526 struct mlx5_ifc_fte_match_set_misc_bits {
527 u8 gre_c_present[0x1];
528 u8 reserved_at_1[0x1];
529 u8 gre_k_present[0x1];
530 u8 gre_s_present[0x1];
531 u8 source_vhca_port[0x4];
534 u8 source_eswitch_owner_vhca_id[0x10];
535 u8 source_port[0x10];
537 u8 outer_second_prio[0x3];
538 u8 outer_second_cfi[0x1];
539 u8 outer_second_vid[0xc];
540 u8 inner_second_prio[0x3];
541 u8 inner_second_cfi[0x1];
542 u8 inner_second_vid[0xc];
544 u8 outer_second_cvlan_tag[0x1];
545 u8 inner_second_cvlan_tag[0x1];
546 u8 outer_second_svlan_tag[0x1];
547 u8 inner_second_svlan_tag[0x1];
548 u8 reserved_at_64[0xc];
549 u8 gre_protocol[0x10];
551 union mlx5_ifc_gre_key_bits gre_key;
557 u8 reserved_at_d8[0x6];
558 u8 geneve_tlv_option_0_exist[0x1];
561 u8 reserved_at_e0[0xc];
562 u8 outer_ipv6_flow_label[0x14];
564 u8 reserved_at_100[0xc];
565 u8 inner_ipv6_flow_label[0x14];
567 u8 reserved_at_120[0xa];
568 u8 geneve_opt_len[0x6];
569 u8 geneve_protocol_type[0x10];
571 u8 reserved_at_140[0x8];
573 u8 reserved_at_160[0x20];
574 u8 outer_esp_spi[0x20];
575 u8 reserved_at_1a0[0x60];
578 struct mlx5_ifc_fte_match_mpls_bits {
585 struct mlx5_ifc_fte_match_set_misc2_bits {
586 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
588 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
590 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
592 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
594 u8 metadata_reg_c_7[0x20];
596 u8 metadata_reg_c_6[0x20];
598 u8 metadata_reg_c_5[0x20];
600 u8 metadata_reg_c_4[0x20];
602 u8 metadata_reg_c_3[0x20];
604 u8 metadata_reg_c_2[0x20];
606 u8 metadata_reg_c_1[0x20];
608 u8 metadata_reg_c_0[0x20];
610 u8 metadata_reg_a[0x20];
612 u8 reserved_at_1a0[0x60];
615 struct mlx5_ifc_fte_match_set_misc3_bits {
616 u8 inner_tcp_seq_num[0x20];
618 u8 outer_tcp_seq_num[0x20];
620 u8 inner_tcp_ack_num[0x20];
622 u8 outer_tcp_ack_num[0x20];
624 u8 reserved_at_80[0x8];
625 u8 outer_vxlan_gpe_vni[0x18];
627 u8 outer_vxlan_gpe_next_protocol[0x8];
628 u8 outer_vxlan_gpe_flags[0x8];
629 u8 reserved_at_b0[0x10];
631 u8 icmp_header_data[0x20];
633 u8 icmpv6_header_data[0x20];
640 u8 geneve_tlv_option_0_data[0x20];
644 u8 gtpu_msg_type[0x8];
645 u8 gtpu_msg_flags[0x8];
646 u8 reserved_at_170[0x10];
650 u8 gtpu_first_ext_dw_0[0x20];
654 u8 reserved_at_1e0[0x20];
657 struct mlx5_ifc_fte_match_set_misc4_bits {
658 u8 prog_sample_field_value_0[0x20];
660 u8 prog_sample_field_id_0[0x20];
662 u8 prog_sample_field_value_1[0x20];
664 u8 prog_sample_field_id_1[0x20];
666 u8 prog_sample_field_value_2[0x20];
668 u8 prog_sample_field_id_2[0x20];
670 u8 prog_sample_field_value_3[0x20];
672 u8 prog_sample_field_id_3[0x20];
674 u8 reserved_at_100[0x100];
677 struct mlx5_ifc_fte_match_set_misc5_bits {
678 u8 macsec_tag_0[0x20];
680 u8 macsec_tag_1[0x20];
682 u8 macsec_tag_2[0x20];
684 u8 macsec_tag_3[0x20];
686 u8 tunnel_header_0[0x20];
688 u8 tunnel_header_1[0x20];
690 u8 tunnel_header_2[0x20];
692 u8 tunnel_header_3[0x20];
694 u8 reserved_at_100[0x100];
697 struct mlx5_ifc_cmd_pas_bits {
701 u8 reserved_at_34[0xc];
704 struct mlx5_ifc_uint64_bits {
711 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
712 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
713 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
714 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
715 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
716 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
717 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
718 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
719 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
720 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
723 struct mlx5_ifc_ads_bits {
726 u8 reserved_at_2[0xe];
729 u8 reserved_at_20[0x8];
735 u8 reserved_at_45[0x3];
736 u8 src_addr_index[0x8];
737 u8 reserved_at_50[0x4];
741 u8 reserved_at_60[0x4];
745 u8 rgid_rip[16][0x8];
747 u8 reserved_at_100[0x4];
750 u8 reserved_at_106[0x1];
759 u8 vhca_port_num[0x8];
765 struct mlx5_ifc_flow_table_nic_cap_bits {
766 u8 nic_rx_multi_path_tirs[0x1];
767 u8 nic_rx_multi_path_tirs_fts[0x1];
768 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
769 u8 reserved_at_3[0x4];
770 u8 sw_owner_reformat_supported[0x1];
771 u8 reserved_at_8[0x18];
773 u8 encap_general_header[0x1];
774 u8 reserved_at_21[0xa];
775 u8 log_max_packet_reformat_context[0x5];
776 u8 reserved_at_30[0x6];
777 u8 max_encap_header_size[0xa];
778 u8 reserved_at_40[0x1c0];
780 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
782 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
784 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
786 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
788 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
790 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
792 u8 reserved_at_e00[0x700];
794 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
796 u8 reserved_at_1580[0x280];
798 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
800 u8 reserved_at_1880[0x780];
802 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
804 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
806 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
808 u8 reserved_at_20c0[0x5f40];
811 struct mlx5_ifc_port_selection_cap_bits {
812 u8 reserved_at_0[0x10];
813 u8 port_select_flow_table[0x1];
814 u8 reserved_at_11[0xf];
816 u8 reserved_at_20[0x1e0];
818 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
820 u8 reserved_at_400[0x7c00];
824 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
825 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
826 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
827 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
828 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
829 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
830 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
831 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
834 struct mlx5_ifc_flow_table_eswitch_cap_bits {
835 u8 fdb_to_vport_reg_c_id[0x8];
836 u8 reserved_at_8[0xd];
837 u8 fdb_modify_header_fwd_to_table[0x1];
838 u8 fdb_ipv4_ttl_modify[0x1];
840 u8 reserved_at_18[0x2];
841 u8 multi_fdb_encap[0x1];
842 u8 egress_acl_forward_to_vport[0x1];
843 u8 fdb_multi_path_to_table[0x1];
844 u8 reserved_at_1d[0x3];
846 u8 reserved_at_20[0x1e0];
848 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
850 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
852 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
854 u8 reserved_at_800[0x1000];
856 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
858 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
860 u8 sw_steering_uplink_icm_address_rx[0x40];
862 u8 sw_steering_uplink_icm_address_tx[0x40];
864 u8 reserved_at_1900[0x6700];
868 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
869 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
872 struct mlx5_ifc_e_switch_cap_bits {
873 u8 vport_svlan_strip[0x1];
874 u8 vport_cvlan_strip[0x1];
875 u8 vport_svlan_insert[0x1];
876 u8 vport_cvlan_insert_if_not_exist[0x1];
877 u8 vport_cvlan_insert_overwrite[0x1];
878 u8 reserved_at_5[0x2];
879 u8 esw_shared_ingress_acl[0x1];
880 u8 esw_uplink_ingress_acl[0x1];
881 u8 root_ft_on_other_esw[0x1];
882 u8 reserved_at_a[0xf];
883 u8 esw_functions_changed[0x1];
884 u8 reserved_at_1a[0x1];
885 u8 ecpf_vport_exists[0x1];
886 u8 counter_eswitch_affinity[0x1];
887 u8 merged_eswitch[0x1];
888 u8 nic_vport_node_guid_modify[0x1];
889 u8 nic_vport_port_guid_modify[0x1];
891 u8 vxlan_encap_decap[0x1];
892 u8 nvgre_encap_decap[0x1];
893 u8 reserved_at_22[0x1];
894 u8 log_max_fdb_encap_uplink[0x5];
895 u8 reserved_at_21[0x3];
896 u8 log_max_packet_reformat_context[0x5];
898 u8 max_encap_header_size[0xa];
900 u8 reserved_at_40[0xb];
901 u8 log_max_esw_sf[0x5];
902 u8 esw_sf_base_id[0x10];
904 u8 reserved_at_60[0x7a0];
908 struct mlx5_ifc_qos_cap_bits {
909 u8 packet_pacing[0x1];
910 u8 esw_scheduling[0x1];
911 u8 esw_bw_share[0x1];
912 u8 esw_rate_limit[0x1];
913 u8 reserved_at_4[0x1];
914 u8 packet_pacing_burst_bound[0x1];
915 u8 packet_pacing_typical_size[0x1];
916 u8 reserved_at_7[0x1];
917 u8 nic_sq_scheduling[0x1];
918 u8 nic_bw_share[0x1];
919 u8 nic_rate_limit[0x1];
920 u8 packet_pacing_uid[0x1];
921 u8 log_esw_max_sched_depth[0x4];
922 u8 reserved_at_10[0x10];
924 u8 reserved_at_20[0xb];
925 u8 log_max_qos_nic_queue_group[0x5];
926 u8 reserved_at_30[0x10];
928 u8 packet_pacing_max_rate[0x20];
930 u8 packet_pacing_min_rate[0x20];
932 u8 reserved_at_80[0x10];
933 u8 packet_pacing_rate_table_size[0x10];
935 u8 esw_element_type[0x10];
936 u8 esw_tsar_type[0x10];
938 u8 reserved_at_c0[0x10];
939 u8 max_qos_para_vport[0x10];
941 u8 max_tsar_bw_share[0x20];
943 u8 reserved_at_100[0x700];
946 struct mlx5_ifc_debug_cap_bits {
947 u8 core_dump_general[0x1];
948 u8 core_dump_qp[0x1];
949 u8 reserved_at_2[0x7];
950 u8 resource_dump[0x1];
951 u8 reserved_at_a[0x16];
953 u8 reserved_at_20[0x2];
954 u8 stall_detect[0x1];
955 u8 reserved_at_23[0x1d];
957 u8 reserved_at_40[0x7c0];
960 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
964 u8 lro_psh_flag[0x1];
965 u8 lro_time_stamp[0x1];
966 u8 reserved_at_5[0x2];
967 u8 wqe_vlan_insert[0x1];
968 u8 self_lb_en_modifiable[0x1];
969 u8 reserved_at_9[0x2];
971 u8 multi_pkt_send_wqe[0x2];
972 u8 wqe_inline_mode[0x2];
973 u8 rss_ind_tbl_cap[0x4];
976 u8 enhanced_multi_pkt_send_wqe[0x1];
977 u8 tunnel_lso_const_out_ip_id[0x1];
978 u8 tunnel_lro_gre[0x1];
979 u8 tunnel_lro_vxlan[0x1];
980 u8 tunnel_stateless_gre[0x1];
981 u8 tunnel_stateless_vxlan[0x1];
986 u8 cqe_checksum_full[0x1];
987 u8 tunnel_stateless_geneve_tx[0x1];
988 u8 tunnel_stateless_mpls_over_udp[0x1];
989 u8 tunnel_stateless_mpls_over_gre[0x1];
990 u8 tunnel_stateless_vxlan_gpe[0x1];
991 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
992 u8 tunnel_stateless_ip_over_ip[0x1];
993 u8 insert_trailer[0x1];
994 u8 reserved_at_2b[0x1];
995 u8 tunnel_stateless_ip_over_ip_rx[0x1];
996 u8 tunnel_stateless_ip_over_ip_tx[0x1];
997 u8 reserved_at_2e[0x2];
998 u8 max_vxlan_udp_ports[0x8];
999 u8 reserved_at_38[0x6];
1000 u8 max_geneve_opt_len[0x1];
1001 u8 tunnel_stateless_geneve_rx[0x1];
1003 u8 reserved_at_40[0x10];
1004 u8 lro_min_mss_size[0x10];
1006 u8 reserved_at_60[0x120];
1008 u8 lro_timer_supported_periods[4][0x20];
1010 u8 reserved_at_200[0x600];
1014 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1015 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1016 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1019 struct mlx5_ifc_roce_cap_bits {
1021 u8 reserved_at_1[0x3];
1022 u8 sw_r_roce_src_udp_port[0x1];
1023 u8 fl_rc_qp_when_roce_disabled[0x1];
1024 u8 fl_rc_qp_when_roce_enabled[0x1];
1025 u8 reserved_at_7[0x17];
1026 u8 qp_ts_format[0x2];
1028 u8 reserved_at_20[0x60];
1030 u8 reserved_at_80[0xc];
1032 u8 reserved_at_90[0x8];
1033 u8 roce_version[0x8];
1035 u8 reserved_at_a0[0x10];
1036 u8 r_roce_dest_udp_port[0x10];
1038 u8 r_roce_max_src_udp_port[0x10];
1039 u8 r_roce_min_src_udp_port[0x10];
1041 u8 reserved_at_e0[0x10];
1042 u8 roce_address_table_size[0x10];
1044 u8 reserved_at_100[0x700];
1047 struct mlx5_ifc_sync_steering_in_bits {
1051 u8 reserved_at_20[0x10];
1054 u8 reserved_at_40[0xc0];
1057 struct mlx5_ifc_sync_steering_out_bits {
1059 u8 reserved_at_8[0x18];
1063 u8 reserved_at_40[0x40];
1066 struct mlx5_ifc_device_mem_cap_bits {
1068 u8 reserved_at_1[0x1f];
1070 u8 reserved_at_20[0xb];
1071 u8 log_min_memic_alloc_size[0x5];
1072 u8 reserved_at_30[0x8];
1073 u8 log_max_memic_addr_alignment[0x8];
1075 u8 memic_bar_start_addr[0x40];
1077 u8 memic_bar_size[0x20];
1079 u8 max_memic_size[0x20];
1081 u8 steering_sw_icm_start_address[0x40];
1083 u8 reserved_at_100[0x8];
1084 u8 log_header_modify_sw_icm_size[0x8];
1085 u8 reserved_at_110[0x2];
1086 u8 log_sw_icm_alloc_granularity[0x6];
1087 u8 log_steering_sw_icm_size[0x8];
1089 u8 reserved_at_120[0x20];
1091 u8 header_modify_sw_icm_start_address[0x40];
1093 u8 reserved_at_180[0x80];
1095 u8 memic_operations[0x20];
1097 u8 reserved_at_220[0x5e0];
1100 struct mlx5_ifc_device_event_cap_bits {
1101 u8 user_affiliated_events[4][0x40];
1103 u8 user_unaffiliated_events[4][0x40];
1106 struct mlx5_ifc_virtio_emulation_cap_bits {
1107 u8 desc_tunnel_offload_type[0x1];
1108 u8 eth_frame_offload_type[0x1];
1109 u8 virtio_version_1_0[0x1];
1110 u8 device_features_bits_mask[0xd];
1112 u8 virtio_queue_type[0x8];
1114 u8 max_tunnel_desc[0x10];
1115 u8 reserved_at_30[0x3];
1116 u8 log_doorbell_stride[0x5];
1117 u8 reserved_at_38[0x3];
1118 u8 log_doorbell_bar_size[0x5];
1120 u8 doorbell_bar_offset[0x40];
1122 u8 max_emulated_devices[0x8];
1123 u8 max_num_virtio_queues[0x18];
1125 u8 reserved_at_a0[0x60];
1127 u8 umem_1_buffer_param_a[0x20];
1129 u8 umem_1_buffer_param_b[0x20];
1131 u8 umem_2_buffer_param_a[0x20];
1133 u8 umem_2_buffer_param_b[0x20];
1135 u8 umem_3_buffer_param_a[0x20];
1137 u8 umem_3_buffer_param_b[0x20];
1139 u8 reserved_at_1c0[0x640];
1143 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1144 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1145 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1146 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1147 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1148 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1149 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1150 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1151 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1155 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1156 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1157 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1158 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1159 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1160 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1161 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1162 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1163 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1166 struct mlx5_ifc_atomic_caps_bits {
1167 u8 reserved_at_0[0x40];
1169 u8 atomic_req_8B_endianness_mode[0x2];
1170 u8 reserved_at_42[0x4];
1171 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1173 u8 reserved_at_47[0x19];
1175 u8 reserved_at_60[0x20];
1177 u8 reserved_at_80[0x10];
1178 u8 atomic_operations[0x10];
1180 u8 reserved_at_a0[0x10];
1181 u8 atomic_size_qp[0x10];
1183 u8 reserved_at_c0[0x10];
1184 u8 atomic_size_dc[0x10];
1186 u8 reserved_at_e0[0x720];
1189 struct mlx5_ifc_odp_cap_bits {
1190 u8 reserved_at_0[0x40];
1193 u8 reserved_at_41[0x1f];
1195 u8 reserved_at_60[0x20];
1197 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1199 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1201 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1203 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1205 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1207 u8 reserved_at_120[0x6E0];
1210 struct mlx5_ifc_calc_op {
1211 u8 reserved_at_0[0x10];
1212 u8 reserved_at_10[0x9];
1213 u8 op_swap_endianness[0x1];
1222 struct mlx5_ifc_vector_calc_cap_bits {
1223 u8 calc_matrix[0x1];
1224 u8 reserved_at_1[0x1f];
1225 u8 reserved_at_20[0x8];
1226 u8 max_vec_count[0x8];
1227 u8 reserved_at_30[0xd];
1228 u8 max_chunk_size[0x3];
1229 struct mlx5_ifc_calc_op calc0;
1230 struct mlx5_ifc_calc_op calc1;
1231 struct mlx5_ifc_calc_op calc2;
1232 struct mlx5_ifc_calc_op calc3;
1234 u8 reserved_at_c0[0x720];
1237 struct mlx5_ifc_tls_cap_bits {
1238 u8 tls_1_2_aes_gcm_128[0x1];
1239 u8 tls_1_3_aes_gcm_128[0x1];
1240 u8 tls_1_2_aes_gcm_256[0x1];
1241 u8 tls_1_3_aes_gcm_256[0x1];
1242 u8 reserved_at_4[0x1c];
1244 u8 reserved_at_20[0x7e0];
1247 struct mlx5_ifc_ipsec_cap_bits {
1248 u8 ipsec_full_offload[0x1];
1249 u8 ipsec_crypto_offload[0x1];
1251 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1252 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1253 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1254 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1255 u8 reserved_at_7[0x4];
1256 u8 log_max_ipsec_offload[0x5];
1257 u8 reserved_at_10[0x10];
1259 u8 min_log_ipsec_full_replay_window[0x8];
1260 u8 max_log_ipsec_full_replay_window[0x8];
1261 u8 reserved_at_30[0x7d0];
1265 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1266 MLX5_WQ_TYPE_CYCLIC = 0x1,
1267 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1268 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1272 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1273 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1277 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1278 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1279 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1280 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1281 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1285 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1286 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1287 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1288 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1289 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1290 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1294 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1295 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1299 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1300 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1301 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1305 MLX5_CAP_PORT_TYPE_IB = 0x0,
1306 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1310 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1311 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1312 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1316 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
1317 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4,
1318 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5,
1319 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1320 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1321 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1322 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1323 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11,
1324 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16,
1325 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1326 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18,
1327 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19,
1331 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1332 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1335 #define MLX5_FC_BULK_SIZE_FACTOR 128
1337 enum mlx5_fc_bulk_alloc_bitmask {
1338 MLX5_FC_BULK_128 = (1 << 0),
1339 MLX5_FC_BULK_256 = (1 << 1),
1340 MLX5_FC_BULK_512 = (1 << 2),
1341 MLX5_FC_BULK_1024 = (1 << 3),
1342 MLX5_FC_BULK_2048 = (1 << 4),
1343 MLX5_FC_BULK_4096 = (1 << 5),
1344 MLX5_FC_BULK_8192 = (1 << 6),
1345 MLX5_FC_BULK_16384 = (1 << 7),
1348 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1350 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1353 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1354 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1355 MLX5_STEERING_FORMAT_CONNECTX_7 = 2,
1358 struct mlx5_ifc_cmd_hca_cap_bits {
1359 u8 reserved_at_0[0x1f];
1360 u8 vhca_resource_manager[0x1];
1363 u8 create_lag_when_not_master_up[0x1];
1365 u8 event_on_vhca_state_teardown_request[0x1];
1366 u8 event_on_vhca_state_in_use[0x1];
1367 u8 event_on_vhca_state_active[0x1];
1368 u8 event_on_vhca_state_allocated[0x1];
1369 u8 event_on_vhca_state_invalid[0x1];
1370 u8 reserved_at_28[0x8];
1373 u8 reserved_at_40[0x40];
1375 u8 log_max_srq_sz[0x8];
1376 u8 log_max_qp_sz[0x8];
1378 u8 reserved_at_91[0x2];
1379 u8 isolate_vl_tc_new[0x1];
1380 u8 reserved_at_94[0x4];
1381 u8 prio_tag_required[0x1];
1382 u8 reserved_at_99[0x2];
1385 u8 reserved_at_a0[0x3];
1386 u8 ece_support[0x1];
1387 u8 reserved_at_a4[0x5];
1388 u8 reg_c_preserve[0x1];
1389 u8 reserved_at_aa[0x1];
1390 u8 log_max_srq[0x5];
1391 u8 reserved_at_b0[0x1];
1392 u8 uplink_follow[0x1];
1393 u8 ts_cqe_to_dest_cqn[0x1];
1394 u8 reserved_at_b3[0x7];
1396 u8 reserved_at_bb[0x5];
1398 u8 max_sgl_for_optimized_performance[0x8];
1399 u8 log_max_cq_sz[0x8];
1400 u8 relaxed_ordering_write_umr[0x1];
1401 u8 relaxed_ordering_read_umr[0x1];
1402 u8 reserved_at_d2[0x7];
1403 u8 virtio_net_device_emualtion_manager[0x1];
1404 u8 virtio_blk_device_emualtion_manager[0x1];
1407 u8 log_max_eq_sz[0x8];
1408 u8 relaxed_ordering_write[0x1];
1409 u8 relaxed_ordering_read[0x1];
1410 u8 log_max_mkey[0x6];
1411 u8 reserved_at_f0[0x8];
1412 u8 dump_fill_mkey[0x1];
1413 u8 reserved_at_f9[0x2];
1414 u8 fast_teardown[0x1];
1417 u8 max_indirection[0x8];
1418 u8 fixed_buffer_size[0x1];
1419 u8 log_max_mrw_sz[0x7];
1420 u8 force_teardown[0x1];
1421 u8 reserved_at_111[0x1];
1422 u8 log_max_bsf_list_size[0x6];
1423 u8 umr_extended_translation_offset[0x1];
1425 u8 log_max_klm_list_size[0x6];
1427 u8 reserved_at_120[0xa];
1428 u8 log_max_ra_req_dc[0x6];
1429 u8 reserved_at_130[0xa];
1430 u8 log_max_ra_res_dc[0x6];
1432 u8 reserved_at_140[0x5];
1433 u8 release_all_pages[0x1];
1434 u8 must_not_use[0x1];
1435 u8 reserved_at_147[0x2];
1437 u8 log_max_ra_req_qp[0x6];
1438 u8 reserved_at_150[0xa];
1439 u8 log_max_ra_res_qp[0x6];
1442 u8 cc_query_allowed[0x1];
1443 u8 cc_modify_allowed[0x1];
1445 u8 cache_line_128byte[0x1];
1446 u8 reserved_at_165[0x4];
1447 u8 rts2rts_qp_counters_set_id[0x1];
1448 u8 reserved_at_16a[0x2];
1449 u8 vnic_env_int_rq_oob[0x1];
1451 u8 reserved_at_16e[0x1];
1453 u8 gid_table_size[0x10];
1455 u8 out_of_seq_cnt[0x1];
1456 u8 vport_counters[0x1];
1457 u8 retransmission_q_counters[0x1];
1459 u8 modify_rq_counter_set_id[0x1];
1460 u8 rq_delay_drop[0x1];
1462 u8 pkey_table_size[0x10];
1464 u8 vport_group_manager[0x1];
1465 u8 vhca_group_manager[0x1];
1468 u8 vnic_env_queue_counters[0x1];
1470 u8 nic_flow_table[0x1];
1471 u8 eswitch_manager[0x1];
1472 u8 device_memory[0x1];
1475 u8 local_ca_ack_delay[0x5];
1476 u8 port_module_event[0x1];
1477 u8 enhanced_error_q_counters[0x1];
1478 u8 ports_check[0x1];
1479 u8 reserved_at_1b3[0x1];
1480 u8 disable_link_up[0x1];
1485 u8 reserved_at_1c0[0x1];
1488 u8 log_max_msg[0x5];
1489 u8 reserved_at_1c8[0x4];
1491 u8 temp_warn_event[0x1];
1493 u8 general_notification_event[0x1];
1494 u8 reserved_at_1d3[0x2];
1498 u8 reserved_at_1d8[0x1];
1507 u8 stat_rate_support[0x10];
1508 u8 reserved_at_1f0[0x1];
1509 u8 pci_sync_for_fw_update_event[0x1];
1510 u8 reserved_at_1f2[0x6];
1511 u8 init2_lag_tx_port_affinity[0x1];
1512 u8 reserved_at_1fa[0x3];
1513 u8 cqe_version[0x4];
1515 u8 compact_address_vector[0x1];
1516 u8 striding_rq[0x1];
1517 u8 reserved_at_202[0x1];
1518 u8 ipoib_enhanced_offloads[0x1];
1519 u8 ipoib_basic_offloads[0x1];
1520 u8 reserved_at_205[0x1];
1521 u8 repeated_block_disabled[0x1];
1522 u8 umr_modify_entity_size_disabled[0x1];
1523 u8 umr_modify_atomic_disabled[0x1];
1524 u8 umr_indirect_mkey_disabled[0x1];
1526 u8 dc_req_scat_data_cqe[0x1];
1527 u8 reserved_at_20d[0x2];
1528 u8 drain_sigerr[0x1];
1529 u8 cmdif_checksum[0x2];
1531 u8 reserved_at_213[0x1];
1532 u8 wq_signature[0x1];
1533 u8 sctr_data_cqe[0x1];
1534 u8 reserved_at_216[0x1];
1540 u8 eth_net_offloads[0x1];
1543 u8 reserved_at_21f[0x1];
1547 u8 cq_moderation[0x1];
1548 u8 reserved_at_223[0x3];
1549 u8 cq_eq_remap[0x1];
1551 u8 block_lb_mc[0x1];
1552 u8 reserved_at_229[0x1];
1553 u8 scqe_break_moderation[0x1];
1554 u8 cq_period_start_from_cqe[0x1];
1556 u8 reserved_at_22d[0x1];
1558 u8 vector_calc[0x1];
1559 u8 umr_ptr_rlky[0x1];
1561 u8 qp_packet_based[0x1];
1562 u8 reserved_at_233[0x3];
1565 u8 set_deth_sqpn[0x1];
1566 u8 reserved_at_239[0x3];
1573 u8 reserved_at_241[0x9];
1575 u8 port_selection_cap[0x1];
1576 u8 reserved_at_248[0x1];
1578 u8 reserved_at_250[0x5];
1582 u8 driver_version[0x1];
1583 u8 pad_tx_eth_packet[0x1];
1584 u8 reserved_at_263[0x3];
1585 u8 mkey_by_name[0x1];
1586 u8 reserved_at_267[0x4];
1588 u8 log_bf_reg_size[0x5];
1590 u8 reserved_at_270[0x6];
1592 u8 lag_tx_port_affinity[0x1];
1593 u8 lag_native_fdb_selection[0x1];
1594 u8 reserved_at_27a[0x1];
1596 u8 num_lag_ports[0x4];
1598 u8 reserved_at_280[0x10];
1599 u8 max_wqe_sz_sq[0x10];
1601 u8 reserved_at_2a0[0x10];
1602 u8 max_wqe_sz_rq[0x10];
1604 u8 max_flow_counter_31_16[0x10];
1605 u8 max_wqe_sz_sq_dc[0x10];
1607 u8 reserved_at_2e0[0x7];
1608 u8 max_qp_mcg[0x19];
1610 u8 reserved_at_300[0x10];
1611 u8 flow_counter_bulk_alloc[0x8];
1612 u8 log_max_mcg[0x8];
1614 u8 reserved_at_320[0x3];
1615 u8 log_max_transport_domain[0x5];
1616 u8 reserved_at_328[0x3];
1618 u8 reserved_at_330[0xb];
1619 u8 log_max_xrcd[0x5];
1621 u8 nic_receive_steering_discard[0x1];
1622 u8 receive_discard_vport_down[0x1];
1623 u8 transmit_discard_vport_down[0x1];
1624 u8 reserved_at_343[0x5];
1625 u8 log_max_flow_counter_bulk[0x8];
1626 u8 max_flow_counter_15_0[0x10];
1629 u8 reserved_at_360[0x3];
1631 u8 reserved_at_368[0x3];
1633 u8 reserved_at_370[0x3];
1634 u8 log_max_tir[0x5];
1635 u8 reserved_at_378[0x3];
1636 u8 log_max_tis[0x5];
1638 u8 basic_cyclic_rcv_wqe[0x1];
1639 u8 reserved_at_381[0x2];
1640 u8 log_max_rmp[0x5];
1641 u8 reserved_at_388[0x3];
1642 u8 log_max_rqt[0x5];
1643 u8 reserved_at_390[0x3];
1644 u8 log_max_rqt_size[0x5];
1645 u8 reserved_at_398[0x3];
1646 u8 log_max_tis_per_sq[0x5];
1648 u8 ext_stride_num_range[0x1];
1649 u8 roce_rw_supported[0x1];
1650 u8 log_max_current_uc_list_wr_supported[0x1];
1651 u8 log_max_stride_sz_rq[0x5];
1652 u8 reserved_at_3a8[0x3];
1653 u8 log_min_stride_sz_rq[0x5];
1654 u8 reserved_at_3b0[0x3];
1655 u8 log_max_stride_sz_sq[0x5];
1656 u8 reserved_at_3b8[0x3];
1657 u8 log_min_stride_sz_sq[0x5];
1660 u8 reserved_at_3c1[0x2];
1661 u8 log_max_hairpin_queues[0x5];
1662 u8 reserved_at_3c8[0x3];
1663 u8 log_max_hairpin_wq_data_sz[0x5];
1664 u8 reserved_at_3d0[0x3];
1665 u8 log_max_hairpin_num_packets[0x5];
1666 u8 reserved_at_3d8[0x3];
1667 u8 log_max_wq_sz[0x5];
1669 u8 nic_vport_change_event[0x1];
1670 u8 disable_local_lb_uc[0x1];
1671 u8 disable_local_lb_mc[0x1];
1672 u8 log_min_hairpin_wq_data_sz[0x5];
1673 u8 reserved_at_3e8[0x2];
1675 u8 log_max_vlan_list[0x5];
1676 u8 reserved_at_3f0[0x3];
1677 u8 log_max_current_mc_list[0x5];
1678 u8 reserved_at_3f8[0x3];
1679 u8 log_max_current_uc_list[0x5];
1681 u8 general_obj_types[0x40];
1683 u8 sq_ts_format[0x2];
1684 u8 rq_ts_format[0x2];
1685 u8 steering_format_version[0x4];
1686 u8 create_qp_start_hint[0x18];
1688 u8 reserved_at_460[0x3];
1689 u8 log_max_uctx[0x5];
1690 u8 reserved_at_468[0x2];
1691 u8 ipsec_offload[0x1];
1692 u8 log_max_umem[0x5];
1693 u8 max_num_eqs[0x10];
1695 u8 reserved_at_480[0x1];
1698 u8 log_max_l2_table[0x5];
1699 u8 reserved_at_488[0x8];
1700 u8 log_uar_page_sz[0x10];
1702 u8 reserved_at_4a0[0x20];
1703 u8 device_frequency_mhz[0x20];
1704 u8 device_frequency_khz[0x20];
1706 u8 reserved_at_500[0x20];
1707 u8 num_of_uars_per_page[0x20];
1709 u8 flex_parser_protocols[0x20];
1711 u8 max_geneve_tlv_options[0x8];
1712 u8 reserved_at_568[0x3];
1713 u8 max_geneve_tlv_option_data_len[0x5];
1714 u8 reserved_at_570[0x10];
1716 u8 reserved_at_580[0xb];
1717 u8 log_max_dci_stream_channels[0x5];
1718 u8 reserved_at_590[0x3];
1719 u8 log_max_dci_errored_streams[0x5];
1720 u8 reserved_at_598[0x8];
1722 u8 reserved_at_5a0[0x13];
1723 u8 log_max_dek[0x5];
1724 u8 reserved_at_5b8[0x4];
1725 u8 mini_cqe_resp_stride_index[0x1];
1726 u8 cqe_128_always[0x1];
1727 u8 cqe_compression_128[0x1];
1728 u8 cqe_compression[0x1];
1730 u8 cqe_compression_timeout[0x10];
1731 u8 cqe_compression_max_num[0x10];
1733 u8 reserved_at_5e0[0x8];
1734 u8 flex_parser_id_gtpu_dw_0[0x4];
1735 u8 reserved_at_5ec[0x4];
1736 u8 tag_matching[0x1];
1737 u8 rndv_offload_rc[0x1];
1738 u8 rndv_offload_dc[0x1];
1739 u8 log_tag_matching_list_sz[0x5];
1740 u8 reserved_at_5f8[0x3];
1741 u8 log_max_xrq[0x5];
1743 u8 affiliate_nic_vport_criteria[0x8];
1744 u8 native_port_num[0x8];
1745 u8 num_vhca_ports[0x8];
1746 u8 flex_parser_id_gtpu_teid[0x4];
1747 u8 reserved_at_61c[0x2];
1748 u8 sw_owner_id[0x1];
1749 u8 reserved_at_61f[0x1];
1751 u8 max_num_of_monitor_counters[0x10];
1752 u8 num_ppcnt_monitor_counters[0x10];
1754 u8 max_num_sf[0x10];
1755 u8 num_q_monitor_counters[0x10];
1757 u8 reserved_at_660[0x20];
1760 u8 sf_set_partition[0x1];
1761 u8 reserved_at_682[0x1];
1764 u8 reserved_at_689[0x4];
1766 u8 reserved_at_68e[0x2];
1767 u8 log_min_sf_size[0x8];
1768 u8 max_num_sf_partitions[0x8];
1772 u8 reserved_at_6c0[0x4];
1773 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1774 u8 flex_parser_id_icmp_dw1[0x4];
1775 u8 flex_parser_id_icmp_dw0[0x4];
1776 u8 flex_parser_id_icmpv6_dw1[0x4];
1777 u8 flex_parser_id_icmpv6_dw0[0x4];
1778 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1779 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1781 u8 max_num_match_definer[0x10];
1782 u8 sf_base_id[0x10];
1784 u8 flex_parser_id_gtpu_dw_2[0x4];
1785 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4];
1786 u8 num_total_dynamic_vf_msix[0x18];
1787 u8 reserved_at_720[0x14];
1788 u8 dynamic_msix_table_size[0xc];
1789 u8 reserved_at_740[0xc];
1790 u8 min_dynamic_vf_msix_table_size[0x4];
1791 u8 reserved_at_750[0x4];
1792 u8 max_dynamic_vf_msix_table_size[0xc];
1794 u8 reserved_at_760[0x20];
1795 u8 vhca_tunnel_commands[0x40];
1796 u8 match_definer_format_supported[0x40];
1799 struct mlx5_ifc_cmd_hca_cap_2_bits {
1800 u8 reserved_at_0[0xa0];
1802 u8 max_reformat_insert_size[0x8];
1803 u8 max_reformat_insert_offset[0x8];
1804 u8 max_reformat_remove_size[0x8];
1805 u8 max_reformat_remove_offset[0x8];
1807 u8 reserved_at_c0[0x740];
1810 enum mlx5_ifc_flow_destination_type {
1811 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1812 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1813 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
1814 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1815 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
1818 enum mlx5_flow_table_miss_action {
1819 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1820 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1821 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1824 struct mlx5_ifc_dest_format_struct_bits {
1825 u8 destination_type[0x8];
1826 u8 destination_id[0x18];
1828 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1829 u8 packet_reformat[0x1];
1830 u8 reserved_at_22[0xe];
1831 u8 destination_eswitch_owner_vhca_id[0x10];
1834 struct mlx5_ifc_flow_counter_list_bits {
1835 u8 flow_counter_id[0x20];
1837 u8 reserved_at_20[0x20];
1840 struct mlx5_ifc_extended_dest_format_bits {
1841 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1843 u8 packet_reformat_id[0x20];
1845 u8 reserved_at_60[0x20];
1848 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1849 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1850 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1853 struct mlx5_ifc_fte_match_param_bits {
1854 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1856 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1858 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1860 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1862 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1864 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1866 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1868 u8 reserved_at_e00[0x200];
1872 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1873 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1874 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1875 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1876 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1879 struct mlx5_ifc_rx_hash_field_select_bits {
1880 u8 l3_prot_type[0x1];
1881 u8 l4_prot_type[0x1];
1882 u8 selected_fields[0x1e];
1886 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1887 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1891 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1892 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1895 struct mlx5_ifc_wq_bits {
1897 u8 wq_signature[0x1];
1898 u8 end_padding_mode[0x2];
1900 u8 reserved_at_8[0x18];
1902 u8 hds_skip_first_sge[0x1];
1903 u8 log2_hds_buf_size[0x3];
1904 u8 reserved_at_24[0x7];
1905 u8 page_offset[0x5];
1908 u8 reserved_at_40[0x8];
1911 u8 reserved_at_60[0x8];
1916 u8 hw_counter[0x20];
1918 u8 sw_counter[0x20];
1920 u8 reserved_at_100[0xc];
1921 u8 log_wq_stride[0x4];
1922 u8 reserved_at_110[0x3];
1923 u8 log_wq_pg_sz[0x5];
1924 u8 reserved_at_118[0x3];
1927 u8 dbr_umem_valid[0x1];
1928 u8 wq_umem_valid[0x1];
1929 u8 reserved_at_122[0x1];
1930 u8 log_hairpin_num_packets[0x5];
1931 u8 reserved_at_128[0x3];
1932 u8 log_hairpin_data_sz[0x5];
1934 u8 reserved_at_130[0x4];
1935 u8 log_wqe_num_of_strides[0x4];
1936 u8 two_byte_shift_en[0x1];
1937 u8 reserved_at_139[0x4];
1938 u8 log_wqe_stride_size[0x3];
1940 u8 reserved_at_140[0x80];
1942 u8 headers_mkey[0x20];
1944 u8 shampo_enable[0x1];
1945 u8 reserved_at_1e1[0x4];
1946 u8 log_reservation_size[0x3];
1947 u8 reserved_at_1e8[0x5];
1948 u8 log_max_num_of_packets_per_reservation[0x3];
1949 u8 reserved_at_1f0[0x6];
1950 u8 log_headers_entry_size[0x2];
1951 u8 reserved_at_1f8[0x4];
1952 u8 log_headers_buffer_entry_num[0x4];
1954 u8 reserved_at_200[0x400];
1956 struct mlx5_ifc_cmd_pas_bits pas[];
1959 struct mlx5_ifc_rq_num_bits {
1960 u8 reserved_at_0[0x8];
1964 struct mlx5_ifc_mac_address_layout_bits {
1965 u8 reserved_at_0[0x10];
1966 u8 mac_addr_47_32[0x10];
1968 u8 mac_addr_31_0[0x20];
1971 struct mlx5_ifc_vlan_layout_bits {
1972 u8 reserved_at_0[0x14];
1975 u8 reserved_at_20[0x20];
1978 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1979 u8 reserved_at_0[0xa0];
1981 u8 min_time_between_cnps[0x20];
1983 u8 reserved_at_c0[0x12];
1985 u8 reserved_at_d8[0x4];
1986 u8 cnp_prio_mode[0x1];
1987 u8 cnp_802p_prio[0x3];
1989 u8 reserved_at_e0[0x720];
1992 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1993 u8 reserved_at_0[0x60];
1995 u8 reserved_at_60[0x4];
1996 u8 clamp_tgt_rate[0x1];
1997 u8 reserved_at_65[0x3];
1998 u8 clamp_tgt_rate_after_time_inc[0x1];
1999 u8 reserved_at_69[0x17];
2001 u8 reserved_at_80[0x20];
2003 u8 rpg_time_reset[0x20];
2005 u8 rpg_byte_reset[0x20];
2007 u8 rpg_threshold[0x20];
2009 u8 rpg_max_rate[0x20];
2011 u8 rpg_ai_rate[0x20];
2013 u8 rpg_hai_rate[0x20];
2017 u8 rpg_min_dec_fac[0x20];
2019 u8 rpg_min_rate[0x20];
2021 u8 reserved_at_1c0[0xe0];
2023 u8 rate_to_set_on_first_cnp[0x20];
2027 u8 dce_tcp_rtt[0x20];
2029 u8 rate_reduce_monitor_period[0x20];
2031 u8 reserved_at_320[0x20];
2033 u8 initial_alpha_value[0x20];
2035 u8 reserved_at_360[0x4a0];
2038 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2039 u8 reserved_at_0[0x80];
2041 u8 rppp_max_rps[0x20];
2043 u8 rpg_time_reset[0x20];
2045 u8 rpg_byte_reset[0x20];
2047 u8 rpg_threshold[0x20];
2049 u8 rpg_max_rate[0x20];
2051 u8 rpg_ai_rate[0x20];
2053 u8 rpg_hai_rate[0x20];
2057 u8 rpg_min_dec_fac[0x20];
2059 u8 rpg_min_rate[0x20];
2061 u8 reserved_at_1c0[0x640];
2065 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
2066 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
2067 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
2070 struct mlx5_ifc_resize_field_select_bits {
2071 u8 resize_field_select[0x20];
2074 struct mlx5_ifc_resource_dump_bits {
2076 u8 inline_dump[0x1];
2077 u8 reserved_at_2[0xa];
2079 u8 segment_type[0x10];
2081 u8 reserved_at_20[0x10];
2088 u8 num_of_obj1[0x10];
2089 u8 num_of_obj2[0x10];
2091 u8 reserved_at_a0[0x20];
2093 u8 device_opaque[0x40];
2101 u8 inline_data[52][0x20];
2104 struct mlx5_ifc_resource_dump_menu_record_bits {
2105 u8 reserved_at_0[0x4];
2106 u8 num_of_obj2_supports_active[0x1];
2107 u8 num_of_obj2_supports_all[0x1];
2108 u8 must_have_num_of_obj2[0x1];
2109 u8 support_num_of_obj2[0x1];
2110 u8 num_of_obj1_supports_active[0x1];
2111 u8 num_of_obj1_supports_all[0x1];
2112 u8 must_have_num_of_obj1[0x1];
2113 u8 support_num_of_obj1[0x1];
2114 u8 must_have_index2[0x1];
2115 u8 support_index2[0x1];
2116 u8 must_have_index1[0x1];
2117 u8 support_index1[0x1];
2118 u8 segment_type[0x10];
2120 u8 segment_name[4][0x20];
2122 u8 index1_name[4][0x20];
2124 u8 index2_name[4][0x20];
2127 struct mlx5_ifc_resource_dump_segment_header_bits {
2129 u8 segment_type[0x10];
2132 struct mlx5_ifc_resource_dump_command_segment_bits {
2133 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2135 u8 segment_called[0x10];
2142 u8 num_of_obj1[0x10];
2143 u8 num_of_obj2[0x10];
2146 struct mlx5_ifc_resource_dump_error_segment_bits {
2147 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2149 u8 reserved_at_20[0x10];
2150 u8 syndrome_id[0x10];
2152 u8 reserved_at_40[0x40];
2157 struct mlx5_ifc_resource_dump_info_segment_bits {
2158 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2160 u8 reserved_at_20[0x18];
2161 u8 dump_version[0x8];
2163 u8 hw_version[0x20];
2165 u8 fw_version[0x20];
2168 struct mlx5_ifc_resource_dump_menu_segment_bits {
2169 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2171 u8 reserved_at_20[0x10];
2172 u8 num_of_records[0x10];
2174 struct mlx5_ifc_resource_dump_menu_record_bits record[];
2177 struct mlx5_ifc_resource_dump_resource_segment_bits {
2178 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2180 u8 reserved_at_20[0x20];
2189 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2190 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2193 struct mlx5_ifc_menu_resource_dump_response_bits {
2194 struct mlx5_ifc_resource_dump_info_segment_bits info;
2195 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2196 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2197 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2201 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2202 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2203 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2204 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2207 struct mlx5_ifc_modify_field_select_bits {
2208 u8 modify_field_select[0x20];
2211 struct mlx5_ifc_field_select_r_roce_np_bits {
2212 u8 field_select_r_roce_np[0x20];
2215 struct mlx5_ifc_field_select_r_roce_rp_bits {
2216 u8 field_select_r_roce_rp[0x20];
2220 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2221 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2222 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2223 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2224 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2225 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2226 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2227 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2228 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2229 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2232 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2233 u8 field_select_8021qaurp[0x20];
2236 struct mlx5_ifc_phys_layer_cntrs_bits {
2237 u8 time_since_last_clear_high[0x20];
2239 u8 time_since_last_clear_low[0x20];
2241 u8 symbol_errors_high[0x20];
2243 u8 symbol_errors_low[0x20];
2245 u8 sync_headers_errors_high[0x20];
2247 u8 sync_headers_errors_low[0x20];
2249 u8 edpl_bip_errors_lane0_high[0x20];
2251 u8 edpl_bip_errors_lane0_low[0x20];
2253 u8 edpl_bip_errors_lane1_high[0x20];
2255 u8 edpl_bip_errors_lane1_low[0x20];
2257 u8 edpl_bip_errors_lane2_high[0x20];
2259 u8 edpl_bip_errors_lane2_low[0x20];
2261 u8 edpl_bip_errors_lane3_high[0x20];
2263 u8 edpl_bip_errors_lane3_low[0x20];
2265 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2267 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2269 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2271 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2273 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2275 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2277 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2279 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2281 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2283 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2285 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2287 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2289 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2291 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2293 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2295 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2297 u8 rs_fec_corrected_blocks_high[0x20];
2299 u8 rs_fec_corrected_blocks_low[0x20];
2301 u8 rs_fec_uncorrectable_blocks_high[0x20];
2303 u8 rs_fec_uncorrectable_blocks_low[0x20];
2305 u8 rs_fec_no_errors_blocks_high[0x20];
2307 u8 rs_fec_no_errors_blocks_low[0x20];
2309 u8 rs_fec_single_error_blocks_high[0x20];
2311 u8 rs_fec_single_error_blocks_low[0x20];
2313 u8 rs_fec_corrected_symbols_total_high[0x20];
2315 u8 rs_fec_corrected_symbols_total_low[0x20];
2317 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2319 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2321 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2323 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2325 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2327 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2329 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2331 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2333 u8 link_down_events[0x20];
2335 u8 successful_recovery_events[0x20];
2337 u8 reserved_at_640[0x180];
2340 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2341 u8 time_since_last_clear_high[0x20];
2343 u8 time_since_last_clear_low[0x20];
2345 u8 phy_received_bits_high[0x20];
2347 u8 phy_received_bits_low[0x20];
2349 u8 phy_symbol_errors_high[0x20];
2351 u8 phy_symbol_errors_low[0x20];
2353 u8 phy_corrected_bits_high[0x20];
2355 u8 phy_corrected_bits_low[0x20];
2357 u8 phy_corrected_bits_lane0_high[0x20];
2359 u8 phy_corrected_bits_lane0_low[0x20];
2361 u8 phy_corrected_bits_lane1_high[0x20];
2363 u8 phy_corrected_bits_lane1_low[0x20];
2365 u8 phy_corrected_bits_lane2_high[0x20];
2367 u8 phy_corrected_bits_lane2_low[0x20];
2369 u8 phy_corrected_bits_lane3_high[0x20];
2371 u8 phy_corrected_bits_lane3_low[0x20];
2373 u8 reserved_at_200[0x5c0];
2376 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2377 u8 symbol_error_counter[0x10];
2379 u8 link_error_recovery_counter[0x8];
2381 u8 link_downed_counter[0x8];
2383 u8 port_rcv_errors[0x10];
2385 u8 port_rcv_remote_physical_errors[0x10];
2387 u8 port_rcv_switch_relay_errors[0x10];
2389 u8 port_xmit_discards[0x10];
2391 u8 port_xmit_constraint_errors[0x8];
2393 u8 port_rcv_constraint_errors[0x8];
2395 u8 reserved_at_70[0x8];
2397 u8 link_overrun_errors[0x8];
2399 u8 reserved_at_80[0x10];
2401 u8 vl_15_dropped[0x10];
2403 u8 reserved_at_a0[0x80];
2405 u8 port_xmit_wait[0x20];
2408 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2409 u8 transmit_queue_high[0x20];
2411 u8 transmit_queue_low[0x20];
2413 u8 no_buffer_discard_uc_high[0x20];
2415 u8 no_buffer_discard_uc_low[0x20];
2417 u8 reserved_at_80[0x740];
2420 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2421 u8 wred_discard_high[0x20];
2423 u8 wred_discard_low[0x20];
2425 u8 ecn_marked_tc_high[0x20];
2427 u8 ecn_marked_tc_low[0x20];
2429 u8 reserved_at_80[0x740];
2432 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2433 u8 rx_octets_high[0x20];
2435 u8 rx_octets_low[0x20];
2437 u8 reserved_at_40[0xc0];
2439 u8 rx_frames_high[0x20];
2441 u8 rx_frames_low[0x20];
2443 u8 tx_octets_high[0x20];
2445 u8 tx_octets_low[0x20];
2447 u8 reserved_at_180[0xc0];
2449 u8 tx_frames_high[0x20];
2451 u8 tx_frames_low[0x20];
2453 u8 rx_pause_high[0x20];
2455 u8 rx_pause_low[0x20];
2457 u8 rx_pause_duration_high[0x20];
2459 u8 rx_pause_duration_low[0x20];
2461 u8 tx_pause_high[0x20];
2463 u8 tx_pause_low[0x20];
2465 u8 tx_pause_duration_high[0x20];
2467 u8 tx_pause_duration_low[0x20];
2469 u8 rx_pause_transition_high[0x20];
2471 u8 rx_pause_transition_low[0x20];
2473 u8 rx_discards_high[0x20];
2475 u8 rx_discards_low[0x20];
2477 u8 device_stall_minor_watermark_cnt_high[0x20];
2479 u8 device_stall_minor_watermark_cnt_low[0x20];
2481 u8 device_stall_critical_watermark_cnt_high[0x20];
2483 u8 device_stall_critical_watermark_cnt_low[0x20];
2485 u8 reserved_at_480[0x340];
2488 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2489 u8 port_transmit_wait_high[0x20];
2491 u8 port_transmit_wait_low[0x20];
2493 u8 reserved_at_40[0x100];
2495 u8 rx_buffer_almost_full_high[0x20];
2497 u8 rx_buffer_almost_full_low[0x20];
2499 u8 rx_buffer_full_high[0x20];
2501 u8 rx_buffer_full_low[0x20];
2503 u8 rx_icrc_encapsulated_high[0x20];
2505 u8 rx_icrc_encapsulated_low[0x20];
2507 u8 reserved_at_200[0x5c0];
2510 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2511 u8 dot3stats_alignment_errors_high[0x20];
2513 u8 dot3stats_alignment_errors_low[0x20];
2515 u8 dot3stats_fcs_errors_high[0x20];
2517 u8 dot3stats_fcs_errors_low[0x20];
2519 u8 dot3stats_single_collision_frames_high[0x20];
2521 u8 dot3stats_single_collision_frames_low[0x20];
2523 u8 dot3stats_multiple_collision_frames_high[0x20];
2525 u8 dot3stats_multiple_collision_frames_low[0x20];
2527 u8 dot3stats_sqe_test_errors_high[0x20];
2529 u8 dot3stats_sqe_test_errors_low[0x20];
2531 u8 dot3stats_deferred_transmissions_high[0x20];
2533 u8 dot3stats_deferred_transmissions_low[0x20];
2535 u8 dot3stats_late_collisions_high[0x20];
2537 u8 dot3stats_late_collisions_low[0x20];
2539 u8 dot3stats_excessive_collisions_high[0x20];
2541 u8 dot3stats_excessive_collisions_low[0x20];
2543 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2545 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2547 u8 dot3stats_carrier_sense_errors_high[0x20];
2549 u8 dot3stats_carrier_sense_errors_low[0x20];
2551 u8 dot3stats_frame_too_longs_high[0x20];
2553 u8 dot3stats_frame_too_longs_low[0x20];
2555 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2557 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2559 u8 dot3stats_symbol_errors_high[0x20];
2561 u8 dot3stats_symbol_errors_low[0x20];
2563 u8 dot3control_in_unknown_opcodes_high[0x20];
2565 u8 dot3control_in_unknown_opcodes_low[0x20];
2567 u8 dot3in_pause_frames_high[0x20];
2569 u8 dot3in_pause_frames_low[0x20];
2571 u8 dot3out_pause_frames_high[0x20];
2573 u8 dot3out_pause_frames_low[0x20];
2575 u8 reserved_at_400[0x3c0];
2578 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2579 u8 ether_stats_drop_events_high[0x20];
2581 u8 ether_stats_drop_events_low[0x20];
2583 u8 ether_stats_octets_high[0x20];
2585 u8 ether_stats_octets_low[0x20];
2587 u8 ether_stats_pkts_high[0x20];
2589 u8 ether_stats_pkts_low[0x20];
2591 u8 ether_stats_broadcast_pkts_high[0x20];
2593 u8 ether_stats_broadcast_pkts_low[0x20];
2595 u8 ether_stats_multicast_pkts_high[0x20];
2597 u8 ether_stats_multicast_pkts_low[0x20];
2599 u8 ether_stats_crc_align_errors_high[0x20];
2601 u8 ether_stats_crc_align_errors_low[0x20];
2603 u8 ether_stats_undersize_pkts_high[0x20];
2605 u8 ether_stats_undersize_pkts_low[0x20];
2607 u8 ether_stats_oversize_pkts_high[0x20];
2609 u8 ether_stats_oversize_pkts_low[0x20];
2611 u8 ether_stats_fragments_high[0x20];
2613 u8 ether_stats_fragments_low[0x20];
2615 u8 ether_stats_jabbers_high[0x20];
2617 u8 ether_stats_jabbers_low[0x20];
2619 u8 ether_stats_collisions_high[0x20];
2621 u8 ether_stats_collisions_low[0x20];
2623 u8 ether_stats_pkts64octets_high[0x20];
2625 u8 ether_stats_pkts64octets_low[0x20];
2627 u8 ether_stats_pkts65to127octets_high[0x20];
2629 u8 ether_stats_pkts65to127octets_low[0x20];
2631 u8 ether_stats_pkts128to255octets_high[0x20];
2633 u8 ether_stats_pkts128to255octets_low[0x20];
2635 u8 ether_stats_pkts256to511octets_high[0x20];
2637 u8 ether_stats_pkts256to511octets_low[0x20];
2639 u8 ether_stats_pkts512to1023octets_high[0x20];
2641 u8 ether_stats_pkts512to1023octets_low[0x20];
2643 u8 ether_stats_pkts1024to1518octets_high[0x20];
2645 u8 ether_stats_pkts1024to1518octets_low[0x20];
2647 u8 ether_stats_pkts1519to2047octets_high[0x20];
2649 u8 ether_stats_pkts1519to2047octets_low[0x20];
2651 u8 ether_stats_pkts2048to4095octets_high[0x20];
2653 u8 ether_stats_pkts2048to4095octets_low[0x20];
2655 u8 ether_stats_pkts4096to8191octets_high[0x20];
2657 u8 ether_stats_pkts4096to8191octets_low[0x20];
2659 u8 ether_stats_pkts8192to10239octets_high[0x20];
2661 u8 ether_stats_pkts8192to10239octets_low[0x20];
2663 u8 reserved_at_540[0x280];
2666 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2667 u8 if_in_octets_high[0x20];
2669 u8 if_in_octets_low[0x20];
2671 u8 if_in_ucast_pkts_high[0x20];
2673 u8 if_in_ucast_pkts_low[0x20];
2675 u8 if_in_discards_high[0x20];
2677 u8 if_in_discards_low[0x20];
2679 u8 if_in_errors_high[0x20];
2681 u8 if_in_errors_low[0x20];
2683 u8 if_in_unknown_protos_high[0x20];
2685 u8 if_in_unknown_protos_low[0x20];
2687 u8 if_out_octets_high[0x20];
2689 u8 if_out_octets_low[0x20];
2691 u8 if_out_ucast_pkts_high[0x20];
2693 u8 if_out_ucast_pkts_low[0x20];
2695 u8 if_out_discards_high[0x20];
2697 u8 if_out_discards_low[0x20];
2699 u8 if_out_errors_high[0x20];
2701 u8 if_out_errors_low[0x20];
2703 u8 if_in_multicast_pkts_high[0x20];
2705 u8 if_in_multicast_pkts_low[0x20];
2707 u8 if_in_broadcast_pkts_high[0x20];
2709 u8 if_in_broadcast_pkts_low[0x20];
2711 u8 if_out_multicast_pkts_high[0x20];
2713 u8 if_out_multicast_pkts_low[0x20];
2715 u8 if_out_broadcast_pkts_high[0x20];
2717 u8 if_out_broadcast_pkts_low[0x20];
2719 u8 reserved_at_340[0x480];
2722 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2723 u8 a_frames_transmitted_ok_high[0x20];
2725 u8 a_frames_transmitted_ok_low[0x20];
2727 u8 a_frames_received_ok_high[0x20];
2729 u8 a_frames_received_ok_low[0x20];
2731 u8 a_frame_check_sequence_errors_high[0x20];
2733 u8 a_frame_check_sequence_errors_low[0x20];
2735 u8 a_alignment_errors_high[0x20];
2737 u8 a_alignment_errors_low[0x20];
2739 u8 a_octets_transmitted_ok_high[0x20];
2741 u8 a_octets_transmitted_ok_low[0x20];
2743 u8 a_octets_received_ok_high[0x20];
2745 u8 a_octets_received_ok_low[0x20];
2747 u8 a_multicast_frames_xmitted_ok_high[0x20];
2749 u8 a_multicast_frames_xmitted_ok_low[0x20];
2751 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2753 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2755 u8 a_multicast_frames_received_ok_high[0x20];
2757 u8 a_multicast_frames_received_ok_low[0x20];
2759 u8 a_broadcast_frames_received_ok_high[0x20];
2761 u8 a_broadcast_frames_received_ok_low[0x20];
2763 u8 a_in_range_length_errors_high[0x20];
2765 u8 a_in_range_length_errors_low[0x20];
2767 u8 a_out_of_range_length_field_high[0x20];
2769 u8 a_out_of_range_length_field_low[0x20];
2771 u8 a_frame_too_long_errors_high[0x20];
2773 u8 a_frame_too_long_errors_low[0x20];
2775 u8 a_symbol_error_during_carrier_high[0x20];
2777 u8 a_symbol_error_during_carrier_low[0x20];
2779 u8 a_mac_control_frames_transmitted_high[0x20];
2781 u8 a_mac_control_frames_transmitted_low[0x20];
2783 u8 a_mac_control_frames_received_high[0x20];
2785 u8 a_mac_control_frames_received_low[0x20];
2787 u8 a_unsupported_opcodes_received_high[0x20];
2789 u8 a_unsupported_opcodes_received_low[0x20];
2791 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2793 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2795 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2797 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2799 u8 reserved_at_4c0[0x300];
2802 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2803 u8 life_time_counter_high[0x20];
2805 u8 life_time_counter_low[0x20];
2811 u8 l0_to_recovery_eieos[0x20];
2813 u8 l0_to_recovery_ts[0x20];
2815 u8 l0_to_recovery_framing[0x20];
2817 u8 l0_to_recovery_retrain[0x20];
2819 u8 crc_error_dllp[0x20];
2821 u8 crc_error_tlp[0x20];
2823 u8 tx_overflow_buffer_pkt_high[0x20];
2825 u8 tx_overflow_buffer_pkt_low[0x20];
2827 u8 outbound_stalled_reads[0x20];
2829 u8 outbound_stalled_writes[0x20];
2831 u8 outbound_stalled_reads_events[0x20];
2833 u8 outbound_stalled_writes_events[0x20];
2835 u8 reserved_at_200[0x5c0];
2838 struct mlx5_ifc_cmd_inter_comp_event_bits {
2839 u8 command_completion_vector[0x20];
2841 u8 reserved_at_20[0xc0];
2844 struct mlx5_ifc_stall_vl_event_bits {
2845 u8 reserved_at_0[0x18];
2847 u8 reserved_at_19[0x3];
2850 u8 reserved_at_20[0xa0];
2853 struct mlx5_ifc_db_bf_congestion_event_bits {
2854 u8 event_subtype[0x8];
2855 u8 reserved_at_8[0x8];
2856 u8 congestion_level[0x8];
2857 u8 reserved_at_18[0x8];
2859 u8 reserved_at_20[0xa0];
2862 struct mlx5_ifc_gpio_event_bits {
2863 u8 reserved_at_0[0x60];
2865 u8 gpio_event_hi[0x20];
2867 u8 gpio_event_lo[0x20];
2869 u8 reserved_at_a0[0x40];
2872 struct mlx5_ifc_port_state_change_event_bits {
2873 u8 reserved_at_0[0x40];
2876 u8 reserved_at_44[0x1c];
2878 u8 reserved_at_60[0x80];
2881 struct mlx5_ifc_dropped_packet_logged_bits {
2882 u8 reserved_at_0[0xe0];
2885 struct mlx5_ifc_default_timeout_bits {
2886 u8 to_multiplier[0x3];
2887 u8 reserved_at_3[0x9];
2891 struct mlx5_ifc_dtor_reg_bits {
2892 u8 reserved_at_0[0x20];
2894 struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
2896 u8 reserved_at_40[0x60];
2898 struct mlx5_ifc_default_timeout_bits health_poll_to;
2900 struct mlx5_ifc_default_timeout_bits full_crdump_to;
2902 struct mlx5_ifc_default_timeout_bits fw_reset_to;
2904 struct mlx5_ifc_default_timeout_bits flush_on_err_to;
2906 struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
2908 struct mlx5_ifc_default_timeout_bits tear_down_to;
2910 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
2912 struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
2914 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
2916 u8 reserved_at_1c0[0x40];
2920 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2921 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2924 struct mlx5_ifc_cq_error_bits {
2925 u8 reserved_at_0[0x8];
2928 u8 reserved_at_20[0x20];
2930 u8 reserved_at_40[0x18];
2933 u8 reserved_at_60[0x80];
2936 struct mlx5_ifc_rdma_page_fault_event_bits {
2937 u8 bytes_committed[0x20];
2941 u8 reserved_at_40[0x10];
2942 u8 packet_len[0x10];
2944 u8 rdma_op_len[0x20];
2948 u8 reserved_at_c0[0x5];
2955 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2956 u8 bytes_committed[0x20];
2958 u8 reserved_at_20[0x10];
2961 u8 reserved_at_40[0x10];
2964 u8 reserved_at_60[0x60];
2966 u8 reserved_at_c0[0x5];
2973 struct mlx5_ifc_qp_events_bits {
2974 u8 reserved_at_0[0xa0];
2977 u8 reserved_at_a8[0x18];
2979 u8 reserved_at_c0[0x8];
2980 u8 qpn_rqn_sqn[0x18];
2983 struct mlx5_ifc_dct_events_bits {
2984 u8 reserved_at_0[0xc0];
2986 u8 reserved_at_c0[0x8];
2987 u8 dct_number[0x18];
2990 struct mlx5_ifc_comp_event_bits {
2991 u8 reserved_at_0[0xc0];
2993 u8 reserved_at_c0[0x8];
2998 MLX5_QPC_STATE_RST = 0x0,
2999 MLX5_QPC_STATE_INIT = 0x1,
3000 MLX5_QPC_STATE_RTR = 0x2,
3001 MLX5_QPC_STATE_RTS = 0x3,
3002 MLX5_QPC_STATE_SQER = 0x4,
3003 MLX5_QPC_STATE_ERR = 0x6,
3004 MLX5_QPC_STATE_SQD = 0x7,
3005 MLX5_QPC_STATE_SUSPENDED = 0x9,
3009 MLX5_QPC_ST_RC = 0x0,
3010 MLX5_QPC_ST_UC = 0x1,
3011 MLX5_QPC_ST_UD = 0x2,
3012 MLX5_QPC_ST_XRC = 0x3,
3013 MLX5_QPC_ST_DCI = 0x5,
3014 MLX5_QPC_ST_QP0 = 0x7,
3015 MLX5_QPC_ST_QP1 = 0x8,
3016 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
3017 MLX5_QPC_ST_REG_UMR = 0xc,
3021 MLX5_QPC_PM_STATE_ARMED = 0x0,
3022 MLX5_QPC_PM_STATE_REARM = 0x1,
3023 MLX5_QPC_PM_STATE_RESERVED = 0x2,
3024 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
3028 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
3032 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
3033 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
3037 MLX5_QPC_MTU_256_BYTES = 0x1,
3038 MLX5_QPC_MTU_512_BYTES = 0x2,
3039 MLX5_QPC_MTU_1K_BYTES = 0x3,
3040 MLX5_QPC_MTU_2K_BYTES = 0x4,
3041 MLX5_QPC_MTU_4K_BYTES = 0x5,
3042 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
3046 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
3047 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
3048 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
3049 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
3050 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
3051 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
3052 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
3053 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
3057 MLX5_QPC_CS_REQ_DISABLE = 0x0,
3058 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
3059 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
3063 MLX5_QPC_CS_RES_DISABLE = 0x0,
3064 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
3065 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
3069 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3070 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1,
3071 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
3074 struct mlx5_ifc_qpc_bits {
3076 u8 lag_tx_port_affinity[0x4];
3078 u8 reserved_at_10[0x2];
3079 u8 isolate_vl_tc[0x1];
3081 u8 reserved_at_15[0x1];
3082 u8 req_e2e_credit_mode[0x2];
3083 u8 offload_type[0x4];
3084 u8 end_padding_mode[0x2];
3085 u8 reserved_at_1e[0x2];
3087 u8 wq_signature[0x1];
3088 u8 block_lb_mc[0x1];
3089 u8 atomic_like_write_en[0x1];
3090 u8 latency_sensitive[0x1];
3091 u8 reserved_at_24[0x1];
3092 u8 drain_sigerr[0x1];
3093 u8 reserved_at_26[0x2];
3097 u8 log_msg_max[0x5];
3098 u8 reserved_at_48[0x1];
3099 u8 log_rq_size[0x4];
3100 u8 log_rq_stride[0x3];
3102 u8 log_sq_size[0x4];
3103 u8 reserved_at_55[0x3];
3105 u8 reserved_at_5a[0x1];
3107 u8 ulp_stateless_offload_mode[0x4];
3109 u8 counter_set_id[0x8];
3112 u8 reserved_at_80[0x8];
3113 u8 user_index[0x18];
3115 u8 reserved_at_a0[0x3];
3116 u8 log_page_size[0x5];
3117 u8 remote_qpn[0x18];
3119 struct mlx5_ifc_ads_bits primary_address_path;
3121 struct mlx5_ifc_ads_bits secondary_address_path;
3123 u8 log_ack_req_freq[0x4];
3124 u8 reserved_at_384[0x4];
3125 u8 log_sra_max[0x3];
3126 u8 reserved_at_38b[0x2];
3127 u8 retry_count[0x3];
3129 u8 reserved_at_393[0x1];
3131 u8 cur_rnr_retry[0x3];
3132 u8 cur_retry_count[0x3];
3133 u8 reserved_at_39b[0x5];
3135 u8 reserved_at_3a0[0x20];
3137 u8 reserved_at_3c0[0x8];
3138 u8 next_send_psn[0x18];
3140 u8 reserved_at_3e0[0x3];
3141 u8 log_num_dci_stream_channels[0x5];
3144 u8 reserved_at_400[0x3];
3145 u8 log_num_dci_errored_streams[0x5];
3148 u8 reserved_at_420[0x20];
3150 u8 reserved_at_440[0x8];
3151 u8 last_acked_psn[0x18];
3153 u8 reserved_at_460[0x8];
3156 u8 reserved_at_480[0x8];
3157 u8 log_rra_max[0x3];
3158 u8 reserved_at_48b[0x1];
3159 u8 atomic_mode[0x4];
3163 u8 reserved_at_493[0x1];
3164 u8 page_offset[0x6];
3165 u8 reserved_at_49a[0x3];
3166 u8 cd_slave_receive[0x1];
3167 u8 cd_slave_send[0x1];
3170 u8 reserved_at_4a0[0x3];
3171 u8 min_rnr_nak[0x5];
3172 u8 next_rcv_psn[0x18];
3174 u8 reserved_at_4c0[0x8];
3177 u8 reserved_at_4e0[0x8];
3184 u8 reserved_at_560[0x5];
3186 u8 srqn_rmpn_xrqn[0x18];
3188 u8 reserved_at_580[0x8];
3191 u8 hw_sq_wqebb_counter[0x10];
3192 u8 sw_sq_wqebb_counter[0x10];
3194 u8 hw_rq_counter[0x20];
3196 u8 sw_rq_counter[0x20];
3198 u8 reserved_at_600[0x20];
3200 u8 reserved_at_620[0xf];
3205 u8 dc_access_key[0x40];
3207 u8 reserved_at_680[0x3];
3208 u8 dbr_umem_valid[0x1];
3210 u8 reserved_at_684[0xbc];
3213 struct mlx5_ifc_roce_addr_layout_bits {
3214 u8 source_l3_address[16][0x8];
3216 u8 reserved_at_80[0x3];
3219 u8 source_mac_47_32[0x10];
3221 u8 source_mac_31_0[0x20];
3223 u8 reserved_at_c0[0x14];
3224 u8 roce_l3_type[0x4];
3225 u8 roce_version[0x8];
3227 u8 reserved_at_e0[0x20];
3230 struct mlx5_ifc_shampo_cap_bits {
3231 u8 reserved_at_0[0x3];
3232 u8 shampo_log_max_reservation_size[0x5];
3233 u8 reserved_at_8[0x3];
3234 u8 shampo_log_min_reservation_size[0x5];
3235 u8 shampo_min_mss_size[0x10];
3237 u8 reserved_at_20[0x3];
3238 u8 shampo_max_log_headers_entry_size[0x5];
3239 u8 reserved_at_28[0x18];
3241 u8 reserved_at_40[0x7c0];
3244 union mlx5_ifc_hca_cap_union_bits {
3245 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3246 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3247 struct mlx5_ifc_odp_cap_bits odp_cap;
3248 struct mlx5_ifc_atomic_caps_bits atomic_caps;
3249 struct mlx5_ifc_roce_cap_bits roce_cap;
3250 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3251 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3252 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3253 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3254 struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3255 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3256 struct mlx5_ifc_qos_cap_bits qos_cap;
3257 struct mlx5_ifc_debug_cap_bits debug_cap;
3258 struct mlx5_ifc_fpga_cap_bits fpga_cap;
3259 struct mlx5_ifc_tls_cap_bits tls_cap;
3260 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3261 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3262 struct mlx5_ifc_shampo_cap_bits shampo_cap;
3263 u8 reserved_at_0[0x8000];
3267 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3268 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3269 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
3270 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
3271 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3272 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
3273 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
3274 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3275 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3276 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3277 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3278 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3279 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3283 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3284 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3285 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3288 struct mlx5_ifc_vlan_bits {
3295 struct mlx5_ifc_flow_context_bits {
3296 struct mlx5_ifc_vlan_bits push_vlan;
3300 u8 reserved_at_40[0x8];
3303 u8 reserved_at_60[0x10];
3306 u8 extended_destination[0x1];
3307 u8 reserved_at_81[0x1];
3308 u8 flow_source[0x2];
3309 u8 reserved_at_84[0x4];
3310 u8 destination_list_size[0x18];
3312 u8 reserved_at_a0[0x8];
3313 u8 flow_counter_list_size[0x18];
3315 u8 packet_reformat_id[0x20];
3317 u8 modify_header_id[0x20];
3319 struct mlx5_ifc_vlan_bits push_vlan_2;
3321 u8 ipsec_obj_id[0x20];
3322 u8 reserved_at_140[0xc0];
3324 struct mlx5_ifc_fte_match_param_bits match_value;
3326 u8 reserved_at_1200[0x600];
3328 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3332 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3333 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3336 struct mlx5_ifc_xrc_srqc_bits {
3338 u8 log_xrc_srq_size[0x4];
3339 u8 reserved_at_8[0x18];
3341 u8 wq_signature[0x1];
3343 u8 reserved_at_22[0x1];
3345 u8 basic_cyclic_rcv_wqe[0x1];
3346 u8 log_rq_stride[0x3];
3349 u8 page_offset[0x6];
3350 u8 reserved_at_46[0x1];
3351 u8 dbr_umem_valid[0x1];
3354 u8 reserved_at_60[0x20];
3356 u8 user_index_equal_xrc_srqn[0x1];
3357 u8 reserved_at_81[0x1];
3358 u8 log_page_size[0x6];
3359 u8 user_index[0x18];
3361 u8 reserved_at_a0[0x20];
3363 u8 reserved_at_c0[0x8];
3369 u8 reserved_at_100[0x40];
3371 u8 db_record_addr_h[0x20];
3373 u8 db_record_addr_l[0x1e];
3374 u8 reserved_at_17e[0x2];
3376 u8 reserved_at_180[0x80];
3379 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3380 u8 counter_error_queues[0x20];
3382 u8 total_error_queues[0x20];
3384 u8 send_queue_priority_update_flow[0x20];
3386 u8 reserved_at_60[0x20];
3388 u8 nic_receive_steering_discard[0x40];
3390 u8 receive_discard_vport_down[0x40];
3392 u8 transmit_discard_vport_down[0x40];
3394 u8 reserved_at_140[0xa0];
3396 u8 internal_rq_out_of_buffer[0x20];
3398 u8 reserved_at_200[0xe00];
3401 struct mlx5_ifc_traffic_counter_bits {
3407 struct mlx5_ifc_tisc_bits {
3408 u8 strict_lag_tx_port_affinity[0x1];
3410 u8 reserved_at_2[0x2];
3411 u8 lag_tx_port_affinity[0x04];
3413 u8 reserved_at_8[0x4];
3415 u8 reserved_at_10[0x10];
3417 u8 reserved_at_20[0x100];
3419 u8 reserved_at_120[0x8];
3420 u8 transport_domain[0x18];
3422 u8 reserved_at_140[0x8];
3423 u8 underlay_qpn[0x18];
3425 u8 reserved_at_160[0x8];
3428 u8 reserved_at_180[0x380];
3432 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3433 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3437 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
3438 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1),
3442 MLX5_RX_HASH_FN_NONE = 0x0,
3443 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3444 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
3448 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3449 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
3452 struct mlx5_ifc_tirc_bits {
3453 u8 reserved_at_0[0x20];
3457 u8 reserved_at_25[0x1b];
3459 u8 reserved_at_40[0x40];
3461 u8 reserved_at_80[0x4];
3462 u8 lro_timeout_period_usecs[0x10];
3463 u8 packet_merge_mask[0x4];
3464 u8 lro_max_ip_payload_size[0x8];
3466 u8 reserved_at_a0[0x40];
3468 u8 reserved_at_e0[0x8];
3469 u8 inline_rqn[0x18];
3471 u8 rx_hash_symmetric[0x1];
3472 u8 reserved_at_101[0x1];
3473 u8 tunneled_offload_en[0x1];
3474 u8 reserved_at_103[0x5];
3475 u8 indirect_table[0x18];
3478 u8 reserved_at_124[0x2];
3479 u8 self_lb_block[0x2];
3480 u8 transport_domain[0x18];
3482 u8 rx_hash_toeplitz_key[10][0x20];
3484 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3486 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3488 u8 reserved_at_2c0[0x4c0];
3492 MLX5_SRQC_STATE_GOOD = 0x0,
3493 MLX5_SRQC_STATE_ERROR = 0x1,
3496 struct mlx5_ifc_srqc_bits {
3498 u8 log_srq_size[0x4];
3499 u8 reserved_at_8[0x18];
3501 u8 wq_signature[0x1];
3503 u8 reserved_at_22[0x1];
3505 u8 reserved_at_24[0x1];
3506 u8 log_rq_stride[0x3];
3509 u8 page_offset[0x6];
3510 u8 reserved_at_46[0x2];
3513 u8 reserved_at_60[0x20];
3515 u8 reserved_at_80[0x2];
3516 u8 log_page_size[0x6];
3517 u8 reserved_at_88[0x18];
3519 u8 reserved_at_a0[0x20];
3521 u8 reserved_at_c0[0x8];
3527 u8 reserved_at_100[0x40];
3531 u8 reserved_at_180[0x80];
3535 MLX5_SQC_STATE_RST = 0x0,
3536 MLX5_SQC_STATE_RDY = 0x1,
3537 MLX5_SQC_STATE_ERR = 0x3,
3540 struct mlx5_ifc_sqc_bits {
3544 u8 flush_in_error_en[0x1];
3545 u8 allow_multi_pkt_send_wqe[0x1];
3546 u8 min_wqe_inline_mode[0x3];
3551 u8 reserved_at_f[0xb];
3553 u8 reserved_at_1c[0x4];
3555 u8 reserved_at_20[0x8];
3556 u8 user_index[0x18];
3558 u8 reserved_at_40[0x8];
3561 u8 reserved_at_60[0x8];
3562 u8 hairpin_peer_rq[0x18];
3564 u8 reserved_at_80[0x10];
3565 u8 hairpin_peer_vhca[0x10];
3567 u8 reserved_at_a0[0x20];
3569 u8 reserved_at_c0[0x8];
3570 u8 ts_cqe_to_dest_cqn[0x18];
3572 u8 reserved_at_e0[0x10];
3573 u8 packet_pacing_rate_limit_index[0x10];
3574 u8 tis_lst_sz[0x10];
3575 u8 qos_queue_group_id[0x10];
3577 u8 reserved_at_120[0x40];
3579 u8 reserved_at_160[0x8];
3582 struct mlx5_ifc_wq_bits wq;
3586 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3587 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3588 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3589 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3590 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3594 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3595 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3596 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3597 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3600 struct mlx5_ifc_scheduling_context_bits {
3601 u8 element_type[0x8];
3602 u8 reserved_at_8[0x18];
3604 u8 element_attributes[0x20];
3606 u8 parent_element_id[0x20];
3608 u8 reserved_at_60[0x40];
3612 u8 max_average_bw[0x20];
3614 u8 reserved_at_e0[0x120];
3617 struct mlx5_ifc_rqtc_bits {
3618 u8 reserved_at_0[0xa0];
3620 u8 reserved_at_a0[0x5];
3621 u8 list_q_type[0x3];
3622 u8 reserved_at_a8[0x8];
3623 u8 rqt_max_size[0x10];
3625 u8 rq_vhca_id_format[0x1];
3626 u8 reserved_at_c1[0xf];
3627 u8 rqt_actual_size[0x10];
3629 u8 reserved_at_e0[0x6a0];
3631 struct mlx5_ifc_rq_num_bits rq_num[];
3635 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3636 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3640 MLX5_RQC_STATE_RST = 0x0,
3641 MLX5_RQC_STATE_RDY = 0x1,
3642 MLX5_RQC_STATE_ERR = 0x3,
3646 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0,
3647 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1,
3648 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2,
3652 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0,
3653 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1,
3654 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2,
3657 struct mlx5_ifc_rqc_bits {
3659 u8 delay_drop_en[0x1];
3660 u8 scatter_fcs[0x1];
3662 u8 mem_rq_type[0x4];
3664 u8 reserved_at_c[0x1];
3665 u8 flush_in_error_en[0x1];
3667 u8 reserved_at_f[0xb];
3669 u8 reserved_at_1c[0x4];
3671 u8 reserved_at_20[0x8];
3672 u8 user_index[0x18];
3674 u8 reserved_at_40[0x8];
3677 u8 counter_set_id[0x8];
3678 u8 reserved_at_68[0x18];
3680 u8 reserved_at_80[0x8];
3683 u8 reserved_at_a0[0x8];
3684 u8 hairpin_peer_sq[0x18];
3686 u8 reserved_at_c0[0x10];
3687 u8 hairpin_peer_vhca[0x10];
3689 u8 reserved_at_e0[0x46];
3690 u8 shampo_no_match_alignment_granularity[0x2];
3691 u8 reserved_at_128[0x6];
3692 u8 shampo_match_criteria_type[0x2];
3693 u8 reservation_timeout[0x10];
3695 u8 reserved_at_140[0x40];
3697 struct mlx5_ifc_wq_bits wq;
3701 MLX5_RMPC_STATE_RDY = 0x1,
3702 MLX5_RMPC_STATE_ERR = 0x3,
3705 struct mlx5_ifc_rmpc_bits {
3706 u8 reserved_at_0[0x8];
3708 u8 reserved_at_c[0x14];
3710 u8 basic_cyclic_rcv_wqe[0x1];
3711 u8 reserved_at_21[0x1f];
3713 u8 reserved_at_40[0x140];
3715 struct mlx5_ifc_wq_bits wq;
3718 struct mlx5_ifc_nic_vport_context_bits {
3719 u8 reserved_at_0[0x5];
3720 u8 min_wqe_inline_mode[0x3];
3721 u8 reserved_at_8[0x15];
3722 u8 disable_mc_local_lb[0x1];
3723 u8 disable_uc_local_lb[0x1];
3726 u8 arm_change_event[0x1];
3727 u8 reserved_at_21[0x1a];
3728 u8 event_on_mtu[0x1];
3729 u8 event_on_promisc_change[0x1];
3730 u8 event_on_vlan_change[0x1];
3731 u8 event_on_mc_address_change[0x1];
3732 u8 event_on_uc_address_change[0x1];
3734 u8 reserved_at_40[0xc];
3736 u8 affiliation_criteria[0x4];
3737 u8 affiliated_vhca_id[0x10];
3739 u8 reserved_at_60[0xd0];
3743 u8 system_image_guid[0x40];
3747 u8 reserved_at_200[0x140];
3748 u8 qkey_violation_counter[0x10];
3749 u8 reserved_at_350[0x430];
3753 u8 promisc_all[0x1];
3754 u8 reserved_at_783[0x2];
3755 u8 allowed_list_type[0x3];
3756 u8 reserved_at_788[0xc];
3757 u8 allowed_list_size[0xc];
3759 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3761 u8 reserved_at_7e0[0x20];
3763 u8 current_uc_mac_address[][0x40];
3767 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3768 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3769 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3770 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3771 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3772 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3775 struct mlx5_ifc_mkc_bits {
3776 u8 reserved_at_0[0x1];
3778 u8 reserved_at_2[0x1];
3779 u8 access_mode_4_2[0x3];
3780 u8 reserved_at_6[0x7];
3781 u8 relaxed_ordering_write[0x1];
3782 u8 reserved_at_e[0x1];
3783 u8 small_fence_on_rdma_read_response[0x1];
3790 u8 access_mode_1_0[0x2];
3791 u8 reserved_at_18[0x8];
3796 u8 reserved_at_40[0x20];
3801 u8 reserved_at_63[0x2];
3802 u8 expected_sigerr_count[0x1];
3803 u8 reserved_at_66[0x1];
3807 u8 start_addr[0x40];
3811 u8 bsf_octword_size[0x20];
3813 u8 reserved_at_120[0x80];
3815 u8 translations_octword_size[0x20];
3817 u8 reserved_at_1c0[0x19];
3818 u8 relaxed_ordering_read[0x1];
3819 u8 reserved_at_1d9[0x1];
3820 u8 log_page_size[0x5];
3822 u8 reserved_at_1e0[0x20];
3825 struct mlx5_ifc_pkey_bits {
3826 u8 reserved_at_0[0x10];
3830 struct mlx5_ifc_array128_auto_bits {
3831 u8 array128_auto[16][0x8];
3834 struct mlx5_ifc_hca_vport_context_bits {
3835 u8 field_select[0x20];
3837 u8 reserved_at_20[0xe0];
3839 u8 sm_virt_aware[0x1];
3842 u8 grh_required[0x1];
3843 u8 reserved_at_104[0xc];
3844 u8 port_physical_state[0x4];
3845 u8 vport_state_policy[0x4];
3847 u8 vport_state[0x4];
3849 u8 reserved_at_120[0x20];
3851 u8 system_image_guid[0x40];
3859 u8 cap_mask1_field_select[0x20];
3863 u8 cap_mask2_field_select[0x20];
3865 u8 reserved_at_280[0x80];
3868 u8 reserved_at_310[0x4];
3869 u8 init_type_reply[0x4];
3871 u8 subnet_timeout[0x5];
3875 u8 reserved_at_334[0xc];
3877 u8 qkey_violation_counter[0x10];
3878 u8 pkey_violation_counter[0x10];
3880 u8 reserved_at_360[0xca0];
3883 struct mlx5_ifc_esw_vport_context_bits {
3884 u8 fdb_to_vport_reg_c[0x1];
3885 u8 reserved_at_1[0x2];
3886 u8 vport_svlan_strip[0x1];
3887 u8 vport_cvlan_strip[0x1];
3888 u8 vport_svlan_insert[0x1];
3889 u8 vport_cvlan_insert[0x2];
3890 u8 fdb_to_vport_reg_c_id[0x8];
3891 u8 reserved_at_10[0x10];
3893 u8 reserved_at_20[0x20];
3902 u8 reserved_at_60[0x720];
3904 u8 sw_steering_vport_icm_address_rx[0x40];
3906 u8 sw_steering_vport_icm_address_tx[0x40];
3910 MLX5_EQC_STATUS_OK = 0x0,
3911 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3915 MLX5_EQC_ST_ARMED = 0x9,
3916 MLX5_EQC_ST_FIRED = 0xa,
3919 struct mlx5_ifc_eqc_bits {
3921 u8 reserved_at_4[0x9];
3924 u8 reserved_at_f[0x5];
3926 u8 reserved_at_18[0x8];
3928 u8 reserved_at_20[0x20];
3930 u8 reserved_at_40[0x14];
3931 u8 page_offset[0x6];
3932 u8 reserved_at_5a[0x6];
3934 u8 reserved_at_60[0x3];
3935 u8 log_eq_size[0x5];
3938 u8 reserved_at_80[0x20];
3940 u8 reserved_at_a0[0x14];
3943 u8 reserved_at_c0[0x3];
3944 u8 log_page_size[0x5];
3945 u8 reserved_at_c8[0x18];
3947 u8 reserved_at_e0[0x60];
3949 u8 reserved_at_140[0x8];
3950 u8 consumer_counter[0x18];
3952 u8 reserved_at_160[0x8];
3953 u8 producer_counter[0x18];
3955 u8 reserved_at_180[0x80];
3959 MLX5_DCTC_STATE_ACTIVE = 0x0,
3960 MLX5_DCTC_STATE_DRAINING = 0x1,
3961 MLX5_DCTC_STATE_DRAINED = 0x2,
3965 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3966 MLX5_DCTC_CS_RES_NA = 0x1,
3967 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3971 MLX5_DCTC_MTU_256_BYTES = 0x1,
3972 MLX5_DCTC_MTU_512_BYTES = 0x2,
3973 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3974 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3975 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3978 struct mlx5_ifc_dctc_bits {
3979 u8 reserved_at_0[0x4];
3981 u8 reserved_at_8[0x18];
3983 u8 reserved_at_20[0x8];
3984 u8 user_index[0x18];
3986 u8 reserved_at_40[0x8];
3989 u8 counter_set_id[0x8];
3990 u8 atomic_mode[0x4];
3994 u8 atomic_like_write_en[0x1];
3995 u8 latency_sensitive[0x1];
3998 u8 reserved_at_73[0xd];
4000 u8 reserved_at_80[0x8];
4002 u8 reserved_at_90[0x3];
4003 u8 min_rnr_nak[0x5];
4004 u8 reserved_at_98[0x8];
4006 u8 reserved_at_a0[0x8];
4009 u8 reserved_at_c0[0x8];
4013 u8 reserved_at_e8[0x4];
4014 u8 flow_label[0x14];
4016 u8 dc_access_key[0x40];
4018 u8 reserved_at_140[0x5];
4021 u8 pkey_index[0x10];
4023 u8 reserved_at_160[0x8];
4024 u8 my_addr_index[0x8];
4025 u8 reserved_at_170[0x8];
4028 u8 dc_access_key_violation_count[0x20];
4030 u8 reserved_at_1a0[0x14];
4036 u8 reserved_at_1c0[0x20];
4041 MLX5_CQC_STATUS_OK = 0x0,
4042 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
4043 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
4047 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
4048 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
4052 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
4053 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
4054 MLX5_CQC_ST_FIRED = 0xa,
4058 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4059 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4060 MLX5_CQ_PERIOD_NUM_MODES
4063 struct mlx5_ifc_cqc_bits {
4065 u8 reserved_at_4[0x2];
4066 u8 dbr_umem_valid[0x1];
4070 u8 reserved_at_c[0x1];
4071 u8 scqe_break_moderation_en[0x1];
4073 u8 cq_period_mode[0x2];
4074 u8 cqe_comp_en[0x1];
4075 u8 mini_cqe_res_format[0x2];
4077 u8 reserved_at_18[0x8];
4079 u8 reserved_at_20[0x20];
4081 u8 reserved_at_40[0x14];
4082 u8 page_offset[0x6];
4083 u8 reserved_at_5a[0x6];
4085 u8 reserved_at_60[0x3];
4086 u8 log_cq_size[0x5];
4089 u8 reserved_at_80[0x4];
4091 u8 cq_max_count[0x10];
4093 u8 c_eqn_or_apu_element[0x20];
4095 u8 reserved_at_c0[0x3];
4096 u8 log_page_size[0x5];
4097 u8 reserved_at_c8[0x18];
4099 u8 reserved_at_e0[0x20];
4101 u8 reserved_at_100[0x8];
4102 u8 last_notified_index[0x18];
4104 u8 reserved_at_120[0x8];
4105 u8 last_solicit_index[0x18];
4107 u8 reserved_at_140[0x8];
4108 u8 consumer_counter[0x18];
4110 u8 reserved_at_160[0x8];
4111 u8 producer_counter[0x18];
4113 u8 reserved_at_180[0x40];
4118 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4119 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4120 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4121 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4122 u8 reserved_at_0[0x800];
4125 struct mlx5_ifc_query_adapter_param_block_bits {
4126 u8 reserved_at_0[0xc0];
4128 u8 reserved_at_c0[0x8];
4129 u8 ieee_vendor_id[0x18];
4131 u8 reserved_at_e0[0x10];
4132 u8 vsd_vendor_id[0x10];
4136 u8 vsd_contd_psid[16][0x8];
4140 MLX5_XRQC_STATE_GOOD = 0x0,
4141 MLX5_XRQC_STATE_ERROR = 0x1,
4145 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4146 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
4150 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4153 struct mlx5_ifc_tag_matching_topology_context_bits {
4154 u8 log_matching_list_sz[0x4];
4155 u8 reserved_at_4[0xc];
4156 u8 append_next_index[0x10];
4158 u8 sw_phase_cnt[0x10];
4159 u8 hw_phase_cnt[0x10];
4161 u8 reserved_at_40[0x40];
4164 struct mlx5_ifc_xrqc_bits {
4167 u8 reserved_at_5[0xf];
4169 u8 reserved_at_18[0x4];
4172 u8 reserved_at_20[0x8];
4173 u8 user_index[0x18];
4175 u8 reserved_at_40[0x8];
4178 u8 reserved_at_60[0xa0];
4180 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4182 u8 reserved_at_180[0x280];
4184 struct mlx5_ifc_wq_bits wq;
4187 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4188 struct mlx5_ifc_modify_field_select_bits modify_field_select;
4189 struct mlx5_ifc_resize_field_select_bits resize_field_select;
4190 u8 reserved_at_0[0x20];
4193 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4194 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4195 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4196 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4197 u8 reserved_at_0[0x20];
4200 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4201 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4202 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4203 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4204 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4205 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4206 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4207 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4208 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4209 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4210 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4211 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4212 u8 reserved_at_0[0x7c0];
4215 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4216 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4217 u8 reserved_at_0[0x7c0];
4220 union mlx5_ifc_event_auto_bits {
4221 struct mlx5_ifc_comp_event_bits comp_event;
4222 struct mlx5_ifc_dct_events_bits dct_events;
4223 struct mlx5_ifc_qp_events_bits qp_events;
4224 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4225 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4226 struct mlx5_ifc_cq_error_bits cq_error;
4227 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4228 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4229 struct mlx5_ifc_gpio_event_bits gpio_event;
4230 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4231 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4232 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4233 u8 reserved_at_0[0xe0];
4236 struct mlx5_ifc_health_buffer_bits {
4237 u8 reserved_at_0[0x100];
4239 u8 assert_existptr[0x20];
4241 u8 assert_callra[0x20];
4243 u8 reserved_at_140[0x20];
4247 u8 fw_version[0x20];
4252 u8 reserved_at_1c1[0x3];
4255 u8 reserved_at_1c8[0x18];
4257 u8 irisc_index[0x8];
4262 struct mlx5_ifc_register_loopback_control_bits {
4264 u8 reserved_at_1[0x7];
4266 u8 reserved_at_10[0x10];
4268 u8 reserved_at_20[0x60];
4271 struct mlx5_ifc_vport_tc_element_bits {
4272 u8 traffic_class[0x4];
4273 u8 reserved_at_4[0xc];
4274 u8 vport_number[0x10];
4277 struct mlx5_ifc_vport_element_bits {
4278 u8 reserved_at_0[0x10];
4279 u8 vport_number[0x10];
4283 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4284 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4285 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4288 struct mlx5_ifc_tsar_element_bits {
4289 u8 reserved_at_0[0x8];
4291 u8 reserved_at_10[0x10];
4295 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4296 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4299 struct mlx5_ifc_teardown_hca_out_bits {
4301 u8 reserved_at_8[0x18];
4305 u8 reserved_at_40[0x3f];
4311 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
4312 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
4313 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4316 struct mlx5_ifc_teardown_hca_in_bits {
4318 u8 reserved_at_10[0x10];
4320 u8 reserved_at_20[0x10];
4323 u8 reserved_at_40[0x10];
4326 u8 reserved_at_60[0x20];
4329 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4331 u8 reserved_at_8[0x18];
4335 u8 reserved_at_40[0x40];
4338 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4342 u8 reserved_at_20[0x10];
4345 u8 reserved_at_40[0x8];
4348 u8 reserved_at_60[0x20];
4350 u8 opt_param_mask[0x20];
4352 u8 reserved_at_a0[0x20];
4354 struct mlx5_ifc_qpc_bits qpc;
4356 u8 reserved_at_800[0x80];
4359 struct mlx5_ifc_sqd2rts_qp_out_bits {
4361 u8 reserved_at_8[0x18];
4365 u8 reserved_at_40[0x40];
4368 struct mlx5_ifc_sqd2rts_qp_in_bits {
4372 u8 reserved_at_20[0x10];
4375 u8 reserved_at_40[0x8];
4378 u8 reserved_at_60[0x20];
4380 u8 opt_param_mask[0x20];
4382 u8 reserved_at_a0[0x20];
4384 struct mlx5_ifc_qpc_bits qpc;
4386 u8 reserved_at_800[0x80];
4389 struct mlx5_ifc_set_roce_address_out_bits {
4391 u8 reserved_at_8[0x18];
4395 u8 reserved_at_40[0x40];
4398 struct mlx5_ifc_set_roce_address_in_bits {
4400 u8 reserved_at_10[0x10];
4402 u8 reserved_at_20[0x10];
4405 u8 roce_address_index[0x10];
4406 u8 reserved_at_50[0xc];
4407 u8 vhca_port_num[0x4];
4409 u8 reserved_at_60[0x20];
4411 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4414 struct mlx5_ifc_set_mad_demux_out_bits {
4416 u8 reserved_at_8[0x18];
4420 u8 reserved_at_40[0x40];
4424 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4425 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4428 struct mlx5_ifc_set_mad_demux_in_bits {
4430 u8 reserved_at_10[0x10];
4432 u8 reserved_at_20[0x10];
4435 u8 reserved_at_40[0x20];
4437 u8 reserved_at_60[0x6];
4439 u8 reserved_at_68[0x18];
4442 struct mlx5_ifc_set_l2_table_entry_out_bits {
4444 u8 reserved_at_8[0x18];
4448 u8 reserved_at_40[0x40];
4451 struct mlx5_ifc_set_l2_table_entry_in_bits {
4453 u8 reserved_at_10[0x10];
4455 u8 reserved_at_20[0x10];
4458 u8 reserved_at_40[0x60];
4460 u8 reserved_at_a0[0x8];
4461 u8 table_index[0x18];
4463 u8 reserved_at_c0[0x20];
4465 u8 reserved_at_e0[0x13];
4469 struct mlx5_ifc_mac_address_layout_bits mac_address;
4471 u8 reserved_at_140[0xc0];
4474 struct mlx5_ifc_set_issi_out_bits {
4476 u8 reserved_at_8[0x18];
4480 u8 reserved_at_40[0x40];
4483 struct mlx5_ifc_set_issi_in_bits {
4485 u8 reserved_at_10[0x10];
4487 u8 reserved_at_20[0x10];
4490 u8 reserved_at_40[0x10];
4491 u8 current_issi[0x10];
4493 u8 reserved_at_60[0x20];
4496 struct mlx5_ifc_set_hca_cap_out_bits {
4498 u8 reserved_at_8[0x18];
4502 u8 reserved_at_40[0x40];
4505 struct mlx5_ifc_set_hca_cap_in_bits {
4507 u8 reserved_at_10[0x10];
4509 u8 reserved_at_20[0x10];
4512 u8 other_function[0x1];
4513 u8 reserved_at_41[0xf];
4514 u8 function_id[0x10];
4516 u8 reserved_at_60[0x20];
4518 union mlx5_ifc_hca_cap_union_bits capability;
4522 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4523 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4524 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
4525 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4526 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
4529 struct mlx5_ifc_set_fte_out_bits {
4531 u8 reserved_at_8[0x18];
4535 u8 reserved_at_40[0x40];
4538 struct mlx5_ifc_set_fte_in_bits {
4540 u8 reserved_at_10[0x10];
4542 u8 reserved_at_20[0x10];
4545 u8 other_vport[0x1];
4546 u8 reserved_at_41[0xf];
4547 u8 vport_number[0x10];
4549 u8 reserved_at_60[0x20];
4552 u8 reserved_at_88[0x18];
4554 u8 reserved_at_a0[0x8];
4557 u8 ignore_flow_level[0x1];
4558 u8 reserved_at_c1[0x17];
4559 u8 modify_enable_mask[0x8];
4561 u8 reserved_at_e0[0x20];
4563 u8 flow_index[0x20];
4565 u8 reserved_at_120[0xe0];
4567 struct mlx5_ifc_flow_context_bits flow_context;
4570 struct mlx5_ifc_rts2rts_qp_out_bits {
4572 u8 reserved_at_8[0x18];
4576 u8 reserved_at_40[0x20];
4580 struct mlx5_ifc_rts2rts_qp_in_bits {
4584 u8 reserved_at_20[0x10];
4587 u8 reserved_at_40[0x8];
4590 u8 reserved_at_60[0x20];
4592 u8 opt_param_mask[0x20];
4596 struct mlx5_ifc_qpc_bits qpc;
4598 u8 reserved_at_800[0x80];
4601 struct mlx5_ifc_rtr2rts_qp_out_bits {
4603 u8 reserved_at_8[0x18];
4607 u8 reserved_at_40[0x20];
4611 struct mlx5_ifc_rtr2rts_qp_in_bits {
4615 u8 reserved_at_20[0x10];
4618 u8 reserved_at_40[0x8];
4621 u8 reserved_at_60[0x20];
4623 u8 opt_param_mask[0x20];
4627 struct mlx5_ifc_qpc_bits qpc;
4629 u8 reserved_at_800[0x80];
4632 struct mlx5_ifc_rst2init_qp_out_bits {
4634 u8 reserved_at_8[0x18];
4638 u8 reserved_at_40[0x20];
4642 struct mlx5_ifc_rst2init_qp_in_bits {
4646 u8 reserved_at_20[0x10];
4649 u8 reserved_at_40[0x8];
4652 u8 reserved_at_60[0x20];
4654 u8 opt_param_mask[0x20];
4658 struct mlx5_ifc_qpc_bits qpc;
4660 u8 reserved_at_800[0x80];
4663 struct mlx5_ifc_query_xrq_out_bits {
4665 u8 reserved_at_8[0x18];
4669 u8 reserved_at_40[0x40];
4671 struct mlx5_ifc_xrqc_bits xrq_context;
4674 struct mlx5_ifc_query_xrq_in_bits {
4676 u8 reserved_at_10[0x10];
4678 u8 reserved_at_20[0x10];
4681 u8 reserved_at_40[0x8];
4684 u8 reserved_at_60[0x20];
4687 struct mlx5_ifc_query_xrc_srq_out_bits {
4689 u8 reserved_at_8[0x18];
4693 u8 reserved_at_40[0x40];
4695 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4697 u8 reserved_at_280[0x600];
4702 struct mlx5_ifc_query_xrc_srq_in_bits {
4704 u8 reserved_at_10[0x10];
4706 u8 reserved_at_20[0x10];
4709 u8 reserved_at_40[0x8];
4712 u8 reserved_at_60[0x20];
4716 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4717 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4720 struct mlx5_ifc_query_vport_state_out_bits {
4722 u8 reserved_at_8[0x18];
4726 u8 reserved_at_40[0x20];
4728 u8 reserved_at_60[0x18];
4729 u8 admin_state[0x4];
4734 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4735 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4736 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
4739 struct mlx5_ifc_arm_monitor_counter_in_bits {
4743 u8 reserved_at_20[0x10];
4746 u8 reserved_at_40[0x20];
4748 u8 reserved_at_60[0x20];
4751 struct mlx5_ifc_arm_monitor_counter_out_bits {
4753 u8 reserved_at_8[0x18];
4757 u8 reserved_at_40[0x40];
4761 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4762 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4765 enum mlx5_monitor_counter_ppcnt {
4766 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4767 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4768 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4769 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4770 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4771 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4775 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4778 struct mlx5_ifc_monitor_counter_output_bits {
4779 u8 reserved_at_0[0x4];
4781 u8 reserved_at_8[0x8];
4784 u8 counter_group_id[0x20];
4787 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4788 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4789 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4790 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4792 struct mlx5_ifc_set_monitor_counter_in_bits {
4796 u8 reserved_at_20[0x10];
4799 u8 reserved_at_40[0x10];
4800 u8 num_of_counters[0x10];
4802 u8 reserved_at_60[0x20];
4804 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4807 struct mlx5_ifc_set_monitor_counter_out_bits {
4809 u8 reserved_at_8[0x18];
4813 u8 reserved_at_40[0x40];
4816 struct mlx5_ifc_query_vport_state_in_bits {
4818 u8 reserved_at_10[0x10];
4820 u8 reserved_at_20[0x10];
4823 u8 other_vport[0x1];
4824 u8 reserved_at_41[0xf];
4825 u8 vport_number[0x10];
4827 u8 reserved_at_60[0x20];
4830 struct mlx5_ifc_query_vnic_env_out_bits {
4832 u8 reserved_at_8[0x18];
4836 u8 reserved_at_40[0x40];
4838 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4842 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4845 struct mlx5_ifc_query_vnic_env_in_bits {
4847 u8 reserved_at_10[0x10];
4849 u8 reserved_at_20[0x10];
4852 u8 other_vport[0x1];
4853 u8 reserved_at_41[0xf];
4854 u8 vport_number[0x10];
4856 u8 reserved_at_60[0x20];
4859 struct mlx5_ifc_query_vport_counter_out_bits {
4861 u8 reserved_at_8[0x18];
4865 u8 reserved_at_40[0x40];
4867 struct mlx5_ifc_traffic_counter_bits received_errors;
4869 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4871 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4873 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4875 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4877 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4879 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4881 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4883 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4885 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4887 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4889 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4891 u8 reserved_at_680[0xa00];
4895 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4898 struct mlx5_ifc_query_vport_counter_in_bits {
4900 u8 reserved_at_10[0x10];
4902 u8 reserved_at_20[0x10];
4905 u8 other_vport[0x1];
4906 u8 reserved_at_41[0xb];
4908 u8 vport_number[0x10];
4910 u8 reserved_at_60[0x60];
4913 u8 reserved_at_c1[0x1f];
4915 u8 reserved_at_e0[0x20];
4918 struct mlx5_ifc_query_tis_out_bits {
4920 u8 reserved_at_8[0x18];
4924 u8 reserved_at_40[0x40];
4926 struct mlx5_ifc_tisc_bits tis_context;
4929 struct mlx5_ifc_query_tis_in_bits {
4931 u8 reserved_at_10[0x10];
4933 u8 reserved_at_20[0x10];
4936 u8 reserved_at_40[0x8];
4939 u8 reserved_at_60[0x20];
4942 struct mlx5_ifc_query_tir_out_bits {
4944 u8 reserved_at_8[0x18];
4948 u8 reserved_at_40[0xc0];
4950 struct mlx5_ifc_tirc_bits tir_context;
4953 struct mlx5_ifc_query_tir_in_bits {
4955 u8 reserved_at_10[0x10];
4957 u8 reserved_at_20[0x10];
4960 u8 reserved_at_40[0x8];
4963 u8 reserved_at_60[0x20];
4966 struct mlx5_ifc_query_srq_out_bits {
4968 u8 reserved_at_8[0x18];
4972 u8 reserved_at_40[0x40];
4974 struct mlx5_ifc_srqc_bits srq_context_entry;
4976 u8 reserved_at_280[0x600];
4981 struct mlx5_ifc_query_srq_in_bits {
4983 u8 reserved_at_10[0x10];
4985 u8 reserved_at_20[0x10];
4988 u8 reserved_at_40[0x8];
4991 u8 reserved_at_60[0x20];
4994 struct mlx5_ifc_query_sq_out_bits {
4996 u8 reserved_at_8[0x18];
5000 u8 reserved_at_40[0xc0];
5002 struct mlx5_ifc_sqc_bits sq_context;
5005 struct mlx5_ifc_query_sq_in_bits {
5007 u8 reserved_at_10[0x10];
5009 u8 reserved_at_20[0x10];
5012 u8 reserved_at_40[0x8];
5015 u8 reserved_at_60[0x20];
5018 struct mlx5_ifc_query_special_contexts_out_bits {
5020 u8 reserved_at_8[0x18];
5024 u8 dump_fill_mkey[0x20];
5030 u8 reserved_at_a0[0x60];
5033 struct mlx5_ifc_query_special_contexts_in_bits {
5035 u8 reserved_at_10[0x10];
5037 u8 reserved_at_20[0x10];
5040 u8 reserved_at_40[0x40];
5043 struct mlx5_ifc_query_scheduling_element_out_bits {
5045 u8 reserved_at_10[0x10];
5047 u8 reserved_at_20[0x10];
5050 u8 reserved_at_40[0xc0];
5052 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5054 u8 reserved_at_300[0x100];
5058 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5059 SCHEDULING_HIERARCHY_NIC = 0x3,
5062 struct mlx5_ifc_query_scheduling_element_in_bits {
5064 u8 reserved_at_10[0x10];
5066 u8 reserved_at_20[0x10];
5069 u8 scheduling_hierarchy[0x8];
5070 u8 reserved_at_48[0x18];
5072 u8 scheduling_element_id[0x20];
5074 u8 reserved_at_80[0x180];
5077 struct mlx5_ifc_query_rqt_out_bits {
5079 u8 reserved_at_8[0x18];
5083 u8 reserved_at_40[0xc0];
5085 struct mlx5_ifc_rqtc_bits rqt_context;
5088 struct mlx5_ifc_query_rqt_in_bits {
5090 u8 reserved_at_10[0x10];
5092 u8 reserved_at_20[0x10];
5095 u8 reserved_at_40[0x8];
5098 u8 reserved_at_60[0x20];
5101 struct mlx5_ifc_query_rq_out_bits {
5103 u8 reserved_at_8[0x18];
5107 u8 reserved_at_40[0xc0];
5109 struct mlx5_ifc_rqc_bits rq_context;
5112 struct mlx5_ifc_query_rq_in_bits {
5114 u8 reserved_at_10[0x10];
5116 u8 reserved_at_20[0x10];
5119 u8 reserved_at_40[0x8];
5122 u8 reserved_at_60[0x20];
5125 struct mlx5_ifc_query_roce_address_out_bits {
5127 u8 reserved_at_8[0x18];
5131 u8 reserved_at_40[0x40];
5133 struct mlx5_ifc_roce_addr_layout_bits roce_address;
5136 struct mlx5_ifc_query_roce_address_in_bits {
5138 u8 reserved_at_10[0x10];
5140 u8 reserved_at_20[0x10];
5143 u8 roce_address_index[0x10];
5144 u8 reserved_at_50[0xc];
5145 u8 vhca_port_num[0x4];
5147 u8 reserved_at_60[0x20];
5150 struct mlx5_ifc_query_rmp_out_bits {
5152 u8 reserved_at_8[0x18];
5156 u8 reserved_at_40[0xc0];
5158 struct mlx5_ifc_rmpc_bits rmp_context;
5161 struct mlx5_ifc_query_rmp_in_bits {
5163 u8 reserved_at_10[0x10];
5165 u8 reserved_at_20[0x10];
5168 u8 reserved_at_40[0x8];
5171 u8 reserved_at_60[0x20];
5174 struct mlx5_ifc_query_qp_out_bits {
5176 u8 reserved_at_8[0x18];
5180 u8 reserved_at_40[0x40];
5182 u8 opt_param_mask[0x20];
5186 struct mlx5_ifc_qpc_bits qpc;
5188 u8 reserved_at_800[0x80];
5193 struct mlx5_ifc_query_qp_in_bits {
5195 u8 reserved_at_10[0x10];
5197 u8 reserved_at_20[0x10];
5200 u8 reserved_at_40[0x8];
5203 u8 reserved_at_60[0x20];
5206 struct mlx5_ifc_query_q_counter_out_bits {
5208 u8 reserved_at_8[0x18];
5212 u8 reserved_at_40[0x40];
5214 u8 rx_write_requests[0x20];
5216 u8 reserved_at_a0[0x20];
5218 u8 rx_read_requests[0x20];
5220 u8 reserved_at_e0[0x20];
5222 u8 rx_atomic_requests[0x20];
5224 u8 reserved_at_120[0x20];
5226 u8 rx_dct_connect[0x20];
5228 u8 reserved_at_160[0x20];
5230 u8 out_of_buffer[0x20];
5232 u8 reserved_at_1a0[0x20];
5234 u8 out_of_sequence[0x20];
5236 u8 reserved_at_1e0[0x20];
5238 u8 duplicate_request[0x20];
5240 u8 reserved_at_220[0x20];
5242 u8 rnr_nak_retry_err[0x20];
5244 u8 reserved_at_260[0x20];
5246 u8 packet_seq_err[0x20];
5248 u8 reserved_at_2a0[0x20];
5250 u8 implied_nak_seq_err[0x20];
5252 u8 reserved_at_2e0[0x20];
5254 u8 local_ack_timeout_err[0x20];
5256 u8 reserved_at_320[0xa0];
5258 u8 resp_local_length_error[0x20];
5260 u8 req_local_length_error[0x20];
5262 u8 resp_local_qp_error[0x20];
5264 u8 local_operation_error[0x20];
5266 u8 resp_local_protection[0x20];
5268 u8 req_local_protection[0x20];
5270 u8 resp_cqe_error[0x20];
5272 u8 req_cqe_error[0x20];
5274 u8 req_mw_binding[0x20];
5276 u8 req_bad_response[0x20];
5278 u8 req_remote_invalid_request[0x20];
5280 u8 resp_remote_invalid_request[0x20];
5282 u8 req_remote_access_errors[0x20];
5284 u8 resp_remote_access_errors[0x20];
5286 u8 req_remote_operation_errors[0x20];
5288 u8 req_transport_retries_exceeded[0x20];
5290 u8 cq_overflow[0x20];
5292 u8 resp_cqe_flush_error[0x20];
5294 u8 req_cqe_flush_error[0x20];
5296 u8 reserved_at_620[0x20];
5298 u8 roce_adp_retrans[0x20];
5300 u8 roce_adp_retrans_to[0x20];
5302 u8 roce_slow_restart[0x20];
5304 u8 roce_slow_restart_cnps[0x20];
5306 u8 roce_slow_restart_trans[0x20];
5308 u8 reserved_at_6e0[0x120];
5311 struct mlx5_ifc_query_q_counter_in_bits {
5313 u8 reserved_at_10[0x10];
5315 u8 reserved_at_20[0x10];
5318 u8 reserved_at_40[0x80];
5321 u8 reserved_at_c1[0x1f];
5323 u8 reserved_at_e0[0x18];
5324 u8 counter_set_id[0x8];
5327 struct mlx5_ifc_query_pages_out_bits {
5329 u8 reserved_at_8[0x18];
5333 u8 embedded_cpu_function[0x1];
5334 u8 reserved_at_41[0xf];
5335 u8 function_id[0x10];
5341 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5342 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5343 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5346 struct mlx5_ifc_query_pages_in_bits {
5348 u8 reserved_at_10[0x10];
5350 u8 reserved_at_20[0x10];
5353 u8 embedded_cpu_function[0x1];
5354 u8 reserved_at_41[0xf];
5355 u8 function_id[0x10];
5357 u8 reserved_at_60[0x20];
5360 struct mlx5_ifc_query_nic_vport_context_out_bits {
5362 u8 reserved_at_8[0x18];
5366 u8 reserved_at_40[0x40];
5368 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5371 struct mlx5_ifc_query_nic_vport_context_in_bits {
5373 u8 reserved_at_10[0x10];
5375 u8 reserved_at_20[0x10];
5378 u8 other_vport[0x1];
5379 u8 reserved_at_41[0xf];
5380 u8 vport_number[0x10];
5382 u8 reserved_at_60[0x5];
5383 u8 allowed_list_type[0x3];
5384 u8 reserved_at_68[0x18];
5387 struct mlx5_ifc_query_mkey_out_bits {
5389 u8 reserved_at_8[0x18];
5393 u8 reserved_at_40[0x40];
5395 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5397 u8 reserved_at_280[0x600];
5399 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5401 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5404 struct mlx5_ifc_query_mkey_in_bits {
5406 u8 reserved_at_10[0x10];
5408 u8 reserved_at_20[0x10];
5411 u8 reserved_at_40[0x8];
5412 u8 mkey_index[0x18];
5415 u8 reserved_at_61[0x1f];
5418 struct mlx5_ifc_query_mad_demux_out_bits {
5420 u8 reserved_at_8[0x18];
5424 u8 reserved_at_40[0x40];
5426 u8 mad_dumux_parameters_block[0x20];
5429 struct mlx5_ifc_query_mad_demux_in_bits {
5431 u8 reserved_at_10[0x10];
5433 u8 reserved_at_20[0x10];
5436 u8 reserved_at_40[0x40];
5439 struct mlx5_ifc_query_l2_table_entry_out_bits {
5441 u8 reserved_at_8[0x18];
5445 u8 reserved_at_40[0xa0];
5447 u8 reserved_at_e0[0x13];
5451 struct mlx5_ifc_mac_address_layout_bits mac_address;
5453 u8 reserved_at_140[0xc0];
5456 struct mlx5_ifc_query_l2_table_entry_in_bits {
5458 u8 reserved_at_10[0x10];
5460 u8 reserved_at_20[0x10];
5463 u8 reserved_at_40[0x60];
5465 u8 reserved_at_a0[0x8];
5466 u8 table_index[0x18];
5468 u8 reserved_at_c0[0x140];
5471 struct mlx5_ifc_query_issi_out_bits {
5473 u8 reserved_at_8[0x18];
5477 u8 reserved_at_40[0x10];
5478 u8 current_issi[0x10];
5480 u8 reserved_at_60[0xa0];
5482 u8 reserved_at_100[76][0x8];
5483 u8 supported_issi_dw0[0x20];
5486 struct mlx5_ifc_query_issi_in_bits {
5488 u8 reserved_at_10[0x10];
5490 u8 reserved_at_20[0x10];
5493 u8 reserved_at_40[0x40];
5496 struct mlx5_ifc_set_driver_version_out_bits {
5498 u8 reserved_0[0x18];
5501 u8 reserved_1[0x40];
5504 struct mlx5_ifc_set_driver_version_in_bits {
5506 u8 reserved_0[0x10];
5508 u8 reserved_1[0x10];
5511 u8 reserved_2[0x40];
5512 u8 driver_version[64][0x8];
5515 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5517 u8 reserved_at_8[0x18];
5521 u8 reserved_at_40[0x40];
5523 struct mlx5_ifc_pkey_bits pkey[];
5526 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5528 u8 reserved_at_10[0x10];
5530 u8 reserved_at_20[0x10];
5533 u8 other_vport[0x1];
5534 u8 reserved_at_41[0xb];
5536 u8 vport_number[0x10];
5538 u8 reserved_at_60[0x10];
5539 u8 pkey_index[0x10];
5543 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5544 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5545 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5548 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5550 u8 reserved_at_8[0x18];
5554 u8 reserved_at_40[0x20];
5557 u8 reserved_at_70[0x10];
5559 struct mlx5_ifc_array128_auto_bits gid[];
5562 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5564 u8 reserved_at_10[0x10];
5566 u8 reserved_at_20[0x10];
5569 u8 other_vport[0x1];
5570 u8 reserved_at_41[0xb];
5572 u8 vport_number[0x10];
5574 u8 reserved_at_60[0x10];
5578 struct mlx5_ifc_query_hca_vport_context_out_bits {
5580 u8 reserved_at_8[0x18];
5584 u8 reserved_at_40[0x40];
5586 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5589 struct mlx5_ifc_query_hca_vport_context_in_bits {
5591 u8 reserved_at_10[0x10];
5593 u8 reserved_at_20[0x10];
5596 u8 other_vport[0x1];
5597 u8 reserved_at_41[0xb];
5599 u8 vport_number[0x10];
5601 u8 reserved_at_60[0x20];
5604 struct mlx5_ifc_query_hca_cap_out_bits {
5606 u8 reserved_at_8[0x18];
5610 u8 reserved_at_40[0x40];
5612 union mlx5_ifc_hca_cap_union_bits capability;
5615 struct mlx5_ifc_query_hca_cap_in_bits {
5617 u8 reserved_at_10[0x10];
5619 u8 reserved_at_20[0x10];
5622 u8 other_function[0x1];
5623 u8 reserved_at_41[0xf];
5624 u8 function_id[0x10];
5626 u8 reserved_at_60[0x20];
5629 struct mlx5_ifc_other_hca_cap_bits {
5631 u8 reserved_at_1[0x27f];
5634 struct mlx5_ifc_query_other_hca_cap_out_bits {
5636 u8 reserved_at_8[0x18];
5640 u8 reserved_at_40[0x40];
5642 struct mlx5_ifc_other_hca_cap_bits other_capability;
5645 struct mlx5_ifc_query_other_hca_cap_in_bits {
5647 u8 reserved_at_10[0x10];
5649 u8 reserved_at_20[0x10];
5652 u8 reserved_at_40[0x10];
5653 u8 function_id[0x10];
5655 u8 reserved_at_60[0x20];
5658 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5660 u8 reserved_at_8[0x18];
5664 u8 reserved_at_40[0x40];
5667 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5669 u8 reserved_at_10[0x10];
5671 u8 reserved_at_20[0x10];
5674 u8 reserved_at_40[0x10];
5675 u8 function_id[0x10];
5676 u8 field_select[0x20];
5678 struct mlx5_ifc_other_hca_cap_bits other_capability;
5681 struct mlx5_ifc_flow_table_context_bits {
5682 u8 reformat_en[0x1];
5685 u8 termination_table[0x1];
5686 u8 table_miss_action[0x4];
5688 u8 reserved_at_10[0x8];
5691 u8 reserved_at_20[0x8];
5692 u8 table_miss_id[0x18];
5694 u8 reserved_at_40[0x8];
5695 u8 lag_master_next_table_id[0x18];
5697 u8 reserved_at_60[0x60];
5699 u8 sw_owner_icm_root_1[0x40];
5701 u8 sw_owner_icm_root_0[0x40];
5705 struct mlx5_ifc_query_flow_table_out_bits {
5707 u8 reserved_at_8[0x18];
5711 u8 reserved_at_40[0x80];
5713 struct mlx5_ifc_flow_table_context_bits flow_table_context;
5716 struct mlx5_ifc_query_flow_table_in_bits {
5718 u8 reserved_at_10[0x10];
5720 u8 reserved_at_20[0x10];
5723 u8 reserved_at_40[0x40];
5726 u8 reserved_at_88[0x18];
5728 u8 reserved_at_a0[0x8];
5731 u8 reserved_at_c0[0x140];
5734 struct mlx5_ifc_query_fte_out_bits {
5736 u8 reserved_at_8[0x18];
5740 u8 reserved_at_40[0x1c0];
5742 struct mlx5_ifc_flow_context_bits flow_context;
5745 struct mlx5_ifc_query_fte_in_bits {
5747 u8 reserved_at_10[0x10];
5749 u8 reserved_at_20[0x10];
5752 u8 reserved_at_40[0x40];
5755 u8 reserved_at_88[0x18];
5757 u8 reserved_at_a0[0x8];
5760 u8 reserved_at_c0[0x40];
5762 u8 flow_index[0x20];
5764 u8 reserved_at_120[0xe0];
5767 struct mlx5_ifc_match_definer_format_0_bits {
5768 u8 reserved_at_0[0x100];
5770 u8 metadata_reg_c_0[0x20];
5772 u8 metadata_reg_c_1[0x20];
5774 u8 outer_dmac_47_16[0x20];
5776 u8 outer_dmac_15_0[0x10];
5777 u8 outer_ethertype[0x10];
5779 u8 reserved_at_180[0x1];
5781 u8 functional_lb[0x1];
5782 u8 outer_ip_frag[0x1];
5783 u8 outer_qp_type[0x2];
5784 u8 outer_encap_type[0x2];
5785 u8 port_number[0x2];
5786 u8 outer_l3_type[0x2];
5787 u8 outer_l4_type[0x2];
5788 u8 outer_first_vlan_type[0x2];
5789 u8 outer_first_vlan_prio[0x3];
5790 u8 outer_first_vlan_cfi[0x1];
5791 u8 outer_first_vlan_vid[0xc];
5793 u8 outer_l4_type_ext[0x4];
5794 u8 reserved_at_1a4[0x2];
5795 u8 outer_ipsec_layer[0x2];
5796 u8 outer_l2_type[0x2];
5798 u8 outer_l2_ok[0x1];
5799 u8 outer_l3_ok[0x1];
5800 u8 outer_l4_ok[0x1];
5801 u8 outer_second_vlan_type[0x2];
5802 u8 outer_second_vlan_prio[0x3];
5803 u8 outer_second_vlan_cfi[0x1];
5804 u8 outer_second_vlan_vid[0xc];
5806 u8 outer_smac_47_16[0x20];
5808 u8 outer_smac_15_0[0x10];
5809 u8 inner_ipv4_checksum_ok[0x1];
5810 u8 inner_l4_checksum_ok[0x1];
5811 u8 outer_ipv4_checksum_ok[0x1];
5812 u8 outer_l4_checksum_ok[0x1];
5813 u8 inner_l3_ok[0x1];
5814 u8 inner_l4_ok[0x1];
5815 u8 outer_l3_ok_duplicate[0x1];
5816 u8 outer_l4_ok_duplicate[0x1];
5817 u8 outer_tcp_cwr[0x1];
5818 u8 outer_tcp_ece[0x1];
5819 u8 outer_tcp_urg[0x1];
5820 u8 outer_tcp_ack[0x1];
5821 u8 outer_tcp_psh[0x1];
5822 u8 outer_tcp_rst[0x1];
5823 u8 outer_tcp_syn[0x1];
5824 u8 outer_tcp_fin[0x1];
5827 struct mlx5_ifc_match_definer_format_22_bits {
5828 u8 reserved_at_0[0x100];
5830 u8 outer_ip_src_addr[0x20];
5832 u8 outer_ip_dest_addr[0x20];
5834 u8 outer_l4_sport[0x10];
5835 u8 outer_l4_dport[0x10];
5837 u8 reserved_at_160[0x1];
5839 u8 functional_lb[0x1];
5840 u8 outer_ip_frag[0x1];
5841 u8 outer_qp_type[0x2];
5842 u8 outer_encap_type[0x2];
5843 u8 port_number[0x2];
5844 u8 outer_l3_type[0x2];
5845 u8 outer_l4_type[0x2];
5846 u8 outer_first_vlan_type[0x2];
5847 u8 outer_first_vlan_prio[0x3];
5848 u8 outer_first_vlan_cfi[0x1];
5849 u8 outer_first_vlan_vid[0xc];
5851 u8 metadata_reg_c_0[0x20];
5853 u8 outer_dmac_47_16[0x20];
5855 u8 outer_smac_47_16[0x20];
5857 u8 outer_smac_15_0[0x10];
5858 u8 outer_dmac_15_0[0x10];
5861 struct mlx5_ifc_match_definer_format_23_bits {
5862 u8 reserved_at_0[0x100];
5864 u8 inner_ip_src_addr[0x20];
5866 u8 inner_ip_dest_addr[0x20];
5868 u8 inner_l4_sport[0x10];
5869 u8 inner_l4_dport[0x10];
5871 u8 reserved_at_160[0x1];
5873 u8 functional_lb[0x1];
5874 u8 inner_ip_frag[0x1];
5875 u8 inner_qp_type[0x2];
5876 u8 inner_encap_type[0x2];
5877 u8 port_number[0x2];
5878 u8 inner_l3_type[0x2];
5879 u8 inner_l4_type[0x2];
5880 u8 inner_first_vlan_type[0x2];
5881 u8 inner_first_vlan_prio[0x3];
5882 u8 inner_first_vlan_cfi[0x1];
5883 u8 inner_first_vlan_vid[0xc];
5885 u8 tunnel_header_0[0x20];
5887 u8 inner_dmac_47_16[0x20];
5889 u8 inner_smac_47_16[0x20];
5891 u8 inner_smac_15_0[0x10];
5892 u8 inner_dmac_15_0[0x10];
5895 struct mlx5_ifc_match_definer_format_29_bits {
5896 u8 reserved_at_0[0xc0];
5898 u8 outer_ip_dest_addr[0x80];
5900 u8 outer_ip_src_addr[0x80];
5902 u8 outer_l4_sport[0x10];
5903 u8 outer_l4_dport[0x10];
5905 u8 reserved_at_1e0[0x20];
5908 struct mlx5_ifc_match_definer_format_30_bits {
5909 u8 reserved_at_0[0xa0];
5911 u8 outer_ip_dest_addr[0x80];
5913 u8 outer_ip_src_addr[0x80];
5915 u8 outer_dmac_47_16[0x20];
5917 u8 outer_smac_47_16[0x20];
5919 u8 outer_smac_15_0[0x10];
5920 u8 outer_dmac_15_0[0x10];
5923 struct mlx5_ifc_match_definer_format_31_bits {
5924 u8 reserved_at_0[0xc0];
5926 u8 inner_ip_dest_addr[0x80];
5928 u8 inner_ip_src_addr[0x80];
5930 u8 inner_l4_sport[0x10];
5931 u8 inner_l4_dport[0x10];
5933 u8 reserved_at_1e0[0x20];
5936 struct mlx5_ifc_match_definer_format_32_bits {
5937 u8 reserved_at_0[0xa0];
5939 u8 inner_ip_dest_addr[0x80];
5941 u8 inner_ip_src_addr[0x80];
5943 u8 inner_dmac_47_16[0x20];
5945 u8 inner_smac_47_16[0x20];
5947 u8 inner_smac_15_0[0x10];
5948 u8 inner_dmac_15_0[0x10];
5951 struct mlx5_ifc_match_definer_bits {
5952 u8 modify_field_select[0x40];
5954 u8 reserved_at_40[0x40];
5956 u8 reserved_at_80[0x10];
5959 u8 reserved_at_a0[0x160];
5961 u8 match_mask[16][0x20];
5964 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
5968 u8 vhca_tunnel_id[0x10];
5973 u8 reserved_at_60[0x20];
5976 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
5978 u8 reserved_at_8[0x18];
5984 u8 reserved_at_60[0x20];
5987 struct mlx5_ifc_create_match_definer_in_bits {
5988 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
5990 struct mlx5_ifc_match_definer_bits obj_context;
5993 struct mlx5_ifc_create_match_definer_out_bits {
5994 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
5998 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5999 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6000 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6001 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6002 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6003 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6004 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6007 struct mlx5_ifc_query_flow_group_out_bits {
6009 u8 reserved_at_8[0x18];
6013 u8 reserved_at_40[0xa0];
6015 u8 start_flow_index[0x20];
6017 u8 reserved_at_100[0x20];
6019 u8 end_flow_index[0x20];
6021 u8 reserved_at_140[0xa0];
6023 u8 reserved_at_1e0[0x18];
6024 u8 match_criteria_enable[0x8];
6026 struct mlx5_ifc_fte_match_param_bits match_criteria;
6028 u8 reserved_at_1200[0xe00];
6031 struct mlx5_ifc_query_flow_group_in_bits {
6033 u8 reserved_at_10[0x10];
6035 u8 reserved_at_20[0x10];
6038 u8 reserved_at_40[0x40];
6041 u8 reserved_at_88[0x18];
6043 u8 reserved_at_a0[0x8];
6048 u8 reserved_at_e0[0x120];
6051 struct mlx5_ifc_query_flow_counter_out_bits {
6053 u8 reserved_at_8[0x18];
6057 u8 reserved_at_40[0x40];
6059 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6062 struct mlx5_ifc_query_flow_counter_in_bits {
6064 u8 reserved_at_10[0x10];
6066 u8 reserved_at_20[0x10];
6069 u8 reserved_at_40[0x80];
6072 u8 reserved_at_c1[0xf];
6073 u8 num_of_counters[0x10];
6075 u8 flow_counter_id[0x20];
6078 struct mlx5_ifc_query_esw_vport_context_out_bits {
6080 u8 reserved_at_8[0x18];
6084 u8 reserved_at_40[0x40];
6086 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6089 struct mlx5_ifc_query_esw_vport_context_in_bits {
6091 u8 reserved_at_10[0x10];
6093 u8 reserved_at_20[0x10];
6096 u8 other_vport[0x1];
6097 u8 reserved_at_41[0xf];
6098 u8 vport_number[0x10];
6100 u8 reserved_at_60[0x20];
6103 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6105 u8 reserved_at_8[0x18];
6109 u8 reserved_at_40[0x40];
6112 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6113 u8 reserved_at_0[0x1b];
6114 u8 fdb_to_vport_reg_c_id[0x1];
6115 u8 vport_cvlan_insert[0x1];
6116 u8 vport_svlan_insert[0x1];
6117 u8 vport_cvlan_strip[0x1];
6118 u8 vport_svlan_strip[0x1];
6121 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6123 u8 reserved_at_10[0x10];
6125 u8 reserved_at_20[0x10];
6128 u8 other_vport[0x1];
6129 u8 reserved_at_41[0xf];
6130 u8 vport_number[0x10];
6132 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6134 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6137 struct mlx5_ifc_query_eq_out_bits {
6139 u8 reserved_at_8[0x18];
6143 u8 reserved_at_40[0x40];
6145 struct mlx5_ifc_eqc_bits eq_context_entry;
6147 u8 reserved_at_280[0x40];
6149 u8 event_bitmask[0x40];
6151 u8 reserved_at_300[0x580];
6156 struct mlx5_ifc_query_eq_in_bits {
6158 u8 reserved_at_10[0x10];
6160 u8 reserved_at_20[0x10];
6163 u8 reserved_at_40[0x18];
6166 u8 reserved_at_60[0x20];
6169 struct mlx5_ifc_packet_reformat_context_in_bits {
6170 u8 reformat_type[0x8];
6171 u8 reserved_at_8[0x4];
6172 u8 reformat_param_0[0x4];
6173 u8 reserved_at_10[0x6];
6174 u8 reformat_data_size[0xa];
6176 u8 reformat_param_1[0x8];
6177 u8 reserved_at_28[0x8];
6178 u8 reformat_data[2][0x8];
6180 u8 more_reformat_data[][0x8];
6183 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6185 u8 reserved_at_8[0x18];
6189 u8 reserved_at_40[0xa0];
6191 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6194 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6196 u8 reserved_at_10[0x10];
6198 u8 reserved_at_20[0x10];
6201 u8 packet_reformat_id[0x20];
6203 u8 reserved_at_60[0xa0];
6206 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6208 u8 reserved_at_8[0x18];
6212 u8 packet_reformat_id[0x20];
6214 u8 reserved_at_60[0x20];
6218 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6219 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6220 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6223 enum mlx5_reformat_ctx_type {
6224 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6225 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6226 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6227 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6228 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6229 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6230 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6233 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6235 u8 reserved_at_10[0x10];
6237 u8 reserved_at_20[0x10];
6240 u8 reserved_at_40[0xa0];
6242 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6245 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6247 u8 reserved_at_8[0x18];
6251 u8 reserved_at_40[0x40];
6254 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6256 u8 reserved_at_10[0x10];
6258 u8 reserved_20[0x10];
6261 u8 packet_reformat_id[0x20];
6263 u8 reserved_60[0x20];
6266 struct mlx5_ifc_set_action_in_bits {
6267 u8 action_type[0x4];
6269 u8 reserved_at_10[0x3];
6271 u8 reserved_at_18[0x3];
6277 struct mlx5_ifc_add_action_in_bits {
6278 u8 action_type[0x4];
6280 u8 reserved_at_10[0x10];
6285 struct mlx5_ifc_copy_action_in_bits {
6286 u8 action_type[0x4];
6288 u8 reserved_at_10[0x3];
6290 u8 reserved_at_18[0x3];
6293 u8 reserved_at_20[0x4];
6295 u8 reserved_at_30[0x3];
6297 u8 reserved_at_38[0x8];
6300 union mlx5_ifc_set_add_copy_action_in_auto_bits {
6301 struct mlx5_ifc_set_action_in_bits set_action_in;
6302 struct mlx5_ifc_add_action_in_bits add_action_in;
6303 struct mlx5_ifc_copy_action_in_bits copy_action_in;
6304 u8 reserved_at_0[0x40];
6308 MLX5_ACTION_TYPE_SET = 0x1,
6309 MLX5_ACTION_TYPE_ADD = 0x2,
6310 MLX5_ACTION_TYPE_COPY = 0x3,
6314 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
6315 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
6316 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
6317 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
6318 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
6319 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
6320 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
6321 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
6322 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
6323 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
6324 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
6325 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
6326 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
6327 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
6328 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
6329 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
6330 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
6331 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
6332 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
6333 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
6334 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
6335 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
6336 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
6337 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6338 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
6339 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
6340 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
6341 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
6342 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
6343 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
6344 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
6345 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
6346 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
6347 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
6348 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
6349 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
6350 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
6351 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F,
6352 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70,
6355 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6357 u8 reserved_at_8[0x18];
6361 u8 modify_header_id[0x20];
6363 u8 reserved_at_60[0x20];
6366 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6368 u8 reserved_at_10[0x10];
6370 u8 reserved_at_20[0x10];
6373 u8 reserved_at_40[0x20];
6376 u8 reserved_at_68[0x10];
6377 u8 num_of_actions[0x8];
6379 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6382 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6384 u8 reserved_at_8[0x18];
6388 u8 reserved_at_40[0x40];
6391 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6393 u8 reserved_at_10[0x10];
6395 u8 reserved_at_20[0x10];
6398 u8 modify_header_id[0x20];
6400 u8 reserved_at_60[0x20];
6403 struct mlx5_ifc_query_modify_header_context_in_bits {
6407 u8 reserved_at_20[0x10];
6410 u8 modify_header_id[0x20];
6412 u8 reserved_at_60[0xa0];
6415 struct mlx5_ifc_query_dct_out_bits {
6417 u8 reserved_at_8[0x18];
6421 u8 reserved_at_40[0x40];
6423 struct mlx5_ifc_dctc_bits dct_context_entry;
6425 u8 reserved_at_280[0x180];
6428 struct mlx5_ifc_query_dct_in_bits {
6430 u8 reserved_at_10[0x10];
6432 u8 reserved_at_20[0x10];
6435 u8 reserved_at_40[0x8];
6438 u8 reserved_at_60[0x20];
6441 struct mlx5_ifc_query_cq_out_bits {
6443 u8 reserved_at_8[0x18];
6447 u8 reserved_at_40[0x40];
6449 struct mlx5_ifc_cqc_bits cq_context;
6451 u8 reserved_at_280[0x600];
6456 struct mlx5_ifc_query_cq_in_bits {
6458 u8 reserved_at_10[0x10];
6460 u8 reserved_at_20[0x10];
6463 u8 reserved_at_40[0x8];
6466 u8 reserved_at_60[0x20];
6469 struct mlx5_ifc_query_cong_status_out_bits {
6471 u8 reserved_at_8[0x18];
6475 u8 reserved_at_40[0x20];
6479 u8 reserved_at_62[0x1e];
6482 struct mlx5_ifc_query_cong_status_in_bits {
6484 u8 reserved_at_10[0x10];
6486 u8 reserved_at_20[0x10];
6489 u8 reserved_at_40[0x18];
6491 u8 cong_protocol[0x4];
6493 u8 reserved_at_60[0x20];
6496 struct mlx5_ifc_query_cong_statistics_out_bits {
6498 u8 reserved_at_8[0x18];
6502 u8 reserved_at_40[0x40];
6504 u8 rp_cur_flows[0x20];
6508 u8 rp_cnp_ignored_high[0x20];
6510 u8 rp_cnp_ignored_low[0x20];
6512 u8 rp_cnp_handled_high[0x20];
6514 u8 rp_cnp_handled_low[0x20];
6516 u8 reserved_at_140[0x100];
6518 u8 time_stamp_high[0x20];
6520 u8 time_stamp_low[0x20];
6522 u8 accumulators_period[0x20];
6524 u8 np_ecn_marked_roce_packets_high[0x20];
6526 u8 np_ecn_marked_roce_packets_low[0x20];
6528 u8 np_cnp_sent_high[0x20];
6530 u8 np_cnp_sent_low[0x20];
6532 u8 reserved_at_320[0x560];
6535 struct mlx5_ifc_query_cong_statistics_in_bits {
6537 u8 reserved_at_10[0x10];
6539 u8 reserved_at_20[0x10];
6543 u8 reserved_at_41[0x1f];
6545 u8 reserved_at_60[0x20];
6548 struct mlx5_ifc_query_cong_params_out_bits {
6550 u8 reserved_at_8[0x18];
6554 u8 reserved_at_40[0x40];
6556 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6559 struct mlx5_ifc_query_cong_params_in_bits {
6561 u8 reserved_at_10[0x10];
6563 u8 reserved_at_20[0x10];
6566 u8 reserved_at_40[0x1c];
6567 u8 cong_protocol[0x4];
6569 u8 reserved_at_60[0x20];
6572 struct mlx5_ifc_query_adapter_out_bits {
6574 u8 reserved_at_8[0x18];
6578 u8 reserved_at_40[0x40];
6580 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6583 struct mlx5_ifc_query_adapter_in_bits {
6585 u8 reserved_at_10[0x10];
6587 u8 reserved_at_20[0x10];
6590 u8 reserved_at_40[0x40];
6593 struct mlx5_ifc_qp_2rst_out_bits {
6595 u8 reserved_at_8[0x18];
6599 u8 reserved_at_40[0x40];
6602 struct mlx5_ifc_qp_2rst_in_bits {
6606 u8 reserved_at_20[0x10];
6609 u8 reserved_at_40[0x8];
6612 u8 reserved_at_60[0x20];
6615 struct mlx5_ifc_qp_2err_out_bits {
6617 u8 reserved_at_8[0x18];
6621 u8 reserved_at_40[0x40];
6624 struct mlx5_ifc_qp_2err_in_bits {
6628 u8 reserved_at_20[0x10];
6631 u8 reserved_at_40[0x8];
6634 u8 reserved_at_60[0x20];
6637 struct mlx5_ifc_page_fault_resume_out_bits {
6639 u8 reserved_at_8[0x18];
6643 u8 reserved_at_40[0x40];
6646 struct mlx5_ifc_page_fault_resume_in_bits {
6648 u8 reserved_at_10[0x10];
6650 u8 reserved_at_20[0x10];
6654 u8 reserved_at_41[0x4];
6655 u8 page_fault_type[0x3];
6658 u8 reserved_at_60[0x8];
6662 struct mlx5_ifc_nop_out_bits {
6664 u8 reserved_at_8[0x18];
6668 u8 reserved_at_40[0x40];
6671 struct mlx5_ifc_nop_in_bits {
6673 u8 reserved_at_10[0x10];
6675 u8 reserved_at_20[0x10];
6678 u8 reserved_at_40[0x40];
6681 struct mlx5_ifc_modify_vport_state_out_bits {
6683 u8 reserved_at_8[0x18];
6687 u8 reserved_at_40[0x40];
6690 struct mlx5_ifc_modify_vport_state_in_bits {
6692 u8 reserved_at_10[0x10];
6694 u8 reserved_at_20[0x10];
6697 u8 other_vport[0x1];
6698 u8 reserved_at_41[0xf];
6699 u8 vport_number[0x10];
6701 u8 reserved_at_60[0x18];
6702 u8 admin_state[0x4];
6703 u8 reserved_at_7c[0x4];
6706 struct mlx5_ifc_modify_tis_out_bits {
6708 u8 reserved_at_8[0x18];
6712 u8 reserved_at_40[0x40];
6715 struct mlx5_ifc_modify_tis_bitmask_bits {
6716 u8 reserved_at_0[0x20];
6718 u8 reserved_at_20[0x1d];
6719 u8 lag_tx_port_affinity[0x1];
6720 u8 strict_lag_tx_port_affinity[0x1];
6724 struct mlx5_ifc_modify_tis_in_bits {
6728 u8 reserved_at_20[0x10];
6731 u8 reserved_at_40[0x8];
6734 u8 reserved_at_60[0x20];
6736 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6738 u8 reserved_at_c0[0x40];
6740 struct mlx5_ifc_tisc_bits ctx;
6743 struct mlx5_ifc_modify_tir_bitmask_bits {
6744 u8 reserved_at_0[0x20];
6746 u8 reserved_at_20[0x1b];
6748 u8 reserved_at_3c[0x1];
6750 u8 reserved_at_3e[0x1];
6751 u8 packet_merge[0x1];
6754 struct mlx5_ifc_modify_tir_out_bits {
6756 u8 reserved_at_8[0x18];
6760 u8 reserved_at_40[0x40];
6763 struct mlx5_ifc_modify_tir_in_bits {
6767 u8 reserved_at_20[0x10];
6770 u8 reserved_at_40[0x8];
6773 u8 reserved_at_60[0x20];
6775 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6777 u8 reserved_at_c0[0x40];
6779 struct mlx5_ifc_tirc_bits ctx;
6782 struct mlx5_ifc_modify_sq_out_bits {
6784 u8 reserved_at_8[0x18];
6788 u8 reserved_at_40[0x40];
6791 struct mlx5_ifc_modify_sq_in_bits {
6795 u8 reserved_at_20[0x10];
6799 u8 reserved_at_44[0x4];
6802 u8 reserved_at_60[0x20];
6804 u8 modify_bitmask[0x40];
6806 u8 reserved_at_c0[0x40];
6808 struct mlx5_ifc_sqc_bits ctx;
6811 struct mlx5_ifc_modify_scheduling_element_out_bits {
6813 u8 reserved_at_8[0x18];
6817 u8 reserved_at_40[0x1c0];
6821 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6822 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6825 struct mlx5_ifc_modify_scheduling_element_in_bits {
6827 u8 reserved_at_10[0x10];
6829 u8 reserved_at_20[0x10];
6832 u8 scheduling_hierarchy[0x8];
6833 u8 reserved_at_48[0x18];
6835 u8 scheduling_element_id[0x20];
6837 u8 reserved_at_80[0x20];
6839 u8 modify_bitmask[0x20];
6841 u8 reserved_at_c0[0x40];
6843 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6845 u8 reserved_at_300[0x100];
6848 struct mlx5_ifc_modify_rqt_out_bits {
6850 u8 reserved_at_8[0x18];
6854 u8 reserved_at_40[0x40];
6857 struct mlx5_ifc_rqt_bitmask_bits {
6858 u8 reserved_at_0[0x20];
6860 u8 reserved_at_20[0x1f];
6864 struct mlx5_ifc_modify_rqt_in_bits {
6868 u8 reserved_at_20[0x10];
6871 u8 reserved_at_40[0x8];
6874 u8 reserved_at_60[0x20];
6876 struct mlx5_ifc_rqt_bitmask_bits bitmask;
6878 u8 reserved_at_c0[0x40];
6880 struct mlx5_ifc_rqtc_bits ctx;
6883 struct mlx5_ifc_modify_rq_out_bits {
6885 u8 reserved_at_8[0x18];
6889 u8 reserved_at_40[0x40];
6893 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6894 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6895 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6898 struct mlx5_ifc_modify_rq_in_bits {
6902 u8 reserved_at_20[0x10];
6906 u8 reserved_at_44[0x4];
6909 u8 reserved_at_60[0x20];
6911 u8 modify_bitmask[0x40];
6913 u8 reserved_at_c0[0x40];
6915 struct mlx5_ifc_rqc_bits ctx;
6918 struct mlx5_ifc_modify_rmp_out_bits {
6920 u8 reserved_at_8[0x18];
6924 u8 reserved_at_40[0x40];
6927 struct mlx5_ifc_rmp_bitmask_bits {
6928 u8 reserved_at_0[0x20];
6930 u8 reserved_at_20[0x1f];
6934 struct mlx5_ifc_modify_rmp_in_bits {
6938 u8 reserved_at_20[0x10];
6942 u8 reserved_at_44[0x4];
6945 u8 reserved_at_60[0x20];
6947 struct mlx5_ifc_rmp_bitmask_bits bitmask;
6949 u8 reserved_at_c0[0x40];
6951 struct mlx5_ifc_rmpc_bits ctx;
6954 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6956 u8 reserved_at_8[0x18];
6960 u8 reserved_at_40[0x40];
6963 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6964 u8 reserved_at_0[0x12];
6965 u8 affiliation[0x1];
6966 u8 reserved_at_13[0x1];
6967 u8 disable_uc_local_lb[0x1];
6968 u8 disable_mc_local_lb[0x1];
6973 u8 change_event[0x1];
6975 u8 permanent_address[0x1];
6976 u8 addresses_list[0x1];
6978 u8 reserved_at_1f[0x1];
6981 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6983 u8 reserved_at_10[0x10];
6985 u8 reserved_at_20[0x10];
6988 u8 other_vport[0x1];
6989 u8 reserved_at_41[0xf];
6990 u8 vport_number[0x10];
6992 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6994 u8 reserved_at_80[0x780];
6996 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6999 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7001 u8 reserved_at_8[0x18];
7005 u8 reserved_at_40[0x40];
7008 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7010 u8 reserved_at_10[0x10];
7012 u8 reserved_at_20[0x10];
7015 u8 other_vport[0x1];
7016 u8 reserved_at_41[0xb];
7018 u8 vport_number[0x10];
7020 u8 reserved_at_60[0x20];
7022 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7025 struct mlx5_ifc_modify_cq_out_bits {
7027 u8 reserved_at_8[0x18];
7031 u8 reserved_at_40[0x40];
7035 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
7036 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
7039 struct mlx5_ifc_modify_cq_in_bits {
7043 u8 reserved_at_20[0x10];
7046 u8 reserved_at_40[0x8];
7049 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7051 struct mlx5_ifc_cqc_bits cq_context;
7053 u8 reserved_at_280[0x60];
7055 u8 cq_umem_valid[0x1];
7056 u8 reserved_at_2e1[0x1f];
7058 u8 reserved_at_300[0x580];
7063 struct mlx5_ifc_modify_cong_status_out_bits {
7065 u8 reserved_at_8[0x18];
7069 u8 reserved_at_40[0x40];
7072 struct mlx5_ifc_modify_cong_status_in_bits {
7074 u8 reserved_at_10[0x10];
7076 u8 reserved_at_20[0x10];
7079 u8 reserved_at_40[0x18];
7081 u8 cong_protocol[0x4];
7085 u8 reserved_at_62[0x1e];
7088 struct mlx5_ifc_modify_cong_params_out_bits {
7090 u8 reserved_at_8[0x18];
7094 u8 reserved_at_40[0x40];
7097 struct mlx5_ifc_modify_cong_params_in_bits {
7099 u8 reserved_at_10[0x10];
7101 u8 reserved_at_20[0x10];
7104 u8 reserved_at_40[0x1c];
7105 u8 cong_protocol[0x4];
7107 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7109 u8 reserved_at_80[0x80];
7111 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7114 struct mlx5_ifc_manage_pages_out_bits {
7116 u8 reserved_at_8[0x18];
7120 u8 output_num_entries[0x20];
7122 u8 reserved_at_60[0x20];
7128 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
7129 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
7130 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
7133 struct mlx5_ifc_manage_pages_in_bits {
7135 u8 reserved_at_10[0x10];
7137 u8 reserved_at_20[0x10];
7140 u8 embedded_cpu_function[0x1];
7141 u8 reserved_at_41[0xf];
7142 u8 function_id[0x10];
7144 u8 input_num_entries[0x20];
7149 struct mlx5_ifc_mad_ifc_out_bits {
7151 u8 reserved_at_8[0x18];
7155 u8 reserved_at_40[0x40];
7157 u8 response_mad_packet[256][0x8];
7160 struct mlx5_ifc_mad_ifc_in_bits {
7162 u8 reserved_at_10[0x10];
7164 u8 reserved_at_20[0x10];
7167 u8 remote_lid[0x10];
7168 u8 reserved_at_50[0x8];
7171 u8 reserved_at_60[0x20];
7176 struct mlx5_ifc_init_hca_out_bits {
7178 u8 reserved_at_8[0x18];
7182 u8 reserved_at_40[0x40];
7185 struct mlx5_ifc_init_hca_in_bits {
7187 u8 reserved_at_10[0x10];
7189 u8 reserved_at_20[0x10];
7192 u8 reserved_at_40[0x40];
7193 u8 sw_owner_id[4][0x20];
7196 struct mlx5_ifc_init2rtr_qp_out_bits {
7198 u8 reserved_at_8[0x18];
7202 u8 reserved_at_40[0x20];
7206 struct mlx5_ifc_init2rtr_qp_in_bits {
7210 u8 reserved_at_20[0x10];
7213 u8 reserved_at_40[0x8];
7216 u8 reserved_at_60[0x20];
7218 u8 opt_param_mask[0x20];
7222 struct mlx5_ifc_qpc_bits qpc;
7224 u8 reserved_at_800[0x80];
7227 struct mlx5_ifc_init2init_qp_out_bits {
7229 u8 reserved_at_8[0x18];
7233 u8 reserved_at_40[0x20];
7237 struct mlx5_ifc_init2init_qp_in_bits {
7241 u8 reserved_at_20[0x10];
7244 u8 reserved_at_40[0x8];
7247 u8 reserved_at_60[0x20];
7249 u8 opt_param_mask[0x20];
7253 struct mlx5_ifc_qpc_bits qpc;
7255 u8 reserved_at_800[0x80];
7258 struct mlx5_ifc_get_dropped_packet_log_out_bits {
7260 u8 reserved_at_8[0x18];
7264 u8 reserved_at_40[0x40];
7266 u8 packet_headers_log[128][0x8];
7268 u8 packet_syndrome[64][0x8];
7271 struct mlx5_ifc_get_dropped_packet_log_in_bits {
7273 u8 reserved_at_10[0x10];
7275 u8 reserved_at_20[0x10];
7278 u8 reserved_at_40[0x40];
7281 struct mlx5_ifc_gen_eqe_in_bits {
7283 u8 reserved_at_10[0x10];
7285 u8 reserved_at_20[0x10];
7288 u8 reserved_at_40[0x18];
7291 u8 reserved_at_60[0x20];
7296 struct mlx5_ifc_gen_eq_out_bits {
7298 u8 reserved_at_8[0x18];
7302 u8 reserved_at_40[0x40];
7305 struct mlx5_ifc_enable_hca_out_bits {
7307 u8 reserved_at_8[0x18];
7311 u8 reserved_at_40[0x20];
7314 struct mlx5_ifc_enable_hca_in_bits {
7316 u8 reserved_at_10[0x10];
7318 u8 reserved_at_20[0x10];
7321 u8 embedded_cpu_function[0x1];
7322 u8 reserved_at_41[0xf];
7323 u8 function_id[0x10];
7325 u8 reserved_at_60[0x20];
7328 struct mlx5_ifc_drain_dct_out_bits {
7330 u8 reserved_at_8[0x18];
7334 u8 reserved_at_40[0x40];
7337 struct mlx5_ifc_drain_dct_in_bits {
7341 u8 reserved_at_20[0x10];
7344 u8 reserved_at_40[0x8];
7347 u8 reserved_at_60[0x20];
7350 struct mlx5_ifc_disable_hca_out_bits {
7352 u8 reserved_at_8[0x18];
7356 u8 reserved_at_40[0x20];
7359 struct mlx5_ifc_disable_hca_in_bits {
7361 u8 reserved_at_10[0x10];
7363 u8 reserved_at_20[0x10];
7366 u8 embedded_cpu_function[0x1];
7367 u8 reserved_at_41[0xf];
7368 u8 function_id[0x10];
7370 u8 reserved_at_60[0x20];
7373 struct mlx5_ifc_detach_from_mcg_out_bits {
7375 u8 reserved_at_8[0x18];
7379 u8 reserved_at_40[0x40];
7382 struct mlx5_ifc_detach_from_mcg_in_bits {
7386 u8 reserved_at_20[0x10];
7389 u8 reserved_at_40[0x8];
7392 u8 reserved_at_60[0x20];
7394 u8 multicast_gid[16][0x8];
7397 struct mlx5_ifc_destroy_xrq_out_bits {
7399 u8 reserved_at_8[0x18];
7403 u8 reserved_at_40[0x40];
7406 struct mlx5_ifc_destroy_xrq_in_bits {
7410 u8 reserved_at_20[0x10];
7413 u8 reserved_at_40[0x8];
7416 u8 reserved_at_60[0x20];
7419 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7421 u8 reserved_at_8[0x18];
7425 u8 reserved_at_40[0x40];
7428 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7432 u8 reserved_at_20[0x10];
7435 u8 reserved_at_40[0x8];
7438 u8 reserved_at_60[0x20];
7441 struct mlx5_ifc_destroy_tis_out_bits {
7443 u8 reserved_at_8[0x18];
7447 u8 reserved_at_40[0x40];
7450 struct mlx5_ifc_destroy_tis_in_bits {
7454 u8 reserved_at_20[0x10];
7457 u8 reserved_at_40[0x8];
7460 u8 reserved_at_60[0x20];
7463 struct mlx5_ifc_destroy_tir_out_bits {
7465 u8 reserved_at_8[0x18];
7469 u8 reserved_at_40[0x40];
7472 struct mlx5_ifc_destroy_tir_in_bits {
7476 u8 reserved_at_20[0x10];
7479 u8 reserved_at_40[0x8];
7482 u8 reserved_at_60[0x20];
7485 struct mlx5_ifc_destroy_srq_out_bits {
7487 u8 reserved_at_8[0x18];
7491 u8 reserved_at_40[0x40];
7494 struct mlx5_ifc_destroy_srq_in_bits {
7498 u8 reserved_at_20[0x10];
7501 u8 reserved_at_40[0x8];
7504 u8 reserved_at_60[0x20];
7507 struct mlx5_ifc_destroy_sq_out_bits {
7509 u8 reserved_at_8[0x18];
7513 u8 reserved_at_40[0x40];
7516 struct mlx5_ifc_destroy_sq_in_bits {
7520 u8 reserved_at_20[0x10];
7523 u8 reserved_at_40[0x8];
7526 u8 reserved_at_60[0x20];
7529 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7531 u8 reserved_at_8[0x18];
7535 u8 reserved_at_40[0x1c0];
7538 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7540 u8 reserved_at_10[0x10];
7542 u8 reserved_at_20[0x10];
7545 u8 scheduling_hierarchy[0x8];
7546 u8 reserved_at_48[0x18];
7548 u8 scheduling_element_id[0x20];
7550 u8 reserved_at_80[0x180];
7553 struct mlx5_ifc_destroy_rqt_out_bits {
7555 u8 reserved_at_8[0x18];
7559 u8 reserved_at_40[0x40];
7562 struct mlx5_ifc_destroy_rqt_in_bits {
7566 u8 reserved_at_20[0x10];
7569 u8 reserved_at_40[0x8];
7572 u8 reserved_at_60[0x20];
7575 struct mlx5_ifc_destroy_rq_out_bits {
7577 u8 reserved_at_8[0x18];
7581 u8 reserved_at_40[0x40];
7584 struct mlx5_ifc_destroy_rq_in_bits {
7588 u8 reserved_at_20[0x10];
7591 u8 reserved_at_40[0x8];
7594 u8 reserved_at_60[0x20];
7597 struct mlx5_ifc_set_delay_drop_params_in_bits {
7599 u8 reserved_at_10[0x10];
7601 u8 reserved_at_20[0x10];
7604 u8 reserved_at_40[0x20];
7606 u8 reserved_at_60[0x10];
7607 u8 delay_drop_timeout[0x10];
7610 struct mlx5_ifc_set_delay_drop_params_out_bits {
7612 u8 reserved_at_8[0x18];
7616 u8 reserved_at_40[0x40];
7619 struct mlx5_ifc_destroy_rmp_out_bits {
7621 u8 reserved_at_8[0x18];
7625 u8 reserved_at_40[0x40];
7628 struct mlx5_ifc_destroy_rmp_in_bits {
7632 u8 reserved_at_20[0x10];
7635 u8 reserved_at_40[0x8];
7638 u8 reserved_at_60[0x20];
7641 struct mlx5_ifc_destroy_qp_out_bits {
7643 u8 reserved_at_8[0x18];
7647 u8 reserved_at_40[0x40];
7650 struct mlx5_ifc_destroy_qp_in_bits {
7654 u8 reserved_at_20[0x10];
7657 u8 reserved_at_40[0x8];
7660 u8 reserved_at_60[0x20];
7663 struct mlx5_ifc_destroy_psv_out_bits {
7665 u8 reserved_at_8[0x18];
7669 u8 reserved_at_40[0x40];
7672 struct mlx5_ifc_destroy_psv_in_bits {
7674 u8 reserved_at_10[0x10];
7676 u8 reserved_at_20[0x10];
7679 u8 reserved_at_40[0x8];
7682 u8 reserved_at_60[0x20];
7685 struct mlx5_ifc_destroy_mkey_out_bits {
7687 u8 reserved_at_8[0x18];
7691 u8 reserved_at_40[0x40];
7694 struct mlx5_ifc_destroy_mkey_in_bits {
7698 u8 reserved_at_20[0x10];
7701 u8 reserved_at_40[0x8];
7702 u8 mkey_index[0x18];
7704 u8 reserved_at_60[0x20];
7707 struct mlx5_ifc_destroy_flow_table_out_bits {
7709 u8 reserved_at_8[0x18];
7713 u8 reserved_at_40[0x40];
7716 struct mlx5_ifc_destroy_flow_table_in_bits {
7718 u8 reserved_at_10[0x10];
7720 u8 reserved_at_20[0x10];
7723 u8 other_vport[0x1];
7724 u8 reserved_at_41[0xf];
7725 u8 vport_number[0x10];
7727 u8 reserved_at_60[0x20];
7730 u8 reserved_at_88[0x18];
7732 u8 reserved_at_a0[0x8];
7735 u8 reserved_at_c0[0x140];
7738 struct mlx5_ifc_destroy_flow_group_out_bits {
7740 u8 reserved_at_8[0x18];
7744 u8 reserved_at_40[0x40];
7747 struct mlx5_ifc_destroy_flow_group_in_bits {
7749 u8 reserved_at_10[0x10];
7751 u8 reserved_at_20[0x10];
7754 u8 other_vport[0x1];
7755 u8 reserved_at_41[0xf];
7756 u8 vport_number[0x10];
7758 u8 reserved_at_60[0x20];
7761 u8 reserved_at_88[0x18];
7763 u8 reserved_at_a0[0x8];
7768 u8 reserved_at_e0[0x120];
7771 struct mlx5_ifc_destroy_eq_out_bits {
7773 u8 reserved_at_8[0x18];
7777 u8 reserved_at_40[0x40];
7780 struct mlx5_ifc_destroy_eq_in_bits {
7782 u8 reserved_at_10[0x10];
7784 u8 reserved_at_20[0x10];
7787 u8 reserved_at_40[0x18];
7790 u8 reserved_at_60[0x20];
7793 struct mlx5_ifc_destroy_dct_out_bits {
7795 u8 reserved_at_8[0x18];
7799 u8 reserved_at_40[0x40];
7802 struct mlx5_ifc_destroy_dct_in_bits {
7806 u8 reserved_at_20[0x10];
7809 u8 reserved_at_40[0x8];
7812 u8 reserved_at_60[0x20];
7815 struct mlx5_ifc_destroy_cq_out_bits {
7817 u8 reserved_at_8[0x18];
7821 u8 reserved_at_40[0x40];
7824 struct mlx5_ifc_destroy_cq_in_bits {
7828 u8 reserved_at_20[0x10];
7831 u8 reserved_at_40[0x8];
7834 u8 reserved_at_60[0x20];
7837 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7839 u8 reserved_at_8[0x18];
7843 u8 reserved_at_40[0x40];
7846 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7848 u8 reserved_at_10[0x10];
7850 u8 reserved_at_20[0x10];
7853 u8 reserved_at_40[0x20];
7855 u8 reserved_at_60[0x10];
7856 u8 vxlan_udp_port[0x10];
7859 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7861 u8 reserved_at_8[0x18];
7865 u8 reserved_at_40[0x40];
7868 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7870 u8 reserved_at_10[0x10];
7872 u8 reserved_at_20[0x10];
7875 u8 reserved_at_40[0x60];
7877 u8 reserved_at_a0[0x8];
7878 u8 table_index[0x18];
7880 u8 reserved_at_c0[0x140];
7883 struct mlx5_ifc_delete_fte_out_bits {
7885 u8 reserved_at_8[0x18];
7889 u8 reserved_at_40[0x40];
7892 struct mlx5_ifc_delete_fte_in_bits {
7894 u8 reserved_at_10[0x10];
7896 u8 reserved_at_20[0x10];
7899 u8 other_vport[0x1];
7900 u8 reserved_at_41[0xf];
7901 u8 vport_number[0x10];
7903 u8 reserved_at_60[0x20];
7906 u8 reserved_at_88[0x18];
7908 u8 reserved_at_a0[0x8];
7911 u8 reserved_at_c0[0x40];
7913 u8 flow_index[0x20];
7915 u8 reserved_at_120[0xe0];
7918 struct mlx5_ifc_dealloc_xrcd_out_bits {
7920 u8 reserved_at_8[0x18];
7924 u8 reserved_at_40[0x40];
7927 struct mlx5_ifc_dealloc_xrcd_in_bits {
7931 u8 reserved_at_20[0x10];
7934 u8 reserved_at_40[0x8];
7937 u8 reserved_at_60[0x20];
7940 struct mlx5_ifc_dealloc_uar_out_bits {
7942 u8 reserved_at_8[0x18];
7946 u8 reserved_at_40[0x40];
7949 struct mlx5_ifc_dealloc_uar_in_bits {
7953 u8 reserved_at_20[0x10];
7956 u8 reserved_at_40[0x8];
7959 u8 reserved_at_60[0x20];
7962 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7964 u8 reserved_at_8[0x18];
7968 u8 reserved_at_40[0x40];
7971 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7975 u8 reserved_at_20[0x10];
7978 u8 reserved_at_40[0x8];
7979 u8 transport_domain[0x18];
7981 u8 reserved_at_60[0x20];
7984 struct mlx5_ifc_dealloc_q_counter_out_bits {
7986 u8 reserved_at_8[0x18];
7990 u8 reserved_at_40[0x40];
7993 struct mlx5_ifc_dealloc_q_counter_in_bits {
7995 u8 reserved_at_10[0x10];
7997 u8 reserved_at_20[0x10];
8000 u8 reserved_at_40[0x18];
8001 u8 counter_set_id[0x8];
8003 u8 reserved_at_60[0x20];
8006 struct mlx5_ifc_dealloc_pd_out_bits {
8008 u8 reserved_at_8[0x18];
8012 u8 reserved_at_40[0x40];
8015 struct mlx5_ifc_dealloc_pd_in_bits {
8019 u8 reserved_at_20[0x10];
8022 u8 reserved_at_40[0x8];
8025 u8 reserved_at_60[0x20];
8028 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8030 u8 reserved_at_8[0x18];
8034 u8 reserved_at_40[0x40];
8037 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8039 u8 reserved_at_10[0x10];
8041 u8 reserved_at_20[0x10];
8044 u8 flow_counter_id[0x20];
8046 u8 reserved_at_60[0x20];
8049 struct mlx5_ifc_create_xrq_out_bits {
8051 u8 reserved_at_8[0x18];
8055 u8 reserved_at_40[0x8];
8058 u8 reserved_at_60[0x20];
8061 struct mlx5_ifc_create_xrq_in_bits {
8065 u8 reserved_at_20[0x10];
8068 u8 reserved_at_40[0x40];
8070 struct mlx5_ifc_xrqc_bits xrq_context;
8073 struct mlx5_ifc_create_xrc_srq_out_bits {
8075 u8 reserved_at_8[0x18];
8079 u8 reserved_at_40[0x8];
8082 u8 reserved_at_60[0x20];
8085 struct mlx5_ifc_create_xrc_srq_in_bits {
8089 u8 reserved_at_20[0x10];
8092 u8 reserved_at_40[0x40];
8094 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8096 u8 reserved_at_280[0x60];
8098 u8 xrc_srq_umem_valid[0x1];
8099 u8 reserved_at_2e1[0x1f];
8101 u8 reserved_at_300[0x580];
8106 struct mlx5_ifc_create_tis_out_bits {
8108 u8 reserved_at_8[0x18];
8112 u8 reserved_at_40[0x8];
8115 u8 reserved_at_60[0x20];
8118 struct mlx5_ifc_create_tis_in_bits {
8122 u8 reserved_at_20[0x10];
8125 u8 reserved_at_40[0xc0];
8127 struct mlx5_ifc_tisc_bits ctx;
8130 struct mlx5_ifc_create_tir_out_bits {
8132 u8 icm_address_63_40[0x18];
8136 u8 icm_address_39_32[0x8];
8139 u8 icm_address_31_0[0x20];
8142 struct mlx5_ifc_create_tir_in_bits {
8146 u8 reserved_at_20[0x10];
8149 u8 reserved_at_40[0xc0];
8151 struct mlx5_ifc_tirc_bits ctx;
8154 struct mlx5_ifc_create_srq_out_bits {
8156 u8 reserved_at_8[0x18];
8160 u8 reserved_at_40[0x8];
8163 u8 reserved_at_60[0x20];
8166 struct mlx5_ifc_create_srq_in_bits {
8170 u8 reserved_at_20[0x10];
8173 u8 reserved_at_40[0x40];
8175 struct mlx5_ifc_srqc_bits srq_context_entry;
8177 u8 reserved_at_280[0x600];
8182 struct mlx5_ifc_create_sq_out_bits {
8184 u8 reserved_at_8[0x18];
8188 u8 reserved_at_40[0x8];
8191 u8 reserved_at_60[0x20];
8194 struct mlx5_ifc_create_sq_in_bits {
8198 u8 reserved_at_20[0x10];
8201 u8 reserved_at_40[0xc0];
8203 struct mlx5_ifc_sqc_bits ctx;
8206 struct mlx5_ifc_create_scheduling_element_out_bits {
8208 u8 reserved_at_8[0x18];
8212 u8 reserved_at_40[0x40];
8214 u8 scheduling_element_id[0x20];
8216 u8 reserved_at_a0[0x160];
8219 struct mlx5_ifc_create_scheduling_element_in_bits {
8221 u8 reserved_at_10[0x10];
8223 u8 reserved_at_20[0x10];
8226 u8 scheduling_hierarchy[0x8];
8227 u8 reserved_at_48[0x18];
8229 u8 reserved_at_60[0xa0];
8231 struct mlx5_ifc_scheduling_context_bits scheduling_context;
8233 u8 reserved_at_300[0x100];
8236 struct mlx5_ifc_create_rqt_out_bits {
8238 u8 reserved_at_8[0x18];
8242 u8 reserved_at_40[0x8];
8245 u8 reserved_at_60[0x20];
8248 struct mlx5_ifc_create_rqt_in_bits {
8252 u8 reserved_at_20[0x10];
8255 u8 reserved_at_40[0xc0];
8257 struct mlx5_ifc_rqtc_bits rqt_context;
8260 struct mlx5_ifc_create_rq_out_bits {
8262 u8 reserved_at_8[0x18];
8266 u8 reserved_at_40[0x8];
8269 u8 reserved_at_60[0x20];
8272 struct mlx5_ifc_create_rq_in_bits {
8276 u8 reserved_at_20[0x10];
8279 u8 reserved_at_40[0xc0];
8281 struct mlx5_ifc_rqc_bits ctx;
8284 struct mlx5_ifc_create_rmp_out_bits {
8286 u8 reserved_at_8[0x18];
8290 u8 reserved_at_40[0x8];
8293 u8 reserved_at_60[0x20];
8296 struct mlx5_ifc_create_rmp_in_bits {
8300 u8 reserved_at_20[0x10];
8303 u8 reserved_at_40[0xc0];
8305 struct mlx5_ifc_rmpc_bits ctx;
8308 struct mlx5_ifc_create_qp_out_bits {
8310 u8 reserved_at_8[0x18];
8314 u8 reserved_at_40[0x8];
8320 struct mlx5_ifc_create_qp_in_bits {
8324 u8 reserved_at_20[0x10];
8327 u8 reserved_at_40[0x8];
8330 u8 reserved_at_60[0x20];
8331 u8 opt_param_mask[0x20];
8335 struct mlx5_ifc_qpc_bits qpc;
8337 u8 reserved_at_800[0x60];
8339 u8 wq_umem_valid[0x1];
8340 u8 reserved_at_861[0x1f];
8345 struct mlx5_ifc_create_psv_out_bits {
8347 u8 reserved_at_8[0x18];
8351 u8 reserved_at_40[0x40];
8353 u8 reserved_at_80[0x8];
8354 u8 psv0_index[0x18];
8356 u8 reserved_at_a0[0x8];
8357 u8 psv1_index[0x18];
8359 u8 reserved_at_c0[0x8];
8360 u8 psv2_index[0x18];
8362 u8 reserved_at_e0[0x8];
8363 u8 psv3_index[0x18];
8366 struct mlx5_ifc_create_psv_in_bits {
8368 u8 reserved_at_10[0x10];
8370 u8 reserved_at_20[0x10];
8374 u8 reserved_at_44[0x4];
8377 u8 reserved_at_60[0x20];
8380 struct mlx5_ifc_create_mkey_out_bits {
8382 u8 reserved_at_8[0x18];
8386 u8 reserved_at_40[0x8];
8387 u8 mkey_index[0x18];
8389 u8 reserved_at_60[0x20];
8392 struct mlx5_ifc_create_mkey_in_bits {
8396 u8 reserved_at_20[0x10];
8399 u8 reserved_at_40[0x20];
8402 u8 mkey_umem_valid[0x1];
8403 u8 reserved_at_62[0x1e];
8405 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8407 u8 reserved_at_280[0x80];
8409 u8 translations_octword_actual_size[0x20];
8411 u8 reserved_at_320[0x560];
8413 u8 klm_pas_mtt[][0x20];
8417 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
8418 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
8419 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
8420 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
8421 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
8422 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
8423 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
8426 struct mlx5_ifc_create_flow_table_out_bits {
8428 u8 icm_address_63_40[0x18];
8432 u8 icm_address_39_32[0x8];
8435 u8 icm_address_31_0[0x20];
8438 struct mlx5_ifc_create_flow_table_in_bits {
8440 u8 reserved_at_10[0x10];
8442 u8 reserved_at_20[0x10];
8445 u8 other_vport[0x1];
8446 u8 reserved_at_41[0xf];
8447 u8 vport_number[0x10];
8449 u8 reserved_at_60[0x20];
8452 u8 reserved_at_88[0x18];
8454 u8 reserved_at_a0[0x20];
8456 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8459 struct mlx5_ifc_create_flow_group_out_bits {
8461 u8 reserved_at_8[0x18];
8465 u8 reserved_at_40[0x8];
8468 u8 reserved_at_60[0x20];
8472 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0,
8473 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1,
8477 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
8478 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
8479 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
8480 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8483 struct mlx5_ifc_create_flow_group_in_bits {
8485 u8 reserved_at_10[0x10];
8487 u8 reserved_at_20[0x10];
8490 u8 other_vport[0x1];
8491 u8 reserved_at_41[0xf];
8492 u8 vport_number[0x10];
8494 u8 reserved_at_60[0x20];
8497 u8 reserved_at_88[0x4];
8499 u8 reserved_at_90[0x10];
8501 u8 reserved_at_a0[0x8];
8504 u8 source_eswitch_owner_vhca_id_valid[0x1];
8506 u8 reserved_at_c1[0x1f];
8508 u8 start_flow_index[0x20];
8510 u8 reserved_at_100[0x20];
8512 u8 end_flow_index[0x20];
8514 u8 reserved_at_140[0x10];
8515 u8 match_definer_id[0x10];
8517 u8 reserved_at_160[0x80];
8519 u8 reserved_at_1e0[0x18];
8520 u8 match_criteria_enable[0x8];
8522 struct mlx5_ifc_fte_match_param_bits match_criteria;
8524 u8 reserved_at_1200[0xe00];
8527 struct mlx5_ifc_create_eq_out_bits {
8529 u8 reserved_at_8[0x18];
8533 u8 reserved_at_40[0x18];
8536 u8 reserved_at_60[0x20];
8539 struct mlx5_ifc_create_eq_in_bits {
8543 u8 reserved_at_20[0x10];
8546 u8 reserved_at_40[0x40];
8548 struct mlx5_ifc_eqc_bits eq_context_entry;
8550 u8 reserved_at_280[0x40];
8552 u8 event_bitmask[4][0x40];
8554 u8 reserved_at_3c0[0x4c0];
8559 struct mlx5_ifc_create_dct_out_bits {
8561 u8 reserved_at_8[0x18];
8565 u8 reserved_at_40[0x8];
8571 struct mlx5_ifc_create_dct_in_bits {
8575 u8 reserved_at_20[0x10];
8578 u8 reserved_at_40[0x40];
8580 struct mlx5_ifc_dctc_bits dct_context_entry;
8582 u8 reserved_at_280[0x180];
8585 struct mlx5_ifc_create_cq_out_bits {
8587 u8 reserved_at_8[0x18];
8591 u8 reserved_at_40[0x8];
8594 u8 reserved_at_60[0x20];
8597 struct mlx5_ifc_create_cq_in_bits {
8601 u8 reserved_at_20[0x10];
8604 u8 reserved_at_40[0x40];
8606 struct mlx5_ifc_cqc_bits cq_context;
8608 u8 reserved_at_280[0x60];
8610 u8 cq_umem_valid[0x1];
8611 u8 reserved_at_2e1[0x59f];
8616 struct mlx5_ifc_config_int_moderation_out_bits {
8618 u8 reserved_at_8[0x18];
8622 u8 reserved_at_40[0x4];
8624 u8 int_vector[0x10];
8626 u8 reserved_at_60[0x20];
8630 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8631 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8634 struct mlx5_ifc_config_int_moderation_in_bits {
8636 u8 reserved_at_10[0x10];
8638 u8 reserved_at_20[0x10];
8641 u8 reserved_at_40[0x4];
8643 u8 int_vector[0x10];
8645 u8 reserved_at_60[0x20];
8648 struct mlx5_ifc_attach_to_mcg_out_bits {
8650 u8 reserved_at_8[0x18];
8654 u8 reserved_at_40[0x40];
8657 struct mlx5_ifc_attach_to_mcg_in_bits {
8661 u8 reserved_at_20[0x10];
8664 u8 reserved_at_40[0x8];
8667 u8 reserved_at_60[0x20];
8669 u8 multicast_gid[16][0x8];
8672 struct mlx5_ifc_arm_xrq_out_bits {
8674 u8 reserved_at_8[0x18];
8678 u8 reserved_at_40[0x40];
8681 struct mlx5_ifc_arm_xrq_in_bits {
8683 u8 reserved_at_10[0x10];
8685 u8 reserved_at_20[0x10];
8688 u8 reserved_at_40[0x8];
8691 u8 reserved_at_60[0x10];
8695 struct mlx5_ifc_arm_xrc_srq_out_bits {
8697 u8 reserved_at_8[0x18];
8701 u8 reserved_at_40[0x40];
8705 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8708 struct mlx5_ifc_arm_xrc_srq_in_bits {
8712 u8 reserved_at_20[0x10];
8715 u8 reserved_at_40[0x8];
8718 u8 reserved_at_60[0x10];
8722 struct mlx5_ifc_arm_rq_out_bits {
8724 u8 reserved_at_8[0x18];
8728 u8 reserved_at_40[0x40];
8732 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8733 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8736 struct mlx5_ifc_arm_rq_in_bits {
8740 u8 reserved_at_20[0x10];
8743 u8 reserved_at_40[0x8];
8744 u8 srq_number[0x18];
8746 u8 reserved_at_60[0x10];
8750 struct mlx5_ifc_arm_dct_out_bits {
8752 u8 reserved_at_8[0x18];
8756 u8 reserved_at_40[0x40];
8759 struct mlx5_ifc_arm_dct_in_bits {
8761 u8 reserved_at_10[0x10];
8763 u8 reserved_at_20[0x10];
8766 u8 reserved_at_40[0x8];
8767 u8 dct_number[0x18];
8769 u8 reserved_at_60[0x20];
8772 struct mlx5_ifc_alloc_xrcd_out_bits {
8774 u8 reserved_at_8[0x18];
8778 u8 reserved_at_40[0x8];
8781 u8 reserved_at_60[0x20];
8784 struct mlx5_ifc_alloc_xrcd_in_bits {
8788 u8 reserved_at_20[0x10];
8791 u8 reserved_at_40[0x40];
8794 struct mlx5_ifc_alloc_uar_out_bits {
8796 u8 reserved_at_8[0x18];
8800 u8 reserved_at_40[0x8];
8803 u8 reserved_at_60[0x20];
8806 struct mlx5_ifc_alloc_uar_in_bits {
8810 u8 reserved_at_20[0x10];
8813 u8 reserved_at_40[0x40];
8816 struct mlx5_ifc_alloc_transport_domain_out_bits {
8818 u8 reserved_at_8[0x18];
8822 u8 reserved_at_40[0x8];
8823 u8 transport_domain[0x18];
8825 u8 reserved_at_60[0x20];
8828 struct mlx5_ifc_alloc_transport_domain_in_bits {
8832 u8 reserved_at_20[0x10];
8835 u8 reserved_at_40[0x40];
8838 struct mlx5_ifc_alloc_q_counter_out_bits {
8840 u8 reserved_at_8[0x18];
8844 u8 reserved_at_40[0x18];
8845 u8 counter_set_id[0x8];
8847 u8 reserved_at_60[0x20];
8850 struct mlx5_ifc_alloc_q_counter_in_bits {
8854 u8 reserved_at_20[0x10];
8857 u8 reserved_at_40[0x40];
8860 struct mlx5_ifc_alloc_pd_out_bits {
8862 u8 reserved_at_8[0x18];
8866 u8 reserved_at_40[0x8];
8869 u8 reserved_at_60[0x20];
8872 struct mlx5_ifc_alloc_pd_in_bits {
8876 u8 reserved_at_20[0x10];
8879 u8 reserved_at_40[0x40];
8882 struct mlx5_ifc_alloc_flow_counter_out_bits {
8884 u8 reserved_at_8[0x18];
8888 u8 flow_counter_id[0x20];
8890 u8 reserved_at_60[0x20];
8893 struct mlx5_ifc_alloc_flow_counter_in_bits {
8895 u8 reserved_at_10[0x10];
8897 u8 reserved_at_20[0x10];
8900 u8 reserved_at_40[0x38];
8901 u8 flow_counter_bulk[0x8];
8904 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8906 u8 reserved_at_8[0x18];
8910 u8 reserved_at_40[0x40];
8913 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8915 u8 reserved_at_10[0x10];
8917 u8 reserved_at_20[0x10];
8920 u8 reserved_at_40[0x20];
8922 u8 reserved_at_60[0x10];
8923 u8 vxlan_udp_port[0x10];
8926 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8928 u8 reserved_at_8[0x18];
8932 u8 reserved_at_40[0x40];
8935 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8936 u8 rate_limit[0x20];
8938 u8 burst_upper_bound[0x20];
8940 u8 reserved_at_40[0x10];
8941 u8 typical_packet_size[0x10];
8943 u8 reserved_at_60[0x120];
8946 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8950 u8 reserved_at_20[0x10];
8953 u8 reserved_at_40[0x10];
8954 u8 rate_limit_index[0x10];
8956 u8 reserved_at_60[0x20];
8958 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8961 struct mlx5_ifc_access_register_out_bits {
8963 u8 reserved_at_8[0x18];
8967 u8 reserved_at_40[0x40];
8969 u8 register_data[][0x20];
8973 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8974 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8977 struct mlx5_ifc_access_register_in_bits {
8979 u8 reserved_at_10[0x10];
8981 u8 reserved_at_20[0x10];
8984 u8 reserved_at_40[0x10];
8985 u8 register_id[0x10];
8989 u8 register_data[][0x20];
8992 struct mlx5_ifc_sltp_reg_bits {
8997 u8 reserved_at_12[0x2];
8999 u8 reserved_at_18[0x8];
9001 u8 reserved_at_20[0x20];
9003 u8 reserved_at_40[0x7];
9009 u8 reserved_at_60[0xc];
9010 u8 ob_preemp_mode[0x4];
9014 u8 reserved_at_80[0x20];
9017 struct mlx5_ifc_slrg_reg_bits {
9022 u8 reserved_at_12[0x2];
9024 u8 reserved_at_18[0x8];
9026 u8 time_to_link_up[0x10];
9027 u8 reserved_at_30[0xc];
9028 u8 grade_lane_speed[0x4];
9030 u8 grade_version[0x8];
9033 u8 reserved_at_60[0x4];
9034 u8 height_grade_type[0x4];
9035 u8 height_grade[0x18];
9040 u8 reserved_at_a0[0x10];
9041 u8 height_sigma[0x10];
9043 u8 reserved_at_c0[0x20];
9045 u8 reserved_at_e0[0x4];
9046 u8 phase_grade_type[0x4];
9047 u8 phase_grade[0x18];
9049 u8 reserved_at_100[0x8];
9050 u8 phase_eo_pos[0x8];
9051 u8 reserved_at_110[0x8];
9052 u8 phase_eo_neg[0x8];
9054 u8 ffe_set_tested[0x10];
9055 u8 test_errors_per_lane[0x10];
9058 struct mlx5_ifc_pvlc_reg_bits {
9059 u8 reserved_at_0[0x8];
9061 u8 reserved_at_10[0x10];
9063 u8 reserved_at_20[0x1c];
9066 u8 reserved_at_40[0x1c];
9069 u8 reserved_at_60[0x1c];
9070 u8 vl_operational[0x4];
9073 struct mlx5_ifc_pude_reg_bits {
9076 u8 reserved_at_10[0x4];
9077 u8 admin_status[0x4];
9078 u8 reserved_at_18[0x4];
9079 u8 oper_status[0x4];
9081 u8 reserved_at_20[0x60];
9084 struct mlx5_ifc_ptys_reg_bits {
9085 u8 reserved_at_0[0x1];
9086 u8 an_disable_admin[0x1];
9087 u8 an_disable_cap[0x1];
9088 u8 reserved_at_3[0x5];
9090 u8 reserved_at_10[0xd];
9094 u8 reserved_at_24[0xc];
9095 u8 data_rate_oper[0x10];
9097 u8 ext_eth_proto_capability[0x20];
9099 u8 eth_proto_capability[0x20];
9101 u8 ib_link_width_capability[0x10];
9102 u8 ib_proto_capability[0x10];
9104 u8 ext_eth_proto_admin[0x20];
9106 u8 eth_proto_admin[0x20];
9108 u8 ib_link_width_admin[0x10];
9109 u8 ib_proto_admin[0x10];
9111 u8 ext_eth_proto_oper[0x20];
9113 u8 eth_proto_oper[0x20];
9115 u8 ib_link_width_oper[0x10];
9116 u8 ib_proto_oper[0x10];
9118 u8 reserved_at_160[0x1c];
9119 u8 connector_type[0x4];
9121 u8 eth_proto_lp_advertise[0x20];
9123 u8 reserved_at_1a0[0x60];
9126 struct mlx5_ifc_mlcr_reg_bits {
9127 u8 reserved_at_0[0x8];
9129 u8 reserved_at_10[0x20];
9131 u8 beacon_duration[0x10];
9132 u8 reserved_at_40[0x10];
9134 u8 beacon_remain[0x10];
9137 struct mlx5_ifc_ptas_reg_bits {
9138 u8 reserved_at_0[0x20];
9140 u8 algorithm_options[0x10];
9141 u8 reserved_at_30[0x4];
9142 u8 repetitions_mode[0x4];
9143 u8 num_of_repetitions[0x8];
9145 u8 grade_version[0x8];
9146 u8 height_grade_type[0x4];
9147 u8 phase_grade_type[0x4];
9148 u8 height_grade_weight[0x8];
9149 u8 phase_grade_weight[0x8];
9151 u8 gisim_measure_bits[0x10];
9152 u8 adaptive_tap_measure_bits[0x10];
9154 u8 ber_bath_high_error_threshold[0x10];
9155 u8 ber_bath_mid_error_threshold[0x10];
9157 u8 ber_bath_low_error_threshold[0x10];
9158 u8 one_ratio_high_threshold[0x10];
9160 u8 one_ratio_high_mid_threshold[0x10];
9161 u8 one_ratio_low_mid_threshold[0x10];
9163 u8 one_ratio_low_threshold[0x10];
9164 u8 ndeo_error_threshold[0x10];
9166 u8 mixer_offset_step_size[0x10];
9167 u8 reserved_at_110[0x8];
9168 u8 mix90_phase_for_voltage_bath[0x8];
9170 u8 mixer_offset_start[0x10];
9171 u8 mixer_offset_end[0x10];
9173 u8 reserved_at_140[0x15];
9174 u8 ber_test_time[0xb];
9177 struct mlx5_ifc_pspa_reg_bits {
9181 u8 reserved_at_18[0x8];
9183 u8 reserved_at_20[0x20];
9186 struct mlx5_ifc_pqdr_reg_bits {
9187 u8 reserved_at_0[0x8];
9189 u8 reserved_at_10[0x5];
9191 u8 reserved_at_18[0x6];
9194 u8 reserved_at_20[0x20];
9196 u8 reserved_at_40[0x10];
9197 u8 min_threshold[0x10];
9199 u8 reserved_at_60[0x10];
9200 u8 max_threshold[0x10];
9202 u8 reserved_at_80[0x10];
9203 u8 mark_probability_denominator[0x10];
9205 u8 reserved_at_a0[0x60];
9208 struct mlx5_ifc_ppsc_reg_bits {
9209 u8 reserved_at_0[0x8];
9211 u8 reserved_at_10[0x10];
9213 u8 reserved_at_20[0x60];
9215 u8 reserved_at_80[0x1c];
9218 u8 reserved_at_a0[0x1c];
9219 u8 wrps_status[0x4];
9221 u8 reserved_at_c0[0x8];
9222 u8 up_threshold[0x8];
9223 u8 reserved_at_d0[0x8];
9224 u8 down_threshold[0x8];
9226 u8 reserved_at_e0[0x20];
9228 u8 reserved_at_100[0x1c];
9231 u8 reserved_at_120[0x1c];
9232 u8 srps_status[0x4];
9234 u8 reserved_at_140[0x40];
9237 struct mlx5_ifc_pplr_reg_bits {
9238 u8 reserved_at_0[0x8];
9240 u8 reserved_at_10[0x10];
9242 u8 reserved_at_20[0x8];
9244 u8 reserved_at_30[0x8];
9248 struct mlx5_ifc_pplm_reg_bits {
9249 u8 reserved_at_0[0x8];
9251 u8 reserved_at_10[0x10];
9253 u8 reserved_at_20[0x20];
9255 u8 port_profile_mode[0x8];
9256 u8 static_port_profile[0x8];
9257 u8 active_port_profile[0x8];
9258 u8 reserved_at_58[0x8];
9260 u8 retransmission_active[0x8];
9261 u8 fec_mode_active[0x18];
9263 u8 rs_fec_correction_bypass_cap[0x4];
9264 u8 reserved_at_84[0x8];
9265 u8 fec_override_cap_56g[0x4];
9266 u8 fec_override_cap_100g[0x4];
9267 u8 fec_override_cap_50g[0x4];
9268 u8 fec_override_cap_25g[0x4];
9269 u8 fec_override_cap_10g_40g[0x4];
9271 u8 rs_fec_correction_bypass_admin[0x4];
9272 u8 reserved_at_a4[0x8];
9273 u8 fec_override_admin_56g[0x4];
9274 u8 fec_override_admin_100g[0x4];
9275 u8 fec_override_admin_50g[0x4];
9276 u8 fec_override_admin_25g[0x4];
9277 u8 fec_override_admin_10g_40g[0x4];
9279 u8 fec_override_cap_400g_8x[0x10];
9280 u8 fec_override_cap_200g_4x[0x10];
9282 u8 fec_override_cap_100g_2x[0x10];
9283 u8 fec_override_cap_50g_1x[0x10];
9285 u8 fec_override_admin_400g_8x[0x10];
9286 u8 fec_override_admin_200g_4x[0x10];
9288 u8 fec_override_admin_100g_2x[0x10];
9289 u8 fec_override_admin_50g_1x[0x10];
9291 u8 reserved_at_140[0x140];
9294 struct mlx5_ifc_ppcnt_reg_bits {
9298 u8 reserved_at_12[0x8];
9302 u8 reserved_at_21[0x1c];
9305 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9308 struct mlx5_ifc_mpein_reg_bits {
9309 u8 reserved_at_0[0x2];
9313 u8 reserved_at_18[0x8];
9315 u8 capability_mask[0x20];
9317 u8 reserved_at_40[0x8];
9318 u8 link_width_enabled[0x8];
9319 u8 link_speed_enabled[0x10];
9321 u8 lane0_physical_position[0x8];
9322 u8 link_width_active[0x8];
9323 u8 link_speed_active[0x10];
9325 u8 num_of_pfs[0x10];
9326 u8 num_of_vfs[0x10];
9329 u8 reserved_at_b0[0x10];
9331 u8 max_read_request_size[0x4];
9332 u8 max_payload_size[0x4];
9333 u8 reserved_at_c8[0x5];
9336 u8 reserved_at_d4[0xb];
9337 u8 lane_reversal[0x1];
9339 u8 reserved_at_e0[0x14];
9342 u8 reserved_at_100[0x20];
9344 u8 device_status[0x10];
9346 u8 reserved_at_138[0x8];
9348 u8 reserved_at_140[0x10];
9349 u8 receiver_detect_result[0x10];
9351 u8 reserved_at_160[0x20];
9354 struct mlx5_ifc_mpcnt_reg_bits {
9355 u8 reserved_at_0[0x8];
9357 u8 reserved_at_10[0xa];
9361 u8 reserved_at_21[0x1f];
9363 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9366 struct mlx5_ifc_ppad_reg_bits {
9367 u8 reserved_at_0[0x3];
9369 u8 reserved_at_4[0x4];
9375 u8 reserved_at_40[0x40];
9378 struct mlx5_ifc_pmtu_reg_bits {
9379 u8 reserved_at_0[0x8];
9381 u8 reserved_at_10[0x10];
9384 u8 reserved_at_30[0x10];
9387 u8 reserved_at_50[0x10];
9390 u8 reserved_at_70[0x10];
9393 struct mlx5_ifc_pmpr_reg_bits {
9394 u8 reserved_at_0[0x8];
9396 u8 reserved_at_10[0x10];
9398 u8 reserved_at_20[0x18];
9399 u8 attenuation_5g[0x8];
9401 u8 reserved_at_40[0x18];
9402 u8 attenuation_7g[0x8];
9404 u8 reserved_at_60[0x18];
9405 u8 attenuation_12g[0x8];
9408 struct mlx5_ifc_pmpe_reg_bits {
9409 u8 reserved_at_0[0x8];
9411 u8 reserved_at_10[0xc];
9412 u8 module_status[0x4];
9414 u8 reserved_at_20[0x60];
9417 struct mlx5_ifc_pmpc_reg_bits {
9418 u8 module_state_updated[32][0x8];
9421 struct mlx5_ifc_pmlpn_reg_bits {
9422 u8 reserved_at_0[0x4];
9423 u8 mlpn_status[0x4];
9425 u8 reserved_at_10[0x10];
9428 u8 reserved_at_21[0x1f];
9431 struct mlx5_ifc_pmlp_reg_bits {
9433 u8 reserved_at_1[0x7];
9435 u8 reserved_at_10[0x8];
9438 u8 lane0_module_mapping[0x20];
9440 u8 lane1_module_mapping[0x20];
9442 u8 lane2_module_mapping[0x20];
9444 u8 lane3_module_mapping[0x20];
9446 u8 reserved_at_a0[0x160];
9449 struct mlx5_ifc_pmaos_reg_bits {
9450 u8 reserved_at_0[0x8];
9452 u8 reserved_at_10[0x4];
9453 u8 admin_status[0x4];
9454 u8 reserved_at_18[0x4];
9455 u8 oper_status[0x4];
9459 u8 reserved_at_22[0x1c];
9462 u8 reserved_at_40[0x40];
9465 struct mlx5_ifc_plpc_reg_bits {
9466 u8 reserved_at_0[0x4];
9468 u8 reserved_at_10[0x4];
9470 u8 reserved_at_18[0x8];
9472 u8 reserved_at_20[0x10];
9473 u8 lane_speed[0x10];
9475 u8 reserved_at_40[0x17];
9477 u8 fec_mode_policy[0x8];
9479 u8 retransmission_capability[0x8];
9480 u8 fec_mode_capability[0x18];
9482 u8 retransmission_support_admin[0x8];
9483 u8 fec_mode_support_admin[0x18];
9485 u8 retransmission_request_admin[0x8];
9486 u8 fec_mode_request_admin[0x18];
9488 u8 reserved_at_c0[0x80];
9491 struct mlx5_ifc_plib_reg_bits {
9492 u8 reserved_at_0[0x8];
9494 u8 reserved_at_10[0x8];
9497 u8 reserved_at_20[0x60];
9500 struct mlx5_ifc_plbf_reg_bits {
9501 u8 reserved_at_0[0x8];
9503 u8 reserved_at_10[0xd];
9506 u8 reserved_at_20[0x20];
9509 struct mlx5_ifc_pipg_reg_bits {
9510 u8 reserved_at_0[0x8];
9512 u8 reserved_at_10[0x10];
9515 u8 reserved_at_21[0x19];
9517 u8 reserved_at_3e[0x2];
9520 struct mlx5_ifc_pifr_reg_bits {
9521 u8 reserved_at_0[0x8];
9523 u8 reserved_at_10[0x10];
9525 u8 reserved_at_20[0xe0];
9527 u8 port_filter[8][0x20];
9529 u8 port_filter_update_en[8][0x20];
9532 struct mlx5_ifc_pfcc_reg_bits {
9533 u8 reserved_at_0[0x8];
9535 u8 reserved_at_10[0xb];
9536 u8 ppan_mask_n[0x1];
9537 u8 minor_stall_mask[0x1];
9538 u8 critical_stall_mask[0x1];
9539 u8 reserved_at_1e[0x2];
9542 u8 reserved_at_24[0x4];
9543 u8 prio_mask_tx[0x8];
9544 u8 reserved_at_30[0x8];
9545 u8 prio_mask_rx[0x8];
9549 u8 pptx_mask_n[0x1];
9550 u8 reserved_at_43[0x5];
9552 u8 reserved_at_50[0x10];
9556 u8 pprx_mask_n[0x1];
9557 u8 reserved_at_63[0x5];
9559 u8 reserved_at_70[0x10];
9561 u8 device_stall_minor_watermark[0x10];
9562 u8 device_stall_critical_watermark[0x10];
9564 u8 reserved_at_a0[0x60];
9567 struct mlx5_ifc_pelc_reg_bits {
9569 u8 reserved_at_4[0x4];
9571 u8 reserved_at_10[0x10];
9574 u8 op_capability[0x8];
9580 u8 capability[0x40];
9586 u8 reserved_at_140[0x80];
9589 struct mlx5_ifc_peir_reg_bits {
9590 u8 reserved_at_0[0x8];
9592 u8 reserved_at_10[0x10];
9594 u8 reserved_at_20[0xc];
9595 u8 error_count[0x4];
9596 u8 reserved_at_30[0x10];
9598 u8 reserved_at_40[0xc];
9600 u8 reserved_at_50[0x8];
9604 struct mlx5_ifc_mpegc_reg_bits {
9605 u8 reserved_at_0[0x30];
9606 u8 field_select[0x10];
9608 u8 tx_overflow_sense[0x1];
9611 u8 reserved_at_43[0x1b];
9612 u8 tx_lossy_overflow_oper[0x2];
9614 u8 reserved_at_60[0x100];
9618 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1,
9619 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2,
9620 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3,
9623 struct mlx5_ifc_mtutc_reg_bits {
9624 u8 reserved_at_0[0x1c];
9627 u8 freq_adjustment[0x20];
9629 u8 reserved_at_40[0x40];
9633 u8 reserved_at_a0[0x2];
9636 u8 time_adjustment[0x20];
9639 struct mlx5_ifc_pcam_enhanced_features_bits {
9640 u8 reserved_at_0[0x68];
9641 u8 fec_50G_per_lane_in_pplm[0x1];
9642 u8 reserved_at_69[0x4];
9643 u8 rx_icrc_encapsulated_counter[0x1];
9644 u8 reserved_at_6e[0x4];
9645 u8 ptys_extended_ethernet[0x1];
9646 u8 reserved_at_73[0x3];
9648 u8 reserved_at_77[0x3];
9649 u8 per_lane_error_counters[0x1];
9650 u8 rx_buffer_fullness_counters[0x1];
9651 u8 ptys_connector_type[0x1];
9652 u8 reserved_at_7d[0x1];
9653 u8 ppcnt_discard_group[0x1];
9654 u8 ppcnt_statistical_group[0x1];
9657 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9658 u8 port_access_reg_cap_mask_127_to_96[0x20];
9659 u8 port_access_reg_cap_mask_95_to_64[0x20];
9661 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9663 u8 port_access_reg_cap_mask_34_to_32[0x3];
9665 u8 port_access_reg_cap_mask_31_to_13[0x13];
9668 u8 port_access_reg_cap_mask_10_to_09[0x2];
9670 u8 port_access_reg_cap_mask_07_to_00[0x8];
9673 struct mlx5_ifc_pcam_reg_bits {
9674 u8 reserved_at_0[0x8];
9675 u8 feature_group[0x8];
9676 u8 reserved_at_10[0x8];
9677 u8 access_reg_group[0x8];
9679 u8 reserved_at_20[0x20];
9682 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9683 u8 reserved_at_0[0x80];
9684 } port_access_reg_cap_mask;
9686 u8 reserved_at_c0[0x80];
9689 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9690 u8 reserved_at_0[0x80];
9693 u8 reserved_at_1c0[0xc0];
9696 struct mlx5_ifc_mcam_enhanced_features_bits {
9697 u8 reserved_at_0[0x5d];
9698 u8 mcia_32dwords[0x1];
9699 u8 reserved_at_5e[0xc];
9700 u8 reset_state[0x1];
9701 u8 ptpcyc2realtime_modify[0x1];
9702 u8 reserved_at_6c[0x2];
9703 u8 pci_status_and_power[0x1];
9704 u8 reserved_at_6f[0x5];
9705 u8 mark_tx_action_cnp[0x1];
9706 u8 mark_tx_action_cqe[0x1];
9707 u8 dynamic_tx_overflow[0x1];
9708 u8 reserved_at_77[0x4];
9709 u8 pcie_outbound_stalled[0x1];
9710 u8 tx_overflow_buffer_pkt[0x1];
9711 u8 mtpps_enh_out_per_adj[0x1];
9713 u8 pcie_performance_group[0x1];
9716 struct mlx5_ifc_mcam_access_reg_bits {
9717 u8 reserved_at_0[0x1c];
9723 u8 regs_95_to_87[0x9];
9726 u8 regs_84_to_68[0x11];
9727 u8 tracer_registers[0x4];
9729 u8 regs_63_to_46[0x12];
9731 u8 regs_44_to_32[0xd];
9733 u8 regs_31_to_0[0x20];
9736 struct mlx5_ifc_mcam_access_reg_bits1 {
9737 u8 regs_127_to_96[0x20];
9739 u8 regs_95_to_64[0x20];
9741 u8 regs_63_to_32[0x20];
9743 u8 regs_31_to_0[0x20];
9746 struct mlx5_ifc_mcam_access_reg_bits2 {
9747 u8 regs_127_to_99[0x1d];
9749 u8 regs_97_to_96[0x2];
9751 u8 regs_95_to_64[0x20];
9753 u8 regs_63_to_32[0x20];
9755 u8 regs_31_to_0[0x20];
9758 struct mlx5_ifc_mcam_reg_bits {
9759 u8 reserved_at_0[0x8];
9760 u8 feature_group[0x8];
9761 u8 reserved_at_10[0x8];
9762 u8 access_reg_group[0x8];
9764 u8 reserved_at_20[0x20];
9767 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9768 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9769 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9770 u8 reserved_at_0[0x80];
9771 } mng_access_reg_cap_mask;
9773 u8 reserved_at_c0[0x80];
9776 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9777 u8 reserved_at_0[0x80];
9778 } mng_feature_cap_mask;
9780 u8 reserved_at_1c0[0x80];
9783 struct mlx5_ifc_qcam_access_reg_cap_mask {
9784 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9786 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9790 u8 qcam_access_reg_cap_mask_0[0x1];
9793 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9794 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9795 u8 qpts_trust_both[0x1];
9798 struct mlx5_ifc_qcam_reg_bits {
9799 u8 reserved_at_0[0x8];
9800 u8 feature_group[0x8];
9801 u8 reserved_at_10[0x8];
9802 u8 access_reg_group[0x8];
9803 u8 reserved_at_20[0x20];
9806 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9807 u8 reserved_at_0[0x80];
9808 } qos_access_reg_cap_mask;
9810 u8 reserved_at_c0[0x80];
9813 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9814 u8 reserved_at_0[0x80];
9815 } qos_feature_cap_mask;
9817 u8 reserved_at_1c0[0x80];
9820 struct mlx5_ifc_core_dump_reg_bits {
9821 u8 reserved_at_0[0x18];
9822 u8 core_dump_type[0x8];
9824 u8 reserved_at_20[0x30];
9827 u8 reserved_at_60[0x8];
9829 u8 reserved_at_80[0x180];
9832 struct mlx5_ifc_pcap_reg_bits {
9833 u8 reserved_at_0[0x8];
9835 u8 reserved_at_10[0x10];
9837 u8 port_capability_mask[4][0x20];
9840 struct mlx5_ifc_paos_reg_bits {
9843 u8 reserved_at_10[0x4];
9844 u8 admin_status[0x4];
9845 u8 reserved_at_18[0x4];
9846 u8 oper_status[0x4];
9850 u8 reserved_at_22[0x1c];
9853 u8 reserved_at_40[0x40];
9856 struct mlx5_ifc_pamp_reg_bits {
9857 u8 reserved_at_0[0x8];
9858 u8 opamp_group[0x8];
9859 u8 reserved_at_10[0xc];
9860 u8 opamp_group_type[0x4];
9862 u8 start_index[0x10];
9863 u8 reserved_at_30[0x4];
9864 u8 num_of_indices[0xc];
9866 u8 index_data[18][0x10];
9869 struct mlx5_ifc_pcmr_reg_bits {
9870 u8 reserved_at_0[0x8];
9872 u8 reserved_at_10[0x10];
9874 u8 entropy_force_cap[0x1];
9875 u8 entropy_calc_cap[0x1];
9876 u8 entropy_gre_calc_cap[0x1];
9877 u8 reserved_at_23[0xf];
9878 u8 rx_ts_over_crc_cap[0x1];
9879 u8 reserved_at_33[0xb];
9881 u8 reserved_at_3f[0x1];
9883 u8 entropy_force[0x1];
9884 u8 entropy_calc[0x1];
9885 u8 entropy_gre_calc[0x1];
9886 u8 reserved_at_43[0xf];
9887 u8 rx_ts_over_crc[0x1];
9888 u8 reserved_at_53[0xb];
9890 u8 reserved_at_5f[0x1];
9893 struct mlx5_ifc_lane_2_module_mapping_bits {
9894 u8 reserved_at_0[0x4];
9896 u8 reserved_at_8[0x4];
9898 u8 reserved_at_10[0x8];
9902 struct mlx5_ifc_bufferx_reg_bits {
9903 u8 reserved_at_0[0x6];
9906 u8 reserved_at_8[0x8];
9909 u8 xoff_threshold[0x10];
9910 u8 xon_threshold[0x10];
9913 struct mlx5_ifc_set_node_in_bits {
9914 u8 node_description[64][0x8];
9917 struct mlx5_ifc_register_power_settings_bits {
9918 u8 reserved_at_0[0x18];
9919 u8 power_settings_level[0x8];
9921 u8 reserved_at_20[0x60];
9924 struct mlx5_ifc_register_host_endianness_bits {
9926 u8 reserved_at_1[0x1f];
9928 u8 reserved_at_20[0x60];
9931 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9932 u8 reserved_at_0[0x20];
9936 u8 addressh_63_32[0x20];
9938 u8 addressl_31_0[0x20];
9941 struct mlx5_ifc_ud_adrs_vector_bits {
9945 u8 reserved_at_41[0x7];
9946 u8 destination_qp_dct[0x18];
9948 u8 static_rate[0x4];
9949 u8 sl_eth_prio[0x4];
9952 u8 rlid_udp_sport[0x10];
9954 u8 reserved_at_80[0x20];
9956 u8 rmac_47_16[0x20];
9962 u8 reserved_at_e0[0x1];
9964 u8 reserved_at_e2[0x2];
9965 u8 src_addr_index[0x8];
9966 u8 flow_label[0x14];
9968 u8 rgid_rip[16][0x8];
9971 struct mlx5_ifc_pages_req_event_bits {
9972 u8 reserved_at_0[0x10];
9973 u8 function_id[0x10];
9977 u8 reserved_at_40[0xa0];
9980 struct mlx5_ifc_eqe_bits {
9981 u8 reserved_at_0[0x8];
9983 u8 reserved_at_10[0x8];
9984 u8 event_sub_type[0x8];
9986 u8 reserved_at_20[0xe0];
9988 union mlx5_ifc_event_auto_bits event_data;
9990 u8 reserved_at_1e0[0x10];
9992 u8 reserved_at_1f8[0x7];
9997 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
10000 struct mlx5_ifc_cmd_queue_entry_bits {
10002 u8 reserved_at_8[0x18];
10004 u8 input_length[0x20];
10006 u8 input_mailbox_pointer_63_32[0x20];
10008 u8 input_mailbox_pointer_31_9[0x17];
10009 u8 reserved_at_77[0x9];
10011 u8 command_input_inline_data[16][0x8];
10013 u8 command_output_inline_data[16][0x8];
10015 u8 output_mailbox_pointer_63_32[0x20];
10017 u8 output_mailbox_pointer_31_9[0x17];
10018 u8 reserved_at_1b7[0x9];
10020 u8 output_length[0x20];
10024 u8 reserved_at_1f0[0x8];
10029 struct mlx5_ifc_cmd_out_bits {
10031 u8 reserved_at_8[0x18];
10035 u8 command_output[0x20];
10038 struct mlx5_ifc_cmd_in_bits {
10040 u8 reserved_at_10[0x10];
10042 u8 reserved_at_20[0x10];
10045 u8 command[][0x20];
10048 struct mlx5_ifc_cmd_if_box_bits {
10049 u8 mailbox_data[512][0x8];
10051 u8 reserved_at_1000[0x180];
10053 u8 next_pointer_63_32[0x20];
10055 u8 next_pointer_31_10[0x16];
10056 u8 reserved_at_11b6[0xa];
10058 u8 block_number[0x20];
10060 u8 reserved_at_11e0[0x8];
10062 u8 ctrl_signature[0x8];
10066 struct mlx5_ifc_mtt_bits {
10067 u8 ptag_63_32[0x20];
10069 u8 ptag_31_8[0x18];
10070 u8 reserved_at_38[0x6];
10075 struct mlx5_ifc_query_wol_rol_out_bits {
10077 u8 reserved_at_8[0x18];
10081 u8 reserved_at_40[0x10];
10085 u8 reserved_at_60[0x20];
10088 struct mlx5_ifc_query_wol_rol_in_bits {
10090 u8 reserved_at_10[0x10];
10092 u8 reserved_at_20[0x10];
10095 u8 reserved_at_40[0x40];
10098 struct mlx5_ifc_set_wol_rol_out_bits {
10100 u8 reserved_at_8[0x18];
10104 u8 reserved_at_40[0x40];
10107 struct mlx5_ifc_set_wol_rol_in_bits {
10109 u8 reserved_at_10[0x10];
10111 u8 reserved_at_20[0x10];
10114 u8 rol_mode_valid[0x1];
10115 u8 wol_mode_valid[0x1];
10116 u8 reserved_at_42[0xe];
10120 u8 reserved_at_60[0x20];
10124 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
10125 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
10126 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
10130 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
10131 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
10132 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
10136 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
10137 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
10138 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
10139 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
10140 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
10141 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
10142 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
10143 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
10144 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
10145 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
10146 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
10149 struct mlx5_ifc_initial_seg_bits {
10150 u8 fw_rev_minor[0x10];
10151 u8 fw_rev_major[0x10];
10153 u8 cmd_interface_rev[0x10];
10154 u8 fw_rev_subminor[0x10];
10156 u8 reserved_at_40[0x40];
10158 u8 cmdq_phy_addr_63_32[0x20];
10160 u8 cmdq_phy_addr_31_12[0x14];
10161 u8 reserved_at_b4[0x2];
10162 u8 nic_interface[0x2];
10163 u8 log_cmdq_size[0x4];
10164 u8 log_cmdq_stride[0x4];
10166 u8 command_doorbell_vector[0x20];
10168 u8 reserved_at_e0[0xf00];
10170 u8 initializing[0x1];
10171 u8 reserved_at_fe1[0x4];
10172 u8 nic_interface_supported[0x3];
10173 u8 embedded_cpu[0x1];
10174 u8 reserved_at_fe9[0x17];
10176 struct mlx5_ifc_health_buffer_bits health_buffer;
10178 u8 no_dram_nic_offset[0x20];
10180 u8 reserved_at_1220[0x6e40];
10182 u8 reserved_at_8060[0x1f];
10185 u8 health_syndrome[0x8];
10186 u8 health_counter[0x18];
10188 u8 reserved_at_80a0[0x17fc0];
10191 struct mlx5_ifc_mtpps_reg_bits {
10192 u8 reserved_at_0[0xc];
10193 u8 cap_number_of_pps_pins[0x4];
10194 u8 reserved_at_10[0x4];
10195 u8 cap_max_num_of_pps_in_pins[0x4];
10196 u8 reserved_at_18[0x4];
10197 u8 cap_max_num_of_pps_out_pins[0x4];
10199 u8 reserved_at_20[0x24];
10200 u8 cap_pin_3_mode[0x4];
10201 u8 reserved_at_48[0x4];
10202 u8 cap_pin_2_mode[0x4];
10203 u8 reserved_at_50[0x4];
10204 u8 cap_pin_1_mode[0x4];
10205 u8 reserved_at_58[0x4];
10206 u8 cap_pin_0_mode[0x4];
10208 u8 reserved_at_60[0x4];
10209 u8 cap_pin_7_mode[0x4];
10210 u8 reserved_at_68[0x4];
10211 u8 cap_pin_6_mode[0x4];
10212 u8 reserved_at_70[0x4];
10213 u8 cap_pin_5_mode[0x4];
10214 u8 reserved_at_78[0x4];
10215 u8 cap_pin_4_mode[0x4];
10217 u8 field_select[0x20];
10218 u8 reserved_at_a0[0x60];
10221 u8 reserved_at_101[0xb];
10223 u8 reserved_at_110[0x4];
10227 u8 reserved_at_120[0x20];
10229 u8 time_stamp[0x40];
10231 u8 out_pulse_duration[0x10];
10232 u8 out_periodic_adjustment[0x10];
10233 u8 enhanced_out_periodic_adjustment[0x20];
10235 u8 reserved_at_1c0[0x20];
10238 struct mlx5_ifc_mtppse_reg_bits {
10239 u8 reserved_at_0[0x18];
10242 u8 reserved_at_21[0x1b];
10243 u8 event_generation_mode[0x4];
10244 u8 reserved_at_40[0x40];
10247 struct mlx5_ifc_mcqs_reg_bits {
10248 u8 last_index_flag[0x1];
10249 u8 reserved_at_1[0x7];
10251 u8 component_index[0x10];
10253 u8 reserved_at_20[0x10];
10254 u8 identifier[0x10];
10256 u8 reserved_at_40[0x17];
10257 u8 component_status[0x5];
10258 u8 component_update_state[0x4];
10260 u8 last_update_state_changer_type[0x4];
10261 u8 last_update_state_changer_host_id[0x4];
10262 u8 reserved_at_68[0x18];
10265 struct mlx5_ifc_mcqi_cap_bits {
10266 u8 supported_info_bitmask[0x20];
10268 u8 component_size[0x20];
10270 u8 max_component_size[0x20];
10272 u8 log_mcda_word_size[0x4];
10273 u8 reserved_at_64[0xc];
10274 u8 mcda_max_write_size[0x10];
10277 u8 reserved_at_81[0x1];
10278 u8 match_chip_id[0x1];
10279 u8 match_psid[0x1];
10280 u8 check_user_timestamp[0x1];
10281 u8 match_base_guid_mac[0x1];
10282 u8 reserved_at_86[0x1a];
10285 struct mlx5_ifc_mcqi_version_bits {
10286 u8 reserved_at_0[0x2];
10287 u8 build_time_valid[0x1];
10288 u8 user_defined_time_valid[0x1];
10289 u8 reserved_at_4[0x14];
10290 u8 version_string_length[0x8];
10294 u8 build_time[0x40];
10296 u8 user_defined_time[0x40];
10298 u8 build_tool_version[0x20];
10300 u8 reserved_at_e0[0x20];
10302 u8 version_string[92][0x8];
10305 struct mlx5_ifc_mcqi_activation_method_bits {
10306 u8 pending_server_ac_power_cycle[0x1];
10307 u8 pending_server_dc_power_cycle[0x1];
10308 u8 pending_server_reboot[0x1];
10309 u8 pending_fw_reset[0x1];
10310 u8 auto_activate[0x1];
10311 u8 all_hosts_sync[0x1];
10312 u8 device_hw_reset[0x1];
10313 u8 reserved_at_7[0x19];
10316 union mlx5_ifc_mcqi_reg_data_bits {
10317 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
10318 struct mlx5_ifc_mcqi_version_bits mcqi_version;
10319 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10322 struct mlx5_ifc_mcqi_reg_bits {
10323 u8 read_pending_component[0x1];
10324 u8 reserved_at_1[0xf];
10325 u8 component_index[0x10];
10327 u8 reserved_at_20[0x20];
10329 u8 reserved_at_40[0x1b];
10332 u8 info_size[0x20];
10336 u8 reserved_at_a0[0x10];
10337 u8 data_size[0x10];
10339 union mlx5_ifc_mcqi_reg_data_bits data[];
10342 struct mlx5_ifc_mcc_reg_bits {
10343 u8 reserved_at_0[0x4];
10344 u8 time_elapsed_since_last_cmd[0xc];
10345 u8 reserved_at_10[0x8];
10346 u8 instruction[0x8];
10348 u8 reserved_at_20[0x10];
10349 u8 component_index[0x10];
10351 u8 reserved_at_40[0x8];
10352 u8 update_handle[0x18];
10354 u8 handle_owner_type[0x4];
10355 u8 handle_owner_host_id[0x4];
10356 u8 reserved_at_68[0x1];
10357 u8 control_progress[0x7];
10358 u8 error_code[0x8];
10359 u8 reserved_at_78[0x4];
10360 u8 control_state[0x4];
10362 u8 component_size[0x20];
10364 u8 reserved_at_a0[0x60];
10367 struct mlx5_ifc_mcda_reg_bits {
10368 u8 reserved_at_0[0x8];
10369 u8 update_handle[0x18];
10373 u8 reserved_at_40[0x10];
10376 u8 reserved_at_60[0x20];
10382 MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10383 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10384 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10385 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3,
10386 MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10390 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10391 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10395 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10396 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10397 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10400 struct mlx5_ifc_mfrl_reg_bits {
10401 u8 reserved_at_0[0x20];
10403 u8 reserved_at_20[0x2];
10404 u8 pci_sync_for_fw_update_start[0x1];
10405 u8 pci_sync_for_fw_update_resp[0x2];
10406 u8 rst_type_sel[0x3];
10407 u8 reserved_at_28[0x4];
10408 u8 reset_state[0x4];
10409 u8 reset_type[0x8];
10410 u8 reset_level[0x8];
10413 struct mlx5_ifc_mirc_reg_bits {
10414 u8 reserved_at_0[0x18];
10415 u8 status_code[0x8];
10417 u8 reserved_at_20[0x20];
10420 struct mlx5_ifc_pddr_monitor_opcode_bits {
10421 u8 reserved_at_0[0x10];
10422 u8 monitor_opcode[0x10];
10425 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10426 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10427 u8 reserved_at_0[0x20];
10431 /* Monitor opcodes */
10432 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10435 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10436 u8 reserved_at_0[0x10];
10437 u8 group_opcode[0x10];
10439 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10441 u8 reserved_at_40[0x20];
10443 u8 status_message[59][0x20];
10446 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10447 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10448 u8 reserved_at_0[0x7c0];
10452 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1,
10455 struct mlx5_ifc_pddr_reg_bits {
10456 u8 reserved_at_0[0x8];
10457 u8 local_port[0x8];
10459 u8 reserved_at_12[0xe];
10461 u8 reserved_at_20[0x18];
10462 u8 page_select[0x8];
10464 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10467 struct mlx5_ifc_mrtc_reg_bits {
10468 u8 time_synced[0x1];
10469 u8 reserved_at_1[0x1f];
10471 u8 reserved_at_20[0x20];
10478 union mlx5_ifc_ports_control_registers_document_bits {
10479 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10480 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10481 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10482 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10483 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10484 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10485 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10486 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10487 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10488 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10489 struct mlx5_ifc_pamp_reg_bits pamp_reg;
10490 struct mlx5_ifc_paos_reg_bits paos_reg;
10491 struct mlx5_ifc_pcap_reg_bits pcap_reg;
10492 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10493 struct mlx5_ifc_pddr_reg_bits pddr_reg;
10494 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10495 struct mlx5_ifc_peir_reg_bits peir_reg;
10496 struct mlx5_ifc_pelc_reg_bits pelc_reg;
10497 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10498 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10499 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10500 struct mlx5_ifc_pifr_reg_bits pifr_reg;
10501 struct mlx5_ifc_pipg_reg_bits pipg_reg;
10502 struct mlx5_ifc_plbf_reg_bits plbf_reg;
10503 struct mlx5_ifc_plib_reg_bits plib_reg;
10504 struct mlx5_ifc_plpc_reg_bits plpc_reg;
10505 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10506 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10507 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10508 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10509 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10510 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10511 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10512 struct mlx5_ifc_ppad_reg_bits ppad_reg;
10513 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10514 struct mlx5_ifc_mpein_reg_bits mpein_reg;
10515 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10516 struct mlx5_ifc_pplm_reg_bits pplm_reg;
10517 struct mlx5_ifc_pplr_reg_bits pplr_reg;
10518 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10519 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10520 struct mlx5_ifc_pspa_reg_bits pspa_reg;
10521 struct mlx5_ifc_ptas_reg_bits ptas_reg;
10522 struct mlx5_ifc_ptys_reg_bits ptys_reg;
10523 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10524 struct mlx5_ifc_pude_reg_bits pude_reg;
10525 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10526 struct mlx5_ifc_slrg_reg_bits slrg_reg;
10527 struct mlx5_ifc_sltp_reg_bits sltp_reg;
10528 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10529 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
10530 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
10531 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10532 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
10533 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10534 struct mlx5_ifc_mcc_reg_bits mcc_reg;
10535 struct mlx5_ifc_mcda_reg_bits mcda_reg;
10536 struct mlx5_ifc_mirc_reg_bits mirc_reg;
10537 struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
10538 struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
10539 struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
10540 u8 reserved_at_0[0x60e0];
10543 union mlx5_ifc_debug_enhancements_document_bits {
10544 struct mlx5_ifc_health_buffer_bits health_buffer;
10545 u8 reserved_at_0[0x200];
10548 union mlx5_ifc_uplink_pci_interface_document_bits {
10549 struct mlx5_ifc_initial_seg_bits initial_seg;
10550 u8 reserved_at_0[0x20060];
10553 struct mlx5_ifc_set_flow_table_root_out_bits {
10555 u8 reserved_at_8[0x18];
10559 u8 reserved_at_40[0x40];
10562 struct mlx5_ifc_set_flow_table_root_in_bits {
10564 u8 reserved_at_10[0x10];
10566 u8 reserved_at_20[0x10];
10569 u8 other_vport[0x1];
10570 u8 reserved_at_41[0xf];
10571 u8 vport_number[0x10];
10573 u8 reserved_at_60[0x20];
10575 u8 table_type[0x8];
10576 u8 reserved_at_88[0x7];
10577 u8 table_of_other_vport[0x1];
10578 u8 table_vport_number[0x10];
10580 u8 reserved_at_a0[0x8];
10583 u8 reserved_at_c0[0x8];
10584 u8 underlay_qpn[0x18];
10585 u8 table_eswitch_owner_vhca_id_valid[0x1];
10586 u8 reserved_at_e1[0xf];
10587 u8 table_eswitch_owner_vhca_id[0x10];
10588 u8 reserved_at_100[0x100];
10592 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
10593 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
10596 struct mlx5_ifc_modify_flow_table_out_bits {
10598 u8 reserved_at_8[0x18];
10602 u8 reserved_at_40[0x40];
10605 struct mlx5_ifc_modify_flow_table_in_bits {
10607 u8 reserved_at_10[0x10];
10609 u8 reserved_at_20[0x10];
10612 u8 other_vport[0x1];
10613 u8 reserved_at_41[0xf];
10614 u8 vport_number[0x10];
10616 u8 reserved_at_60[0x10];
10617 u8 modify_field_select[0x10];
10619 u8 table_type[0x8];
10620 u8 reserved_at_88[0x18];
10622 u8 reserved_at_a0[0x8];
10625 struct mlx5_ifc_flow_table_context_bits flow_table_context;
10628 struct mlx5_ifc_ets_tcn_config_reg_bits {
10632 u8 reserved_at_3[0x9];
10634 u8 reserved_at_10[0x9];
10635 u8 bw_allocation[0x7];
10637 u8 reserved_at_20[0xc];
10638 u8 max_bw_units[0x4];
10639 u8 reserved_at_30[0x8];
10640 u8 max_bw_value[0x8];
10643 struct mlx5_ifc_ets_global_config_reg_bits {
10644 u8 reserved_at_0[0x2];
10646 u8 reserved_at_3[0x1d];
10648 u8 reserved_at_20[0xc];
10649 u8 max_bw_units[0x4];
10650 u8 reserved_at_30[0x8];
10651 u8 max_bw_value[0x8];
10654 struct mlx5_ifc_qetc_reg_bits {
10655 u8 reserved_at_0[0x8];
10656 u8 port_number[0x8];
10657 u8 reserved_at_10[0x30];
10659 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
10660 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10663 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10665 u8 reserved_at_01[0x0b];
10669 struct mlx5_ifc_qpdpm_reg_bits {
10670 u8 reserved_at_0[0x8];
10671 u8 local_port[0x8];
10672 u8 reserved_at_10[0x10];
10673 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
10676 struct mlx5_ifc_qpts_reg_bits {
10677 u8 reserved_at_0[0x8];
10678 u8 local_port[0x8];
10679 u8 reserved_at_10[0x2d];
10680 u8 trust_state[0x3];
10683 struct mlx5_ifc_pptb_reg_bits {
10684 u8 reserved_at_0[0x2];
10686 u8 reserved_at_4[0x4];
10687 u8 local_port[0x8];
10688 u8 reserved_at_10[0x6];
10693 u8 prio_x_buff[0x20];
10696 u8 reserved_at_48[0x10];
10698 u8 untagged_buff[0x4];
10701 struct mlx5_ifc_sbcam_reg_bits {
10702 u8 reserved_at_0[0x8];
10703 u8 feature_group[0x8];
10704 u8 reserved_at_10[0x8];
10705 u8 access_reg_group[0x8];
10707 u8 reserved_at_20[0x20];
10709 u8 sb_access_reg_cap_mask[4][0x20];
10711 u8 reserved_at_c0[0x80];
10713 u8 sb_feature_cap_mask[4][0x20];
10715 u8 reserved_at_1c0[0x40];
10717 u8 cap_total_buffer_size[0x20];
10719 u8 cap_cell_size[0x10];
10720 u8 cap_max_pg_buffers[0x8];
10721 u8 cap_num_pool_supported[0x8];
10723 u8 reserved_at_240[0x8];
10724 u8 cap_sbsr_stat_size[0x8];
10725 u8 cap_max_tclass_data[0x8];
10726 u8 cap_max_cpu_ingress_tclass_sb[0x8];
10729 struct mlx5_ifc_pbmc_reg_bits {
10730 u8 reserved_at_0[0x8];
10731 u8 local_port[0x8];
10732 u8 reserved_at_10[0x10];
10734 u8 xoff_timer_value[0x10];
10735 u8 xoff_refresh[0x10];
10737 u8 reserved_at_40[0x9];
10738 u8 fullness_threshold[0x7];
10739 u8 port_buffer_size[0x10];
10741 struct mlx5_ifc_bufferx_reg_bits buffer[10];
10743 u8 reserved_at_2e0[0x80];
10746 struct mlx5_ifc_qtct_reg_bits {
10747 u8 reserved_at_0[0x8];
10748 u8 port_number[0x8];
10749 u8 reserved_at_10[0xd];
10752 u8 reserved_at_20[0x1d];
10756 struct mlx5_ifc_mcia_reg_bits {
10758 u8 reserved_at_1[0x7];
10760 u8 reserved_at_10[0x8];
10763 u8 i2c_device_address[0x8];
10764 u8 page_number[0x8];
10765 u8 device_address[0x10];
10767 u8 reserved_at_40[0x10];
10770 u8 reserved_at_60[0x20];
10786 struct mlx5_ifc_dcbx_param_bits {
10787 u8 dcbx_cee_cap[0x1];
10788 u8 dcbx_ieee_cap[0x1];
10789 u8 dcbx_standby_cap[0x1];
10790 u8 reserved_at_3[0x5];
10791 u8 port_number[0x8];
10792 u8 reserved_at_10[0xa];
10793 u8 max_application_table_size[6];
10794 u8 reserved_at_20[0x15];
10795 u8 version_oper[0x3];
10796 u8 reserved_at_38[5];
10797 u8 version_admin[0x3];
10798 u8 willing_admin[0x1];
10799 u8 reserved_at_41[0x3];
10800 u8 pfc_cap_oper[0x4];
10801 u8 reserved_at_48[0x4];
10802 u8 pfc_cap_admin[0x4];
10803 u8 reserved_at_50[0x4];
10804 u8 num_of_tc_oper[0x4];
10805 u8 reserved_at_58[0x4];
10806 u8 num_of_tc_admin[0x4];
10807 u8 remote_willing[0x1];
10808 u8 reserved_at_61[3];
10809 u8 remote_pfc_cap[4];
10810 u8 reserved_at_68[0x14];
10811 u8 remote_num_of_tc[0x4];
10812 u8 reserved_at_80[0x18];
10814 u8 reserved_at_a0[0x160];
10818 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
10819 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
10820 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
10823 struct mlx5_ifc_lagc_bits {
10824 u8 fdb_selection_mode[0x1];
10825 u8 reserved_at_1[0x14];
10826 u8 port_select_mode[0x3];
10827 u8 reserved_at_18[0x5];
10830 u8 reserved_at_20[0x14];
10831 u8 tx_remap_affinity_2[0x4];
10832 u8 reserved_at_38[0x4];
10833 u8 tx_remap_affinity_1[0x4];
10836 struct mlx5_ifc_create_lag_out_bits {
10838 u8 reserved_at_8[0x18];
10842 u8 reserved_at_40[0x40];
10845 struct mlx5_ifc_create_lag_in_bits {
10847 u8 reserved_at_10[0x10];
10849 u8 reserved_at_20[0x10];
10852 struct mlx5_ifc_lagc_bits ctx;
10855 struct mlx5_ifc_modify_lag_out_bits {
10857 u8 reserved_at_8[0x18];
10861 u8 reserved_at_40[0x40];
10864 struct mlx5_ifc_modify_lag_in_bits {
10866 u8 reserved_at_10[0x10];
10868 u8 reserved_at_20[0x10];
10871 u8 reserved_at_40[0x20];
10872 u8 field_select[0x20];
10874 struct mlx5_ifc_lagc_bits ctx;
10877 struct mlx5_ifc_query_lag_out_bits {
10879 u8 reserved_at_8[0x18];
10883 struct mlx5_ifc_lagc_bits ctx;
10886 struct mlx5_ifc_query_lag_in_bits {
10888 u8 reserved_at_10[0x10];
10890 u8 reserved_at_20[0x10];
10893 u8 reserved_at_40[0x40];
10896 struct mlx5_ifc_destroy_lag_out_bits {
10898 u8 reserved_at_8[0x18];
10902 u8 reserved_at_40[0x40];
10905 struct mlx5_ifc_destroy_lag_in_bits {
10907 u8 reserved_at_10[0x10];
10909 u8 reserved_at_20[0x10];
10912 u8 reserved_at_40[0x40];
10915 struct mlx5_ifc_create_vport_lag_out_bits {
10917 u8 reserved_at_8[0x18];
10921 u8 reserved_at_40[0x40];
10924 struct mlx5_ifc_create_vport_lag_in_bits {
10926 u8 reserved_at_10[0x10];
10928 u8 reserved_at_20[0x10];
10931 u8 reserved_at_40[0x40];
10934 struct mlx5_ifc_destroy_vport_lag_out_bits {
10936 u8 reserved_at_8[0x18];
10940 u8 reserved_at_40[0x40];
10943 struct mlx5_ifc_destroy_vport_lag_in_bits {
10945 u8 reserved_at_10[0x10];
10947 u8 reserved_at_20[0x10];
10950 u8 reserved_at_40[0x40];
10954 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
10955 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
10958 struct mlx5_ifc_modify_memic_in_bits {
10962 u8 reserved_at_20[0x10];
10965 u8 reserved_at_40[0x20];
10967 u8 reserved_at_60[0x18];
10968 u8 memic_operation_type[0x8];
10970 u8 memic_start_addr[0x40];
10972 u8 reserved_at_c0[0x140];
10975 struct mlx5_ifc_modify_memic_out_bits {
10977 u8 reserved_at_8[0x18];
10981 u8 reserved_at_40[0x40];
10983 u8 memic_operation_addr[0x40];
10985 u8 reserved_at_c0[0x140];
10988 struct mlx5_ifc_alloc_memic_in_bits {
10990 u8 reserved_at_10[0x10];
10992 u8 reserved_at_20[0x10];
10995 u8 reserved_at_30[0x20];
10997 u8 reserved_at_40[0x18];
10998 u8 log_memic_addr_alignment[0x8];
11000 u8 range_start_addr[0x40];
11002 u8 range_size[0x20];
11004 u8 memic_size[0x20];
11007 struct mlx5_ifc_alloc_memic_out_bits {
11009 u8 reserved_at_8[0x18];
11013 u8 memic_start_addr[0x40];
11016 struct mlx5_ifc_dealloc_memic_in_bits {
11018 u8 reserved_at_10[0x10];
11020 u8 reserved_at_20[0x10];
11023 u8 reserved_at_40[0x40];
11025 u8 memic_start_addr[0x40];
11027 u8 memic_size[0x20];
11029 u8 reserved_at_e0[0x20];
11032 struct mlx5_ifc_dealloc_memic_out_bits {
11034 u8 reserved_at_8[0x18];
11038 u8 reserved_at_40[0x40];
11041 struct mlx5_ifc_umem_bits {
11042 u8 reserved_at_0[0x80];
11044 u8 reserved_at_80[0x1b];
11045 u8 log_page_size[0x5];
11047 u8 page_offset[0x20];
11049 u8 num_of_mtt[0x40];
11051 struct mlx5_ifc_mtt_bits mtt[];
11054 struct mlx5_ifc_uctx_bits {
11057 u8 reserved_at_20[0x160];
11060 struct mlx5_ifc_sw_icm_bits {
11061 u8 modify_field_select[0x40];
11063 u8 reserved_at_40[0x18];
11064 u8 log_sw_icm_size[0x8];
11066 u8 reserved_at_60[0x20];
11068 u8 sw_icm_start_addr[0x40];
11070 u8 reserved_at_c0[0x140];
11073 struct mlx5_ifc_geneve_tlv_option_bits {
11074 u8 modify_field_select[0x40];
11076 u8 reserved_at_40[0x18];
11077 u8 geneve_option_fte_index[0x8];
11079 u8 option_class[0x10];
11080 u8 option_type[0x8];
11081 u8 reserved_at_78[0x3];
11082 u8 option_data_length[0x5];
11084 u8 reserved_at_80[0x180];
11087 struct mlx5_ifc_create_umem_in_bits {
11091 u8 reserved_at_20[0x10];
11094 u8 reserved_at_40[0x40];
11096 struct mlx5_ifc_umem_bits umem;
11099 struct mlx5_ifc_create_umem_out_bits {
11101 u8 reserved_at_8[0x18];
11105 u8 reserved_at_40[0x8];
11108 u8 reserved_at_60[0x20];
11111 struct mlx5_ifc_destroy_umem_in_bits {
11115 u8 reserved_at_20[0x10];
11118 u8 reserved_at_40[0x8];
11121 u8 reserved_at_60[0x20];
11124 struct mlx5_ifc_destroy_umem_out_bits {
11126 u8 reserved_at_8[0x18];
11130 u8 reserved_at_40[0x40];
11133 struct mlx5_ifc_create_uctx_in_bits {
11135 u8 reserved_at_10[0x10];
11137 u8 reserved_at_20[0x10];
11140 u8 reserved_at_40[0x40];
11142 struct mlx5_ifc_uctx_bits uctx;
11145 struct mlx5_ifc_create_uctx_out_bits {
11147 u8 reserved_at_8[0x18];
11151 u8 reserved_at_40[0x10];
11154 u8 reserved_at_60[0x20];
11157 struct mlx5_ifc_destroy_uctx_in_bits {
11159 u8 reserved_at_10[0x10];
11161 u8 reserved_at_20[0x10];
11164 u8 reserved_at_40[0x10];
11167 u8 reserved_at_60[0x20];
11170 struct mlx5_ifc_destroy_uctx_out_bits {
11172 u8 reserved_at_8[0x18];
11176 u8 reserved_at_40[0x40];
11179 struct mlx5_ifc_create_sw_icm_in_bits {
11180 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11181 struct mlx5_ifc_sw_icm_bits sw_icm;
11184 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11185 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11186 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
11189 struct mlx5_ifc_mtrc_string_db_param_bits {
11190 u8 string_db_base_address[0x20];
11192 u8 reserved_at_20[0x8];
11193 u8 string_db_size[0x18];
11196 struct mlx5_ifc_mtrc_cap_bits {
11197 u8 trace_owner[0x1];
11198 u8 trace_to_memory[0x1];
11199 u8 reserved_at_2[0x4];
11201 u8 reserved_at_8[0x14];
11202 u8 num_string_db[0x4];
11204 u8 first_string_trace[0x8];
11205 u8 num_string_trace[0x8];
11206 u8 reserved_at_30[0x28];
11208 u8 log_max_trace_buffer_size[0x8];
11210 u8 reserved_at_60[0x20];
11212 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11214 u8 reserved_at_280[0x180];
11217 struct mlx5_ifc_mtrc_conf_bits {
11218 u8 reserved_at_0[0x1c];
11219 u8 trace_mode[0x4];
11220 u8 reserved_at_20[0x18];
11221 u8 log_trace_buffer_size[0x8];
11222 u8 trace_mkey[0x20];
11223 u8 reserved_at_60[0x3a0];
11226 struct mlx5_ifc_mtrc_stdb_bits {
11227 u8 string_db_index[0x4];
11228 u8 reserved_at_4[0x4];
11229 u8 read_size[0x18];
11230 u8 start_offset[0x20];
11231 u8 string_db_data[];
11234 struct mlx5_ifc_mtrc_ctrl_bits {
11235 u8 trace_status[0x2];
11236 u8 reserved_at_2[0x2];
11238 u8 reserved_at_5[0xb];
11239 u8 modify_field_select[0x10];
11240 u8 reserved_at_20[0x2b];
11241 u8 current_timestamp52_32[0x15];
11242 u8 current_timestamp31_0[0x20];
11243 u8 reserved_at_80[0x180];
11246 struct mlx5_ifc_host_params_context_bits {
11247 u8 host_number[0x8];
11248 u8 reserved_at_8[0x7];
11249 u8 host_pf_disabled[0x1];
11250 u8 host_num_of_vfs[0x10];
11252 u8 host_total_vfs[0x10];
11253 u8 host_pci_bus[0x10];
11255 u8 reserved_at_40[0x10];
11256 u8 host_pci_device[0x10];
11258 u8 reserved_at_60[0x10];
11259 u8 host_pci_function[0x10];
11261 u8 reserved_at_80[0x180];
11264 struct mlx5_ifc_query_esw_functions_in_bits {
11266 u8 reserved_at_10[0x10];
11268 u8 reserved_at_20[0x10];
11271 u8 reserved_at_40[0x40];
11274 struct mlx5_ifc_query_esw_functions_out_bits {
11276 u8 reserved_at_8[0x18];
11280 u8 reserved_at_40[0x40];
11282 struct mlx5_ifc_host_params_context_bits host_params_context;
11284 u8 reserved_at_280[0x180];
11285 u8 host_sf_enable[][0x40];
11288 struct mlx5_ifc_sf_partition_bits {
11289 u8 reserved_at_0[0x10];
11290 u8 log_num_sf[0x8];
11291 u8 log_sf_bar_size[0x8];
11294 struct mlx5_ifc_query_sf_partitions_out_bits {
11296 u8 reserved_at_8[0x18];
11300 u8 reserved_at_40[0x18];
11301 u8 num_sf_partitions[0x8];
11303 u8 reserved_at_60[0x20];
11305 struct mlx5_ifc_sf_partition_bits sf_partition[];
11308 struct mlx5_ifc_query_sf_partitions_in_bits {
11310 u8 reserved_at_10[0x10];
11312 u8 reserved_at_20[0x10];
11315 u8 reserved_at_40[0x40];
11318 struct mlx5_ifc_dealloc_sf_out_bits {
11320 u8 reserved_at_8[0x18];
11324 u8 reserved_at_40[0x40];
11327 struct mlx5_ifc_dealloc_sf_in_bits {
11329 u8 reserved_at_10[0x10];
11331 u8 reserved_at_20[0x10];
11334 u8 reserved_at_40[0x10];
11335 u8 function_id[0x10];
11337 u8 reserved_at_60[0x20];
11340 struct mlx5_ifc_alloc_sf_out_bits {
11342 u8 reserved_at_8[0x18];
11346 u8 reserved_at_40[0x40];
11349 struct mlx5_ifc_alloc_sf_in_bits {
11351 u8 reserved_at_10[0x10];
11353 u8 reserved_at_20[0x10];
11356 u8 reserved_at_40[0x10];
11357 u8 function_id[0x10];
11359 u8 reserved_at_60[0x20];
11362 struct mlx5_ifc_affiliated_event_header_bits {
11363 u8 reserved_at_0[0x10];
11370 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11371 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11372 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11376 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11377 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11378 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11382 MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11385 struct mlx5_ifc_ipsec_obj_bits {
11386 u8 modify_field_select[0x40];
11387 u8 full_offload[0x1];
11388 u8 reserved_at_41[0x1];
11390 u8 esn_overlap[0x1];
11391 u8 reserved_at_44[0x2];
11392 u8 icv_length[0x2];
11393 u8 reserved_at_48[0x4];
11394 u8 aso_return_reg[0x4];
11395 u8 reserved_at_50[0x10];
11399 u8 reserved_at_80[0x8];
11404 u8 implicit_iv[0x40];
11406 u8 reserved_at_100[0x700];
11409 struct mlx5_ifc_create_ipsec_obj_in_bits {
11410 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11411 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11415 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11416 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11419 struct mlx5_ifc_query_ipsec_obj_out_bits {
11420 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11421 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11424 struct mlx5_ifc_modify_ipsec_obj_in_bits {
11425 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11426 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11429 struct mlx5_ifc_encryption_key_obj_bits {
11430 u8 modify_field_select[0x40];
11432 u8 reserved_at_40[0x14];
11434 u8 reserved_at_58[0x4];
11437 u8 reserved_at_60[0x8];
11440 u8 reserved_at_80[0x180];
11443 u8 reserved_at_300[0x500];
11446 struct mlx5_ifc_create_encryption_key_in_bits {
11447 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11448 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11451 struct mlx5_ifc_sampler_obj_bits {
11452 u8 modify_field_select[0x40];
11454 u8 table_type[0x8];
11456 u8 reserved_at_50[0xf];
11457 u8 ignore_flow_level[0x1];
11459 u8 sample_ratio[0x20];
11461 u8 reserved_at_80[0x8];
11462 u8 sample_table_id[0x18];
11464 u8 reserved_at_a0[0x8];
11465 u8 default_table_id[0x18];
11467 u8 sw_steering_icm_address_rx[0x40];
11468 u8 sw_steering_icm_address_tx[0x40];
11470 u8 reserved_at_140[0xa0];
11473 struct mlx5_ifc_create_sampler_obj_in_bits {
11474 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11475 struct mlx5_ifc_sampler_obj_bits sampler_object;
11478 struct mlx5_ifc_query_sampler_obj_out_bits {
11479 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11480 struct mlx5_ifc_sampler_obj_bits sampler_object;
11484 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11485 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11489 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11490 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
11493 struct mlx5_ifc_tls_static_params_bits {
11495 u8 tls_version[0x4];
11497 u8 reserved_at_8[0x14];
11498 u8 encryption_standard[0x4];
11500 u8 reserved_at_20[0x20];
11502 u8 initial_record_number[0x40];
11504 u8 resync_tcp_sn[0x20];
11508 u8 implicit_iv[0x40];
11510 u8 reserved_at_100[0x8];
11511 u8 dek_index[0x18];
11513 u8 reserved_at_120[0xe0];
11516 struct mlx5_ifc_tls_progress_params_bits {
11517 u8 next_record_tcp_sn[0x20];
11519 u8 hw_resync_tcp_sn[0x20];
11521 u8 record_tracker_state[0x2];
11522 u8 auth_state[0x2];
11523 u8 reserved_at_44[0x4];
11524 u8 hw_offset_record_number[0x18];
11528 MLX5_MTT_PERM_READ = 1 << 0,
11529 MLX5_MTT_PERM_WRITE = 1 << 1,
11530 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11534 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0,
11535 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1,
11538 struct mlx5_ifc_suspend_vhca_in_bits {
11542 u8 reserved_at_20[0x10];
11545 u8 reserved_at_40[0x10];
11548 u8 reserved_at_60[0x20];
11551 struct mlx5_ifc_suspend_vhca_out_bits {
11553 u8 reserved_at_8[0x18];
11557 u8 reserved_at_40[0x40];
11561 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0,
11562 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1,
11565 struct mlx5_ifc_resume_vhca_in_bits {
11569 u8 reserved_at_20[0x10];
11572 u8 reserved_at_40[0x10];
11575 u8 reserved_at_60[0x20];
11578 struct mlx5_ifc_resume_vhca_out_bits {
11580 u8 reserved_at_8[0x18];
11584 u8 reserved_at_40[0x40];
11587 struct mlx5_ifc_query_vhca_migration_state_in_bits {
11591 u8 reserved_at_20[0x10];
11594 u8 reserved_at_40[0x10];
11597 u8 reserved_at_60[0x20];
11600 struct mlx5_ifc_query_vhca_migration_state_out_bits {
11602 u8 reserved_at_8[0x18];
11606 u8 reserved_at_40[0x40];
11608 u8 required_umem_size[0x20];
11610 u8 reserved_at_a0[0x160];
11613 struct mlx5_ifc_save_vhca_state_in_bits {
11617 u8 reserved_at_20[0x10];
11620 u8 reserved_at_40[0x10];
11623 u8 reserved_at_60[0x20];
11632 struct mlx5_ifc_save_vhca_state_out_bits {
11634 u8 reserved_at_8[0x18];
11638 u8 actual_image_size[0x20];
11640 u8 reserved_at_60[0x20];
11643 struct mlx5_ifc_load_vhca_state_in_bits {
11647 u8 reserved_at_20[0x10];
11650 u8 reserved_at_40[0x10];
11653 u8 reserved_at_60[0x20];
11662 struct mlx5_ifc_load_vhca_state_out_bits {
11664 u8 reserved_at_8[0x18];
11668 u8 reserved_at_40[0x40];
11671 #endif /* MLX5_IFC_H */