include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63 };
  64
  65 enum {
  66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  70 };
  71
  72 enum {
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  75 };
  76
  77 enum {
  78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  95         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  96         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  97         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  98         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  99         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 100         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 101         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 102         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 103         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 104         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 105         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 106         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 107         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 108         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 109         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 110         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 111         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 112         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 113         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 114         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 115         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 116         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 117         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 118         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 119         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 120         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 121         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 122         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 123         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 124         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 125         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 126         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 127         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 128         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 129         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 130         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 131         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 132         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 133         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 146         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 147         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 148         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 149         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 150         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 151         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 152         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 153         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 154         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 155         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 156         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 157         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 158         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 159         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 160         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 161         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 162         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 163         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 164         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 165         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 166         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 167         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 168         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 169         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 170         MLX5_CMD_OP_NOP                           = 0x80d,
 171         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 172         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 173         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 174         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 175         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 176         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 177         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 178         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 179         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 180         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 181         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 182         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 183         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 184         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 185         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 186         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 187         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 188         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 189         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 190         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 191         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 192         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 193         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 194         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 195         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 196         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 197         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 198         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 199         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 200         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 201         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 202         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 203         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 204         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 205         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 206         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 207         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 208         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 209         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 210         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 211         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 212         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 213         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 214         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 215         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 216         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 217         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 218         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 219         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 220         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 221         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 222         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 223         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 224         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 225         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 226         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 227         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 228         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 229         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 230         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 231         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 232         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 233         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 234         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 235         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 236         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 237         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 238         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 239         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 240         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 241         MLX5_CMD_OP_MAX
 242 };
 243
 244 struct mlx5_ifc_flow_table_fields_supported_bits {
 245         u8         outer_dmac[0x1];
 246         u8         outer_smac[0x1];
 247         u8         outer_ether_type[0x1];
 248         u8         outer_ip_version[0x1];
 249         u8         outer_first_prio[0x1];
 250         u8         outer_first_cfi[0x1];
 251         u8         outer_first_vid[0x1];
 252         u8         outer_ipv4_ttl[0x1];
 253         u8         outer_second_prio[0x1];
 254         u8         outer_second_cfi[0x1];
 255         u8         outer_second_vid[0x1];
 256         u8         reserved_at_b[0x1];
 257         u8         outer_sip[0x1];
 258         u8         outer_dip[0x1];
 259         u8         outer_frag[0x1];
 260         u8         outer_ip_protocol[0x1];
 261         u8         outer_ip_ecn[0x1];
 262         u8         outer_ip_dscp[0x1];
 263         u8         outer_udp_sport[0x1];
 264         u8         outer_udp_dport[0x1];
 265         u8         outer_tcp_sport[0x1];
 266         u8         outer_tcp_dport[0x1];
 267         u8         outer_tcp_flags[0x1];
 268         u8         outer_gre_protocol[0x1];
 269         u8         outer_gre_key[0x1];
 270         u8         outer_vxlan_vni[0x1];
 271         u8         reserved_at_1a[0x5];
 272         u8         source_eswitch_port[0x1];
 273
 274         u8         inner_dmac[0x1];
 275         u8         inner_smac[0x1];
 276         u8         inner_ether_type[0x1];
 277         u8         inner_ip_version[0x1];
 278         u8         inner_first_prio[0x1];
 279         u8         inner_first_cfi[0x1];
 280         u8         inner_first_vid[0x1];
 281         u8         reserved_at_27[0x1];
 282         u8         inner_second_prio[0x1];
 283         u8         inner_second_cfi[0x1];
 284         u8         inner_second_vid[0x1];
 285         u8         reserved_at_2b[0x1];
 286         u8         inner_sip[0x1];
 287         u8         inner_dip[0x1];
 288         u8         inner_frag[0x1];
 289         u8         inner_ip_protocol[0x1];
 290         u8         inner_ip_ecn[0x1];
 291         u8         inner_ip_dscp[0x1];
 292         u8         inner_udp_sport[0x1];
 293         u8         inner_udp_dport[0x1];
 294         u8         inner_tcp_sport[0x1];
 295         u8         inner_tcp_dport[0x1];
 296         u8         inner_tcp_flags[0x1];
 297         u8         reserved_at_37[0x9];
 298
 299         u8         reserved_at_40[0x40];
 300 };
 301
 302 struct mlx5_ifc_flow_table_prop_layout_bits {
 303         u8         ft_support[0x1];
 304         u8         reserved_at_1[0x1];
 305         u8         flow_counter[0x1];
 306         u8         flow_modify_en[0x1];
 307         u8         modify_root[0x1];
 308         u8         identified_miss_table_mode[0x1];
 309         u8         flow_table_modify[0x1];
 310         u8         encap[0x1];
 311         u8         decap[0x1];
 312         u8         reserved_at_9[0x17];
 313
 314         u8         reserved_at_20[0x2];
 315         u8         log_max_ft_size[0x6];
 316         u8         log_max_modify_header_context[0x8];
 317         u8         max_modify_header_actions[0x8];
 318         u8         max_ft_level[0x8];
 319
 320         u8         reserved_at_40[0x20];
 321
 322         u8         reserved_at_60[0x18];
 323         u8         log_max_ft_num[0x8];
 324
 325         u8         reserved_at_80[0x18];
 326         u8         log_max_destination[0x8];
 327
 328         u8         reserved_at_a0[0x18];
 329         u8         log_max_flow[0x8];
 330
 331         u8         reserved_at_c0[0x40];
 332
 333         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 334
 335         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 336 };
 337
 338 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 339         u8         send[0x1];
 340         u8         receive[0x1];
 341         u8         write[0x1];
 342         u8         read[0x1];
 343         u8         atomic[0x1];
 344         u8         srq_receive[0x1];
 345         u8         reserved_at_6[0x1a];
 346 };
 347
 348 struct mlx5_ifc_ipv4_layout_bits {
 349         u8         reserved_at_0[0x60];
 350
 351         u8         ipv4[0x20];
 352 };
 353
 354 struct mlx5_ifc_ipv6_layout_bits {
 355         u8         ipv6[16][0x8];
 356 };
 357
 358 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 359         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 360         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 361         u8         reserved_at_0[0x80];
 362 };
 363
 364 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 365         u8         smac_47_16[0x20];
 366
 367         u8         smac_15_0[0x10];
 368         u8         ethertype[0x10];
 369
 370         u8         dmac_47_16[0x20];
 371
 372         u8         dmac_15_0[0x10];
 373         u8         first_prio[0x3];
 374         u8         first_cfi[0x1];
 375         u8         first_vid[0xc];
 376
 377         u8         ip_protocol[0x8];
 378         u8         ip_dscp[0x6];
 379         u8         ip_ecn[0x2];
 380         u8         cvlan_tag[0x1];
 381         u8         svlan_tag[0x1];
 382         u8         frag[0x1];
 383         u8         ip_version[0x4];
 384         u8         tcp_flags[0x9];
 385
 386         u8         tcp_sport[0x10];
 387         u8         tcp_dport[0x10];
 388
 389         u8         reserved_at_c0[0x18];
 390         u8         ttl_hoplimit[0x8];
 391
 392         u8         udp_sport[0x10];
 393         u8         udp_dport[0x10];
 394
 395         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 396
 397         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 398 };
 399
 400 struct mlx5_ifc_fte_match_set_misc_bits {
 401         u8         reserved_at_0[0x8];
 402         u8         source_sqn[0x18];
 403
 404         u8         reserved_at_20[0x10];
 405         u8         source_port[0x10];
 406
 407         u8         outer_second_prio[0x3];
 408         u8         outer_second_cfi[0x1];
 409         u8         outer_second_vid[0xc];
 410         u8         inner_second_prio[0x3];
 411         u8         inner_second_cfi[0x1];
 412         u8         inner_second_vid[0xc];
 413
 414         u8         outer_second_cvlan_tag[0x1];
 415         u8         inner_second_cvlan_tag[0x1];
 416         u8         outer_second_svlan_tag[0x1];
 417         u8         inner_second_svlan_tag[0x1];
 418         u8         reserved_at_64[0xc];
 419         u8         gre_protocol[0x10];
 420
 421         u8         gre_key_h[0x18];
 422         u8         gre_key_l[0x8];
 423
 424         u8         vxlan_vni[0x18];
 425         u8         reserved_at_b8[0x8];
 426
 427         u8         reserved_at_c0[0x20];
 428
 429         u8         reserved_at_e0[0xc];
 430         u8         outer_ipv6_flow_label[0x14];
 431
 432         u8         reserved_at_100[0xc];
 433         u8         inner_ipv6_flow_label[0x14];
 434
 435         u8         reserved_at_120[0xe0];
 436 };
 437
 438 struct mlx5_ifc_cmd_pas_bits {
 439         u8         pa_h[0x20];
 440
 441         u8         pa_l[0x14];
 442         u8         reserved_at_34[0xc];
 443 };
 444
 445 struct mlx5_ifc_uint64_bits {
 446         u8         hi[0x20];
 447
 448         u8         lo[0x20];
 449 };
 450
 451 enum {
 452         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 453         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 454         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 455         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 456         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 457         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 458         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 459         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 460         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 461         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 462 };
 463
 464 struct mlx5_ifc_ads_bits {
 465         u8         fl[0x1];
 466         u8         free_ar[0x1];
 467         u8         reserved_at_2[0xe];
 468         u8         pkey_index[0x10];
 469
 470         u8         reserved_at_20[0x8];
 471         u8         grh[0x1];
 472         u8         mlid[0x7];
 473         u8         rlid[0x10];
 474
 475         u8         ack_timeout[0x5];
 476         u8         reserved_at_45[0x3];
 477         u8         src_addr_index[0x8];
 478         u8         reserved_at_50[0x4];
 479         u8         stat_rate[0x4];
 480         u8         hop_limit[0x8];
 481
 482         u8         reserved_at_60[0x4];
 483         u8         tclass[0x8];
 484         u8         flow_label[0x14];
 485
 486         u8         rgid_rip[16][0x8];
 487
 488         u8         reserved_at_100[0x4];
 489         u8         f_dscp[0x1];
 490         u8         f_ecn[0x1];
 491         u8         reserved_at_106[0x1];
 492         u8         f_eth_prio[0x1];
 493         u8         ecn[0x2];
 494         u8         dscp[0x6];
 495         u8         udp_sport[0x10];
 496
 497         u8         dei_cfi[0x1];
 498         u8         eth_prio[0x3];
 499         u8         sl[0x4];
 500         u8         port[0x8];
 501         u8         rmac_47_32[0x10];
 502
 503         u8         rmac_31_0[0x20];
 504 };
 505
 506 struct mlx5_ifc_flow_table_nic_cap_bits {
 507         u8         nic_rx_multi_path_tirs[0x1];
 508         u8         nic_rx_multi_path_tirs_fts[0x1];
 509         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 510         u8         reserved_at_3[0x1fd];
 511
 512         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 513
 514         u8         reserved_at_400[0x200];
 515
 516         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 517
 518         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 519
 520         u8         reserved_at_a00[0x200];
 521
 522         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 523
 524         u8         reserved_at_e00[0x7200];
 525 };
 526
 527 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 528         u8     reserved_at_0[0x200];
 529
 530         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 531
 532         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 533
 534         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 535
 536         u8      reserved_at_800[0x7800];
 537 };
 538
 539 struct mlx5_ifc_e_switch_cap_bits {
 540         u8         vport_svlan_strip[0x1];
 541         u8         vport_cvlan_strip[0x1];
 542         u8         vport_svlan_insert[0x1];
 543         u8         vport_cvlan_insert_if_not_exist[0x1];
 544         u8         vport_cvlan_insert_overwrite[0x1];
 545         u8         reserved_at_5[0x19];
 546         u8         nic_vport_node_guid_modify[0x1];
 547         u8         nic_vport_port_guid_modify[0x1];
 548
 549         u8         vxlan_encap_decap[0x1];
 550         u8         nvgre_encap_decap[0x1];
 551         u8         reserved_at_22[0x9];
 552         u8         log_max_encap_headers[0x5];
 553         u8         reserved_2b[0x6];
 554         u8         max_encap_header_size[0xa];
 555
 556         u8         reserved_40[0x7c0];
 557
 558 };
 559
 560 struct mlx5_ifc_qos_cap_bits {
 561         u8         packet_pacing[0x1];
 562         u8         esw_scheduling[0x1];
 563         u8         esw_bw_share[0x1];
 564         u8         esw_rate_limit[0x1];
 565         u8         reserved_at_4[0x1c];
 566
 567         u8         reserved_at_20[0x20];
 568
 569         u8         packet_pacing_max_rate[0x20];
 570
 571         u8         packet_pacing_min_rate[0x20];
 572
 573         u8         reserved_at_80[0x10];
 574         u8         packet_pacing_rate_table_size[0x10];
 575
 576         u8         esw_element_type[0x10];
 577         u8         esw_tsar_type[0x10];
 578
 579         u8         reserved_at_c0[0x10];
 580         u8         max_qos_para_vport[0x10];
 581
 582         u8         max_tsar_bw_share[0x20];
 583
 584         u8         reserved_at_100[0x700];
 585 };
 586
 587 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 588         u8         csum_cap[0x1];
 589         u8         vlan_cap[0x1];
 590         u8         lro_cap[0x1];
 591         u8         lro_psh_flag[0x1];
 592         u8         lro_time_stamp[0x1];
 593         u8         reserved_at_5[0x2];
 594         u8         wqe_vlan_insert[0x1];
 595         u8         self_lb_en_modifiable[0x1];
 596         u8         reserved_at_9[0x2];
 597         u8         max_lso_cap[0x5];
 598         u8         multi_pkt_send_wqe[0x2];
 599         u8         wqe_inline_mode[0x2];
 600         u8         rss_ind_tbl_cap[0x4];
 601         u8         reg_umr_sq[0x1];
 602         u8         scatter_fcs[0x1];
 603         u8         reserved_at_1a[0x1];
 604         u8         tunnel_lso_const_out_ip_id[0x1];
 605         u8         reserved_at_1c[0x2];
 606         u8         tunnel_statless_gre[0x1];
 607         u8         tunnel_stateless_vxlan[0x1];
 608
 609         u8         swp[0x1];
 610         u8         swp_csum[0x1];
 611         u8         swp_lso[0x1];
 612         u8         reserved_at_23[0x1d];
 613
 614         u8         reserved_at_40[0x10];
 615         u8         lro_min_mss_size[0x10];
 616
 617         u8         reserved_at_60[0x120];
 618
 619         u8         lro_timer_supported_periods[4][0x20];
 620
 621         u8         reserved_at_200[0x600];
 622 };
 623
 624 struct mlx5_ifc_roce_cap_bits {
 625         u8         roce_apm[0x1];
 626         u8         reserved_at_1[0x1f];
 627
 628         u8         reserved_at_20[0x60];
 629
 630         u8         reserved_at_80[0xc];
 631         u8         l3_type[0x4];
 632         u8         reserved_at_90[0x8];
 633         u8         roce_version[0x8];
 634
 635         u8         reserved_at_a0[0x10];
 636         u8         r_roce_dest_udp_port[0x10];
 637
 638         u8         r_roce_max_src_udp_port[0x10];
 639         u8         r_roce_min_src_udp_port[0x10];
 640
 641         u8         reserved_at_e0[0x10];
 642         u8         roce_address_table_size[0x10];
 643
 644         u8         reserved_at_100[0x700];
 645 };
 646
 647 enum {
 648         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 649         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 650         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 651         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 652         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 653         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 654         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 655         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 656         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 657 };
 658
 659 enum {
 660         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 661         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 662         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 663         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 664         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 665         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 666         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 667         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 668         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 669 };
 670
 671 struct mlx5_ifc_atomic_caps_bits {
 672         u8         reserved_at_0[0x40];
 673
 674         u8         atomic_req_8B_endianness_mode[0x2];
 675         u8         reserved_at_42[0x4];
 676         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 677
 678         u8         reserved_at_47[0x19];
 679
 680         u8         reserved_at_60[0x20];
 681
 682         u8         reserved_at_80[0x10];
 683         u8         atomic_operations[0x10];
 684
 685         u8         reserved_at_a0[0x10];
 686         u8         atomic_size_qp[0x10];
 687
 688         u8         reserved_at_c0[0x10];
 689         u8         atomic_size_dc[0x10];
 690
 691         u8         reserved_at_e0[0x720];
 692 };
 693
 694 struct mlx5_ifc_odp_cap_bits {
 695         u8         reserved_at_0[0x40];
 696
 697         u8         sig[0x1];
 698         u8         reserved_at_41[0x1f];
 699
 700         u8         reserved_at_60[0x20];
 701
 702         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 703
 704         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 705
 706         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 707
 708         u8         reserved_at_e0[0x720];
 709 };
 710
 711 struct mlx5_ifc_calc_op {
 712         u8        reserved_at_0[0x10];
 713         u8        reserved_at_10[0x9];
 714         u8        op_swap_endianness[0x1];
 715         u8        op_min[0x1];
 716         u8        op_xor[0x1];
 717         u8        op_or[0x1];
 718         u8        op_and[0x1];
 719         u8        op_max[0x1];
 720         u8        op_add[0x1];
 721 };
 722
 723 struct mlx5_ifc_vector_calc_cap_bits {
 724         u8         calc_matrix[0x1];
 725         u8         reserved_at_1[0x1f];
 726         u8         reserved_at_20[0x8];
 727         u8         max_vec_count[0x8];
 728         u8         reserved_at_30[0xd];
 729         u8         max_chunk_size[0x3];
 730         struct mlx5_ifc_calc_op calc0;
 731         struct mlx5_ifc_calc_op calc1;
 732         struct mlx5_ifc_calc_op calc2;
 733         struct mlx5_ifc_calc_op calc3;
 734
 735         u8         reserved_at_e0[0x720];
 736 };
 737
 738 enum {
 739         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 740         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 741         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 742 };
 743
 744 enum {
 745         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 746         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 747 };
 748
 749 enum {
 750         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 751         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 752         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 753         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 754         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 755 };
 756
 757 enum {
 758         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 759         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 760         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 761         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 762         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 763         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 764 };
 765
 766 enum {
 767         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 768         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 769 };
 770
 771 enum {
 772         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 773         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 774         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 775 };
 776
 777 enum {
 778         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 779         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 780 };
 781
 782 enum {
 783         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 784         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 785         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 786 };
 787
 788 struct mlx5_ifc_cmd_hca_cap_bits {
 789         u8         reserved_at_0[0x80];
 790
 791         u8         log_max_srq_sz[0x8];
 792         u8         log_max_qp_sz[0x8];
 793         u8         reserved_at_90[0xb];
 794         u8         log_max_qp[0x5];
 795
 796         u8         reserved_at_a0[0xb];
 797         u8         log_max_srq[0x5];
 798         u8         reserved_at_b0[0x10];
 799
 800         u8         reserved_at_c0[0x8];
 801         u8         log_max_cq_sz[0x8];
 802         u8         reserved_at_d0[0xb];
 803         u8         log_max_cq[0x5];
 804
 805         u8         log_max_eq_sz[0x8];
 806         u8         reserved_at_e8[0x2];
 807         u8         log_max_mkey[0x6];
 808         u8         reserved_at_f0[0xc];
 809         u8         log_max_eq[0x4];
 810
 811         u8         max_indirection[0x8];
 812         u8         fixed_buffer_size[0x1];
 813         u8         log_max_mrw_sz[0x7];
 814         u8         force_teardown[0x1];
 815         u8         reserved_at_111[0x1];
 816         u8         log_max_bsf_list_size[0x6];
 817         u8         umr_extended_translation_offset[0x1];
 818         u8         null_mkey[0x1];
 819         u8         log_max_klm_list_size[0x6];
 820
 821         u8         reserved_at_120[0xa];
 822         u8         log_max_ra_req_dc[0x6];
 823         u8         reserved_at_130[0xa];
 824         u8         log_max_ra_res_dc[0x6];
 825
 826         u8         reserved_at_140[0xa];
 827         u8         log_max_ra_req_qp[0x6];
 828         u8         reserved_at_150[0xa];
 829         u8         log_max_ra_res_qp[0x6];
 830
 831         u8         end_pad[0x1];
 832         u8         cc_query_allowed[0x1];
 833         u8         cc_modify_allowed[0x1];
 834         u8         start_pad[0x1];
 835         u8         cache_line_128byte[0x1];
 836         u8         reserved_at_165[0xb];
 837         u8         gid_table_size[0x10];
 838
 839         u8         out_of_seq_cnt[0x1];
 840         u8         vport_counters[0x1];
 841         u8         retransmission_q_counters[0x1];
 842         u8         reserved_at_183[0x1];
 843         u8         modify_rq_counter_set_id[0x1];
 844         u8         rq_delay_drop[0x1];
 845         u8         max_qp_cnt[0xa];
 846         u8         pkey_table_size[0x10];
 847
 848         u8         vport_group_manager[0x1];
 849         u8         vhca_group_manager[0x1];
 850         u8         ib_virt[0x1];
 851         u8         eth_virt[0x1];
 852         u8         reserved_at_1a4[0x1];
 853         u8         ets[0x1];
 854         u8         nic_flow_table[0x1];
 855         u8         eswitch_flow_table[0x1];
 856         u8         early_vf_enable[0x1];
 857         u8         mcam_reg[0x1];
 858         u8         pcam_reg[0x1];
 859         u8         local_ca_ack_delay[0x5];
 860         u8         port_module_event[0x1];
 861         u8         reserved_at_1b1[0x1];
 862         u8         ports_check[0x1];
 863         u8         reserved_at_1b3[0x1];
 864         u8         disable_link_up[0x1];
 865         u8         beacon_led[0x1];
 866         u8         port_type[0x2];
 867         u8         num_ports[0x8];
 868
 869         u8         reserved_at_1c0[0x1];
 870         u8         pps[0x1];
 871         u8         pps_modify[0x1];
 872         u8         log_max_msg[0x5];
 873         u8         reserved_at_1c8[0x4];
 874         u8         max_tc[0x4];
 875         u8         reserved_at_1d0[0x1];
 876         u8         dcbx[0x1];
 877         u8         general_notification_event[0x1];
 878         u8         reserved_at_1d3[0x2];
 879         u8         fpga[0x1];
 880         u8         rol_s[0x1];
 881         u8         rol_g[0x1];
 882         u8         reserved_at_1d8[0x1];
 883         u8         wol_s[0x1];
 884         u8         wol_g[0x1];
 885         u8         wol_a[0x1];
 886         u8         wol_b[0x1];
 887         u8         wol_m[0x1];
 888         u8         wol_u[0x1];
 889         u8         wol_p[0x1];
 890
 891         u8         stat_rate_support[0x10];
 892         u8         reserved_at_1f0[0xc];
 893         u8         cqe_version[0x4];
 894
 895         u8         compact_address_vector[0x1];
 896         u8         striding_rq[0x1];
 897         u8         reserved_at_202[0x1];
 898         u8         ipoib_enhanced_offloads[0x1];
 899         u8         ipoib_basic_offloads[0x1];
 900         u8         reserved_at_205[0x5];
 901         u8         umr_fence[0x2];
 902         u8         reserved_at_20c[0x3];
 903         u8         drain_sigerr[0x1];
 904         u8         cmdif_checksum[0x2];
 905         u8         sigerr_cqe[0x1];
 906         u8         reserved_at_213[0x1];
 907         u8         wq_signature[0x1];
 908         u8         sctr_data_cqe[0x1];
 909         u8         reserved_at_216[0x1];
 910         u8         sho[0x1];
 911         u8         tph[0x1];
 912         u8         rf[0x1];
 913         u8         dct[0x1];
 914         u8         qos[0x1];
 915         u8         eth_net_offloads[0x1];
 916         u8         roce[0x1];
 917         u8         atomic[0x1];
 918         u8         reserved_at_21f[0x1];
 919
 920         u8         cq_oi[0x1];
 921         u8         cq_resize[0x1];
 922         u8         cq_moderation[0x1];
 923         u8         reserved_at_223[0x3];
 924         u8         cq_eq_remap[0x1];
 925         u8         pg[0x1];
 926         u8         block_lb_mc[0x1];
 927         u8         reserved_at_229[0x1];
 928         u8         scqe_break_moderation[0x1];
 929         u8         cq_period_start_from_cqe[0x1];
 930         u8         cd[0x1];
 931         u8         reserved_at_22d[0x1];
 932         u8         apm[0x1];
 933         u8         vector_calc[0x1];
 934         u8         umr_ptr_rlky[0x1];
 935         u8         imaicl[0x1];
 936         u8         reserved_at_232[0x4];
 937         u8         qkv[0x1];
 938         u8         pkv[0x1];
 939         u8         set_deth_sqpn[0x1];
 940         u8         reserved_at_239[0x3];
 941         u8         xrc[0x1];
 942         u8         ud[0x1];
 943         u8         uc[0x1];
 944         u8         rc[0x1];
 945
 946         u8         uar_4k[0x1];
 947         u8         reserved_at_241[0x9];
 948         u8         uar_sz[0x6];
 949         u8         reserved_at_250[0x8];
 950         u8         log_pg_sz[0x8];
 951
 952         u8         bf[0x1];
 953         u8         driver_version[0x1];
 954         u8         pad_tx_eth_packet[0x1];
 955         u8         reserved_at_263[0x8];
 956         u8         log_bf_reg_size[0x5];
 957
 958         u8         reserved_at_270[0xb];
 959         u8         lag_master[0x1];
 960         u8         num_lag_ports[0x4];
 961
 962         u8         reserved_at_280[0x10];
 963         u8         max_wqe_sz_sq[0x10];
 964
 965         u8         reserved_at_2a0[0x10];
 966         u8         max_wqe_sz_rq[0x10];
 967
 968         u8         reserved_at_2c0[0x10];
 969         u8         max_wqe_sz_sq_dc[0x10];
 970
 971         u8         reserved_at_2e0[0x7];
 972         u8         max_qp_mcg[0x19];
 973
 974         u8         reserved_at_300[0x18];
 975         u8         log_max_mcg[0x8];
 976
 977         u8         reserved_at_320[0x3];
 978         u8         log_max_transport_domain[0x5];
 979         u8         reserved_at_328[0x3];
 980         u8         log_max_pd[0x5];
 981         u8         reserved_at_330[0xb];
 982         u8         log_max_xrcd[0x5];
 983
 984         u8         reserved_at_340[0x8];
 985         u8         log_max_flow_counter_bulk[0x8];
 986         u8         max_flow_counter[0x10];
 987
 988
 989         u8         reserved_at_360[0x3];
 990         u8         log_max_rq[0x5];
 991         u8         reserved_at_368[0x3];
 992         u8         log_max_sq[0x5];
 993         u8         reserved_at_370[0x3];
 994         u8         log_max_tir[0x5];
 995         u8         reserved_at_378[0x3];
 996         u8         log_max_tis[0x5];
 997
 998         u8         basic_cyclic_rcv_wqe[0x1];
 999         u8         reserved_at_381[0x2];
1000         u8         log_max_rmp[0x5];
1001         u8         reserved_at_388[0x3];
1002         u8         log_max_rqt[0x5];
1003         u8         reserved_at_390[0x3];
1004         u8         log_max_rqt_size[0x5];
1005         u8         reserved_at_398[0x3];
1006         u8         log_max_tis_per_sq[0x5];
1007
1008         u8         reserved_at_3a0[0x3];
1009         u8         log_max_stride_sz_rq[0x5];
1010         u8         reserved_at_3a8[0x3];
1011         u8         log_min_stride_sz_rq[0x5];
1012         u8         reserved_at_3b0[0x3];
1013         u8         log_max_stride_sz_sq[0x5];
1014         u8         reserved_at_3b8[0x3];
1015         u8         log_min_stride_sz_sq[0x5];
1016
1017         u8         reserved_at_3c0[0x1b];
1018         u8         log_max_wq_sz[0x5];
1019
1020         u8         nic_vport_change_event[0x1];
1021         u8         disable_local_lb[0x1];
1022         u8         reserved_at_3e2[0x9];
1023         u8         log_max_vlan_list[0x5];
1024         u8         reserved_at_3f0[0x3];
1025         u8         log_max_current_mc_list[0x5];
1026         u8         reserved_at_3f8[0x3];
1027         u8         log_max_current_uc_list[0x5];
1028
1029         u8         reserved_at_400[0x80];
1030
1031         u8         reserved_at_480[0x3];
1032         u8         log_max_l2_table[0x5];
1033         u8         reserved_at_488[0x8];
1034         u8         log_uar_page_sz[0x10];
1035
1036         u8         reserved_at_4a0[0x20];
1037         u8         device_frequency_mhz[0x20];
1038         u8         device_frequency_khz[0x20];
1039
1040         u8         reserved_at_500[0x20];
1041         u8         num_of_uars_per_page[0x20];
1042         u8         reserved_at_540[0x40];
1043
1044         u8         reserved_at_580[0x3f];
1045         u8         cqe_compression[0x1];
1046
1047         u8         cqe_compression_timeout[0x10];
1048         u8         cqe_compression_max_num[0x10];
1049
1050         u8         reserved_at_5e0[0x10];
1051         u8         tag_matching[0x1];
1052         u8         rndv_offload_rc[0x1];
1053         u8         rndv_offload_dc[0x1];
1054         u8         log_tag_matching_list_sz[0x5];
1055         u8         reserved_at_5f8[0x3];
1056         u8         log_max_xrq[0x5];
1057
1058         u8         reserved_at_600[0x200];
1059 };
1060
1061 enum mlx5_flow_destination_type {
1062         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1063         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1064         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1065
1066         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1067 };
1068
1069 struct mlx5_ifc_dest_format_struct_bits {
1070         u8         destination_type[0x8];
1071         u8         destination_id[0x18];
1072
1073         u8         reserved_at_20[0x20];
1074 };
1075
1076 struct mlx5_ifc_flow_counter_list_bits {
1077         u8         clear[0x1];
1078         u8         num_of_counters[0xf];
1079         u8         flow_counter_id[0x10];
1080
1081         u8         reserved_at_20[0x20];
1082 };
1083
1084 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1085         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1086         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1087         u8         reserved_at_0[0x40];
1088 };
1089
1090 struct mlx5_ifc_fte_match_param_bits {
1091         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1092
1093         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1094
1095         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1096
1097         u8         reserved_at_600[0xa00];
1098 };
1099
1100 enum {
1101         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1102         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1103         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1104         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1105         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1106 };
1107
1108 struct mlx5_ifc_rx_hash_field_select_bits {
1109         u8         l3_prot_type[0x1];
1110         u8         l4_prot_type[0x1];
1111         u8         selected_fields[0x1e];
1112 };
1113
1114 enum {
1115         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1116         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1117 };
1118
1119 enum {
1120         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1121         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1122 };
1123
1124 struct mlx5_ifc_wq_bits {
1125         u8         wq_type[0x4];
1126         u8         wq_signature[0x1];
1127         u8         end_padding_mode[0x2];
1128         u8         cd_slave[0x1];
1129         u8         reserved_at_8[0x18];
1130
1131         u8         hds_skip_first_sge[0x1];
1132         u8         log2_hds_buf_size[0x3];
1133         u8         reserved_at_24[0x7];
1134         u8         page_offset[0x5];
1135         u8         lwm[0x10];
1136
1137         u8         reserved_at_40[0x8];
1138         u8         pd[0x18];
1139
1140         u8         reserved_at_60[0x8];
1141         u8         uar_page[0x18];
1142
1143         u8         dbr_addr[0x40];
1144
1145         u8         hw_counter[0x20];
1146
1147         u8         sw_counter[0x20];
1148
1149         u8         reserved_at_100[0xc];
1150         u8         log_wq_stride[0x4];
1151         u8         reserved_at_110[0x3];
1152         u8         log_wq_pg_sz[0x5];
1153         u8         reserved_at_118[0x3];
1154         u8         log_wq_sz[0x5];
1155
1156         u8         reserved_at_120[0x15];
1157         u8         log_wqe_num_of_strides[0x3];
1158         u8         two_byte_shift_en[0x1];
1159         u8         reserved_at_139[0x4];
1160         u8         log_wqe_stride_size[0x3];
1161
1162         u8         reserved_at_140[0x4c0];
1163
1164         struct mlx5_ifc_cmd_pas_bits pas[0];
1165 };
1166
1167 struct mlx5_ifc_rq_num_bits {
1168         u8         reserved_at_0[0x8];
1169         u8         rq_num[0x18];
1170 };
1171
1172 struct mlx5_ifc_mac_address_layout_bits {
1173         u8         reserved_at_0[0x10];
1174         u8         mac_addr_47_32[0x10];
1175
1176         u8         mac_addr_31_0[0x20];
1177 };
1178
1179 struct mlx5_ifc_vlan_layout_bits {
1180         u8         reserved_at_0[0x14];
1181         u8         vlan[0x0c];
1182
1183         u8         reserved_at_20[0x20];
1184 };
1185
1186 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1187         u8         reserved_at_0[0xa0];
1188
1189         u8         min_time_between_cnps[0x20];
1190
1191         u8         reserved_at_c0[0x12];
1192         u8         cnp_dscp[0x6];
1193         u8         reserved_at_d8[0x4];
1194         u8         cnp_prio_mode[0x1];
1195         u8         cnp_802p_prio[0x3];
1196
1197         u8         reserved_at_e0[0x720];
1198 };
1199
1200 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1201         u8         reserved_at_0[0x60];
1202
1203         u8         reserved_at_60[0x4];
1204         u8         clamp_tgt_rate[0x1];
1205         u8         reserved_at_65[0x3];
1206         u8         clamp_tgt_rate_after_time_inc[0x1];
1207         u8         reserved_at_69[0x17];
1208
1209         u8         reserved_at_80[0x20];
1210
1211         u8         rpg_time_reset[0x20];
1212
1213         u8         rpg_byte_reset[0x20];
1214
1215         u8         rpg_threshold[0x20];
1216
1217         u8         rpg_max_rate[0x20];
1218
1219         u8         rpg_ai_rate[0x20];
1220
1221         u8         rpg_hai_rate[0x20];
1222
1223         u8         rpg_gd[0x20];
1224
1225         u8         rpg_min_dec_fac[0x20];
1226
1227         u8         rpg_min_rate[0x20];
1228
1229         u8         reserved_at_1c0[0xe0];
1230
1231         u8         rate_to_set_on_first_cnp[0x20];
1232
1233         u8         dce_tcp_g[0x20];
1234
1235         u8         dce_tcp_rtt[0x20];
1236
1237         u8         rate_reduce_monitor_period[0x20];
1238
1239         u8         reserved_at_320[0x20];
1240
1241         u8         initial_alpha_value[0x20];
1242
1243         u8         reserved_at_360[0x4a0];
1244 };
1245
1246 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1247         u8         reserved_at_0[0x80];
1248
1249         u8         rppp_max_rps[0x20];
1250
1251         u8         rpg_time_reset[0x20];
1252
1253         u8         rpg_byte_reset[0x20];
1254
1255         u8         rpg_threshold[0x20];
1256
1257         u8         rpg_max_rate[0x20];
1258
1259         u8         rpg_ai_rate[0x20];
1260
1261         u8         rpg_hai_rate[0x20];
1262
1263         u8         rpg_gd[0x20];
1264
1265         u8         rpg_min_dec_fac[0x20];
1266
1267         u8         rpg_min_rate[0x20];
1268
1269         u8         reserved_at_1c0[0x640];
1270 };
1271
1272 enum {
1273         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1274         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1275         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1276 };
1277
1278 struct mlx5_ifc_resize_field_select_bits {
1279         u8         resize_field_select[0x20];
1280 };
1281
1282 enum {
1283         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1284         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1285         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1286         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1287 };
1288
1289 struct mlx5_ifc_modify_field_select_bits {
1290         u8         modify_field_select[0x20];
1291 };
1292
1293 struct mlx5_ifc_field_select_r_roce_np_bits {
1294         u8         field_select_r_roce_np[0x20];
1295 };
1296
1297 struct mlx5_ifc_field_select_r_roce_rp_bits {
1298         u8         field_select_r_roce_rp[0x20];
1299 };
1300
1301 enum {
1302         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1303         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1304         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1305         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1306         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1307         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1308         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1309         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1310         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1311         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1312 };
1313
1314 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1315         u8         field_select_8021qaurp[0x20];
1316 };
1317
1318 struct mlx5_ifc_phys_layer_cntrs_bits {
1319         u8         time_since_last_clear_high[0x20];
1320
1321         u8         time_since_last_clear_low[0x20];
1322
1323         u8         symbol_errors_high[0x20];
1324
1325         u8         symbol_errors_low[0x20];
1326
1327         u8         sync_headers_errors_high[0x20];
1328
1329         u8         sync_headers_errors_low[0x20];
1330
1331         u8         edpl_bip_errors_lane0_high[0x20];
1332
1333         u8         edpl_bip_errors_lane0_low[0x20];
1334
1335         u8         edpl_bip_errors_lane1_high[0x20];
1336
1337         u8         edpl_bip_errors_lane1_low[0x20];
1338
1339         u8         edpl_bip_errors_lane2_high[0x20];
1340
1341         u8         edpl_bip_errors_lane2_low[0x20];
1342
1343         u8         edpl_bip_errors_lane3_high[0x20];
1344
1345         u8         edpl_bip_errors_lane3_low[0x20];
1346
1347         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1348
1349         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1350
1351         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1352
1353         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1354
1355         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1356
1357         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1358
1359         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1360
1361         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1362
1363         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1364
1365         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1366
1367         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1368
1369         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1370
1371         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1372
1373         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1374
1375         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1376
1377         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1378
1379         u8         rs_fec_corrected_blocks_high[0x20];
1380
1381         u8         rs_fec_corrected_blocks_low[0x20];
1382
1383         u8         rs_fec_uncorrectable_blocks_high[0x20];
1384
1385         u8         rs_fec_uncorrectable_blocks_low[0x20];
1386
1387         u8         rs_fec_no_errors_blocks_high[0x20];
1388
1389         u8         rs_fec_no_errors_blocks_low[0x20];
1390
1391         u8         rs_fec_single_error_blocks_high[0x20];
1392
1393         u8         rs_fec_single_error_blocks_low[0x20];
1394
1395         u8         rs_fec_corrected_symbols_total_high[0x20];
1396
1397         u8         rs_fec_corrected_symbols_total_low[0x20];
1398
1399         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1400
1401         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1402
1403         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1404
1405         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1406
1407         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1408
1409         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1410
1411         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1412
1413         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1414
1415         u8         link_down_events[0x20];
1416
1417         u8         successful_recovery_events[0x20];
1418
1419         u8         reserved_at_640[0x180];
1420 };
1421
1422 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1423         u8         time_since_last_clear_high[0x20];
1424
1425         u8         time_since_last_clear_low[0x20];
1426
1427         u8         phy_received_bits_high[0x20];
1428
1429         u8         phy_received_bits_low[0x20];
1430
1431         u8         phy_symbol_errors_high[0x20];
1432
1433         u8         phy_symbol_errors_low[0x20];
1434
1435         u8         phy_corrected_bits_high[0x20];
1436
1437         u8         phy_corrected_bits_low[0x20];
1438
1439         u8         phy_corrected_bits_lane0_high[0x20];
1440
1441         u8         phy_corrected_bits_lane0_low[0x20];
1442
1443         u8         phy_corrected_bits_lane1_high[0x20];
1444
1445         u8         phy_corrected_bits_lane1_low[0x20];
1446
1447         u8         phy_corrected_bits_lane2_high[0x20];
1448
1449         u8         phy_corrected_bits_lane2_low[0x20];
1450
1451         u8         phy_corrected_bits_lane3_high[0x20];
1452
1453         u8         phy_corrected_bits_lane3_low[0x20];
1454
1455         u8         reserved_at_200[0x5c0];
1456 };
1457
1458 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1459         u8         symbol_error_counter[0x10];
1460
1461         u8         link_error_recovery_counter[0x8];
1462
1463         u8         link_downed_counter[0x8];
1464
1465         u8         port_rcv_errors[0x10];
1466
1467         u8         port_rcv_remote_physical_errors[0x10];
1468
1469         u8         port_rcv_switch_relay_errors[0x10];
1470
1471         u8         port_xmit_discards[0x10];
1472
1473         u8         port_xmit_constraint_errors[0x8];
1474
1475         u8         port_rcv_constraint_errors[0x8];
1476
1477         u8         reserved_at_70[0x8];
1478
1479         u8         link_overrun_errors[0x8];
1480
1481         u8         reserved_at_80[0x10];
1482
1483         u8         vl_15_dropped[0x10];
1484
1485         u8         reserved_at_a0[0x80];
1486
1487         u8         port_xmit_wait[0x20];
1488 };
1489
1490 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1491         u8         transmit_queue_high[0x20];
1492
1493         u8         transmit_queue_low[0x20];
1494
1495         u8         reserved_at_40[0x780];
1496 };
1497
1498 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1499         u8         rx_octets_high[0x20];
1500
1501         u8         rx_octets_low[0x20];
1502
1503         u8         reserved_at_40[0xc0];
1504
1505         u8         rx_frames_high[0x20];
1506
1507         u8         rx_frames_low[0x20];
1508
1509         u8         tx_octets_high[0x20];
1510
1511         u8         tx_octets_low[0x20];
1512
1513         u8         reserved_at_180[0xc0];
1514
1515         u8         tx_frames_high[0x20];
1516
1517         u8         tx_frames_low[0x20];
1518
1519         u8         rx_pause_high[0x20];
1520
1521         u8         rx_pause_low[0x20];
1522
1523         u8         rx_pause_duration_high[0x20];
1524
1525         u8         rx_pause_duration_low[0x20];
1526
1527         u8         tx_pause_high[0x20];
1528
1529         u8         tx_pause_low[0x20];
1530
1531         u8         tx_pause_duration_high[0x20];
1532
1533         u8         tx_pause_duration_low[0x20];
1534
1535         u8         rx_pause_transition_high[0x20];
1536
1537         u8         rx_pause_transition_low[0x20];
1538
1539         u8         reserved_at_3c0[0x400];
1540 };
1541
1542 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1543         u8         port_transmit_wait_high[0x20];
1544
1545         u8         port_transmit_wait_low[0x20];
1546
1547         u8         reserved_at_40[0x780];
1548 };
1549
1550 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1551         u8         dot3stats_alignment_errors_high[0x20];
1552
1553         u8         dot3stats_alignment_errors_low[0x20];
1554
1555         u8         dot3stats_fcs_errors_high[0x20];
1556
1557         u8         dot3stats_fcs_errors_low[0x20];
1558
1559         u8         dot3stats_single_collision_frames_high[0x20];
1560
1561         u8         dot3stats_single_collision_frames_low[0x20];
1562
1563         u8         dot3stats_multiple_collision_frames_high[0x20];
1564
1565         u8         dot3stats_multiple_collision_frames_low[0x20];
1566
1567         u8         dot3stats_sqe_test_errors_high[0x20];
1568
1569         u8         dot3stats_sqe_test_errors_low[0x20];
1570
1571         u8         dot3stats_deferred_transmissions_high[0x20];
1572
1573         u8         dot3stats_deferred_transmissions_low[0x20];
1574
1575         u8         dot3stats_late_collisions_high[0x20];
1576
1577         u8         dot3stats_late_collisions_low[0x20];
1578
1579         u8         dot3stats_excessive_collisions_high[0x20];
1580
1581         u8         dot3stats_excessive_collisions_low[0x20];
1582
1583         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1584
1585         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1586
1587         u8         dot3stats_carrier_sense_errors_high[0x20];
1588
1589         u8         dot3stats_carrier_sense_errors_low[0x20];
1590
1591         u8         dot3stats_frame_too_longs_high[0x20];
1592
1593         u8         dot3stats_frame_too_longs_low[0x20];
1594
1595         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1596
1597         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1598
1599         u8         dot3stats_symbol_errors_high[0x20];
1600
1601         u8         dot3stats_symbol_errors_low[0x20];
1602
1603         u8         dot3control_in_unknown_opcodes_high[0x20];
1604
1605         u8         dot3control_in_unknown_opcodes_low[0x20];
1606
1607         u8         dot3in_pause_frames_high[0x20];
1608
1609         u8         dot3in_pause_frames_low[0x20];
1610
1611         u8         dot3out_pause_frames_high[0x20];
1612
1613         u8         dot3out_pause_frames_low[0x20];
1614
1615         u8         reserved_at_400[0x3c0];
1616 };
1617
1618 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1619         u8         ether_stats_drop_events_high[0x20];
1620
1621         u8         ether_stats_drop_events_low[0x20];
1622
1623         u8         ether_stats_octets_high[0x20];
1624
1625         u8         ether_stats_octets_low[0x20];
1626
1627         u8         ether_stats_pkts_high[0x20];
1628
1629         u8         ether_stats_pkts_low[0x20];
1630
1631         u8         ether_stats_broadcast_pkts_high[0x20];
1632
1633         u8         ether_stats_broadcast_pkts_low[0x20];
1634
1635         u8         ether_stats_multicast_pkts_high[0x20];
1636
1637         u8         ether_stats_multicast_pkts_low[0x20];
1638
1639         u8         ether_stats_crc_align_errors_high[0x20];
1640
1641         u8         ether_stats_crc_align_errors_low[0x20];
1642
1643         u8         ether_stats_undersize_pkts_high[0x20];
1644
1645         u8         ether_stats_undersize_pkts_low[0x20];
1646
1647         u8         ether_stats_oversize_pkts_high[0x20];
1648
1649         u8         ether_stats_oversize_pkts_low[0x20];
1650
1651         u8         ether_stats_fragments_high[0x20];
1652
1653         u8         ether_stats_fragments_low[0x20];
1654
1655         u8         ether_stats_jabbers_high[0x20];
1656
1657         u8         ether_stats_jabbers_low[0x20];
1658
1659         u8         ether_stats_collisions_high[0x20];
1660
1661         u8         ether_stats_collisions_low[0x20];
1662
1663         u8         ether_stats_pkts64octets_high[0x20];
1664
1665         u8         ether_stats_pkts64octets_low[0x20];
1666
1667         u8         ether_stats_pkts65to127octets_high[0x20];
1668
1669         u8         ether_stats_pkts65to127octets_low[0x20];
1670
1671         u8         ether_stats_pkts128to255octets_high[0x20];
1672
1673         u8         ether_stats_pkts128to255octets_low[0x20];
1674
1675         u8         ether_stats_pkts256to511octets_high[0x20];
1676
1677         u8         ether_stats_pkts256to511octets_low[0x20];
1678
1679         u8         ether_stats_pkts512to1023octets_high[0x20];
1680
1681         u8         ether_stats_pkts512to1023octets_low[0x20];
1682
1683         u8         ether_stats_pkts1024to1518octets_high[0x20];
1684
1685         u8         ether_stats_pkts1024to1518octets_low[0x20];
1686
1687         u8         ether_stats_pkts1519to2047octets_high[0x20];
1688
1689         u8         ether_stats_pkts1519to2047octets_low[0x20];
1690
1691         u8         ether_stats_pkts2048to4095octets_high[0x20];
1692
1693         u8         ether_stats_pkts2048to4095octets_low[0x20];
1694
1695         u8         ether_stats_pkts4096to8191octets_high[0x20];
1696
1697         u8         ether_stats_pkts4096to8191octets_low[0x20];
1698
1699         u8         ether_stats_pkts8192to10239octets_high[0x20];
1700
1701         u8         ether_stats_pkts8192to10239octets_low[0x20];
1702
1703         u8         reserved_at_540[0x280];
1704 };
1705
1706 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1707         u8         if_in_octets_high[0x20];
1708
1709         u8         if_in_octets_low[0x20];
1710
1711         u8         if_in_ucast_pkts_high[0x20];
1712
1713         u8         if_in_ucast_pkts_low[0x20];
1714
1715         u8         if_in_discards_high[0x20];
1716
1717         u8         if_in_discards_low[0x20];
1718
1719         u8         if_in_errors_high[0x20];
1720
1721         u8         if_in_errors_low[0x20];
1722
1723         u8         if_in_unknown_protos_high[0x20];
1724
1725         u8         if_in_unknown_protos_low[0x20];
1726
1727         u8         if_out_octets_high[0x20];
1728
1729         u8         if_out_octets_low[0x20];
1730
1731         u8         if_out_ucast_pkts_high[0x20];
1732
1733         u8         if_out_ucast_pkts_low[0x20];
1734
1735         u8         if_out_discards_high[0x20];
1736
1737         u8         if_out_discards_low[0x20];
1738
1739         u8         if_out_errors_high[0x20];
1740
1741         u8         if_out_errors_low[0x20];
1742
1743         u8         if_in_multicast_pkts_high[0x20];
1744
1745         u8         if_in_multicast_pkts_low[0x20];
1746
1747         u8         if_in_broadcast_pkts_high[0x20];
1748
1749         u8         if_in_broadcast_pkts_low[0x20];
1750
1751         u8         if_out_multicast_pkts_high[0x20];
1752
1753         u8         if_out_multicast_pkts_low[0x20];
1754
1755         u8         if_out_broadcast_pkts_high[0x20];
1756
1757         u8         if_out_broadcast_pkts_low[0x20];
1758
1759         u8         reserved_at_340[0x480];
1760 };
1761
1762 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1763         u8         a_frames_transmitted_ok_high[0x20];
1764
1765         u8         a_frames_transmitted_ok_low[0x20];
1766
1767         u8         a_frames_received_ok_high[0x20];
1768
1769         u8         a_frames_received_ok_low[0x20];
1770
1771         u8         a_frame_check_sequence_errors_high[0x20];
1772
1773         u8         a_frame_check_sequence_errors_low[0x20];
1774
1775         u8         a_alignment_errors_high[0x20];
1776
1777         u8         a_alignment_errors_low[0x20];
1778
1779         u8         a_octets_transmitted_ok_high[0x20];
1780
1781         u8         a_octets_transmitted_ok_low[0x20];
1782
1783         u8         a_octets_received_ok_high[0x20];
1784
1785         u8         a_octets_received_ok_low[0x20];
1786
1787         u8         a_multicast_frames_xmitted_ok_high[0x20];
1788
1789         u8         a_multicast_frames_xmitted_ok_low[0x20];
1790
1791         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1792
1793         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1794
1795         u8         a_multicast_frames_received_ok_high[0x20];
1796
1797         u8         a_multicast_frames_received_ok_low[0x20];
1798
1799         u8         a_broadcast_frames_received_ok_high[0x20];
1800
1801         u8         a_broadcast_frames_received_ok_low[0x20];
1802
1803         u8         a_in_range_length_errors_high[0x20];
1804
1805         u8         a_in_range_length_errors_low[0x20];
1806
1807         u8         a_out_of_range_length_field_high[0x20];
1808
1809         u8         a_out_of_range_length_field_low[0x20];
1810
1811         u8         a_frame_too_long_errors_high[0x20];
1812
1813         u8         a_frame_too_long_errors_low[0x20];
1814
1815         u8         a_symbol_error_during_carrier_high[0x20];
1816
1817         u8         a_symbol_error_during_carrier_low[0x20];
1818
1819         u8         a_mac_control_frames_transmitted_high[0x20];
1820
1821         u8         a_mac_control_frames_transmitted_low[0x20];
1822
1823         u8         a_mac_control_frames_received_high[0x20];
1824
1825         u8         a_mac_control_frames_received_low[0x20];
1826
1827         u8         a_unsupported_opcodes_received_high[0x20];
1828
1829         u8         a_unsupported_opcodes_received_low[0x20];
1830
1831         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1832
1833         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1834
1835         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1836
1837         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1838
1839         u8         reserved_at_4c0[0x300];
1840 };
1841
1842 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1843         u8         life_time_counter_high[0x20];
1844
1845         u8         life_time_counter_low[0x20];
1846
1847         u8         rx_errors[0x20];
1848
1849         u8         tx_errors[0x20];
1850
1851         u8         l0_to_recovery_eieos[0x20];
1852
1853         u8         l0_to_recovery_ts[0x20];
1854
1855         u8         l0_to_recovery_framing[0x20];
1856
1857         u8         l0_to_recovery_retrain[0x20];
1858
1859         u8         crc_error_dllp[0x20];
1860
1861         u8         crc_error_tlp[0x20];
1862
1863         u8         reserved_at_140[0x680];
1864 };
1865
1866 struct mlx5_ifc_cmd_inter_comp_event_bits {
1867         u8         command_completion_vector[0x20];
1868
1869         u8         reserved_at_20[0xc0];
1870 };
1871
1872 struct mlx5_ifc_stall_vl_event_bits {
1873         u8         reserved_at_0[0x18];
1874         u8         port_num[0x1];
1875         u8         reserved_at_19[0x3];
1876         u8         vl[0x4];
1877
1878         u8         reserved_at_20[0xa0];
1879 };
1880
1881 struct mlx5_ifc_db_bf_congestion_event_bits {
1882         u8         event_subtype[0x8];
1883         u8         reserved_at_8[0x8];
1884         u8         congestion_level[0x8];
1885         u8         reserved_at_18[0x8];
1886
1887         u8         reserved_at_20[0xa0];
1888 };
1889
1890 struct mlx5_ifc_gpio_event_bits {
1891         u8         reserved_at_0[0x60];
1892
1893         u8         gpio_event_hi[0x20];
1894
1895         u8         gpio_event_lo[0x20];
1896
1897         u8         reserved_at_a0[0x40];
1898 };
1899
1900 struct mlx5_ifc_port_state_change_event_bits {
1901         u8         reserved_at_0[0x40];
1902
1903         u8         port_num[0x4];
1904         u8         reserved_at_44[0x1c];
1905
1906         u8         reserved_at_60[0x80];
1907 };
1908
1909 struct mlx5_ifc_dropped_packet_logged_bits {
1910         u8         reserved_at_0[0xe0];
1911 };
1912
1913 enum {
1914         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1915         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1916 };
1917
1918 struct mlx5_ifc_cq_error_bits {
1919         u8         reserved_at_0[0x8];
1920         u8         cqn[0x18];
1921
1922         u8         reserved_at_20[0x20];
1923
1924         u8         reserved_at_40[0x18];
1925         u8         syndrome[0x8];
1926
1927         u8         reserved_at_60[0x80];
1928 };
1929
1930 struct mlx5_ifc_rdma_page_fault_event_bits {
1931         u8         bytes_committed[0x20];
1932
1933         u8         r_key[0x20];
1934
1935         u8         reserved_at_40[0x10];
1936         u8         packet_len[0x10];
1937
1938         u8         rdma_op_len[0x20];
1939
1940         u8         rdma_va[0x40];
1941
1942         u8         reserved_at_c0[0x5];
1943         u8         rdma[0x1];
1944         u8         write[0x1];
1945         u8         requestor[0x1];
1946         u8         qp_number[0x18];
1947 };
1948
1949 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1950         u8         bytes_committed[0x20];
1951
1952         u8         reserved_at_20[0x10];
1953         u8         wqe_index[0x10];
1954
1955         u8         reserved_at_40[0x10];
1956         u8         len[0x10];
1957
1958         u8         reserved_at_60[0x60];
1959
1960         u8         reserved_at_c0[0x5];
1961         u8         rdma[0x1];
1962         u8         write_read[0x1];
1963         u8         requestor[0x1];
1964         u8         qpn[0x18];
1965 };
1966
1967 struct mlx5_ifc_qp_events_bits {
1968         u8         reserved_at_0[0xa0];
1969
1970         u8         type[0x8];
1971         u8         reserved_at_a8[0x18];
1972
1973         u8         reserved_at_c0[0x8];
1974         u8         qpn_rqn_sqn[0x18];
1975 };
1976
1977 struct mlx5_ifc_dct_events_bits {
1978         u8         reserved_at_0[0xc0];
1979
1980         u8         reserved_at_c0[0x8];
1981         u8         dct_number[0x18];
1982 };
1983
1984 struct mlx5_ifc_comp_event_bits {
1985         u8         reserved_at_0[0xc0];
1986
1987         u8         reserved_at_c0[0x8];
1988         u8         cq_number[0x18];
1989 };
1990
1991 enum {
1992         MLX5_QPC_STATE_RST        = 0x0,
1993         MLX5_QPC_STATE_INIT       = 0x1,
1994         MLX5_QPC_STATE_RTR        = 0x2,
1995         MLX5_QPC_STATE_RTS        = 0x3,
1996         MLX5_QPC_STATE_SQER       = 0x4,
1997         MLX5_QPC_STATE_ERR        = 0x6,
1998         MLX5_QPC_STATE_SQD        = 0x7,
1999         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2000 };
2001
2002 enum {
2003         MLX5_QPC_ST_RC            = 0x0,
2004         MLX5_QPC_ST_UC            = 0x1,
2005         MLX5_QPC_ST_UD            = 0x2,
2006         MLX5_QPC_ST_XRC           = 0x3,
2007         MLX5_QPC_ST_DCI           = 0x5,
2008         MLX5_QPC_ST_QP0           = 0x7,
2009         MLX5_QPC_ST_QP1           = 0x8,
2010         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2011         MLX5_QPC_ST_REG_UMR       = 0xc,
2012 };
2013
2014 enum {
2015         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2016         MLX5_QPC_PM_STATE_REARM     = 0x1,
2017         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2018         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2019 };
2020
2021 enum {
2022         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2023         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2024 };
2025
2026 enum {
2027         MLX5_QPC_MTU_256_BYTES        = 0x1,
2028         MLX5_QPC_MTU_512_BYTES        = 0x2,
2029         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2030         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2031         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2032         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2033 };
2034
2035 enum {
2036         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2037         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2038         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2039         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2040         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2041         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2042         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2043         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2044 };
2045
2046 enum {
2047         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2048         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2049         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2050 };
2051
2052 enum {
2053         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2054         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2055         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2056 };
2057
2058 struct mlx5_ifc_qpc_bits {
2059         u8         state[0x4];
2060         u8         lag_tx_port_affinity[0x4];
2061         u8         st[0x8];
2062         u8         reserved_at_10[0x3];
2063         u8         pm_state[0x2];
2064         u8         reserved_at_15[0x7];
2065         u8         end_padding_mode[0x2];
2066         u8         reserved_at_1e[0x2];
2067
2068         u8         wq_signature[0x1];
2069         u8         block_lb_mc[0x1];
2070         u8         atomic_like_write_en[0x1];
2071         u8         latency_sensitive[0x1];
2072         u8         reserved_at_24[0x1];
2073         u8         drain_sigerr[0x1];
2074         u8         reserved_at_26[0x2];
2075         u8         pd[0x18];
2076
2077         u8         mtu[0x3];
2078         u8         log_msg_max[0x5];
2079         u8         reserved_at_48[0x1];
2080         u8         log_rq_size[0x4];
2081         u8         log_rq_stride[0x3];
2082         u8         no_sq[0x1];
2083         u8         log_sq_size[0x4];
2084         u8         reserved_at_55[0x6];
2085         u8         rlky[0x1];
2086         u8         ulp_stateless_offload_mode[0x4];
2087
2088         u8         counter_set_id[0x8];
2089         u8         uar_page[0x18];
2090
2091         u8         reserved_at_80[0x8];
2092         u8         user_index[0x18];
2093
2094         u8         reserved_at_a0[0x3];
2095         u8         log_page_size[0x5];
2096         u8         remote_qpn[0x18];
2097
2098         struct mlx5_ifc_ads_bits primary_address_path;
2099
2100         struct mlx5_ifc_ads_bits secondary_address_path;
2101
2102         u8         log_ack_req_freq[0x4];
2103         u8         reserved_at_384[0x4];
2104         u8         log_sra_max[0x3];
2105         u8         reserved_at_38b[0x2];
2106         u8         retry_count[0x3];
2107         u8         rnr_retry[0x3];
2108         u8         reserved_at_393[0x1];
2109         u8         fre[0x1];
2110         u8         cur_rnr_retry[0x3];
2111         u8         cur_retry_count[0x3];
2112         u8         reserved_at_39b[0x5];
2113
2114         u8         reserved_at_3a0[0x20];
2115
2116         u8         reserved_at_3c0[0x8];
2117         u8         next_send_psn[0x18];
2118
2119         u8         reserved_at_3e0[0x8];
2120         u8         cqn_snd[0x18];
2121
2122         u8         reserved_at_400[0x8];
2123         u8         deth_sqpn[0x18];
2124
2125         u8         reserved_at_420[0x20];
2126
2127         u8         reserved_at_440[0x8];
2128         u8         last_acked_psn[0x18];
2129
2130         u8         reserved_at_460[0x8];
2131         u8         ssn[0x18];
2132
2133         u8         reserved_at_480[0x8];
2134         u8         log_rra_max[0x3];
2135         u8         reserved_at_48b[0x1];
2136         u8         atomic_mode[0x4];
2137         u8         rre[0x1];
2138         u8         rwe[0x1];
2139         u8         rae[0x1];
2140         u8         reserved_at_493[0x1];
2141         u8         page_offset[0x6];
2142         u8         reserved_at_49a[0x3];
2143         u8         cd_slave_receive[0x1];
2144         u8         cd_slave_send[0x1];
2145         u8         cd_master[0x1];
2146
2147         u8         reserved_at_4a0[0x3];
2148         u8         min_rnr_nak[0x5];
2149         u8         next_rcv_psn[0x18];
2150
2151         u8         reserved_at_4c0[0x8];
2152         u8         xrcd[0x18];
2153
2154         u8         reserved_at_4e0[0x8];
2155         u8         cqn_rcv[0x18];
2156
2157         u8         dbr_addr[0x40];
2158
2159         u8         q_key[0x20];
2160
2161         u8         reserved_at_560[0x5];
2162         u8         rq_type[0x3];
2163         u8         srqn_rmpn_xrqn[0x18];
2164
2165         u8         reserved_at_580[0x8];
2166         u8         rmsn[0x18];
2167
2168         u8         hw_sq_wqebb_counter[0x10];
2169         u8         sw_sq_wqebb_counter[0x10];
2170
2171         u8         hw_rq_counter[0x20];
2172
2173         u8         sw_rq_counter[0x20];
2174
2175         u8         reserved_at_600[0x20];
2176
2177         u8         reserved_at_620[0xf];
2178         u8         cgs[0x1];
2179         u8         cs_req[0x8];
2180         u8         cs_res[0x8];
2181
2182         u8         dc_access_key[0x40];
2183
2184         u8         reserved_at_680[0xc0];
2185 };
2186
2187 struct mlx5_ifc_roce_addr_layout_bits {
2188         u8         source_l3_address[16][0x8];
2189
2190         u8         reserved_at_80[0x3];
2191         u8         vlan_valid[0x1];
2192         u8         vlan_id[0xc];
2193         u8         source_mac_47_32[0x10];
2194
2195         u8         source_mac_31_0[0x20];
2196
2197         u8         reserved_at_c0[0x14];
2198         u8         roce_l3_type[0x4];
2199         u8         roce_version[0x8];
2200
2201         u8         reserved_at_e0[0x20];
2202 };
2203
2204 union mlx5_ifc_hca_cap_union_bits {
2205         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2206         struct mlx5_ifc_odp_cap_bits odp_cap;
2207         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2208         struct mlx5_ifc_roce_cap_bits roce_cap;
2209         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2210         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2211         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2212         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2213         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2214         struct mlx5_ifc_qos_cap_bits qos_cap;
2215         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2216         u8         reserved_at_0[0x8000];
2217 };
2218
2219 enum {
2220         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2221         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2222         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2223         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2224         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2225         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2226         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2227 };
2228
2229 struct mlx5_ifc_flow_context_bits {
2230         u8         reserved_at_0[0x20];
2231
2232         u8         group_id[0x20];
2233
2234         u8         reserved_at_40[0x8];
2235         u8         flow_tag[0x18];
2236
2237         u8         reserved_at_60[0x10];
2238         u8         action[0x10];
2239
2240         u8         reserved_at_80[0x8];
2241         u8         destination_list_size[0x18];
2242
2243         u8         reserved_at_a0[0x8];
2244         u8         flow_counter_list_size[0x18];
2245
2246         u8         encap_id[0x20];
2247
2248         u8         modify_header_id[0x20];
2249
2250         u8         reserved_at_100[0x100];
2251
2252         struct mlx5_ifc_fte_match_param_bits match_value;
2253
2254         u8         reserved_at_1200[0x600];
2255
2256         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2257 };
2258
2259 enum {
2260         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2261         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2262 };
2263
2264 struct mlx5_ifc_xrc_srqc_bits {
2265         u8         state[0x4];
2266         u8         log_xrc_srq_size[0x4];
2267         u8         reserved_at_8[0x18];
2268
2269         u8         wq_signature[0x1];
2270         u8         cont_srq[0x1];
2271         u8         reserved_at_22[0x1];
2272         u8         rlky[0x1];
2273         u8         basic_cyclic_rcv_wqe[0x1];
2274         u8         log_rq_stride[0x3];
2275         u8         xrcd[0x18];
2276
2277         u8         page_offset[0x6];
2278         u8         reserved_at_46[0x2];
2279         u8         cqn[0x18];
2280
2281         u8         reserved_at_60[0x20];
2282
2283         u8         user_index_equal_xrc_srqn[0x1];
2284         u8         reserved_at_81[0x1];
2285         u8         log_page_size[0x6];
2286         u8         user_index[0x18];
2287
2288         u8         reserved_at_a0[0x20];
2289
2290         u8         reserved_at_c0[0x8];
2291         u8         pd[0x18];
2292
2293         u8         lwm[0x10];
2294         u8         wqe_cnt[0x10];
2295
2296         u8         reserved_at_100[0x40];
2297
2298         u8         db_record_addr_h[0x20];
2299
2300         u8         db_record_addr_l[0x1e];
2301         u8         reserved_at_17e[0x2];
2302
2303         u8         reserved_at_180[0x80];
2304 };
2305
2306 struct mlx5_ifc_traffic_counter_bits {
2307         u8         packets[0x40];
2308
2309         u8         octets[0x40];
2310 };
2311
2312 struct mlx5_ifc_tisc_bits {
2313         u8         strict_lag_tx_port_affinity[0x1];
2314         u8         reserved_at_1[0x3];
2315         u8         lag_tx_port_affinity[0x04];
2316
2317         u8         reserved_at_8[0x4];
2318         u8         prio[0x4];
2319         u8         reserved_at_10[0x10];
2320
2321         u8         reserved_at_20[0x100];
2322
2323         u8         reserved_at_120[0x8];
2324         u8         transport_domain[0x18];
2325
2326         u8         reserved_at_140[0x8];
2327         u8         underlay_qpn[0x18];
2328         u8         reserved_at_160[0x3a0];
2329 };
2330
2331 enum {
2332         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2333         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2334 };
2335
2336 enum {
2337         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2338         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2339 };
2340
2341 enum {
2342         MLX5_RX_HASH_FN_NONE           = 0x0,
2343         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2344         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2345 };
2346
2347 enum {
2348         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2349         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2350 };
2351
2352 struct mlx5_ifc_tirc_bits {
2353         u8         reserved_at_0[0x20];
2354
2355         u8         disp_type[0x4];
2356         u8         reserved_at_24[0x1c];
2357
2358         u8         reserved_at_40[0x40];
2359
2360         u8         reserved_at_80[0x4];
2361         u8         lro_timeout_period_usecs[0x10];
2362         u8         lro_enable_mask[0x4];
2363         u8         lro_max_ip_payload_size[0x8];
2364
2365         u8         reserved_at_a0[0x40];
2366
2367         u8         reserved_at_e0[0x8];
2368         u8         inline_rqn[0x18];
2369
2370         u8         rx_hash_symmetric[0x1];
2371         u8         reserved_at_101[0x1];
2372         u8         tunneled_offload_en[0x1];
2373         u8         reserved_at_103[0x5];
2374         u8         indirect_table[0x18];
2375
2376         u8         rx_hash_fn[0x4];
2377         u8         reserved_at_124[0x2];
2378         u8         self_lb_block[0x2];
2379         u8         transport_domain[0x18];
2380
2381         u8         rx_hash_toeplitz_key[10][0x20];
2382
2383         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2384
2385         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2386
2387         u8         reserved_at_2c0[0x4c0];
2388 };
2389
2390 enum {
2391         MLX5_SRQC_STATE_GOOD   = 0x0,
2392         MLX5_SRQC_STATE_ERROR  = 0x1,
2393 };
2394
2395 struct mlx5_ifc_srqc_bits {
2396         u8         state[0x4];
2397         u8         log_srq_size[0x4];
2398         u8         reserved_at_8[0x18];
2399
2400         u8         wq_signature[0x1];
2401         u8         cont_srq[0x1];
2402         u8         reserved_at_22[0x1];
2403         u8         rlky[0x1];
2404         u8         reserved_at_24[0x1];
2405         u8         log_rq_stride[0x3];
2406         u8         xrcd[0x18];
2407
2408         u8         page_offset[0x6];
2409         u8         reserved_at_46[0x2];
2410         u8         cqn[0x18];
2411
2412         u8         reserved_at_60[0x20];
2413
2414         u8         reserved_at_80[0x2];
2415         u8         log_page_size[0x6];
2416         u8         reserved_at_88[0x18];
2417
2418         u8         reserved_at_a0[0x20];
2419
2420         u8         reserved_at_c0[0x8];
2421         u8         pd[0x18];
2422
2423         u8         lwm[0x10];
2424         u8         wqe_cnt[0x10];
2425
2426         u8         reserved_at_100[0x40];
2427
2428         u8         dbr_addr[0x40];
2429
2430         u8         reserved_at_180[0x80];
2431 };
2432
2433 enum {
2434         MLX5_SQC_STATE_RST  = 0x0,
2435         MLX5_SQC_STATE_RDY  = 0x1,
2436         MLX5_SQC_STATE_ERR  = 0x3,
2437 };
2438
2439 struct mlx5_ifc_sqc_bits {
2440         u8         rlky[0x1];
2441         u8         cd_master[0x1];
2442         u8         fre[0x1];
2443         u8         flush_in_error_en[0x1];
2444         u8         reserved_at_4[0x1];
2445         u8         min_wqe_inline_mode[0x3];
2446         u8         state[0x4];
2447         u8         reg_umr[0x1];
2448         u8         allow_swp[0x1];
2449         u8         reserved_at_e[0x12];
2450
2451         u8         reserved_at_20[0x8];
2452         u8         user_index[0x18];
2453
2454         u8         reserved_at_40[0x8];
2455         u8         cqn[0x18];
2456
2457         u8         reserved_at_60[0x90];
2458
2459         u8         packet_pacing_rate_limit_index[0x10];
2460         u8         tis_lst_sz[0x10];
2461         u8         reserved_at_110[0x10];
2462
2463         u8         reserved_at_120[0x40];
2464
2465         u8         reserved_at_160[0x8];
2466         u8         tis_num_0[0x18];
2467
2468         struct mlx5_ifc_wq_bits wq;
2469 };
2470
2471 enum {
2472         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2473         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2474         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2475         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2476 };
2477
2478 struct mlx5_ifc_scheduling_context_bits {
2479         u8         element_type[0x8];
2480         u8         reserved_at_8[0x18];
2481
2482         u8         element_attributes[0x20];
2483
2484         u8         parent_element_id[0x20];
2485
2486         u8         reserved_at_60[0x40];
2487
2488         u8         bw_share[0x20];
2489
2490         u8         max_average_bw[0x20];
2491
2492         u8         reserved_at_e0[0x120];
2493 };
2494
2495 struct mlx5_ifc_rqtc_bits {
2496         u8         reserved_at_0[0xa0];
2497
2498         u8         reserved_at_a0[0x10];
2499         u8         rqt_max_size[0x10];
2500
2501         u8         reserved_at_c0[0x10];
2502         u8         rqt_actual_size[0x10];
2503
2504         u8         reserved_at_e0[0x6a0];
2505
2506         struct mlx5_ifc_rq_num_bits rq_num[0];
2507 };
2508
2509 enum {
2510         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2511         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2512 };
2513
2514 enum {
2515         MLX5_RQC_STATE_RST  = 0x0,
2516         MLX5_RQC_STATE_RDY  = 0x1,
2517         MLX5_RQC_STATE_ERR  = 0x3,
2518 };
2519
2520 struct mlx5_ifc_rqc_bits {
2521         u8         rlky[0x1];
2522         u8         delay_drop_en[0x1];
2523         u8         scatter_fcs[0x1];
2524         u8         vsd[0x1];
2525         u8         mem_rq_type[0x4];
2526         u8         state[0x4];
2527         u8         reserved_at_c[0x1];
2528         u8         flush_in_error_en[0x1];
2529         u8         reserved_at_e[0x12];
2530
2531         u8         reserved_at_20[0x8];
2532         u8         user_index[0x18];
2533
2534         u8         reserved_at_40[0x8];
2535         u8         cqn[0x18];
2536
2537         u8         counter_set_id[0x8];
2538         u8         reserved_at_68[0x18];
2539
2540         u8         reserved_at_80[0x8];
2541         u8         rmpn[0x18];
2542
2543         u8         reserved_at_a0[0xe0];
2544
2545         struct mlx5_ifc_wq_bits wq;
2546 };
2547
2548 enum {
2549         MLX5_RMPC_STATE_RDY  = 0x1,
2550         MLX5_RMPC_STATE_ERR  = 0x3,
2551 };
2552
2553 struct mlx5_ifc_rmpc_bits {
2554         u8         reserved_at_0[0x8];
2555         u8         state[0x4];
2556         u8         reserved_at_c[0x14];
2557
2558         u8         basic_cyclic_rcv_wqe[0x1];
2559         u8         reserved_at_21[0x1f];
2560
2561         u8         reserved_at_40[0x140];
2562
2563         struct mlx5_ifc_wq_bits wq;
2564 };
2565
2566 struct mlx5_ifc_nic_vport_context_bits {
2567         u8         reserved_at_0[0x5];
2568         u8         min_wqe_inline_mode[0x3];
2569         u8         reserved_at_8[0x15];
2570         u8         disable_mc_local_lb[0x1];
2571         u8         disable_uc_local_lb[0x1];
2572         u8         roce_en[0x1];
2573
2574         u8         arm_change_event[0x1];
2575         u8         reserved_at_21[0x1a];
2576         u8         event_on_mtu[0x1];
2577         u8         event_on_promisc_change[0x1];
2578         u8         event_on_vlan_change[0x1];
2579         u8         event_on_mc_address_change[0x1];
2580         u8         event_on_uc_address_change[0x1];
2581
2582         u8         reserved_at_40[0xf0];
2583
2584         u8         mtu[0x10];
2585
2586         u8         system_image_guid[0x40];
2587         u8         port_guid[0x40];
2588         u8         node_guid[0x40];
2589
2590         u8         reserved_at_200[0x140];
2591         u8         qkey_violation_counter[0x10];
2592         u8         reserved_at_350[0x430];
2593
2594         u8         promisc_uc[0x1];
2595         u8         promisc_mc[0x1];
2596         u8         promisc_all[0x1];
2597         u8         reserved_at_783[0x2];
2598         u8         allowed_list_type[0x3];
2599         u8         reserved_at_788[0xc];
2600         u8         allowed_list_size[0xc];
2601
2602         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2603
2604         u8         reserved_at_7e0[0x20];
2605
2606         u8         current_uc_mac_address[0][0x40];
2607 };
2608
2609 enum {
2610         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2611         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2612         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2613         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2614 };
2615
2616 struct mlx5_ifc_mkc_bits {
2617         u8         reserved_at_0[0x1];
2618         u8         free[0x1];
2619         u8         reserved_at_2[0xd];
2620         u8         small_fence_on_rdma_read_response[0x1];
2621         u8         umr_en[0x1];
2622         u8         a[0x1];
2623         u8         rw[0x1];
2624         u8         rr[0x1];
2625         u8         lw[0x1];
2626         u8         lr[0x1];
2627         u8         access_mode[0x2];
2628         u8         reserved_at_18[0x8];
2629
2630         u8         qpn[0x18];
2631         u8         mkey_7_0[0x8];
2632
2633         u8         reserved_at_40[0x20];
2634
2635         u8         length64[0x1];
2636         u8         bsf_en[0x1];
2637         u8         sync_umr[0x1];
2638         u8         reserved_at_63[0x2];
2639         u8         expected_sigerr_count[0x1];
2640         u8         reserved_at_66[0x1];
2641         u8         en_rinval[0x1];
2642         u8         pd[0x18];
2643
2644         u8         start_addr[0x40];
2645
2646         u8         len[0x40];
2647
2648         u8         bsf_octword_size[0x20];
2649
2650         u8         reserved_at_120[0x80];
2651
2652         u8         translations_octword_size[0x20];
2653
2654         u8         reserved_at_1c0[0x1b];
2655         u8         log_page_size[0x5];
2656
2657         u8         reserved_at_1e0[0x20];
2658 };
2659
2660 struct mlx5_ifc_pkey_bits {
2661         u8         reserved_at_0[0x10];
2662         u8         pkey[0x10];
2663 };
2664
2665 struct mlx5_ifc_array128_auto_bits {
2666         u8         array128_auto[16][0x8];
2667 };
2668
2669 struct mlx5_ifc_hca_vport_context_bits {
2670         u8         field_select[0x20];
2671
2672         u8         reserved_at_20[0xe0];
2673
2674         u8         sm_virt_aware[0x1];
2675         u8         has_smi[0x1];
2676         u8         has_raw[0x1];
2677         u8         grh_required[0x1];
2678         u8         reserved_at_104[0xc];
2679         u8         port_physical_state[0x4];
2680         u8         vport_state_policy[0x4];
2681         u8         port_state[0x4];
2682         u8         vport_state[0x4];
2683
2684         u8         reserved_at_120[0x20];
2685
2686         u8         system_image_guid[0x40];
2687
2688         u8         port_guid[0x40];
2689
2690         u8         node_guid[0x40];
2691
2692         u8         cap_mask1[0x20];
2693
2694         u8         cap_mask1_field_select[0x20];
2695
2696         u8         cap_mask2[0x20];
2697
2698         u8         cap_mask2_field_select[0x20];
2699
2700         u8         reserved_at_280[0x80];
2701
2702         u8         lid[0x10];
2703         u8         reserved_at_310[0x4];
2704         u8         init_type_reply[0x4];
2705         u8         lmc[0x3];
2706         u8         subnet_timeout[0x5];
2707
2708         u8         sm_lid[0x10];
2709         u8         sm_sl[0x4];
2710         u8         reserved_at_334[0xc];
2711
2712         u8         qkey_violation_counter[0x10];
2713         u8         pkey_violation_counter[0x10];
2714
2715         u8         reserved_at_360[0xca0];
2716 };
2717
2718 struct mlx5_ifc_esw_vport_context_bits {
2719         u8         reserved_at_0[0x3];
2720         u8         vport_svlan_strip[0x1];
2721         u8         vport_cvlan_strip[0x1];
2722         u8         vport_svlan_insert[0x1];
2723         u8         vport_cvlan_insert[0x2];
2724         u8         reserved_at_8[0x18];
2725
2726         u8         reserved_at_20[0x20];
2727
2728         u8         svlan_cfi[0x1];
2729         u8         svlan_pcp[0x3];
2730         u8         svlan_id[0xc];
2731         u8         cvlan_cfi[0x1];
2732         u8         cvlan_pcp[0x3];
2733         u8         cvlan_id[0xc];
2734
2735         u8         reserved_at_60[0x7a0];
2736 };
2737
2738 enum {
2739         MLX5_EQC_STATUS_OK                = 0x0,
2740         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2741 };
2742
2743 enum {
2744         MLX5_EQC_ST_ARMED  = 0x9,
2745         MLX5_EQC_ST_FIRED  = 0xa,
2746 };
2747
2748 struct mlx5_ifc_eqc_bits {
2749         u8         status[0x4];
2750         u8         reserved_at_4[0x9];
2751         u8         ec[0x1];
2752         u8         oi[0x1];
2753         u8         reserved_at_f[0x5];
2754         u8         st[0x4];
2755         u8         reserved_at_18[0x8];
2756
2757         u8         reserved_at_20[0x20];
2758
2759         u8         reserved_at_40[0x14];
2760         u8         page_offset[0x6];
2761         u8         reserved_at_5a[0x6];
2762
2763         u8         reserved_at_60[0x3];
2764         u8         log_eq_size[0x5];
2765         u8         uar_page[0x18];
2766
2767         u8         reserved_at_80[0x20];
2768
2769         u8         reserved_at_a0[0x18];
2770         u8         intr[0x8];
2771
2772         u8         reserved_at_c0[0x3];
2773         u8         log_page_size[0x5];
2774         u8         reserved_at_c8[0x18];
2775
2776         u8         reserved_at_e0[0x60];
2777
2778         u8         reserved_at_140[0x8];
2779         u8         consumer_counter[0x18];
2780
2781         u8         reserved_at_160[0x8];
2782         u8         producer_counter[0x18];
2783
2784         u8         reserved_at_180[0x80];
2785 };
2786
2787 enum {
2788         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2789         MLX5_DCTC_STATE_DRAINING  = 0x1,
2790         MLX5_DCTC_STATE_DRAINED   = 0x2,
2791 };
2792
2793 enum {
2794         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2795         MLX5_DCTC_CS_RES_NA         = 0x1,
2796         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2797 };
2798
2799 enum {
2800         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2801         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2802         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2803         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2804         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2805 };
2806
2807 struct mlx5_ifc_dctc_bits {
2808         u8         reserved_at_0[0x4];
2809         u8         state[0x4];
2810         u8         reserved_at_8[0x18];
2811
2812         u8         reserved_at_20[0x8];
2813         u8         user_index[0x18];
2814
2815         u8         reserved_at_40[0x8];
2816         u8         cqn[0x18];
2817
2818         u8         counter_set_id[0x8];
2819         u8         atomic_mode[0x4];
2820         u8         rre[0x1];
2821         u8         rwe[0x1];
2822         u8         rae[0x1];
2823         u8         atomic_like_write_en[0x1];
2824         u8         latency_sensitive[0x1];
2825         u8         rlky[0x1];
2826         u8         free_ar[0x1];
2827         u8         reserved_at_73[0xd];
2828
2829         u8         reserved_at_80[0x8];
2830         u8         cs_res[0x8];
2831         u8         reserved_at_90[0x3];
2832         u8         min_rnr_nak[0x5];
2833         u8         reserved_at_98[0x8];
2834
2835         u8         reserved_at_a0[0x8];
2836         u8         srqn_xrqn[0x18];
2837
2838         u8         reserved_at_c0[0x8];
2839         u8         pd[0x18];
2840
2841         u8         tclass[0x8];
2842         u8         reserved_at_e8[0x4];
2843         u8         flow_label[0x14];
2844
2845         u8         dc_access_key[0x40];
2846
2847         u8         reserved_at_140[0x5];
2848         u8         mtu[0x3];
2849         u8         port[0x8];
2850         u8         pkey_index[0x10];
2851
2852         u8         reserved_at_160[0x8];
2853         u8         my_addr_index[0x8];
2854         u8         reserved_at_170[0x8];
2855         u8         hop_limit[0x8];
2856
2857         u8         dc_access_key_violation_count[0x20];
2858
2859         u8         reserved_at_1a0[0x14];
2860         u8         dei_cfi[0x1];
2861         u8         eth_prio[0x3];
2862         u8         ecn[0x2];
2863         u8         dscp[0x6];
2864
2865         u8         reserved_at_1c0[0x40];
2866 };
2867
2868 enum {
2869         MLX5_CQC_STATUS_OK             = 0x0,
2870         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2871         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2872 };
2873
2874 enum {
2875         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2876         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2877 };
2878
2879 enum {
2880         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2881         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2882         MLX5_CQC_ST_FIRED                                 = 0xa,
2883 };
2884
2885 enum {
2886         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2887         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2888         MLX5_CQ_PERIOD_NUM_MODES
2889 };
2890
2891 struct mlx5_ifc_cqc_bits {
2892         u8         status[0x4];
2893         u8         reserved_at_4[0x4];
2894         u8         cqe_sz[0x3];
2895         u8         cc[0x1];
2896         u8         reserved_at_c[0x1];
2897         u8         scqe_break_moderation_en[0x1];
2898         u8         oi[0x1];
2899         u8         cq_period_mode[0x2];
2900         u8         cqe_comp_en[0x1];
2901         u8         mini_cqe_res_format[0x2];
2902         u8         st[0x4];
2903         u8         reserved_at_18[0x8];
2904
2905         u8         reserved_at_20[0x20];
2906
2907         u8         reserved_at_40[0x14];
2908         u8         page_offset[0x6];
2909         u8         reserved_at_5a[0x6];
2910
2911         u8         reserved_at_60[0x3];
2912         u8         log_cq_size[0x5];
2913         u8         uar_page[0x18];
2914
2915         u8         reserved_at_80[0x4];
2916         u8         cq_period[0xc];
2917         u8         cq_max_count[0x10];
2918
2919         u8         reserved_at_a0[0x18];
2920         u8         c_eqn[0x8];
2921
2922         u8         reserved_at_c0[0x3];
2923         u8         log_page_size[0x5];
2924         u8         reserved_at_c8[0x18];
2925
2926         u8         reserved_at_e0[0x20];
2927
2928         u8         reserved_at_100[0x8];
2929         u8         last_notified_index[0x18];
2930
2931         u8         reserved_at_120[0x8];
2932         u8         last_solicit_index[0x18];
2933
2934         u8         reserved_at_140[0x8];
2935         u8         consumer_counter[0x18];
2936
2937         u8         reserved_at_160[0x8];
2938         u8         producer_counter[0x18];
2939
2940         u8         reserved_at_180[0x40];
2941
2942         u8         dbr_addr[0x40];
2943 };
2944
2945 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2946         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2947         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2948         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2949         u8         reserved_at_0[0x800];
2950 };
2951
2952 struct mlx5_ifc_query_adapter_param_block_bits {
2953         u8         reserved_at_0[0xc0];
2954
2955         u8         reserved_at_c0[0x8];
2956         u8         ieee_vendor_id[0x18];
2957
2958         u8         reserved_at_e0[0x10];
2959         u8         vsd_vendor_id[0x10];
2960
2961         u8         vsd[208][0x8];
2962
2963         u8         vsd_contd_psid[16][0x8];
2964 };
2965
2966 enum {
2967         MLX5_XRQC_STATE_GOOD   = 0x0,
2968         MLX5_XRQC_STATE_ERROR  = 0x1,
2969 };
2970
2971 enum {
2972         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2973         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2974 };
2975
2976 enum {
2977         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2978 };
2979
2980 struct mlx5_ifc_tag_matching_topology_context_bits {
2981         u8         log_matching_list_sz[0x4];
2982         u8         reserved_at_4[0xc];
2983         u8         append_next_index[0x10];
2984
2985         u8         sw_phase_cnt[0x10];
2986         u8         hw_phase_cnt[0x10];
2987
2988         u8         reserved_at_40[0x40];
2989 };
2990
2991 struct mlx5_ifc_xrqc_bits {
2992         u8         state[0x4];
2993         u8         rlkey[0x1];
2994         u8         reserved_at_5[0xf];
2995         u8         topology[0x4];
2996         u8         reserved_at_18[0x4];
2997         u8         offload[0x4];
2998
2999         u8         reserved_at_20[0x8];
3000         u8         user_index[0x18];
3001
3002         u8         reserved_at_40[0x8];
3003         u8         cqn[0x18];
3004
3005         u8         reserved_at_60[0xa0];
3006
3007         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3008
3009         u8         reserved_at_180[0x880];
3010
3011         struct mlx5_ifc_wq_bits wq;
3012 };
3013
3014 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3015         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3016         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3017         u8         reserved_at_0[0x20];
3018 };
3019
3020 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3021         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3022         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3023         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3024         u8         reserved_at_0[0x20];
3025 };
3026
3027 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3028         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3029         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3030         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3031         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3032         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3033         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3034         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3035         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3036         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3037         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3038         u8         reserved_at_0[0x7c0];
3039 };
3040
3041 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3042         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3043         u8         reserved_at_0[0x7c0];
3044 };
3045
3046 union mlx5_ifc_event_auto_bits {
3047         struct mlx5_ifc_comp_event_bits comp_event;
3048         struct mlx5_ifc_dct_events_bits dct_events;
3049         struct mlx5_ifc_qp_events_bits qp_events;
3050         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3051         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3052         struct mlx5_ifc_cq_error_bits cq_error;
3053         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3054         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3055         struct mlx5_ifc_gpio_event_bits gpio_event;
3056         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3057         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3058         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3059         u8         reserved_at_0[0xe0];
3060 };
3061
3062 struct mlx5_ifc_health_buffer_bits {
3063         u8         reserved_at_0[0x100];
3064
3065         u8         assert_existptr[0x20];
3066
3067         u8         assert_callra[0x20];
3068
3069         u8         reserved_at_140[0x40];
3070
3071         u8         fw_version[0x20];
3072
3073         u8         hw_id[0x20];
3074
3075         u8         reserved_at_1c0[0x20];
3076
3077         u8         irisc_index[0x8];
3078         u8         synd[0x8];
3079         u8         ext_synd[0x10];
3080 };
3081
3082 struct mlx5_ifc_register_loopback_control_bits {
3083         u8         no_lb[0x1];
3084         u8         reserved_at_1[0x7];
3085         u8         port[0x8];
3086         u8         reserved_at_10[0x10];
3087
3088         u8         reserved_at_20[0x60];
3089 };
3090
3091 struct mlx5_ifc_vport_tc_element_bits {
3092         u8         traffic_class[0x4];
3093         u8         reserved_at_4[0xc];
3094         u8         vport_number[0x10];
3095 };
3096
3097 struct mlx5_ifc_vport_element_bits {
3098         u8         reserved_at_0[0x10];
3099         u8         vport_number[0x10];
3100 };
3101
3102 enum {
3103         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3104         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3105         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3106 };
3107
3108 struct mlx5_ifc_tsar_element_bits {
3109         u8         reserved_at_0[0x8];
3110         u8         tsar_type[0x8];
3111         u8         reserved_at_10[0x10];
3112 };
3113
3114 enum {
3115         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3116         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3117 };
3118
3119 struct mlx5_ifc_teardown_hca_out_bits {
3120         u8         status[0x8];
3121         u8         reserved_at_8[0x18];
3122
3123         u8         syndrome[0x20];
3124
3125         u8         reserved_at_40[0x3f];
3126
3127         u8         force_state[0x1];
3128 };
3129
3130 enum {
3131         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3132         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3133 };
3134
3135 struct mlx5_ifc_teardown_hca_in_bits {
3136         u8         opcode[0x10];
3137         u8         reserved_at_10[0x10];
3138
3139         u8         reserved_at_20[0x10];
3140         u8         op_mod[0x10];
3141
3142         u8         reserved_at_40[0x10];
3143         u8         profile[0x10];
3144
3145         u8         reserved_at_60[0x20];
3146 };
3147
3148 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3149         u8         status[0x8];
3150         u8         reserved_at_8[0x18];
3151
3152         u8         syndrome[0x20];
3153
3154         u8         reserved_at_40[0x40];
3155 };
3156
3157 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3158         u8         opcode[0x10];
3159         u8         reserved_at_10[0x10];
3160
3161         u8         reserved_at_20[0x10];
3162         u8         op_mod[0x10];
3163
3164         u8         reserved_at_40[0x8];
3165         u8         qpn[0x18];
3166
3167         u8         reserved_at_60[0x20];
3168
3169         u8         opt_param_mask[0x20];
3170
3171         u8         reserved_at_a0[0x20];
3172
3173         struct mlx5_ifc_qpc_bits qpc;
3174
3175         u8         reserved_at_800[0x80];
3176 };
3177
3178 struct mlx5_ifc_sqd2rts_qp_out_bits {
3179         u8         status[0x8];
3180         u8         reserved_at_8[0x18];
3181
3182         u8         syndrome[0x20];
3183
3184         u8         reserved_at_40[0x40];
3185 };
3186
3187 struct mlx5_ifc_sqd2rts_qp_in_bits {
3188         u8         opcode[0x10];
3189         u8         reserved_at_10[0x10];
3190
3191         u8         reserved_at_20[0x10];
3192         u8         op_mod[0x10];
3193
3194         u8         reserved_at_40[0x8];
3195         u8         qpn[0x18];
3196
3197         u8         reserved_at_60[0x20];
3198
3199         u8         opt_param_mask[0x20];
3200
3201         u8         reserved_at_a0[0x20];
3202
3203         struct mlx5_ifc_qpc_bits qpc;
3204
3205         u8         reserved_at_800[0x80];
3206 };
3207
3208 struct mlx5_ifc_set_roce_address_out_bits {
3209         u8         status[0x8];
3210         u8         reserved_at_8[0x18];
3211
3212         u8         syndrome[0x20];
3213
3214         u8         reserved_at_40[0x40];
3215 };
3216
3217 struct mlx5_ifc_set_roce_address_in_bits {
3218         u8         opcode[0x10];
3219         u8         reserved_at_10[0x10];
3220
3221         u8         reserved_at_20[0x10];
3222         u8         op_mod[0x10];
3223
3224         u8         roce_address_index[0x10];
3225         u8         reserved_at_50[0x10];
3226
3227         u8         reserved_at_60[0x20];
3228
3229         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3230 };
3231
3232 struct mlx5_ifc_set_mad_demux_out_bits {
3233         u8         status[0x8];
3234         u8         reserved_at_8[0x18];
3235
3236         u8         syndrome[0x20];
3237
3238         u8         reserved_at_40[0x40];
3239 };
3240
3241 enum {
3242         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3243         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3244 };
3245
3246 struct mlx5_ifc_set_mad_demux_in_bits {
3247         u8         opcode[0x10];
3248         u8         reserved_at_10[0x10];
3249
3250         u8         reserved_at_20[0x10];
3251         u8         op_mod[0x10];
3252
3253         u8         reserved_at_40[0x20];
3254
3255         u8         reserved_at_60[0x6];
3256         u8         demux_mode[0x2];
3257         u8         reserved_at_68[0x18];
3258 };
3259
3260 struct mlx5_ifc_set_l2_table_entry_out_bits {
3261         u8         status[0x8];
3262         u8         reserved_at_8[0x18];
3263
3264         u8         syndrome[0x20];
3265
3266         u8         reserved_at_40[0x40];
3267 };
3268
3269 struct mlx5_ifc_set_l2_table_entry_in_bits {
3270         u8         opcode[0x10];
3271         u8         reserved_at_10[0x10];
3272
3273         u8         reserved_at_20[0x10];
3274         u8         op_mod[0x10];
3275
3276         u8         reserved_at_40[0x60];
3277
3278         u8         reserved_at_a0[0x8];
3279         u8         table_index[0x18];
3280
3281         u8         reserved_at_c0[0x20];
3282
3283         u8         reserved_at_e0[0x13];
3284         u8         vlan_valid[0x1];
3285         u8         vlan[0xc];
3286
3287         struct mlx5_ifc_mac_address_layout_bits mac_address;
3288
3289         u8         reserved_at_140[0xc0];
3290 };
3291
3292 struct mlx5_ifc_set_issi_out_bits {
3293         u8         status[0x8];
3294         u8         reserved_at_8[0x18];
3295
3296         u8         syndrome[0x20];
3297
3298         u8         reserved_at_40[0x40];
3299 };
3300
3301 struct mlx5_ifc_set_issi_in_bits {
3302         u8         opcode[0x10];
3303         u8         reserved_at_10[0x10];
3304
3305         u8         reserved_at_20[0x10];
3306         u8         op_mod[0x10];
3307
3308         u8         reserved_at_40[0x10];
3309         u8         current_issi[0x10];
3310
3311         u8         reserved_at_60[0x20];
3312 };
3313
3314 struct mlx5_ifc_set_hca_cap_out_bits {
3315         u8         status[0x8];
3316         u8         reserved_at_8[0x18];
3317
3318         u8         syndrome[0x20];
3319
3320         u8         reserved_at_40[0x40];
3321 };
3322
3323 struct mlx5_ifc_set_hca_cap_in_bits {
3324         u8         opcode[0x10];
3325         u8         reserved_at_10[0x10];
3326
3327         u8         reserved_at_20[0x10];
3328         u8         op_mod[0x10];
3329
3330         u8         reserved_at_40[0x40];
3331
3332         union mlx5_ifc_hca_cap_union_bits capability;
3333 };
3334
3335 enum {
3336         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3337         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3338         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3339         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3340 };
3341
3342 struct mlx5_ifc_set_fte_out_bits {
3343         u8         status[0x8];
3344         u8         reserved_at_8[0x18];
3345
3346         u8         syndrome[0x20];
3347
3348         u8         reserved_at_40[0x40];
3349 };
3350
3351 struct mlx5_ifc_set_fte_in_bits {
3352         u8         opcode[0x10];
3353         u8         reserved_at_10[0x10];
3354
3355         u8         reserved_at_20[0x10];
3356         u8         op_mod[0x10];
3357
3358         u8         other_vport[0x1];
3359         u8         reserved_at_41[0xf];
3360         u8         vport_number[0x10];
3361
3362         u8         reserved_at_60[0x20];
3363
3364         u8         table_type[0x8];
3365         u8         reserved_at_88[0x18];
3366
3367         u8         reserved_at_a0[0x8];
3368         u8         table_id[0x18];
3369
3370         u8         reserved_at_c0[0x18];
3371         u8         modify_enable_mask[0x8];
3372
3373         u8         reserved_at_e0[0x20];
3374
3375         u8         flow_index[0x20];
3376
3377         u8         reserved_at_120[0xe0];
3378
3379         struct mlx5_ifc_flow_context_bits flow_context;
3380 };
3381
3382 struct mlx5_ifc_rts2rts_qp_out_bits {
3383         u8         status[0x8];
3384         u8         reserved_at_8[0x18];
3385
3386         u8         syndrome[0x20];
3387
3388         u8         reserved_at_40[0x40];
3389 };
3390
3391 struct mlx5_ifc_rts2rts_qp_in_bits {
3392         u8         opcode[0x10];
3393         u8         reserved_at_10[0x10];
3394
3395         u8         reserved_at_20[0x10];
3396         u8         op_mod[0x10];
3397
3398         u8         reserved_at_40[0x8];
3399         u8         qpn[0x18];
3400
3401         u8         reserved_at_60[0x20];
3402
3403         u8         opt_param_mask[0x20];
3404
3405         u8         reserved_at_a0[0x20];
3406
3407         struct mlx5_ifc_qpc_bits qpc;
3408
3409         u8         reserved_at_800[0x80];
3410 };
3411
3412 struct mlx5_ifc_rtr2rts_qp_out_bits {
3413         u8         status[0x8];
3414         u8         reserved_at_8[0x18];
3415
3416         u8         syndrome[0x20];
3417
3418         u8         reserved_at_40[0x40];
3419 };
3420
3421 struct mlx5_ifc_rtr2rts_qp_in_bits {
3422         u8         opcode[0x10];
3423         u8         reserved_at_10[0x10];
3424
3425         u8         reserved_at_20[0x10];
3426         u8         op_mod[0x10];
3427
3428         u8         reserved_at_40[0x8];
3429         u8         qpn[0x18];
3430
3431         u8         reserved_at_60[0x20];
3432
3433         u8         opt_param_mask[0x20];
3434
3435         u8         reserved_at_a0[0x20];
3436
3437         struct mlx5_ifc_qpc_bits qpc;
3438
3439         u8         reserved_at_800[0x80];
3440 };
3441
3442 struct mlx5_ifc_rst2init_qp_out_bits {
3443         u8         status[0x8];
3444         u8         reserved_at_8[0x18];
3445
3446         u8         syndrome[0x20];
3447
3448         u8         reserved_at_40[0x40];
3449 };
3450
3451 struct mlx5_ifc_rst2init_qp_in_bits {
3452         u8         opcode[0x10];
3453         u8         reserved_at_10[0x10];
3454
3455         u8         reserved_at_20[0x10];
3456         u8         op_mod[0x10];
3457
3458         u8         reserved_at_40[0x8];
3459         u8         qpn[0x18];
3460
3461         u8         reserved_at_60[0x20];
3462
3463         u8         opt_param_mask[0x20];
3464
3465         u8         reserved_at_a0[0x20];
3466
3467         struct mlx5_ifc_qpc_bits qpc;
3468
3469         u8         reserved_at_800[0x80];
3470 };
3471
3472 struct mlx5_ifc_query_xrq_out_bits {
3473         u8         status[0x8];
3474         u8         reserved_at_8[0x18];
3475
3476         u8         syndrome[0x20];
3477
3478         u8         reserved_at_40[0x40];
3479
3480         struct mlx5_ifc_xrqc_bits xrq_context;
3481 };
3482
3483 struct mlx5_ifc_query_xrq_in_bits {
3484         u8         opcode[0x10];
3485         u8         reserved_at_10[0x10];
3486
3487         u8         reserved_at_20[0x10];
3488         u8         op_mod[0x10];
3489
3490         u8         reserved_at_40[0x8];
3491         u8         xrqn[0x18];
3492
3493         u8         reserved_at_60[0x20];
3494 };
3495
3496 struct mlx5_ifc_query_xrc_srq_out_bits {
3497         u8         status[0x8];
3498         u8         reserved_at_8[0x18];
3499
3500         u8         syndrome[0x20];
3501
3502         u8         reserved_at_40[0x40];
3503
3504         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3505
3506         u8         reserved_at_280[0x600];
3507
3508         u8         pas[0][0x40];
3509 };
3510
3511 struct mlx5_ifc_query_xrc_srq_in_bits {
3512         u8         opcode[0x10];
3513         u8         reserved_at_10[0x10];
3514
3515         u8         reserved_at_20[0x10];
3516         u8         op_mod[0x10];
3517
3518         u8         reserved_at_40[0x8];
3519         u8         xrc_srqn[0x18];
3520
3521         u8         reserved_at_60[0x20];
3522 };
3523
3524 enum {
3525         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3526         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3527 };
3528
3529 struct mlx5_ifc_query_vport_state_out_bits {
3530         u8         status[0x8];
3531         u8         reserved_at_8[0x18];
3532
3533         u8         syndrome[0x20];
3534
3535         u8         reserved_at_40[0x20];
3536
3537         u8         reserved_at_60[0x18];
3538         u8         admin_state[0x4];
3539         u8         state[0x4];
3540 };
3541
3542 enum {
3543         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3544         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3545 };
3546
3547 struct mlx5_ifc_query_vport_state_in_bits {
3548         u8         opcode[0x10];
3549         u8         reserved_at_10[0x10];
3550
3551         u8         reserved_at_20[0x10];
3552         u8         op_mod[0x10];
3553
3554         u8         other_vport[0x1];
3555         u8         reserved_at_41[0xf];
3556         u8         vport_number[0x10];
3557
3558         u8         reserved_at_60[0x20];
3559 };
3560
3561 struct mlx5_ifc_query_vport_counter_out_bits {
3562         u8         status[0x8];
3563         u8         reserved_at_8[0x18];
3564
3565         u8         syndrome[0x20];
3566
3567         u8         reserved_at_40[0x40];
3568
3569         struct mlx5_ifc_traffic_counter_bits received_errors;
3570
3571         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3572
3573         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3574
3575         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3576
3577         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3578
3579         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3580
3581         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3582
3583         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3584
3585         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3586
3587         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3588
3589         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3590
3591         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3592
3593         u8         reserved_at_680[0xa00];
3594 };
3595
3596 enum {
3597         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3598 };
3599
3600 struct mlx5_ifc_query_vport_counter_in_bits {
3601         u8         opcode[0x10];
3602         u8         reserved_at_10[0x10];
3603
3604         u8         reserved_at_20[0x10];
3605         u8         op_mod[0x10];
3606
3607         u8         other_vport[0x1];
3608         u8         reserved_at_41[0xb];
3609         u8         port_num[0x4];
3610         u8         vport_number[0x10];
3611
3612         u8         reserved_at_60[0x60];
3613
3614         u8         clear[0x1];
3615         u8         reserved_at_c1[0x1f];
3616
3617         u8         reserved_at_e0[0x20];
3618 };
3619
3620 struct mlx5_ifc_query_tis_out_bits {
3621         u8         status[0x8];
3622         u8         reserved_at_8[0x18];
3623
3624         u8         syndrome[0x20];
3625
3626         u8         reserved_at_40[0x40];
3627
3628         struct mlx5_ifc_tisc_bits tis_context;
3629 };
3630
3631 struct mlx5_ifc_query_tis_in_bits {
3632         u8         opcode[0x10];
3633         u8         reserved_at_10[0x10];
3634
3635         u8         reserved_at_20[0x10];
3636         u8         op_mod[0x10];
3637
3638         u8         reserved_at_40[0x8];
3639         u8         tisn[0x18];
3640
3641         u8         reserved_at_60[0x20];
3642 };
3643
3644 struct mlx5_ifc_query_tir_out_bits {
3645         u8         status[0x8];
3646         u8         reserved_at_8[0x18];
3647
3648         u8         syndrome[0x20];
3649
3650         u8         reserved_at_40[0xc0];
3651
3652         struct mlx5_ifc_tirc_bits tir_context;
3653 };
3654
3655 struct mlx5_ifc_query_tir_in_bits {
3656         u8         opcode[0x10];
3657         u8         reserved_at_10[0x10];
3658
3659         u8         reserved_at_20[0x10];
3660         u8         op_mod[0x10];
3661
3662         u8         reserved_at_40[0x8];
3663         u8         tirn[0x18];
3664
3665         u8         reserved_at_60[0x20];
3666 };
3667
3668 struct mlx5_ifc_query_srq_out_bits {
3669         u8         status[0x8];
3670         u8         reserved_at_8[0x18];
3671
3672         u8         syndrome[0x20];
3673
3674         u8         reserved_at_40[0x40];
3675
3676         struct mlx5_ifc_srqc_bits srq_context_entry;
3677
3678         u8         reserved_at_280[0x600];
3679
3680         u8         pas[0][0x40];
3681 };
3682
3683 struct mlx5_ifc_query_srq_in_bits {
3684         u8         opcode[0x10];
3685         u8         reserved_at_10[0x10];
3686
3687         u8         reserved_at_20[0x10];
3688         u8         op_mod[0x10];
3689
3690         u8         reserved_at_40[0x8];
3691         u8         srqn[0x18];
3692
3693         u8         reserved_at_60[0x20];
3694 };
3695
3696 struct mlx5_ifc_query_sq_out_bits {
3697         u8         status[0x8];
3698         u8         reserved_at_8[0x18];
3699
3700         u8         syndrome[0x20];
3701
3702         u8         reserved_at_40[0xc0];
3703
3704         struct mlx5_ifc_sqc_bits sq_context;
3705 };
3706
3707 struct mlx5_ifc_query_sq_in_bits {
3708         u8         opcode[0x10];
3709         u8         reserved_at_10[0x10];
3710
3711         u8         reserved_at_20[0x10];
3712         u8         op_mod[0x10];
3713
3714         u8         reserved_at_40[0x8];
3715         u8         sqn[0x18];
3716
3717         u8         reserved_at_60[0x20];
3718 };
3719
3720 struct mlx5_ifc_query_special_contexts_out_bits {
3721         u8         status[0x8];
3722         u8         reserved_at_8[0x18];
3723
3724         u8         syndrome[0x20];
3725
3726         u8         dump_fill_mkey[0x20];
3727
3728         u8         resd_lkey[0x20];
3729
3730         u8         null_mkey[0x20];
3731
3732         u8         reserved_at_a0[0x60];
3733 };
3734
3735 struct mlx5_ifc_query_special_contexts_in_bits {
3736         u8         opcode[0x10];
3737         u8         reserved_at_10[0x10];
3738
3739         u8         reserved_at_20[0x10];
3740         u8         op_mod[0x10];
3741
3742         u8         reserved_at_40[0x40];
3743 };
3744
3745 struct mlx5_ifc_query_scheduling_element_out_bits {
3746         u8         opcode[0x10];
3747         u8         reserved_at_10[0x10];
3748
3749         u8         reserved_at_20[0x10];
3750         u8         op_mod[0x10];
3751
3752         u8         reserved_at_40[0xc0];
3753
3754         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3755
3756         u8         reserved_at_300[0x100];
3757 };
3758
3759 enum {
3760         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3761 };
3762
3763 struct mlx5_ifc_query_scheduling_element_in_bits {
3764         u8         opcode[0x10];
3765         u8         reserved_at_10[0x10];
3766
3767         u8         reserved_at_20[0x10];
3768         u8         op_mod[0x10];
3769
3770         u8         scheduling_hierarchy[0x8];
3771         u8         reserved_at_48[0x18];
3772
3773         u8         scheduling_element_id[0x20];
3774
3775         u8         reserved_at_80[0x180];
3776 };
3777
3778 struct mlx5_ifc_query_rqt_out_bits {
3779         u8         status[0x8];
3780         u8         reserved_at_8[0x18];
3781
3782         u8         syndrome[0x20];
3783
3784         u8         reserved_at_40[0xc0];
3785
3786         struct mlx5_ifc_rqtc_bits rqt_context;
3787 };
3788
3789 struct mlx5_ifc_query_rqt_in_bits {
3790         u8         opcode[0x10];
3791         u8         reserved_at_10[0x10];
3792
3793         u8         reserved_at_20[0x10];
3794         u8         op_mod[0x10];
3795
3796         u8         reserved_at_40[0x8];
3797         u8         rqtn[0x18];
3798
3799         u8         reserved_at_60[0x20];
3800 };
3801
3802 struct mlx5_ifc_query_rq_out_bits {
3803         u8         status[0x8];
3804         u8         reserved_at_8[0x18];
3805
3806         u8         syndrome[0x20];
3807
3808         u8         reserved_at_40[0xc0];
3809
3810         struct mlx5_ifc_rqc_bits rq_context;
3811 };
3812
3813 struct mlx5_ifc_query_rq_in_bits {
3814         u8         opcode[0x10];
3815         u8         reserved_at_10[0x10];
3816
3817         u8         reserved_at_20[0x10];
3818         u8         op_mod[0x10];
3819
3820         u8         reserved_at_40[0x8];
3821         u8         rqn[0x18];
3822
3823         u8         reserved_at_60[0x20];
3824 };
3825
3826 struct mlx5_ifc_query_roce_address_out_bits {
3827         u8         status[0x8];
3828         u8         reserved_at_8[0x18];
3829
3830         u8         syndrome[0x20];
3831
3832         u8         reserved_at_40[0x40];
3833
3834         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3835 };
3836
3837 struct mlx5_ifc_query_roce_address_in_bits {
3838         u8         opcode[0x10];
3839         u8         reserved_at_10[0x10];
3840
3841         u8         reserved_at_20[0x10];
3842         u8         op_mod[0x10];
3843
3844         u8         roce_address_index[0x10];
3845         u8         reserved_at_50[0x10];
3846
3847         u8         reserved_at_60[0x20];
3848 };
3849
3850 struct mlx5_ifc_query_rmp_out_bits {
3851         u8         status[0x8];
3852         u8         reserved_at_8[0x18];
3853
3854         u8         syndrome[0x20];
3855
3856         u8         reserved_at_40[0xc0];
3857
3858         struct mlx5_ifc_rmpc_bits rmp_context;
3859 };
3860
3861 struct mlx5_ifc_query_rmp_in_bits {
3862         u8         opcode[0x10];
3863         u8         reserved_at_10[0x10];
3864
3865         u8         reserved_at_20[0x10];
3866         u8         op_mod[0x10];
3867
3868         u8         reserved_at_40[0x8];
3869         u8         rmpn[0x18];
3870
3871         u8         reserved_at_60[0x20];
3872 };
3873
3874 struct mlx5_ifc_query_qp_out_bits {
3875         u8         status[0x8];
3876         u8         reserved_at_8[0x18];
3877
3878         u8         syndrome[0x20];
3879
3880         u8         reserved_at_40[0x40];
3881
3882         u8         opt_param_mask[0x20];
3883
3884         u8         reserved_at_a0[0x20];
3885
3886         struct mlx5_ifc_qpc_bits qpc;
3887
3888         u8         reserved_at_800[0x80];
3889
3890         u8         pas[0][0x40];
3891 };
3892
3893 struct mlx5_ifc_query_qp_in_bits {
3894         u8         opcode[0x10];
3895         u8         reserved_at_10[0x10];
3896
3897         u8         reserved_at_20[0x10];
3898         u8         op_mod[0x10];
3899
3900         u8         reserved_at_40[0x8];
3901         u8         qpn[0x18];
3902
3903         u8         reserved_at_60[0x20];
3904 };
3905
3906 struct mlx5_ifc_query_q_counter_out_bits {
3907         u8         status[0x8];
3908         u8         reserved_at_8[0x18];
3909
3910         u8         syndrome[0x20];
3911
3912         u8         reserved_at_40[0x40];
3913
3914         u8         rx_write_requests[0x20];
3915
3916         u8         reserved_at_a0[0x20];
3917
3918         u8         rx_read_requests[0x20];
3919
3920         u8         reserved_at_e0[0x20];
3921
3922         u8         rx_atomic_requests[0x20];
3923
3924         u8         reserved_at_120[0x20];
3925
3926         u8         rx_dct_connect[0x20];
3927
3928         u8         reserved_at_160[0x20];
3929
3930         u8         out_of_buffer[0x20];
3931
3932         u8         reserved_at_1a0[0x20];
3933
3934         u8         out_of_sequence[0x20];
3935
3936         u8         reserved_at_1e0[0x20];
3937
3938         u8         duplicate_request[0x20];
3939
3940         u8         reserved_at_220[0x20];
3941
3942         u8         rnr_nak_retry_err[0x20];
3943
3944         u8         reserved_at_260[0x20];
3945
3946         u8         packet_seq_err[0x20];
3947
3948         u8         reserved_at_2a0[0x20];
3949
3950         u8         implied_nak_seq_err[0x20];
3951
3952         u8         reserved_at_2e0[0x20];
3953
3954         u8         local_ack_timeout_err[0x20];
3955
3956         u8         reserved_at_320[0x4e0];
3957 };
3958
3959 struct mlx5_ifc_query_q_counter_in_bits {
3960         u8         opcode[0x10];
3961         u8         reserved_at_10[0x10];
3962
3963         u8         reserved_at_20[0x10];
3964         u8         op_mod[0x10];
3965
3966         u8         reserved_at_40[0x80];
3967
3968         u8         clear[0x1];
3969         u8         reserved_at_c1[0x1f];
3970
3971         u8         reserved_at_e0[0x18];
3972         u8         counter_set_id[0x8];
3973 };
3974
3975 struct mlx5_ifc_query_pages_out_bits {
3976         u8         status[0x8];
3977         u8         reserved_at_8[0x18];
3978
3979         u8         syndrome[0x20];
3980
3981         u8         reserved_at_40[0x10];
3982         u8         function_id[0x10];
3983
3984         u8         num_pages[0x20];
3985 };
3986
3987 enum {
3988         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3989         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3990         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3991 };
3992
3993 struct mlx5_ifc_query_pages_in_bits {
3994         u8         opcode[0x10];
3995         u8         reserved_at_10[0x10];
3996
3997         u8         reserved_at_20[0x10];
3998         u8         op_mod[0x10];
3999
4000         u8         reserved_at_40[0x10];
4001         u8         function_id[0x10];
4002
4003         u8         reserved_at_60[0x20];
4004 };
4005
4006 struct mlx5_ifc_query_nic_vport_context_out_bits {
4007         u8         status[0x8];
4008         u8         reserved_at_8[0x18];
4009
4010         u8         syndrome[0x20];
4011
4012         u8         reserved_at_40[0x40];
4013
4014         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4015 };
4016
4017 struct mlx5_ifc_query_nic_vport_context_in_bits {
4018         u8         opcode[0x10];
4019         u8         reserved_at_10[0x10];
4020
4021         u8         reserved_at_20[0x10];
4022         u8         op_mod[0x10];
4023
4024         u8         other_vport[0x1];
4025         u8         reserved_at_41[0xf];
4026         u8         vport_number[0x10];
4027
4028         u8         reserved_at_60[0x5];
4029         u8         allowed_list_type[0x3];
4030         u8         reserved_at_68[0x18];
4031 };
4032
4033 struct mlx5_ifc_query_mkey_out_bits {
4034         u8         status[0x8];
4035         u8         reserved_at_8[0x18];
4036
4037         u8         syndrome[0x20];
4038
4039         u8         reserved_at_40[0x40];
4040
4041         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4042
4043         u8         reserved_at_280[0x600];
4044
4045         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4046
4047         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4048 };
4049
4050 struct mlx5_ifc_query_mkey_in_bits {
4051         u8         opcode[0x10];
4052         u8         reserved_at_10[0x10];
4053
4054         u8         reserved_at_20[0x10];
4055         u8         op_mod[0x10];
4056
4057         u8         reserved_at_40[0x8];
4058         u8         mkey_index[0x18];
4059
4060         u8         pg_access[0x1];
4061         u8         reserved_at_61[0x1f];
4062 };
4063
4064 struct mlx5_ifc_query_mad_demux_out_bits {
4065         u8         status[0x8];
4066         u8         reserved_at_8[0x18];
4067
4068         u8         syndrome[0x20];
4069
4070         u8         reserved_at_40[0x40];
4071
4072         u8         mad_dumux_parameters_block[0x20];
4073 };
4074
4075 struct mlx5_ifc_query_mad_demux_in_bits {
4076         u8         opcode[0x10];
4077         u8         reserved_at_10[0x10];
4078
4079         u8         reserved_at_20[0x10];
4080         u8         op_mod[0x10];
4081
4082         u8         reserved_at_40[0x40];
4083 };
4084
4085 struct mlx5_ifc_query_l2_table_entry_out_bits {
4086         u8         status[0x8];
4087         u8         reserved_at_8[0x18];
4088
4089         u8         syndrome[0x20];
4090
4091         u8         reserved_at_40[0xa0];
4092
4093         u8         reserved_at_e0[0x13];
4094         u8         vlan_valid[0x1];
4095         u8         vlan[0xc];
4096
4097         struct mlx5_ifc_mac_address_layout_bits mac_address;
4098
4099         u8         reserved_at_140[0xc0];
4100 };
4101
4102 struct mlx5_ifc_query_l2_table_entry_in_bits {
4103         u8         opcode[0x10];
4104         u8         reserved_at_10[0x10];
4105
4106         u8         reserved_at_20[0x10];
4107         u8         op_mod[0x10];
4108
4109         u8         reserved_at_40[0x60];
4110
4111         u8         reserved_at_a0[0x8];
4112         u8         table_index[0x18];
4113
4114         u8         reserved_at_c0[0x140];
4115 };
4116
4117 struct mlx5_ifc_query_issi_out_bits {
4118         u8         status[0x8];
4119         u8         reserved_at_8[0x18];
4120
4121         u8         syndrome[0x20];
4122
4123         u8         reserved_at_40[0x10];
4124         u8         current_issi[0x10];
4125
4126         u8         reserved_at_60[0xa0];
4127
4128         u8         reserved_at_100[76][0x8];
4129         u8         supported_issi_dw0[0x20];
4130 };
4131
4132 struct mlx5_ifc_query_issi_in_bits {
4133         u8         opcode[0x10];
4134         u8         reserved_at_10[0x10];
4135
4136         u8         reserved_at_20[0x10];
4137         u8         op_mod[0x10];
4138
4139         u8         reserved_at_40[0x40];
4140 };
4141
4142 struct mlx5_ifc_set_driver_version_out_bits {
4143         u8         status[0x8];
4144         u8         reserved_0[0x18];
4145
4146         u8         syndrome[0x20];
4147         u8         reserved_1[0x40];
4148 };
4149
4150 struct mlx5_ifc_set_driver_version_in_bits {
4151         u8         opcode[0x10];
4152         u8         reserved_0[0x10];
4153
4154         u8         reserved_1[0x10];
4155         u8         op_mod[0x10];
4156
4157         u8         reserved_2[0x40];
4158         u8         driver_version[64][0x8];
4159 };
4160
4161 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4162         u8         status[0x8];
4163         u8         reserved_at_8[0x18];
4164
4165         u8         syndrome[0x20];
4166
4167         u8         reserved_at_40[0x40];
4168
4169         struct mlx5_ifc_pkey_bits pkey[0];
4170 };
4171
4172 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4173         u8         opcode[0x10];
4174         u8         reserved_at_10[0x10];
4175
4176         u8         reserved_at_20[0x10];
4177         u8         op_mod[0x10];
4178
4179         u8         other_vport[0x1];
4180         u8         reserved_at_41[0xb];
4181         u8         port_num[0x4];
4182         u8         vport_number[0x10];
4183
4184         u8         reserved_at_60[0x10];
4185         u8         pkey_index[0x10];
4186 };
4187
4188 enum {
4189         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4190         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4191         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4192 };
4193
4194 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4195         u8         status[0x8];
4196         u8         reserved_at_8[0x18];
4197
4198         u8         syndrome[0x20];
4199
4200         u8         reserved_at_40[0x20];
4201
4202         u8         gids_num[0x10];
4203         u8         reserved_at_70[0x10];
4204
4205         struct mlx5_ifc_array128_auto_bits gid[0];
4206 };
4207
4208 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4209         u8         opcode[0x10];
4210         u8         reserved_at_10[0x10];
4211
4212         u8         reserved_at_20[0x10];
4213         u8         op_mod[0x10];
4214
4215         u8         other_vport[0x1];
4216         u8         reserved_at_41[0xb];
4217         u8         port_num[0x4];
4218         u8         vport_number[0x10];
4219
4220         u8         reserved_at_60[0x10];
4221         u8         gid_index[0x10];
4222 };
4223
4224 struct mlx5_ifc_query_hca_vport_context_out_bits {
4225         u8         status[0x8];
4226         u8         reserved_at_8[0x18];
4227
4228         u8         syndrome[0x20];
4229
4230         u8         reserved_at_40[0x40];
4231
4232         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4233 };
4234
4235 struct mlx5_ifc_query_hca_vport_context_in_bits {
4236         u8         opcode[0x10];
4237         u8         reserved_at_10[0x10];
4238
4239         u8         reserved_at_20[0x10];
4240         u8         op_mod[0x10];
4241
4242         u8         other_vport[0x1];
4243         u8         reserved_at_41[0xb];
4244         u8         port_num[0x4];
4245         u8         vport_number[0x10];
4246
4247         u8         reserved_at_60[0x20];
4248 };
4249
4250 struct mlx5_ifc_query_hca_cap_out_bits {
4251         u8         status[0x8];
4252         u8         reserved_at_8[0x18];
4253
4254         u8         syndrome[0x20];
4255
4256         u8         reserved_at_40[0x40];
4257
4258         union mlx5_ifc_hca_cap_union_bits capability;
4259 };
4260
4261 struct mlx5_ifc_query_hca_cap_in_bits {
4262         u8         opcode[0x10];
4263         u8         reserved_at_10[0x10];
4264
4265         u8         reserved_at_20[0x10];
4266         u8         op_mod[0x10];
4267
4268         u8         reserved_at_40[0x40];
4269 };
4270
4271 struct mlx5_ifc_query_flow_table_out_bits {
4272         u8         status[0x8];
4273         u8         reserved_at_8[0x18];
4274
4275         u8         syndrome[0x20];
4276
4277         u8         reserved_at_40[0x80];
4278
4279         u8         reserved_at_c0[0x8];
4280         u8         level[0x8];
4281         u8         reserved_at_d0[0x8];
4282         u8         log_size[0x8];
4283
4284         u8         reserved_at_e0[0x120];
4285 };
4286
4287 struct mlx5_ifc_query_flow_table_in_bits {
4288         u8         opcode[0x10];
4289         u8         reserved_at_10[0x10];
4290
4291         u8         reserved_at_20[0x10];
4292         u8         op_mod[0x10];
4293
4294         u8         reserved_at_40[0x40];
4295
4296         u8         table_type[0x8];
4297         u8         reserved_at_88[0x18];
4298
4299         u8         reserved_at_a0[0x8];
4300         u8         table_id[0x18];
4301
4302         u8         reserved_at_c0[0x140];
4303 };
4304
4305 struct mlx5_ifc_query_fte_out_bits {
4306         u8         status[0x8];
4307         u8         reserved_at_8[0x18];
4308
4309         u8         syndrome[0x20];
4310
4311         u8         reserved_at_40[0x1c0];
4312
4313         struct mlx5_ifc_flow_context_bits flow_context;
4314 };
4315
4316 struct mlx5_ifc_query_fte_in_bits {
4317         u8         opcode[0x10];
4318         u8         reserved_at_10[0x10];
4319
4320         u8         reserved_at_20[0x10];
4321         u8         op_mod[0x10];
4322
4323         u8         reserved_at_40[0x40];
4324
4325         u8         table_type[0x8];
4326         u8         reserved_at_88[0x18];
4327
4328         u8         reserved_at_a0[0x8];
4329         u8         table_id[0x18];
4330
4331         u8         reserved_at_c0[0x40];
4332
4333         u8         flow_index[0x20];
4334
4335         u8         reserved_at_120[0xe0];
4336 };
4337
4338 enum {
4339         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4340         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4341         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4342 };
4343
4344 struct mlx5_ifc_query_flow_group_out_bits {
4345         u8         status[0x8];
4346         u8         reserved_at_8[0x18];
4347
4348         u8         syndrome[0x20];
4349
4350         u8         reserved_at_40[0xa0];
4351
4352         u8         start_flow_index[0x20];
4353
4354         u8         reserved_at_100[0x20];
4355
4356         u8         end_flow_index[0x20];
4357
4358         u8         reserved_at_140[0xa0];
4359
4360         u8         reserved_at_1e0[0x18];
4361         u8         match_criteria_enable[0x8];
4362
4363         struct mlx5_ifc_fte_match_param_bits match_criteria;
4364
4365         u8         reserved_at_1200[0xe00];
4366 };
4367
4368 struct mlx5_ifc_query_flow_group_in_bits {
4369         u8         opcode[0x10];
4370         u8         reserved_at_10[0x10];
4371
4372         u8         reserved_at_20[0x10];
4373         u8         op_mod[0x10];
4374
4375         u8         reserved_at_40[0x40];
4376
4377         u8         table_type[0x8];
4378         u8         reserved_at_88[0x18];
4379
4380         u8         reserved_at_a0[0x8];
4381         u8         table_id[0x18];
4382
4383         u8         group_id[0x20];
4384
4385         u8         reserved_at_e0[0x120];
4386 };
4387
4388 struct mlx5_ifc_query_flow_counter_out_bits {
4389         u8         status[0x8];
4390         u8         reserved_at_8[0x18];
4391
4392         u8         syndrome[0x20];
4393
4394         u8         reserved_at_40[0x40];
4395
4396         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4397 };
4398
4399 struct mlx5_ifc_query_flow_counter_in_bits {
4400         u8         opcode[0x10];
4401         u8         reserved_at_10[0x10];
4402
4403         u8         reserved_at_20[0x10];
4404         u8         op_mod[0x10];
4405
4406         u8         reserved_at_40[0x80];
4407
4408         u8         clear[0x1];
4409         u8         reserved_at_c1[0xf];
4410         u8         num_of_counters[0x10];
4411
4412         u8         reserved_at_e0[0x10];
4413         u8         flow_counter_id[0x10];
4414 };
4415
4416 struct mlx5_ifc_query_esw_vport_context_out_bits {
4417         u8         status[0x8];
4418         u8         reserved_at_8[0x18];
4419
4420         u8         syndrome[0x20];
4421
4422         u8         reserved_at_40[0x40];
4423
4424         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4425 };
4426
4427 struct mlx5_ifc_query_esw_vport_context_in_bits {
4428         u8         opcode[0x10];
4429         u8         reserved_at_10[0x10];
4430
4431         u8         reserved_at_20[0x10];
4432         u8         op_mod[0x10];
4433
4434         u8         other_vport[0x1];
4435         u8         reserved_at_41[0xf];
4436         u8         vport_number[0x10];
4437
4438         u8         reserved_at_60[0x20];
4439 };
4440
4441 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4442         u8         status[0x8];
4443         u8         reserved_at_8[0x18];
4444
4445         u8         syndrome[0x20];
4446
4447         u8         reserved_at_40[0x40];
4448 };
4449
4450 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4451         u8         reserved_at_0[0x1c];
4452         u8         vport_cvlan_insert[0x1];
4453         u8         vport_svlan_insert[0x1];
4454         u8         vport_cvlan_strip[0x1];
4455         u8         vport_svlan_strip[0x1];
4456 };
4457
4458 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4459         u8         opcode[0x10];
4460         u8         reserved_at_10[0x10];
4461
4462         u8         reserved_at_20[0x10];
4463         u8         op_mod[0x10];
4464
4465         u8         other_vport[0x1];
4466         u8         reserved_at_41[0xf];
4467         u8         vport_number[0x10];
4468
4469         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4470
4471         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4472 };
4473
4474 struct mlx5_ifc_query_eq_out_bits {
4475         u8         status[0x8];
4476         u8         reserved_at_8[0x18];
4477
4478         u8         syndrome[0x20];
4479
4480         u8         reserved_at_40[0x40];
4481
4482         struct mlx5_ifc_eqc_bits eq_context_entry;
4483
4484         u8         reserved_at_280[0x40];
4485
4486         u8         event_bitmask[0x40];
4487
4488         u8         reserved_at_300[0x580];
4489
4490         u8         pas[0][0x40];
4491 };
4492
4493 struct mlx5_ifc_query_eq_in_bits {
4494         u8         opcode[0x10];
4495         u8         reserved_at_10[0x10];
4496
4497         u8         reserved_at_20[0x10];
4498         u8         op_mod[0x10];
4499
4500         u8         reserved_at_40[0x18];
4501         u8         eq_number[0x8];
4502
4503         u8         reserved_at_60[0x20];
4504 };
4505
4506 struct mlx5_ifc_encap_header_in_bits {
4507         u8         reserved_at_0[0x5];
4508         u8         header_type[0x3];
4509         u8         reserved_at_8[0xe];
4510         u8         encap_header_size[0xa];
4511
4512         u8         reserved_at_20[0x10];
4513         u8         encap_header[2][0x8];
4514
4515         u8         more_encap_header[0][0x8];
4516 };
4517
4518 struct mlx5_ifc_query_encap_header_out_bits {
4519         u8         status[0x8];
4520         u8         reserved_at_8[0x18];
4521
4522         u8         syndrome[0x20];
4523
4524         u8         reserved_at_40[0xa0];
4525
4526         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4527 };
4528
4529 struct mlx5_ifc_query_encap_header_in_bits {
4530         u8         opcode[0x10];
4531         u8         reserved_at_10[0x10];
4532
4533         u8         reserved_at_20[0x10];
4534         u8         op_mod[0x10];
4535
4536         u8         encap_id[0x20];
4537
4538         u8         reserved_at_60[0xa0];
4539 };
4540
4541 struct mlx5_ifc_alloc_encap_header_out_bits {
4542         u8         status[0x8];
4543         u8         reserved_at_8[0x18];
4544
4545         u8         syndrome[0x20];
4546
4547         u8         encap_id[0x20];
4548
4549         u8         reserved_at_60[0x20];
4550 };
4551
4552 struct mlx5_ifc_alloc_encap_header_in_bits {
4553         u8         opcode[0x10];
4554         u8         reserved_at_10[0x10];
4555
4556         u8         reserved_at_20[0x10];
4557         u8         op_mod[0x10];
4558
4559         u8         reserved_at_40[0xa0];
4560
4561         struct mlx5_ifc_encap_header_in_bits encap_header;
4562 };
4563
4564 struct mlx5_ifc_dealloc_encap_header_out_bits {
4565         u8         status[0x8];
4566         u8         reserved_at_8[0x18];
4567
4568         u8         syndrome[0x20];
4569
4570         u8         reserved_at_40[0x40];
4571 };
4572
4573 struct mlx5_ifc_dealloc_encap_header_in_bits {
4574         u8         opcode[0x10];
4575         u8         reserved_at_10[0x10];
4576
4577         u8         reserved_20[0x10];
4578         u8         op_mod[0x10];
4579
4580         u8         encap_id[0x20];
4581
4582         u8         reserved_60[0x20];
4583 };
4584
4585 struct mlx5_ifc_set_action_in_bits {
4586         u8         action_type[0x4];
4587         u8         field[0xc];
4588         u8         reserved_at_10[0x3];
4589         u8         offset[0x5];
4590         u8         reserved_at_18[0x3];
4591         u8         length[0x5];
4592
4593         u8         data[0x20];
4594 };
4595
4596 struct mlx5_ifc_add_action_in_bits {
4597         u8         action_type[0x4];
4598         u8         field[0xc];
4599         u8         reserved_at_10[0x10];
4600
4601         u8         data[0x20];
4602 };
4603
4604 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4605         struct mlx5_ifc_set_action_in_bits set_action_in;
4606         struct mlx5_ifc_add_action_in_bits add_action_in;
4607         u8         reserved_at_0[0x40];
4608 };
4609
4610 enum {
4611         MLX5_ACTION_TYPE_SET   = 0x1,
4612         MLX5_ACTION_TYPE_ADD   = 0x2,
4613 };
4614
4615 enum {
4616         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4617         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4618         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4619         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4620         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4621         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4622         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4623         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4624         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4625         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4626         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4627         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4628         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4629         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4630         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4631         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4632         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4633         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4634         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4635         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4636         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4637         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4638         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4639 };
4640
4641 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4642         u8         status[0x8];
4643         u8         reserved_at_8[0x18];
4644
4645         u8         syndrome[0x20];
4646
4647         u8         modify_header_id[0x20];
4648
4649         u8         reserved_at_60[0x20];
4650 };
4651
4652 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4653         u8         opcode[0x10];
4654         u8         reserved_at_10[0x10];
4655
4656         u8         reserved_at_20[0x10];
4657         u8         op_mod[0x10];
4658
4659         u8         reserved_at_40[0x20];
4660
4661         u8         table_type[0x8];
4662         u8         reserved_at_68[0x10];
4663         u8         num_of_actions[0x8];
4664
4665         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4666 };
4667
4668 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4669         u8         status[0x8];
4670         u8         reserved_at_8[0x18];
4671
4672         u8         syndrome[0x20];
4673
4674         u8         reserved_at_40[0x40];
4675 };
4676
4677 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4678         u8         opcode[0x10];
4679         u8         reserved_at_10[0x10];
4680
4681         u8         reserved_at_20[0x10];
4682         u8         op_mod[0x10];
4683
4684         u8         modify_header_id[0x20];
4685
4686         u8         reserved_at_60[0x20];
4687 };
4688
4689 struct mlx5_ifc_query_dct_out_bits {
4690         u8         status[0x8];
4691         u8         reserved_at_8[0x18];
4692
4693         u8         syndrome[0x20];
4694
4695         u8         reserved_at_40[0x40];
4696
4697         struct mlx5_ifc_dctc_bits dct_context_entry;
4698
4699         u8         reserved_at_280[0x180];
4700 };
4701
4702 struct mlx5_ifc_query_dct_in_bits {
4703         u8         opcode[0x10];
4704         u8         reserved_at_10[0x10];
4705
4706         u8         reserved_at_20[0x10];
4707         u8         op_mod[0x10];
4708
4709         u8         reserved_at_40[0x8];
4710         u8         dctn[0x18];
4711
4712         u8         reserved_at_60[0x20];
4713 };
4714
4715 struct mlx5_ifc_query_cq_out_bits {
4716         u8         status[0x8];
4717         u8         reserved_at_8[0x18];
4718
4719         u8         syndrome[0x20];
4720
4721         u8         reserved_at_40[0x40];
4722
4723         struct mlx5_ifc_cqc_bits cq_context;
4724
4725         u8         reserved_at_280[0x600];
4726
4727         u8         pas[0][0x40];
4728 };
4729
4730 struct mlx5_ifc_query_cq_in_bits {
4731         u8         opcode[0x10];
4732         u8         reserved_at_10[0x10];
4733
4734         u8         reserved_at_20[0x10];
4735         u8         op_mod[0x10];
4736
4737         u8         reserved_at_40[0x8];
4738         u8         cqn[0x18];
4739
4740         u8         reserved_at_60[0x20];
4741 };
4742
4743 struct mlx5_ifc_query_cong_status_out_bits {
4744         u8         status[0x8];
4745         u8         reserved_at_8[0x18];
4746
4747         u8         syndrome[0x20];
4748
4749         u8         reserved_at_40[0x20];
4750
4751         u8         enable[0x1];
4752         u8         tag_enable[0x1];
4753         u8         reserved_at_62[0x1e];
4754 };
4755
4756 struct mlx5_ifc_query_cong_status_in_bits {
4757         u8         opcode[0x10];
4758         u8         reserved_at_10[0x10];
4759
4760         u8         reserved_at_20[0x10];
4761         u8         op_mod[0x10];
4762
4763         u8         reserved_at_40[0x18];
4764         u8         priority[0x4];
4765         u8         cong_protocol[0x4];
4766
4767         u8         reserved_at_60[0x20];
4768 };
4769
4770 struct mlx5_ifc_query_cong_statistics_out_bits {
4771         u8         status[0x8];
4772         u8         reserved_at_8[0x18];
4773
4774         u8         syndrome[0x20];
4775
4776         u8         reserved_at_40[0x40];
4777
4778         u8         rp_cur_flows[0x20];
4779
4780         u8         sum_flows[0x20];
4781
4782         u8         rp_cnp_ignored_high[0x20];
4783
4784         u8         rp_cnp_ignored_low[0x20];
4785
4786         u8         rp_cnp_handled_high[0x20];
4787
4788         u8         rp_cnp_handled_low[0x20];
4789
4790         u8         reserved_at_140[0x100];
4791
4792         u8         time_stamp_high[0x20];
4793
4794         u8         time_stamp_low[0x20];
4795
4796         u8         accumulators_period[0x20];
4797
4798         u8         np_ecn_marked_roce_packets_high[0x20];
4799
4800         u8         np_ecn_marked_roce_packets_low[0x20];
4801
4802         u8         np_cnp_sent_high[0x20];
4803
4804         u8         np_cnp_sent_low[0x20];
4805
4806         u8         reserved_at_320[0x560];
4807 };
4808
4809 struct mlx5_ifc_query_cong_statistics_in_bits {
4810         u8         opcode[0x10];
4811         u8         reserved_at_10[0x10];
4812
4813         u8         reserved_at_20[0x10];
4814         u8         op_mod[0x10];
4815
4816         u8         clear[0x1];
4817         u8         reserved_at_41[0x1f];
4818
4819         u8         reserved_at_60[0x20];
4820 };
4821
4822 struct mlx5_ifc_query_cong_params_out_bits {
4823         u8         status[0x8];
4824         u8         reserved_at_8[0x18];
4825
4826         u8         syndrome[0x20];
4827
4828         u8         reserved_at_40[0x40];
4829
4830         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4831 };
4832
4833 struct mlx5_ifc_query_cong_params_in_bits {
4834         u8         opcode[0x10];
4835         u8         reserved_at_10[0x10];
4836
4837         u8         reserved_at_20[0x10];
4838         u8         op_mod[0x10];
4839
4840         u8         reserved_at_40[0x1c];
4841         u8         cong_protocol[0x4];
4842
4843         u8         reserved_at_60[0x20];
4844 };
4845
4846 struct mlx5_ifc_query_adapter_out_bits {
4847         u8         status[0x8];
4848         u8         reserved_at_8[0x18];
4849
4850         u8         syndrome[0x20];
4851
4852         u8         reserved_at_40[0x40];
4853
4854         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4855 };
4856
4857 struct mlx5_ifc_query_adapter_in_bits {
4858         u8         opcode[0x10];
4859         u8         reserved_at_10[0x10];
4860
4861         u8         reserved_at_20[0x10];
4862         u8         op_mod[0x10];
4863
4864         u8         reserved_at_40[0x40];
4865 };
4866
4867 struct mlx5_ifc_qp_2rst_out_bits {
4868         u8         status[0x8];
4869         u8         reserved_at_8[0x18];
4870
4871         u8         syndrome[0x20];
4872
4873         u8         reserved_at_40[0x40];
4874 };
4875
4876 struct mlx5_ifc_qp_2rst_in_bits {
4877         u8         opcode[0x10];
4878         u8         reserved_at_10[0x10];
4879
4880         u8         reserved_at_20[0x10];
4881         u8         op_mod[0x10];
4882
4883         u8         reserved_at_40[0x8];
4884         u8         qpn[0x18];
4885
4886         u8         reserved_at_60[0x20];
4887 };
4888
4889 struct mlx5_ifc_qp_2err_out_bits {
4890         u8         status[0x8];
4891         u8         reserved_at_8[0x18];
4892
4893         u8         syndrome[0x20];
4894
4895         u8         reserved_at_40[0x40];
4896 };
4897
4898 struct mlx5_ifc_qp_2err_in_bits {
4899         u8         opcode[0x10];
4900         u8         reserved_at_10[0x10];
4901
4902         u8         reserved_at_20[0x10];
4903         u8         op_mod[0x10];
4904
4905         u8         reserved_at_40[0x8];
4906         u8         qpn[0x18];
4907
4908         u8         reserved_at_60[0x20];
4909 };
4910
4911 struct mlx5_ifc_page_fault_resume_out_bits {
4912         u8         status[0x8];
4913         u8         reserved_at_8[0x18];
4914
4915         u8         syndrome[0x20];
4916
4917         u8         reserved_at_40[0x40];
4918 };
4919
4920 struct mlx5_ifc_page_fault_resume_in_bits {
4921         u8         opcode[0x10];
4922         u8         reserved_at_10[0x10];
4923
4924         u8         reserved_at_20[0x10];
4925         u8         op_mod[0x10];
4926
4927         u8         error[0x1];
4928         u8         reserved_at_41[0x4];
4929         u8         page_fault_type[0x3];
4930         u8         wq_number[0x18];
4931
4932         u8         reserved_at_60[0x8];
4933         u8         token[0x18];
4934 };
4935
4936 struct mlx5_ifc_nop_out_bits {
4937         u8         status[0x8];
4938         u8         reserved_at_8[0x18];
4939
4940         u8         syndrome[0x20];
4941
4942         u8         reserved_at_40[0x40];
4943 };
4944
4945 struct mlx5_ifc_nop_in_bits {
4946         u8         opcode[0x10];
4947         u8         reserved_at_10[0x10];
4948
4949         u8         reserved_at_20[0x10];
4950         u8         op_mod[0x10];
4951
4952         u8         reserved_at_40[0x40];
4953 };
4954
4955 struct mlx5_ifc_modify_vport_state_out_bits {
4956         u8         status[0x8];
4957         u8         reserved_at_8[0x18];
4958
4959         u8         syndrome[0x20];
4960
4961         u8         reserved_at_40[0x40];
4962 };
4963
4964 struct mlx5_ifc_modify_vport_state_in_bits {
4965         u8         opcode[0x10];
4966         u8         reserved_at_10[0x10];
4967
4968         u8         reserved_at_20[0x10];
4969         u8         op_mod[0x10];
4970
4971         u8         other_vport[0x1];
4972         u8         reserved_at_41[0xf];
4973         u8         vport_number[0x10];
4974
4975         u8         reserved_at_60[0x18];
4976         u8         admin_state[0x4];
4977         u8         reserved_at_7c[0x4];
4978 };
4979
4980 struct mlx5_ifc_modify_tis_out_bits {
4981         u8         status[0x8];
4982         u8         reserved_at_8[0x18];
4983
4984         u8         syndrome[0x20];
4985
4986         u8         reserved_at_40[0x40];
4987 };
4988
4989 struct mlx5_ifc_modify_tis_bitmask_bits {
4990         u8         reserved_at_0[0x20];
4991
4992         u8         reserved_at_20[0x1d];
4993         u8         lag_tx_port_affinity[0x1];
4994         u8         strict_lag_tx_port_affinity[0x1];
4995         u8         prio[0x1];
4996 };
4997
4998 struct mlx5_ifc_modify_tis_in_bits {
4999         u8         opcode[0x10];
5000         u8         reserved_at_10[0x10];
5001
5002         u8         reserved_at_20[0x10];
5003         u8         op_mod[0x10];
5004
5005         u8         reserved_at_40[0x8];
5006         u8         tisn[0x18];
5007
5008         u8         reserved_at_60[0x20];
5009
5010         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5011
5012         u8         reserved_at_c0[0x40];
5013
5014         struct mlx5_ifc_tisc_bits ctx;
5015 };
5016
5017 struct mlx5_ifc_modify_tir_bitmask_bits {
5018         u8         reserved_at_0[0x20];
5019
5020         u8         reserved_at_20[0x1b];
5021         u8         self_lb_en[0x1];
5022         u8         reserved_at_3c[0x1];
5023         u8         hash[0x1];
5024         u8         reserved_at_3e[0x1];
5025         u8         lro[0x1];
5026 };
5027
5028 struct mlx5_ifc_modify_tir_out_bits {
5029         u8         status[0x8];
5030         u8         reserved_at_8[0x18];
5031
5032         u8         syndrome[0x20];
5033
5034         u8         reserved_at_40[0x40];
5035 };
5036
5037 struct mlx5_ifc_modify_tir_in_bits {
5038         u8         opcode[0x10];
5039         u8         reserved_at_10[0x10];
5040
5041         u8         reserved_at_20[0x10];
5042         u8         op_mod[0x10];
5043
5044         u8         reserved_at_40[0x8];
5045         u8         tirn[0x18];
5046
5047         u8         reserved_at_60[0x20];
5048
5049         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5050
5051         u8         reserved_at_c0[0x40];
5052
5053         struct mlx5_ifc_tirc_bits ctx;
5054 };
5055
5056 struct mlx5_ifc_modify_sq_out_bits {
5057         u8         status[0x8];
5058         u8         reserved_at_8[0x18];
5059
5060         u8         syndrome[0x20];
5061
5062         u8         reserved_at_40[0x40];
5063 };
5064
5065 struct mlx5_ifc_modify_sq_in_bits {
5066         u8         opcode[0x10];
5067         u8         reserved_at_10[0x10];
5068
5069         u8         reserved_at_20[0x10];
5070         u8         op_mod[0x10];
5071
5072         u8         sq_state[0x4];
5073         u8         reserved_at_44[0x4];
5074         u8         sqn[0x18];
5075
5076         u8         reserved_at_60[0x20];
5077
5078         u8         modify_bitmask[0x40];
5079
5080         u8         reserved_at_c0[0x40];
5081
5082         struct mlx5_ifc_sqc_bits ctx;
5083 };
5084
5085 struct mlx5_ifc_modify_scheduling_element_out_bits {
5086         u8         status[0x8];
5087         u8         reserved_at_8[0x18];
5088
5089         u8         syndrome[0x20];
5090
5091         u8         reserved_at_40[0x1c0];
5092 };
5093
5094 enum {
5095         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5096         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5097 };
5098
5099 struct mlx5_ifc_modify_scheduling_element_in_bits {
5100         u8         opcode[0x10];
5101         u8         reserved_at_10[0x10];
5102
5103         u8         reserved_at_20[0x10];
5104         u8         op_mod[0x10];
5105
5106         u8         scheduling_hierarchy[0x8];
5107         u8         reserved_at_48[0x18];
5108
5109         u8         scheduling_element_id[0x20];
5110
5111         u8         reserved_at_80[0x20];
5112
5113         u8         modify_bitmask[0x20];
5114
5115         u8         reserved_at_c0[0x40];
5116
5117         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5118
5119         u8         reserved_at_300[0x100];
5120 };
5121
5122 struct mlx5_ifc_modify_rqt_out_bits {
5123         u8         status[0x8];
5124         u8         reserved_at_8[0x18];
5125
5126         u8         syndrome[0x20];
5127
5128         u8         reserved_at_40[0x40];
5129 };
5130
5131 struct mlx5_ifc_rqt_bitmask_bits {
5132         u8         reserved_at_0[0x20];
5133
5134         u8         reserved_at_20[0x1f];
5135         u8         rqn_list[0x1];
5136 };
5137
5138 struct mlx5_ifc_modify_rqt_in_bits {
5139         u8         opcode[0x10];
5140         u8         reserved_at_10[0x10];
5141
5142         u8         reserved_at_20[0x10];
5143         u8         op_mod[0x10];
5144
5145         u8         reserved_at_40[0x8];
5146         u8         rqtn[0x18];
5147
5148         u8         reserved_at_60[0x20];
5149
5150         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5151
5152         u8         reserved_at_c0[0x40];
5153
5154         struct mlx5_ifc_rqtc_bits ctx;
5155 };
5156
5157 struct mlx5_ifc_modify_rq_out_bits {
5158         u8         status[0x8];
5159         u8         reserved_at_8[0x18];
5160
5161         u8         syndrome[0x20];
5162
5163         u8         reserved_at_40[0x40];
5164 };
5165
5166 enum {
5167         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5168         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5169         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5170 };
5171
5172 struct mlx5_ifc_modify_rq_in_bits {
5173         u8         opcode[0x10];
5174         u8         reserved_at_10[0x10];
5175
5176         u8         reserved_at_20[0x10];
5177         u8         op_mod[0x10];
5178
5179         u8         rq_state[0x4];
5180         u8         reserved_at_44[0x4];
5181         u8         rqn[0x18];
5182
5183         u8         reserved_at_60[0x20];
5184
5185         u8         modify_bitmask[0x40];
5186
5187         u8         reserved_at_c0[0x40];
5188
5189         struct mlx5_ifc_rqc_bits ctx;
5190 };
5191
5192 struct mlx5_ifc_modify_rmp_out_bits {
5193         u8         status[0x8];
5194         u8         reserved_at_8[0x18];
5195
5196         u8         syndrome[0x20];
5197
5198         u8         reserved_at_40[0x40];
5199 };
5200
5201 struct mlx5_ifc_rmp_bitmask_bits {
5202         u8         reserved_at_0[0x20];
5203
5204         u8         reserved_at_20[0x1f];
5205         u8         lwm[0x1];
5206 };
5207
5208 struct mlx5_ifc_modify_rmp_in_bits {
5209         u8         opcode[0x10];
5210         u8         reserved_at_10[0x10];
5211
5212         u8         reserved_at_20[0x10];
5213         u8         op_mod[0x10];
5214
5215         u8         rmp_state[0x4];
5216         u8         reserved_at_44[0x4];
5217         u8         rmpn[0x18];
5218
5219         u8         reserved_at_60[0x20];
5220
5221         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5222
5223         u8         reserved_at_c0[0x40];
5224
5225         struct mlx5_ifc_rmpc_bits ctx;
5226 };
5227
5228 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5229         u8         status[0x8];
5230         u8         reserved_at_8[0x18];
5231
5232         u8         syndrome[0x20];
5233
5234         u8         reserved_at_40[0x40];
5235 };
5236
5237 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5238         u8         reserved_at_0[0x14];
5239         u8         disable_uc_local_lb[0x1];
5240         u8         disable_mc_local_lb[0x1];
5241         u8         node_guid[0x1];
5242         u8         port_guid[0x1];
5243         u8         min_inline[0x1];
5244         u8         mtu[0x1];
5245         u8         change_event[0x1];
5246         u8         promisc[0x1];
5247         u8         permanent_address[0x1];
5248         u8         addresses_list[0x1];
5249         u8         roce_en[0x1];
5250         u8         reserved_at_1f[0x1];
5251 };
5252
5253 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5254         u8         opcode[0x10];
5255         u8         reserved_at_10[0x10];
5256
5257         u8         reserved_at_20[0x10];
5258         u8         op_mod[0x10];
5259
5260         u8         other_vport[0x1];
5261         u8         reserved_at_41[0xf];
5262         u8         vport_number[0x10];
5263
5264         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5265
5266         u8         reserved_at_80[0x780];
5267
5268         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5269 };
5270
5271 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5272         u8         status[0x8];
5273         u8         reserved_at_8[0x18];
5274
5275         u8         syndrome[0x20];
5276
5277         u8         reserved_at_40[0x40];
5278 };
5279
5280 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5281         u8         opcode[0x10];
5282         u8         reserved_at_10[0x10];
5283
5284         u8         reserved_at_20[0x10];
5285         u8         op_mod[0x10];
5286
5287         u8         other_vport[0x1];
5288         u8         reserved_at_41[0xb];
5289         u8         port_num[0x4];
5290         u8         vport_number[0x10];
5291
5292         u8         reserved_at_60[0x20];
5293
5294         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5295 };
5296
5297 struct mlx5_ifc_modify_cq_out_bits {
5298         u8         status[0x8];
5299         u8         reserved_at_8[0x18];
5300
5301         u8         syndrome[0x20];
5302
5303         u8         reserved_at_40[0x40];
5304 };
5305
5306 enum {
5307         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5308         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5309 };
5310
5311 struct mlx5_ifc_modify_cq_in_bits {
5312         u8         opcode[0x10];
5313         u8         reserved_at_10[0x10];
5314
5315         u8         reserved_at_20[0x10];
5316         u8         op_mod[0x10];
5317
5318         u8         reserved_at_40[0x8];
5319         u8         cqn[0x18];
5320
5321         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5322
5323         struct mlx5_ifc_cqc_bits cq_context;
5324
5325         u8         reserved_at_280[0x600];
5326
5327         u8         pas[0][0x40];
5328 };
5329
5330 struct mlx5_ifc_modify_cong_status_out_bits {
5331         u8         status[0x8];
5332         u8         reserved_at_8[0x18];
5333
5334         u8         syndrome[0x20];
5335
5336         u8         reserved_at_40[0x40];
5337 };
5338
5339 struct mlx5_ifc_modify_cong_status_in_bits {
5340         u8         opcode[0x10];
5341         u8         reserved_at_10[0x10];
5342
5343         u8         reserved_at_20[0x10];
5344         u8         op_mod[0x10];
5345
5346         u8         reserved_at_40[0x18];
5347         u8         priority[0x4];
5348         u8         cong_protocol[0x4];
5349
5350         u8         enable[0x1];
5351         u8         tag_enable[0x1];
5352         u8         reserved_at_62[0x1e];
5353 };
5354
5355 struct mlx5_ifc_modify_cong_params_out_bits {
5356         u8         status[0x8];
5357         u8         reserved_at_8[0x18];
5358
5359         u8         syndrome[0x20];
5360
5361         u8         reserved_at_40[0x40];
5362 };
5363
5364 struct mlx5_ifc_modify_cong_params_in_bits {
5365         u8         opcode[0x10];
5366         u8         reserved_at_10[0x10];
5367
5368         u8         reserved_at_20[0x10];
5369         u8         op_mod[0x10];
5370
5371         u8         reserved_at_40[0x1c];
5372         u8         cong_protocol[0x4];
5373
5374         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5375
5376         u8         reserved_at_80[0x80];
5377
5378         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5379 };
5380
5381 struct mlx5_ifc_manage_pages_out_bits {
5382         u8         status[0x8];
5383         u8         reserved_at_8[0x18];
5384
5385         u8         syndrome[0x20];
5386
5387         u8         output_num_entries[0x20];
5388
5389         u8         reserved_at_60[0x20];
5390
5391         u8         pas[0][0x40];
5392 };
5393
5394 enum {
5395         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5396         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5397         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5398 };
5399
5400 struct mlx5_ifc_manage_pages_in_bits {
5401         u8         opcode[0x10];
5402         u8         reserved_at_10[0x10];
5403
5404         u8         reserved_at_20[0x10];
5405         u8         op_mod[0x10];
5406
5407         u8         reserved_at_40[0x10];
5408         u8         function_id[0x10];
5409
5410         u8         input_num_entries[0x20];
5411
5412         u8         pas[0][0x40];
5413 };
5414
5415 struct mlx5_ifc_mad_ifc_out_bits {
5416         u8         status[0x8];
5417         u8         reserved_at_8[0x18];
5418
5419         u8         syndrome[0x20];
5420
5421         u8         reserved_at_40[0x40];
5422
5423         u8         response_mad_packet[256][0x8];
5424 };
5425
5426 struct mlx5_ifc_mad_ifc_in_bits {
5427         u8         opcode[0x10];
5428         u8         reserved_at_10[0x10];
5429
5430         u8         reserved_at_20[0x10];
5431         u8         op_mod[0x10];
5432
5433         u8         remote_lid[0x10];
5434         u8         reserved_at_50[0x8];
5435         u8         port[0x8];
5436
5437         u8         reserved_at_60[0x20];
5438
5439         u8         mad[256][0x8];
5440 };
5441
5442 struct mlx5_ifc_init_hca_out_bits {
5443         u8         status[0x8];
5444         u8         reserved_at_8[0x18];
5445
5446         u8         syndrome[0x20];
5447
5448         u8         reserved_at_40[0x40];
5449 };
5450
5451 struct mlx5_ifc_init_hca_in_bits {
5452         u8         opcode[0x10];
5453         u8         reserved_at_10[0x10];
5454
5455         u8         reserved_at_20[0x10];
5456         u8         op_mod[0x10];
5457
5458         u8         reserved_at_40[0x40];
5459 };
5460
5461 struct mlx5_ifc_init2rtr_qp_out_bits {
5462         u8         status[0x8];
5463         u8         reserved_at_8[0x18];
5464
5465         u8         syndrome[0x20];
5466
5467         u8         reserved_at_40[0x40];
5468 };
5469
5470 struct mlx5_ifc_init2rtr_qp_in_bits {
5471         u8         opcode[0x10];
5472         u8         reserved_at_10[0x10];
5473
5474         u8         reserved_at_20[0x10];
5475         u8         op_mod[0x10];
5476
5477         u8         reserved_at_40[0x8];
5478         u8         qpn[0x18];
5479
5480         u8         reserved_at_60[0x20];
5481
5482         u8         opt_param_mask[0x20];
5483
5484         u8         reserved_at_a0[0x20];
5485
5486         struct mlx5_ifc_qpc_bits qpc;
5487
5488         u8         reserved_at_800[0x80];
5489 };
5490
5491 struct mlx5_ifc_init2init_qp_out_bits {
5492         u8         status[0x8];
5493         u8         reserved_at_8[0x18];
5494
5495         u8         syndrome[0x20];
5496
5497         u8         reserved_at_40[0x40];
5498 };
5499
5500 struct mlx5_ifc_init2init_qp_in_bits {
5501         u8         opcode[0x10];
5502         u8         reserved_at_10[0x10];
5503
5504         u8         reserved_at_20[0x10];
5505         u8         op_mod[0x10];
5506
5507         u8         reserved_at_40[0x8];
5508         u8         qpn[0x18];
5509
5510         u8         reserved_at_60[0x20];
5511
5512         u8         opt_param_mask[0x20];
5513
5514         u8         reserved_at_a0[0x20];
5515
5516         struct mlx5_ifc_qpc_bits qpc;
5517
5518         u8         reserved_at_800[0x80];
5519 };
5520
5521 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5522         u8         status[0x8];
5523         u8         reserved_at_8[0x18];
5524
5525         u8         syndrome[0x20];
5526
5527         u8         reserved_at_40[0x40];
5528
5529         u8         packet_headers_log[128][0x8];
5530
5531         u8         packet_syndrome[64][0x8];
5532 };
5533
5534 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5535         u8         opcode[0x10];
5536         u8         reserved_at_10[0x10];
5537
5538         u8         reserved_at_20[0x10];
5539         u8         op_mod[0x10];
5540
5541         u8         reserved_at_40[0x40];
5542 };
5543
5544 struct mlx5_ifc_gen_eqe_in_bits {
5545         u8         opcode[0x10];
5546         u8         reserved_at_10[0x10];
5547
5548         u8         reserved_at_20[0x10];
5549         u8         op_mod[0x10];
5550
5551         u8         reserved_at_40[0x18];
5552         u8         eq_number[0x8];
5553
5554         u8         reserved_at_60[0x20];
5555
5556         u8         eqe[64][0x8];
5557 };
5558
5559 struct mlx5_ifc_gen_eq_out_bits {
5560         u8         status[0x8];
5561         u8         reserved_at_8[0x18];
5562
5563         u8         syndrome[0x20];
5564
5565         u8         reserved_at_40[0x40];
5566 };
5567
5568 struct mlx5_ifc_enable_hca_out_bits {
5569         u8         status[0x8];
5570         u8         reserved_at_8[0x18];
5571
5572         u8         syndrome[0x20];
5573
5574         u8         reserved_at_40[0x20];
5575 };
5576
5577 struct mlx5_ifc_enable_hca_in_bits {
5578         u8         opcode[0x10];
5579         u8         reserved_at_10[0x10];
5580
5581         u8         reserved_at_20[0x10];
5582         u8         op_mod[0x10];
5583
5584         u8         reserved_at_40[0x10];
5585         u8         function_id[0x10];
5586
5587         u8         reserved_at_60[0x20];
5588 };
5589
5590 struct mlx5_ifc_drain_dct_out_bits {
5591         u8         status[0x8];
5592         u8         reserved_at_8[0x18];
5593
5594         u8         syndrome[0x20];
5595
5596         u8         reserved_at_40[0x40];
5597 };
5598
5599 struct mlx5_ifc_drain_dct_in_bits {
5600         u8         opcode[0x10];
5601         u8         reserved_at_10[0x10];
5602
5603         u8         reserved_at_20[0x10];
5604         u8         op_mod[0x10];
5605
5606         u8         reserved_at_40[0x8];
5607         u8         dctn[0x18];
5608
5609         u8         reserved_at_60[0x20];
5610 };
5611
5612 struct mlx5_ifc_disable_hca_out_bits {
5613         u8         status[0x8];
5614         u8         reserved_at_8[0x18];
5615
5616         u8         syndrome[0x20];
5617
5618         u8         reserved_at_40[0x20];
5619 };
5620
5621 struct mlx5_ifc_disable_hca_in_bits {
5622         u8         opcode[0x10];
5623         u8         reserved_at_10[0x10];
5624
5625         u8         reserved_at_20[0x10];
5626         u8         op_mod[0x10];
5627
5628         u8         reserved_at_40[0x10];
5629         u8         function_id[0x10];
5630
5631         u8         reserved_at_60[0x20];
5632 };
5633
5634 struct mlx5_ifc_detach_from_mcg_out_bits {
5635         u8         status[0x8];
5636         u8         reserved_at_8[0x18];
5637
5638         u8         syndrome[0x20];
5639
5640         u8         reserved_at_40[0x40];
5641 };
5642
5643 struct mlx5_ifc_detach_from_mcg_in_bits {
5644         u8         opcode[0x10];
5645         u8         reserved_at_10[0x10];
5646
5647         u8         reserved_at_20[0x10];
5648         u8         op_mod[0x10];
5649
5650         u8         reserved_at_40[0x8];
5651         u8         qpn[0x18];
5652
5653         u8         reserved_at_60[0x20];
5654
5655         u8         multicast_gid[16][0x8];
5656 };
5657
5658 struct mlx5_ifc_destroy_xrq_out_bits {
5659         u8         status[0x8];
5660         u8         reserved_at_8[0x18];
5661
5662         u8         syndrome[0x20];
5663
5664         u8         reserved_at_40[0x40];
5665 };
5666
5667 struct mlx5_ifc_destroy_xrq_in_bits {
5668         u8         opcode[0x10];
5669         u8         reserved_at_10[0x10];
5670
5671         u8         reserved_at_20[0x10];
5672         u8         op_mod[0x10];
5673
5674         u8         reserved_at_40[0x8];
5675         u8         xrqn[0x18];
5676
5677         u8         reserved_at_60[0x20];
5678 };
5679
5680 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5681         u8         status[0x8];
5682         u8         reserved_at_8[0x18];
5683
5684         u8         syndrome[0x20];
5685
5686         u8         reserved_at_40[0x40];
5687 };
5688
5689 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5690         u8         opcode[0x10];
5691         u8         reserved_at_10[0x10];
5692
5693         u8         reserved_at_20[0x10];
5694         u8         op_mod[0x10];
5695
5696         u8         reserved_at_40[0x8];
5697         u8         xrc_srqn[0x18];
5698
5699         u8         reserved_at_60[0x20];
5700 };
5701
5702 struct mlx5_ifc_destroy_tis_out_bits {
5703         u8         status[0x8];
5704         u8         reserved_at_8[0x18];
5705
5706         u8         syndrome[0x20];
5707
5708         u8         reserved_at_40[0x40];
5709 };
5710
5711 struct mlx5_ifc_destroy_tis_in_bits {
5712         u8         opcode[0x10];
5713         u8         reserved_at_10[0x10];
5714
5715         u8         reserved_at_20[0x10];
5716         u8         op_mod[0x10];
5717
5718         u8         reserved_at_40[0x8];
5719         u8         tisn[0x18];
5720
5721         u8         reserved_at_60[0x20];
5722 };
5723
5724 struct mlx5_ifc_destroy_tir_out_bits {
5725         u8         status[0x8];
5726         u8         reserved_at_8[0x18];
5727
5728         u8         syndrome[0x20];
5729
5730         u8         reserved_at_40[0x40];
5731 };
5732
5733 struct mlx5_ifc_destroy_tir_in_bits {
5734         u8         opcode[0x10];
5735         u8         reserved_at_10[0x10];
5736
5737         u8         reserved_at_20[0x10];
5738         u8         op_mod[0x10];
5739
5740         u8         reserved_at_40[0x8];
5741         u8         tirn[0x18];
5742
5743         u8         reserved_at_60[0x20];
5744 };
5745
5746 struct mlx5_ifc_destroy_srq_out_bits {
5747         u8         status[0x8];
5748         u8         reserved_at_8[0x18];
5749
5750         u8         syndrome[0x20];
5751
5752         u8         reserved_at_40[0x40];
5753 };
5754
5755 struct mlx5_ifc_destroy_srq_in_bits {
5756         u8         opcode[0x10];
5757         u8         reserved_at_10[0x10];
5758
5759         u8         reserved_at_20[0x10];
5760         u8         op_mod[0x10];
5761
5762         u8         reserved_at_40[0x8];
5763         u8         srqn[0x18];
5764
5765         u8         reserved_at_60[0x20];
5766 };
5767
5768 struct mlx5_ifc_destroy_sq_out_bits {
5769         u8         status[0x8];
5770         u8         reserved_at_8[0x18];
5771
5772         u8         syndrome[0x20];
5773
5774         u8         reserved_at_40[0x40];
5775 };
5776
5777 struct mlx5_ifc_destroy_sq_in_bits {
5778         u8         opcode[0x10];
5779         u8         reserved_at_10[0x10];
5780
5781         u8         reserved_at_20[0x10];
5782         u8         op_mod[0x10];
5783
5784         u8         reserved_at_40[0x8];
5785         u8         sqn[0x18];
5786
5787         u8         reserved_at_60[0x20];
5788 };
5789
5790 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5791         u8         status[0x8];
5792         u8         reserved_at_8[0x18];
5793
5794         u8         syndrome[0x20];
5795
5796         u8         reserved_at_40[0x1c0];
5797 };
5798
5799 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5800         u8         opcode[0x10];
5801         u8         reserved_at_10[0x10];
5802
5803         u8         reserved_at_20[0x10];
5804         u8         op_mod[0x10];
5805
5806         u8         scheduling_hierarchy[0x8];
5807         u8         reserved_at_48[0x18];
5808
5809         u8         scheduling_element_id[0x20];
5810
5811         u8         reserved_at_80[0x180];
5812 };
5813
5814 struct mlx5_ifc_destroy_rqt_out_bits {
5815         u8         status[0x8];
5816         u8         reserved_at_8[0x18];
5817
5818         u8         syndrome[0x20];
5819
5820         u8         reserved_at_40[0x40];
5821 };
5822
5823 struct mlx5_ifc_destroy_rqt_in_bits {
5824         u8         opcode[0x10];
5825         u8         reserved_at_10[0x10];
5826
5827         u8         reserved_at_20[0x10];
5828         u8         op_mod[0x10];
5829
5830         u8         reserved_at_40[0x8];
5831         u8         rqtn[0x18];
5832
5833         u8         reserved_at_60[0x20];
5834 };
5835
5836 struct mlx5_ifc_destroy_rq_out_bits {
5837         u8         status[0x8];
5838         u8         reserved_at_8[0x18];
5839
5840         u8         syndrome[0x20];
5841
5842         u8         reserved_at_40[0x40];
5843 };
5844
5845 struct mlx5_ifc_destroy_rq_in_bits {
5846         u8         opcode[0x10];
5847         u8         reserved_at_10[0x10];
5848
5849         u8         reserved_at_20[0x10];
5850         u8         op_mod[0x10];
5851
5852         u8         reserved_at_40[0x8];
5853         u8         rqn[0x18];
5854
5855         u8         reserved_at_60[0x20];
5856 };
5857
5858 struct mlx5_ifc_set_delay_drop_params_in_bits {
5859         u8         opcode[0x10];
5860         u8         reserved_at_10[0x10];
5861
5862         u8         reserved_at_20[0x10];
5863         u8         op_mod[0x10];
5864
5865         u8         reserved_at_40[0x20];
5866
5867         u8         reserved_at_60[0x10];
5868         u8         delay_drop_timeout[0x10];
5869 };
5870
5871 struct mlx5_ifc_set_delay_drop_params_out_bits {
5872         u8         status[0x8];
5873         u8         reserved_at_8[0x18];
5874
5875         u8         syndrome[0x20];
5876
5877         u8         reserved_at_40[0x40];
5878 };
5879
5880 struct mlx5_ifc_destroy_rmp_out_bits {
5881         u8         status[0x8];
5882         u8         reserved_at_8[0x18];
5883
5884         u8         syndrome[0x20];
5885
5886         u8         reserved_at_40[0x40];
5887 };
5888
5889 struct mlx5_ifc_destroy_rmp_in_bits {
5890         u8         opcode[0x10];
5891         u8         reserved_at_10[0x10];
5892
5893         u8         reserved_at_20[0x10];
5894         u8         op_mod[0x10];
5895
5896         u8         reserved_at_40[0x8];
5897         u8         rmpn[0x18];
5898
5899         u8         reserved_at_60[0x20];
5900 };
5901
5902 struct mlx5_ifc_destroy_qp_out_bits {
5903         u8         status[0x8];
5904         u8         reserved_at_8[0x18];
5905
5906         u8         syndrome[0x20];
5907
5908         u8         reserved_at_40[0x40];
5909 };
5910
5911 struct mlx5_ifc_destroy_qp_in_bits {
5912         u8         opcode[0x10];
5913         u8         reserved_at_10[0x10];
5914
5915         u8         reserved_at_20[0x10];
5916         u8         op_mod[0x10];
5917
5918         u8         reserved_at_40[0x8];
5919         u8         qpn[0x18];
5920
5921         u8         reserved_at_60[0x20];
5922 };
5923
5924 struct mlx5_ifc_destroy_psv_out_bits {
5925         u8         status[0x8];
5926         u8         reserved_at_8[0x18];
5927
5928         u8         syndrome[0x20];
5929
5930         u8         reserved_at_40[0x40];
5931 };
5932
5933 struct mlx5_ifc_destroy_psv_in_bits {
5934         u8         opcode[0x10];
5935         u8         reserved_at_10[0x10];
5936
5937         u8         reserved_at_20[0x10];
5938         u8         op_mod[0x10];
5939
5940         u8         reserved_at_40[0x8];
5941         u8         psvn[0x18];
5942
5943         u8         reserved_at_60[0x20];
5944 };
5945
5946 struct mlx5_ifc_destroy_mkey_out_bits {
5947         u8         status[0x8];
5948         u8         reserved_at_8[0x18];
5949
5950         u8         syndrome[0x20];
5951
5952         u8         reserved_at_40[0x40];
5953 };
5954
5955 struct mlx5_ifc_destroy_mkey_in_bits {
5956         u8         opcode[0x10];
5957         u8         reserved_at_10[0x10];
5958
5959         u8         reserved_at_20[0x10];
5960         u8         op_mod[0x10];
5961
5962         u8         reserved_at_40[0x8];
5963         u8         mkey_index[0x18];
5964
5965         u8         reserved_at_60[0x20];
5966 };
5967
5968 struct mlx5_ifc_destroy_flow_table_out_bits {
5969         u8         status[0x8];
5970         u8         reserved_at_8[0x18];
5971
5972         u8         syndrome[0x20];
5973
5974         u8         reserved_at_40[0x40];
5975 };
5976
5977 struct mlx5_ifc_destroy_flow_table_in_bits {
5978         u8         opcode[0x10];
5979         u8         reserved_at_10[0x10];
5980
5981         u8         reserved_at_20[0x10];
5982         u8         op_mod[0x10];
5983
5984         u8         other_vport[0x1];
5985         u8         reserved_at_41[0xf];
5986         u8         vport_number[0x10];
5987
5988         u8         reserved_at_60[0x20];
5989
5990         u8         table_type[0x8];
5991         u8         reserved_at_88[0x18];
5992
5993         u8         reserved_at_a0[0x8];
5994         u8         table_id[0x18];
5995
5996         u8         reserved_at_c0[0x140];
5997 };
5998
5999 struct mlx5_ifc_destroy_flow_group_out_bits {
6000         u8         status[0x8];
6001         u8         reserved_at_8[0x18];
6002
6003         u8         syndrome[0x20];
6004
6005         u8         reserved_at_40[0x40];
6006 };
6007
6008 struct mlx5_ifc_destroy_flow_group_in_bits {
6009         u8         opcode[0x10];
6010         u8         reserved_at_10[0x10];
6011
6012         u8         reserved_at_20[0x10];
6013         u8         op_mod[0x10];
6014
6015         u8         other_vport[0x1];
6016         u8         reserved_at_41[0xf];
6017         u8         vport_number[0x10];
6018
6019         u8         reserved_at_60[0x20];
6020
6021         u8         table_type[0x8];
6022         u8         reserved_at_88[0x18];
6023
6024         u8         reserved_at_a0[0x8];
6025         u8         table_id[0x18];
6026
6027         u8         group_id[0x20];
6028
6029         u8         reserved_at_e0[0x120];
6030 };
6031
6032 struct mlx5_ifc_destroy_eq_out_bits {
6033         u8         status[0x8];
6034         u8         reserved_at_8[0x18];
6035
6036         u8         syndrome[0x20];
6037
6038         u8         reserved_at_40[0x40];
6039 };
6040
6041 struct mlx5_ifc_destroy_eq_in_bits {
6042         u8         opcode[0x10];
6043         u8         reserved_at_10[0x10];
6044
6045         u8         reserved_at_20[0x10];
6046         u8         op_mod[0x10];
6047
6048         u8         reserved_at_40[0x18];
6049         u8         eq_number[0x8];
6050
6051         u8         reserved_at_60[0x20];
6052 };
6053
6054 struct mlx5_ifc_destroy_dct_out_bits {
6055         u8         status[0x8];
6056         u8         reserved_at_8[0x18];
6057
6058         u8         syndrome[0x20];
6059
6060         u8         reserved_at_40[0x40];
6061 };
6062
6063 struct mlx5_ifc_destroy_dct_in_bits {
6064         u8         opcode[0x10];
6065         u8         reserved_at_10[0x10];
6066
6067         u8         reserved_at_20[0x10];
6068         u8         op_mod[0x10];
6069
6070         u8         reserved_at_40[0x8];
6071         u8         dctn[0x18];
6072
6073         u8         reserved_at_60[0x20];
6074 };
6075
6076 struct mlx5_ifc_destroy_cq_out_bits {
6077         u8         status[0x8];
6078         u8         reserved_at_8[0x18];
6079
6080         u8         syndrome[0x20];
6081
6082         u8         reserved_at_40[0x40];
6083 };
6084
6085 struct mlx5_ifc_destroy_cq_in_bits {
6086         u8         opcode[0x10];
6087         u8         reserved_at_10[0x10];
6088
6089         u8         reserved_at_20[0x10];
6090         u8         op_mod[0x10];
6091
6092         u8         reserved_at_40[0x8];
6093         u8         cqn[0x18];
6094
6095         u8         reserved_at_60[0x20];
6096 };
6097
6098 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6099         u8         status[0x8];
6100         u8         reserved_at_8[0x18];
6101
6102         u8         syndrome[0x20];
6103
6104         u8         reserved_at_40[0x40];
6105 };
6106
6107 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6108         u8         opcode[0x10];
6109         u8         reserved_at_10[0x10];
6110
6111         u8         reserved_at_20[0x10];
6112         u8         op_mod[0x10];
6113
6114         u8         reserved_at_40[0x20];
6115
6116         u8         reserved_at_60[0x10];
6117         u8         vxlan_udp_port[0x10];
6118 };
6119
6120 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6121         u8         status[0x8];
6122         u8         reserved_at_8[0x18];
6123
6124         u8         syndrome[0x20];
6125
6126         u8         reserved_at_40[0x40];
6127 };
6128
6129 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6130         u8         opcode[0x10];
6131         u8         reserved_at_10[0x10];
6132
6133         u8         reserved_at_20[0x10];
6134         u8         op_mod[0x10];
6135
6136         u8         reserved_at_40[0x60];
6137
6138         u8         reserved_at_a0[0x8];
6139         u8         table_index[0x18];
6140
6141         u8         reserved_at_c0[0x140];
6142 };
6143
6144 struct mlx5_ifc_delete_fte_out_bits {
6145         u8         status[0x8];
6146         u8         reserved_at_8[0x18];
6147
6148         u8         syndrome[0x20];
6149
6150         u8         reserved_at_40[0x40];
6151 };
6152
6153 struct mlx5_ifc_delete_fte_in_bits {
6154         u8         opcode[0x10];
6155         u8         reserved_at_10[0x10];
6156
6157         u8         reserved_at_20[0x10];
6158         u8         op_mod[0x10];
6159
6160         u8         other_vport[0x1];
6161         u8         reserved_at_41[0xf];
6162         u8         vport_number[0x10];
6163
6164         u8         reserved_at_60[0x20];
6165
6166         u8         table_type[0x8];
6167         u8         reserved_at_88[0x18];
6168
6169         u8         reserved_at_a0[0x8];
6170         u8         table_id[0x18];
6171
6172         u8         reserved_at_c0[0x40];
6173
6174         u8         flow_index[0x20];
6175
6176         u8         reserved_at_120[0xe0];
6177 };
6178
6179 struct mlx5_ifc_dealloc_xrcd_out_bits {
6180         u8         status[0x8];
6181         u8         reserved_at_8[0x18];
6182
6183         u8         syndrome[0x20];
6184
6185         u8         reserved_at_40[0x40];
6186 };
6187
6188 struct mlx5_ifc_dealloc_xrcd_in_bits {
6189         u8         opcode[0x10];
6190         u8         reserved_at_10[0x10];
6191
6192         u8         reserved_at_20[0x10];
6193         u8         op_mod[0x10];
6194
6195         u8         reserved_at_40[0x8];
6196         u8         xrcd[0x18];
6197
6198         u8         reserved_at_60[0x20];
6199 };
6200
6201 struct mlx5_ifc_dealloc_uar_out_bits {
6202         u8         status[0x8];
6203         u8         reserved_at_8[0x18];
6204
6205         u8         syndrome[0x20];
6206
6207         u8         reserved_at_40[0x40];
6208 };
6209
6210 struct mlx5_ifc_dealloc_uar_in_bits {
6211         u8         opcode[0x10];
6212         u8         reserved_at_10[0x10];
6213
6214         u8         reserved_at_20[0x10];
6215         u8         op_mod[0x10];
6216
6217         u8         reserved_at_40[0x8];
6218         u8         uar[0x18];
6219
6220         u8         reserved_at_60[0x20];
6221 };
6222
6223 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6224         u8         status[0x8];
6225         u8         reserved_at_8[0x18];
6226
6227         u8         syndrome[0x20];
6228
6229         u8         reserved_at_40[0x40];
6230 };
6231
6232 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6233         u8         opcode[0x10];
6234         u8         reserved_at_10[0x10];
6235
6236         u8         reserved_at_20[0x10];
6237         u8         op_mod[0x10];
6238
6239         u8         reserved_at_40[0x8];
6240         u8         transport_domain[0x18];
6241
6242         u8         reserved_at_60[0x20];
6243 };
6244
6245 struct mlx5_ifc_dealloc_q_counter_out_bits {
6246         u8         status[0x8];
6247         u8         reserved_at_8[0x18];
6248
6249         u8         syndrome[0x20];
6250
6251         u8         reserved_at_40[0x40];
6252 };
6253
6254 struct mlx5_ifc_dealloc_q_counter_in_bits {
6255         u8         opcode[0x10];
6256         u8         reserved_at_10[0x10];
6257
6258         u8         reserved_at_20[0x10];
6259         u8         op_mod[0x10];
6260
6261         u8         reserved_at_40[0x18];
6262         u8         counter_set_id[0x8];
6263
6264         u8         reserved_at_60[0x20];
6265 };
6266
6267 struct mlx5_ifc_dealloc_pd_out_bits {
6268         u8         status[0x8];
6269         u8         reserved_at_8[0x18];
6270
6271         u8         syndrome[0x20];
6272
6273         u8         reserved_at_40[0x40];
6274 };
6275
6276 struct mlx5_ifc_dealloc_pd_in_bits {
6277         u8         opcode[0x10];
6278         u8         reserved_at_10[0x10];
6279
6280         u8         reserved_at_20[0x10];
6281         u8         op_mod[0x10];
6282
6283         u8         reserved_at_40[0x8];
6284         u8         pd[0x18];
6285
6286         u8         reserved_at_60[0x20];
6287 };
6288
6289 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6290         u8         status[0x8];
6291         u8         reserved_at_8[0x18];
6292
6293         u8         syndrome[0x20];
6294
6295         u8         reserved_at_40[0x40];
6296 };
6297
6298 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6299         u8         opcode[0x10];
6300         u8         reserved_at_10[0x10];
6301
6302         u8         reserved_at_20[0x10];
6303         u8         op_mod[0x10];
6304
6305         u8         reserved_at_40[0x10];
6306         u8         flow_counter_id[0x10];
6307
6308         u8         reserved_at_60[0x20];
6309 };
6310
6311 struct mlx5_ifc_create_xrq_out_bits {
6312         u8         status[0x8];
6313         u8         reserved_at_8[0x18];
6314
6315         u8         syndrome[0x20];
6316
6317         u8         reserved_at_40[0x8];
6318         u8         xrqn[0x18];
6319
6320         u8         reserved_at_60[0x20];
6321 };
6322
6323 struct mlx5_ifc_create_xrq_in_bits {
6324         u8         opcode[0x10];
6325         u8         reserved_at_10[0x10];
6326
6327         u8         reserved_at_20[0x10];
6328         u8         op_mod[0x10];
6329
6330         u8         reserved_at_40[0x40];
6331
6332         struct mlx5_ifc_xrqc_bits xrq_context;
6333 };
6334
6335 struct mlx5_ifc_create_xrc_srq_out_bits {
6336         u8         status[0x8];
6337         u8         reserved_at_8[0x18];
6338
6339         u8         syndrome[0x20];
6340
6341         u8         reserved_at_40[0x8];
6342         u8         xrc_srqn[0x18];
6343
6344         u8         reserved_at_60[0x20];
6345 };
6346
6347 struct mlx5_ifc_create_xrc_srq_in_bits {
6348         u8         opcode[0x10];
6349         u8         reserved_at_10[0x10];
6350
6351         u8         reserved_at_20[0x10];
6352         u8         op_mod[0x10];
6353
6354         u8         reserved_at_40[0x40];
6355
6356         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6357
6358         u8         reserved_at_280[0x600];
6359
6360         u8         pas[0][0x40];
6361 };
6362
6363 struct mlx5_ifc_create_tis_out_bits {
6364         u8         status[0x8];
6365         u8         reserved_at_8[0x18];
6366
6367         u8         syndrome[0x20];
6368
6369         u8         reserved_at_40[0x8];
6370         u8         tisn[0x18];
6371
6372         u8         reserved_at_60[0x20];
6373 };
6374
6375 struct mlx5_ifc_create_tis_in_bits {
6376         u8         opcode[0x10];
6377         u8         reserved_at_10[0x10];
6378
6379         u8         reserved_at_20[0x10];
6380         u8         op_mod[0x10];
6381
6382         u8         reserved_at_40[0xc0];
6383
6384         struct mlx5_ifc_tisc_bits ctx;
6385 };
6386
6387 struct mlx5_ifc_create_tir_out_bits {
6388         u8         status[0x8];
6389         u8         reserved_at_8[0x18];
6390
6391         u8         syndrome[0x20];
6392
6393         u8         reserved_at_40[0x8];
6394         u8         tirn[0x18];
6395
6396         u8         reserved_at_60[0x20];
6397 };
6398
6399 struct mlx5_ifc_create_tir_in_bits {
6400         u8         opcode[0x10];
6401         u8         reserved_at_10[0x10];
6402
6403         u8         reserved_at_20[0x10];
6404         u8         op_mod[0x10];
6405
6406         u8         reserved_at_40[0xc0];
6407
6408         struct mlx5_ifc_tirc_bits ctx;
6409 };
6410
6411 struct mlx5_ifc_create_srq_out_bits {
6412         u8         status[0x8];
6413         u8         reserved_at_8[0x18];
6414
6415         u8         syndrome[0x20];
6416
6417         u8         reserved_at_40[0x8];
6418         u8         srqn[0x18];
6419
6420         u8         reserved_at_60[0x20];
6421 };
6422
6423 struct mlx5_ifc_create_srq_in_bits {
6424         u8         opcode[0x10];
6425         u8         reserved_at_10[0x10];
6426
6427         u8         reserved_at_20[0x10];
6428         u8         op_mod[0x10];
6429
6430         u8         reserved_at_40[0x40];
6431
6432         struct mlx5_ifc_srqc_bits srq_context_entry;
6433
6434         u8         reserved_at_280[0x600];
6435
6436         u8         pas[0][0x40];
6437 };
6438
6439 struct mlx5_ifc_create_sq_out_bits {
6440         u8         status[0x8];
6441         u8         reserved_at_8[0x18];
6442
6443         u8         syndrome[0x20];
6444
6445         u8         reserved_at_40[0x8];
6446         u8         sqn[0x18];
6447
6448         u8         reserved_at_60[0x20];
6449 };
6450
6451 struct mlx5_ifc_create_sq_in_bits {
6452         u8         opcode[0x10];
6453         u8         reserved_at_10[0x10];
6454
6455         u8         reserved_at_20[0x10];
6456         u8         op_mod[0x10];
6457
6458         u8         reserved_at_40[0xc0];
6459
6460         struct mlx5_ifc_sqc_bits ctx;
6461 };
6462
6463 struct mlx5_ifc_create_scheduling_element_out_bits {
6464         u8         status[0x8];
6465         u8         reserved_at_8[0x18];
6466
6467         u8         syndrome[0x20];
6468
6469         u8         reserved_at_40[0x40];
6470
6471         u8         scheduling_element_id[0x20];
6472
6473         u8         reserved_at_a0[0x160];
6474 };
6475
6476 struct mlx5_ifc_create_scheduling_element_in_bits {
6477         u8         opcode[0x10];
6478         u8         reserved_at_10[0x10];
6479
6480         u8         reserved_at_20[0x10];
6481         u8         op_mod[0x10];
6482
6483         u8         scheduling_hierarchy[0x8];
6484         u8         reserved_at_48[0x18];
6485
6486         u8         reserved_at_60[0xa0];
6487
6488         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6489
6490         u8         reserved_at_300[0x100];
6491 };
6492
6493 struct mlx5_ifc_create_rqt_out_bits {
6494         u8         status[0x8];
6495         u8         reserved_at_8[0x18];
6496
6497         u8         syndrome[0x20];
6498
6499         u8         reserved_at_40[0x8];
6500         u8         rqtn[0x18];
6501
6502         u8         reserved_at_60[0x20];
6503 };
6504
6505 struct mlx5_ifc_create_rqt_in_bits {
6506         u8         opcode[0x10];
6507         u8         reserved_at_10[0x10];
6508
6509         u8         reserved_at_20[0x10];
6510         u8         op_mod[0x10];
6511
6512         u8         reserved_at_40[0xc0];
6513
6514         struct mlx5_ifc_rqtc_bits rqt_context;
6515 };
6516
6517 struct mlx5_ifc_create_rq_out_bits {
6518         u8         status[0x8];
6519         u8         reserved_at_8[0x18];
6520
6521         u8         syndrome[0x20];
6522
6523         u8         reserved_at_40[0x8];
6524         u8         rqn[0x18];
6525
6526         u8         reserved_at_60[0x20];
6527 };
6528
6529 struct mlx5_ifc_create_rq_in_bits {
6530         u8         opcode[0x10];
6531         u8         reserved_at_10[0x10];
6532
6533         u8         reserved_at_20[0x10];
6534         u8         op_mod[0x10];
6535
6536         u8         reserved_at_40[0xc0];
6537
6538         struct mlx5_ifc_rqc_bits ctx;
6539 };
6540
6541 struct mlx5_ifc_create_rmp_out_bits {
6542         u8         status[0x8];
6543         u8         reserved_at_8[0x18];
6544
6545         u8         syndrome[0x20];
6546
6547         u8         reserved_at_40[0x8];
6548         u8         rmpn[0x18];
6549
6550         u8         reserved_at_60[0x20];
6551 };
6552
6553 struct mlx5_ifc_create_rmp_in_bits {
6554         u8         opcode[0x10];
6555         u8         reserved_at_10[0x10];
6556
6557         u8         reserved_at_20[0x10];
6558         u8         op_mod[0x10];
6559
6560         u8         reserved_at_40[0xc0];
6561
6562         struct mlx5_ifc_rmpc_bits ctx;
6563 };
6564
6565 struct mlx5_ifc_create_qp_out_bits {
6566         u8         status[0x8];
6567         u8         reserved_at_8[0x18];
6568
6569         u8         syndrome[0x20];
6570
6571         u8         reserved_at_40[0x8];
6572         u8         qpn[0x18];
6573
6574         u8         reserved_at_60[0x20];
6575 };
6576
6577 struct mlx5_ifc_create_qp_in_bits {
6578         u8         opcode[0x10];
6579         u8         reserved_at_10[0x10];
6580
6581         u8         reserved_at_20[0x10];
6582         u8         op_mod[0x10];
6583
6584         u8         reserved_at_40[0x40];
6585
6586         u8         opt_param_mask[0x20];
6587
6588         u8         reserved_at_a0[0x20];
6589
6590         struct mlx5_ifc_qpc_bits qpc;
6591
6592         u8         reserved_at_800[0x80];
6593
6594         u8         pas[0][0x40];
6595 };
6596
6597 struct mlx5_ifc_create_psv_out_bits {
6598         u8         status[0x8];
6599         u8         reserved_at_8[0x18];
6600
6601         u8         syndrome[0x20];
6602
6603         u8         reserved_at_40[0x40];
6604
6605         u8         reserved_at_80[0x8];
6606         u8         psv0_index[0x18];
6607
6608         u8         reserved_at_a0[0x8];
6609         u8         psv1_index[0x18];
6610
6611         u8         reserved_at_c0[0x8];
6612         u8         psv2_index[0x18];
6613
6614         u8         reserved_at_e0[0x8];
6615         u8         psv3_index[0x18];
6616 };
6617
6618 struct mlx5_ifc_create_psv_in_bits {
6619         u8         opcode[0x10];
6620         u8         reserved_at_10[0x10];
6621
6622         u8         reserved_at_20[0x10];
6623         u8         op_mod[0x10];
6624
6625         u8         num_psv[0x4];
6626         u8         reserved_at_44[0x4];
6627         u8         pd[0x18];
6628
6629         u8         reserved_at_60[0x20];
6630 };
6631
6632 struct mlx5_ifc_create_mkey_out_bits {
6633         u8         status[0x8];
6634         u8         reserved_at_8[0x18];
6635
6636         u8         syndrome[0x20];
6637
6638         u8         reserved_at_40[0x8];
6639         u8         mkey_index[0x18];
6640
6641         u8         reserved_at_60[0x20];
6642 };
6643
6644 struct mlx5_ifc_create_mkey_in_bits {
6645         u8         opcode[0x10];
6646         u8         reserved_at_10[0x10];
6647
6648         u8         reserved_at_20[0x10];
6649         u8         op_mod[0x10];
6650
6651         u8         reserved_at_40[0x20];
6652
6653         u8         pg_access[0x1];
6654         u8         reserved_at_61[0x1f];
6655
6656         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6657
6658         u8         reserved_at_280[0x80];
6659
6660         u8         translations_octword_actual_size[0x20];
6661
6662         u8         reserved_at_320[0x560];
6663
6664         u8         klm_pas_mtt[0][0x20];
6665 };
6666
6667 struct mlx5_ifc_create_flow_table_out_bits {
6668         u8         status[0x8];
6669         u8         reserved_at_8[0x18];
6670
6671         u8         syndrome[0x20];
6672
6673         u8         reserved_at_40[0x8];
6674         u8         table_id[0x18];
6675
6676         u8         reserved_at_60[0x20];
6677 };
6678
6679 struct mlx5_ifc_flow_table_context_bits {
6680         u8         encap_en[0x1];
6681         u8         decap_en[0x1];
6682         u8         reserved_at_2[0x2];
6683         u8         table_miss_action[0x4];
6684         u8         level[0x8];
6685         u8         reserved_at_10[0x8];
6686         u8         log_size[0x8];
6687
6688         u8         reserved_at_20[0x8];
6689         u8         table_miss_id[0x18];
6690
6691         u8         reserved_at_40[0x8];
6692         u8         lag_master_next_table_id[0x18];
6693
6694         u8         reserved_at_60[0xe0];
6695 };
6696
6697 struct mlx5_ifc_create_flow_table_in_bits {
6698         u8         opcode[0x10];
6699         u8         reserved_at_10[0x10];
6700
6701         u8         reserved_at_20[0x10];
6702         u8         op_mod[0x10];
6703
6704         u8         other_vport[0x1];
6705         u8         reserved_at_41[0xf];
6706         u8         vport_number[0x10];
6707
6708         u8         reserved_at_60[0x20];
6709
6710         u8         table_type[0x8];
6711         u8         reserved_at_88[0x18];
6712
6713         u8         reserved_at_a0[0x20];
6714
6715         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6716 };
6717
6718 struct mlx5_ifc_create_flow_group_out_bits {
6719         u8         status[0x8];
6720         u8         reserved_at_8[0x18];
6721
6722         u8         syndrome[0x20];
6723
6724         u8         reserved_at_40[0x8];
6725         u8         group_id[0x18];
6726
6727         u8         reserved_at_60[0x20];
6728 };
6729
6730 enum {
6731         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6732         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6733         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6734 };
6735
6736 struct mlx5_ifc_create_flow_group_in_bits {
6737         u8         opcode[0x10];
6738         u8         reserved_at_10[0x10];
6739
6740         u8         reserved_at_20[0x10];
6741         u8         op_mod[0x10];
6742
6743         u8         other_vport[0x1];
6744         u8         reserved_at_41[0xf];
6745         u8         vport_number[0x10];
6746
6747         u8         reserved_at_60[0x20];
6748
6749         u8         table_type[0x8];
6750         u8         reserved_at_88[0x18];
6751
6752         u8         reserved_at_a0[0x8];
6753         u8         table_id[0x18];
6754
6755         u8         reserved_at_c0[0x20];
6756
6757         u8         start_flow_index[0x20];
6758
6759         u8         reserved_at_100[0x20];
6760
6761         u8         end_flow_index[0x20];
6762
6763         u8         reserved_at_140[0xa0];
6764
6765         u8         reserved_at_1e0[0x18];
6766         u8         match_criteria_enable[0x8];
6767
6768         struct mlx5_ifc_fte_match_param_bits match_criteria;
6769
6770         u8         reserved_at_1200[0xe00];
6771 };
6772
6773 struct mlx5_ifc_create_eq_out_bits {
6774         u8         status[0x8];
6775         u8         reserved_at_8[0x18];
6776
6777         u8         syndrome[0x20];
6778
6779         u8         reserved_at_40[0x18];
6780         u8         eq_number[0x8];
6781
6782         u8         reserved_at_60[0x20];
6783 };
6784
6785 struct mlx5_ifc_create_eq_in_bits {
6786         u8         opcode[0x10];
6787         u8         reserved_at_10[0x10];
6788
6789         u8         reserved_at_20[0x10];
6790         u8         op_mod[0x10];
6791
6792         u8         reserved_at_40[0x40];
6793
6794         struct mlx5_ifc_eqc_bits eq_context_entry;
6795
6796         u8         reserved_at_280[0x40];
6797
6798         u8         event_bitmask[0x40];
6799
6800         u8         reserved_at_300[0x580];
6801
6802         u8         pas[0][0x40];
6803 };
6804
6805 struct mlx5_ifc_create_dct_out_bits {
6806         u8         status[0x8];
6807         u8         reserved_at_8[0x18];
6808
6809         u8         syndrome[0x20];
6810
6811         u8         reserved_at_40[0x8];
6812         u8         dctn[0x18];
6813
6814         u8         reserved_at_60[0x20];
6815 };
6816
6817 struct mlx5_ifc_create_dct_in_bits {
6818         u8         opcode[0x10];
6819         u8         reserved_at_10[0x10];
6820
6821         u8         reserved_at_20[0x10];
6822         u8         op_mod[0x10];
6823
6824         u8         reserved_at_40[0x40];
6825
6826         struct mlx5_ifc_dctc_bits dct_context_entry;
6827
6828         u8         reserved_at_280[0x180];
6829 };
6830
6831 struct mlx5_ifc_create_cq_out_bits {
6832         u8         status[0x8];
6833         u8         reserved_at_8[0x18];
6834
6835         u8         syndrome[0x20];
6836
6837         u8         reserved_at_40[0x8];
6838         u8         cqn[0x18];
6839
6840         u8         reserved_at_60[0x20];
6841 };
6842
6843 struct mlx5_ifc_create_cq_in_bits {
6844         u8         opcode[0x10];
6845         u8         reserved_at_10[0x10];
6846
6847         u8         reserved_at_20[0x10];
6848         u8         op_mod[0x10];
6849
6850         u8         reserved_at_40[0x40];
6851
6852         struct mlx5_ifc_cqc_bits cq_context;
6853
6854         u8         reserved_at_280[0x600];
6855
6856         u8         pas[0][0x40];
6857 };
6858
6859 struct mlx5_ifc_config_int_moderation_out_bits {
6860         u8         status[0x8];
6861         u8         reserved_at_8[0x18];
6862
6863         u8         syndrome[0x20];
6864
6865         u8         reserved_at_40[0x4];
6866         u8         min_delay[0xc];
6867         u8         int_vector[0x10];
6868
6869         u8         reserved_at_60[0x20];
6870 };
6871
6872 enum {
6873         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6874         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6875 };
6876
6877 struct mlx5_ifc_config_int_moderation_in_bits {
6878         u8         opcode[0x10];
6879         u8         reserved_at_10[0x10];
6880
6881         u8         reserved_at_20[0x10];
6882         u8         op_mod[0x10];
6883
6884         u8         reserved_at_40[0x4];
6885         u8         min_delay[0xc];
6886         u8         int_vector[0x10];
6887
6888         u8         reserved_at_60[0x20];
6889 };
6890
6891 struct mlx5_ifc_attach_to_mcg_out_bits {
6892         u8         status[0x8];
6893         u8         reserved_at_8[0x18];
6894
6895         u8         syndrome[0x20];
6896
6897         u8         reserved_at_40[0x40];
6898 };
6899
6900 struct mlx5_ifc_attach_to_mcg_in_bits {
6901         u8         opcode[0x10];
6902         u8         reserved_at_10[0x10];
6903
6904         u8         reserved_at_20[0x10];
6905         u8         op_mod[0x10];
6906
6907         u8         reserved_at_40[0x8];
6908         u8         qpn[0x18];
6909
6910         u8         reserved_at_60[0x20];
6911
6912         u8         multicast_gid[16][0x8];
6913 };
6914
6915 struct mlx5_ifc_arm_xrq_out_bits {
6916         u8         status[0x8];
6917         u8         reserved_at_8[0x18];
6918
6919         u8         syndrome[0x20];
6920
6921         u8         reserved_at_40[0x40];
6922 };
6923
6924 struct mlx5_ifc_arm_xrq_in_bits {
6925         u8         opcode[0x10];
6926         u8         reserved_at_10[0x10];
6927
6928         u8         reserved_at_20[0x10];
6929         u8         op_mod[0x10];
6930
6931         u8         reserved_at_40[0x8];
6932         u8         xrqn[0x18];
6933
6934         u8         reserved_at_60[0x10];
6935         u8         lwm[0x10];
6936 };
6937
6938 struct mlx5_ifc_arm_xrc_srq_out_bits {
6939         u8         status[0x8];
6940         u8         reserved_at_8[0x18];
6941
6942         u8         syndrome[0x20];
6943
6944         u8         reserved_at_40[0x40];
6945 };
6946
6947 enum {
6948         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6949 };
6950
6951 struct mlx5_ifc_arm_xrc_srq_in_bits {
6952         u8         opcode[0x10];
6953         u8         reserved_at_10[0x10];
6954
6955         u8         reserved_at_20[0x10];
6956         u8         op_mod[0x10];
6957
6958         u8         reserved_at_40[0x8];
6959         u8         xrc_srqn[0x18];
6960
6961         u8         reserved_at_60[0x10];
6962         u8         lwm[0x10];
6963 };
6964
6965 struct mlx5_ifc_arm_rq_out_bits {
6966         u8         status[0x8];
6967         u8         reserved_at_8[0x18];
6968
6969         u8         syndrome[0x20];
6970
6971         u8         reserved_at_40[0x40];
6972 };
6973
6974 enum {
6975         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6976         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6977 };
6978
6979 struct mlx5_ifc_arm_rq_in_bits {
6980         u8         opcode[0x10];
6981         u8         reserved_at_10[0x10];
6982
6983         u8         reserved_at_20[0x10];
6984         u8         op_mod[0x10];
6985
6986         u8         reserved_at_40[0x8];
6987         u8         srq_number[0x18];
6988
6989         u8         reserved_at_60[0x10];
6990         u8         lwm[0x10];
6991 };
6992
6993 struct mlx5_ifc_arm_dct_out_bits {
6994         u8         status[0x8];
6995         u8         reserved_at_8[0x18];
6996
6997         u8         syndrome[0x20];
6998
6999         u8         reserved_at_40[0x40];
7000 };
7001
7002 struct mlx5_ifc_arm_dct_in_bits {
7003         u8         opcode[0x10];
7004         u8         reserved_at_10[0x10];
7005
7006         u8         reserved_at_20[0x10];
7007         u8         op_mod[0x10];
7008
7009         u8         reserved_at_40[0x8];
7010         u8         dct_number[0x18];
7011
7012         u8         reserved_at_60[0x20];
7013 };
7014
7015 struct mlx5_ifc_alloc_xrcd_out_bits {
7016         u8         status[0x8];
7017         u8         reserved_at_8[0x18];
7018
7019         u8         syndrome[0x20];
7020
7021         u8         reserved_at_40[0x8];
7022         u8         xrcd[0x18];
7023
7024         u8         reserved_at_60[0x20];
7025 };
7026
7027 struct mlx5_ifc_alloc_xrcd_in_bits {
7028         u8         opcode[0x10];
7029         u8         reserved_at_10[0x10];
7030
7031         u8         reserved_at_20[0x10];
7032         u8         op_mod[0x10];
7033
7034         u8         reserved_at_40[0x40];
7035 };
7036
7037 struct mlx5_ifc_alloc_uar_out_bits {
7038         u8         status[0x8];
7039         u8         reserved_at_8[0x18];
7040
7041         u8         syndrome[0x20];
7042
7043         u8         reserved_at_40[0x8];
7044         u8         uar[0x18];
7045
7046         u8         reserved_at_60[0x20];
7047 };
7048
7049 struct mlx5_ifc_alloc_uar_in_bits {
7050         u8         opcode[0x10];
7051         u8         reserved_at_10[0x10];
7052
7053         u8         reserved_at_20[0x10];
7054         u8         op_mod[0x10];
7055
7056         u8         reserved_at_40[0x40];
7057 };
7058
7059 struct mlx5_ifc_alloc_transport_domain_out_bits {
7060         u8         status[0x8];
7061         u8         reserved_at_8[0x18];
7062
7063         u8         syndrome[0x20];
7064
7065         u8         reserved_at_40[0x8];
7066         u8         transport_domain[0x18];
7067
7068         u8         reserved_at_60[0x20];
7069 };
7070
7071 struct mlx5_ifc_alloc_transport_domain_in_bits {
7072         u8         opcode[0x10];
7073         u8         reserved_at_10[0x10];
7074
7075         u8         reserved_at_20[0x10];
7076         u8         op_mod[0x10];
7077
7078         u8         reserved_at_40[0x40];
7079 };
7080
7081 struct mlx5_ifc_alloc_q_counter_out_bits {
7082         u8         status[0x8];
7083         u8         reserved_at_8[0x18];
7084
7085         u8         syndrome[0x20];
7086
7087         u8         reserved_at_40[0x18];
7088         u8         counter_set_id[0x8];
7089
7090         u8         reserved_at_60[0x20];
7091 };
7092
7093 struct mlx5_ifc_alloc_q_counter_in_bits {
7094         u8         opcode[0x10];
7095         u8         reserved_at_10[0x10];
7096
7097         u8         reserved_at_20[0x10];
7098         u8         op_mod[0x10];
7099
7100         u8         reserved_at_40[0x40];
7101 };
7102
7103 struct mlx5_ifc_alloc_pd_out_bits {
7104         u8         status[0x8];
7105         u8         reserved_at_8[0x18];
7106
7107         u8         syndrome[0x20];
7108
7109         u8         reserved_at_40[0x8];
7110         u8         pd[0x18];
7111
7112         u8         reserved_at_60[0x20];
7113 };
7114
7115 struct mlx5_ifc_alloc_pd_in_bits {
7116         u8         opcode[0x10];
7117         u8         reserved_at_10[0x10];
7118
7119         u8         reserved_at_20[0x10];
7120         u8         op_mod[0x10];
7121
7122         u8         reserved_at_40[0x40];
7123 };
7124
7125 struct mlx5_ifc_alloc_flow_counter_out_bits {
7126         u8         status[0x8];
7127         u8         reserved_at_8[0x18];
7128
7129         u8         syndrome[0x20];
7130
7131         u8         reserved_at_40[0x10];
7132         u8         flow_counter_id[0x10];
7133
7134         u8         reserved_at_60[0x20];
7135 };
7136
7137 struct mlx5_ifc_alloc_flow_counter_in_bits {
7138         u8         opcode[0x10];
7139         u8         reserved_at_10[0x10];
7140
7141         u8         reserved_at_20[0x10];
7142         u8         op_mod[0x10];
7143
7144         u8         reserved_at_40[0x40];
7145 };
7146
7147 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7148         u8         status[0x8];
7149         u8         reserved_at_8[0x18];
7150
7151         u8         syndrome[0x20];
7152
7153         u8         reserved_at_40[0x40];
7154 };
7155
7156 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7157         u8         opcode[0x10];
7158         u8         reserved_at_10[0x10];
7159
7160         u8         reserved_at_20[0x10];
7161         u8         op_mod[0x10];
7162
7163         u8         reserved_at_40[0x20];
7164
7165         u8         reserved_at_60[0x10];
7166         u8         vxlan_udp_port[0x10];
7167 };
7168
7169 struct mlx5_ifc_set_rate_limit_out_bits {
7170         u8         status[0x8];
7171         u8         reserved_at_8[0x18];
7172
7173         u8         syndrome[0x20];
7174
7175         u8         reserved_at_40[0x40];
7176 };
7177
7178 struct mlx5_ifc_set_rate_limit_in_bits {
7179         u8         opcode[0x10];
7180         u8         reserved_at_10[0x10];
7181
7182         u8         reserved_at_20[0x10];
7183         u8         op_mod[0x10];
7184
7185         u8         reserved_at_40[0x10];
7186         u8         rate_limit_index[0x10];
7187
7188         u8         reserved_at_60[0x20];
7189
7190         u8         rate_limit[0x20];
7191 };
7192
7193 struct mlx5_ifc_access_register_out_bits {
7194         u8         status[0x8];
7195         u8         reserved_at_8[0x18];
7196
7197         u8         syndrome[0x20];
7198
7199         u8         reserved_at_40[0x40];
7200
7201         u8         register_data[0][0x20];
7202 };
7203
7204 enum {
7205         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7206         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7207 };
7208
7209 struct mlx5_ifc_access_register_in_bits {
7210         u8         opcode[0x10];
7211         u8         reserved_at_10[0x10];
7212
7213         u8         reserved_at_20[0x10];
7214         u8         op_mod[0x10];
7215
7216         u8         reserved_at_40[0x10];
7217         u8         register_id[0x10];
7218
7219         u8         argument[0x20];
7220
7221         u8         register_data[0][0x20];
7222 };
7223
7224 struct mlx5_ifc_sltp_reg_bits {
7225         u8         status[0x4];
7226         u8         version[0x4];
7227         u8         local_port[0x8];
7228         u8         pnat[0x2];
7229         u8         reserved_at_12[0x2];
7230         u8         lane[0x4];
7231         u8         reserved_at_18[0x8];
7232
7233         u8         reserved_at_20[0x20];
7234
7235         u8         reserved_at_40[0x7];
7236         u8         polarity[0x1];
7237         u8         ob_tap0[0x8];
7238         u8         ob_tap1[0x8];
7239         u8         ob_tap2[0x8];
7240
7241         u8         reserved_at_60[0xc];
7242         u8         ob_preemp_mode[0x4];
7243         u8         ob_reg[0x8];
7244         u8         ob_bias[0x8];
7245
7246         u8         reserved_at_80[0x20];
7247 };
7248
7249 struct mlx5_ifc_slrg_reg_bits {
7250         u8         status[0x4];
7251         u8         version[0x4];
7252         u8         local_port[0x8];
7253         u8         pnat[0x2];
7254         u8         reserved_at_12[0x2];
7255         u8         lane[0x4];
7256         u8         reserved_at_18[0x8];
7257
7258         u8         time_to_link_up[0x10];
7259         u8         reserved_at_30[0xc];
7260         u8         grade_lane_speed[0x4];
7261
7262         u8         grade_version[0x8];
7263         u8         grade[0x18];
7264
7265         u8         reserved_at_60[0x4];
7266         u8         height_grade_type[0x4];
7267         u8         height_grade[0x18];
7268
7269         u8         height_dz[0x10];
7270         u8         height_dv[0x10];
7271
7272         u8         reserved_at_a0[0x10];
7273         u8         height_sigma[0x10];
7274
7275         u8         reserved_at_c0[0x20];
7276
7277         u8         reserved_at_e0[0x4];
7278         u8         phase_grade_type[0x4];
7279         u8         phase_grade[0x18];
7280
7281         u8         reserved_at_100[0x8];
7282         u8         phase_eo_pos[0x8];
7283         u8         reserved_at_110[0x8];
7284         u8         phase_eo_neg[0x8];
7285
7286         u8         ffe_set_tested[0x10];
7287         u8         test_errors_per_lane[0x10];
7288 };
7289
7290 struct mlx5_ifc_pvlc_reg_bits {
7291         u8         reserved_at_0[0x8];
7292         u8         local_port[0x8];
7293         u8         reserved_at_10[0x10];
7294
7295         u8         reserved_at_20[0x1c];
7296         u8         vl_hw_cap[0x4];
7297
7298         u8         reserved_at_40[0x1c];
7299         u8         vl_admin[0x4];
7300
7301         u8         reserved_at_60[0x1c];
7302         u8         vl_operational[0x4];
7303 };
7304
7305 struct mlx5_ifc_pude_reg_bits {
7306         u8         swid[0x8];
7307         u8         local_port[0x8];
7308         u8         reserved_at_10[0x4];
7309         u8         admin_status[0x4];
7310         u8         reserved_at_18[0x4];
7311         u8         oper_status[0x4];
7312
7313         u8         reserved_at_20[0x60];
7314 };
7315
7316 struct mlx5_ifc_ptys_reg_bits {
7317         u8         reserved_at_0[0x1];
7318         u8         an_disable_admin[0x1];
7319         u8         an_disable_cap[0x1];
7320         u8         reserved_at_3[0x5];
7321         u8         local_port[0x8];
7322         u8         reserved_at_10[0xd];
7323         u8         proto_mask[0x3];
7324
7325         u8         an_status[0x4];
7326         u8         reserved_at_24[0x3c];
7327
7328         u8         eth_proto_capability[0x20];
7329
7330         u8         ib_link_width_capability[0x10];
7331         u8         ib_proto_capability[0x10];
7332
7333         u8         reserved_at_a0[0x20];
7334
7335         u8         eth_proto_admin[0x20];
7336
7337         u8         ib_link_width_admin[0x10];
7338         u8         ib_proto_admin[0x10];
7339
7340         u8         reserved_at_100[0x20];
7341
7342         u8         eth_proto_oper[0x20];
7343
7344         u8         ib_link_width_oper[0x10];
7345         u8         ib_proto_oper[0x10];
7346
7347         u8         reserved_at_160[0x1c];
7348         u8         connector_type[0x4];
7349
7350         u8         eth_proto_lp_advertise[0x20];
7351
7352         u8         reserved_at_1a0[0x60];
7353 };
7354
7355 struct mlx5_ifc_mlcr_reg_bits {
7356         u8         reserved_at_0[0x8];
7357         u8         local_port[0x8];
7358         u8         reserved_at_10[0x20];
7359
7360         u8         beacon_duration[0x10];
7361         u8         reserved_at_40[0x10];
7362
7363         u8         beacon_remain[0x10];
7364 };
7365
7366 struct mlx5_ifc_ptas_reg_bits {
7367         u8         reserved_at_0[0x20];
7368
7369         u8         algorithm_options[0x10];
7370         u8         reserved_at_30[0x4];
7371         u8         repetitions_mode[0x4];
7372         u8         num_of_repetitions[0x8];
7373
7374         u8         grade_version[0x8];
7375         u8         height_grade_type[0x4];
7376         u8         phase_grade_type[0x4];
7377         u8         height_grade_weight[0x8];
7378         u8         phase_grade_weight[0x8];
7379
7380         u8         gisim_measure_bits[0x10];
7381         u8         adaptive_tap_measure_bits[0x10];
7382
7383         u8         ber_bath_high_error_threshold[0x10];
7384         u8         ber_bath_mid_error_threshold[0x10];
7385
7386         u8         ber_bath_low_error_threshold[0x10];
7387         u8         one_ratio_high_threshold[0x10];
7388
7389         u8         one_ratio_high_mid_threshold[0x10];
7390         u8         one_ratio_low_mid_threshold[0x10];
7391
7392         u8         one_ratio_low_threshold[0x10];
7393         u8         ndeo_error_threshold[0x10];
7394
7395         u8         mixer_offset_step_size[0x10];
7396         u8         reserved_at_110[0x8];
7397         u8         mix90_phase_for_voltage_bath[0x8];
7398
7399         u8         mixer_offset_start[0x10];
7400         u8         mixer_offset_end[0x10];
7401
7402         u8         reserved_at_140[0x15];
7403         u8         ber_test_time[0xb];
7404 };
7405
7406 struct mlx5_ifc_pspa_reg_bits {
7407         u8         swid[0x8];
7408         u8         local_port[0x8];
7409         u8         sub_port[0x8];
7410         u8         reserved_at_18[0x8];
7411
7412         u8         reserved_at_20[0x20];
7413 };
7414
7415 struct mlx5_ifc_pqdr_reg_bits {
7416         u8         reserved_at_0[0x8];
7417         u8         local_port[0x8];
7418         u8         reserved_at_10[0x5];
7419         u8         prio[0x3];
7420         u8         reserved_at_18[0x6];
7421         u8         mode[0x2];
7422
7423         u8         reserved_at_20[0x20];
7424
7425         u8         reserved_at_40[0x10];
7426         u8         min_threshold[0x10];
7427
7428         u8         reserved_at_60[0x10];
7429         u8         max_threshold[0x10];
7430
7431         u8         reserved_at_80[0x10];
7432         u8         mark_probability_denominator[0x10];
7433
7434         u8         reserved_at_a0[0x60];
7435 };
7436
7437 struct mlx5_ifc_ppsc_reg_bits {
7438         u8         reserved_at_0[0x8];
7439         u8         local_port[0x8];
7440         u8         reserved_at_10[0x10];
7441
7442         u8         reserved_at_20[0x60];
7443
7444         u8         reserved_at_80[0x1c];
7445         u8         wrps_admin[0x4];
7446
7447         u8         reserved_at_a0[0x1c];
7448         u8         wrps_status[0x4];
7449
7450         u8         reserved_at_c0[0x8];
7451         u8         up_threshold[0x8];
7452         u8         reserved_at_d0[0x8];
7453         u8         down_threshold[0x8];
7454
7455         u8         reserved_at_e0[0x20];
7456
7457         u8         reserved_at_100[0x1c];
7458         u8         srps_admin[0x4];
7459
7460         u8         reserved_at_120[0x1c];
7461         u8         srps_status[0x4];
7462
7463         u8         reserved_at_140[0x40];
7464 };
7465
7466 struct mlx5_ifc_pplr_reg_bits {
7467         u8         reserved_at_0[0x8];
7468         u8         local_port[0x8];
7469         u8         reserved_at_10[0x10];
7470
7471         u8         reserved_at_20[0x8];
7472         u8         lb_cap[0x8];
7473         u8         reserved_at_30[0x8];
7474         u8         lb_en[0x8];
7475 };
7476
7477 struct mlx5_ifc_pplm_reg_bits {
7478         u8         reserved_at_0[0x8];
7479         u8         local_port[0x8];
7480         u8         reserved_at_10[0x10];
7481
7482         u8         reserved_at_20[0x20];
7483
7484         u8         port_profile_mode[0x8];
7485         u8         static_port_profile[0x8];
7486         u8         active_port_profile[0x8];
7487         u8         reserved_at_58[0x8];
7488
7489         u8         retransmission_active[0x8];
7490         u8         fec_mode_active[0x18];
7491
7492         u8         reserved_at_80[0x20];
7493 };
7494
7495 struct mlx5_ifc_ppcnt_reg_bits {
7496         u8         swid[0x8];
7497         u8         local_port[0x8];
7498         u8         pnat[0x2];
7499         u8         reserved_at_12[0x8];
7500         u8         grp[0x6];
7501
7502         u8         clr[0x1];
7503         u8         reserved_at_21[0x1c];
7504         u8         prio_tc[0x3];
7505
7506         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7507 };
7508
7509 struct mlx5_ifc_mpcnt_reg_bits {
7510         u8         reserved_at_0[0x8];
7511         u8         pcie_index[0x8];
7512         u8         reserved_at_10[0xa];
7513         u8         grp[0x6];
7514
7515         u8         clr[0x1];
7516         u8         reserved_at_21[0x1f];
7517
7518         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7519 };
7520
7521 struct mlx5_ifc_ppad_reg_bits {
7522         u8         reserved_at_0[0x3];
7523         u8         single_mac[0x1];
7524         u8         reserved_at_4[0x4];
7525         u8         local_port[0x8];
7526         u8         mac_47_32[0x10];
7527
7528         u8         mac_31_0[0x20];
7529
7530         u8         reserved_at_40[0x40];
7531 };
7532
7533 struct mlx5_ifc_pmtu_reg_bits {
7534         u8         reserved_at_0[0x8];
7535         u8         local_port[0x8];
7536         u8         reserved_at_10[0x10];
7537
7538         u8         max_mtu[0x10];
7539         u8         reserved_at_30[0x10];
7540
7541         u8         admin_mtu[0x10];
7542         u8         reserved_at_50[0x10];
7543
7544         u8         oper_mtu[0x10];
7545         u8         reserved_at_70[0x10];
7546 };
7547
7548 struct mlx5_ifc_pmpr_reg_bits {
7549         u8         reserved_at_0[0x8];
7550         u8         module[0x8];
7551         u8         reserved_at_10[0x10];
7552
7553         u8         reserved_at_20[0x18];
7554         u8         attenuation_5g[0x8];
7555
7556         u8         reserved_at_40[0x18];
7557         u8         attenuation_7g[0x8];
7558
7559         u8         reserved_at_60[0x18];
7560         u8         attenuation_12g[0x8];
7561 };
7562
7563 struct mlx5_ifc_pmpe_reg_bits {
7564         u8         reserved_at_0[0x8];
7565         u8         module[0x8];
7566         u8         reserved_at_10[0xc];
7567         u8         module_status[0x4];
7568
7569         u8         reserved_at_20[0x60];
7570 };
7571
7572 struct mlx5_ifc_pmpc_reg_bits {
7573         u8         module_state_updated[32][0x8];
7574 };
7575
7576 struct mlx5_ifc_pmlpn_reg_bits {
7577         u8         reserved_at_0[0x4];
7578         u8         mlpn_status[0x4];
7579         u8         local_port[0x8];
7580         u8         reserved_at_10[0x10];
7581
7582         u8         e[0x1];
7583         u8         reserved_at_21[0x1f];
7584 };
7585
7586 struct mlx5_ifc_pmlp_reg_bits {
7587         u8         rxtx[0x1];
7588         u8         reserved_at_1[0x7];
7589         u8         local_port[0x8];
7590         u8         reserved_at_10[0x8];
7591         u8         width[0x8];
7592
7593         u8         lane0_module_mapping[0x20];
7594
7595         u8         lane1_module_mapping[0x20];
7596
7597         u8         lane2_module_mapping[0x20];
7598
7599         u8         lane3_module_mapping[0x20];
7600
7601         u8         reserved_at_a0[0x160];
7602 };
7603
7604 struct mlx5_ifc_pmaos_reg_bits {
7605         u8         reserved_at_0[0x8];
7606         u8         module[0x8];
7607         u8         reserved_at_10[0x4];
7608         u8         admin_status[0x4];
7609         u8         reserved_at_18[0x4];
7610         u8         oper_status[0x4];
7611
7612         u8         ase[0x1];
7613         u8         ee[0x1];
7614         u8         reserved_at_22[0x1c];
7615         u8         e[0x2];
7616
7617         u8         reserved_at_40[0x40];
7618 };
7619
7620 struct mlx5_ifc_plpc_reg_bits {
7621         u8         reserved_at_0[0x4];
7622         u8         profile_id[0xc];
7623         u8         reserved_at_10[0x4];
7624         u8         proto_mask[0x4];
7625         u8         reserved_at_18[0x8];
7626
7627         u8         reserved_at_20[0x10];
7628         u8         lane_speed[0x10];
7629
7630         u8         reserved_at_40[0x17];
7631         u8         lpbf[0x1];
7632         u8         fec_mode_policy[0x8];
7633
7634         u8         retransmission_capability[0x8];
7635         u8         fec_mode_capability[0x18];
7636
7637         u8         retransmission_support_admin[0x8];
7638         u8         fec_mode_support_admin[0x18];
7639
7640         u8         retransmission_request_admin[0x8];
7641         u8         fec_mode_request_admin[0x18];
7642
7643         u8         reserved_at_c0[0x80];
7644 };
7645
7646 struct mlx5_ifc_plib_reg_bits {
7647         u8         reserved_at_0[0x8];
7648         u8         local_port[0x8];
7649         u8         reserved_at_10[0x8];
7650         u8         ib_port[0x8];
7651
7652         u8         reserved_at_20[0x60];
7653 };
7654
7655 struct mlx5_ifc_plbf_reg_bits {
7656         u8         reserved_at_0[0x8];
7657         u8         local_port[0x8];
7658         u8         reserved_at_10[0xd];
7659         u8         lbf_mode[0x3];
7660
7661         u8         reserved_at_20[0x20];
7662 };
7663
7664 struct mlx5_ifc_pipg_reg_bits {
7665         u8         reserved_at_0[0x8];
7666         u8         local_port[0x8];
7667         u8         reserved_at_10[0x10];
7668
7669         u8         dic[0x1];
7670         u8         reserved_at_21[0x19];
7671         u8         ipg[0x4];
7672         u8         reserved_at_3e[0x2];
7673 };
7674
7675 struct mlx5_ifc_pifr_reg_bits {
7676         u8         reserved_at_0[0x8];
7677         u8         local_port[0x8];
7678         u8         reserved_at_10[0x10];
7679
7680         u8         reserved_at_20[0xe0];
7681
7682         u8         port_filter[8][0x20];
7683
7684         u8         port_filter_update_en[8][0x20];
7685 };
7686
7687 struct mlx5_ifc_pfcc_reg_bits {
7688         u8         reserved_at_0[0x8];
7689         u8         local_port[0x8];
7690         u8         reserved_at_10[0x10];
7691
7692         u8         ppan[0x4];
7693         u8         reserved_at_24[0x4];
7694         u8         prio_mask_tx[0x8];
7695         u8         reserved_at_30[0x8];
7696         u8         prio_mask_rx[0x8];
7697
7698         u8         pptx[0x1];
7699         u8         aptx[0x1];
7700         u8         reserved_at_42[0x6];
7701         u8         pfctx[0x8];
7702         u8         reserved_at_50[0x10];
7703
7704         u8         pprx[0x1];
7705         u8         aprx[0x1];
7706         u8         reserved_at_62[0x6];
7707         u8         pfcrx[0x8];
7708         u8         reserved_at_70[0x10];
7709
7710         u8         reserved_at_80[0x80];
7711 };
7712
7713 struct mlx5_ifc_pelc_reg_bits {
7714         u8         op[0x4];
7715         u8         reserved_at_4[0x4];
7716         u8         local_port[0x8];
7717         u8         reserved_at_10[0x10];
7718
7719         u8         op_admin[0x8];
7720         u8         op_capability[0x8];
7721         u8         op_request[0x8];
7722         u8         op_active[0x8];
7723
7724         u8         admin[0x40];
7725
7726         u8         capability[0x40];
7727
7728         u8         request[0x40];
7729
7730         u8         active[0x40];
7731
7732         u8         reserved_at_140[0x80];
7733 };
7734
7735 struct mlx5_ifc_peir_reg_bits {
7736         u8         reserved_at_0[0x8];
7737         u8         local_port[0x8];
7738         u8         reserved_at_10[0x10];
7739
7740         u8         reserved_at_20[0xc];
7741         u8         error_count[0x4];
7742         u8         reserved_at_30[0x10];
7743
7744         u8         reserved_at_40[0xc];
7745         u8         lane[0x4];
7746         u8         reserved_at_50[0x8];
7747         u8         error_type[0x8];
7748 };
7749
7750 struct mlx5_ifc_pcam_enhanced_features_bits {
7751         u8         reserved_at_0[0x7c];
7752
7753         u8         ptys_connector_type[0x1];
7754         u8         reserved_at_7d[0x1];
7755         u8         ppcnt_discard_group[0x1];
7756         u8         ppcnt_statistical_group[0x1];
7757 };
7758
7759 struct mlx5_ifc_pcam_reg_bits {
7760         u8         reserved_at_0[0x8];
7761         u8         feature_group[0x8];
7762         u8         reserved_at_10[0x8];
7763         u8         access_reg_group[0x8];
7764
7765         u8         reserved_at_20[0x20];
7766
7767         union {
7768                 u8         reserved_at_0[0x80];
7769         } port_access_reg_cap_mask;
7770
7771         u8         reserved_at_c0[0x80];
7772
7773         union {
7774                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7775                 u8         reserved_at_0[0x80];
7776         } feature_cap_mask;
7777
7778         u8         reserved_at_1c0[0xc0];
7779 };
7780
7781 struct mlx5_ifc_mcam_enhanced_features_bits {
7782         u8         reserved_at_0[0x7f];
7783
7784         u8         pcie_performance_group[0x1];
7785 };
7786
7787 struct mlx5_ifc_mcam_access_reg_bits {
7788         u8         reserved_at_0[0x1c];
7789         u8         mcda[0x1];
7790         u8         mcc[0x1];
7791         u8         mcqi[0x1];
7792         u8         reserved_at_1f[0x1];
7793
7794         u8         regs_95_to_64[0x20];
7795         u8         regs_63_to_32[0x20];
7796         u8         regs_31_to_0[0x20];
7797 };
7798
7799 struct mlx5_ifc_mcam_reg_bits {
7800         u8         reserved_at_0[0x8];
7801         u8         feature_group[0x8];
7802         u8         reserved_at_10[0x8];
7803         u8         access_reg_group[0x8];
7804
7805         u8         reserved_at_20[0x20];
7806
7807         union {
7808                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
7809                 u8         reserved_at_0[0x80];
7810         } mng_access_reg_cap_mask;
7811
7812         u8         reserved_at_c0[0x80];
7813
7814         union {
7815                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7816                 u8         reserved_at_0[0x80];
7817         } mng_feature_cap_mask;
7818
7819         u8         reserved_at_1c0[0x80];
7820 };
7821
7822 struct mlx5_ifc_pcap_reg_bits {
7823         u8         reserved_at_0[0x8];
7824         u8         local_port[0x8];
7825         u8         reserved_at_10[0x10];
7826
7827         u8         port_capability_mask[4][0x20];
7828 };
7829
7830 struct mlx5_ifc_paos_reg_bits {
7831         u8         swid[0x8];
7832         u8         local_port[0x8];
7833         u8         reserved_at_10[0x4];
7834         u8         admin_status[0x4];
7835         u8         reserved_at_18[0x4];
7836         u8         oper_status[0x4];
7837
7838         u8         ase[0x1];
7839         u8         ee[0x1];
7840         u8         reserved_at_22[0x1c];
7841         u8         e[0x2];
7842
7843         u8         reserved_at_40[0x40];
7844 };
7845
7846 struct mlx5_ifc_pamp_reg_bits {
7847         u8         reserved_at_0[0x8];
7848         u8         opamp_group[0x8];
7849         u8         reserved_at_10[0xc];
7850         u8         opamp_group_type[0x4];
7851
7852         u8         start_index[0x10];
7853         u8         reserved_at_30[0x4];
7854         u8         num_of_indices[0xc];
7855
7856         u8         index_data[18][0x10];
7857 };
7858
7859 struct mlx5_ifc_pcmr_reg_bits {
7860         u8         reserved_at_0[0x8];
7861         u8         local_port[0x8];
7862         u8         reserved_at_10[0x2e];
7863         u8         fcs_cap[0x1];
7864         u8         reserved_at_3f[0x1f];
7865         u8         fcs_chk[0x1];
7866         u8         reserved_at_5f[0x1];
7867 };
7868
7869 struct mlx5_ifc_lane_2_module_mapping_bits {
7870         u8         reserved_at_0[0x6];
7871         u8         rx_lane[0x2];
7872         u8         reserved_at_8[0x6];
7873         u8         tx_lane[0x2];
7874         u8         reserved_at_10[0x8];
7875         u8         module[0x8];
7876 };
7877
7878 struct mlx5_ifc_bufferx_reg_bits {
7879         u8         reserved_at_0[0x6];
7880         u8         lossy[0x1];
7881         u8         epsb[0x1];
7882         u8         reserved_at_8[0xc];
7883         u8         size[0xc];
7884
7885         u8         xoff_threshold[0x10];
7886         u8         xon_threshold[0x10];
7887 };
7888
7889 struct mlx5_ifc_set_node_in_bits {
7890         u8         node_description[64][0x8];
7891 };
7892
7893 struct mlx5_ifc_register_power_settings_bits {
7894         u8         reserved_at_0[0x18];
7895         u8         power_settings_level[0x8];
7896
7897         u8         reserved_at_20[0x60];
7898 };
7899
7900 struct mlx5_ifc_register_host_endianness_bits {
7901         u8         he[0x1];
7902         u8         reserved_at_1[0x1f];
7903
7904         u8         reserved_at_20[0x60];
7905 };
7906
7907 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7908         u8         reserved_at_0[0x20];
7909
7910         u8         mkey[0x20];
7911
7912         u8         addressh_63_32[0x20];
7913
7914         u8         addressl_31_0[0x20];
7915 };
7916
7917 struct mlx5_ifc_ud_adrs_vector_bits {
7918         u8         dc_key[0x40];
7919
7920         u8         ext[0x1];
7921         u8         reserved_at_41[0x7];
7922         u8         destination_qp_dct[0x18];
7923
7924         u8         static_rate[0x4];
7925         u8         sl_eth_prio[0x4];
7926         u8         fl[0x1];
7927         u8         mlid[0x7];
7928         u8         rlid_udp_sport[0x10];
7929
7930         u8         reserved_at_80[0x20];
7931
7932         u8         rmac_47_16[0x20];
7933
7934         u8         rmac_15_0[0x10];
7935         u8         tclass[0x8];
7936         u8         hop_limit[0x8];
7937
7938         u8         reserved_at_e0[0x1];
7939         u8         grh[0x1];
7940         u8         reserved_at_e2[0x2];
7941         u8         src_addr_index[0x8];
7942         u8         flow_label[0x14];
7943
7944         u8         rgid_rip[16][0x8];
7945 };
7946
7947 struct mlx5_ifc_pages_req_event_bits {
7948         u8         reserved_at_0[0x10];
7949         u8         function_id[0x10];
7950
7951         u8         num_pages[0x20];
7952
7953         u8         reserved_at_40[0xa0];
7954 };
7955
7956 struct mlx5_ifc_eqe_bits {
7957         u8         reserved_at_0[0x8];
7958         u8         event_type[0x8];
7959         u8         reserved_at_10[0x8];
7960         u8         event_sub_type[0x8];
7961
7962         u8         reserved_at_20[0xe0];
7963
7964         union mlx5_ifc_event_auto_bits event_data;
7965
7966         u8         reserved_at_1e0[0x10];
7967         u8         signature[0x8];
7968         u8         reserved_at_1f8[0x7];
7969         u8         owner[0x1];
7970 };
7971
7972 enum {
7973         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7974 };
7975
7976 struct mlx5_ifc_cmd_queue_entry_bits {
7977         u8         type[0x8];
7978         u8         reserved_at_8[0x18];
7979
7980         u8         input_length[0x20];
7981
7982         u8         input_mailbox_pointer_63_32[0x20];
7983
7984         u8         input_mailbox_pointer_31_9[0x17];
7985         u8         reserved_at_77[0x9];
7986
7987         u8         command_input_inline_data[16][0x8];
7988
7989         u8         command_output_inline_data[16][0x8];
7990
7991         u8         output_mailbox_pointer_63_32[0x20];
7992
7993         u8         output_mailbox_pointer_31_9[0x17];
7994         u8         reserved_at_1b7[0x9];
7995
7996         u8         output_length[0x20];
7997
7998         u8         token[0x8];
7999         u8         signature[0x8];
8000         u8         reserved_at_1f0[0x8];
8001         u8         status[0x7];
8002         u8         ownership[0x1];
8003 };
8004
8005 struct mlx5_ifc_cmd_out_bits {
8006         u8         status[0x8];
8007         u8         reserved_at_8[0x18];
8008
8009         u8         syndrome[0x20];
8010
8011         u8         command_output[0x20];
8012 };
8013
8014 struct mlx5_ifc_cmd_in_bits {
8015         u8         opcode[0x10];
8016         u8         reserved_at_10[0x10];
8017
8018         u8         reserved_at_20[0x10];
8019         u8         op_mod[0x10];
8020
8021         u8         command[0][0x20];
8022 };
8023
8024 struct mlx5_ifc_cmd_if_box_bits {
8025         u8         mailbox_data[512][0x8];
8026
8027         u8         reserved_at_1000[0x180];
8028
8029         u8         next_pointer_63_32[0x20];
8030
8031         u8         next_pointer_31_10[0x16];
8032         u8         reserved_at_11b6[0xa];
8033
8034         u8         block_number[0x20];
8035
8036         u8         reserved_at_11e0[0x8];
8037         u8         token[0x8];
8038         u8         ctrl_signature[0x8];
8039         u8         signature[0x8];
8040 };
8041
8042 struct mlx5_ifc_mtt_bits {
8043         u8         ptag_63_32[0x20];
8044
8045         u8         ptag_31_8[0x18];
8046         u8         reserved_at_38[0x6];
8047         u8         wr_en[0x1];
8048         u8         rd_en[0x1];
8049 };
8050
8051 struct mlx5_ifc_query_wol_rol_out_bits {
8052         u8         status[0x8];
8053         u8         reserved_at_8[0x18];
8054
8055         u8         syndrome[0x20];
8056
8057         u8         reserved_at_40[0x10];
8058         u8         rol_mode[0x8];
8059         u8         wol_mode[0x8];
8060
8061         u8         reserved_at_60[0x20];
8062 };
8063
8064 struct mlx5_ifc_query_wol_rol_in_bits {
8065         u8         opcode[0x10];
8066         u8         reserved_at_10[0x10];
8067
8068         u8         reserved_at_20[0x10];
8069         u8         op_mod[0x10];
8070
8071         u8         reserved_at_40[0x40];
8072 };
8073
8074 struct mlx5_ifc_set_wol_rol_out_bits {
8075         u8         status[0x8];
8076         u8         reserved_at_8[0x18];
8077
8078         u8         syndrome[0x20];
8079
8080         u8         reserved_at_40[0x40];
8081 };
8082
8083 struct mlx5_ifc_set_wol_rol_in_bits {
8084         u8         opcode[0x10];
8085         u8         reserved_at_10[0x10];
8086
8087         u8         reserved_at_20[0x10];
8088         u8         op_mod[0x10];
8089
8090         u8         rol_mode_valid[0x1];
8091         u8         wol_mode_valid[0x1];
8092         u8         reserved_at_42[0xe];
8093         u8         rol_mode[0x8];
8094         u8         wol_mode[0x8];
8095
8096         u8         reserved_at_60[0x20];
8097 };
8098
8099 enum {
8100         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8101         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8102         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8103 };
8104
8105 enum {
8106         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8107         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8108         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8109 };
8110
8111 enum {
8112         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8113         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8114         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8115         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8116         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8117         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8118         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8119         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8120         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8121         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8122         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8123 };
8124
8125 struct mlx5_ifc_initial_seg_bits {
8126         u8         fw_rev_minor[0x10];
8127         u8         fw_rev_major[0x10];
8128
8129         u8         cmd_interface_rev[0x10];
8130         u8         fw_rev_subminor[0x10];
8131
8132         u8         reserved_at_40[0x40];
8133
8134         u8         cmdq_phy_addr_63_32[0x20];
8135
8136         u8         cmdq_phy_addr_31_12[0x14];
8137         u8         reserved_at_b4[0x2];
8138         u8         nic_interface[0x2];
8139         u8         log_cmdq_size[0x4];
8140         u8         log_cmdq_stride[0x4];
8141
8142         u8         command_doorbell_vector[0x20];
8143
8144         u8         reserved_at_e0[0xf00];
8145
8146         u8         initializing[0x1];
8147         u8         reserved_at_fe1[0x4];
8148         u8         nic_interface_supported[0x3];
8149         u8         reserved_at_fe8[0x18];
8150
8151         struct mlx5_ifc_health_buffer_bits health_buffer;
8152
8153         u8         no_dram_nic_offset[0x20];
8154
8155         u8         reserved_at_1220[0x6e40];
8156
8157         u8         reserved_at_8060[0x1f];
8158         u8         clear_int[0x1];
8159
8160         u8         health_syndrome[0x8];
8161         u8         health_counter[0x18];
8162
8163         u8         reserved_at_80a0[0x17fc0];
8164 };
8165
8166 struct mlx5_ifc_mtpps_reg_bits {
8167         u8         reserved_at_0[0xc];
8168         u8         cap_number_of_pps_pins[0x4];
8169         u8         reserved_at_10[0x4];
8170         u8         cap_max_num_of_pps_in_pins[0x4];
8171         u8         reserved_at_18[0x4];
8172         u8         cap_max_num_of_pps_out_pins[0x4];
8173
8174         u8         reserved_at_20[0x24];
8175         u8         cap_pin_3_mode[0x4];
8176         u8         reserved_at_48[0x4];
8177         u8         cap_pin_2_mode[0x4];
8178         u8         reserved_at_50[0x4];
8179         u8         cap_pin_1_mode[0x4];
8180         u8         reserved_at_58[0x4];
8181         u8         cap_pin_0_mode[0x4];
8182
8183         u8         reserved_at_60[0x4];
8184         u8         cap_pin_7_mode[0x4];
8185         u8         reserved_at_68[0x4];
8186         u8         cap_pin_6_mode[0x4];
8187         u8         reserved_at_70[0x4];
8188         u8         cap_pin_5_mode[0x4];
8189         u8         reserved_at_78[0x4];
8190         u8         cap_pin_4_mode[0x4];
8191
8192         u8         reserved_at_80[0x80];
8193
8194         u8         enable[0x1];
8195         u8         reserved_at_101[0xb];
8196         u8         pattern[0x4];
8197         u8         reserved_at_110[0x4];
8198         u8         pin_mode[0x4];
8199         u8         pin[0x8];
8200
8201         u8         reserved_at_120[0x20];
8202
8203         u8         time_stamp[0x40];
8204
8205         u8         out_pulse_duration[0x10];
8206         u8         out_periodic_adjustment[0x10];
8207
8208         u8         reserved_at_1a0[0x60];
8209 };
8210
8211 struct mlx5_ifc_mtppse_reg_bits {
8212         u8         reserved_at_0[0x18];
8213         u8         pin[0x8];
8214         u8         event_arm[0x1];
8215         u8         reserved_at_21[0x1b];
8216         u8         event_generation_mode[0x4];
8217         u8         reserved_at_40[0x40];
8218 };
8219
8220 struct mlx5_ifc_mcqi_cap_bits {
8221         u8         supported_info_bitmask[0x20];
8222
8223         u8         component_size[0x20];
8224
8225         u8         max_component_size[0x20];
8226
8227         u8         log_mcda_word_size[0x4];
8228         u8         reserved_at_64[0xc];
8229         u8         mcda_max_write_size[0x10];
8230
8231         u8         rd_en[0x1];
8232         u8         reserved_at_81[0x1];
8233         u8         match_chip_id[0x1];
8234         u8         match_psid[0x1];
8235         u8         check_user_timestamp[0x1];
8236         u8         match_base_guid_mac[0x1];
8237         u8         reserved_at_86[0x1a];
8238 };
8239
8240 struct mlx5_ifc_mcqi_reg_bits {
8241         u8         read_pending_component[0x1];
8242         u8         reserved_at_1[0xf];
8243         u8         component_index[0x10];
8244
8245         u8         reserved_at_20[0x20];
8246
8247         u8         reserved_at_40[0x1b];
8248         u8         info_type[0x5];
8249
8250         u8         info_size[0x20];
8251
8252         u8         offset[0x20];
8253
8254         u8         reserved_at_a0[0x10];
8255         u8         data_size[0x10];
8256
8257         u8         data[0][0x20];
8258 };
8259
8260 struct mlx5_ifc_mcc_reg_bits {
8261         u8         reserved_at_0[0x4];
8262         u8         time_elapsed_since_last_cmd[0xc];
8263         u8         reserved_at_10[0x8];
8264         u8         instruction[0x8];
8265
8266         u8         reserved_at_20[0x10];
8267         u8         component_index[0x10];
8268
8269         u8         reserved_at_40[0x8];
8270         u8         update_handle[0x18];
8271
8272         u8         handle_owner_type[0x4];
8273         u8         handle_owner_host_id[0x4];
8274         u8         reserved_at_68[0x1];
8275         u8         control_progress[0x7];
8276         u8         error_code[0x8];
8277         u8         reserved_at_78[0x4];
8278         u8         control_state[0x4];
8279
8280         u8         component_size[0x20];
8281
8282         u8         reserved_at_a0[0x60];
8283 };
8284
8285 struct mlx5_ifc_mcda_reg_bits {
8286         u8         reserved_at_0[0x8];
8287         u8         update_handle[0x18];
8288
8289         u8         offset[0x20];
8290
8291         u8         reserved_at_40[0x10];
8292         u8         size[0x10];
8293
8294         u8         reserved_at_60[0x20];
8295
8296         u8         data[0][0x20];
8297 };
8298
8299 union mlx5_ifc_ports_control_registers_document_bits {
8300         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8301         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8302         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8303         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8304         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8305         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8306         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8307         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8308         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8309         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8310         struct mlx5_ifc_paos_reg_bits paos_reg;
8311         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8312         struct mlx5_ifc_peir_reg_bits peir_reg;
8313         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8314         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8315         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8316         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8317         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8318         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8319         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8320         struct mlx5_ifc_plib_reg_bits plib_reg;
8321         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8322         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8323         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8324         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8325         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8326         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8327         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8328         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8329         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8330         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8331         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8332         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8333         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8334         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8335         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8336         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8337         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8338         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8339         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8340         struct mlx5_ifc_pude_reg_bits pude_reg;
8341         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8342         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8343         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8344         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8345         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8346         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8347         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8348         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8349         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8350         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8351         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8352         u8         reserved_at_0[0x60e0];
8353 };
8354
8355 union mlx5_ifc_debug_enhancements_document_bits {
8356         struct mlx5_ifc_health_buffer_bits health_buffer;
8357         u8         reserved_at_0[0x200];
8358 };
8359
8360 union mlx5_ifc_uplink_pci_interface_document_bits {
8361         struct mlx5_ifc_initial_seg_bits initial_seg;
8362         u8         reserved_at_0[0x20060];
8363 };
8364
8365 struct mlx5_ifc_set_flow_table_root_out_bits {
8366         u8         status[0x8];
8367         u8         reserved_at_8[0x18];
8368
8369         u8         syndrome[0x20];
8370
8371         u8         reserved_at_40[0x40];
8372 };
8373
8374 struct mlx5_ifc_set_flow_table_root_in_bits {
8375         u8         opcode[0x10];
8376         u8         reserved_at_10[0x10];
8377
8378         u8         reserved_at_20[0x10];
8379         u8         op_mod[0x10];
8380
8381         u8         other_vport[0x1];
8382         u8         reserved_at_41[0xf];
8383         u8         vport_number[0x10];
8384
8385         u8         reserved_at_60[0x20];
8386
8387         u8         table_type[0x8];
8388         u8         reserved_at_88[0x18];
8389
8390         u8         reserved_at_a0[0x8];
8391         u8         table_id[0x18];
8392
8393         u8         reserved_at_c0[0x8];
8394         u8         underlay_qpn[0x18];
8395         u8         reserved_at_e0[0x120];
8396 };
8397
8398 enum {
8399         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8400         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8401 };
8402
8403 struct mlx5_ifc_modify_flow_table_out_bits {
8404         u8         status[0x8];
8405         u8         reserved_at_8[0x18];
8406
8407         u8         syndrome[0x20];
8408
8409         u8         reserved_at_40[0x40];
8410 };
8411
8412 struct mlx5_ifc_modify_flow_table_in_bits {
8413         u8         opcode[0x10];
8414         u8         reserved_at_10[0x10];
8415
8416         u8         reserved_at_20[0x10];
8417         u8         op_mod[0x10];
8418
8419         u8         other_vport[0x1];
8420         u8         reserved_at_41[0xf];
8421         u8         vport_number[0x10];
8422
8423         u8         reserved_at_60[0x10];
8424         u8         modify_field_select[0x10];
8425
8426         u8         table_type[0x8];
8427         u8         reserved_at_88[0x18];
8428
8429         u8         reserved_at_a0[0x8];
8430         u8         table_id[0x18];
8431
8432         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8433 };
8434
8435 struct mlx5_ifc_ets_tcn_config_reg_bits {
8436         u8         g[0x1];
8437         u8         b[0x1];
8438         u8         r[0x1];
8439         u8         reserved_at_3[0x9];
8440         u8         group[0x4];
8441         u8         reserved_at_10[0x9];
8442         u8         bw_allocation[0x7];
8443
8444         u8         reserved_at_20[0xc];
8445         u8         max_bw_units[0x4];
8446         u8         reserved_at_30[0x8];
8447         u8         max_bw_value[0x8];
8448 };
8449
8450 struct mlx5_ifc_ets_global_config_reg_bits {
8451         u8         reserved_at_0[0x2];
8452         u8         r[0x1];
8453         u8         reserved_at_3[0x1d];
8454
8455         u8         reserved_at_20[0xc];
8456         u8         max_bw_units[0x4];
8457         u8         reserved_at_30[0x8];
8458         u8         max_bw_value[0x8];
8459 };
8460
8461 struct mlx5_ifc_qetc_reg_bits {
8462         u8                                         reserved_at_0[0x8];
8463         u8                                         port_number[0x8];
8464         u8                                         reserved_at_10[0x30];
8465
8466         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8467         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8468 };
8469
8470 struct mlx5_ifc_qtct_reg_bits {
8471         u8         reserved_at_0[0x8];
8472         u8         port_number[0x8];
8473         u8         reserved_at_10[0xd];
8474         u8         prio[0x3];
8475
8476         u8         reserved_at_20[0x1d];
8477         u8         tclass[0x3];
8478 };
8479
8480 struct mlx5_ifc_mcia_reg_bits {
8481         u8         l[0x1];
8482         u8         reserved_at_1[0x7];
8483         u8         module[0x8];
8484         u8         reserved_at_10[0x8];
8485         u8         status[0x8];
8486
8487         u8         i2c_device_address[0x8];
8488         u8         page_number[0x8];
8489         u8         device_address[0x10];
8490
8491         u8         reserved_at_40[0x10];
8492         u8         size[0x10];
8493
8494         u8         reserved_at_60[0x20];
8495
8496         u8         dword_0[0x20];
8497         u8         dword_1[0x20];
8498         u8         dword_2[0x20];
8499         u8         dword_3[0x20];
8500         u8         dword_4[0x20];
8501         u8         dword_5[0x20];
8502         u8         dword_6[0x20];
8503         u8         dword_7[0x20];
8504         u8         dword_8[0x20];
8505         u8         dword_9[0x20];
8506         u8         dword_10[0x20];
8507         u8         dword_11[0x20];
8508 };
8509
8510 struct mlx5_ifc_dcbx_param_bits {
8511         u8         dcbx_cee_cap[0x1];
8512         u8         dcbx_ieee_cap[0x1];
8513         u8         dcbx_standby_cap[0x1];
8514         u8         reserved_at_0[0x5];
8515         u8         port_number[0x8];
8516         u8         reserved_at_10[0xa];
8517         u8         max_application_table_size[6];
8518         u8         reserved_at_20[0x15];
8519         u8         version_oper[0x3];
8520         u8         reserved_at_38[5];
8521         u8         version_admin[0x3];
8522         u8         willing_admin[0x1];
8523         u8         reserved_at_41[0x3];
8524         u8         pfc_cap_oper[0x4];
8525         u8         reserved_at_48[0x4];
8526         u8         pfc_cap_admin[0x4];
8527         u8         reserved_at_50[0x4];
8528         u8         num_of_tc_oper[0x4];
8529         u8         reserved_at_58[0x4];
8530         u8         num_of_tc_admin[0x4];
8531         u8         remote_willing[0x1];
8532         u8         reserved_at_61[3];
8533         u8         remote_pfc_cap[4];
8534         u8         reserved_at_68[0x14];
8535         u8         remote_num_of_tc[0x4];
8536         u8         reserved_at_80[0x18];
8537         u8         error[0x8];
8538         u8         reserved_at_a0[0x160];
8539 };
8540
8541 struct mlx5_ifc_lagc_bits {
8542         u8         reserved_at_0[0x1d];
8543         u8         lag_state[0x3];
8544
8545         u8         reserved_at_20[0x14];
8546         u8         tx_remap_affinity_2[0x4];
8547         u8         reserved_at_38[0x4];
8548         u8         tx_remap_affinity_1[0x4];
8549 };
8550
8551 struct mlx5_ifc_create_lag_out_bits {
8552         u8         status[0x8];
8553         u8         reserved_at_8[0x18];
8554
8555         u8         syndrome[0x20];
8556
8557         u8         reserved_at_40[0x40];
8558 };
8559
8560 struct mlx5_ifc_create_lag_in_bits {
8561         u8         opcode[0x10];
8562         u8         reserved_at_10[0x10];
8563
8564         u8         reserved_at_20[0x10];
8565         u8         op_mod[0x10];
8566
8567         struct mlx5_ifc_lagc_bits ctx;
8568 };
8569
8570 struct mlx5_ifc_modify_lag_out_bits {
8571         u8         status[0x8];
8572         u8         reserved_at_8[0x18];
8573
8574         u8         syndrome[0x20];
8575
8576         u8         reserved_at_40[0x40];
8577 };
8578
8579 struct mlx5_ifc_modify_lag_in_bits {
8580         u8         opcode[0x10];
8581         u8         reserved_at_10[0x10];
8582
8583         u8         reserved_at_20[0x10];
8584         u8         op_mod[0x10];
8585
8586         u8         reserved_at_40[0x20];
8587         u8         field_select[0x20];
8588
8589         struct mlx5_ifc_lagc_bits ctx;
8590 };
8591
8592 struct mlx5_ifc_query_lag_out_bits {
8593         u8         status[0x8];
8594         u8         reserved_at_8[0x18];
8595
8596         u8         syndrome[0x20];
8597
8598         u8         reserved_at_40[0x40];
8599
8600         struct mlx5_ifc_lagc_bits ctx;
8601 };
8602
8603 struct mlx5_ifc_query_lag_in_bits {
8604         u8         opcode[0x10];
8605         u8         reserved_at_10[0x10];
8606
8607         u8         reserved_at_20[0x10];
8608         u8         op_mod[0x10];
8609
8610         u8         reserved_at_40[0x40];
8611 };
8612
8613 struct mlx5_ifc_destroy_lag_out_bits {
8614         u8         status[0x8];
8615         u8         reserved_at_8[0x18];
8616
8617         u8         syndrome[0x20];
8618
8619         u8         reserved_at_40[0x40];
8620 };
8621
8622 struct mlx5_ifc_destroy_lag_in_bits {
8623         u8         opcode[0x10];
8624         u8         reserved_at_10[0x10];
8625
8626         u8         reserved_at_20[0x10];
8627         u8         op_mod[0x10];
8628
8629         u8         reserved_at_40[0x40];
8630 };
8631
8632 struct mlx5_ifc_create_vport_lag_out_bits {
8633         u8         status[0x8];
8634         u8         reserved_at_8[0x18];
8635
8636         u8         syndrome[0x20];
8637
8638         u8         reserved_at_40[0x40];
8639 };
8640
8641 struct mlx5_ifc_create_vport_lag_in_bits {
8642         u8         opcode[0x10];
8643         u8         reserved_at_10[0x10];
8644
8645         u8         reserved_at_20[0x10];
8646         u8         op_mod[0x10];
8647
8648         u8         reserved_at_40[0x40];
8649 };
8650
8651 struct mlx5_ifc_destroy_vport_lag_out_bits {
8652         u8         status[0x8];
8653         u8         reserved_at_8[0x18];
8654
8655         u8         syndrome[0x20];
8656
8657         u8         reserved_at_40[0x40];
8658 };
8659
8660 struct mlx5_ifc_destroy_vport_lag_in_bits {
8661         u8         opcode[0x10];
8662         u8         reserved_at_10[0x10];
8663
8664         u8         reserved_at_20[0x10];
8665         u8         op_mod[0x10];
8666
8667         u8         reserved_at_40[0x40];
8668 };
8669
8670 #endif /* MLX5_IFC_H */