include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  76 };
  77
  78 enum {
  79         MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
  80         MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_UCTX = 0x0004,
  85         MLX5_OBJ_TYPE_UMEM = 0x0005,
  86 };
  87
  88 enum {
  89         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  90         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  91         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  92         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  93         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  94         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  95         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  96         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  97         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  98         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  99         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 100         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 101         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 102         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 103         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 104         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 105         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 106         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 107         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 108         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 109         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 110         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 111         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 112         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 113         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 114         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 115         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 116         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 117         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 118         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 119         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 120         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 121         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 122         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 123         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 124         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 125         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 126         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 127         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 128         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 129         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 130         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 131         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 132         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 133         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 134         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 135         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 136         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 137         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 138         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 139         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 140         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 141         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 142         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 143         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 144         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 145         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 146         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 147         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 148         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 149         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 150         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 151         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 152         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 153         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 154         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 155         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 156         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 157         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 158         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 159         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 160         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 161         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 162         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 163         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 164         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 165         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 166         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 167         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 168         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 169         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 170         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 171         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 172         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 173         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 174         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 175         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 176         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 177         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 178         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 179         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 180         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 181         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 182         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 183         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 184         MLX5_CMD_OP_NOP                           = 0x80d,
 185         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 186         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 187         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 188         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 189         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 190         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 191         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 192         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 193         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 194         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 195         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 196         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 197         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 198         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 199         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 200         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 201         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 202         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 203         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 204         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 205         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 206         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 207         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 208         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 209         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 210         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 211         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 212         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 213         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 214         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 215         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 216         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 217         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 218         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 219         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 220         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 221         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 222         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 223         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 224         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 225         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 226         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 227         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 228         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 229         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 230         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 231         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 232         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 233         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 234         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 235         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 236         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 237         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 238         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 239         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 240         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 241         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 242         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 243         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 244         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 245         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 246         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 247         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 248         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 249         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 250         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 251         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 252         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 253         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 254         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 255         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 256         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 257         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 258         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 259         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 260         MLX5_CMD_OP_MAX
 261 };
 262
 263 struct mlx5_ifc_flow_table_fields_supported_bits {
 264         u8         outer_dmac[0x1];
 265         u8         outer_smac[0x1];
 266         u8         outer_ether_type[0x1];
 267         u8         outer_ip_version[0x1];
 268         u8         outer_first_prio[0x1];
 269         u8         outer_first_cfi[0x1];
 270         u8         outer_first_vid[0x1];
 271         u8         outer_ipv4_ttl[0x1];
 272         u8         outer_second_prio[0x1];
 273         u8         outer_second_cfi[0x1];
 274         u8         outer_second_vid[0x1];
 275         u8         reserved_at_b[0x1];
 276         u8         outer_sip[0x1];
 277         u8         outer_dip[0x1];
 278         u8         outer_frag[0x1];
 279         u8         outer_ip_protocol[0x1];
 280         u8         outer_ip_ecn[0x1];
 281         u8         outer_ip_dscp[0x1];
 282         u8         outer_udp_sport[0x1];
 283         u8         outer_udp_dport[0x1];
 284         u8         outer_tcp_sport[0x1];
 285         u8         outer_tcp_dport[0x1];
 286         u8         outer_tcp_flags[0x1];
 287         u8         outer_gre_protocol[0x1];
 288         u8         outer_gre_key[0x1];
 289         u8         outer_vxlan_vni[0x1];
 290         u8         reserved_at_1a[0x5];
 291         u8         source_eswitch_port[0x1];
 292
 293         u8         inner_dmac[0x1];
 294         u8         inner_smac[0x1];
 295         u8         inner_ether_type[0x1];
 296         u8         inner_ip_version[0x1];
 297         u8         inner_first_prio[0x1];
 298         u8         inner_first_cfi[0x1];
 299         u8         inner_first_vid[0x1];
 300         u8         reserved_at_27[0x1];
 301         u8         inner_second_prio[0x1];
 302         u8         inner_second_cfi[0x1];
 303         u8         inner_second_vid[0x1];
 304         u8         reserved_at_2b[0x1];
 305         u8         inner_sip[0x1];
 306         u8         inner_dip[0x1];
 307         u8         inner_frag[0x1];
 308         u8         inner_ip_protocol[0x1];
 309         u8         inner_ip_ecn[0x1];
 310         u8         inner_ip_dscp[0x1];
 311         u8         inner_udp_sport[0x1];
 312         u8         inner_udp_dport[0x1];
 313         u8         inner_tcp_sport[0x1];
 314         u8         inner_tcp_dport[0x1];
 315         u8         inner_tcp_flags[0x1];
 316         u8         reserved_at_37[0x9];
 317
 318         u8         reserved_at_40[0x5];
 319         u8         outer_first_mpls_over_udp[0x4];
 320         u8         outer_first_mpls_over_gre[0x4];
 321         u8         inner_first_mpls[0x4];
 322         u8         outer_first_mpls[0x4];
 323         u8         reserved_at_55[0x2];
 324         u8         outer_esp_spi[0x1];
 325         u8         reserved_at_58[0x2];
 326         u8         bth_dst_qp[0x1];
 327
 328         u8         reserved_at_5b[0x25];
 329 };
 330
 331 struct mlx5_ifc_flow_table_prop_layout_bits {
 332         u8         ft_support[0x1];
 333         u8         reserved_at_1[0x1];
 334         u8         flow_counter[0x1];
 335         u8         flow_modify_en[0x1];
 336         u8         modify_root[0x1];
 337         u8         identified_miss_table_mode[0x1];
 338         u8         flow_table_modify[0x1];
 339         u8         encap[0x1];
 340         u8         decap[0x1];
 341         u8         reserved_at_9[0x1];
 342         u8         pop_vlan[0x1];
 343         u8         push_vlan[0x1];
 344         u8         reserved_at_c[0x1];
 345         u8         pop_vlan_2[0x1];
 346         u8         push_vlan_2[0x1];
 347         u8         reserved_at_f[0x11];
 348
 349         u8         reserved_at_20[0x2];
 350         u8         log_max_ft_size[0x6];
 351         u8         log_max_modify_header_context[0x8];
 352         u8         max_modify_header_actions[0x8];
 353         u8         max_ft_level[0x8];
 354
 355         u8         reserved_at_40[0x20];
 356
 357         u8         reserved_at_60[0x18];
 358         u8         log_max_ft_num[0x8];
 359
 360         u8         reserved_at_80[0x18];
 361         u8         log_max_destination[0x8];
 362
 363         u8         log_max_flow_counter[0x8];
 364         u8         reserved_at_a8[0x10];
 365         u8         log_max_flow[0x8];
 366
 367         u8         reserved_at_c0[0x40];
 368
 369         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 370
 371         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 372 };
 373
 374 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 375         u8         send[0x1];
 376         u8         receive[0x1];
 377         u8         write[0x1];
 378         u8         read[0x1];
 379         u8         atomic[0x1];
 380         u8         srq_receive[0x1];
 381         u8         reserved_at_6[0x1a];
 382 };
 383
 384 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 385         u8         smac_47_16[0x20];
 386
 387         u8         smac_15_0[0x10];
 388         u8         ethertype[0x10];
 389
 390         u8         dmac_47_16[0x20];
 391
 392         u8         dmac_15_0[0x10];
 393         u8         first_prio[0x3];
 394         u8         first_cfi[0x1];
 395         u8         first_vid[0xc];
 396
 397         u8         ip_protocol[0x8];
 398         u8         ip_dscp[0x6];
 399         u8         ip_ecn[0x2];
 400         u8         cvlan_tag[0x1];
 401         u8         svlan_tag[0x1];
 402         u8         frag[0x1];
 403         u8         ip_version[0x4];
 404         u8         tcp_flags[0x9];
 405
 406         u8         tcp_sport[0x10];
 407         u8         tcp_dport[0x10];
 408
 409         u8         reserved_at_c0[0x18];
 410         u8         ttl_hoplimit[0x8];
 411
 412         u8         udp_sport[0x10];
 413         u8         udp_dport[0x10];
 414
 415         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 416
 417         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 418 };
 419
 420 struct mlx5_ifc_fte_match_set_misc_bits {
 421         u8         reserved_at_0[0x8];
 422         u8         source_sqn[0x18];
 423
 424         u8         source_eswitch_owner_vhca_id[0x10];
 425         u8         source_port[0x10];
 426
 427         u8         outer_second_prio[0x3];
 428         u8         outer_second_cfi[0x1];
 429         u8         outer_second_vid[0xc];
 430         u8         inner_second_prio[0x3];
 431         u8         inner_second_cfi[0x1];
 432         u8         inner_second_vid[0xc];
 433
 434         u8         outer_second_cvlan_tag[0x1];
 435         u8         inner_second_cvlan_tag[0x1];
 436         u8         outer_second_svlan_tag[0x1];
 437         u8         inner_second_svlan_tag[0x1];
 438         u8         reserved_at_64[0xc];
 439         u8         gre_protocol[0x10];
 440
 441         u8         gre_key_h[0x18];
 442         u8         gre_key_l[0x8];
 443
 444         u8         vxlan_vni[0x18];
 445         u8         reserved_at_b8[0x8];
 446
 447         u8         reserved_at_c0[0x20];
 448
 449         u8         reserved_at_e0[0xc];
 450         u8         outer_ipv6_flow_label[0x14];
 451
 452         u8         reserved_at_100[0xc];
 453         u8         inner_ipv6_flow_label[0x14];
 454
 455         u8         reserved_at_120[0x28];
 456         u8         bth_dst_qp[0x18];
 457         u8         reserved_at_160[0x20];
 458         u8         outer_esp_spi[0x20];
 459         u8         reserved_at_1a0[0x60];
 460 };
 461
 462 struct mlx5_ifc_fte_match_mpls_bits {
 463         u8         mpls_label[0x14];
 464         u8         mpls_exp[0x3];
 465         u8         mpls_s_bos[0x1];
 466         u8         mpls_ttl[0x8];
 467 };
 468
 469 struct mlx5_ifc_fte_match_set_misc2_bits {
 470         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 471
 472         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 473
 474         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 475
 476         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 477
 478         u8         reserved_at_80[0x100];
 479
 480         u8         metadata_reg_a[0x20];
 481
 482         u8         reserved_at_1a0[0x60];
 483 };
 484
 485 struct mlx5_ifc_cmd_pas_bits {
 486         u8         pa_h[0x20];
 487
 488         u8         pa_l[0x14];
 489         u8         reserved_at_34[0xc];
 490 };
 491
 492 struct mlx5_ifc_uint64_bits {
 493         u8         hi[0x20];
 494
 495         u8         lo[0x20];
 496 };
 497
 498 enum {
 499         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 500         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 501         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 502         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 503         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 504         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 505         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 506         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 507         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 508         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 509 };
 510
 511 struct mlx5_ifc_ads_bits {
 512         u8         fl[0x1];
 513         u8         free_ar[0x1];
 514         u8         reserved_at_2[0xe];
 515         u8         pkey_index[0x10];
 516
 517         u8         reserved_at_20[0x8];
 518         u8         grh[0x1];
 519         u8         mlid[0x7];
 520         u8         rlid[0x10];
 521
 522         u8         ack_timeout[0x5];
 523         u8         reserved_at_45[0x3];
 524         u8         src_addr_index[0x8];
 525         u8         reserved_at_50[0x4];
 526         u8         stat_rate[0x4];
 527         u8         hop_limit[0x8];
 528
 529         u8         reserved_at_60[0x4];
 530         u8         tclass[0x8];
 531         u8         flow_label[0x14];
 532
 533         u8         rgid_rip[16][0x8];
 534
 535         u8         reserved_at_100[0x4];
 536         u8         f_dscp[0x1];
 537         u8         f_ecn[0x1];
 538         u8         reserved_at_106[0x1];
 539         u8         f_eth_prio[0x1];
 540         u8         ecn[0x2];
 541         u8         dscp[0x6];
 542         u8         udp_sport[0x10];
 543
 544         u8         dei_cfi[0x1];
 545         u8         eth_prio[0x3];
 546         u8         sl[0x4];
 547         u8         vhca_port_num[0x8];
 548         u8         rmac_47_32[0x10];
 549
 550         u8         rmac_31_0[0x20];
 551 };
 552
 553 struct mlx5_ifc_flow_table_nic_cap_bits {
 554         u8         nic_rx_multi_path_tirs[0x1];
 555         u8         nic_rx_multi_path_tirs_fts[0x1];
 556         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 557         u8         reserved_at_3[0x1fd];
 558
 559         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 560
 561         u8         reserved_at_400[0x200];
 562
 563         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 564
 565         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 566
 567         u8         reserved_at_a00[0x200];
 568
 569         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 570
 571         u8         reserved_at_e00[0x7200];
 572 };
 573
 574 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 575         u8      reserved_at_0[0x1c];
 576         u8      fdb_multi_path_to_table[0x1];
 577         u8      reserved_at_1d[0x1e3];
 578
 579         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 580
 581         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 582
 583         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 584
 585         u8      reserved_at_800[0x7800];
 586 };
 587
 588 struct mlx5_ifc_e_switch_cap_bits {
 589         u8         vport_svlan_strip[0x1];
 590         u8         vport_cvlan_strip[0x1];
 591         u8         vport_svlan_insert[0x1];
 592         u8         vport_cvlan_insert_if_not_exist[0x1];
 593         u8         vport_cvlan_insert_overwrite[0x1];
 594         u8         reserved_at_5[0x18];
 595         u8         merged_eswitch[0x1];
 596         u8         nic_vport_node_guid_modify[0x1];
 597         u8         nic_vport_port_guid_modify[0x1];
 598
 599         u8         vxlan_encap_decap[0x1];
 600         u8         nvgre_encap_decap[0x1];
 601         u8         reserved_at_22[0x9];
 602         u8         log_max_encap_headers[0x5];
 603         u8         reserved_2b[0x6];
 604         u8         max_encap_header_size[0xa];
 605
 606         u8         reserved_40[0x7c0];
 607
 608 };
 609
 610 struct mlx5_ifc_qos_cap_bits {
 611         u8         packet_pacing[0x1];
 612         u8         esw_scheduling[0x1];
 613         u8         esw_bw_share[0x1];
 614         u8         esw_rate_limit[0x1];
 615         u8         reserved_at_4[0x1];
 616         u8         packet_pacing_burst_bound[0x1];
 617         u8         packet_pacing_typical_size[0x1];
 618         u8         reserved_at_7[0x19];
 619
 620         u8         reserved_at_20[0x20];
 621
 622         u8         packet_pacing_max_rate[0x20];
 623
 624         u8         packet_pacing_min_rate[0x20];
 625
 626         u8         reserved_at_80[0x10];
 627         u8         packet_pacing_rate_table_size[0x10];
 628
 629         u8         esw_element_type[0x10];
 630         u8         esw_tsar_type[0x10];
 631
 632         u8         reserved_at_c0[0x10];
 633         u8         max_qos_para_vport[0x10];
 634
 635         u8         max_tsar_bw_share[0x20];
 636
 637         u8         reserved_at_100[0x700];
 638 };
 639
 640 struct mlx5_ifc_debug_cap_bits {
 641         u8         reserved_at_0[0x20];
 642
 643         u8         reserved_at_20[0x2];
 644         u8         stall_detect[0x1];
 645         u8         reserved_at_23[0x1d];
 646
 647         u8         reserved_at_40[0x7c0];
 648 };
 649
 650 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 651         u8         csum_cap[0x1];
 652         u8         vlan_cap[0x1];
 653         u8         lro_cap[0x1];
 654         u8         lro_psh_flag[0x1];
 655         u8         lro_time_stamp[0x1];
 656         u8         reserved_at_5[0x2];
 657         u8         wqe_vlan_insert[0x1];
 658         u8         self_lb_en_modifiable[0x1];
 659         u8         reserved_at_9[0x2];
 660         u8         max_lso_cap[0x5];
 661         u8         multi_pkt_send_wqe[0x2];
 662         u8         wqe_inline_mode[0x2];
 663         u8         rss_ind_tbl_cap[0x4];
 664         u8         reg_umr_sq[0x1];
 665         u8         scatter_fcs[0x1];
 666         u8         enhanced_multi_pkt_send_wqe[0x1];
 667         u8         tunnel_lso_const_out_ip_id[0x1];
 668         u8         reserved_at_1c[0x2];
 669         u8         tunnel_stateless_gre[0x1];
 670         u8         tunnel_stateless_vxlan[0x1];
 671
 672         u8         swp[0x1];
 673         u8         swp_csum[0x1];
 674         u8         swp_lso[0x1];
 675         u8         reserved_at_23[0x1b];
 676         u8         max_geneve_opt_len[0x1];
 677         u8         tunnel_stateless_geneve_rx[0x1];
 678
 679         u8         reserved_at_40[0x10];
 680         u8         lro_min_mss_size[0x10];
 681
 682         u8         reserved_at_60[0x120];
 683
 684         u8         lro_timer_supported_periods[4][0x20];
 685
 686         u8         reserved_at_200[0x600];
 687 };
 688
 689 struct mlx5_ifc_roce_cap_bits {
 690         u8         roce_apm[0x1];
 691         u8         reserved_at_1[0x1f];
 692
 693         u8         reserved_at_20[0x60];
 694
 695         u8         reserved_at_80[0xc];
 696         u8         l3_type[0x4];
 697         u8         reserved_at_90[0x8];
 698         u8         roce_version[0x8];
 699
 700         u8         reserved_at_a0[0x10];
 701         u8         r_roce_dest_udp_port[0x10];
 702
 703         u8         r_roce_max_src_udp_port[0x10];
 704         u8         r_roce_min_src_udp_port[0x10];
 705
 706         u8         reserved_at_e0[0x10];
 707         u8         roce_address_table_size[0x10];
 708
 709         u8         reserved_at_100[0x700];
 710 };
 711
 712 struct mlx5_ifc_device_mem_cap_bits {
 713         u8         memic[0x1];
 714         u8         reserved_at_1[0x1f];
 715
 716         u8         reserved_at_20[0xb];
 717         u8         log_min_memic_alloc_size[0x5];
 718         u8         reserved_at_30[0x8];
 719         u8         log_max_memic_addr_alignment[0x8];
 720
 721         u8         memic_bar_start_addr[0x40];
 722
 723         u8         memic_bar_size[0x20];
 724
 725         u8         max_memic_size[0x20];
 726
 727         u8         reserved_at_c0[0x740];
 728 };
 729
 730 enum {
 731         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 732         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 733         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 734         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 735         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 736         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 737         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 738         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 739         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 740 };
 741
 742 enum {
 743         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 744         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 745         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 746         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 747         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 748         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 749         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 750         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 751         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 752 };
 753
 754 struct mlx5_ifc_atomic_caps_bits {
 755         u8         reserved_at_0[0x40];
 756
 757         u8         atomic_req_8B_endianness_mode[0x2];
 758         u8         reserved_at_42[0x4];
 759         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 760
 761         u8         reserved_at_47[0x19];
 762
 763         u8         reserved_at_60[0x20];
 764
 765         u8         reserved_at_80[0x10];
 766         u8         atomic_operations[0x10];
 767
 768         u8         reserved_at_a0[0x10];
 769         u8         atomic_size_qp[0x10];
 770
 771         u8         reserved_at_c0[0x10];
 772         u8         atomic_size_dc[0x10];
 773
 774         u8         reserved_at_e0[0x720];
 775 };
 776
 777 struct mlx5_ifc_odp_cap_bits {
 778         u8         reserved_at_0[0x40];
 779
 780         u8         sig[0x1];
 781         u8         reserved_at_41[0x1f];
 782
 783         u8         reserved_at_60[0x20];
 784
 785         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 786
 787         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 788
 789         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 790
 791         u8         reserved_at_e0[0x720];
 792 };
 793
 794 struct mlx5_ifc_calc_op {
 795         u8        reserved_at_0[0x10];
 796         u8        reserved_at_10[0x9];
 797         u8        op_swap_endianness[0x1];
 798         u8        op_min[0x1];
 799         u8        op_xor[0x1];
 800         u8        op_or[0x1];
 801         u8        op_and[0x1];
 802         u8        op_max[0x1];
 803         u8        op_add[0x1];
 804 };
 805
 806 struct mlx5_ifc_vector_calc_cap_bits {
 807         u8         calc_matrix[0x1];
 808         u8         reserved_at_1[0x1f];
 809         u8         reserved_at_20[0x8];
 810         u8         max_vec_count[0x8];
 811         u8         reserved_at_30[0xd];
 812         u8         max_chunk_size[0x3];
 813         struct mlx5_ifc_calc_op calc0;
 814         struct mlx5_ifc_calc_op calc1;
 815         struct mlx5_ifc_calc_op calc2;
 816         struct mlx5_ifc_calc_op calc3;
 817
 818         u8         reserved_at_e0[0x720];
 819 };
 820
 821 enum {
 822         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 823         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 824         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 825         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 826 };
 827
 828 enum {
 829         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 830         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 831 };
 832
 833 enum {
 834         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 835         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 836         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 837         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 838         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 839 };
 840
 841 enum {
 842         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 843         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 844         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 845         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 846         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 847         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 848 };
 849
 850 enum {
 851         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 852         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 853 };
 854
 855 enum {
 856         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 857         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 858         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 859 };
 860
 861 enum {
 862         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 863         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 864 };
 865
 866 enum {
 867         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 868         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 869         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 870 };
 871
 872 struct mlx5_ifc_cmd_hca_cap_bits {
 873         u8         reserved_at_0[0x30];
 874         u8         vhca_id[0x10];
 875
 876         u8         reserved_at_40[0x40];
 877
 878         u8         log_max_srq_sz[0x8];
 879         u8         log_max_qp_sz[0x8];
 880         u8         reserved_at_90[0xb];
 881         u8         log_max_qp[0x5];
 882
 883         u8         reserved_at_a0[0xb];
 884         u8         log_max_srq[0x5];
 885         u8         reserved_at_b0[0x10];
 886
 887         u8         reserved_at_c0[0x8];
 888         u8         log_max_cq_sz[0x8];
 889         u8         reserved_at_d0[0xb];
 890         u8         log_max_cq[0x5];
 891
 892         u8         log_max_eq_sz[0x8];
 893         u8         reserved_at_e8[0x2];
 894         u8         log_max_mkey[0x6];
 895         u8         reserved_at_f0[0x8];
 896         u8         dump_fill_mkey[0x1];
 897         u8         reserved_at_f9[0x3];
 898         u8         log_max_eq[0x4];
 899
 900         u8         max_indirection[0x8];
 901         u8         fixed_buffer_size[0x1];
 902         u8         log_max_mrw_sz[0x7];
 903         u8         force_teardown[0x1];
 904         u8         reserved_at_111[0x1];
 905         u8         log_max_bsf_list_size[0x6];
 906         u8         umr_extended_translation_offset[0x1];
 907         u8         null_mkey[0x1];
 908         u8         log_max_klm_list_size[0x6];
 909
 910         u8         reserved_at_120[0xa];
 911         u8         log_max_ra_req_dc[0x6];
 912         u8         reserved_at_130[0xa];
 913         u8         log_max_ra_res_dc[0x6];
 914
 915         u8         reserved_at_140[0xa];
 916         u8         log_max_ra_req_qp[0x6];
 917         u8         reserved_at_150[0xa];
 918         u8         log_max_ra_res_qp[0x6];
 919
 920         u8         end_pad[0x1];
 921         u8         cc_query_allowed[0x1];
 922         u8         cc_modify_allowed[0x1];
 923         u8         start_pad[0x1];
 924         u8         cache_line_128byte[0x1];
 925         u8         reserved_at_165[0xa];
 926         u8         qcam_reg[0x1];
 927         u8         gid_table_size[0x10];
 928
 929         u8         out_of_seq_cnt[0x1];
 930         u8         vport_counters[0x1];
 931         u8         retransmission_q_counters[0x1];
 932         u8         debug[0x1];
 933         u8         modify_rq_counter_set_id[0x1];
 934         u8         rq_delay_drop[0x1];
 935         u8         max_qp_cnt[0xa];
 936         u8         pkey_table_size[0x10];
 937
 938         u8         vport_group_manager[0x1];
 939         u8         vhca_group_manager[0x1];
 940         u8         ib_virt[0x1];
 941         u8         eth_virt[0x1];
 942         u8         vnic_env_queue_counters[0x1];
 943         u8         ets[0x1];
 944         u8         nic_flow_table[0x1];
 945         u8         eswitch_manager[0x1];
 946         u8         device_memory[0x1];
 947         u8         mcam_reg[0x1];
 948         u8         pcam_reg[0x1];
 949         u8         local_ca_ack_delay[0x5];
 950         u8         port_module_event[0x1];
 951         u8         enhanced_error_q_counters[0x1];
 952         u8         ports_check[0x1];
 953         u8         reserved_at_1b3[0x1];
 954         u8         disable_link_up[0x1];
 955         u8         beacon_led[0x1];
 956         u8         port_type[0x2];
 957         u8         num_ports[0x8];
 958
 959         u8         reserved_at_1c0[0x1];
 960         u8         pps[0x1];
 961         u8         pps_modify[0x1];
 962         u8         log_max_msg[0x5];
 963         u8         reserved_at_1c8[0x4];
 964         u8         max_tc[0x4];
 965         u8         temp_warn_event[0x1];
 966         u8         dcbx[0x1];
 967         u8         general_notification_event[0x1];
 968         u8         reserved_at_1d3[0x2];
 969         u8         fpga[0x1];
 970         u8         rol_s[0x1];
 971         u8         rol_g[0x1];
 972         u8         reserved_at_1d8[0x1];
 973         u8         wol_s[0x1];
 974         u8         wol_g[0x1];
 975         u8         wol_a[0x1];
 976         u8         wol_b[0x1];
 977         u8         wol_m[0x1];
 978         u8         wol_u[0x1];
 979         u8         wol_p[0x1];
 980
 981         u8         stat_rate_support[0x10];
 982         u8         reserved_at_1f0[0xc];
 983         u8         cqe_version[0x4];
 984
 985         u8         compact_address_vector[0x1];
 986         u8         striding_rq[0x1];
 987         u8         reserved_at_202[0x1];
 988         u8         ipoib_enhanced_offloads[0x1];
 989         u8         ipoib_basic_offloads[0x1];
 990         u8         reserved_at_205[0x1];
 991         u8         repeated_block_disabled[0x1];
 992         u8         umr_modify_entity_size_disabled[0x1];
 993         u8         umr_modify_atomic_disabled[0x1];
 994         u8         umr_indirect_mkey_disabled[0x1];
 995         u8         umr_fence[0x2];
 996         u8         reserved_at_20c[0x3];
 997         u8         drain_sigerr[0x1];
 998         u8         cmdif_checksum[0x2];
 999         u8         sigerr_cqe[0x1];
1000         u8         reserved_at_213[0x1];
1001         u8         wq_signature[0x1];
1002         u8         sctr_data_cqe[0x1];
1003         u8         reserved_at_216[0x1];
1004         u8         sho[0x1];
1005         u8         tph[0x1];
1006         u8         rf[0x1];
1007         u8         dct[0x1];
1008         u8         qos[0x1];
1009         u8         eth_net_offloads[0x1];
1010         u8         roce[0x1];
1011         u8         atomic[0x1];
1012         u8         reserved_at_21f[0x1];
1013
1014         u8         cq_oi[0x1];
1015         u8         cq_resize[0x1];
1016         u8         cq_moderation[0x1];
1017         u8         reserved_at_223[0x3];
1018         u8         cq_eq_remap[0x1];
1019         u8         pg[0x1];
1020         u8         block_lb_mc[0x1];
1021         u8         reserved_at_229[0x1];
1022         u8         scqe_break_moderation[0x1];
1023         u8         cq_period_start_from_cqe[0x1];
1024         u8         cd[0x1];
1025         u8         reserved_at_22d[0x1];
1026         u8         apm[0x1];
1027         u8         vector_calc[0x1];
1028         u8         umr_ptr_rlky[0x1];
1029         u8         imaicl[0x1];
1030         u8         reserved_at_232[0x4];
1031         u8         qkv[0x1];
1032         u8         pkv[0x1];
1033         u8         set_deth_sqpn[0x1];
1034         u8         reserved_at_239[0x3];
1035         u8         xrc[0x1];
1036         u8         ud[0x1];
1037         u8         uc[0x1];
1038         u8         rc[0x1];
1039
1040         u8         uar_4k[0x1];
1041         u8         reserved_at_241[0x9];
1042         u8         uar_sz[0x6];
1043         u8         reserved_at_250[0x8];
1044         u8         log_pg_sz[0x8];
1045
1046         u8         bf[0x1];
1047         u8         driver_version[0x1];
1048         u8         pad_tx_eth_packet[0x1];
1049         u8         reserved_at_263[0x8];
1050         u8         log_bf_reg_size[0x5];
1051
1052         u8         reserved_at_270[0xb];
1053         u8         lag_master[0x1];
1054         u8         num_lag_ports[0x4];
1055
1056         u8         reserved_at_280[0x10];
1057         u8         max_wqe_sz_sq[0x10];
1058
1059         u8         reserved_at_2a0[0x10];
1060         u8         max_wqe_sz_rq[0x10];
1061
1062         u8         max_flow_counter_31_16[0x10];
1063         u8         max_wqe_sz_sq_dc[0x10];
1064
1065         u8         reserved_at_2e0[0x7];
1066         u8         max_qp_mcg[0x19];
1067
1068         u8         reserved_at_300[0x18];
1069         u8         log_max_mcg[0x8];
1070
1071         u8         reserved_at_320[0x3];
1072         u8         log_max_transport_domain[0x5];
1073         u8         reserved_at_328[0x3];
1074         u8         log_max_pd[0x5];
1075         u8         reserved_at_330[0xb];
1076         u8         log_max_xrcd[0x5];
1077
1078         u8         nic_receive_steering_discard[0x1];
1079         u8         receive_discard_vport_down[0x1];
1080         u8         transmit_discard_vport_down[0x1];
1081         u8         reserved_at_343[0x5];
1082         u8         log_max_flow_counter_bulk[0x8];
1083         u8         max_flow_counter_15_0[0x10];
1084
1085
1086         u8         reserved_at_360[0x3];
1087         u8         log_max_rq[0x5];
1088         u8         reserved_at_368[0x3];
1089         u8         log_max_sq[0x5];
1090         u8         reserved_at_370[0x3];
1091         u8         log_max_tir[0x5];
1092         u8         reserved_at_378[0x3];
1093         u8         log_max_tis[0x5];
1094
1095         u8         basic_cyclic_rcv_wqe[0x1];
1096         u8         reserved_at_381[0x2];
1097         u8         log_max_rmp[0x5];
1098         u8         reserved_at_388[0x3];
1099         u8         log_max_rqt[0x5];
1100         u8         reserved_at_390[0x3];
1101         u8         log_max_rqt_size[0x5];
1102         u8         reserved_at_398[0x3];
1103         u8         log_max_tis_per_sq[0x5];
1104
1105         u8         ext_stride_num_range[0x1];
1106         u8         reserved_at_3a1[0x2];
1107         u8         log_max_stride_sz_rq[0x5];
1108         u8         reserved_at_3a8[0x3];
1109         u8         log_min_stride_sz_rq[0x5];
1110         u8         reserved_at_3b0[0x3];
1111         u8         log_max_stride_sz_sq[0x5];
1112         u8         reserved_at_3b8[0x3];
1113         u8         log_min_stride_sz_sq[0x5];
1114
1115         u8         hairpin[0x1];
1116         u8         reserved_at_3c1[0x2];
1117         u8         log_max_hairpin_queues[0x5];
1118         u8         reserved_at_3c8[0x3];
1119         u8         log_max_hairpin_wq_data_sz[0x5];
1120         u8         reserved_at_3d0[0x3];
1121         u8         log_max_hairpin_num_packets[0x5];
1122         u8         reserved_at_3d8[0x3];
1123         u8         log_max_wq_sz[0x5];
1124
1125         u8         nic_vport_change_event[0x1];
1126         u8         disable_local_lb_uc[0x1];
1127         u8         disable_local_lb_mc[0x1];
1128         u8         log_min_hairpin_wq_data_sz[0x5];
1129         u8         reserved_at_3e8[0x3];
1130         u8         log_max_vlan_list[0x5];
1131         u8         reserved_at_3f0[0x3];
1132         u8         log_max_current_mc_list[0x5];
1133         u8         reserved_at_3f8[0x3];
1134         u8         log_max_current_uc_list[0x5];
1135
1136         u8         general_obj_types[0x40];
1137
1138         u8         reserved_at_440[0x40];
1139
1140         u8         reserved_at_480[0x3];
1141         u8         log_max_l2_table[0x5];
1142         u8         reserved_at_488[0x8];
1143         u8         log_uar_page_sz[0x10];
1144
1145         u8         reserved_at_4a0[0x20];
1146         u8         device_frequency_mhz[0x20];
1147         u8         device_frequency_khz[0x20];
1148
1149         u8         reserved_at_500[0x20];
1150         u8         num_of_uars_per_page[0x20];
1151
1152         u8         flex_parser_protocols[0x20];
1153         u8         reserved_at_560[0x20];
1154
1155         u8         reserved_at_580[0x3c];
1156         u8         mini_cqe_resp_stride_index[0x1];
1157         u8         cqe_128_always[0x1];
1158         u8         cqe_compression_128[0x1];
1159         u8         cqe_compression[0x1];
1160
1161         u8         cqe_compression_timeout[0x10];
1162         u8         cqe_compression_max_num[0x10];
1163
1164         u8         reserved_at_5e0[0x10];
1165         u8         tag_matching[0x1];
1166         u8         rndv_offload_rc[0x1];
1167         u8         rndv_offload_dc[0x1];
1168         u8         log_tag_matching_list_sz[0x5];
1169         u8         reserved_at_5f8[0x3];
1170         u8         log_max_xrq[0x5];
1171
1172         u8         affiliate_nic_vport_criteria[0x8];
1173         u8         native_port_num[0x8];
1174         u8         num_vhca_ports[0x8];
1175         u8         reserved_at_618[0x6];
1176         u8         sw_owner_id[0x1];
1177         u8         reserved_at_61f[0x1e1];
1178 };
1179
1180 enum mlx5_flow_destination_type {
1181         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1182         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1183         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1184
1185         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1186         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1187         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1188 };
1189
1190 struct mlx5_ifc_dest_format_struct_bits {
1191         u8         destination_type[0x8];
1192         u8         destination_id[0x18];
1193         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1194         u8         reserved_at_21[0xf];
1195         u8         destination_eswitch_owner_vhca_id[0x10];
1196 };
1197
1198 struct mlx5_ifc_flow_counter_list_bits {
1199         u8         flow_counter_id[0x20];
1200
1201         u8         reserved_at_20[0x20];
1202 };
1203
1204 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1205         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1206         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1207         u8         reserved_at_0[0x40];
1208 };
1209
1210 struct mlx5_ifc_fte_match_param_bits {
1211         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1212
1213         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1214
1215         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1216
1217         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1218
1219         u8         reserved_at_800[0x800];
1220 };
1221
1222 enum {
1223         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1224         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1225         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1226         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1227         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1228 };
1229
1230 struct mlx5_ifc_rx_hash_field_select_bits {
1231         u8         l3_prot_type[0x1];
1232         u8         l4_prot_type[0x1];
1233         u8         selected_fields[0x1e];
1234 };
1235
1236 enum {
1237         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1238         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1239 };
1240
1241 enum {
1242         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1243         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1244 };
1245
1246 struct mlx5_ifc_wq_bits {
1247         u8         wq_type[0x4];
1248         u8         wq_signature[0x1];
1249         u8         end_padding_mode[0x2];
1250         u8         cd_slave[0x1];
1251         u8         reserved_at_8[0x18];
1252
1253         u8         hds_skip_first_sge[0x1];
1254         u8         log2_hds_buf_size[0x3];
1255         u8         reserved_at_24[0x7];
1256         u8         page_offset[0x5];
1257         u8         lwm[0x10];
1258
1259         u8         reserved_at_40[0x8];
1260         u8         pd[0x18];
1261
1262         u8         reserved_at_60[0x8];
1263         u8         uar_page[0x18];
1264
1265         u8         dbr_addr[0x40];
1266
1267         u8         hw_counter[0x20];
1268
1269         u8         sw_counter[0x20];
1270
1271         u8         reserved_at_100[0xc];
1272         u8         log_wq_stride[0x4];
1273         u8         reserved_at_110[0x3];
1274         u8         log_wq_pg_sz[0x5];
1275         u8         reserved_at_118[0x3];
1276         u8         log_wq_sz[0x5];
1277
1278         u8         reserved_at_120[0x3];
1279         u8         log_hairpin_num_packets[0x5];
1280         u8         reserved_at_128[0x3];
1281         u8         log_hairpin_data_sz[0x5];
1282
1283         u8         reserved_at_130[0x4];
1284         u8         log_wqe_num_of_strides[0x4];
1285         u8         two_byte_shift_en[0x1];
1286         u8         reserved_at_139[0x4];
1287         u8         log_wqe_stride_size[0x3];
1288
1289         u8         reserved_at_140[0x4c0];
1290
1291         struct mlx5_ifc_cmd_pas_bits pas[0];
1292 };
1293
1294 struct mlx5_ifc_rq_num_bits {
1295         u8         reserved_at_0[0x8];
1296         u8         rq_num[0x18];
1297 };
1298
1299 struct mlx5_ifc_mac_address_layout_bits {
1300         u8         reserved_at_0[0x10];
1301         u8         mac_addr_47_32[0x10];
1302
1303         u8         mac_addr_31_0[0x20];
1304 };
1305
1306 struct mlx5_ifc_vlan_layout_bits {
1307         u8         reserved_at_0[0x14];
1308         u8         vlan[0x0c];
1309
1310         u8         reserved_at_20[0x20];
1311 };
1312
1313 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1314         u8         reserved_at_0[0xa0];
1315
1316         u8         min_time_between_cnps[0x20];
1317
1318         u8         reserved_at_c0[0x12];
1319         u8         cnp_dscp[0x6];
1320         u8         reserved_at_d8[0x4];
1321         u8         cnp_prio_mode[0x1];
1322         u8         cnp_802p_prio[0x3];
1323
1324         u8         reserved_at_e0[0x720];
1325 };
1326
1327 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1328         u8         reserved_at_0[0x60];
1329
1330         u8         reserved_at_60[0x4];
1331         u8         clamp_tgt_rate[0x1];
1332         u8         reserved_at_65[0x3];
1333         u8         clamp_tgt_rate_after_time_inc[0x1];
1334         u8         reserved_at_69[0x17];
1335
1336         u8         reserved_at_80[0x20];
1337
1338         u8         rpg_time_reset[0x20];
1339
1340         u8         rpg_byte_reset[0x20];
1341
1342         u8         rpg_threshold[0x20];
1343
1344         u8         rpg_max_rate[0x20];
1345
1346         u8         rpg_ai_rate[0x20];
1347
1348         u8         rpg_hai_rate[0x20];
1349
1350         u8         rpg_gd[0x20];
1351
1352         u8         rpg_min_dec_fac[0x20];
1353
1354         u8         rpg_min_rate[0x20];
1355
1356         u8         reserved_at_1c0[0xe0];
1357
1358         u8         rate_to_set_on_first_cnp[0x20];
1359
1360         u8         dce_tcp_g[0x20];
1361
1362         u8         dce_tcp_rtt[0x20];
1363
1364         u8         rate_reduce_monitor_period[0x20];
1365
1366         u8         reserved_at_320[0x20];
1367
1368         u8         initial_alpha_value[0x20];
1369
1370         u8         reserved_at_360[0x4a0];
1371 };
1372
1373 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1374         u8         reserved_at_0[0x80];
1375
1376         u8         rppp_max_rps[0x20];
1377
1378         u8         rpg_time_reset[0x20];
1379
1380         u8         rpg_byte_reset[0x20];
1381
1382         u8         rpg_threshold[0x20];
1383
1384         u8         rpg_max_rate[0x20];
1385
1386         u8         rpg_ai_rate[0x20];
1387
1388         u8         rpg_hai_rate[0x20];
1389
1390         u8         rpg_gd[0x20];
1391
1392         u8         rpg_min_dec_fac[0x20];
1393
1394         u8         rpg_min_rate[0x20];
1395
1396         u8         reserved_at_1c0[0x640];
1397 };
1398
1399 enum {
1400         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1401         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1402         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1403 };
1404
1405 struct mlx5_ifc_resize_field_select_bits {
1406         u8         resize_field_select[0x20];
1407 };
1408
1409 enum {
1410         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1411         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1412         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1413         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1414 };
1415
1416 struct mlx5_ifc_modify_field_select_bits {
1417         u8         modify_field_select[0x20];
1418 };
1419
1420 struct mlx5_ifc_field_select_r_roce_np_bits {
1421         u8         field_select_r_roce_np[0x20];
1422 };
1423
1424 struct mlx5_ifc_field_select_r_roce_rp_bits {
1425         u8         field_select_r_roce_rp[0x20];
1426 };
1427
1428 enum {
1429         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1430         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1431         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1432         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1433         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1434         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1435         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1436         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1437         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1438         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1439 };
1440
1441 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1442         u8         field_select_8021qaurp[0x20];
1443 };
1444
1445 struct mlx5_ifc_phys_layer_cntrs_bits {
1446         u8         time_since_last_clear_high[0x20];
1447
1448         u8         time_since_last_clear_low[0x20];
1449
1450         u8         symbol_errors_high[0x20];
1451
1452         u8         symbol_errors_low[0x20];
1453
1454         u8         sync_headers_errors_high[0x20];
1455
1456         u8         sync_headers_errors_low[0x20];
1457
1458         u8         edpl_bip_errors_lane0_high[0x20];
1459
1460         u8         edpl_bip_errors_lane0_low[0x20];
1461
1462         u8         edpl_bip_errors_lane1_high[0x20];
1463
1464         u8         edpl_bip_errors_lane1_low[0x20];
1465
1466         u8         edpl_bip_errors_lane2_high[0x20];
1467
1468         u8         edpl_bip_errors_lane2_low[0x20];
1469
1470         u8         edpl_bip_errors_lane3_high[0x20];
1471
1472         u8         edpl_bip_errors_lane3_low[0x20];
1473
1474         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1475
1476         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1477
1478         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1479
1480         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1481
1482         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1483
1484         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1485
1486         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1487
1488         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1489
1490         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1491
1492         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1493
1494         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1495
1496         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1497
1498         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1499
1500         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1501
1502         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1503
1504         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1505
1506         u8         rs_fec_corrected_blocks_high[0x20];
1507
1508         u8         rs_fec_corrected_blocks_low[0x20];
1509
1510         u8         rs_fec_uncorrectable_blocks_high[0x20];
1511
1512         u8         rs_fec_uncorrectable_blocks_low[0x20];
1513
1514         u8         rs_fec_no_errors_blocks_high[0x20];
1515
1516         u8         rs_fec_no_errors_blocks_low[0x20];
1517
1518         u8         rs_fec_single_error_blocks_high[0x20];
1519
1520         u8         rs_fec_single_error_blocks_low[0x20];
1521
1522         u8         rs_fec_corrected_symbols_total_high[0x20];
1523
1524         u8         rs_fec_corrected_symbols_total_low[0x20];
1525
1526         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1527
1528         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1529
1530         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1531
1532         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1533
1534         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1535
1536         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1537
1538         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1539
1540         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1541
1542         u8         link_down_events[0x20];
1543
1544         u8         successful_recovery_events[0x20];
1545
1546         u8         reserved_at_640[0x180];
1547 };
1548
1549 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1550         u8         time_since_last_clear_high[0x20];
1551
1552         u8         time_since_last_clear_low[0x20];
1553
1554         u8         phy_received_bits_high[0x20];
1555
1556         u8         phy_received_bits_low[0x20];
1557
1558         u8         phy_symbol_errors_high[0x20];
1559
1560         u8         phy_symbol_errors_low[0x20];
1561
1562         u8         phy_corrected_bits_high[0x20];
1563
1564         u8         phy_corrected_bits_low[0x20];
1565
1566         u8         phy_corrected_bits_lane0_high[0x20];
1567
1568         u8         phy_corrected_bits_lane0_low[0x20];
1569
1570         u8         phy_corrected_bits_lane1_high[0x20];
1571
1572         u8         phy_corrected_bits_lane1_low[0x20];
1573
1574         u8         phy_corrected_bits_lane2_high[0x20];
1575
1576         u8         phy_corrected_bits_lane2_low[0x20];
1577
1578         u8         phy_corrected_bits_lane3_high[0x20];
1579
1580         u8         phy_corrected_bits_lane3_low[0x20];
1581
1582         u8         reserved_at_200[0x5c0];
1583 };
1584
1585 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1586         u8         symbol_error_counter[0x10];
1587
1588         u8         link_error_recovery_counter[0x8];
1589
1590         u8         link_downed_counter[0x8];
1591
1592         u8         port_rcv_errors[0x10];
1593
1594         u8         port_rcv_remote_physical_errors[0x10];
1595
1596         u8         port_rcv_switch_relay_errors[0x10];
1597
1598         u8         port_xmit_discards[0x10];
1599
1600         u8         port_xmit_constraint_errors[0x8];
1601
1602         u8         port_rcv_constraint_errors[0x8];
1603
1604         u8         reserved_at_70[0x8];
1605
1606         u8         link_overrun_errors[0x8];
1607
1608         u8         reserved_at_80[0x10];
1609
1610         u8         vl_15_dropped[0x10];
1611
1612         u8         reserved_at_a0[0x80];
1613
1614         u8         port_xmit_wait[0x20];
1615 };
1616
1617 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1618         u8         transmit_queue_high[0x20];
1619
1620         u8         transmit_queue_low[0x20];
1621
1622         u8         reserved_at_40[0x780];
1623 };
1624
1625 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1626         u8         rx_octets_high[0x20];
1627
1628         u8         rx_octets_low[0x20];
1629
1630         u8         reserved_at_40[0xc0];
1631
1632         u8         rx_frames_high[0x20];
1633
1634         u8         rx_frames_low[0x20];
1635
1636         u8         tx_octets_high[0x20];
1637
1638         u8         tx_octets_low[0x20];
1639
1640         u8         reserved_at_180[0xc0];
1641
1642         u8         tx_frames_high[0x20];
1643
1644         u8         tx_frames_low[0x20];
1645
1646         u8         rx_pause_high[0x20];
1647
1648         u8         rx_pause_low[0x20];
1649
1650         u8         rx_pause_duration_high[0x20];
1651
1652         u8         rx_pause_duration_low[0x20];
1653
1654         u8         tx_pause_high[0x20];
1655
1656         u8         tx_pause_low[0x20];
1657
1658         u8         tx_pause_duration_high[0x20];
1659
1660         u8         tx_pause_duration_low[0x20];
1661
1662         u8         rx_pause_transition_high[0x20];
1663
1664         u8         rx_pause_transition_low[0x20];
1665
1666         u8         reserved_at_3c0[0x40];
1667
1668         u8         device_stall_minor_watermark_cnt_high[0x20];
1669
1670         u8         device_stall_minor_watermark_cnt_low[0x20];
1671
1672         u8         device_stall_critical_watermark_cnt_high[0x20];
1673
1674         u8         device_stall_critical_watermark_cnt_low[0x20];
1675
1676         u8         reserved_at_480[0x340];
1677 };
1678
1679 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1680         u8         port_transmit_wait_high[0x20];
1681
1682         u8         port_transmit_wait_low[0x20];
1683
1684         u8         reserved_at_40[0x100];
1685
1686         u8         rx_buffer_almost_full_high[0x20];
1687
1688         u8         rx_buffer_almost_full_low[0x20];
1689
1690         u8         rx_buffer_full_high[0x20];
1691
1692         u8         rx_buffer_full_low[0x20];
1693
1694         u8         rx_icrc_encapsulated_high[0x20];
1695
1696         u8         rx_icrc_encapsulated_low[0x20];
1697
1698         u8         reserved_at_200[0x5c0];
1699 };
1700
1701 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1702         u8         dot3stats_alignment_errors_high[0x20];
1703
1704         u8         dot3stats_alignment_errors_low[0x20];
1705
1706         u8         dot3stats_fcs_errors_high[0x20];
1707
1708         u8         dot3stats_fcs_errors_low[0x20];
1709
1710         u8         dot3stats_single_collision_frames_high[0x20];
1711
1712         u8         dot3stats_single_collision_frames_low[0x20];
1713
1714         u8         dot3stats_multiple_collision_frames_high[0x20];
1715
1716         u8         dot3stats_multiple_collision_frames_low[0x20];
1717
1718         u8         dot3stats_sqe_test_errors_high[0x20];
1719
1720         u8         dot3stats_sqe_test_errors_low[0x20];
1721
1722         u8         dot3stats_deferred_transmissions_high[0x20];
1723
1724         u8         dot3stats_deferred_transmissions_low[0x20];
1725
1726         u8         dot3stats_late_collisions_high[0x20];
1727
1728         u8         dot3stats_late_collisions_low[0x20];
1729
1730         u8         dot3stats_excessive_collisions_high[0x20];
1731
1732         u8         dot3stats_excessive_collisions_low[0x20];
1733
1734         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1735
1736         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1737
1738         u8         dot3stats_carrier_sense_errors_high[0x20];
1739
1740         u8         dot3stats_carrier_sense_errors_low[0x20];
1741
1742         u8         dot3stats_frame_too_longs_high[0x20];
1743
1744         u8         dot3stats_frame_too_longs_low[0x20];
1745
1746         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1747
1748         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1749
1750         u8         dot3stats_symbol_errors_high[0x20];
1751
1752         u8         dot3stats_symbol_errors_low[0x20];
1753
1754         u8         dot3control_in_unknown_opcodes_high[0x20];
1755
1756         u8         dot3control_in_unknown_opcodes_low[0x20];
1757
1758         u8         dot3in_pause_frames_high[0x20];
1759
1760         u8         dot3in_pause_frames_low[0x20];
1761
1762         u8         dot3out_pause_frames_high[0x20];
1763
1764         u8         dot3out_pause_frames_low[0x20];
1765
1766         u8         reserved_at_400[0x3c0];
1767 };
1768
1769 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1770         u8         ether_stats_drop_events_high[0x20];
1771
1772         u8         ether_stats_drop_events_low[0x20];
1773
1774         u8         ether_stats_octets_high[0x20];
1775
1776         u8         ether_stats_octets_low[0x20];
1777
1778         u8         ether_stats_pkts_high[0x20];
1779
1780         u8         ether_stats_pkts_low[0x20];
1781
1782         u8         ether_stats_broadcast_pkts_high[0x20];
1783
1784         u8         ether_stats_broadcast_pkts_low[0x20];
1785
1786         u8         ether_stats_multicast_pkts_high[0x20];
1787
1788         u8         ether_stats_multicast_pkts_low[0x20];
1789
1790         u8         ether_stats_crc_align_errors_high[0x20];
1791
1792         u8         ether_stats_crc_align_errors_low[0x20];
1793
1794         u8         ether_stats_undersize_pkts_high[0x20];
1795
1796         u8         ether_stats_undersize_pkts_low[0x20];
1797
1798         u8         ether_stats_oversize_pkts_high[0x20];
1799
1800         u8         ether_stats_oversize_pkts_low[0x20];
1801
1802         u8         ether_stats_fragments_high[0x20];
1803
1804         u8         ether_stats_fragments_low[0x20];
1805
1806         u8         ether_stats_jabbers_high[0x20];
1807
1808         u8         ether_stats_jabbers_low[0x20];
1809
1810         u8         ether_stats_collisions_high[0x20];
1811
1812         u8         ether_stats_collisions_low[0x20];
1813
1814         u8         ether_stats_pkts64octets_high[0x20];
1815
1816         u8         ether_stats_pkts64octets_low[0x20];
1817
1818         u8         ether_stats_pkts65to127octets_high[0x20];
1819
1820         u8         ether_stats_pkts65to127octets_low[0x20];
1821
1822         u8         ether_stats_pkts128to255octets_high[0x20];
1823
1824         u8         ether_stats_pkts128to255octets_low[0x20];
1825
1826         u8         ether_stats_pkts256to511octets_high[0x20];
1827
1828         u8         ether_stats_pkts256to511octets_low[0x20];
1829
1830         u8         ether_stats_pkts512to1023octets_high[0x20];
1831
1832         u8         ether_stats_pkts512to1023octets_low[0x20];
1833
1834         u8         ether_stats_pkts1024to1518octets_high[0x20];
1835
1836         u8         ether_stats_pkts1024to1518octets_low[0x20];
1837
1838         u8         ether_stats_pkts1519to2047octets_high[0x20];
1839
1840         u8         ether_stats_pkts1519to2047octets_low[0x20];
1841
1842         u8         ether_stats_pkts2048to4095octets_high[0x20];
1843
1844         u8         ether_stats_pkts2048to4095octets_low[0x20];
1845
1846         u8         ether_stats_pkts4096to8191octets_high[0x20];
1847
1848         u8         ether_stats_pkts4096to8191octets_low[0x20];
1849
1850         u8         ether_stats_pkts8192to10239octets_high[0x20];
1851
1852         u8         ether_stats_pkts8192to10239octets_low[0x20];
1853
1854         u8         reserved_at_540[0x280];
1855 };
1856
1857 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1858         u8         if_in_octets_high[0x20];
1859
1860         u8         if_in_octets_low[0x20];
1861
1862         u8         if_in_ucast_pkts_high[0x20];
1863
1864         u8         if_in_ucast_pkts_low[0x20];
1865
1866         u8         if_in_discards_high[0x20];
1867
1868         u8         if_in_discards_low[0x20];
1869
1870         u8         if_in_errors_high[0x20];
1871
1872         u8         if_in_errors_low[0x20];
1873
1874         u8         if_in_unknown_protos_high[0x20];
1875
1876         u8         if_in_unknown_protos_low[0x20];
1877
1878         u8         if_out_octets_high[0x20];
1879
1880         u8         if_out_octets_low[0x20];
1881
1882         u8         if_out_ucast_pkts_high[0x20];
1883
1884         u8         if_out_ucast_pkts_low[0x20];
1885
1886         u8         if_out_discards_high[0x20];
1887
1888         u8         if_out_discards_low[0x20];
1889
1890         u8         if_out_errors_high[0x20];
1891
1892         u8         if_out_errors_low[0x20];
1893
1894         u8         if_in_multicast_pkts_high[0x20];
1895
1896         u8         if_in_multicast_pkts_low[0x20];
1897
1898         u8         if_in_broadcast_pkts_high[0x20];
1899
1900         u8         if_in_broadcast_pkts_low[0x20];
1901
1902         u8         if_out_multicast_pkts_high[0x20];
1903
1904         u8         if_out_multicast_pkts_low[0x20];
1905
1906         u8         if_out_broadcast_pkts_high[0x20];
1907
1908         u8         if_out_broadcast_pkts_low[0x20];
1909
1910         u8         reserved_at_340[0x480];
1911 };
1912
1913 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1914         u8         a_frames_transmitted_ok_high[0x20];
1915
1916         u8         a_frames_transmitted_ok_low[0x20];
1917
1918         u8         a_frames_received_ok_high[0x20];
1919
1920         u8         a_frames_received_ok_low[0x20];
1921
1922         u8         a_frame_check_sequence_errors_high[0x20];
1923
1924         u8         a_frame_check_sequence_errors_low[0x20];
1925
1926         u8         a_alignment_errors_high[0x20];
1927
1928         u8         a_alignment_errors_low[0x20];
1929
1930         u8         a_octets_transmitted_ok_high[0x20];
1931
1932         u8         a_octets_transmitted_ok_low[0x20];
1933
1934         u8         a_octets_received_ok_high[0x20];
1935
1936         u8         a_octets_received_ok_low[0x20];
1937
1938         u8         a_multicast_frames_xmitted_ok_high[0x20];
1939
1940         u8         a_multicast_frames_xmitted_ok_low[0x20];
1941
1942         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1943
1944         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1945
1946         u8         a_multicast_frames_received_ok_high[0x20];
1947
1948         u8         a_multicast_frames_received_ok_low[0x20];
1949
1950         u8         a_broadcast_frames_received_ok_high[0x20];
1951
1952         u8         a_broadcast_frames_received_ok_low[0x20];
1953
1954         u8         a_in_range_length_errors_high[0x20];
1955
1956         u8         a_in_range_length_errors_low[0x20];
1957
1958         u8         a_out_of_range_length_field_high[0x20];
1959
1960         u8         a_out_of_range_length_field_low[0x20];
1961
1962         u8         a_frame_too_long_errors_high[0x20];
1963
1964         u8         a_frame_too_long_errors_low[0x20];
1965
1966         u8         a_symbol_error_during_carrier_high[0x20];
1967
1968         u8         a_symbol_error_during_carrier_low[0x20];
1969
1970         u8         a_mac_control_frames_transmitted_high[0x20];
1971
1972         u8         a_mac_control_frames_transmitted_low[0x20];
1973
1974         u8         a_mac_control_frames_received_high[0x20];
1975
1976         u8         a_mac_control_frames_received_low[0x20];
1977
1978         u8         a_unsupported_opcodes_received_high[0x20];
1979
1980         u8         a_unsupported_opcodes_received_low[0x20];
1981
1982         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1983
1984         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1985
1986         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1987
1988         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1989
1990         u8         reserved_at_4c0[0x300];
1991 };
1992
1993 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1994         u8         life_time_counter_high[0x20];
1995
1996         u8         life_time_counter_low[0x20];
1997
1998         u8         rx_errors[0x20];
1999
2000         u8         tx_errors[0x20];
2001
2002         u8         l0_to_recovery_eieos[0x20];
2003
2004         u8         l0_to_recovery_ts[0x20];
2005
2006         u8         l0_to_recovery_framing[0x20];
2007
2008         u8         l0_to_recovery_retrain[0x20];
2009
2010         u8         crc_error_dllp[0x20];
2011
2012         u8         crc_error_tlp[0x20];
2013
2014         u8         tx_overflow_buffer_pkt_high[0x20];
2015
2016         u8         tx_overflow_buffer_pkt_low[0x20];
2017
2018         u8         outbound_stalled_reads[0x20];
2019
2020         u8         outbound_stalled_writes[0x20];
2021
2022         u8         outbound_stalled_reads_events[0x20];
2023
2024         u8         outbound_stalled_writes_events[0x20];
2025
2026         u8         reserved_at_200[0x5c0];
2027 };
2028
2029 struct mlx5_ifc_cmd_inter_comp_event_bits {
2030         u8         command_completion_vector[0x20];
2031
2032         u8         reserved_at_20[0xc0];
2033 };
2034
2035 struct mlx5_ifc_stall_vl_event_bits {
2036         u8         reserved_at_0[0x18];
2037         u8         port_num[0x1];
2038         u8         reserved_at_19[0x3];
2039         u8         vl[0x4];
2040
2041         u8         reserved_at_20[0xa0];
2042 };
2043
2044 struct mlx5_ifc_db_bf_congestion_event_bits {
2045         u8         event_subtype[0x8];
2046         u8         reserved_at_8[0x8];
2047         u8         congestion_level[0x8];
2048         u8         reserved_at_18[0x8];
2049
2050         u8         reserved_at_20[0xa0];
2051 };
2052
2053 struct mlx5_ifc_gpio_event_bits {
2054         u8         reserved_at_0[0x60];
2055
2056         u8         gpio_event_hi[0x20];
2057
2058         u8         gpio_event_lo[0x20];
2059
2060         u8         reserved_at_a0[0x40];
2061 };
2062
2063 struct mlx5_ifc_port_state_change_event_bits {
2064         u8         reserved_at_0[0x40];
2065
2066         u8         port_num[0x4];
2067         u8         reserved_at_44[0x1c];
2068
2069         u8         reserved_at_60[0x80];
2070 };
2071
2072 struct mlx5_ifc_dropped_packet_logged_bits {
2073         u8         reserved_at_0[0xe0];
2074 };
2075
2076 enum {
2077         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2078         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2079 };
2080
2081 struct mlx5_ifc_cq_error_bits {
2082         u8         reserved_at_0[0x8];
2083         u8         cqn[0x18];
2084
2085         u8         reserved_at_20[0x20];
2086
2087         u8         reserved_at_40[0x18];
2088         u8         syndrome[0x8];
2089
2090         u8         reserved_at_60[0x80];
2091 };
2092
2093 struct mlx5_ifc_rdma_page_fault_event_bits {
2094         u8         bytes_committed[0x20];
2095
2096         u8         r_key[0x20];
2097
2098         u8         reserved_at_40[0x10];
2099         u8         packet_len[0x10];
2100
2101         u8         rdma_op_len[0x20];
2102
2103         u8         rdma_va[0x40];
2104
2105         u8         reserved_at_c0[0x5];
2106         u8         rdma[0x1];
2107         u8         write[0x1];
2108         u8         requestor[0x1];
2109         u8         qp_number[0x18];
2110 };
2111
2112 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2113         u8         bytes_committed[0x20];
2114
2115         u8         reserved_at_20[0x10];
2116         u8         wqe_index[0x10];
2117
2118         u8         reserved_at_40[0x10];
2119         u8         len[0x10];
2120
2121         u8         reserved_at_60[0x60];
2122
2123         u8         reserved_at_c0[0x5];
2124         u8         rdma[0x1];
2125         u8         write_read[0x1];
2126         u8         requestor[0x1];
2127         u8         qpn[0x18];
2128 };
2129
2130 struct mlx5_ifc_qp_events_bits {
2131         u8         reserved_at_0[0xa0];
2132
2133         u8         type[0x8];
2134         u8         reserved_at_a8[0x18];
2135
2136         u8         reserved_at_c0[0x8];
2137         u8         qpn_rqn_sqn[0x18];
2138 };
2139
2140 struct mlx5_ifc_dct_events_bits {
2141         u8         reserved_at_0[0xc0];
2142
2143         u8         reserved_at_c0[0x8];
2144         u8         dct_number[0x18];
2145 };
2146
2147 struct mlx5_ifc_comp_event_bits {
2148         u8         reserved_at_0[0xc0];
2149
2150         u8         reserved_at_c0[0x8];
2151         u8         cq_number[0x18];
2152 };
2153
2154 enum {
2155         MLX5_QPC_STATE_RST        = 0x0,
2156         MLX5_QPC_STATE_INIT       = 0x1,
2157         MLX5_QPC_STATE_RTR        = 0x2,
2158         MLX5_QPC_STATE_RTS        = 0x3,
2159         MLX5_QPC_STATE_SQER       = 0x4,
2160         MLX5_QPC_STATE_ERR        = 0x6,
2161         MLX5_QPC_STATE_SQD        = 0x7,
2162         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2163 };
2164
2165 enum {
2166         MLX5_QPC_ST_RC            = 0x0,
2167         MLX5_QPC_ST_UC            = 0x1,
2168         MLX5_QPC_ST_UD            = 0x2,
2169         MLX5_QPC_ST_XRC           = 0x3,
2170         MLX5_QPC_ST_DCI           = 0x5,
2171         MLX5_QPC_ST_QP0           = 0x7,
2172         MLX5_QPC_ST_QP1           = 0x8,
2173         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2174         MLX5_QPC_ST_REG_UMR       = 0xc,
2175 };
2176
2177 enum {
2178         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2179         MLX5_QPC_PM_STATE_REARM     = 0x1,
2180         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2181         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2182 };
2183
2184 enum {
2185         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2186 };
2187
2188 enum {
2189         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2190         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2191 };
2192
2193 enum {
2194         MLX5_QPC_MTU_256_BYTES        = 0x1,
2195         MLX5_QPC_MTU_512_BYTES        = 0x2,
2196         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2197         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2198         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2199         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2200 };
2201
2202 enum {
2203         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2204         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2205         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2206         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2207         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2208         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2209         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2210         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2211 };
2212
2213 enum {
2214         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2215         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2216         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2217 };
2218
2219 enum {
2220         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2221         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2222         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2223 };
2224
2225 struct mlx5_ifc_qpc_bits {
2226         u8         state[0x4];
2227         u8         lag_tx_port_affinity[0x4];
2228         u8         st[0x8];
2229         u8         reserved_at_10[0x3];
2230         u8         pm_state[0x2];
2231         u8         reserved_at_15[0x3];
2232         u8         offload_type[0x4];
2233         u8         end_padding_mode[0x2];
2234         u8         reserved_at_1e[0x2];
2235
2236         u8         wq_signature[0x1];
2237         u8         block_lb_mc[0x1];
2238         u8         atomic_like_write_en[0x1];
2239         u8         latency_sensitive[0x1];
2240         u8         reserved_at_24[0x1];
2241         u8         drain_sigerr[0x1];
2242         u8         reserved_at_26[0x2];
2243         u8         pd[0x18];
2244
2245         u8         mtu[0x3];
2246         u8         log_msg_max[0x5];
2247         u8         reserved_at_48[0x1];
2248         u8         log_rq_size[0x4];
2249         u8         log_rq_stride[0x3];
2250         u8         no_sq[0x1];
2251         u8         log_sq_size[0x4];
2252         u8         reserved_at_55[0x6];
2253         u8         rlky[0x1];
2254         u8         ulp_stateless_offload_mode[0x4];
2255
2256         u8         counter_set_id[0x8];
2257         u8         uar_page[0x18];
2258
2259         u8         reserved_at_80[0x8];
2260         u8         user_index[0x18];
2261
2262         u8         reserved_at_a0[0x3];
2263         u8         log_page_size[0x5];
2264         u8         remote_qpn[0x18];
2265
2266         struct mlx5_ifc_ads_bits primary_address_path;
2267
2268         struct mlx5_ifc_ads_bits secondary_address_path;
2269
2270         u8         log_ack_req_freq[0x4];
2271         u8         reserved_at_384[0x4];
2272         u8         log_sra_max[0x3];
2273         u8         reserved_at_38b[0x2];
2274         u8         retry_count[0x3];
2275         u8         rnr_retry[0x3];
2276         u8         reserved_at_393[0x1];
2277         u8         fre[0x1];
2278         u8         cur_rnr_retry[0x3];
2279         u8         cur_retry_count[0x3];
2280         u8         reserved_at_39b[0x5];
2281
2282         u8         reserved_at_3a0[0x20];
2283
2284         u8         reserved_at_3c0[0x8];
2285         u8         next_send_psn[0x18];
2286
2287         u8         reserved_at_3e0[0x8];
2288         u8         cqn_snd[0x18];
2289
2290         u8         reserved_at_400[0x8];
2291         u8         deth_sqpn[0x18];
2292
2293         u8         reserved_at_420[0x20];
2294
2295         u8         reserved_at_440[0x8];
2296         u8         last_acked_psn[0x18];
2297
2298         u8         reserved_at_460[0x8];
2299         u8         ssn[0x18];
2300
2301         u8         reserved_at_480[0x8];
2302         u8         log_rra_max[0x3];
2303         u8         reserved_at_48b[0x1];
2304         u8         atomic_mode[0x4];
2305         u8         rre[0x1];
2306         u8         rwe[0x1];
2307         u8         rae[0x1];
2308         u8         reserved_at_493[0x1];
2309         u8         page_offset[0x6];
2310         u8         reserved_at_49a[0x3];
2311         u8         cd_slave_receive[0x1];
2312         u8         cd_slave_send[0x1];
2313         u8         cd_master[0x1];
2314
2315         u8         reserved_at_4a0[0x3];
2316         u8         min_rnr_nak[0x5];
2317         u8         next_rcv_psn[0x18];
2318
2319         u8         reserved_at_4c0[0x8];
2320         u8         xrcd[0x18];
2321
2322         u8         reserved_at_4e0[0x8];
2323         u8         cqn_rcv[0x18];
2324
2325         u8         dbr_addr[0x40];
2326
2327         u8         q_key[0x20];
2328
2329         u8         reserved_at_560[0x5];
2330         u8         rq_type[0x3];
2331         u8         srqn_rmpn_xrqn[0x18];
2332
2333         u8         reserved_at_580[0x8];
2334         u8         rmsn[0x18];
2335
2336         u8         hw_sq_wqebb_counter[0x10];
2337         u8         sw_sq_wqebb_counter[0x10];
2338
2339         u8         hw_rq_counter[0x20];
2340
2341         u8         sw_rq_counter[0x20];
2342
2343         u8         reserved_at_600[0x20];
2344
2345         u8         reserved_at_620[0xf];
2346         u8         cgs[0x1];
2347         u8         cs_req[0x8];
2348         u8         cs_res[0x8];
2349
2350         u8         dc_access_key[0x40];
2351
2352         u8         reserved_at_680[0xc0];
2353 };
2354
2355 struct mlx5_ifc_roce_addr_layout_bits {
2356         u8         source_l3_address[16][0x8];
2357
2358         u8         reserved_at_80[0x3];
2359         u8         vlan_valid[0x1];
2360         u8         vlan_id[0xc];
2361         u8         source_mac_47_32[0x10];
2362
2363         u8         source_mac_31_0[0x20];
2364
2365         u8         reserved_at_c0[0x14];
2366         u8         roce_l3_type[0x4];
2367         u8         roce_version[0x8];
2368
2369         u8         reserved_at_e0[0x20];
2370 };
2371
2372 union mlx5_ifc_hca_cap_union_bits {
2373         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2374         struct mlx5_ifc_odp_cap_bits odp_cap;
2375         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2376         struct mlx5_ifc_roce_cap_bits roce_cap;
2377         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2378         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2379         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2380         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2381         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2382         struct mlx5_ifc_qos_cap_bits qos_cap;
2383         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2384         u8         reserved_at_0[0x8000];
2385 };
2386
2387 enum {
2388         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2389         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2390         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2391         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2392         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2393         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2394         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2395         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2396         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2397         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2398         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2399 };
2400
2401 struct mlx5_ifc_vlan_bits {
2402         u8         ethtype[0x10];
2403         u8         prio[0x3];
2404         u8         cfi[0x1];
2405         u8         vid[0xc];
2406 };
2407
2408 struct mlx5_ifc_flow_context_bits {
2409         struct mlx5_ifc_vlan_bits push_vlan;
2410
2411         u8         group_id[0x20];
2412
2413         u8         reserved_at_40[0x8];
2414         u8         flow_tag[0x18];
2415
2416         u8         reserved_at_60[0x10];
2417         u8         action[0x10];
2418
2419         u8         reserved_at_80[0x8];
2420         u8         destination_list_size[0x18];
2421
2422         u8         reserved_at_a0[0x8];
2423         u8         flow_counter_list_size[0x18];
2424
2425         u8         encap_id[0x20];
2426
2427         u8         modify_header_id[0x20];
2428
2429         struct mlx5_ifc_vlan_bits push_vlan_2;
2430
2431         u8         reserved_at_120[0xe0];
2432
2433         struct mlx5_ifc_fte_match_param_bits match_value;
2434
2435         u8         reserved_at_1200[0x600];
2436
2437         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2438 };
2439
2440 enum {
2441         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2442         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2443 };
2444
2445 struct mlx5_ifc_xrc_srqc_bits {
2446         u8         state[0x4];
2447         u8         log_xrc_srq_size[0x4];
2448         u8         reserved_at_8[0x18];
2449
2450         u8         wq_signature[0x1];
2451         u8         cont_srq[0x1];
2452         u8         reserved_at_22[0x1];
2453         u8         rlky[0x1];
2454         u8         basic_cyclic_rcv_wqe[0x1];
2455         u8         log_rq_stride[0x3];
2456         u8         xrcd[0x18];
2457
2458         u8         page_offset[0x6];
2459         u8         reserved_at_46[0x2];
2460         u8         cqn[0x18];
2461
2462         u8         reserved_at_60[0x20];
2463
2464         u8         user_index_equal_xrc_srqn[0x1];
2465         u8         reserved_at_81[0x1];
2466         u8         log_page_size[0x6];
2467         u8         user_index[0x18];
2468
2469         u8         reserved_at_a0[0x20];
2470
2471         u8         reserved_at_c0[0x8];
2472         u8         pd[0x18];
2473
2474         u8         lwm[0x10];
2475         u8         wqe_cnt[0x10];
2476
2477         u8         reserved_at_100[0x40];
2478
2479         u8         db_record_addr_h[0x20];
2480
2481         u8         db_record_addr_l[0x1e];
2482         u8         reserved_at_17e[0x2];
2483
2484         u8         reserved_at_180[0x80];
2485 };
2486
2487 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2488         u8         counter_error_queues[0x20];
2489
2490         u8         total_error_queues[0x20];
2491
2492         u8         send_queue_priority_update_flow[0x20];
2493
2494         u8         reserved_at_60[0x20];
2495
2496         u8         nic_receive_steering_discard[0x40];
2497
2498         u8         receive_discard_vport_down[0x40];
2499
2500         u8         transmit_discard_vport_down[0x40];
2501
2502         u8         reserved_at_140[0xec0];
2503 };
2504
2505 struct mlx5_ifc_traffic_counter_bits {
2506         u8         packets[0x40];
2507
2508         u8         octets[0x40];
2509 };
2510
2511 struct mlx5_ifc_tisc_bits {
2512         u8         strict_lag_tx_port_affinity[0x1];
2513         u8         reserved_at_1[0x3];
2514         u8         lag_tx_port_affinity[0x04];
2515
2516         u8         reserved_at_8[0x4];
2517         u8         prio[0x4];
2518         u8         reserved_at_10[0x10];
2519
2520         u8         reserved_at_20[0x100];
2521
2522         u8         reserved_at_120[0x8];
2523         u8         transport_domain[0x18];
2524
2525         u8         reserved_at_140[0x8];
2526         u8         underlay_qpn[0x18];
2527         u8         reserved_at_160[0x3a0];
2528 };
2529
2530 enum {
2531         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2532         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2533 };
2534
2535 enum {
2536         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2537         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2538 };
2539
2540 enum {
2541         MLX5_RX_HASH_FN_NONE           = 0x0,
2542         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2543         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2544 };
2545
2546 enum {
2547         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2548         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2549 };
2550
2551 struct mlx5_ifc_tirc_bits {
2552         u8         reserved_at_0[0x20];
2553
2554         u8         disp_type[0x4];
2555         u8         reserved_at_24[0x1c];
2556
2557         u8         reserved_at_40[0x40];
2558
2559         u8         reserved_at_80[0x4];
2560         u8         lro_timeout_period_usecs[0x10];
2561         u8         lro_enable_mask[0x4];
2562         u8         lro_max_ip_payload_size[0x8];
2563
2564         u8         reserved_at_a0[0x40];
2565
2566         u8         reserved_at_e0[0x8];
2567         u8         inline_rqn[0x18];
2568
2569         u8         rx_hash_symmetric[0x1];
2570         u8         reserved_at_101[0x1];
2571         u8         tunneled_offload_en[0x1];
2572         u8         reserved_at_103[0x5];
2573         u8         indirect_table[0x18];
2574
2575         u8         rx_hash_fn[0x4];
2576         u8         reserved_at_124[0x2];
2577         u8         self_lb_block[0x2];
2578         u8         transport_domain[0x18];
2579
2580         u8         rx_hash_toeplitz_key[10][0x20];
2581
2582         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2583
2584         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2585
2586         u8         reserved_at_2c0[0x4c0];
2587 };
2588
2589 enum {
2590         MLX5_SRQC_STATE_GOOD   = 0x0,
2591         MLX5_SRQC_STATE_ERROR  = 0x1,
2592 };
2593
2594 struct mlx5_ifc_srqc_bits {
2595         u8         state[0x4];
2596         u8         log_srq_size[0x4];
2597         u8         reserved_at_8[0x18];
2598
2599         u8         wq_signature[0x1];
2600         u8         cont_srq[0x1];
2601         u8         reserved_at_22[0x1];
2602         u8         rlky[0x1];
2603         u8         reserved_at_24[0x1];
2604         u8         log_rq_stride[0x3];
2605         u8         xrcd[0x18];
2606
2607         u8         page_offset[0x6];
2608         u8         reserved_at_46[0x2];
2609         u8         cqn[0x18];
2610
2611         u8         reserved_at_60[0x20];
2612
2613         u8         reserved_at_80[0x2];
2614         u8         log_page_size[0x6];
2615         u8         reserved_at_88[0x18];
2616
2617         u8         reserved_at_a0[0x20];
2618
2619         u8         reserved_at_c0[0x8];
2620         u8         pd[0x18];
2621
2622         u8         lwm[0x10];
2623         u8         wqe_cnt[0x10];
2624
2625         u8         reserved_at_100[0x40];
2626
2627         u8         dbr_addr[0x40];
2628
2629         u8         reserved_at_180[0x80];
2630 };
2631
2632 enum {
2633         MLX5_SQC_STATE_RST  = 0x0,
2634         MLX5_SQC_STATE_RDY  = 0x1,
2635         MLX5_SQC_STATE_ERR  = 0x3,
2636 };
2637
2638 struct mlx5_ifc_sqc_bits {
2639         u8         rlky[0x1];
2640         u8         cd_master[0x1];
2641         u8         fre[0x1];
2642         u8         flush_in_error_en[0x1];
2643         u8         allow_multi_pkt_send_wqe[0x1];
2644         u8         min_wqe_inline_mode[0x3];
2645         u8         state[0x4];
2646         u8         reg_umr[0x1];
2647         u8         allow_swp[0x1];
2648         u8         hairpin[0x1];
2649         u8         reserved_at_f[0x11];
2650
2651         u8         reserved_at_20[0x8];
2652         u8         user_index[0x18];
2653
2654         u8         reserved_at_40[0x8];
2655         u8         cqn[0x18];
2656
2657         u8         reserved_at_60[0x8];
2658         u8         hairpin_peer_rq[0x18];
2659
2660         u8         reserved_at_80[0x10];
2661         u8         hairpin_peer_vhca[0x10];
2662
2663         u8         reserved_at_a0[0x50];
2664
2665         u8         packet_pacing_rate_limit_index[0x10];
2666         u8         tis_lst_sz[0x10];
2667         u8         reserved_at_110[0x10];
2668
2669         u8         reserved_at_120[0x40];
2670
2671         u8         reserved_at_160[0x8];
2672         u8         tis_num_0[0x18];
2673
2674         struct mlx5_ifc_wq_bits wq;
2675 };
2676
2677 enum {
2678         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2679         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2680         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2681         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2682 };
2683
2684 struct mlx5_ifc_scheduling_context_bits {
2685         u8         element_type[0x8];
2686         u8         reserved_at_8[0x18];
2687
2688         u8         element_attributes[0x20];
2689
2690         u8         parent_element_id[0x20];
2691
2692         u8         reserved_at_60[0x40];
2693
2694         u8         bw_share[0x20];
2695
2696         u8         max_average_bw[0x20];
2697
2698         u8         reserved_at_e0[0x120];
2699 };
2700
2701 struct mlx5_ifc_rqtc_bits {
2702         u8         reserved_at_0[0xa0];
2703
2704         u8         reserved_at_a0[0x10];
2705         u8         rqt_max_size[0x10];
2706
2707         u8         reserved_at_c0[0x10];
2708         u8         rqt_actual_size[0x10];
2709
2710         u8         reserved_at_e0[0x6a0];
2711
2712         struct mlx5_ifc_rq_num_bits rq_num[0];
2713 };
2714
2715 enum {
2716         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2717         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2718 };
2719
2720 enum {
2721         MLX5_RQC_STATE_RST  = 0x0,
2722         MLX5_RQC_STATE_RDY  = 0x1,
2723         MLX5_RQC_STATE_ERR  = 0x3,
2724 };
2725
2726 struct mlx5_ifc_rqc_bits {
2727         u8         rlky[0x1];
2728         u8         delay_drop_en[0x1];
2729         u8         scatter_fcs[0x1];
2730         u8         vsd[0x1];
2731         u8         mem_rq_type[0x4];
2732         u8         state[0x4];
2733         u8         reserved_at_c[0x1];
2734         u8         flush_in_error_en[0x1];
2735         u8         hairpin[0x1];
2736         u8         reserved_at_f[0x11];
2737
2738         u8         reserved_at_20[0x8];
2739         u8         user_index[0x18];
2740
2741         u8         reserved_at_40[0x8];
2742         u8         cqn[0x18];
2743
2744         u8         counter_set_id[0x8];
2745         u8         reserved_at_68[0x18];
2746
2747         u8         reserved_at_80[0x8];
2748         u8         rmpn[0x18];
2749
2750         u8         reserved_at_a0[0x8];
2751         u8         hairpin_peer_sq[0x18];
2752
2753         u8         reserved_at_c0[0x10];
2754         u8         hairpin_peer_vhca[0x10];
2755
2756         u8         reserved_at_e0[0xa0];
2757
2758         struct mlx5_ifc_wq_bits wq;
2759 };
2760
2761 enum {
2762         MLX5_RMPC_STATE_RDY  = 0x1,
2763         MLX5_RMPC_STATE_ERR  = 0x3,
2764 };
2765
2766 struct mlx5_ifc_rmpc_bits {
2767         u8         reserved_at_0[0x8];
2768         u8         state[0x4];
2769         u8         reserved_at_c[0x14];
2770
2771         u8         basic_cyclic_rcv_wqe[0x1];
2772         u8         reserved_at_21[0x1f];
2773
2774         u8         reserved_at_40[0x140];
2775
2776         struct mlx5_ifc_wq_bits wq;
2777 };
2778
2779 struct mlx5_ifc_nic_vport_context_bits {
2780         u8         reserved_at_0[0x5];
2781         u8         min_wqe_inline_mode[0x3];
2782         u8         reserved_at_8[0x15];
2783         u8         disable_mc_local_lb[0x1];
2784         u8         disable_uc_local_lb[0x1];
2785         u8         roce_en[0x1];
2786
2787         u8         arm_change_event[0x1];
2788         u8         reserved_at_21[0x1a];
2789         u8         event_on_mtu[0x1];
2790         u8         event_on_promisc_change[0x1];
2791         u8         event_on_vlan_change[0x1];
2792         u8         event_on_mc_address_change[0x1];
2793         u8         event_on_uc_address_change[0x1];
2794
2795         u8         reserved_at_40[0xc];
2796
2797         u8         affiliation_criteria[0x4];
2798         u8         affiliated_vhca_id[0x10];
2799
2800         u8         reserved_at_60[0xd0];
2801
2802         u8         mtu[0x10];
2803
2804         u8         system_image_guid[0x40];
2805         u8         port_guid[0x40];
2806         u8         node_guid[0x40];
2807
2808         u8         reserved_at_200[0x140];
2809         u8         qkey_violation_counter[0x10];
2810         u8         reserved_at_350[0x430];
2811
2812         u8         promisc_uc[0x1];
2813         u8         promisc_mc[0x1];
2814         u8         promisc_all[0x1];
2815         u8         reserved_at_783[0x2];
2816         u8         allowed_list_type[0x3];
2817         u8         reserved_at_788[0xc];
2818         u8         allowed_list_size[0xc];
2819
2820         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2821
2822         u8         reserved_at_7e0[0x20];
2823
2824         u8         current_uc_mac_address[0][0x40];
2825 };
2826
2827 enum {
2828         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2829         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2830         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2831         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2832         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2833 };
2834
2835 struct mlx5_ifc_mkc_bits {
2836         u8         reserved_at_0[0x1];
2837         u8         free[0x1];
2838         u8         reserved_at_2[0x1];
2839         u8         access_mode_4_2[0x3];
2840         u8         reserved_at_6[0x7];
2841         u8         relaxed_ordering_write[0x1];
2842         u8         reserved_at_e[0x1];
2843         u8         small_fence_on_rdma_read_response[0x1];
2844         u8         umr_en[0x1];
2845         u8         a[0x1];
2846         u8         rw[0x1];
2847         u8         rr[0x1];
2848         u8         lw[0x1];
2849         u8         lr[0x1];
2850         u8         access_mode_1_0[0x2];
2851         u8         reserved_at_18[0x8];
2852
2853         u8         qpn[0x18];
2854         u8         mkey_7_0[0x8];
2855
2856         u8         reserved_at_40[0x20];
2857
2858         u8         length64[0x1];
2859         u8         bsf_en[0x1];
2860         u8         sync_umr[0x1];
2861         u8         reserved_at_63[0x2];
2862         u8         expected_sigerr_count[0x1];
2863         u8         reserved_at_66[0x1];
2864         u8         en_rinval[0x1];
2865         u8         pd[0x18];
2866
2867         u8         start_addr[0x40];
2868
2869         u8         len[0x40];
2870
2871         u8         bsf_octword_size[0x20];
2872
2873         u8         reserved_at_120[0x80];
2874
2875         u8         translations_octword_size[0x20];
2876
2877         u8         reserved_at_1c0[0x1b];
2878         u8         log_page_size[0x5];
2879
2880         u8         reserved_at_1e0[0x20];
2881 };
2882
2883 struct mlx5_ifc_pkey_bits {
2884         u8         reserved_at_0[0x10];
2885         u8         pkey[0x10];
2886 };
2887
2888 struct mlx5_ifc_array128_auto_bits {
2889         u8         array128_auto[16][0x8];
2890 };
2891
2892 struct mlx5_ifc_hca_vport_context_bits {
2893         u8         field_select[0x20];
2894
2895         u8         reserved_at_20[0xe0];
2896
2897         u8         sm_virt_aware[0x1];
2898         u8         has_smi[0x1];
2899         u8         has_raw[0x1];
2900         u8         grh_required[0x1];
2901         u8         reserved_at_104[0xc];
2902         u8         port_physical_state[0x4];
2903         u8         vport_state_policy[0x4];
2904         u8         port_state[0x4];
2905         u8         vport_state[0x4];
2906
2907         u8         reserved_at_120[0x20];
2908
2909         u8         system_image_guid[0x40];
2910
2911         u8         port_guid[0x40];
2912
2913         u8         node_guid[0x40];
2914
2915         u8         cap_mask1[0x20];
2916
2917         u8         cap_mask1_field_select[0x20];
2918
2919         u8         cap_mask2[0x20];
2920
2921         u8         cap_mask2_field_select[0x20];
2922
2923         u8         reserved_at_280[0x80];
2924
2925         u8         lid[0x10];
2926         u8         reserved_at_310[0x4];
2927         u8         init_type_reply[0x4];
2928         u8         lmc[0x3];
2929         u8         subnet_timeout[0x5];
2930
2931         u8         sm_lid[0x10];
2932         u8         sm_sl[0x4];
2933         u8         reserved_at_334[0xc];
2934
2935         u8         qkey_violation_counter[0x10];
2936         u8         pkey_violation_counter[0x10];
2937
2938         u8         reserved_at_360[0xca0];
2939 };
2940
2941 struct mlx5_ifc_esw_vport_context_bits {
2942         u8         reserved_at_0[0x3];
2943         u8         vport_svlan_strip[0x1];
2944         u8         vport_cvlan_strip[0x1];
2945         u8         vport_svlan_insert[0x1];
2946         u8         vport_cvlan_insert[0x2];
2947         u8         reserved_at_8[0x18];
2948
2949         u8         reserved_at_20[0x20];
2950
2951         u8         svlan_cfi[0x1];
2952         u8         svlan_pcp[0x3];
2953         u8         svlan_id[0xc];
2954         u8         cvlan_cfi[0x1];
2955         u8         cvlan_pcp[0x3];
2956         u8         cvlan_id[0xc];
2957
2958         u8         reserved_at_60[0x7a0];
2959 };
2960
2961 enum {
2962         MLX5_EQC_STATUS_OK                = 0x0,
2963         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2964 };
2965
2966 enum {
2967         MLX5_EQC_ST_ARMED  = 0x9,
2968         MLX5_EQC_ST_FIRED  = 0xa,
2969 };
2970
2971 struct mlx5_ifc_eqc_bits {
2972         u8         status[0x4];
2973         u8         reserved_at_4[0x9];
2974         u8         ec[0x1];
2975         u8         oi[0x1];
2976         u8         reserved_at_f[0x5];
2977         u8         st[0x4];
2978         u8         reserved_at_18[0x8];
2979
2980         u8         reserved_at_20[0x20];
2981
2982         u8         reserved_at_40[0x14];
2983         u8         page_offset[0x6];
2984         u8         reserved_at_5a[0x6];
2985
2986         u8         reserved_at_60[0x3];
2987         u8         log_eq_size[0x5];
2988         u8         uar_page[0x18];
2989
2990         u8         reserved_at_80[0x20];
2991
2992         u8         reserved_at_a0[0x18];
2993         u8         intr[0x8];
2994
2995         u8         reserved_at_c0[0x3];
2996         u8         log_page_size[0x5];
2997         u8         reserved_at_c8[0x18];
2998
2999         u8         reserved_at_e0[0x60];
3000
3001         u8         reserved_at_140[0x8];
3002         u8         consumer_counter[0x18];
3003
3004         u8         reserved_at_160[0x8];
3005         u8         producer_counter[0x18];
3006
3007         u8         reserved_at_180[0x80];
3008 };
3009
3010 enum {
3011         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3012         MLX5_DCTC_STATE_DRAINING  = 0x1,
3013         MLX5_DCTC_STATE_DRAINED   = 0x2,
3014 };
3015
3016 enum {
3017         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3018         MLX5_DCTC_CS_RES_NA         = 0x1,
3019         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3020 };
3021
3022 enum {
3023         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3024         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3025         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3026         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3027         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3028 };
3029
3030 struct mlx5_ifc_dctc_bits {
3031         u8         reserved_at_0[0x4];
3032         u8         state[0x4];
3033         u8         reserved_at_8[0x18];
3034
3035         u8         reserved_at_20[0x8];
3036         u8         user_index[0x18];
3037
3038         u8         reserved_at_40[0x8];
3039         u8         cqn[0x18];
3040
3041         u8         counter_set_id[0x8];
3042         u8         atomic_mode[0x4];
3043         u8         rre[0x1];
3044         u8         rwe[0x1];
3045         u8         rae[0x1];
3046         u8         atomic_like_write_en[0x1];
3047         u8         latency_sensitive[0x1];
3048         u8         rlky[0x1];
3049         u8         free_ar[0x1];
3050         u8         reserved_at_73[0xd];
3051
3052         u8         reserved_at_80[0x8];
3053         u8         cs_res[0x8];
3054         u8         reserved_at_90[0x3];
3055         u8         min_rnr_nak[0x5];
3056         u8         reserved_at_98[0x8];
3057
3058         u8         reserved_at_a0[0x8];
3059         u8         srqn_xrqn[0x18];
3060
3061         u8         reserved_at_c0[0x8];
3062         u8         pd[0x18];
3063
3064         u8         tclass[0x8];
3065         u8         reserved_at_e8[0x4];
3066         u8         flow_label[0x14];
3067
3068         u8         dc_access_key[0x40];
3069
3070         u8         reserved_at_140[0x5];
3071         u8         mtu[0x3];
3072         u8         port[0x8];
3073         u8         pkey_index[0x10];
3074
3075         u8         reserved_at_160[0x8];
3076         u8         my_addr_index[0x8];
3077         u8         reserved_at_170[0x8];
3078         u8         hop_limit[0x8];
3079
3080         u8         dc_access_key_violation_count[0x20];
3081
3082         u8         reserved_at_1a0[0x14];
3083         u8         dei_cfi[0x1];
3084         u8         eth_prio[0x3];
3085         u8         ecn[0x2];
3086         u8         dscp[0x6];
3087
3088         u8         reserved_at_1c0[0x40];
3089 };
3090
3091 enum {
3092         MLX5_CQC_STATUS_OK             = 0x0,
3093         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3094         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3095 };
3096
3097 enum {
3098         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3099         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3100 };
3101
3102 enum {
3103         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3104         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3105         MLX5_CQC_ST_FIRED                                 = 0xa,
3106 };
3107
3108 enum {
3109         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3110         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3111         MLX5_CQ_PERIOD_NUM_MODES
3112 };
3113
3114 struct mlx5_ifc_cqc_bits {
3115         u8         status[0x4];
3116         u8         reserved_at_4[0x4];
3117         u8         cqe_sz[0x3];
3118         u8         cc[0x1];
3119         u8         reserved_at_c[0x1];
3120         u8         scqe_break_moderation_en[0x1];
3121         u8         oi[0x1];
3122         u8         cq_period_mode[0x2];
3123         u8         cqe_comp_en[0x1];
3124         u8         mini_cqe_res_format[0x2];
3125         u8         st[0x4];
3126         u8         reserved_at_18[0x8];
3127
3128         u8         reserved_at_20[0x20];
3129
3130         u8         reserved_at_40[0x14];
3131         u8         page_offset[0x6];
3132         u8         reserved_at_5a[0x6];
3133
3134         u8         reserved_at_60[0x3];
3135         u8         log_cq_size[0x5];
3136         u8         uar_page[0x18];
3137
3138         u8         reserved_at_80[0x4];
3139         u8         cq_period[0xc];
3140         u8         cq_max_count[0x10];
3141
3142         u8         reserved_at_a0[0x18];
3143         u8         c_eqn[0x8];
3144
3145         u8         reserved_at_c0[0x3];
3146         u8         log_page_size[0x5];
3147         u8         reserved_at_c8[0x18];
3148
3149         u8         reserved_at_e0[0x20];
3150
3151         u8         reserved_at_100[0x8];
3152         u8         last_notified_index[0x18];
3153
3154         u8         reserved_at_120[0x8];
3155         u8         last_solicit_index[0x18];
3156
3157         u8         reserved_at_140[0x8];
3158         u8         consumer_counter[0x18];
3159
3160         u8         reserved_at_160[0x8];
3161         u8         producer_counter[0x18];
3162
3163         u8         reserved_at_180[0x40];
3164
3165         u8         dbr_addr[0x40];
3166 };
3167
3168 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3169         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3170         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3171         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3172         u8         reserved_at_0[0x800];
3173 };
3174
3175 struct mlx5_ifc_query_adapter_param_block_bits {
3176         u8         reserved_at_0[0xc0];
3177
3178         u8         reserved_at_c0[0x8];
3179         u8         ieee_vendor_id[0x18];
3180
3181         u8         reserved_at_e0[0x10];
3182         u8         vsd_vendor_id[0x10];
3183
3184         u8         vsd[208][0x8];
3185
3186         u8         vsd_contd_psid[16][0x8];
3187 };
3188
3189 enum {
3190         MLX5_XRQC_STATE_GOOD   = 0x0,
3191         MLX5_XRQC_STATE_ERROR  = 0x1,
3192 };
3193
3194 enum {
3195         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3196         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3197 };
3198
3199 enum {
3200         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3201 };
3202
3203 struct mlx5_ifc_tag_matching_topology_context_bits {
3204         u8         log_matching_list_sz[0x4];
3205         u8         reserved_at_4[0xc];
3206         u8         append_next_index[0x10];
3207
3208         u8         sw_phase_cnt[0x10];
3209         u8         hw_phase_cnt[0x10];
3210
3211         u8         reserved_at_40[0x40];
3212 };
3213
3214 struct mlx5_ifc_xrqc_bits {
3215         u8         state[0x4];
3216         u8         rlkey[0x1];
3217         u8         reserved_at_5[0xf];
3218         u8         topology[0x4];
3219         u8         reserved_at_18[0x4];
3220         u8         offload[0x4];
3221
3222         u8         reserved_at_20[0x8];
3223         u8         user_index[0x18];
3224
3225         u8         reserved_at_40[0x8];
3226         u8         cqn[0x18];
3227
3228         u8         reserved_at_60[0xa0];
3229
3230         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3231
3232         u8         reserved_at_180[0x280];
3233
3234         struct mlx5_ifc_wq_bits wq;
3235 };
3236
3237 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3238         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3239         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3240         u8         reserved_at_0[0x20];
3241 };
3242
3243 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3244         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3245         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3246         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3247         u8         reserved_at_0[0x20];
3248 };
3249
3250 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3251         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3252         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3253         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3254         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3255         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3256         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3257         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3258         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3259         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3260         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3261         u8         reserved_at_0[0x7c0];
3262 };
3263
3264 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3265         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3266         u8         reserved_at_0[0x7c0];
3267 };
3268
3269 union mlx5_ifc_event_auto_bits {
3270         struct mlx5_ifc_comp_event_bits comp_event;
3271         struct mlx5_ifc_dct_events_bits dct_events;
3272         struct mlx5_ifc_qp_events_bits qp_events;
3273         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3274         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3275         struct mlx5_ifc_cq_error_bits cq_error;
3276         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3277         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3278         struct mlx5_ifc_gpio_event_bits gpio_event;
3279         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3280         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3281         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3282         u8         reserved_at_0[0xe0];
3283 };
3284
3285 struct mlx5_ifc_health_buffer_bits {
3286         u8         reserved_at_0[0x100];
3287
3288         u8         assert_existptr[0x20];
3289
3290         u8         assert_callra[0x20];
3291
3292         u8         reserved_at_140[0x40];
3293
3294         u8         fw_version[0x20];
3295
3296         u8         hw_id[0x20];
3297
3298         u8         reserved_at_1c0[0x20];
3299
3300         u8         irisc_index[0x8];
3301         u8         synd[0x8];
3302         u8         ext_synd[0x10];
3303 };
3304
3305 struct mlx5_ifc_register_loopback_control_bits {
3306         u8         no_lb[0x1];
3307         u8         reserved_at_1[0x7];
3308         u8         port[0x8];
3309         u8         reserved_at_10[0x10];
3310
3311         u8         reserved_at_20[0x60];
3312 };
3313
3314 struct mlx5_ifc_vport_tc_element_bits {
3315         u8         traffic_class[0x4];
3316         u8         reserved_at_4[0xc];
3317         u8         vport_number[0x10];
3318 };
3319
3320 struct mlx5_ifc_vport_element_bits {
3321         u8         reserved_at_0[0x10];
3322         u8         vport_number[0x10];
3323 };
3324
3325 enum {
3326         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3327         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3328         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3329 };
3330
3331 struct mlx5_ifc_tsar_element_bits {
3332         u8         reserved_at_0[0x8];
3333         u8         tsar_type[0x8];
3334         u8         reserved_at_10[0x10];
3335 };
3336
3337 enum {
3338         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3339         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3340 };
3341
3342 struct mlx5_ifc_teardown_hca_out_bits {
3343         u8         status[0x8];
3344         u8         reserved_at_8[0x18];
3345
3346         u8         syndrome[0x20];
3347
3348         u8         reserved_at_40[0x3f];
3349
3350         u8         force_state[0x1];
3351 };
3352
3353 enum {
3354         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3355         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3356 };
3357
3358 struct mlx5_ifc_teardown_hca_in_bits {
3359         u8         opcode[0x10];
3360         u8         reserved_at_10[0x10];
3361
3362         u8         reserved_at_20[0x10];
3363         u8         op_mod[0x10];
3364
3365         u8         reserved_at_40[0x10];
3366         u8         profile[0x10];
3367
3368         u8         reserved_at_60[0x20];
3369 };
3370
3371 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3372         u8         status[0x8];
3373         u8         reserved_at_8[0x18];
3374
3375         u8         syndrome[0x20];
3376
3377         u8         reserved_at_40[0x40];
3378 };
3379
3380 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3381         u8         opcode[0x10];
3382         u8         reserved_at_10[0x10];
3383
3384         u8         reserved_at_20[0x10];
3385         u8         op_mod[0x10];
3386
3387         u8         reserved_at_40[0x8];
3388         u8         qpn[0x18];
3389
3390         u8         reserved_at_60[0x20];
3391
3392         u8         opt_param_mask[0x20];
3393
3394         u8         reserved_at_a0[0x20];
3395
3396         struct mlx5_ifc_qpc_bits qpc;
3397
3398         u8         reserved_at_800[0x80];
3399 };
3400
3401 struct mlx5_ifc_sqd2rts_qp_out_bits {
3402         u8         status[0x8];
3403         u8         reserved_at_8[0x18];
3404
3405         u8         syndrome[0x20];
3406
3407         u8         reserved_at_40[0x40];
3408 };
3409
3410 struct mlx5_ifc_sqd2rts_qp_in_bits {
3411         u8         opcode[0x10];
3412         u8         reserved_at_10[0x10];
3413
3414         u8         reserved_at_20[0x10];
3415         u8         op_mod[0x10];
3416
3417         u8         reserved_at_40[0x8];
3418         u8         qpn[0x18];
3419
3420         u8         reserved_at_60[0x20];
3421
3422         u8         opt_param_mask[0x20];
3423
3424         u8         reserved_at_a0[0x20];
3425
3426         struct mlx5_ifc_qpc_bits qpc;
3427
3428         u8         reserved_at_800[0x80];
3429 };
3430
3431 struct mlx5_ifc_set_roce_address_out_bits {
3432         u8         status[0x8];
3433         u8         reserved_at_8[0x18];
3434
3435         u8         syndrome[0x20];
3436
3437         u8         reserved_at_40[0x40];
3438 };
3439
3440 struct mlx5_ifc_set_roce_address_in_bits {
3441         u8         opcode[0x10];
3442         u8         reserved_at_10[0x10];
3443
3444         u8         reserved_at_20[0x10];
3445         u8         op_mod[0x10];
3446
3447         u8         roce_address_index[0x10];
3448         u8         reserved_at_50[0xc];
3449         u8         vhca_port_num[0x4];
3450
3451         u8         reserved_at_60[0x20];
3452
3453         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3454 };
3455
3456 struct mlx5_ifc_set_mad_demux_out_bits {
3457         u8         status[0x8];
3458         u8         reserved_at_8[0x18];
3459
3460         u8         syndrome[0x20];
3461
3462         u8         reserved_at_40[0x40];
3463 };
3464
3465 enum {
3466         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3467         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3468 };
3469
3470 struct mlx5_ifc_set_mad_demux_in_bits {
3471         u8         opcode[0x10];
3472         u8         reserved_at_10[0x10];
3473
3474         u8         reserved_at_20[0x10];
3475         u8         op_mod[0x10];
3476
3477         u8         reserved_at_40[0x20];
3478
3479         u8         reserved_at_60[0x6];
3480         u8         demux_mode[0x2];
3481         u8         reserved_at_68[0x18];
3482 };
3483
3484 struct mlx5_ifc_set_l2_table_entry_out_bits {
3485         u8         status[0x8];
3486         u8         reserved_at_8[0x18];
3487
3488         u8         syndrome[0x20];
3489
3490         u8         reserved_at_40[0x40];
3491 };
3492
3493 struct mlx5_ifc_set_l2_table_entry_in_bits {
3494         u8         opcode[0x10];
3495         u8         reserved_at_10[0x10];
3496
3497         u8         reserved_at_20[0x10];
3498         u8         op_mod[0x10];
3499
3500         u8         reserved_at_40[0x60];
3501
3502         u8         reserved_at_a0[0x8];
3503         u8         table_index[0x18];
3504
3505         u8         reserved_at_c0[0x20];
3506
3507         u8         reserved_at_e0[0x13];
3508         u8         vlan_valid[0x1];
3509         u8         vlan[0xc];
3510
3511         struct mlx5_ifc_mac_address_layout_bits mac_address;
3512
3513         u8         reserved_at_140[0xc0];
3514 };
3515
3516 struct mlx5_ifc_set_issi_out_bits {
3517         u8         status[0x8];
3518         u8         reserved_at_8[0x18];
3519
3520         u8         syndrome[0x20];
3521
3522         u8         reserved_at_40[0x40];
3523 };
3524
3525 struct mlx5_ifc_set_issi_in_bits {
3526         u8         opcode[0x10];
3527         u8         reserved_at_10[0x10];
3528
3529         u8         reserved_at_20[0x10];
3530         u8         op_mod[0x10];
3531
3532         u8         reserved_at_40[0x10];
3533         u8         current_issi[0x10];
3534
3535         u8         reserved_at_60[0x20];
3536 };
3537
3538 struct mlx5_ifc_set_hca_cap_out_bits {
3539         u8         status[0x8];
3540         u8         reserved_at_8[0x18];
3541
3542         u8         syndrome[0x20];
3543
3544         u8         reserved_at_40[0x40];
3545 };
3546
3547 struct mlx5_ifc_set_hca_cap_in_bits {
3548         u8         opcode[0x10];
3549         u8         reserved_at_10[0x10];
3550
3551         u8         reserved_at_20[0x10];
3552         u8         op_mod[0x10];
3553
3554         u8         reserved_at_40[0x40];
3555
3556         union mlx5_ifc_hca_cap_union_bits capability;
3557 };
3558
3559 enum {
3560         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3561         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3562         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3563         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3564 };
3565
3566 struct mlx5_ifc_set_fte_out_bits {
3567         u8         status[0x8];
3568         u8         reserved_at_8[0x18];
3569
3570         u8         syndrome[0x20];
3571
3572         u8         reserved_at_40[0x40];
3573 };
3574
3575 struct mlx5_ifc_set_fte_in_bits {
3576         u8         opcode[0x10];
3577         u8         reserved_at_10[0x10];
3578
3579         u8         reserved_at_20[0x10];
3580         u8         op_mod[0x10];
3581
3582         u8         other_vport[0x1];
3583         u8         reserved_at_41[0xf];
3584         u8         vport_number[0x10];
3585
3586         u8         reserved_at_60[0x20];
3587
3588         u8         table_type[0x8];
3589         u8         reserved_at_88[0x18];
3590
3591         u8         reserved_at_a0[0x8];
3592         u8         table_id[0x18];
3593
3594         u8         reserved_at_c0[0x18];
3595         u8         modify_enable_mask[0x8];
3596
3597         u8         reserved_at_e0[0x20];
3598
3599         u8         flow_index[0x20];
3600
3601         u8         reserved_at_120[0xe0];
3602
3603         struct mlx5_ifc_flow_context_bits flow_context;
3604 };
3605
3606 struct mlx5_ifc_rts2rts_qp_out_bits {
3607         u8         status[0x8];
3608         u8         reserved_at_8[0x18];
3609
3610         u8         syndrome[0x20];
3611
3612         u8         reserved_at_40[0x40];
3613 };
3614
3615 struct mlx5_ifc_rts2rts_qp_in_bits {
3616         u8         opcode[0x10];
3617         u8         reserved_at_10[0x10];
3618
3619         u8         reserved_at_20[0x10];
3620         u8         op_mod[0x10];
3621
3622         u8         reserved_at_40[0x8];
3623         u8         qpn[0x18];
3624
3625         u8         reserved_at_60[0x20];
3626
3627         u8         opt_param_mask[0x20];
3628
3629         u8         reserved_at_a0[0x20];
3630
3631         struct mlx5_ifc_qpc_bits qpc;
3632
3633         u8         reserved_at_800[0x80];
3634 };
3635
3636 struct mlx5_ifc_rtr2rts_qp_out_bits {
3637         u8         status[0x8];
3638         u8         reserved_at_8[0x18];
3639
3640         u8         syndrome[0x20];
3641
3642         u8         reserved_at_40[0x40];
3643 };
3644
3645 struct mlx5_ifc_rtr2rts_qp_in_bits {
3646         u8         opcode[0x10];
3647         u8         reserved_at_10[0x10];
3648
3649         u8         reserved_at_20[0x10];
3650         u8         op_mod[0x10];
3651
3652         u8         reserved_at_40[0x8];
3653         u8         qpn[0x18];
3654
3655         u8         reserved_at_60[0x20];
3656
3657         u8         opt_param_mask[0x20];
3658
3659         u8         reserved_at_a0[0x20];
3660
3661         struct mlx5_ifc_qpc_bits qpc;
3662
3663         u8         reserved_at_800[0x80];
3664 };
3665
3666 struct mlx5_ifc_rst2init_qp_out_bits {
3667         u8         status[0x8];
3668         u8         reserved_at_8[0x18];
3669
3670         u8         syndrome[0x20];
3671
3672         u8         reserved_at_40[0x40];
3673 };
3674
3675 struct mlx5_ifc_rst2init_qp_in_bits {
3676         u8         opcode[0x10];
3677         u8         reserved_at_10[0x10];
3678
3679         u8         reserved_at_20[0x10];
3680         u8         op_mod[0x10];
3681
3682         u8         reserved_at_40[0x8];
3683         u8         qpn[0x18];
3684
3685         u8         reserved_at_60[0x20];
3686
3687         u8         opt_param_mask[0x20];
3688
3689         u8         reserved_at_a0[0x20];
3690
3691         struct mlx5_ifc_qpc_bits qpc;
3692
3693         u8         reserved_at_800[0x80];
3694 };
3695
3696 struct mlx5_ifc_query_xrq_out_bits {
3697         u8         status[0x8];
3698         u8         reserved_at_8[0x18];
3699
3700         u8         syndrome[0x20];
3701
3702         u8         reserved_at_40[0x40];
3703
3704         struct mlx5_ifc_xrqc_bits xrq_context;
3705 };
3706
3707 struct mlx5_ifc_query_xrq_in_bits {
3708         u8         opcode[0x10];
3709         u8         reserved_at_10[0x10];
3710
3711         u8         reserved_at_20[0x10];
3712         u8         op_mod[0x10];
3713
3714         u8         reserved_at_40[0x8];
3715         u8         xrqn[0x18];
3716
3717         u8         reserved_at_60[0x20];
3718 };
3719
3720 struct mlx5_ifc_query_xrc_srq_out_bits {
3721         u8         status[0x8];
3722         u8         reserved_at_8[0x18];
3723
3724         u8         syndrome[0x20];
3725
3726         u8         reserved_at_40[0x40];
3727
3728         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3729
3730         u8         reserved_at_280[0x600];
3731
3732         u8         pas[0][0x40];
3733 };
3734
3735 struct mlx5_ifc_query_xrc_srq_in_bits {
3736         u8         opcode[0x10];
3737         u8         reserved_at_10[0x10];
3738
3739         u8         reserved_at_20[0x10];
3740         u8         op_mod[0x10];
3741
3742         u8         reserved_at_40[0x8];
3743         u8         xrc_srqn[0x18];
3744
3745         u8         reserved_at_60[0x20];
3746 };
3747
3748 enum {
3749         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3750         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3751 };
3752
3753 struct mlx5_ifc_query_vport_state_out_bits {
3754         u8         status[0x8];
3755         u8         reserved_at_8[0x18];
3756
3757         u8         syndrome[0x20];
3758
3759         u8         reserved_at_40[0x20];
3760
3761         u8         reserved_at_60[0x18];
3762         u8         admin_state[0x4];
3763         u8         state[0x4];
3764 };
3765
3766 enum {
3767         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3768         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3769 };
3770
3771 struct mlx5_ifc_query_vport_state_in_bits {
3772         u8         opcode[0x10];
3773         u8         reserved_at_10[0x10];
3774
3775         u8         reserved_at_20[0x10];
3776         u8         op_mod[0x10];
3777
3778         u8         other_vport[0x1];
3779         u8         reserved_at_41[0xf];
3780         u8         vport_number[0x10];
3781
3782         u8         reserved_at_60[0x20];
3783 };
3784
3785 struct mlx5_ifc_query_vnic_env_out_bits {
3786         u8         status[0x8];
3787         u8         reserved_at_8[0x18];
3788
3789         u8         syndrome[0x20];
3790
3791         u8         reserved_at_40[0x40];
3792
3793         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3794 };
3795
3796 enum {
3797         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3798 };
3799
3800 struct mlx5_ifc_query_vnic_env_in_bits {
3801         u8         opcode[0x10];
3802         u8         reserved_at_10[0x10];
3803
3804         u8         reserved_at_20[0x10];
3805         u8         op_mod[0x10];
3806
3807         u8         other_vport[0x1];
3808         u8         reserved_at_41[0xf];
3809         u8         vport_number[0x10];
3810
3811         u8         reserved_at_60[0x20];
3812 };
3813
3814 struct mlx5_ifc_query_vport_counter_out_bits {
3815         u8         status[0x8];
3816         u8         reserved_at_8[0x18];
3817
3818         u8         syndrome[0x20];
3819
3820         u8         reserved_at_40[0x40];
3821
3822         struct mlx5_ifc_traffic_counter_bits received_errors;
3823
3824         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3825
3826         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3827
3828         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3829
3830         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3831
3832         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3833
3834         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3835
3836         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3837
3838         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3839
3840         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3841
3842         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3843
3844         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3845
3846         u8         reserved_at_680[0xa00];
3847 };
3848
3849 enum {
3850         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3851 };
3852
3853 struct mlx5_ifc_query_vport_counter_in_bits {
3854         u8         opcode[0x10];
3855         u8         reserved_at_10[0x10];
3856
3857         u8         reserved_at_20[0x10];
3858         u8         op_mod[0x10];
3859
3860         u8         other_vport[0x1];
3861         u8         reserved_at_41[0xb];
3862         u8         port_num[0x4];
3863         u8         vport_number[0x10];
3864
3865         u8         reserved_at_60[0x60];
3866
3867         u8         clear[0x1];
3868         u8         reserved_at_c1[0x1f];
3869
3870         u8         reserved_at_e0[0x20];
3871 };
3872
3873 struct mlx5_ifc_query_tis_out_bits {
3874         u8         status[0x8];
3875         u8         reserved_at_8[0x18];
3876
3877         u8         syndrome[0x20];
3878
3879         u8         reserved_at_40[0x40];
3880
3881         struct mlx5_ifc_tisc_bits tis_context;
3882 };
3883
3884 struct mlx5_ifc_query_tis_in_bits {
3885         u8         opcode[0x10];
3886         u8         reserved_at_10[0x10];
3887
3888         u8         reserved_at_20[0x10];
3889         u8         op_mod[0x10];
3890
3891         u8         reserved_at_40[0x8];
3892         u8         tisn[0x18];
3893
3894         u8         reserved_at_60[0x20];
3895 };
3896
3897 struct mlx5_ifc_query_tir_out_bits {
3898         u8         status[0x8];
3899         u8         reserved_at_8[0x18];
3900
3901         u8         syndrome[0x20];
3902
3903         u8         reserved_at_40[0xc0];
3904
3905         struct mlx5_ifc_tirc_bits tir_context;
3906 };
3907
3908 struct mlx5_ifc_query_tir_in_bits {
3909         u8         opcode[0x10];
3910         u8         reserved_at_10[0x10];
3911
3912         u8         reserved_at_20[0x10];
3913         u8         op_mod[0x10];
3914
3915         u8         reserved_at_40[0x8];
3916         u8         tirn[0x18];
3917
3918         u8         reserved_at_60[0x20];
3919 };
3920
3921 struct mlx5_ifc_query_srq_out_bits {
3922         u8         status[0x8];
3923         u8         reserved_at_8[0x18];
3924
3925         u8         syndrome[0x20];
3926
3927         u8         reserved_at_40[0x40];
3928
3929         struct mlx5_ifc_srqc_bits srq_context_entry;
3930
3931         u8         reserved_at_280[0x600];
3932
3933         u8         pas[0][0x40];
3934 };
3935
3936 struct mlx5_ifc_query_srq_in_bits {
3937         u8         opcode[0x10];
3938         u8         reserved_at_10[0x10];
3939
3940         u8         reserved_at_20[0x10];
3941         u8         op_mod[0x10];
3942
3943         u8         reserved_at_40[0x8];
3944         u8         srqn[0x18];
3945
3946         u8         reserved_at_60[0x20];
3947 };
3948
3949 struct mlx5_ifc_query_sq_out_bits {
3950         u8         status[0x8];
3951         u8         reserved_at_8[0x18];
3952
3953         u8         syndrome[0x20];
3954
3955         u8         reserved_at_40[0xc0];
3956
3957         struct mlx5_ifc_sqc_bits sq_context;
3958 };
3959
3960 struct mlx5_ifc_query_sq_in_bits {
3961         u8         opcode[0x10];
3962         u8         reserved_at_10[0x10];
3963
3964         u8         reserved_at_20[0x10];
3965         u8         op_mod[0x10];
3966
3967         u8         reserved_at_40[0x8];
3968         u8         sqn[0x18];
3969
3970         u8         reserved_at_60[0x20];
3971 };
3972
3973 struct mlx5_ifc_query_special_contexts_out_bits {
3974         u8         status[0x8];
3975         u8         reserved_at_8[0x18];
3976
3977         u8         syndrome[0x20];
3978
3979         u8         dump_fill_mkey[0x20];
3980
3981         u8         resd_lkey[0x20];
3982
3983         u8         null_mkey[0x20];
3984
3985         u8         reserved_at_a0[0x60];
3986 };
3987
3988 struct mlx5_ifc_query_special_contexts_in_bits {
3989         u8         opcode[0x10];
3990         u8         reserved_at_10[0x10];
3991
3992         u8         reserved_at_20[0x10];
3993         u8         op_mod[0x10];
3994
3995         u8         reserved_at_40[0x40];
3996 };
3997
3998 struct mlx5_ifc_query_scheduling_element_out_bits {
3999         u8         opcode[0x10];
4000         u8         reserved_at_10[0x10];
4001
4002         u8         reserved_at_20[0x10];
4003         u8         op_mod[0x10];
4004
4005         u8         reserved_at_40[0xc0];
4006
4007         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4008
4009         u8         reserved_at_300[0x100];
4010 };
4011
4012 enum {
4013         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4014 };
4015
4016 struct mlx5_ifc_query_scheduling_element_in_bits {
4017         u8         opcode[0x10];
4018         u8         reserved_at_10[0x10];
4019
4020         u8         reserved_at_20[0x10];
4021         u8         op_mod[0x10];
4022
4023         u8         scheduling_hierarchy[0x8];
4024         u8         reserved_at_48[0x18];
4025
4026         u8         scheduling_element_id[0x20];
4027
4028         u8         reserved_at_80[0x180];
4029 };
4030
4031 struct mlx5_ifc_query_rqt_out_bits {
4032         u8         status[0x8];
4033         u8         reserved_at_8[0x18];
4034
4035         u8         syndrome[0x20];
4036
4037         u8         reserved_at_40[0xc0];
4038
4039         struct mlx5_ifc_rqtc_bits rqt_context;
4040 };
4041
4042 struct mlx5_ifc_query_rqt_in_bits {
4043         u8         opcode[0x10];
4044         u8         reserved_at_10[0x10];
4045
4046         u8         reserved_at_20[0x10];
4047         u8         op_mod[0x10];
4048
4049         u8         reserved_at_40[0x8];
4050         u8         rqtn[0x18];
4051
4052         u8         reserved_at_60[0x20];
4053 };
4054
4055 struct mlx5_ifc_query_rq_out_bits {
4056         u8         status[0x8];
4057         u8         reserved_at_8[0x18];
4058
4059         u8         syndrome[0x20];
4060
4061         u8         reserved_at_40[0xc0];
4062
4063         struct mlx5_ifc_rqc_bits rq_context;
4064 };
4065
4066 struct mlx5_ifc_query_rq_in_bits {
4067         u8         opcode[0x10];
4068         u8         reserved_at_10[0x10];
4069
4070         u8         reserved_at_20[0x10];
4071         u8         op_mod[0x10];
4072
4073         u8         reserved_at_40[0x8];
4074         u8         rqn[0x18];
4075
4076         u8         reserved_at_60[0x20];
4077 };
4078
4079 struct mlx5_ifc_query_roce_address_out_bits {
4080         u8         status[0x8];
4081         u8         reserved_at_8[0x18];
4082
4083         u8         syndrome[0x20];
4084
4085         u8         reserved_at_40[0x40];
4086
4087         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4088 };
4089
4090 struct mlx5_ifc_query_roce_address_in_bits {
4091         u8         opcode[0x10];
4092         u8         reserved_at_10[0x10];
4093
4094         u8         reserved_at_20[0x10];
4095         u8         op_mod[0x10];
4096
4097         u8         roce_address_index[0x10];
4098         u8         reserved_at_50[0xc];
4099         u8         vhca_port_num[0x4];
4100
4101         u8         reserved_at_60[0x20];
4102 };
4103
4104 struct mlx5_ifc_query_rmp_out_bits {
4105         u8         status[0x8];
4106         u8         reserved_at_8[0x18];
4107
4108         u8         syndrome[0x20];
4109
4110         u8         reserved_at_40[0xc0];
4111
4112         struct mlx5_ifc_rmpc_bits rmp_context;
4113 };
4114
4115 struct mlx5_ifc_query_rmp_in_bits {
4116         u8         opcode[0x10];
4117         u8         reserved_at_10[0x10];
4118
4119         u8         reserved_at_20[0x10];
4120         u8         op_mod[0x10];
4121
4122         u8         reserved_at_40[0x8];
4123         u8         rmpn[0x18];
4124
4125         u8         reserved_at_60[0x20];
4126 };
4127
4128 struct mlx5_ifc_query_qp_out_bits {
4129         u8         status[0x8];
4130         u8         reserved_at_8[0x18];
4131
4132         u8         syndrome[0x20];
4133
4134         u8         reserved_at_40[0x40];
4135
4136         u8         opt_param_mask[0x20];
4137
4138         u8         reserved_at_a0[0x20];
4139
4140         struct mlx5_ifc_qpc_bits qpc;
4141
4142         u8         reserved_at_800[0x80];
4143
4144         u8         pas[0][0x40];
4145 };
4146
4147 struct mlx5_ifc_query_qp_in_bits {
4148         u8         opcode[0x10];
4149         u8         reserved_at_10[0x10];
4150
4151         u8         reserved_at_20[0x10];
4152         u8         op_mod[0x10];
4153
4154         u8         reserved_at_40[0x8];
4155         u8         qpn[0x18];
4156
4157         u8         reserved_at_60[0x20];
4158 };
4159
4160 struct mlx5_ifc_query_q_counter_out_bits {
4161         u8         status[0x8];
4162         u8         reserved_at_8[0x18];
4163
4164         u8         syndrome[0x20];
4165
4166         u8         reserved_at_40[0x40];
4167
4168         u8         rx_write_requests[0x20];
4169
4170         u8         reserved_at_a0[0x20];
4171
4172         u8         rx_read_requests[0x20];
4173
4174         u8         reserved_at_e0[0x20];
4175
4176         u8         rx_atomic_requests[0x20];
4177
4178         u8         reserved_at_120[0x20];
4179
4180         u8         rx_dct_connect[0x20];
4181
4182         u8         reserved_at_160[0x20];
4183
4184         u8         out_of_buffer[0x20];
4185
4186         u8         reserved_at_1a0[0x20];
4187
4188         u8         out_of_sequence[0x20];
4189
4190         u8         reserved_at_1e0[0x20];
4191
4192         u8         duplicate_request[0x20];
4193
4194         u8         reserved_at_220[0x20];
4195
4196         u8         rnr_nak_retry_err[0x20];
4197
4198         u8         reserved_at_260[0x20];
4199
4200         u8         packet_seq_err[0x20];
4201
4202         u8         reserved_at_2a0[0x20];
4203
4204         u8         implied_nak_seq_err[0x20];
4205
4206         u8         reserved_at_2e0[0x20];
4207
4208         u8         local_ack_timeout_err[0x20];
4209
4210         u8         reserved_at_320[0xa0];
4211
4212         u8         resp_local_length_error[0x20];
4213
4214         u8         req_local_length_error[0x20];
4215
4216         u8         resp_local_qp_error[0x20];
4217
4218         u8         local_operation_error[0x20];
4219
4220         u8         resp_local_protection[0x20];
4221
4222         u8         req_local_protection[0x20];
4223
4224         u8         resp_cqe_error[0x20];
4225
4226         u8         req_cqe_error[0x20];
4227
4228         u8         req_mw_binding[0x20];
4229
4230         u8         req_bad_response[0x20];
4231
4232         u8         req_remote_invalid_request[0x20];
4233
4234         u8         resp_remote_invalid_request[0x20];
4235
4236         u8         req_remote_access_errors[0x20];
4237
4238         u8         resp_remote_access_errors[0x20];
4239
4240         u8         req_remote_operation_errors[0x20];
4241
4242         u8         req_transport_retries_exceeded[0x20];
4243
4244         u8         cq_overflow[0x20];
4245
4246         u8         resp_cqe_flush_error[0x20];
4247
4248         u8         req_cqe_flush_error[0x20];
4249
4250         u8         reserved_at_620[0x1e0];
4251 };
4252
4253 struct mlx5_ifc_query_q_counter_in_bits {
4254         u8         opcode[0x10];
4255         u8         reserved_at_10[0x10];
4256
4257         u8         reserved_at_20[0x10];
4258         u8         op_mod[0x10];
4259
4260         u8         reserved_at_40[0x80];
4261
4262         u8         clear[0x1];
4263         u8         reserved_at_c1[0x1f];
4264
4265         u8         reserved_at_e0[0x18];
4266         u8         counter_set_id[0x8];
4267 };
4268
4269 struct mlx5_ifc_query_pages_out_bits {
4270         u8         status[0x8];
4271         u8         reserved_at_8[0x18];
4272
4273         u8         syndrome[0x20];
4274
4275         u8         reserved_at_40[0x10];
4276         u8         function_id[0x10];
4277
4278         u8         num_pages[0x20];
4279 };
4280
4281 enum {
4282         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4283         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4284         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4285 };
4286
4287 struct mlx5_ifc_query_pages_in_bits {
4288         u8         opcode[0x10];
4289         u8         reserved_at_10[0x10];
4290
4291         u8         reserved_at_20[0x10];
4292         u8         op_mod[0x10];
4293
4294         u8         reserved_at_40[0x10];
4295         u8         function_id[0x10];
4296
4297         u8         reserved_at_60[0x20];
4298 };
4299
4300 struct mlx5_ifc_query_nic_vport_context_out_bits {
4301         u8         status[0x8];
4302         u8         reserved_at_8[0x18];
4303
4304         u8         syndrome[0x20];
4305
4306         u8         reserved_at_40[0x40];
4307
4308         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4309 };
4310
4311 struct mlx5_ifc_query_nic_vport_context_in_bits {
4312         u8         opcode[0x10];
4313         u8         reserved_at_10[0x10];
4314
4315         u8         reserved_at_20[0x10];
4316         u8         op_mod[0x10];
4317
4318         u8         other_vport[0x1];
4319         u8         reserved_at_41[0xf];
4320         u8         vport_number[0x10];
4321
4322         u8         reserved_at_60[0x5];
4323         u8         allowed_list_type[0x3];
4324         u8         reserved_at_68[0x18];
4325 };
4326
4327 struct mlx5_ifc_query_mkey_out_bits {
4328         u8         status[0x8];
4329         u8         reserved_at_8[0x18];
4330
4331         u8         syndrome[0x20];
4332
4333         u8         reserved_at_40[0x40];
4334
4335         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4336
4337         u8         reserved_at_280[0x600];
4338
4339         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4340
4341         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4342 };
4343
4344 struct mlx5_ifc_query_mkey_in_bits {
4345         u8         opcode[0x10];
4346         u8         reserved_at_10[0x10];
4347
4348         u8         reserved_at_20[0x10];
4349         u8         op_mod[0x10];
4350
4351         u8         reserved_at_40[0x8];
4352         u8         mkey_index[0x18];
4353
4354         u8         pg_access[0x1];
4355         u8         reserved_at_61[0x1f];
4356 };
4357
4358 struct mlx5_ifc_query_mad_demux_out_bits {
4359         u8         status[0x8];
4360         u8         reserved_at_8[0x18];
4361
4362         u8         syndrome[0x20];
4363
4364         u8         reserved_at_40[0x40];
4365
4366         u8         mad_dumux_parameters_block[0x20];
4367 };
4368
4369 struct mlx5_ifc_query_mad_demux_in_bits {
4370         u8         opcode[0x10];
4371         u8         reserved_at_10[0x10];
4372
4373         u8         reserved_at_20[0x10];
4374         u8         op_mod[0x10];
4375
4376         u8         reserved_at_40[0x40];
4377 };
4378
4379 struct mlx5_ifc_query_l2_table_entry_out_bits {
4380         u8         status[0x8];
4381         u8         reserved_at_8[0x18];
4382
4383         u8         syndrome[0x20];
4384
4385         u8         reserved_at_40[0xa0];
4386
4387         u8         reserved_at_e0[0x13];
4388         u8         vlan_valid[0x1];
4389         u8         vlan[0xc];
4390
4391         struct mlx5_ifc_mac_address_layout_bits mac_address;
4392
4393         u8         reserved_at_140[0xc0];
4394 };
4395
4396 struct mlx5_ifc_query_l2_table_entry_in_bits {
4397         u8         opcode[0x10];
4398         u8         reserved_at_10[0x10];
4399
4400         u8         reserved_at_20[0x10];
4401         u8         op_mod[0x10];
4402
4403         u8         reserved_at_40[0x60];
4404
4405         u8         reserved_at_a0[0x8];
4406         u8         table_index[0x18];
4407
4408         u8         reserved_at_c0[0x140];
4409 };
4410
4411 struct mlx5_ifc_query_issi_out_bits {
4412         u8         status[0x8];
4413         u8         reserved_at_8[0x18];
4414
4415         u8         syndrome[0x20];
4416
4417         u8         reserved_at_40[0x10];
4418         u8         current_issi[0x10];
4419
4420         u8         reserved_at_60[0xa0];
4421
4422         u8         reserved_at_100[76][0x8];
4423         u8         supported_issi_dw0[0x20];
4424 };
4425
4426 struct mlx5_ifc_query_issi_in_bits {
4427         u8         opcode[0x10];
4428         u8         reserved_at_10[0x10];
4429
4430         u8         reserved_at_20[0x10];
4431         u8         op_mod[0x10];
4432
4433         u8         reserved_at_40[0x40];
4434 };
4435
4436 struct mlx5_ifc_set_driver_version_out_bits {
4437         u8         status[0x8];
4438         u8         reserved_0[0x18];
4439
4440         u8         syndrome[0x20];
4441         u8         reserved_1[0x40];
4442 };
4443
4444 struct mlx5_ifc_set_driver_version_in_bits {
4445         u8         opcode[0x10];
4446         u8         reserved_0[0x10];
4447
4448         u8         reserved_1[0x10];
4449         u8         op_mod[0x10];
4450
4451         u8         reserved_2[0x40];
4452         u8         driver_version[64][0x8];
4453 };
4454
4455 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4456         u8         status[0x8];
4457         u8         reserved_at_8[0x18];
4458
4459         u8         syndrome[0x20];
4460
4461         u8         reserved_at_40[0x40];
4462
4463         struct mlx5_ifc_pkey_bits pkey[0];
4464 };
4465
4466 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4467         u8         opcode[0x10];
4468         u8         reserved_at_10[0x10];
4469
4470         u8         reserved_at_20[0x10];
4471         u8         op_mod[0x10];
4472
4473         u8         other_vport[0x1];
4474         u8         reserved_at_41[0xb];
4475         u8         port_num[0x4];
4476         u8         vport_number[0x10];
4477
4478         u8         reserved_at_60[0x10];
4479         u8         pkey_index[0x10];
4480 };
4481
4482 enum {
4483         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4484         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4485         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4486 };
4487
4488 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4489         u8         status[0x8];
4490         u8         reserved_at_8[0x18];
4491
4492         u8         syndrome[0x20];
4493
4494         u8         reserved_at_40[0x20];
4495
4496         u8         gids_num[0x10];
4497         u8         reserved_at_70[0x10];
4498
4499         struct mlx5_ifc_array128_auto_bits gid[0];
4500 };
4501
4502 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4503         u8         opcode[0x10];
4504         u8         reserved_at_10[0x10];
4505
4506         u8         reserved_at_20[0x10];
4507         u8         op_mod[0x10];
4508
4509         u8         other_vport[0x1];
4510         u8         reserved_at_41[0xb];
4511         u8         port_num[0x4];
4512         u8         vport_number[0x10];
4513
4514         u8         reserved_at_60[0x10];
4515         u8         gid_index[0x10];
4516 };
4517
4518 struct mlx5_ifc_query_hca_vport_context_out_bits {
4519         u8         status[0x8];
4520         u8         reserved_at_8[0x18];
4521
4522         u8         syndrome[0x20];
4523
4524         u8         reserved_at_40[0x40];
4525
4526         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4527 };
4528
4529 struct mlx5_ifc_query_hca_vport_context_in_bits {
4530         u8         opcode[0x10];
4531         u8         reserved_at_10[0x10];
4532
4533         u8         reserved_at_20[0x10];
4534         u8         op_mod[0x10];
4535
4536         u8         other_vport[0x1];
4537         u8         reserved_at_41[0xb];
4538         u8         port_num[0x4];
4539         u8         vport_number[0x10];
4540
4541         u8         reserved_at_60[0x20];
4542 };
4543
4544 struct mlx5_ifc_query_hca_cap_out_bits {
4545         u8         status[0x8];
4546         u8         reserved_at_8[0x18];
4547
4548         u8         syndrome[0x20];
4549
4550         u8         reserved_at_40[0x40];
4551
4552         union mlx5_ifc_hca_cap_union_bits capability;
4553 };
4554
4555 struct mlx5_ifc_query_hca_cap_in_bits {
4556         u8         opcode[0x10];
4557         u8         reserved_at_10[0x10];
4558
4559         u8         reserved_at_20[0x10];
4560         u8         op_mod[0x10];
4561
4562         u8         reserved_at_40[0x40];
4563 };
4564
4565 struct mlx5_ifc_query_flow_table_out_bits {
4566         u8         status[0x8];
4567         u8         reserved_at_8[0x18];
4568
4569         u8         syndrome[0x20];
4570
4571         u8         reserved_at_40[0x80];
4572
4573         u8         reserved_at_c0[0x8];
4574         u8         level[0x8];
4575         u8         reserved_at_d0[0x8];
4576         u8         log_size[0x8];
4577
4578         u8         reserved_at_e0[0x120];
4579 };
4580
4581 struct mlx5_ifc_query_flow_table_in_bits {
4582         u8         opcode[0x10];
4583         u8         reserved_at_10[0x10];
4584
4585         u8         reserved_at_20[0x10];
4586         u8         op_mod[0x10];
4587
4588         u8         reserved_at_40[0x40];
4589
4590         u8         table_type[0x8];
4591         u8         reserved_at_88[0x18];
4592
4593         u8         reserved_at_a0[0x8];
4594         u8         table_id[0x18];
4595
4596         u8         reserved_at_c0[0x140];
4597 };
4598
4599 struct mlx5_ifc_query_fte_out_bits {
4600         u8         status[0x8];
4601         u8         reserved_at_8[0x18];
4602
4603         u8         syndrome[0x20];
4604
4605         u8         reserved_at_40[0x1c0];
4606
4607         struct mlx5_ifc_flow_context_bits flow_context;
4608 };
4609
4610 struct mlx5_ifc_query_fte_in_bits {
4611         u8         opcode[0x10];
4612         u8         reserved_at_10[0x10];
4613
4614         u8         reserved_at_20[0x10];
4615         u8         op_mod[0x10];
4616
4617         u8         reserved_at_40[0x40];
4618
4619         u8         table_type[0x8];
4620         u8         reserved_at_88[0x18];
4621
4622         u8         reserved_at_a0[0x8];
4623         u8         table_id[0x18];
4624
4625         u8         reserved_at_c0[0x40];
4626
4627         u8         flow_index[0x20];
4628
4629         u8         reserved_at_120[0xe0];
4630 };
4631
4632 enum {
4633         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4634         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4635         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4636         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
4637 };
4638
4639 struct mlx5_ifc_query_flow_group_out_bits {
4640         u8         status[0x8];
4641         u8         reserved_at_8[0x18];
4642
4643         u8         syndrome[0x20];
4644
4645         u8         reserved_at_40[0xa0];
4646
4647         u8         start_flow_index[0x20];
4648
4649         u8         reserved_at_100[0x20];
4650
4651         u8         end_flow_index[0x20];
4652
4653         u8         reserved_at_140[0xa0];
4654
4655         u8         reserved_at_1e0[0x18];
4656         u8         match_criteria_enable[0x8];
4657
4658         struct mlx5_ifc_fte_match_param_bits match_criteria;
4659
4660         u8         reserved_at_1200[0xe00];
4661 };
4662
4663 struct mlx5_ifc_query_flow_group_in_bits {
4664         u8         opcode[0x10];
4665         u8         reserved_at_10[0x10];
4666
4667         u8         reserved_at_20[0x10];
4668         u8         op_mod[0x10];
4669
4670         u8         reserved_at_40[0x40];
4671
4672         u8         table_type[0x8];
4673         u8         reserved_at_88[0x18];
4674
4675         u8         reserved_at_a0[0x8];
4676         u8         table_id[0x18];
4677
4678         u8         group_id[0x20];
4679
4680         u8         reserved_at_e0[0x120];
4681 };
4682
4683 struct mlx5_ifc_query_flow_counter_out_bits {
4684         u8         status[0x8];
4685         u8         reserved_at_8[0x18];
4686
4687         u8         syndrome[0x20];
4688
4689         u8         reserved_at_40[0x40];
4690
4691         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4692 };
4693
4694 struct mlx5_ifc_query_flow_counter_in_bits {
4695         u8         opcode[0x10];
4696         u8         reserved_at_10[0x10];
4697
4698         u8         reserved_at_20[0x10];
4699         u8         op_mod[0x10];
4700
4701         u8         reserved_at_40[0x80];
4702
4703         u8         clear[0x1];
4704         u8         reserved_at_c1[0xf];
4705         u8         num_of_counters[0x10];
4706
4707         u8         flow_counter_id[0x20];
4708 };
4709
4710 struct mlx5_ifc_query_esw_vport_context_out_bits {
4711         u8         status[0x8];
4712         u8         reserved_at_8[0x18];
4713
4714         u8         syndrome[0x20];
4715
4716         u8         reserved_at_40[0x40];
4717
4718         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4719 };
4720
4721 struct mlx5_ifc_query_esw_vport_context_in_bits {
4722         u8         opcode[0x10];
4723         u8         reserved_at_10[0x10];
4724
4725         u8         reserved_at_20[0x10];
4726         u8         op_mod[0x10];
4727
4728         u8         other_vport[0x1];
4729         u8         reserved_at_41[0xf];
4730         u8         vport_number[0x10];
4731
4732         u8         reserved_at_60[0x20];
4733 };
4734
4735 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4736         u8         status[0x8];
4737         u8         reserved_at_8[0x18];
4738
4739         u8         syndrome[0x20];
4740
4741         u8         reserved_at_40[0x40];
4742 };
4743
4744 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4745         u8         reserved_at_0[0x1c];
4746         u8         vport_cvlan_insert[0x1];
4747         u8         vport_svlan_insert[0x1];
4748         u8         vport_cvlan_strip[0x1];
4749         u8         vport_svlan_strip[0x1];
4750 };
4751
4752 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4753         u8         opcode[0x10];
4754         u8         reserved_at_10[0x10];
4755
4756         u8         reserved_at_20[0x10];
4757         u8         op_mod[0x10];
4758
4759         u8         other_vport[0x1];
4760         u8         reserved_at_41[0xf];
4761         u8         vport_number[0x10];
4762
4763         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4764
4765         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4766 };
4767
4768 struct mlx5_ifc_query_eq_out_bits {
4769         u8         status[0x8];
4770         u8         reserved_at_8[0x18];
4771
4772         u8         syndrome[0x20];
4773
4774         u8         reserved_at_40[0x40];
4775
4776         struct mlx5_ifc_eqc_bits eq_context_entry;
4777
4778         u8         reserved_at_280[0x40];
4779
4780         u8         event_bitmask[0x40];
4781
4782         u8         reserved_at_300[0x580];
4783
4784         u8         pas[0][0x40];
4785 };
4786
4787 struct mlx5_ifc_query_eq_in_bits {
4788         u8         opcode[0x10];
4789         u8         reserved_at_10[0x10];
4790
4791         u8         reserved_at_20[0x10];
4792         u8         op_mod[0x10];
4793
4794         u8         reserved_at_40[0x18];
4795         u8         eq_number[0x8];
4796
4797         u8         reserved_at_60[0x20];
4798 };
4799
4800 struct mlx5_ifc_encap_header_in_bits {
4801         u8         reserved_at_0[0x5];
4802         u8         header_type[0x3];
4803         u8         reserved_at_8[0xe];
4804         u8         encap_header_size[0xa];
4805
4806         u8         reserved_at_20[0x10];
4807         u8         encap_header[2][0x8];
4808
4809         u8         more_encap_header[0][0x8];
4810 };
4811
4812 struct mlx5_ifc_query_encap_header_out_bits {
4813         u8         status[0x8];
4814         u8         reserved_at_8[0x18];
4815
4816         u8         syndrome[0x20];
4817
4818         u8         reserved_at_40[0xa0];
4819
4820         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4821 };
4822
4823 struct mlx5_ifc_query_encap_header_in_bits {
4824         u8         opcode[0x10];
4825         u8         reserved_at_10[0x10];
4826
4827         u8         reserved_at_20[0x10];
4828         u8         op_mod[0x10];
4829
4830         u8         encap_id[0x20];
4831
4832         u8         reserved_at_60[0xa0];
4833 };
4834
4835 struct mlx5_ifc_alloc_encap_header_out_bits {
4836         u8         status[0x8];
4837         u8         reserved_at_8[0x18];
4838
4839         u8         syndrome[0x20];
4840
4841         u8         encap_id[0x20];
4842
4843         u8         reserved_at_60[0x20];
4844 };
4845
4846 struct mlx5_ifc_alloc_encap_header_in_bits {
4847         u8         opcode[0x10];
4848         u8         reserved_at_10[0x10];
4849
4850         u8         reserved_at_20[0x10];
4851         u8         op_mod[0x10];
4852
4853         u8         reserved_at_40[0xa0];
4854
4855         struct mlx5_ifc_encap_header_in_bits encap_header;
4856 };
4857
4858 struct mlx5_ifc_dealloc_encap_header_out_bits {
4859         u8         status[0x8];
4860         u8         reserved_at_8[0x18];
4861
4862         u8         syndrome[0x20];
4863
4864         u8         reserved_at_40[0x40];
4865 };
4866
4867 struct mlx5_ifc_dealloc_encap_header_in_bits {
4868         u8         opcode[0x10];
4869         u8         reserved_at_10[0x10];
4870
4871         u8         reserved_20[0x10];
4872         u8         op_mod[0x10];
4873
4874         u8         encap_id[0x20];
4875
4876         u8         reserved_60[0x20];
4877 };
4878
4879 struct mlx5_ifc_set_action_in_bits {
4880         u8         action_type[0x4];
4881         u8         field[0xc];
4882         u8         reserved_at_10[0x3];
4883         u8         offset[0x5];
4884         u8         reserved_at_18[0x3];
4885         u8         length[0x5];
4886
4887         u8         data[0x20];
4888 };
4889
4890 struct mlx5_ifc_add_action_in_bits {
4891         u8         action_type[0x4];
4892         u8         field[0xc];
4893         u8         reserved_at_10[0x10];
4894
4895         u8         data[0x20];
4896 };
4897
4898 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4899         struct mlx5_ifc_set_action_in_bits set_action_in;
4900         struct mlx5_ifc_add_action_in_bits add_action_in;
4901         u8         reserved_at_0[0x40];
4902 };
4903
4904 enum {
4905         MLX5_ACTION_TYPE_SET   = 0x1,
4906         MLX5_ACTION_TYPE_ADD   = 0x2,
4907 };
4908
4909 enum {
4910         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4911         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4912         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4913         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4914         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4915         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4916         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4917         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4918         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4919         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4920         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4921         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4922         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4923         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4924         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4925         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4926         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4927         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4928         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4929         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4930         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4931         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4932         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4933 };
4934
4935 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4936         u8         status[0x8];
4937         u8         reserved_at_8[0x18];
4938
4939         u8         syndrome[0x20];
4940
4941         u8         modify_header_id[0x20];
4942
4943         u8         reserved_at_60[0x20];
4944 };
4945
4946 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4947         u8         opcode[0x10];
4948         u8         reserved_at_10[0x10];
4949
4950         u8         reserved_at_20[0x10];
4951         u8         op_mod[0x10];
4952
4953         u8         reserved_at_40[0x20];
4954
4955         u8         table_type[0x8];
4956         u8         reserved_at_68[0x10];
4957         u8         num_of_actions[0x8];
4958
4959         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4960 };
4961
4962 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4963         u8         status[0x8];
4964         u8         reserved_at_8[0x18];
4965
4966         u8         syndrome[0x20];
4967
4968         u8         reserved_at_40[0x40];
4969 };
4970
4971 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4972         u8         opcode[0x10];
4973         u8         reserved_at_10[0x10];
4974
4975         u8         reserved_at_20[0x10];
4976         u8         op_mod[0x10];
4977
4978         u8         modify_header_id[0x20];
4979
4980         u8         reserved_at_60[0x20];
4981 };
4982
4983 struct mlx5_ifc_query_dct_out_bits {
4984         u8         status[0x8];
4985         u8         reserved_at_8[0x18];
4986
4987         u8         syndrome[0x20];
4988
4989         u8         reserved_at_40[0x40];
4990
4991         struct mlx5_ifc_dctc_bits dct_context_entry;
4992
4993         u8         reserved_at_280[0x180];
4994 };
4995
4996 struct mlx5_ifc_query_dct_in_bits {
4997         u8         opcode[0x10];
4998         u8         reserved_at_10[0x10];
4999
5000         u8         reserved_at_20[0x10];
5001         u8         op_mod[0x10];
5002
5003         u8         reserved_at_40[0x8];
5004         u8         dctn[0x18];
5005
5006         u8         reserved_at_60[0x20];
5007 };
5008
5009 struct mlx5_ifc_query_cq_out_bits {
5010         u8         status[0x8];
5011         u8         reserved_at_8[0x18];
5012
5013         u8         syndrome[0x20];
5014
5015         u8         reserved_at_40[0x40];
5016
5017         struct mlx5_ifc_cqc_bits cq_context;
5018
5019         u8         reserved_at_280[0x600];
5020
5021         u8         pas[0][0x40];
5022 };
5023
5024 struct mlx5_ifc_query_cq_in_bits {
5025         u8         opcode[0x10];
5026         u8         reserved_at_10[0x10];
5027
5028         u8         reserved_at_20[0x10];
5029         u8         op_mod[0x10];
5030
5031         u8         reserved_at_40[0x8];
5032         u8         cqn[0x18];
5033
5034         u8         reserved_at_60[0x20];
5035 };
5036
5037 struct mlx5_ifc_query_cong_status_out_bits {
5038         u8         status[0x8];
5039         u8         reserved_at_8[0x18];
5040
5041         u8         syndrome[0x20];
5042
5043         u8         reserved_at_40[0x20];
5044
5045         u8         enable[0x1];
5046         u8         tag_enable[0x1];
5047         u8         reserved_at_62[0x1e];
5048 };
5049
5050 struct mlx5_ifc_query_cong_status_in_bits {
5051         u8         opcode[0x10];
5052         u8         reserved_at_10[0x10];
5053
5054         u8         reserved_at_20[0x10];
5055         u8         op_mod[0x10];
5056
5057         u8         reserved_at_40[0x18];
5058         u8         priority[0x4];
5059         u8         cong_protocol[0x4];
5060
5061         u8         reserved_at_60[0x20];
5062 };
5063
5064 struct mlx5_ifc_query_cong_statistics_out_bits {
5065         u8         status[0x8];
5066         u8         reserved_at_8[0x18];
5067
5068         u8         syndrome[0x20];
5069
5070         u8         reserved_at_40[0x40];
5071
5072         u8         rp_cur_flows[0x20];
5073
5074         u8         sum_flows[0x20];
5075
5076         u8         rp_cnp_ignored_high[0x20];
5077
5078         u8         rp_cnp_ignored_low[0x20];
5079
5080         u8         rp_cnp_handled_high[0x20];
5081
5082         u8         rp_cnp_handled_low[0x20];
5083
5084         u8         reserved_at_140[0x100];
5085
5086         u8         time_stamp_high[0x20];
5087
5088         u8         time_stamp_low[0x20];
5089
5090         u8         accumulators_period[0x20];
5091
5092         u8         np_ecn_marked_roce_packets_high[0x20];
5093
5094         u8         np_ecn_marked_roce_packets_low[0x20];
5095
5096         u8         np_cnp_sent_high[0x20];
5097
5098         u8         np_cnp_sent_low[0x20];
5099
5100         u8         reserved_at_320[0x560];
5101 };
5102
5103 struct mlx5_ifc_query_cong_statistics_in_bits {
5104         u8         opcode[0x10];
5105         u8         reserved_at_10[0x10];
5106
5107         u8         reserved_at_20[0x10];
5108         u8         op_mod[0x10];
5109
5110         u8         clear[0x1];
5111         u8         reserved_at_41[0x1f];
5112
5113         u8         reserved_at_60[0x20];
5114 };
5115
5116 struct mlx5_ifc_query_cong_params_out_bits {
5117         u8         status[0x8];
5118         u8         reserved_at_8[0x18];
5119
5120         u8         syndrome[0x20];
5121
5122         u8         reserved_at_40[0x40];
5123
5124         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5125 };
5126
5127 struct mlx5_ifc_query_cong_params_in_bits {
5128         u8         opcode[0x10];
5129         u8         reserved_at_10[0x10];
5130
5131         u8         reserved_at_20[0x10];
5132         u8         op_mod[0x10];
5133
5134         u8         reserved_at_40[0x1c];
5135         u8         cong_protocol[0x4];
5136
5137         u8         reserved_at_60[0x20];
5138 };
5139
5140 struct mlx5_ifc_query_adapter_out_bits {
5141         u8         status[0x8];
5142         u8         reserved_at_8[0x18];
5143
5144         u8         syndrome[0x20];
5145
5146         u8         reserved_at_40[0x40];
5147
5148         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5149 };
5150
5151 struct mlx5_ifc_query_adapter_in_bits {
5152         u8         opcode[0x10];
5153         u8         reserved_at_10[0x10];
5154
5155         u8         reserved_at_20[0x10];
5156         u8         op_mod[0x10];
5157
5158         u8         reserved_at_40[0x40];
5159 };
5160
5161 struct mlx5_ifc_qp_2rst_out_bits {
5162         u8         status[0x8];
5163         u8         reserved_at_8[0x18];
5164
5165         u8         syndrome[0x20];
5166
5167         u8         reserved_at_40[0x40];
5168 };
5169
5170 struct mlx5_ifc_qp_2rst_in_bits {
5171         u8         opcode[0x10];
5172         u8         reserved_at_10[0x10];
5173
5174         u8         reserved_at_20[0x10];
5175         u8         op_mod[0x10];
5176
5177         u8         reserved_at_40[0x8];
5178         u8         qpn[0x18];
5179
5180         u8         reserved_at_60[0x20];
5181 };
5182
5183 struct mlx5_ifc_qp_2err_out_bits {
5184         u8         status[0x8];
5185         u8         reserved_at_8[0x18];
5186
5187         u8         syndrome[0x20];
5188
5189         u8         reserved_at_40[0x40];
5190 };
5191
5192 struct mlx5_ifc_qp_2err_in_bits {
5193         u8         opcode[0x10];
5194         u8         reserved_at_10[0x10];
5195
5196         u8         reserved_at_20[0x10];
5197         u8         op_mod[0x10];
5198
5199         u8         reserved_at_40[0x8];
5200         u8         qpn[0x18];
5201
5202         u8         reserved_at_60[0x20];
5203 };
5204
5205 struct mlx5_ifc_page_fault_resume_out_bits {
5206         u8         status[0x8];
5207         u8         reserved_at_8[0x18];
5208
5209         u8         syndrome[0x20];
5210
5211         u8         reserved_at_40[0x40];
5212 };
5213
5214 struct mlx5_ifc_page_fault_resume_in_bits {
5215         u8         opcode[0x10];
5216         u8         reserved_at_10[0x10];
5217
5218         u8         reserved_at_20[0x10];
5219         u8         op_mod[0x10];
5220
5221         u8         error[0x1];
5222         u8         reserved_at_41[0x4];
5223         u8         page_fault_type[0x3];
5224         u8         wq_number[0x18];
5225
5226         u8         reserved_at_60[0x8];
5227         u8         token[0x18];
5228 };
5229
5230 struct mlx5_ifc_nop_out_bits {
5231         u8         status[0x8];
5232         u8         reserved_at_8[0x18];
5233
5234         u8         syndrome[0x20];
5235
5236         u8         reserved_at_40[0x40];
5237 };
5238
5239 struct mlx5_ifc_nop_in_bits {
5240         u8         opcode[0x10];
5241         u8         reserved_at_10[0x10];
5242
5243         u8         reserved_at_20[0x10];
5244         u8         op_mod[0x10];
5245
5246         u8         reserved_at_40[0x40];
5247 };
5248
5249 struct mlx5_ifc_modify_vport_state_out_bits {
5250         u8         status[0x8];
5251         u8         reserved_at_8[0x18];
5252
5253         u8         syndrome[0x20];
5254
5255         u8         reserved_at_40[0x40];
5256 };
5257
5258 struct mlx5_ifc_modify_vport_state_in_bits {
5259         u8         opcode[0x10];
5260         u8         reserved_at_10[0x10];
5261
5262         u8         reserved_at_20[0x10];
5263         u8         op_mod[0x10];
5264
5265         u8         other_vport[0x1];
5266         u8         reserved_at_41[0xf];
5267         u8         vport_number[0x10];
5268
5269         u8         reserved_at_60[0x18];
5270         u8         admin_state[0x4];
5271         u8         reserved_at_7c[0x4];
5272 };
5273
5274 struct mlx5_ifc_modify_tis_out_bits {
5275         u8         status[0x8];
5276         u8         reserved_at_8[0x18];
5277
5278         u8         syndrome[0x20];
5279
5280         u8         reserved_at_40[0x40];
5281 };
5282
5283 struct mlx5_ifc_modify_tis_bitmask_bits {
5284         u8         reserved_at_0[0x20];
5285
5286         u8         reserved_at_20[0x1d];
5287         u8         lag_tx_port_affinity[0x1];
5288         u8         strict_lag_tx_port_affinity[0x1];
5289         u8         prio[0x1];
5290 };
5291
5292 struct mlx5_ifc_modify_tis_in_bits {
5293         u8         opcode[0x10];
5294         u8         reserved_at_10[0x10];
5295
5296         u8         reserved_at_20[0x10];
5297         u8         op_mod[0x10];
5298
5299         u8         reserved_at_40[0x8];
5300         u8         tisn[0x18];
5301
5302         u8         reserved_at_60[0x20];
5303
5304         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5305
5306         u8         reserved_at_c0[0x40];
5307
5308         struct mlx5_ifc_tisc_bits ctx;
5309 };
5310
5311 struct mlx5_ifc_modify_tir_bitmask_bits {
5312         u8         reserved_at_0[0x20];
5313
5314         u8         reserved_at_20[0x1b];
5315         u8         self_lb_en[0x1];
5316         u8         reserved_at_3c[0x1];
5317         u8         hash[0x1];
5318         u8         reserved_at_3e[0x1];
5319         u8         lro[0x1];
5320 };
5321
5322 struct mlx5_ifc_modify_tir_out_bits {
5323         u8         status[0x8];
5324         u8         reserved_at_8[0x18];
5325
5326         u8         syndrome[0x20];
5327
5328         u8         reserved_at_40[0x40];
5329 };
5330
5331 struct mlx5_ifc_modify_tir_in_bits {
5332         u8         opcode[0x10];
5333         u8         reserved_at_10[0x10];
5334
5335         u8         reserved_at_20[0x10];
5336         u8         op_mod[0x10];
5337
5338         u8         reserved_at_40[0x8];
5339         u8         tirn[0x18];
5340
5341         u8         reserved_at_60[0x20];
5342
5343         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5344
5345         u8         reserved_at_c0[0x40];
5346
5347         struct mlx5_ifc_tirc_bits ctx;
5348 };
5349
5350 struct mlx5_ifc_modify_sq_out_bits {
5351         u8         status[0x8];
5352         u8         reserved_at_8[0x18];
5353
5354         u8         syndrome[0x20];
5355
5356         u8         reserved_at_40[0x40];
5357 };
5358
5359 struct mlx5_ifc_modify_sq_in_bits {
5360         u8         opcode[0x10];
5361         u8         reserved_at_10[0x10];
5362
5363         u8         reserved_at_20[0x10];
5364         u8         op_mod[0x10];
5365
5366         u8         sq_state[0x4];
5367         u8         reserved_at_44[0x4];
5368         u8         sqn[0x18];
5369
5370         u8         reserved_at_60[0x20];
5371
5372         u8         modify_bitmask[0x40];
5373
5374         u8         reserved_at_c0[0x40];
5375
5376         struct mlx5_ifc_sqc_bits ctx;
5377 };
5378
5379 struct mlx5_ifc_modify_scheduling_element_out_bits {
5380         u8         status[0x8];
5381         u8         reserved_at_8[0x18];
5382
5383         u8         syndrome[0x20];
5384
5385         u8         reserved_at_40[0x1c0];
5386 };
5387
5388 enum {
5389         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5390         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5391 };
5392
5393 struct mlx5_ifc_modify_scheduling_element_in_bits {
5394         u8         opcode[0x10];
5395         u8         reserved_at_10[0x10];
5396
5397         u8         reserved_at_20[0x10];
5398         u8         op_mod[0x10];
5399
5400         u8         scheduling_hierarchy[0x8];
5401         u8         reserved_at_48[0x18];
5402
5403         u8         scheduling_element_id[0x20];
5404
5405         u8         reserved_at_80[0x20];
5406
5407         u8         modify_bitmask[0x20];
5408
5409         u8         reserved_at_c0[0x40];
5410
5411         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5412
5413         u8         reserved_at_300[0x100];
5414 };
5415
5416 struct mlx5_ifc_modify_rqt_out_bits {
5417         u8         status[0x8];
5418         u8         reserved_at_8[0x18];
5419
5420         u8         syndrome[0x20];
5421
5422         u8         reserved_at_40[0x40];
5423 };
5424
5425 struct mlx5_ifc_rqt_bitmask_bits {
5426         u8         reserved_at_0[0x20];
5427
5428         u8         reserved_at_20[0x1f];
5429         u8         rqn_list[0x1];
5430 };
5431
5432 struct mlx5_ifc_modify_rqt_in_bits {
5433         u8         opcode[0x10];
5434         u8         reserved_at_10[0x10];
5435
5436         u8         reserved_at_20[0x10];
5437         u8         op_mod[0x10];
5438
5439         u8         reserved_at_40[0x8];
5440         u8         rqtn[0x18];
5441
5442         u8         reserved_at_60[0x20];
5443
5444         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5445
5446         u8         reserved_at_c0[0x40];
5447
5448         struct mlx5_ifc_rqtc_bits ctx;
5449 };
5450
5451 struct mlx5_ifc_modify_rq_out_bits {
5452         u8         status[0x8];
5453         u8         reserved_at_8[0x18];
5454
5455         u8         syndrome[0x20];
5456
5457         u8         reserved_at_40[0x40];
5458 };
5459
5460 enum {
5461         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5462         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5463         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5464 };
5465
5466 struct mlx5_ifc_modify_rq_in_bits {
5467         u8         opcode[0x10];
5468         u8         reserved_at_10[0x10];
5469
5470         u8         reserved_at_20[0x10];
5471         u8         op_mod[0x10];
5472
5473         u8         rq_state[0x4];
5474         u8         reserved_at_44[0x4];
5475         u8         rqn[0x18];
5476
5477         u8         reserved_at_60[0x20];
5478
5479         u8         modify_bitmask[0x40];
5480
5481         u8         reserved_at_c0[0x40];
5482
5483         struct mlx5_ifc_rqc_bits ctx;
5484 };
5485
5486 struct mlx5_ifc_modify_rmp_out_bits {
5487         u8         status[0x8];
5488         u8         reserved_at_8[0x18];
5489
5490         u8         syndrome[0x20];
5491
5492         u8         reserved_at_40[0x40];
5493 };
5494
5495 struct mlx5_ifc_rmp_bitmask_bits {
5496         u8         reserved_at_0[0x20];
5497
5498         u8         reserved_at_20[0x1f];
5499         u8         lwm[0x1];
5500 };
5501
5502 struct mlx5_ifc_modify_rmp_in_bits {
5503         u8         opcode[0x10];
5504         u8         reserved_at_10[0x10];
5505
5506         u8         reserved_at_20[0x10];
5507         u8         op_mod[0x10];
5508
5509         u8         rmp_state[0x4];
5510         u8         reserved_at_44[0x4];
5511         u8         rmpn[0x18];
5512
5513         u8         reserved_at_60[0x20];
5514
5515         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5516
5517         u8         reserved_at_c0[0x40];
5518
5519         struct mlx5_ifc_rmpc_bits ctx;
5520 };
5521
5522 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5523         u8         status[0x8];
5524         u8         reserved_at_8[0x18];
5525
5526         u8         syndrome[0x20];
5527
5528         u8         reserved_at_40[0x40];
5529 };
5530
5531 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5532         u8         reserved_at_0[0x12];
5533         u8         affiliation[0x1];
5534         u8         reserved_at_e[0x1];
5535         u8         disable_uc_local_lb[0x1];
5536         u8         disable_mc_local_lb[0x1];
5537         u8         node_guid[0x1];
5538         u8         port_guid[0x1];
5539         u8         min_inline[0x1];
5540         u8         mtu[0x1];
5541         u8         change_event[0x1];
5542         u8         promisc[0x1];
5543         u8         permanent_address[0x1];
5544         u8         addresses_list[0x1];
5545         u8         roce_en[0x1];
5546         u8         reserved_at_1f[0x1];
5547 };
5548
5549 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5550         u8         opcode[0x10];
5551         u8         reserved_at_10[0x10];
5552
5553         u8         reserved_at_20[0x10];
5554         u8         op_mod[0x10];
5555
5556         u8         other_vport[0x1];
5557         u8         reserved_at_41[0xf];
5558         u8         vport_number[0x10];
5559
5560         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5561
5562         u8         reserved_at_80[0x780];
5563
5564         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5565 };
5566
5567 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5568         u8         status[0x8];
5569         u8         reserved_at_8[0x18];
5570
5571         u8         syndrome[0x20];
5572
5573         u8         reserved_at_40[0x40];
5574 };
5575
5576 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5577         u8         opcode[0x10];
5578         u8         reserved_at_10[0x10];
5579
5580         u8         reserved_at_20[0x10];
5581         u8         op_mod[0x10];
5582
5583         u8         other_vport[0x1];
5584         u8         reserved_at_41[0xb];
5585         u8         port_num[0x4];
5586         u8         vport_number[0x10];
5587
5588         u8         reserved_at_60[0x20];
5589
5590         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5591 };
5592
5593 struct mlx5_ifc_modify_cq_out_bits {
5594         u8         status[0x8];
5595         u8         reserved_at_8[0x18];
5596
5597         u8         syndrome[0x20];
5598
5599         u8         reserved_at_40[0x40];
5600 };
5601
5602 enum {
5603         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5604         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5605 };
5606
5607 struct mlx5_ifc_modify_cq_in_bits {
5608         u8         opcode[0x10];
5609         u8         reserved_at_10[0x10];
5610
5611         u8         reserved_at_20[0x10];
5612         u8         op_mod[0x10];
5613
5614         u8         reserved_at_40[0x8];
5615         u8         cqn[0x18];
5616
5617         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5618
5619         struct mlx5_ifc_cqc_bits cq_context;
5620
5621         u8         reserved_at_280[0x600];
5622
5623         u8         pas[0][0x40];
5624 };
5625
5626 struct mlx5_ifc_modify_cong_status_out_bits {
5627         u8         status[0x8];
5628         u8         reserved_at_8[0x18];
5629
5630         u8         syndrome[0x20];
5631
5632         u8         reserved_at_40[0x40];
5633 };
5634
5635 struct mlx5_ifc_modify_cong_status_in_bits {
5636         u8         opcode[0x10];
5637         u8         reserved_at_10[0x10];
5638
5639         u8         reserved_at_20[0x10];
5640         u8         op_mod[0x10];
5641
5642         u8         reserved_at_40[0x18];
5643         u8         priority[0x4];
5644         u8         cong_protocol[0x4];
5645
5646         u8         enable[0x1];
5647         u8         tag_enable[0x1];
5648         u8         reserved_at_62[0x1e];
5649 };
5650
5651 struct mlx5_ifc_modify_cong_params_out_bits {
5652         u8         status[0x8];
5653         u8         reserved_at_8[0x18];
5654
5655         u8         syndrome[0x20];
5656
5657         u8         reserved_at_40[0x40];
5658 };
5659
5660 struct mlx5_ifc_modify_cong_params_in_bits {
5661         u8         opcode[0x10];
5662         u8         reserved_at_10[0x10];
5663
5664         u8         reserved_at_20[0x10];
5665         u8         op_mod[0x10];
5666
5667         u8         reserved_at_40[0x1c];
5668         u8         cong_protocol[0x4];
5669
5670         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5671
5672         u8         reserved_at_80[0x80];
5673
5674         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5675 };
5676
5677 struct mlx5_ifc_manage_pages_out_bits {
5678         u8         status[0x8];
5679         u8         reserved_at_8[0x18];
5680
5681         u8         syndrome[0x20];
5682
5683         u8         output_num_entries[0x20];
5684
5685         u8         reserved_at_60[0x20];
5686
5687         u8         pas[0][0x40];
5688 };
5689
5690 enum {
5691         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5692         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5693         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5694 };
5695
5696 struct mlx5_ifc_manage_pages_in_bits {
5697         u8         opcode[0x10];
5698         u8         reserved_at_10[0x10];
5699
5700         u8         reserved_at_20[0x10];
5701         u8         op_mod[0x10];
5702
5703         u8         reserved_at_40[0x10];
5704         u8         function_id[0x10];
5705
5706         u8         input_num_entries[0x20];
5707
5708         u8         pas[0][0x40];
5709 };
5710
5711 struct mlx5_ifc_mad_ifc_out_bits {
5712         u8         status[0x8];
5713         u8         reserved_at_8[0x18];
5714
5715         u8         syndrome[0x20];
5716
5717         u8         reserved_at_40[0x40];
5718
5719         u8         response_mad_packet[256][0x8];
5720 };
5721
5722 struct mlx5_ifc_mad_ifc_in_bits {
5723         u8         opcode[0x10];
5724         u8         reserved_at_10[0x10];
5725
5726         u8         reserved_at_20[0x10];
5727         u8         op_mod[0x10];
5728
5729         u8         remote_lid[0x10];
5730         u8         reserved_at_50[0x8];
5731         u8         port[0x8];
5732
5733         u8         reserved_at_60[0x20];
5734
5735         u8         mad[256][0x8];
5736 };
5737
5738 struct mlx5_ifc_init_hca_out_bits {
5739         u8         status[0x8];
5740         u8         reserved_at_8[0x18];
5741
5742         u8         syndrome[0x20];
5743
5744         u8         reserved_at_40[0x40];
5745 };
5746
5747 struct mlx5_ifc_init_hca_in_bits {
5748         u8         opcode[0x10];
5749         u8         reserved_at_10[0x10];
5750
5751         u8         reserved_at_20[0x10];
5752         u8         op_mod[0x10];
5753
5754         u8         reserved_at_40[0x40];
5755         u8         sw_owner_id[4][0x20];
5756 };
5757
5758 struct mlx5_ifc_init2rtr_qp_out_bits {
5759         u8         status[0x8];
5760         u8         reserved_at_8[0x18];
5761
5762         u8         syndrome[0x20];
5763
5764         u8         reserved_at_40[0x40];
5765 };
5766
5767 struct mlx5_ifc_init2rtr_qp_in_bits {
5768         u8         opcode[0x10];
5769         u8         reserved_at_10[0x10];
5770
5771         u8         reserved_at_20[0x10];
5772         u8         op_mod[0x10];
5773
5774         u8         reserved_at_40[0x8];
5775         u8         qpn[0x18];
5776
5777         u8         reserved_at_60[0x20];
5778
5779         u8         opt_param_mask[0x20];
5780
5781         u8         reserved_at_a0[0x20];
5782
5783         struct mlx5_ifc_qpc_bits qpc;
5784
5785         u8         reserved_at_800[0x80];
5786 };
5787
5788 struct mlx5_ifc_init2init_qp_out_bits {
5789         u8         status[0x8];
5790         u8         reserved_at_8[0x18];
5791
5792         u8         syndrome[0x20];
5793
5794         u8         reserved_at_40[0x40];
5795 };
5796
5797 struct mlx5_ifc_init2init_qp_in_bits {
5798         u8         opcode[0x10];
5799         u8         reserved_at_10[0x10];
5800
5801         u8         reserved_at_20[0x10];
5802         u8         op_mod[0x10];
5803
5804         u8         reserved_at_40[0x8];
5805         u8         qpn[0x18];
5806
5807         u8         reserved_at_60[0x20];
5808
5809         u8         opt_param_mask[0x20];
5810
5811         u8         reserved_at_a0[0x20];
5812
5813         struct mlx5_ifc_qpc_bits qpc;
5814
5815         u8         reserved_at_800[0x80];
5816 };
5817
5818 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5819         u8         status[0x8];
5820         u8         reserved_at_8[0x18];
5821
5822         u8         syndrome[0x20];
5823
5824         u8         reserved_at_40[0x40];
5825
5826         u8         packet_headers_log[128][0x8];
5827
5828         u8         packet_syndrome[64][0x8];
5829 };
5830
5831 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5832         u8         opcode[0x10];
5833         u8         reserved_at_10[0x10];
5834
5835         u8         reserved_at_20[0x10];
5836         u8         op_mod[0x10];
5837
5838         u8         reserved_at_40[0x40];
5839 };
5840
5841 struct mlx5_ifc_gen_eqe_in_bits {
5842         u8         opcode[0x10];
5843         u8         reserved_at_10[0x10];
5844
5845         u8         reserved_at_20[0x10];
5846         u8         op_mod[0x10];
5847
5848         u8         reserved_at_40[0x18];
5849         u8         eq_number[0x8];
5850
5851         u8         reserved_at_60[0x20];
5852
5853         u8         eqe[64][0x8];
5854 };
5855
5856 struct mlx5_ifc_gen_eq_out_bits {
5857         u8         status[0x8];
5858         u8         reserved_at_8[0x18];
5859
5860         u8         syndrome[0x20];
5861
5862         u8         reserved_at_40[0x40];
5863 };
5864
5865 struct mlx5_ifc_enable_hca_out_bits {
5866         u8         status[0x8];
5867         u8         reserved_at_8[0x18];
5868
5869         u8         syndrome[0x20];
5870
5871         u8         reserved_at_40[0x20];
5872 };
5873
5874 struct mlx5_ifc_enable_hca_in_bits {
5875         u8         opcode[0x10];
5876         u8         reserved_at_10[0x10];
5877
5878         u8         reserved_at_20[0x10];
5879         u8         op_mod[0x10];
5880
5881         u8         reserved_at_40[0x10];
5882         u8         function_id[0x10];
5883
5884         u8         reserved_at_60[0x20];
5885 };
5886
5887 struct mlx5_ifc_drain_dct_out_bits {
5888         u8         status[0x8];
5889         u8         reserved_at_8[0x18];
5890
5891         u8         syndrome[0x20];
5892
5893         u8         reserved_at_40[0x40];
5894 };
5895
5896 struct mlx5_ifc_drain_dct_in_bits {
5897         u8         opcode[0x10];
5898         u8         reserved_at_10[0x10];
5899
5900         u8         reserved_at_20[0x10];
5901         u8         op_mod[0x10];
5902
5903         u8         reserved_at_40[0x8];
5904         u8         dctn[0x18];
5905
5906         u8         reserved_at_60[0x20];
5907 };
5908
5909 struct mlx5_ifc_disable_hca_out_bits {
5910         u8         status[0x8];
5911         u8         reserved_at_8[0x18];
5912
5913         u8         syndrome[0x20];
5914
5915         u8         reserved_at_40[0x20];
5916 };
5917
5918 struct mlx5_ifc_disable_hca_in_bits {
5919         u8         opcode[0x10];
5920         u8         reserved_at_10[0x10];
5921
5922         u8         reserved_at_20[0x10];
5923         u8         op_mod[0x10];
5924
5925         u8         reserved_at_40[0x10];
5926         u8         function_id[0x10];
5927
5928         u8         reserved_at_60[0x20];
5929 };
5930
5931 struct mlx5_ifc_detach_from_mcg_out_bits {
5932         u8         status[0x8];
5933         u8         reserved_at_8[0x18];
5934
5935         u8         syndrome[0x20];
5936
5937         u8         reserved_at_40[0x40];
5938 };
5939
5940 struct mlx5_ifc_detach_from_mcg_in_bits {
5941         u8         opcode[0x10];
5942         u8         reserved_at_10[0x10];
5943
5944         u8         reserved_at_20[0x10];
5945         u8         op_mod[0x10];
5946
5947         u8         reserved_at_40[0x8];
5948         u8         qpn[0x18];
5949
5950         u8         reserved_at_60[0x20];
5951
5952         u8         multicast_gid[16][0x8];
5953 };
5954
5955 struct mlx5_ifc_destroy_xrq_out_bits {
5956         u8         status[0x8];
5957         u8         reserved_at_8[0x18];
5958
5959         u8         syndrome[0x20];
5960
5961         u8         reserved_at_40[0x40];
5962 };
5963
5964 struct mlx5_ifc_destroy_xrq_in_bits {
5965         u8         opcode[0x10];
5966         u8         reserved_at_10[0x10];
5967
5968         u8         reserved_at_20[0x10];
5969         u8         op_mod[0x10];
5970
5971         u8         reserved_at_40[0x8];
5972         u8         xrqn[0x18];
5973
5974         u8         reserved_at_60[0x20];
5975 };
5976
5977 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5978         u8         status[0x8];
5979         u8         reserved_at_8[0x18];
5980
5981         u8         syndrome[0x20];
5982
5983         u8         reserved_at_40[0x40];
5984 };
5985
5986 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5987         u8         opcode[0x10];
5988         u8         reserved_at_10[0x10];
5989
5990         u8         reserved_at_20[0x10];
5991         u8         op_mod[0x10];
5992
5993         u8         reserved_at_40[0x8];
5994         u8         xrc_srqn[0x18];
5995
5996         u8         reserved_at_60[0x20];
5997 };
5998
5999 struct mlx5_ifc_destroy_tis_out_bits {
6000         u8         status[0x8];
6001         u8         reserved_at_8[0x18];
6002
6003         u8         syndrome[0x20];
6004
6005         u8         reserved_at_40[0x40];
6006 };
6007
6008 struct mlx5_ifc_destroy_tis_in_bits {
6009         u8         opcode[0x10];
6010         u8         reserved_at_10[0x10];
6011
6012         u8         reserved_at_20[0x10];
6013         u8         op_mod[0x10];
6014
6015         u8         reserved_at_40[0x8];
6016         u8         tisn[0x18];
6017
6018         u8         reserved_at_60[0x20];
6019 };
6020
6021 struct mlx5_ifc_destroy_tir_out_bits {
6022         u8         status[0x8];
6023         u8         reserved_at_8[0x18];
6024
6025         u8         syndrome[0x20];
6026
6027         u8         reserved_at_40[0x40];
6028 };
6029
6030 struct mlx5_ifc_destroy_tir_in_bits {
6031         u8         opcode[0x10];
6032         u8         reserved_at_10[0x10];
6033
6034         u8         reserved_at_20[0x10];
6035         u8         op_mod[0x10];
6036
6037         u8         reserved_at_40[0x8];
6038         u8         tirn[0x18];
6039
6040         u8         reserved_at_60[0x20];
6041 };
6042
6043 struct mlx5_ifc_destroy_srq_out_bits {
6044         u8         status[0x8];
6045         u8         reserved_at_8[0x18];
6046
6047         u8         syndrome[0x20];
6048
6049         u8         reserved_at_40[0x40];
6050 };
6051
6052 struct mlx5_ifc_destroy_srq_in_bits {
6053         u8         opcode[0x10];
6054         u8         reserved_at_10[0x10];
6055
6056         u8         reserved_at_20[0x10];
6057         u8         op_mod[0x10];
6058
6059         u8         reserved_at_40[0x8];
6060         u8         srqn[0x18];
6061
6062         u8         reserved_at_60[0x20];
6063 };
6064
6065 struct mlx5_ifc_destroy_sq_out_bits {
6066         u8         status[0x8];
6067         u8         reserved_at_8[0x18];
6068
6069         u8         syndrome[0x20];
6070
6071         u8         reserved_at_40[0x40];
6072 };
6073
6074 struct mlx5_ifc_destroy_sq_in_bits {
6075         u8         opcode[0x10];
6076         u8         reserved_at_10[0x10];
6077
6078         u8         reserved_at_20[0x10];
6079         u8         op_mod[0x10];
6080
6081         u8         reserved_at_40[0x8];
6082         u8         sqn[0x18];
6083
6084         u8         reserved_at_60[0x20];
6085 };
6086
6087 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6088         u8         status[0x8];
6089         u8         reserved_at_8[0x18];
6090
6091         u8         syndrome[0x20];
6092
6093         u8         reserved_at_40[0x1c0];
6094 };
6095
6096 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6097         u8         opcode[0x10];
6098         u8         reserved_at_10[0x10];
6099
6100         u8         reserved_at_20[0x10];
6101         u8         op_mod[0x10];
6102
6103         u8         scheduling_hierarchy[0x8];
6104         u8         reserved_at_48[0x18];
6105
6106         u8         scheduling_element_id[0x20];
6107
6108         u8         reserved_at_80[0x180];
6109 };
6110
6111 struct mlx5_ifc_destroy_rqt_out_bits {
6112         u8         status[0x8];
6113         u8         reserved_at_8[0x18];
6114
6115         u8         syndrome[0x20];
6116
6117         u8         reserved_at_40[0x40];
6118 };
6119
6120 struct mlx5_ifc_destroy_rqt_in_bits {
6121         u8         opcode[0x10];
6122         u8         reserved_at_10[0x10];
6123
6124         u8         reserved_at_20[0x10];
6125         u8         op_mod[0x10];
6126
6127         u8         reserved_at_40[0x8];
6128         u8         rqtn[0x18];
6129
6130         u8         reserved_at_60[0x20];
6131 };
6132
6133 struct mlx5_ifc_destroy_rq_out_bits {
6134         u8         status[0x8];
6135         u8         reserved_at_8[0x18];
6136
6137         u8         syndrome[0x20];
6138
6139         u8         reserved_at_40[0x40];
6140 };
6141
6142 struct mlx5_ifc_destroy_rq_in_bits {
6143         u8         opcode[0x10];
6144         u8         reserved_at_10[0x10];
6145
6146         u8         reserved_at_20[0x10];
6147         u8         op_mod[0x10];
6148
6149         u8         reserved_at_40[0x8];
6150         u8         rqn[0x18];
6151
6152         u8         reserved_at_60[0x20];
6153 };
6154
6155 struct mlx5_ifc_set_delay_drop_params_in_bits {
6156         u8         opcode[0x10];
6157         u8         reserved_at_10[0x10];
6158
6159         u8         reserved_at_20[0x10];
6160         u8         op_mod[0x10];
6161
6162         u8         reserved_at_40[0x20];
6163
6164         u8         reserved_at_60[0x10];
6165         u8         delay_drop_timeout[0x10];
6166 };
6167
6168 struct mlx5_ifc_set_delay_drop_params_out_bits {
6169         u8         status[0x8];
6170         u8         reserved_at_8[0x18];
6171
6172         u8         syndrome[0x20];
6173
6174         u8         reserved_at_40[0x40];
6175 };
6176
6177 struct mlx5_ifc_destroy_rmp_out_bits {
6178         u8         status[0x8];
6179         u8         reserved_at_8[0x18];
6180
6181         u8         syndrome[0x20];
6182
6183         u8         reserved_at_40[0x40];
6184 };
6185
6186 struct mlx5_ifc_destroy_rmp_in_bits {
6187         u8         opcode[0x10];
6188         u8         reserved_at_10[0x10];
6189
6190         u8         reserved_at_20[0x10];
6191         u8         op_mod[0x10];
6192
6193         u8         reserved_at_40[0x8];
6194         u8         rmpn[0x18];
6195
6196         u8         reserved_at_60[0x20];
6197 };
6198
6199 struct mlx5_ifc_destroy_qp_out_bits {
6200         u8         status[0x8];
6201         u8         reserved_at_8[0x18];
6202
6203         u8         syndrome[0x20];
6204
6205         u8         reserved_at_40[0x40];
6206 };
6207
6208 struct mlx5_ifc_destroy_qp_in_bits {
6209         u8         opcode[0x10];
6210         u8         reserved_at_10[0x10];
6211
6212         u8         reserved_at_20[0x10];
6213         u8         op_mod[0x10];
6214
6215         u8         reserved_at_40[0x8];
6216         u8         qpn[0x18];
6217
6218         u8         reserved_at_60[0x20];
6219 };
6220
6221 struct mlx5_ifc_destroy_psv_out_bits {
6222         u8         status[0x8];
6223         u8         reserved_at_8[0x18];
6224
6225         u8         syndrome[0x20];
6226
6227         u8         reserved_at_40[0x40];
6228 };
6229
6230 struct mlx5_ifc_destroy_psv_in_bits {
6231         u8         opcode[0x10];
6232         u8         reserved_at_10[0x10];
6233
6234         u8         reserved_at_20[0x10];
6235         u8         op_mod[0x10];
6236
6237         u8         reserved_at_40[0x8];
6238         u8         psvn[0x18];
6239
6240         u8         reserved_at_60[0x20];
6241 };
6242
6243 struct mlx5_ifc_destroy_mkey_out_bits {
6244         u8         status[0x8];
6245         u8         reserved_at_8[0x18];
6246
6247         u8         syndrome[0x20];
6248
6249         u8         reserved_at_40[0x40];
6250 };
6251
6252 struct mlx5_ifc_destroy_mkey_in_bits {
6253         u8         opcode[0x10];
6254         u8         reserved_at_10[0x10];
6255
6256         u8         reserved_at_20[0x10];
6257         u8         op_mod[0x10];
6258
6259         u8         reserved_at_40[0x8];
6260         u8         mkey_index[0x18];
6261
6262         u8         reserved_at_60[0x20];
6263 };
6264
6265 struct mlx5_ifc_destroy_flow_table_out_bits {
6266         u8         status[0x8];
6267         u8         reserved_at_8[0x18];
6268
6269         u8         syndrome[0x20];
6270
6271         u8         reserved_at_40[0x40];
6272 };
6273
6274 struct mlx5_ifc_destroy_flow_table_in_bits {
6275         u8         opcode[0x10];
6276         u8         reserved_at_10[0x10];
6277
6278         u8         reserved_at_20[0x10];
6279         u8         op_mod[0x10];
6280
6281         u8         other_vport[0x1];
6282         u8         reserved_at_41[0xf];
6283         u8         vport_number[0x10];
6284
6285         u8         reserved_at_60[0x20];
6286
6287         u8         table_type[0x8];
6288         u8         reserved_at_88[0x18];
6289
6290         u8         reserved_at_a0[0x8];
6291         u8         table_id[0x18];
6292
6293         u8         reserved_at_c0[0x140];
6294 };
6295
6296 struct mlx5_ifc_destroy_flow_group_out_bits {
6297         u8         status[0x8];
6298         u8         reserved_at_8[0x18];
6299
6300         u8         syndrome[0x20];
6301
6302         u8         reserved_at_40[0x40];
6303 };
6304
6305 struct mlx5_ifc_destroy_flow_group_in_bits {
6306         u8         opcode[0x10];
6307         u8         reserved_at_10[0x10];
6308
6309         u8         reserved_at_20[0x10];
6310         u8         op_mod[0x10];
6311
6312         u8         other_vport[0x1];
6313         u8         reserved_at_41[0xf];
6314         u8         vport_number[0x10];
6315
6316         u8         reserved_at_60[0x20];
6317
6318         u8         table_type[0x8];
6319         u8         reserved_at_88[0x18];
6320
6321         u8         reserved_at_a0[0x8];
6322         u8         table_id[0x18];
6323
6324         u8         group_id[0x20];
6325
6326         u8         reserved_at_e0[0x120];
6327 };
6328
6329 struct mlx5_ifc_destroy_eq_out_bits {
6330         u8         status[0x8];
6331         u8         reserved_at_8[0x18];
6332
6333         u8         syndrome[0x20];
6334
6335         u8         reserved_at_40[0x40];
6336 };
6337
6338 struct mlx5_ifc_destroy_eq_in_bits {
6339         u8         opcode[0x10];
6340         u8         reserved_at_10[0x10];
6341
6342         u8         reserved_at_20[0x10];
6343         u8         op_mod[0x10];
6344
6345         u8         reserved_at_40[0x18];
6346         u8         eq_number[0x8];
6347
6348         u8         reserved_at_60[0x20];
6349 };
6350
6351 struct mlx5_ifc_destroy_dct_out_bits {
6352         u8         status[0x8];
6353         u8         reserved_at_8[0x18];
6354
6355         u8         syndrome[0x20];
6356
6357         u8         reserved_at_40[0x40];
6358 };
6359
6360 struct mlx5_ifc_destroy_dct_in_bits {
6361         u8         opcode[0x10];
6362         u8         reserved_at_10[0x10];
6363
6364         u8         reserved_at_20[0x10];
6365         u8         op_mod[0x10];
6366
6367         u8         reserved_at_40[0x8];
6368         u8         dctn[0x18];
6369
6370         u8         reserved_at_60[0x20];
6371 };
6372
6373 struct mlx5_ifc_destroy_cq_out_bits {
6374         u8         status[0x8];
6375         u8         reserved_at_8[0x18];
6376
6377         u8         syndrome[0x20];
6378
6379         u8         reserved_at_40[0x40];
6380 };
6381
6382 struct mlx5_ifc_destroy_cq_in_bits {
6383         u8         opcode[0x10];
6384         u8         reserved_at_10[0x10];
6385
6386         u8         reserved_at_20[0x10];
6387         u8         op_mod[0x10];
6388
6389         u8         reserved_at_40[0x8];
6390         u8         cqn[0x18];
6391
6392         u8         reserved_at_60[0x20];
6393 };
6394
6395 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6396         u8         status[0x8];
6397         u8         reserved_at_8[0x18];
6398
6399         u8         syndrome[0x20];
6400
6401         u8         reserved_at_40[0x40];
6402 };
6403
6404 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6405         u8         opcode[0x10];
6406         u8         reserved_at_10[0x10];
6407
6408         u8         reserved_at_20[0x10];
6409         u8         op_mod[0x10];
6410
6411         u8         reserved_at_40[0x20];
6412
6413         u8         reserved_at_60[0x10];
6414         u8         vxlan_udp_port[0x10];
6415 };
6416
6417 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6418         u8         status[0x8];
6419         u8         reserved_at_8[0x18];
6420
6421         u8         syndrome[0x20];
6422
6423         u8         reserved_at_40[0x40];
6424 };
6425
6426 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6427         u8         opcode[0x10];
6428         u8         reserved_at_10[0x10];
6429
6430         u8         reserved_at_20[0x10];
6431         u8         op_mod[0x10];
6432
6433         u8         reserved_at_40[0x60];
6434
6435         u8         reserved_at_a0[0x8];
6436         u8         table_index[0x18];
6437
6438         u8         reserved_at_c0[0x140];
6439 };
6440
6441 struct mlx5_ifc_delete_fte_out_bits {
6442         u8         status[0x8];
6443         u8         reserved_at_8[0x18];
6444
6445         u8         syndrome[0x20];
6446
6447         u8         reserved_at_40[0x40];
6448 };
6449
6450 struct mlx5_ifc_delete_fte_in_bits {
6451         u8         opcode[0x10];
6452         u8         reserved_at_10[0x10];
6453
6454         u8         reserved_at_20[0x10];
6455         u8         op_mod[0x10];
6456
6457         u8         other_vport[0x1];
6458         u8         reserved_at_41[0xf];
6459         u8         vport_number[0x10];
6460
6461         u8         reserved_at_60[0x20];
6462
6463         u8         table_type[0x8];
6464         u8         reserved_at_88[0x18];
6465
6466         u8         reserved_at_a0[0x8];
6467         u8         table_id[0x18];
6468
6469         u8         reserved_at_c0[0x40];
6470
6471         u8         flow_index[0x20];
6472
6473         u8         reserved_at_120[0xe0];
6474 };
6475
6476 struct mlx5_ifc_dealloc_xrcd_out_bits {
6477         u8         status[0x8];
6478         u8         reserved_at_8[0x18];
6479
6480         u8         syndrome[0x20];
6481
6482         u8         reserved_at_40[0x40];
6483 };
6484
6485 struct mlx5_ifc_dealloc_xrcd_in_bits {
6486         u8         opcode[0x10];
6487         u8         reserved_at_10[0x10];
6488
6489         u8         reserved_at_20[0x10];
6490         u8         op_mod[0x10];
6491
6492         u8         reserved_at_40[0x8];
6493         u8         xrcd[0x18];
6494
6495         u8         reserved_at_60[0x20];
6496 };
6497
6498 struct mlx5_ifc_dealloc_uar_out_bits {
6499         u8         status[0x8];
6500         u8         reserved_at_8[0x18];
6501
6502         u8         syndrome[0x20];
6503
6504         u8         reserved_at_40[0x40];
6505 };
6506
6507 struct mlx5_ifc_dealloc_uar_in_bits {
6508         u8         opcode[0x10];
6509         u8         reserved_at_10[0x10];
6510
6511         u8         reserved_at_20[0x10];
6512         u8         op_mod[0x10];
6513
6514         u8         reserved_at_40[0x8];
6515         u8         uar[0x18];
6516
6517         u8         reserved_at_60[0x20];
6518 };
6519
6520 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6521         u8         status[0x8];
6522         u8         reserved_at_8[0x18];
6523
6524         u8         syndrome[0x20];
6525
6526         u8         reserved_at_40[0x40];
6527 };
6528
6529 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6530         u8         opcode[0x10];
6531         u8         reserved_at_10[0x10];
6532
6533         u8         reserved_at_20[0x10];
6534         u8         op_mod[0x10];
6535
6536         u8         reserved_at_40[0x8];
6537         u8         transport_domain[0x18];
6538
6539         u8         reserved_at_60[0x20];
6540 };
6541
6542 struct mlx5_ifc_dealloc_q_counter_out_bits {
6543         u8         status[0x8];
6544         u8         reserved_at_8[0x18];
6545
6546         u8         syndrome[0x20];
6547
6548         u8         reserved_at_40[0x40];
6549 };
6550
6551 struct mlx5_ifc_dealloc_q_counter_in_bits {
6552         u8         opcode[0x10];
6553         u8         reserved_at_10[0x10];
6554
6555         u8         reserved_at_20[0x10];
6556         u8         op_mod[0x10];
6557
6558         u8         reserved_at_40[0x18];
6559         u8         counter_set_id[0x8];
6560
6561         u8         reserved_at_60[0x20];
6562 };
6563
6564 struct mlx5_ifc_dealloc_pd_out_bits {
6565         u8         status[0x8];
6566         u8         reserved_at_8[0x18];
6567
6568         u8         syndrome[0x20];
6569
6570         u8         reserved_at_40[0x40];
6571 };
6572
6573 struct mlx5_ifc_dealloc_pd_in_bits {
6574         u8         opcode[0x10];
6575         u8         reserved_at_10[0x10];
6576
6577         u8         reserved_at_20[0x10];
6578         u8         op_mod[0x10];
6579
6580         u8         reserved_at_40[0x8];
6581         u8         pd[0x18];
6582
6583         u8         reserved_at_60[0x20];
6584 };
6585
6586 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6587         u8         status[0x8];
6588         u8         reserved_at_8[0x18];
6589
6590         u8         syndrome[0x20];
6591
6592         u8         reserved_at_40[0x40];
6593 };
6594
6595 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6596         u8         opcode[0x10];
6597         u8         reserved_at_10[0x10];
6598
6599         u8         reserved_at_20[0x10];
6600         u8         op_mod[0x10];
6601
6602         u8         flow_counter_id[0x20];
6603
6604         u8         reserved_at_60[0x20];
6605 };
6606
6607 struct mlx5_ifc_create_xrq_out_bits {
6608         u8         status[0x8];
6609         u8         reserved_at_8[0x18];
6610
6611         u8         syndrome[0x20];
6612
6613         u8         reserved_at_40[0x8];
6614         u8         xrqn[0x18];
6615
6616         u8         reserved_at_60[0x20];
6617 };
6618
6619 struct mlx5_ifc_create_xrq_in_bits {
6620         u8         opcode[0x10];
6621         u8         reserved_at_10[0x10];
6622
6623         u8         reserved_at_20[0x10];
6624         u8         op_mod[0x10];
6625
6626         u8         reserved_at_40[0x40];
6627
6628         struct mlx5_ifc_xrqc_bits xrq_context;
6629 };
6630
6631 struct mlx5_ifc_create_xrc_srq_out_bits {
6632         u8         status[0x8];
6633         u8         reserved_at_8[0x18];
6634
6635         u8         syndrome[0x20];
6636
6637         u8         reserved_at_40[0x8];
6638         u8         xrc_srqn[0x18];
6639
6640         u8         reserved_at_60[0x20];
6641 };
6642
6643 struct mlx5_ifc_create_xrc_srq_in_bits {
6644         u8         opcode[0x10];
6645         u8         reserved_at_10[0x10];
6646
6647         u8         reserved_at_20[0x10];
6648         u8         op_mod[0x10];
6649
6650         u8         reserved_at_40[0x40];
6651
6652         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6653
6654         u8         reserved_at_280[0x600];
6655
6656         u8         pas[0][0x40];
6657 };
6658
6659 struct mlx5_ifc_create_tis_out_bits {
6660         u8         status[0x8];
6661         u8         reserved_at_8[0x18];
6662
6663         u8         syndrome[0x20];
6664
6665         u8         reserved_at_40[0x8];
6666         u8         tisn[0x18];
6667
6668         u8         reserved_at_60[0x20];
6669 };
6670
6671 struct mlx5_ifc_create_tis_in_bits {
6672         u8         opcode[0x10];
6673         u8         reserved_at_10[0x10];
6674
6675         u8         reserved_at_20[0x10];
6676         u8         op_mod[0x10];
6677
6678         u8         reserved_at_40[0xc0];
6679
6680         struct mlx5_ifc_tisc_bits ctx;
6681 };
6682
6683 struct mlx5_ifc_create_tir_out_bits {
6684         u8         status[0x8];
6685         u8         reserved_at_8[0x18];
6686
6687         u8         syndrome[0x20];
6688
6689         u8         reserved_at_40[0x8];
6690         u8         tirn[0x18];
6691
6692         u8         reserved_at_60[0x20];
6693 };
6694
6695 struct mlx5_ifc_create_tir_in_bits {
6696         u8         opcode[0x10];
6697         u8         reserved_at_10[0x10];
6698
6699         u8         reserved_at_20[0x10];
6700         u8         op_mod[0x10];
6701
6702         u8         reserved_at_40[0xc0];
6703
6704         struct mlx5_ifc_tirc_bits ctx;
6705 };
6706
6707 struct mlx5_ifc_create_srq_out_bits {
6708         u8         status[0x8];
6709         u8         reserved_at_8[0x18];
6710
6711         u8         syndrome[0x20];
6712
6713         u8         reserved_at_40[0x8];
6714         u8         srqn[0x18];
6715
6716         u8         reserved_at_60[0x20];
6717 };
6718
6719 struct mlx5_ifc_create_srq_in_bits {
6720         u8         opcode[0x10];
6721         u8         reserved_at_10[0x10];
6722
6723         u8         reserved_at_20[0x10];
6724         u8         op_mod[0x10];
6725
6726         u8         reserved_at_40[0x40];
6727
6728         struct mlx5_ifc_srqc_bits srq_context_entry;
6729
6730         u8         reserved_at_280[0x600];
6731
6732         u8         pas[0][0x40];
6733 };
6734
6735 struct mlx5_ifc_create_sq_out_bits {
6736         u8         status[0x8];
6737         u8         reserved_at_8[0x18];
6738
6739         u8         syndrome[0x20];
6740
6741         u8         reserved_at_40[0x8];
6742         u8         sqn[0x18];
6743
6744         u8         reserved_at_60[0x20];
6745 };
6746
6747 struct mlx5_ifc_create_sq_in_bits {
6748         u8         opcode[0x10];
6749         u8         reserved_at_10[0x10];
6750
6751         u8         reserved_at_20[0x10];
6752         u8         op_mod[0x10];
6753
6754         u8         reserved_at_40[0xc0];
6755
6756         struct mlx5_ifc_sqc_bits ctx;
6757 };
6758
6759 struct mlx5_ifc_create_scheduling_element_out_bits {
6760         u8         status[0x8];
6761         u8         reserved_at_8[0x18];
6762
6763         u8         syndrome[0x20];
6764
6765         u8         reserved_at_40[0x40];
6766
6767         u8         scheduling_element_id[0x20];
6768
6769         u8         reserved_at_a0[0x160];
6770 };
6771
6772 struct mlx5_ifc_create_scheduling_element_in_bits {
6773         u8         opcode[0x10];
6774         u8         reserved_at_10[0x10];
6775
6776         u8         reserved_at_20[0x10];
6777         u8         op_mod[0x10];
6778
6779         u8         scheduling_hierarchy[0x8];
6780         u8         reserved_at_48[0x18];
6781
6782         u8         reserved_at_60[0xa0];
6783
6784         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6785
6786         u8         reserved_at_300[0x100];
6787 };
6788
6789 struct mlx5_ifc_create_rqt_out_bits {
6790         u8         status[0x8];
6791         u8         reserved_at_8[0x18];
6792
6793         u8         syndrome[0x20];
6794
6795         u8         reserved_at_40[0x8];
6796         u8         rqtn[0x18];
6797
6798         u8         reserved_at_60[0x20];
6799 };
6800
6801 struct mlx5_ifc_create_rqt_in_bits {
6802         u8         opcode[0x10];
6803         u8         reserved_at_10[0x10];
6804
6805         u8         reserved_at_20[0x10];
6806         u8         op_mod[0x10];
6807
6808         u8         reserved_at_40[0xc0];
6809
6810         struct mlx5_ifc_rqtc_bits rqt_context;
6811 };
6812
6813 struct mlx5_ifc_create_rq_out_bits {
6814         u8         status[0x8];
6815         u8         reserved_at_8[0x18];
6816
6817         u8         syndrome[0x20];
6818
6819         u8         reserved_at_40[0x8];
6820         u8         rqn[0x18];
6821
6822         u8         reserved_at_60[0x20];
6823 };
6824
6825 struct mlx5_ifc_create_rq_in_bits {
6826         u8         opcode[0x10];
6827         u8         reserved_at_10[0x10];
6828
6829         u8         reserved_at_20[0x10];
6830         u8         op_mod[0x10];
6831
6832         u8         reserved_at_40[0xc0];
6833
6834         struct mlx5_ifc_rqc_bits ctx;
6835 };
6836
6837 struct mlx5_ifc_create_rmp_out_bits {
6838         u8         status[0x8];
6839         u8         reserved_at_8[0x18];
6840
6841         u8         syndrome[0x20];
6842
6843         u8         reserved_at_40[0x8];
6844         u8         rmpn[0x18];
6845
6846         u8         reserved_at_60[0x20];
6847 };
6848
6849 struct mlx5_ifc_create_rmp_in_bits {
6850         u8         opcode[0x10];
6851         u8         reserved_at_10[0x10];
6852
6853         u8         reserved_at_20[0x10];
6854         u8         op_mod[0x10];
6855
6856         u8         reserved_at_40[0xc0];
6857
6858         struct mlx5_ifc_rmpc_bits ctx;
6859 };
6860
6861 struct mlx5_ifc_create_qp_out_bits {
6862         u8         status[0x8];
6863         u8         reserved_at_8[0x18];
6864
6865         u8         syndrome[0x20];
6866
6867         u8         reserved_at_40[0x8];
6868         u8         qpn[0x18];
6869
6870         u8         reserved_at_60[0x20];
6871 };
6872
6873 struct mlx5_ifc_create_qp_in_bits {
6874         u8         opcode[0x10];
6875         u8         reserved_at_10[0x10];
6876
6877         u8         reserved_at_20[0x10];
6878         u8         op_mod[0x10];
6879
6880         u8         reserved_at_40[0x40];
6881
6882         u8         opt_param_mask[0x20];
6883
6884         u8         reserved_at_a0[0x20];
6885
6886         struct mlx5_ifc_qpc_bits qpc;
6887
6888         u8         reserved_at_800[0x80];
6889
6890         u8         pas[0][0x40];
6891 };
6892
6893 struct mlx5_ifc_create_psv_out_bits {
6894         u8         status[0x8];
6895         u8         reserved_at_8[0x18];
6896
6897         u8         syndrome[0x20];
6898
6899         u8         reserved_at_40[0x40];
6900
6901         u8         reserved_at_80[0x8];
6902         u8         psv0_index[0x18];
6903
6904         u8         reserved_at_a0[0x8];
6905         u8         psv1_index[0x18];
6906
6907         u8         reserved_at_c0[0x8];
6908         u8         psv2_index[0x18];
6909
6910         u8         reserved_at_e0[0x8];
6911         u8         psv3_index[0x18];
6912 };
6913
6914 struct mlx5_ifc_create_psv_in_bits {
6915         u8         opcode[0x10];
6916         u8         reserved_at_10[0x10];
6917
6918         u8         reserved_at_20[0x10];
6919         u8         op_mod[0x10];
6920
6921         u8         num_psv[0x4];
6922         u8         reserved_at_44[0x4];
6923         u8         pd[0x18];
6924
6925         u8         reserved_at_60[0x20];
6926 };
6927
6928 struct mlx5_ifc_create_mkey_out_bits {
6929         u8         status[0x8];
6930         u8         reserved_at_8[0x18];
6931
6932         u8         syndrome[0x20];
6933
6934         u8         reserved_at_40[0x8];
6935         u8         mkey_index[0x18];
6936
6937         u8         reserved_at_60[0x20];
6938 };
6939
6940 struct mlx5_ifc_create_mkey_in_bits {
6941         u8         opcode[0x10];
6942         u8         reserved_at_10[0x10];
6943
6944         u8         reserved_at_20[0x10];
6945         u8         op_mod[0x10];
6946
6947         u8         reserved_at_40[0x20];
6948
6949         u8         pg_access[0x1];
6950         u8         reserved_at_61[0x1f];
6951
6952         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6953
6954         u8         reserved_at_280[0x80];
6955
6956         u8         translations_octword_actual_size[0x20];
6957
6958         u8         reserved_at_320[0x560];
6959
6960         u8         klm_pas_mtt[0][0x20];
6961 };
6962
6963 struct mlx5_ifc_create_flow_table_out_bits {
6964         u8         status[0x8];
6965         u8         reserved_at_8[0x18];
6966
6967         u8         syndrome[0x20];
6968
6969         u8         reserved_at_40[0x8];
6970         u8         table_id[0x18];
6971
6972         u8         reserved_at_60[0x20];
6973 };
6974
6975 struct mlx5_ifc_flow_table_context_bits {
6976         u8         encap_en[0x1];
6977         u8         decap_en[0x1];
6978         u8         reserved_at_2[0x2];
6979         u8         table_miss_action[0x4];
6980         u8         level[0x8];
6981         u8         reserved_at_10[0x8];
6982         u8         log_size[0x8];
6983
6984         u8         reserved_at_20[0x8];
6985         u8         table_miss_id[0x18];
6986
6987         u8         reserved_at_40[0x8];
6988         u8         lag_master_next_table_id[0x18];
6989
6990         u8         reserved_at_60[0xe0];
6991 };
6992
6993 struct mlx5_ifc_create_flow_table_in_bits {
6994         u8         opcode[0x10];
6995         u8         reserved_at_10[0x10];
6996
6997         u8         reserved_at_20[0x10];
6998         u8         op_mod[0x10];
6999
7000         u8         other_vport[0x1];
7001         u8         reserved_at_41[0xf];
7002         u8         vport_number[0x10];
7003
7004         u8         reserved_at_60[0x20];
7005
7006         u8         table_type[0x8];
7007         u8         reserved_at_88[0x18];
7008
7009         u8         reserved_at_a0[0x20];
7010
7011         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7012 };
7013
7014 struct mlx5_ifc_create_flow_group_out_bits {
7015         u8         status[0x8];
7016         u8         reserved_at_8[0x18];
7017
7018         u8         syndrome[0x20];
7019
7020         u8         reserved_at_40[0x8];
7021         u8         group_id[0x18];
7022
7023         u8         reserved_at_60[0x20];
7024 };
7025
7026 enum {
7027         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7028         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7029         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7030         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7031 };
7032
7033 struct mlx5_ifc_create_flow_group_in_bits {
7034         u8         opcode[0x10];
7035         u8         reserved_at_10[0x10];
7036
7037         u8         reserved_at_20[0x10];
7038         u8         op_mod[0x10];
7039
7040         u8         other_vport[0x1];
7041         u8         reserved_at_41[0xf];
7042         u8         vport_number[0x10];
7043
7044         u8         reserved_at_60[0x20];
7045
7046         u8         table_type[0x8];
7047         u8         reserved_at_88[0x18];
7048
7049         u8         reserved_at_a0[0x8];
7050         u8         table_id[0x18];
7051
7052         u8         source_eswitch_owner_vhca_id_valid[0x1];
7053
7054         u8         reserved_at_c1[0x1f];
7055
7056         u8         start_flow_index[0x20];
7057
7058         u8         reserved_at_100[0x20];
7059
7060         u8         end_flow_index[0x20];
7061
7062         u8         reserved_at_140[0xa0];
7063
7064         u8         reserved_at_1e0[0x18];
7065         u8         match_criteria_enable[0x8];
7066
7067         struct mlx5_ifc_fte_match_param_bits match_criteria;
7068
7069         u8         reserved_at_1200[0xe00];
7070 };
7071
7072 struct mlx5_ifc_create_eq_out_bits {
7073         u8         status[0x8];
7074         u8         reserved_at_8[0x18];
7075
7076         u8         syndrome[0x20];
7077
7078         u8         reserved_at_40[0x18];
7079         u8         eq_number[0x8];
7080
7081         u8         reserved_at_60[0x20];
7082 };
7083
7084 struct mlx5_ifc_create_eq_in_bits {
7085         u8         opcode[0x10];
7086         u8         reserved_at_10[0x10];
7087
7088         u8         reserved_at_20[0x10];
7089         u8         op_mod[0x10];
7090
7091         u8         reserved_at_40[0x40];
7092
7093         struct mlx5_ifc_eqc_bits eq_context_entry;
7094
7095         u8         reserved_at_280[0x40];
7096
7097         u8         event_bitmask[0x40];
7098
7099         u8         reserved_at_300[0x580];
7100
7101         u8         pas[0][0x40];
7102 };
7103
7104 struct mlx5_ifc_create_dct_out_bits {
7105         u8         status[0x8];
7106         u8         reserved_at_8[0x18];
7107
7108         u8         syndrome[0x20];
7109
7110         u8         reserved_at_40[0x8];
7111         u8         dctn[0x18];
7112
7113         u8         reserved_at_60[0x20];
7114 };
7115
7116 struct mlx5_ifc_create_dct_in_bits {
7117         u8         opcode[0x10];
7118         u8         reserved_at_10[0x10];
7119
7120         u8         reserved_at_20[0x10];
7121         u8         op_mod[0x10];
7122
7123         u8         reserved_at_40[0x40];
7124
7125         struct mlx5_ifc_dctc_bits dct_context_entry;
7126
7127         u8         reserved_at_280[0x180];
7128 };
7129
7130 struct mlx5_ifc_create_cq_out_bits {
7131         u8         status[0x8];
7132         u8         reserved_at_8[0x18];
7133
7134         u8         syndrome[0x20];
7135
7136         u8         reserved_at_40[0x8];
7137         u8         cqn[0x18];
7138
7139         u8         reserved_at_60[0x20];
7140 };
7141
7142 struct mlx5_ifc_create_cq_in_bits {
7143         u8         opcode[0x10];
7144         u8         reserved_at_10[0x10];
7145
7146         u8         reserved_at_20[0x10];
7147         u8         op_mod[0x10];
7148
7149         u8         reserved_at_40[0x40];
7150
7151         struct mlx5_ifc_cqc_bits cq_context;
7152
7153         u8         reserved_at_280[0x600];
7154
7155         u8         pas[0][0x40];
7156 };
7157
7158 struct mlx5_ifc_config_int_moderation_out_bits {
7159         u8         status[0x8];
7160         u8         reserved_at_8[0x18];
7161
7162         u8         syndrome[0x20];
7163
7164         u8         reserved_at_40[0x4];
7165         u8         min_delay[0xc];
7166         u8         int_vector[0x10];
7167
7168         u8         reserved_at_60[0x20];
7169 };
7170
7171 enum {
7172         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7173         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7174 };
7175
7176 struct mlx5_ifc_config_int_moderation_in_bits {
7177         u8         opcode[0x10];
7178         u8         reserved_at_10[0x10];
7179
7180         u8         reserved_at_20[0x10];
7181         u8         op_mod[0x10];
7182
7183         u8         reserved_at_40[0x4];
7184         u8         min_delay[0xc];
7185         u8         int_vector[0x10];
7186
7187         u8         reserved_at_60[0x20];
7188 };
7189
7190 struct mlx5_ifc_attach_to_mcg_out_bits {
7191         u8         status[0x8];
7192         u8         reserved_at_8[0x18];
7193
7194         u8         syndrome[0x20];
7195
7196         u8         reserved_at_40[0x40];
7197 };
7198
7199 struct mlx5_ifc_attach_to_mcg_in_bits {
7200         u8         opcode[0x10];
7201         u8         reserved_at_10[0x10];
7202
7203         u8         reserved_at_20[0x10];
7204         u8         op_mod[0x10];
7205
7206         u8         reserved_at_40[0x8];
7207         u8         qpn[0x18];
7208
7209         u8         reserved_at_60[0x20];
7210
7211         u8         multicast_gid[16][0x8];
7212 };
7213
7214 struct mlx5_ifc_arm_xrq_out_bits {
7215         u8         status[0x8];
7216         u8         reserved_at_8[0x18];
7217
7218         u8         syndrome[0x20];
7219
7220         u8         reserved_at_40[0x40];
7221 };
7222
7223 struct mlx5_ifc_arm_xrq_in_bits {
7224         u8         opcode[0x10];
7225         u8         reserved_at_10[0x10];
7226
7227         u8         reserved_at_20[0x10];
7228         u8         op_mod[0x10];
7229
7230         u8         reserved_at_40[0x8];
7231         u8         xrqn[0x18];
7232
7233         u8         reserved_at_60[0x10];
7234         u8         lwm[0x10];
7235 };
7236
7237 struct mlx5_ifc_arm_xrc_srq_out_bits {
7238         u8         status[0x8];
7239         u8         reserved_at_8[0x18];
7240
7241         u8         syndrome[0x20];
7242
7243         u8         reserved_at_40[0x40];
7244 };
7245
7246 enum {
7247         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7248 };
7249
7250 struct mlx5_ifc_arm_xrc_srq_in_bits {
7251         u8         opcode[0x10];
7252         u8         reserved_at_10[0x10];
7253
7254         u8         reserved_at_20[0x10];
7255         u8         op_mod[0x10];
7256
7257         u8         reserved_at_40[0x8];
7258         u8         xrc_srqn[0x18];
7259
7260         u8         reserved_at_60[0x10];
7261         u8         lwm[0x10];
7262 };
7263
7264 struct mlx5_ifc_arm_rq_out_bits {
7265         u8         status[0x8];
7266         u8         reserved_at_8[0x18];
7267
7268         u8         syndrome[0x20];
7269
7270         u8         reserved_at_40[0x40];
7271 };
7272
7273 enum {
7274         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7275         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7276 };
7277
7278 struct mlx5_ifc_arm_rq_in_bits {
7279         u8         opcode[0x10];
7280         u8         reserved_at_10[0x10];
7281
7282         u8         reserved_at_20[0x10];
7283         u8         op_mod[0x10];
7284
7285         u8         reserved_at_40[0x8];
7286         u8         srq_number[0x18];
7287
7288         u8         reserved_at_60[0x10];
7289         u8         lwm[0x10];
7290 };
7291
7292 struct mlx5_ifc_arm_dct_out_bits {
7293         u8         status[0x8];
7294         u8         reserved_at_8[0x18];
7295
7296         u8         syndrome[0x20];
7297
7298         u8         reserved_at_40[0x40];
7299 };
7300
7301 struct mlx5_ifc_arm_dct_in_bits {
7302         u8         opcode[0x10];
7303         u8         reserved_at_10[0x10];
7304
7305         u8         reserved_at_20[0x10];
7306         u8         op_mod[0x10];
7307
7308         u8         reserved_at_40[0x8];
7309         u8         dct_number[0x18];
7310
7311         u8         reserved_at_60[0x20];
7312 };
7313
7314 struct mlx5_ifc_alloc_xrcd_out_bits {
7315         u8         status[0x8];
7316         u8         reserved_at_8[0x18];
7317
7318         u8         syndrome[0x20];
7319
7320         u8         reserved_at_40[0x8];
7321         u8         xrcd[0x18];
7322
7323         u8         reserved_at_60[0x20];
7324 };
7325
7326 struct mlx5_ifc_alloc_xrcd_in_bits {
7327         u8         opcode[0x10];
7328         u8         reserved_at_10[0x10];
7329
7330         u8         reserved_at_20[0x10];
7331         u8         op_mod[0x10];
7332
7333         u8         reserved_at_40[0x40];
7334 };
7335
7336 struct mlx5_ifc_alloc_uar_out_bits {
7337         u8         status[0x8];
7338         u8         reserved_at_8[0x18];
7339
7340         u8         syndrome[0x20];
7341
7342         u8         reserved_at_40[0x8];
7343         u8         uar[0x18];
7344
7345         u8         reserved_at_60[0x20];
7346 };
7347
7348 struct mlx5_ifc_alloc_uar_in_bits {
7349         u8         opcode[0x10];
7350         u8         reserved_at_10[0x10];
7351
7352         u8         reserved_at_20[0x10];
7353         u8         op_mod[0x10];
7354
7355         u8         reserved_at_40[0x40];
7356 };
7357
7358 struct mlx5_ifc_alloc_transport_domain_out_bits {
7359         u8         status[0x8];
7360         u8         reserved_at_8[0x18];
7361
7362         u8         syndrome[0x20];
7363
7364         u8         reserved_at_40[0x8];
7365         u8         transport_domain[0x18];
7366
7367         u8         reserved_at_60[0x20];
7368 };
7369
7370 struct mlx5_ifc_alloc_transport_domain_in_bits {
7371         u8         opcode[0x10];
7372         u8         reserved_at_10[0x10];
7373
7374         u8         reserved_at_20[0x10];
7375         u8         op_mod[0x10];
7376
7377         u8         reserved_at_40[0x40];
7378 };
7379
7380 struct mlx5_ifc_alloc_q_counter_out_bits {
7381         u8         status[0x8];
7382         u8         reserved_at_8[0x18];
7383
7384         u8         syndrome[0x20];
7385
7386         u8         reserved_at_40[0x18];
7387         u8         counter_set_id[0x8];
7388
7389         u8         reserved_at_60[0x20];
7390 };
7391
7392 struct mlx5_ifc_alloc_q_counter_in_bits {
7393         u8         opcode[0x10];
7394         u8         reserved_at_10[0x10];
7395
7396         u8         reserved_at_20[0x10];
7397         u8         op_mod[0x10];
7398
7399         u8         reserved_at_40[0x40];
7400 };
7401
7402 struct mlx5_ifc_alloc_pd_out_bits {
7403         u8         status[0x8];
7404         u8         reserved_at_8[0x18];
7405
7406         u8         syndrome[0x20];
7407
7408         u8         reserved_at_40[0x8];
7409         u8         pd[0x18];
7410
7411         u8         reserved_at_60[0x20];
7412 };
7413
7414 struct mlx5_ifc_alloc_pd_in_bits {
7415         u8         opcode[0x10];
7416         u8         reserved_at_10[0x10];
7417
7418         u8         reserved_at_20[0x10];
7419         u8         op_mod[0x10];
7420
7421         u8         reserved_at_40[0x40];
7422 };
7423
7424 struct mlx5_ifc_alloc_flow_counter_out_bits {
7425         u8         status[0x8];
7426         u8         reserved_at_8[0x18];
7427
7428         u8         syndrome[0x20];
7429
7430         u8         flow_counter_id[0x20];
7431
7432         u8         reserved_at_60[0x20];
7433 };
7434
7435 struct mlx5_ifc_alloc_flow_counter_in_bits {
7436         u8         opcode[0x10];
7437         u8         reserved_at_10[0x10];
7438
7439         u8         reserved_at_20[0x10];
7440         u8         op_mod[0x10];
7441
7442         u8         reserved_at_40[0x40];
7443 };
7444
7445 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7446         u8         status[0x8];
7447         u8         reserved_at_8[0x18];
7448
7449         u8         syndrome[0x20];
7450
7451         u8         reserved_at_40[0x40];
7452 };
7453
7454 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7455         u8         opcode[0x10];
7456         u8         reserved_at_10[0x10];
7457
7458         u8         reserved_at_20[0x10];
7459         u8         op_mod[0x10];
7460
7461         u8         reserved_at_40[0x20];
7462
7463         u8         reserved_at_60[0x10];
7464         u8         vxlan_udp_port[0x10];
7465 };
7466
7467 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7468         u8         status[0x8];
7469         u8         reserved_at_8[0x18];
7470
7471         u8         syndrome[0x20];
7472
7473         u8         reserved_at_40[0x40];
7474 };
7475
7476 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7477         u8         opcode[0x10];
7478         u8         reserved_at_10[0x10];
7479
7480         u8         reserved_at_20[0x10];
7481         u8         op_mod[0x10];
7482
7483         u8         reserved_at_40[0x10];
7484         u8         rate_limit_index[0x10];
7485
7486         u8         reserved_at_60[0x20];
7487
7488         u8         rate_limit[0x20];
7489
7490         u8         burst_upper_bound[0x20];
7491
7492         u8         reserved_at_c0[0x10];
7493         u8         typical_packet_size[0x10];
7494
7495         u8         reserved_at_e0[0x120];
7496 };
7497
7498 struct mlx5_ifc_access_register_out_bits {
7499         u8         status[0x8];
7500         u8         reserved_at_8[0x18];
7501
7502         u8         syndrome[0x20];
7503
7504         u8         reserved_at_40[0x40];
7505
7506         u8         register_data[0][0x20];
7507 };
7508
7509 enum {
7510         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7511         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7512 };
7513
7514 struct mlx5_ifc_access_register_in_bits {
7515         u8         opcode[0x10];
7516         u8         reserved_at_10[0x10];
7517
7518         u8         reserved_at_20[0x10];
7519         u8         op_mod[0x10];
7520
7521         u8         reserved_at_40[0x10];
7522         u8         register_id[0x10];
7523
7524         u8         argument[0x20];
7525
7526         u8         register_data[0][0x20];
7527 };
7528
7529 struct mlx5_ifc_sltp_reg_bits {
7530         u8         status[0x4];
7531         u8         version[0x4];
7532         u8         local_port[0x8];
7533         u8         pnat[0x2];
7534         u8         reserved_at_12[0x2];
7535         u8         lane[0x4];
7536         u8         reserved_at_18[0x8];
7537
7538         u8         reserved_at_20[0x20];
7539
7540         u8         reserved_at_40[0x7];
7541         u8         polarity[0x1];
7542         u8         ob_tap0[0x8];
7543         u8         ob_tap1[0x8];
7544         u8         ob_tap2[0x8];
7545
7546         u8         reserved_at_60[0xc];
7547         u8         ob_preemp_mode[0x4];
7548         u8         ob_reg[0x8];
7549         u8         ob_bias[0x8];
7550
7551         u8         reserved_at_80[0x20];
7552 };
7553
7554 struct mlx5_ifc_slrg_reg_bits {
7555         u8         status[0x4];
7556         u8         version[0x4];
7557         u8         local_port[0x8];
7558         u8         pnat[0x2];
7559         u8         reserved_at_12[0x2];
7560         u8         lane[0x4];
7561         u8         reserved_at_18[0x8];
7562
7563         u8         time_to_link_up[0x10];
7564         u8         reserved_at_30[0xc];
7565         u8         grade_lane_speed[0x4];
7566
7567         u8         grade_version[0x8];
7568         u8         grade[0x18];
7569
7570         u8         reserved_at_60[0x4];
7571         u8         height_grade_type[0x4];
7572         u8         height_grade[0x18];
7573
7574         u8         height_dz[0x10];
7575         u8         height_dv[0x10];
7576
7577         u8         reserved_at_a0[0x10];
7578         u8         height_sigma[0x10];
7579
7580         u8         reserved_at_c0[0x20];
7581
7582         u8         reserved_at_e0[0x4];
7583         u8         phase_grade_type[0x4];
7584         u8         phase_grade[0x18];
7585
7586         u8         reserved_at_100[0x8];
7587         u8         phase_eo_pos[0x8];
7588         u8         reserved_at_110[0x8];
7589         u8         phase_eo_neg[0x8];
7590
7591         u8         ffe_set_tested[0x10];
7592         u8         test_errors_per_lane[0x10];
7593 };
7594
7595 struct mlx5_ifc_pvlc_reg_bits {
7596         u8         reserved_at_0[0x8];
7597         u8         local_port[0x8];
7598         u8         reserved_at_10[0x10];
7599
7600         u8         reserved_at_20[0x1c];
7601         u8         vl_hw_cap[0x4];
7602
7603         u8         reserved_at_40[0x1c];
7604         u8         vl_admin[0x4];
7605
7606         u8         reserved_at_60[0x1c];
7607         u8         vl_operational[0x4];
7608 };
7609
7610 struct mlx5_ifc_pude_reg_bits {
7611         u8         swid[0x8];
7612         u8         local_port[0x8];
7613         u8         reserved_at_10[0x4];
7614         u8         admin_status[0x4];
7615         u8         reserved_at_18[0x4];
7616         u8         oper_status[0x4];
7617
7618         u8         reserved_at_20[0x60];
7619 };
7620
7621 struct mlx5_ifc_ptys_reg_bits {
7622         u8         reserved_at_0[0x1];
7623         u8         an_disable_admin[0x1];
7624         u8         an_disable_cap[0x1];
7625         u8         reserved_at_3[0x5];
7626         u8         local_port[0x8];
7627         u8         reserved_at_10[0xd];
7628         u8         proto_mask[0x3];
7629
7630         u8         an_status[0x4];
7631         u8         reserved_at_24[0x3c];
7632
7633         u8         eth_proto_capability[0x20];
7634
7635         u8         ib_link_width_capability[0x10];
7636         u8         ib_proto_capability[0x10];
7637
7638         u8         reserved_at_a0[0x20];
7639
7640         u8         eth_proto_admin[0x20];
7641
7642         u8         ib_link_width_admin[0x10];
7643         u8         ib_proto_admin[0x10];
7644
7645         u8         reserved_at_100[0x20];
7646
7647         u8         eth_proto_oper[0x20];
7648
7649         u8         ib_link_width_oper[0x10];
7650         u8         ib_proto_oper[0x10];
7651
7652         u8         reserved_at_160[0x1c];
7653         u8         connector_type[0x4];
7654
7655         u8         eth_proto_lp_advertise[0x20];
7656
7657         u8         reserved_at_1a0[0x60];
7658 };
7659
7660 struct mlx5_ifc_mlcr_reg_bits {
7661         u8         reserved_at_0[0x8];
7662         u8         local_port[0x8];
7663         u8         reserved_at_10[0x20];
7664
7665         u8         beacon_duration[0x10];
7666         u8         reserved_at_40[0x10];
7667
7668         u8         beacon_remain[0x10];
7669 };
7670
7671 struct mlx5_ifc_ptas_reg_bits {
7672         u8         reserved_at_0[0x20];
7673
7674         u8         algorithm_options[0x10];
7675         u8         reserved_at_30[0x4];
7676         u8         repetitions_mode[0x4];
7677         u8         num_of_repetitions[0x8];
7678
7679         u8         grade_version[0x8];
7680         u8         height_grade_type[0x4];
7681         u8         phase_grade_type[0x4];
7682         u8         height_grade_weight[0x8];
7683         u8         phase_grade_weight[0x8];
7684
7685         u8         gisim_measure_bits[0x10];
7686         u8         adaptive_tap_measure_bits[0x10];
7687
7688         u8         ber_bath_high_error_threshold[0x10];
7689         u8         ber_bath_mid_error_threshold[0x10];
7690
7691         u8         ber_bath_low_error_threshold[0x10];
7692         u8         one_ratio_high_threshold[0x10];
7693
7694         u8         one_ratio_high_mid_threshold[0x10];
7695         u8         one_ratio_low_mid_threshold[0x10];
7696
7697         u8         one_ratio_low_threshold[0x10];
7698         u8         ndeo_error_threshold[0x10];
7699
7700         u8         mixer_offset_step_size[0x10];
7701         u8         reserved_at_110[0x8];
7702         u8         mix90_phase_for_voltage_bath[0x8];
7703
7704         u8         mixer_offset_start[0x10];
7705         u8         mixer_offset_end[0x10];
7706
7707         u8         reserved_at_140[0x15];
7708         u8         ber_test_time[0xb];
7709 };
7710
7711 struct mlx5_ifc_pspa_reg_bits {
7712         u8         swid[0x8];
7713         u8         local_port[0x8];
7714         u8         sub_port[0x8];
7715         u8         reserved_at_18[0x8];
7716
7717         u8         reserved_at_20[0x20];
7718 };
7719
7720 struct mlx5_ifc_pqdr_reg_bits {
7721         u8         reserved_at_0[0x8];
7722         u8         local_port[0x8];
7723         u8         reserved_at_10[0x5];
7724         u8         prio[0x3];
7725         u8         reserved_at_18[0x6];
7726         u8         mode[0x2];
7727
7728         u8         reserved_at_20[0x20];
7729
7730         u8         reserved_at_40[0x10];
7731         u8         min_threshold[0x10];
7732
7733         u8         reserved_at_60[0x10];
7734         u8         max_threshold[0x10];
7735
7736         u8         reserved_at_80[0x10];
7737         u8         mark_probability_denominator[0x10];
7738
7739         u8         reserved_at_a0[0x60];
7740 };
7741
7742 struct mlx5_ifc_ppsc_reg_bits {
7743         u8         reserved_at_0[0x8];
7744         u8         local_port[0x8];
7745         u8         reserved_at_10[0x10];
7746
7747         u8         reserved_at_20[0x60];
7748
7749         u8         reserved_at_80[0x1c];
7750         u8         wrps_admin[0x4];
7751
7752         u8         reserved_at_a0[0x1c];
7753         u8         wrps_status[0x4];
7754
7755         u8         reserved_at_c0[0x8];
7756         u8         up_threshold[0x8];
7757         u8         reserved_at_d0[0x8];
7758         u8         down_threshold[0x8];
7759
7760         u8         reserved_at_e0[0x20];
7761
7762         u8         reserved_at_100[0x1c];
7763         u8         srps_admin[0x4];
7764
7765         u8         reserved_at_120[0x1c];
7766         u8         srps_status[0x4];
7767
7768         u8         reserved_at_140[0x40];
7769 };
7770
7771 struct mlx5_ifc_pplr_reg_bits {
7772         u8         reserved_at_0[0x8];
7773         u8         local_port[0x8];
7774         u8         reserved_at_10[0x10];
7775
7776         u8         reserved_at_20[0x8];
7777         u8         lb_cap[0x8];
7778         u8         reserved_at_30[0x8];
7779         u8         lb_en[0x8];
7780 };
7781
7782 struct mlx5_ifc_pplm_reg_bits {
7783         u8         reserved_at_0[0x8];
7784         u8         local_port[0x8];
7785         u8         reserved_at_10[0x10];
7786
7787         u8         reserved_at_20[0x20];
7788
7789         u8         port_profile_mode[0x8];
7790         u8         static_port_profile[0x8];
7791         u8         active_port_profile[0x8];
7792         u8         reserved_at_58[0x8];
7793
7794         u8         retransmission_active[0x8];
7795         u8         fec_mode_active[0x18];
7796
7797         u8         reserved_at_80[0x20];
7798 };
7799
7800 struct mlx5_ifc_ppcnt_reg_bits {
7801         u8         swid[0x8];
7802         u8         local_port[0x8];
7803         u8         pnat[0x2];
7804         u8         reserved_at_12[0x8];
7805         u8         grp[0x6];
7806
7807         u8         clr[0x1];
7808         u8         reserved_at_21[0x1c];
7809         u8         prio_tc[0x3];
7810
7811         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7812 };
7813
7814 struct mlx5_ifc_mpcnt_reg_bits {
7815         u8         reserved_at_0[0x8];
7816         u8         pcie_index[0x8];
7817         u8         reserved_at_10[0xa];
7818         u8         grp[0x6];
7819
7820         u8         clr[0x1];
7821         u8         reserved_at_21[0x1f];
7822
7823         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7824 };
7825
7826 struct mlx5_ifc_ppad_reg_bits {
7827         u8         reserved_at_0[0x3];
7828         u8         single_mac[0x1];
7829         u8         reserved_at_4[0x4];
7830         u8         local_port[0x8];
7831         u8         mac_47_32[0x10];
7832
7833         u8         mac_31_0[0x20];
7834
7835         u8         reserved_at_40[0x40];
7836 };
7837
7838 struct mlx5_ifc_pmtu_reg_bits {
7839         u8         reserved_at_0[0x8];
7840         u8         local_port[0x8];
7841         u8         reserved_at_10[0x10];
7842
7843         u8         max_mtu[0x10];
7844         u8         reserved_at_30[0x10];
7845
7846         u8         admin_mtu[0x10];
7847         u8         reserved_at_50[0x10];
7848
7849         u8         oper_mtu[0x10];
7850         u8         reserved_at_70[0x10];
7851 };
7852
7853 struct mlx5_ifc_pmpr_reg_bits {
7854         u8         reserved_at_0[0x8];
7855         u8         module[0x8];
7856         u8         reserved_at_10[0x10];
7857
7858         u8         reserved_at_20[0x18];
7859         u8         attenuation_5g[0x8];
7860
7861         u8         reserved_at_40[0x18];
7862         u8         attenuation_7g[0x8];
7863
7864         u8         reserved_at_60[0x18];
7865         u8         attenuation_12g[0x8];
7866 };
7867
7868 struct mlx5_ifc_pmpe_reg_bits {
7869         u8         reserved_at_0[0x8];
7870         u8         module[0x8];
7871         u8         reserved_at_10[0xc];
7872         u8         module_status[0x4];
7873
7874         u8         reserved_at_20[0x60];
7875 };
7876
7877 struct mlx5_ifc_pmpc_reg_bits {
7878         u8         module_state_updated[32][0x8];
7879 };
7880
7881 struct mlx5_ifc_pmlpn_reg_bits {
7882         u8         reserved_at_0[0x4];
7883         u8         mlpn_status[0x4];
7884         u8         local_port[0x8];
7885         u8         reserved_at_10[0x10];
7886
7887         u8         e[0x1];
7888         u8         reserved_at_21[0x1f];
7889 };
7890
7891 struct mlx5_ifc_pmlp_reg_bits {
7892         u8         rxtx[0x1];
7893         u8         reserved_at_1[0x7];
7894         u8         local_port[0x8];
7895         u8         reserved_at_10[0x8];
7896         u8         width[0x8];
7897
7898         u8         lane0_module_mapping[0x20];
7899
7900         u8         lane1_module_mapping[0x20];
7901
7902         u8         lane2_module_mapping[0x20];
7903
7904         u8         lane3_module_mapping[0x20];
7905
7906         u8         reserved_at_a0[0x160];
7907 };
7908
7909 struct mlx5_ifc_pmaos_reg_bits {
7910         u8         reserved_at_0[0x8];
7911         u8         module[0x8];
7912         u8         reserved_at_10[0x4];
7913         u8         admin_status[0x4];
7914         u8         reserved_at_18[0x4];
7915         u8         oper_status[0x4];
7916
7917         u8         ase[0x1];
7918         u8         ee[0x1];
7919         u8         reserved_at_22[0x1c];
7920         u8         e[0x2];
7921
7922         u8         reserved_at_40[0x40];
7923 };
7924
7925 struct mlx5_ifc_plpc_reg_bits {
7926         u8         reserved_at_0[0x4];
7927         u8         profile_id[0xc];
7928         u8         reserved_at_10[0x4];
7929         u8         proto_mask[0x4];
7930         u8         reserved_at_18[0x8];
7931
7932         u8         reserved_at_20[0x10];
7933         u8         lane_speed[0x10];
7934
7935         u8         reserved_at_40[0x17];
7936         u8         lpbf[0x1];
7937         u8         fec_mode_policy[0x8];
7938
7939         u8         retransmission_capability[0x8];
7940         u8         fec_mode_capability[0x18];
7941
7942         u8         retransmission_support_admin[0x8];
7943         u8         fec_mode_support_admin[0x18];
7944
7945         u8         retransmission_request_admin[0x8];
7946         u8         fec_mode_request_admin[0x18];
7947
7948         u8         reserved_at_c0[0x80];
7949 };
7950
7951 struct mlx5_ifc_plib_reg_bits {
7952         u8         reserved_at_0[0x8];
7953         u8         local_port[0x8];
7954         u8         reserved_at_10[0x8];
7955         u8         ib_port[0x8];
7956
7957         u8         reserved_at_20[0x60];
7958 };
7959
7960 struct mlx5_ifc_plbf_reg_bits {
7961         u8         reserved_at_0[0x8];
7962         u8         local_port[0x8];
7963         u8         reserved_at_10[0xd];
7964         u8         lbf_mode[0x3];
7965
7966         u8         reserved_at_20[0x20];
7967 };
7968
7969 struct mlx5_ifc_pipg_reg_bits {
7970         u8         reserved_at_0[0x8];
7971         u8         local_port[0x8];
7972         u8         reserved_at_10[0x10];
7973
7974         u8         dic[0x1];
7975         u8         reserved_at_21[0x19];
7976         u8         ipg[0x4];
7977         u8         reserved_at_3e[0x2];
7978 };
7979
7980 struct mlx5_ifc_pifr_reg_bits {
7981         u8         reserved_at_0[0x8];
7982         u8         local_port[0x8];
7983         u8         reserved_at_10[0x10];
7984
7985         u8         reserved_at_20[0xe0];
7986
7987         u8         port_filter[8][0x20];
7988
7989         u8         port_filter_update_en[8][0x20];
7990 };
7991
7992 struct mlx5_ifc_pfcc_reg_bits {
7993         u8         reserved_at_0[0x8];
7994         u8         local_port[0x8];
7995         u8         reserved_at_10[0xb];
7996         u8         ppan_mask_n[0x1];
7997         u8         minor_stall_mask[0x1];
7998         u8         critical_stall_mask[0x1];
7999         u8         reserved_at_1e[0x2];
8000
8001         u8         ppan[0x4];
8002         u8         reserved_at_24[0x4];
8003         u8         prio_mask_tx[0x8];
8004         u8         reserved_at_30[0x8];
8005         u8         prio_mask_rx[0x8];
8006
8007         u8         pptx[0x1];
8008         u8         aptx[0x1];
8009         u8         pptx_mask_n[0x1];
8010         u8         reserved_at_43[0x5];
8011         u8         pfctx[0x8];
8012         u8         reserved_at_50[0x10];
8013
8014         u8         pprx[0x1];
8015         u8         aprx[0x1];
8016         u8         pprx_mask_n[0x1];
8017         u8         reserved_at_63[0x5];
8018         u8         pfcrx[0x8];
8019         u8         reserved_at_70[0x10];
8020
8021         u8         device_stall_minor_watermark[0x10];
8022         u8         device_stall_critical_watermark[0x10];
8023
8024         u8         reserved_at_a0[0x60];
8025 };
8026
8027 struct mlx5_ifc_pelc_reg_bits {
8028         u8         op[0x4];
8029         u8         reserved_at_4[0x4];
8030         u8         local_port[0x8];
8031         u8         reserved_at_10[0x10];
8032
8033         u8         op_admin[0x8];
8034         u8         op_capability[0x8];
8035         u8         op_request[0x8];
8036         u8         op_active[0x8];
8037
8038         u8         admin[0x40];
8039
8040         u8         capability[0x40];
8041
8042         u8         request[0x40];
8043
8044         u8         active[0x40];
8045
8046         u8         reserved_at_140[0x80];
8047 };
8048
8049 struct mlx5_ifc_peir_reg_bits {
8050         u8         reserved_at_0[0x8];
8051         u8         local_port[0x8];
8052         u8         reserved_at_10[0x10];
8053
8054         u8         reserved_at_20[0xc];
8055         u8         error_count[0x4];
8056         u8         reserved_at_30[0x10];
8057
8058         u8         reserved_at_40[0xc];
8059         u8         lane[0x4];
8060         u8         reserved_at_50[0x8];
8061         u8         error_type[0x8];
8062 };
8063
8064 struct mlx5_ifc_mpegc_reg_bits {
8065         u8         reserved_at_0[0x30];
8066         u8         field_select[0x10];
8067
8068         u8         tx_overflow_sense[0x1];
8069         u8         mark_cqe[0x1];
8070         u8         mark_cnp[0x1];
8071         u8         reserved_at_43[0x1b];
8072         u8         tx_lossy_overflow_oper[0x2];
8073
8074         u8         reserved_at_60[0x100];
8075 };
8076
8077 struct mlx5_ifc_pcam_enhanced_features_bits {
8078         u8         reserved_at_0[0x6d];
8079         u8         rx_icrc_encapsulated_counter[0x1];
8080         u8         reserved_at_6e[0x8];
8081         u8         pfcc_mask[0x1];
8082         u8         reserved_at_77[0x4];
8083         u8         rx_buffer_fullness_counters[0x1];
8084         u8         ptys_connector_type[0x1];
8085         u8         reserved_at_7d[0x1];
8086         u8         ppcnt_discard_group[0x1];
8087         u8         ppcnt_statistical_group[0x1];
8088 };
8089
8090 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8091         u8         port_access_reg_cap_mask_127_to_96[0x20];
8092         u8         port_access_reg_cap_mask_95_to_64[0x20];
8093         u8         port_access_reg_cap_mask_63_to_32[0x20];
8094
8095         u8         port_access_reg_cap_mask_31_to_13[0x13];
8096         u8         pbmc[0x1];
8097         u8         pptb[0x1];
8098         u8         port_access_reg_cap_mask_10_to_0[0xb];
8099 };
8100
8101 struct mlx5_ifc_pcam_reg_bits {
8102         u8         reserved_at_0[0x8];
8103         u8         feature_group[0x8];
8104         u8         reserved_at_10[0x8];
8105         u8         access_reg_group[0x8];
8106
8107         u8         reserved_at_20[0x20];
8108
8109         union {
8110                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8111                 u8         reserved_at_0[0x80];
8112         } port_access_reg_cap_mask;
8113
8114         u8         reserved_at_c0[0x80];
8115
8116         union {
8117                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8118                 u8         reserved_at_0[0x80];
8119         } feature_cap_mask;
8120
8121         u8         reserved_at_1c0[0xc0];
8122 };
8123
8124 struct mlx5_ifc_mcam_enhanced_features_bits {
8125         u8         reserved_at_0[0x74];
8126         u8         mark_tx_action_cnp[0x1];
8127         u8         mark_tx_action_cqe[0x1];
8128         u8         dynamic_tx_overflow[0x1];
8129         u8         reserved_at_77[0x4];
8130         u8         pcie_outbound_stalled[0x1];
8131         u8         tx_overflow_buffer_pkt[0x1];
8132         u8         mtpps_enh_out_per_adj[0x1];
8133         u8         mtpps_fs[0x1];
8134         u8         pcie_performance_group[0x1];
8135 };
8136
8137 struct mlx5_ifc_mcam_access_reg_bits {
8138         u8         reserved_at_0[0x1c];
8139         u8         mcda[0x1];
8140         u8         mcc[0x1];
8141         u8         mcqi[0x1];
8142         u8         reserved_at_1f[0x1];
8143
8144         u8         regs_95_to_87[0x9];
8145         u8         mpegc[0x1];
8146         u8         regs_85_to_68[0x12];
8147         u8         tracer_registers[0x4];
8148
8149         u8         regs_63_to_32[0x20];
8150         u8         regs_31_to_0[0x20];
8151 };
8152
8153 struct mlx5_ifc_mcam_reg_bits {
8154         u8         reserved_at_0[0x8];
8155         u8         feature_group[0x8];
8156         u8         reserved_at_10[0x8];
8157         u8         access_reg_group[0x8];
8158
8159         u8         reserved_at_20[0x20];
8160
8161         union {
8162                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8163                 u8         reserved_at_0[0x80];
8164         } mng_access_reg_cap_mask;
8165
8166         u8         reserved_at_c0[0x80];
8167
8168         union {
8169                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8170                 u8         reserved_at_0[0x80];
8171         } mng_feature_cap_mask;
8172
8173         u8         reserved_at_1c0[0x80];
8174 };
8175
8176 struct mlx5_ifc_qcam_access_reg_cap_mask {
8177         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8178         u8         qpdpm[0x1];
8179         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8180         u8         qdpm[0x1];
8181         u8         qpts[0x1];
8182         u8         qcap[0x1];
8183         u8         qcam_access_reg_cap_mask_0[0x1];
8184 };
8185
8186 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8187         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8188         u8         qpts_trust_both[0x1];
8189 };
8190
8191 struct mlx5_ifc_qcam_reg_bits {
8192         u8         reserved_at_0[0x8];
8193         u8         feature_group[0x8];
8194         u8         reserved_at_10[0x8];
8195         u8         access_reg_group[0x8];
8196         u8         reserved_at_20[0x20];
8197
8198         union {
8199                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8200                 u8  reserved_at_0[0x80];
8201         } qos_access_reg_cap_mask;
8202
8203         u8         reserved_at_c0[0x80];
8204
8205         union {
8206                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8207                 u8  reserved_at_0[0x80];
8208         } qos_feature_cap_mask;
8209
8210         u8         reserved_at_1c0[0x80];
8211 };
8212
8213 struct mlx5_ifc_pcap_reg_bits {
8214         u8         reserved_at_0[0x8];
8215         u8         local_port[0x8];
8216         u8         reserved_at_10[0x10];
8217
8218         u8         port_capability_mask[4][0x20];
8219 };
8220
8221 struct mlx5_ifc_paos_reg_bits {
8222         u8         swid[0x8];
8223         u8         local_port[0x8];
8224         u8         reserved_at_10[0x4];
8225         u8         admin_status[0x4];
8226         u8         reserved_at_18[0x4];
8227         u8         oper_status[0x4];
8228
8229         u8         ase[0x1];
8230         u8         ee[0x1];
8231         u8         reserved_at_22[0x1c];
8232         u8         e[0x2];
8233
8234         u8         reserved_at_40[0x40];
8235 };
8236
8237 struct mlx5_ifc_pamp_reg_bits {
8238         u8         reserved_at_0[0x8];
8239         u8         opamp_group[0x8];
8240         u8         reserved_at_10[0xc];
8241         u8         opamp_group_type[0x4];
8242
8243         u8         start_index[0x10];
8244         u8         reserved_at_30[0x4];
8245         u8         num_of_indices[0xc];
8246
8247         u8         index_data[18][0x10];
8248 };
8249
8250 struct mlx5_ifc_pcmr_reg_bits {
8251         u8         reserved_at_0[0x8];
8252         u8         local_port[0x8];
8253         u8         reserved_at_10[0x2e];
8254         u8         fcs_cap[0x1];
8255         u8         reserved_at_3f[0x1f];
8256         u8         fcs_chk[0x1];
8257         u8         reserved_at_5f[0x1];
8258 };
8259
8260 struct mlx5_ifc_lane_2_module_mapping_bits {
8261         u8         reserved_at_0[0x6];
8262         u8         rx_lane[0x2];
8263         u8         reserved_at_8[0x6];
8264         u8         tx_lane[0x2];
8265         u8         reserved_at_10[0x8];
8266         u8         module[0x8];
8267 };
8268
8269 struct mlx5_ifc_bufferx_reg_bits {
8270         u8         reserved_at_0[0x6];
8271         u8         lossy[0x1];
8272         u8         epsb[0x1];
8273         u8         reserved_at_8[0xc];
8274         u8         size[0xc];
8275
8276         u8         xoff_threshold[0x10];
8277         u8         xon_threshold[0x10];
8278 };
8279
8280 struct mlx5_ifc_set_node_in_bits {
8281         u8         node_description[64][0x8];
8282 };
8283
8284 struct mlx5_ifc_register_power_settings_bits {
8285         u8         reserved_at_0[0x18];
8286         u8         power_settings_level[0x8];
8287
8288         u8         reserved_at_20[0x60];
8289 };
8290
8291 struct mlx5_ifc_register_host_endianness_bits {
8292         u8         he[0x1];
8293         u8         reserved_at_1[0x1f];
8294
8295         u8         reserved_at_20[0x60];
8296 };
8297
8298 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8299         u8         reserved_at_0[0x20];
8300
8301         u8         mkey[0x20];
8302
8303         u8         addressh_63_32[0x20];
8304
8305         u8         addressl_31_0[0x20];
8306 };
8307
8308 struct mlx5_ifc_ud_adrs_vector_bits {
8309         u8         dc_key[0x40];
8310
8311         u8         ext[0x1];
8312         u8         reserved_at_41[0x7];
8313         u8         destination_qp_dct[0x18];
8314
8315         u8         static_rate[0x4];
8316         u8         sl_eth_prio[0x4];
8317         u8         fl[0x1];
8318         u8         mlid[0x7];
8319         u8         rlid_udp_sport[0x10];
8320
8321         u8         reserved_at_80[0x20];
8322
8323         u8         rmac_47_16[0x20];
8324
8325         u8         rmac_15_0[0x10];
8326         u8         tclass[0x8];
8327         u8         hop_limit[0x8];
8328
8329         u8         reserved_at_e0[0x1];
8330         u8         grh[0x1];
8331         u8         reserved_at_e2[0x2];
8332         u8         src_addr_index[0x8];
8333         u8         flow_label[0x14];
8334
8335         u8         rgid_rip[16][0x8];
8336 };
8337
8338 struct mlx5_ifc_pages_req_event_bits {
8339         u8         reserved_at_0[0x10];
8340         u8         function_id[0x10];
8341
8342         u8         num_pages[0x20];
8343
8344         u8         reserved_at_40[0xa0];
8345 };
8346
8347 struct mlx5_ifc_eqe_bits {
8348         u8         reserved_at_0[0x8];
8349         u8         event_type[0x8];
8350         u8         reserved_at_10[0x8];
8351         u8         event_sub_type[0x8];
8352
8353         u8         reserved_at_20[0xe0];
8354
8355         union mlx5_ifc_event_auto_bits event_data;
8356
8357         u8         reserved_at_1e0[0x10];
8358         u8         signature[0x8];
8359         u8         reserved_at_1f8[0x7];
8360         u8         owner[0x1];
8361 };
8362
8363 enum {
8364         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8365 };
8366
8367 struct mlx5_ifc_cmd_queue_entry_bits {
8368         u8         type[0x8];
8369         u8         reserved_at_8[0x18];
8370
8371         u8         input_length[0x20];
8372
8373         u8         input_mailbox_pointer_63_32[0x20];
8374
8375         u8         input_mailbox_pointer_31_9[0x17];
8376         u8         reserved_at_77[0x9];
8377
8378         u8         command_input_inline_data[16][0x8];
8379
8380         u8         command_output_inline_data[16][0x8];
8381
8382         u8         output_mailbox_pointer_63_32[0x20];
8383
8384         u8         output_mailbox_pointer_31_9[0x17];
8385         u8         reserved_at_1b7[0x9];
8386
8387         u8         output_length[0x20];
8388
8389         u8         token[0x8];
8390         u8         signature[0x8];
8391         u8         reserved_at_1f0[0x8];
8392         u8         status[0x7];
8393         u8         ownership[0x1];
8394 };
8395
8396 struct mlx5_ifc_cmd_out_bits {
8397         u8         status[0x8];
8398         u8         reserved_at_8[0x18];
8399
8400         u8         syndrome[0x20];
8401
8402         u8         command_output[0x20];
8403 };
8404
8405 struct mlx5_ifc_cmd_in_bits {
8406         u8         opcode[0x10];
8407         u8         reserved_at_10[0x10];
8408
8409         u8         reserved_at_20[0x10];
8410         u8         op_mod[0x10];
8411
8412         u8         command[0][0x20];
8413 };
8414
8415 struct mlx5_ifc_cmd_if_box_bits {
8416         u8         mailbox_data[512][0x8];
8417
8418         u8         reserved_at_1000[0x180];
8419
8420         u8         next_pointer_63_32[0x20];
8421
8422         u8         next_pointer_31_10[0x16];
8423         u8         reserved_at_11b6[0xa];
8424
8425         u8         block_number[0x20];
8426
8427         u8         reserved_at_11e0[0x8];
8428         u8         token[0x8];
8429         u8         ctrl_signature[0x8];
8430         u8         signature[0x8];
8431 };
8432
8433 struct mlx5_ifc_mtt_bits {
8434         u8         ptag_63_32[0x20];
8435
8436         u8         ptag_31_8[0x18];
8437         u8         reserved_at_38[0x6];
8438         u8         wr_en[0x1];
8439         u8         rd_en[0x1];
8440 };
8441
8442 struct mlx5_ifc_query_wol_rol_out_bits {
8443         u8         status[0x8];
8444         u8         reserved_at_8[0x18];
8445
8446         u8         syndrome[0x20];
8447
8448         u8         reserved_at_40[0x10];
8449         u8         rol_mode[0x8];
8450         u8         wol_mode[0x8];
8451
8452         u8         reserved_at_60[0x20];
8453 };
8454
8455 struct mlx5_ifc_query_wol_rol_in_bits {
8456         u8         opcode[0x10];
8457         u8         reserved_at_10[0x10];
8458
8459         u8         reserved_at_20[0x10];
8460         u8         op_mod[0x10];
8461
8462         u8         reserved_at_40[0x40];
8463 };
8464
8465 struct mlx5_ifc_set_wol_rol_out_bits {
8466         u8         status[0x8];
8467         u8         reserved_at_8[0x18];
8468
8469         u8         syndrome[0x20];
8470
8471         u8         reserved_at_40[0x40];
8472 };
8473
8474 struct mlx5_ifc_set_wol_rol_in_bits {
8475         u8         opcode[0x10];
8476         u8         reserved_at_10[0x10];
8477
8478         u8         reserved_at_20[0x10];
8479         u8         op_mod[0x10];
8480
8481         u8         rol_mode_valid[0x1];
8482         u8         wol_mode_valid[0x1];
8483         u8         reserved_at_42[0xe];
8484         u8         rol_mode[0x8];
8485         u8         wol_mode[0x8];
8486
8487         u8         reserved_at_60[0x20];
8488 };
8489
8490 enum {
8491         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8492         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8493         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8494 };
8495
8496 enum {
8497         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8498         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8499         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8500 };
8501
8502 enum {
8503         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8504         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8505         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8506         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8507         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8508         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8509         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8510         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8511         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8512         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8513         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8514 };
8515
8516 struct mlx5_ifc_initial_seg_bits {
8517         u8         fw_rev_minor[0x10];
8518         u8         fw_rev_major[0x10];
8519
8520         u8         cmd_interface_rev[0x10];
8521         u8         fw_rev_subminor[0x10];
8522
8523         u8         reserved_at_40[0x40];
8524
8525         u8         cmdq_phy_addr_63_32[0x20];
8526
8527         u8         cmdq_phy_addr_31_12[0x14];
8528         u8         reserved_at_b4[0x2];
8529         u8         nic_interface[0x2];
8530         u8         log_cmdq_size[0x4];
8531         u8         log_cmdq_stride[0x4];
8532
8533         u8         command_doorbell_vector[0x20];
8534
8535         u8         reserved_at_e0[0xf00];
8536
8537         u8         initializing[0x1];
8538         u8         reserved_at_fe1[0x4];
8539         u8         nic_interface_supported[0x3];
8540         u8         reserved_at_fe8[0x18];
8541
8542         struct mlx5_ifc_health_buffer_bits health_buffer;
8543
8544         u8         no_dram_nic_offset[0x20];
8545
8546         u8         reserved_at_1220[0x6e40];
8547
8548         u8         reserved_at_8060[0x1f];
8549         u8         clear_int[0x1];
8550
8551         u8         health_syndrome[0x8];
8552         u8         health_counter[0x18];
8553
8554         u8         reserved_at_80a0[0x17fc0];
8555 };
8556
8557 struct mlx5_ifc_mtpps_reg_bits {
8558         u8         reserved_at_0[0xc];
8559         u8         cap_number_of_pps_pins[0x4];
8560         u8         reserved_at_10[0x4];
8561         u8         cap_max_num_of_pps_in_pins[0x4];
8562         u8         reserved_at_18[0x4];
8563         u8         cap_max_num_of_pps_out_pins[0x4];
8564
8565         u8         reserved_at_20[0x24];
8566         u8         cap_pin_3_mode[0x4];
8567         u8         reserved_at_48[0x4];
8568         u8         cap_pin_2_mode[0x4];
8569         u8         reserved_at_50[0x4];
8570         u8         cap_pin_1_mode[0x4];
8571         u8         reserved_at_58[0x4];
8572         u8         cap_pin_0_mode[0x4];
8573
8574         u8         reserved_at_60[0x4];
8575         u8         cap_pin_7_mode[0x4];
8576         u8         reserved_at_68[0x4];
8577         u8         cap_pin_6_mode[0x4];
8578         u8         reserved_at_70[0x4];
8579         u8         cap_pin_5_mode[0x4];
8580         u8         reserved_at_78[0x4];
8581         u8         cap_pin_4_mode[0x4];
8582
8583         u8         field_select[0x20];
8584         u8         reserved_at_a0[0x60];
8585
8586         u8         enable[0x1];
8587         u8         reserved_at_101[0xb];
8588         u8         pattern[0x4];
8589         u8         reserved_at_110[0x4];
8590         u8         pin_mode[0x4];
8591         u8         pin[0x8];
8592
8593         u8         reserved_at_120[0x20];
8594
8595         u8         time_stamp[0x40];
8596
8597         u8         out_pulse_duration[0x10];
8598         u8         out_periodic_adjustment[0x10];
8599         u8         enhanced_out_periodic_adjustment[0x20];
8600
8601         u8         reserved_at_1c0[0x20];
8602 };
8603
8604 struct mlx5_ifc_mtppse_reg_bits {
8605         u8         reserved_at_0[0x18];
8606         u8         pin[0x8];
8607         u8         event_arm[0x1];
8608         u8         reserved_at_21[0x1b];
8609         u8         event_generation_mode[0x4];
8610         u8         reserved_at_40[0x40];
8611 };
8612
8613 struct mlx5_ifc_mcqi_cap_bits {
8614         u8         supported_info_bitmask[0x20];
8615
8616         u8         component_size[0x20];
8617
8618         u8         max_component_size[0x20];
8619
8620         u8         log_mcda_word_size[0x4];
8621         u8         reserved_at_64[0xc];
8622         u8         mcda_max_write_size[0x10];
8623
8624         u8         rd_en[0x1];
8625         u8         reserved_at_81[0x1];
8626         u8         match_chip_id[0x1];
8627         u8         match_psid[0x1];
8628         u8         check_user_timestamp[0x1];
8629         u8         match_base_guid_mac[0x1];
8630         u8         reserved_at_86[0x1a];
8631 };
8632
8633 struct mlx5_ifc_mcqi_reg_bits {
8634         u8         read_pending_component[0x1];
8635         u8         reserved_at_1[0xf];
8636         u8         component_index[0x10];
8637
8638         u8         reserved_at_20[0x20];
8639
8640         u8         reserved_at_40[0x1b];
8641         u8         info_type[0x5];
8642
8643         u8         info_size[0x20];
8644
8645         u8         offset[0x20];
8646
8647         u8         reserved_at_a0[0x10];
8648         u8         data_size[0x10];
8649
8650         u8         data[0][0x20];
8651 };
8652
8653 struct mlx5_ifc_mcc_reg_bits {
8654         u8         reserved_at_0[0x4];
8655         u8         time_elapsed_since_last_cmd[0xc];
8656         u8         reserved_at_10[0x8];
8657         u8         instruction[0x8];
8658
8659         u8         reserved_at_20[0x10];
8660         u8         component_index[0x10];
8661
8662         u8         reserved_at_40[0x8];
8663         u8         update_handle[0x18];
8664
8665         u8         handle_owner_type[0x4];
8666         u8         handle_owner_host_id[0x4];
8667         u8         reserved_at_68[0x1];
8668         u8         control_progress[0x7];
8669         u8         error_code[0x8];
8670         u8         reserved_at_78[0x4];
8671         u8         control_state[0x4];
8672
8673         u8         component_size[0x20];
8674
8675         u8         reserved_at_a0[0x60];
8676 };
8677
8678 struct mlx5_ifc_mcda_reg_bits {
8679         u8         reserved_at_0[0x8];
8680         u8         update_handle[0x18];
8681
8682         u8         offset[0x20];
8683
8684         u8         reserved_at_40[0x10];
8685         u8         size[0x10];
8686
8687         u8         reserved_at_60[0x20];
8688
8689         u8         data[0][0x20];
8690 };
8691
8692 union mlx5_ifc_ports_control_registers_document_bits {
8693         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8694         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8695         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8696         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8697         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8698         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8699         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8700         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8701         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8702         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8703         struct mlx5_ifc_paos_reg_bits paos_reg;
8704         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8705         struct mlx5_ifc_peir_reg_bits peir_reg;
8706         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8707         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8708         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8709         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8710         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8711         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8712         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8713         struct mlx5_ifc_plib_reg_bits plib_reg;
8714         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8715         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8716         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8717         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8718         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8719         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8720         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8721         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8722         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8723         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8724         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8725         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8726         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8727         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8728         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8729         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8730         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8731         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8732         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8733         struct mlx5_ifc_pude_reg_bits pude_reg;
8734         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8735         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8736         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8737         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8738         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8739         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8740         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8741         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8742         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8743         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8744         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8745         u8         reserved_at_0[0x60e0];
8746 };
8747
8748 union mlx5_ifc_debug_enhancements_document_bits {
8749         struct mlx5_ifc_health_buffer_bits health_buffer;
8750         u8         reserved_at_0[0x200];
8751 };
8752
8753 union mlx5_ifc_uplink_pci_interface_document_bits {
8754         struct mlx5_ifc_initial_seg_bits initial_seg;
8755         u8         reserved_at_0[0x20060];
8756 };
8757
8758 struct mlx5_ifc_set_flow_table_root_out_bits {
8759         u8         status[0x8];
8760         u8         reserved_at_8[0x18];
8761
8762         u8         syndrome[0x20];
8763
8764         u8         reserved_at_40[0x40];
8765 };
8766
8767 struct mlx5_ifc_set_flow_table_root_in_bits {
8768         u8         opcode[0x10];
8769         u8         reserved_at_10[0x10];
8770
8771         u8         reserved_at_20[0x10];
8772         u8         op_mod[0x10];
8773
8774         u8         other_vport[0x1];
8775         u8         reserved_at_41[0xf];
8776         u8         vport_number[0x10];
8777
8778         u8         reserved_at_60[0x20];
8779
8780         u8         table_type[0x8];
8781         u8         reserved_at_88[0x18];
8782
8783         u8         reserved_at_a0[0x8];
8784         u8         table_id[0x18];
8785
8786         u8         reserved_at_c0[0x8];
8787         u8         underlay_qpn[0x18];
8788         u8         reserved_at_e0[0x120];
8789 };
8790
8791 enum {
8792         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8793         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8794 };
8795
8796 struct mlx5_ifc_modify_flow_table_out_bits {
8797         u8         status[0x8];
8798         u8         reserved_at_8[0x18];
8799
8800         u8         syndrome[0x20];
8801
8802         u8         reserved_at_40[0x40];
8803 };
8804
8805 struct mlx5_ifc_modify_flow_table_in_bits {
8806         u8         opcode[0x10];
8807         u8         reserved_at_10[0x10];
8808
8809         u8         reserved_at_20[0x10];
8810         u8         op_mod[0x10];
8811
8812         u8         other_vport[0x1];
8813         u8         reserved_at_41[0xf];
8814         u8         vport_number[0x10];
8815
8816         u8         reserved_at_60[0x10];
8817         u8         modify_field_select[0x10];
8818
8819         u8         table_type[0x8];
8820         u8         reserved_at_88[0x18];
8821
8822         u8         reserved_at_a0[0x8];
8823         u8         table_id[0x18];
8824
8825         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8826 };
8827
8828 struct mlx5_ifc_ets_tcn_config_reg_bits {
8829         u8         g[0x1];
8830         u8         b[0x1];
8831         u8         r[0x1];
8832         u8         reserved_at_3[0x9];
8833         u8         group[0x4];
8834         u8         reserved_at_10[0x9];
8835         u8         bw_allocation[0x7];
8836
8837         u8         reserved_at_20[0xc];
8838         u8         max_bw_units[0x4];
8839         u8         reserved_at_30[0x8];
8840         u8         max_bw_value[0x8];
8841 };
8842
8843 struct mlx5_ifc_ets_global_config_reg_bits {
8844         u8         reserved_at_0[0x2];
8845         u8         r[0x1];
8846         u8         reserved_at_3[0x1d];
8847
8848         u8         reserved_at_20[0xc];
8849         u8         max_bw_units[0x4];
8850         u8         reserved_at_30[0x8];
8851         u8         max_bw_value[0x8];
8852 };
8853
8854 struct mlx5_ifc_qetc_reg_bits {
8855         u8                                         reserved_at_0[0x8];
8856         u8                                         port_number[0x8];
8857         u8                                         reserved_at_10[0x30];
8858
8859         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8860         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8861 };
8862
8863 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8864         u8         e[0x1];
8865         u8         reserved_at_01[0x0b];
8866         u8         prio[0x04];
8867 };
8868
8869 struct mlx5_ifc_qpdpm_reg_bits {
8870         u8                                     reserved_at_0[0x8];
8871         u8                                     local_port[0x8];
8872         u8                                     reserved_at_10[0x10];
8873         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
8874 };
8875
8876 struct mlx5_ifc_qpts_reg_bits {
8877         u8         reserved_at_0[0x8];
8878         u8         local_port[0x8];
8879         u8         reserved_at_10[0x2d];
8880         u8         trust_state[0x3];
8881 };
8882
8883 struct mlx5_ifc_pptb_reg_bits {
8884         u8         reserved_at_0[0x2];
8885         u8         mm[0x2];
8886         u8         reserved_at_4[0x4];
8887         u8         local_port[0x8];
8888         u8         reserved_at_10[0x6];
8889         u8         cm[0x1];
8890         u8         um[0x1];
8891         u8         pm[0x8];
8892
8893         u8         prio_x_buff[0x20];
8894
8895         u8         pm_msb[0x8];
8896         u8         reserved_at_48[0x10];
8897         u8         ctrl_buff[0x4];
8898         u8         untagged_buff[0x4];
8899 };
8900
8901 struct mlx5_ifc_pbmc_reg_bits {
8902         u8         reserved_at_0[0x8];
8903         u8         local_port[0x8];
8904         u8         reserved_at_10[0x10];
8905
8906         u8         xoff_timer_value[0x10];
8907         u8         xoff_refresh[0x10];
8908
8909         u8         reserved_at_40[0x9];
8910         u8         fullness_threshold[0x7];
8911         u8         port_buffer_size[0x10];
8912
8913         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8914
8915         u8         reserved_at_2e0[0x40];
8916 };
8917
8918 struct mlx5_ifc_qtct_reg_bits {
8919         u8         reserved_at_0[0x8];
8920         u8         port_number[0x8];
8921         u8         reserved_at_10[0xd];
8922         u8         prio[0x3];
8923
8924         u8         reserved_at_20[0x1d];
8925         u8         tclass[0x3];
8926 };
8927
8928 struct mlx5_ifc_mcia_reg_bits {
8929         u8         l[0x1];
8930         u8         reserved_at_1[0x7];
8931         u8         module[0x8];
8932         u8         reserved_at_10[0x8];
8933         u8         status[0x8];
8934
8935         u8         i2c_device_address[0x8];
8936         u8         page_number[0x8];
8937         u8         device_address[0x10];
8938
8939         u8         reserved_at_40[0x10];
8940         u8         size[0x10];
8941
8942         u8         reserved_at_60[0x20];
8943
8944         u8         dword_0[0x20];
8945         u8         dword_1[0x20];
8946         u8         dword_2[0x20];
8947         u8         dword_3[0x20];
8948         u8         dword_4[0x20];
8949         u8         dword_5[0x20];
8950         u8         dword_6[0x20];
8951         u8         dword_7[0x20];
8952         u8         dword_8[0x20];
8953         u8         dword_9[0x20];
8954         u8         dword_10[0x20];
8955         u8         dword_11[0x20];
8956 };
8957
8958 struct mlx5_ifc_dcbx_param_bits {
8959         u8         dcbx_cee_cap[0x1];
8960         u8         dcbx_ieee_cap[0x1];
8961         u8         dcbx_standby_cap[0x1];
8962         u8         reserved_at_0[0x5];
8963         u8         port_number[0x8];
8964         u8         reserved_at_10[0xa];
8965         u8         max_application_table_size[6];
8966         u8         reserved_at_20[0x15];
8967         u8         version_oper[0x3];
8968         u8         reserved_at_38[5];
8969         u8         version_admin[0x3];
8970         u8         willing_admin[0x1];
8971         u8         reserved_at_41[0x3];
8972         u8         pfc_cap_oper[0x4];
8973         u8         reserved_at_48[0x4];
8974         u8         pfc_cap_admin[0x4];
8975         u8         reserved_at_50[0x4];
8976         u8         num_of_tc_oper[0x4];
8977         u8         reserved_at_58[0x4];
8978         u8         num_of_tc_admin[0x4];
8979         u8         remote_willing[0x1];
8980         u8         reserved_at_61[3];
8981         u8         remote_pfc_cap[4];
8982         u8         reserved_at_68[0x14];
8983         u8         remote_num_of_tc[0x4];
8984         u8         reserved_at_80[0x18];
8985         u8         error[0x8];
8986         u8         reserved_at_a0[0x160];
8987 };
8988
8989 struct mlx5_ifc_lagc_bits {
8990         u8         reserved_at_0[0x1d];
8991         u8         lag_state[0x3];
8992
8993         u8         reserved_at_20[0x14];
8994         u8         tx_remap_affinity_2[0x4];
8995         u8         reserved_at_38[0x4];
8996         u8         tx_remap_affinity_1[0x4];
8997 };
8998
8999 struct mlx5_ifc_create_lag_out_bits {
9000         u8         status[0x8];
9001         u8         reserved_at_8[0x18];
9002
9003         u8         syndrome[0x20];
9004
9005         u8         reserved_at_40[0x40];
9006 };
9007
9008 struct mlx5_ifc_create_lag_in_bits {
9009         u8         opcode[0x10];
9010         u8         reserved_at_10[0x10];
9011
9012         u8         reserved_at_20[0x10];
9013         u8         op_mod[0x10];
9014
9015         struct mlx5_ifc_lagc_bits ctx;
9016 };
9017
9018 struct mlx5_ifc_modify_lag_out_bits {
9019         u8         status[0x8];
9020         u8         reserved_at_8[0x18];
9021
9022         u8         syndrome[0x20];
9023
9024         u8         reserved_at_40[0x40];
9025 };
9026
9027 struct mlx5_ifc_modify_lag_in_bits {
9028         u8         opcode[0x10];
9029         u8         reserved_at_10[0x10];
9030
9031         u8         reserved_at_20[0x10];
9032         u8         op_mod[0x10];
9033
9034         u8         reserved_at_40[0x20];
9035         u8         field_select[0x20];
9036
9037         struct mlx5_ifc_lagc_bits ctx;
9038 };
9039
9040 struct mlx5_ifc_query_lag_out_bits {
9041         u8         status[0x8];
9042         u8         reserved_at_8[0x18];
9043
9044         u8         syndrome[0x20];
9045
9046         u8         reserved_at_40[0x40];
9047
9048         struct mlx5_ifc_lagc_bits ctx;
9049 };
9050
9051 struct mlx5_ifc_query_lag_in_bits {
9052         u8         opcode[0x10];
9053         u8         reserved_at_10[0x10];
9054
9055         u8         reserved_at_20[0x10];
9056         u8         op_mod[0x10];
9057
9058         u8         reserved_at_40[0x40];
9059 };
9060
9061 struct mlx5_ifc_destroy_lag_out_bits {
9062         u8         status[0x8];
9063         u8         reserved_at_8[0x18];
9064
9065         u8         syndrome[0x20];
9066
9067         u8         reserved_at_40[0x40];
9068 };
9069
9070 struct mlx5_ifc_destroy_lag_in_bits {
9071         u8         opcode[0x10];
9072         u8         reserved_at_10[0x10];
9073
9074         u8         reserved_at_20[0x10];
9075         u8         op_mod[0x10];
9076
9077         u8         reserved_at_40[0x40];
9078 };
9079
9080 struct mlx5_ifc_create_vport_lag_out_bits {
9081         u8         status[0x8];
9082         u8         reserved_at_8[0x18];
9083
9084         u8         syndrome[0x20];
9085
9086         u8         reserved_at_40[0x40];
9087 };
9088
9089 struct mlx5_ifc_create_vport_lag_in_bits {
9090         u8         opcode[0x10];
9091         u8         reserved_at_10[0x10];
9092
9093         u8         reserved_at_20[0x10];
9094         u8         op_mod[0x10];
9095
9096         u8         reserved_at_40[0x40];
9097 };
9098
9099 struct mlx5_ifc_destroy_vport_lag_out_bits {
9100         u8         status[0x8];
9101         u8         reserved_at_8[0x18];
9102
9103         u8         syndrome[0x20];
9104
9105         u8         reserved_at_40[0x40];
9106 };
9107
9108 struct mlx5_ifc_destroy_vport_lag_in_bits {
9109         u8         opcode[0x10];
9110         u8         reserved_at_10[0x10];
9111
9112         u8         reserved_at_20[0x10];
9113         u8         op_mod[0x10];
9114
9115         u8         reserved_at_40[0x40];
9116 };
9117
9118 struct mlx5_ifc_alloc_memic_in_bits {
9119         u8         opcode[0x10];
9120         u8         reserved_at_10[0x10];
9121
9122         u8         reserved_at_20[0x10];
9123         u8         op_mod[0x10];
9124
9125         u8         reserved_at_30[0x20];
9126
9127         u8         reserved_at_40[0x18];
9128         u8         log_memic_addr_alignment[0x8];
9129
9130         u8         range_start_addr[0x40];
9131
9132         u8         range_size[0x20];
9133
9134         u8         memic_size[0x20];
9135 };
9136
9137 struct mlx5_ifc_alloc_memic_out_bits {
9138         u8         status[0x8];
9139         u8         reserved_at_8[0x18];
9140
9141         u8         syndrome[0x20];
9142
9143         u8         memic_start_addr[0x40];
9144 };
9145
9146 struct mlx5_ifc_dealloc_memic_in_bits {
9147         u8         opcode[0x10];
9148         u8         reserved_at_10[0x10];
9149
9150         u8         reserved_at_20[0x10];
9151         u8         op_mod[0x10];
9152
9153         u8         reserved_at_40[0x40];
9154
9155         u8         memic_start_addr[0x40];
9156
9157         u8         memic_size[0x20];
9158
9159         u8         reserved_at_e0[0x20];
9160 };
9161
9162 struct mlx5_ifc_dealloc_memic_out_bits {
9163         u8         status[0x8];
9164         u8         reserved_at_8[0x18];
9165
9166         u8         syndrome[0x20];
9167
9168         u8         reserved_at_40[0x40];
9169 };
9170
9171 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9172         u8         opcode[0x10];
9173         u8         uid[0x10];
9174
9175         u8         reserved_at_20[0x10];
9176         u8         obj_type[0x10];
9177
9178         u8         obj_id[0x20];
9179
9180         u8         reserved_at_60[0x20];
9181 };
9182
9183 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9184         u8         status[0x8];
9185         u8         reserved_at_8[0x18];
9186
9187         u8         syndrome[0x20];
9188
9189         u8         obj_id[0x20];
9190
9191         u8         reserved_at_60[0x20];
9192 };
9193
9194 struct mlx5_ifc_umem_bits {
9195         u8         modify_field_select[0x40];
9196
9197         u8         reserved_at_40[0x5b];
9198         u8         log_page_size[0x5];
9199
9200         u8         page_offset[0x20];
9201
9202         u8         num_of_mtt[0x40];
9203
9204         struct mlx5_ifc_mtt_bits  mtt[0];
9205 };
9206
9207 struct mlx5_ifc_uctx_bits {
9208         u8         modify_field_select[0x40];
9209
9210         u8         reserved_at_40[0x1c0];
9211 };
9212
9213 struct mlx5_ifc_create_umem_in_bits {
9214         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9215         struct mlx5_ifc_umem_bits                     umem;
9216 };
9217
9218 struct mlx5_ifc_create_uctx_in_bits {
9219         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9220         struct mlx5_ifc_uctx_bits                     uctx;
9221 };
9222
9223 struct mlx5_ifc_mtrc_string_db_param_bits {
9224         u8         string_db_base_address[0x20];
9225
9226         u8         reserved_at_20[0x8];
9227         u8         string_db_size[0x18];
9228 };
9229
9230 struct mlx5_ifc_mtrc_cap_bits {
9231         u8         trace_owner[0x1];
9232         u8         trace_to_memory[0x1];
9233         u8         reserved_at_2[0x4];
9234         u8         trc_ver[0x2];
9235         u8         reserved_at_8[0x14];
9236         u8         num_string_db[0x4];
9237
9238         u8         first_string_trace[0x8];
9239         u8         num_string_trace[0x8];
9240         u8         reserved_at_30[0x28];
9241
9242         u8         log_max_trace_buffer_size[0x8];
9243
9244         u8         reserved_at_60[0x20];
9245
9246         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9247
9248         u8         reserved_at_280[0x180];
9249 };
9250
9251 struct mlx5_ifc_mtrc_conf_bits {
9252         u8         reserved_at_0[0x1c];
9253         u8         trace_mode[0x4];
9254         u8         reserved_at_20[0x18];
9255         u8         log_trace_buffer_size[0x8];
9256         u8         trace_mkey[0x20];
9257         u8         reserved_at_60[0x3a0];
9258 };
9259
9260 struct mlx5_ifc_mtrc_stdb_bits {
9261         u8         string_db_index[0x4];
9262         u8         reserved_at_4[0x4];
9263         u8         read_size[0x18];
9264         u8         start_offset[0x20];
9265         u8         string_db_data[0];
9266 };
9267
9268 struct mlx5_ifc_mtrc_ctrl_bits {
9269         u8         trace_status[0x2];
9270         u8         reserved_at_2[0x2];
9271         u8         arm_event[0x1];
9272         u8         reserved_at_5[0xb];
9273         u8         modify_field_select[0x10];
9274         u8         reserved_at_20[0x2b];
9275         u8         current_timestamp52_32[0x15];
9276         u8         current_timestamp31_0[0x20];
9277         u8         reserved_at_80[0x180];
9278 };
9279
9280 #endif /* MLX5_IFC_H */