include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77         MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
  78 };
  79
  80 enum {
  81         MLX5_SHARED_RESOURCE_UID = 0xffff,
  82 };
  83
  84 enum {
  85         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  86 };
  87
  88 enum {
  89         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  90         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  91         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  92 };
  93
  94 enum {
  95         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  96         MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
  97         MLX5_OBJ_TYPE_MKEY = 0xff01,
  98         MLX5_OBJ_TYPE_QP = 0xff02,
  99         MLX5_OBJ_TYPE_PSV = 0xff03,
 100         MLX5_OBJ_TYPE_RMP = 0xff04,
 101         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 102         MLX5_OBJ_TYPE_RQ = 0xff06,
 103         MLX5_OBJ_TYPE_SQ = 0xff07,
 104         MLX5_OBJ_TYPE_TIR = 0xff08,
 105         MLX5_OBJ_TYPE_TIS = 0xff09,
 106         MLX5_OBJ_TYPE_DCT = 0xff0a,
 107         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 108         MLX5_OBJ_TYPE_RQT = 0xff0e,
 109         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 110         MLX5_OBJ_TYPE_CQ = 0xff10,
 111 };
 112
 113 enum {
 114         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 115         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 116         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 117         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 118         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 119         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 120         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 121         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 122         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 123         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 124         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 125         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 126         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 127         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 128         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 129         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 130         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 131         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 132         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 133         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 134         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 135         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 136         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 137         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 138         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 139         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 140         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 141         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 142         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 143         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 144         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 145         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 146         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 147         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 148         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 149         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 150         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 151         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 152         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 153         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 154         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 155         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 156         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 157         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 158         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 159         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 160         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 161         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 162         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 163         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 164         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 165         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 166         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 167         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 168         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 169         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 170         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 171         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 172         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 173         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 174         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 175         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 176         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 177         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 178         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 179         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 180         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 181         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 182         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 183         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 184         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 185         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 186         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 187         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 188         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 189         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 190         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 191         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 192         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 193         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 194         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 195         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 196         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 197         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 198         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 199         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 200         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 201         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 202         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 203         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 204         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 205         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 206         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 207         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 208         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 209         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 210         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 211         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 212         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 213         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 214         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 215         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 216         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 217         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 218         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 219         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 220         MLX5_CMD_OP_NOP                           = 0x80d,
 221         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 222         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 223         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 224         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 225         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 226         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 227         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 228         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 229         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 230         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 231         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 232         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 233         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 234         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 235         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 236         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 237         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 238         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 239         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 240         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 241         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 242         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 243         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 244         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 245         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 246         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 247         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 248         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 249         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 250         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 251         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 252         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 253         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 254         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 255         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 256         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 257         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 258         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 259         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 260         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 261         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 262         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 263         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 264         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 265         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 266         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 267         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 268         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 269         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 270         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 271         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 272         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 273         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 274         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 275         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 276         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 277         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 278         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 279         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 280         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 281         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 282         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 283         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 284         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 285         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 286         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 287         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 288         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 289         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 290         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 291         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 292         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 293         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 294         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 295         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 296         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 297         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 298         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 299         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 300         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 301         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 302         MLX5_CMD_OP_MAX
 303 };
 304
 305 /* Valid range for general commands that don't work over an object */
 306 enum {
 307         MLX5_CMD_OP_GENERAL_START = 0xb00,
 308         MLX5_CMD_OP_GENERAL_END = 0xd00,
 309 };
 310
 311 struct mlx5_ifc_flow_table_fields_supported_bits {
 312         u8         outer_dmac[0x1];
 313         u8         outer_smac[0x1];
 314         u8         outer_ether_type[0x1];
 315         u8         outer_ip_version[0x1];
 316         u8         outer_first_prio[0x1];
 317         u8         outer_first_cfi[0x1];
 318         u8         outer_first_vid[0x1];
 319         u8         outer_ipv4_ttl[0x1];
 320         u8         outer_second_prio[0x1];
 321         u8         outer_second_cfi[0x1];
 322         u8         outer_second_vid[0x1];
 323         u8         reserved_at_b[0x1];
 324         u8         outer_sip[0x1];
 325         u8         outer_dip[0x1];
 326         u8         outer_frag[0x1];
 327         u8         outer_ip_protocol[0x1];
 328         u8         outer_ip_ecn[0x1];
 329         u8         outer_ip_dscp[0x1];
 330         u8         outer_udp_sport[0x1];
 331         u8         outer_udp_dport[0x1];
 332         u8         outer_tcp_sport[0x1];
 333         u8         outer_tcp_dport[0x1];
 334         u8         outer_tcp_flags[0x1];
 335         u8         outer_gre_protocol[0x1];
 336         u8         outer_gre_key[0x1];
 337         u8         outer_vxlan_vni[0x1];
 338         u8         outer_geneve_vni[0x1];
 339         u8         outer_geneve_oam[0x1];
 340         u8         outer_geneve_protocol_type[0x1];
 341         u8         outer_geneve_opt_len[0x1];
 342         u8         reserved_at_1e[0x1];
 343         u8         source_eswitch_port[0x1];
 344
 345         u8         inner_dmac[0x1];
 346         u8         inner_smac[0x1];
 347         u8         inner_ether_type[0x1];
 348         u8         inner_ip_version[0x1];
 349         u8         inner_first_prio[0x1];
 350         u8         inner_first_cfi[0x1];
 351         u8         inner_first_vid[0x1];
 352         u8         reserved_at_27[0x1];
 353         u8         inner_second_prio[0x1];
 354         u8         inner_second_cfi[0x1];
 355         u8         inner_second_vid[0x1];
 356         u8         reserved_at_2b[0x1];
 357         u8         inner_sip[0x1];
 358         u8         inner_dip[0x1];
 359         u8         inner_frag[0x1];
 360         u8         inner_ip_protocol[0x1];
 361         u8         inner_ip_ecn[0x1];
 362         u8         inner_ip_dscp[0x1];
 363         u8         inner_udp_sport[0x1];
 364         u8         inner_udp_dport[0x1];
 365         u8         inner_tcp_sport[0x1];
 366         u8         inner_tcp_dport[0x1];
 367         u8         inner_tcp_flags[0x1];
 368         u8         reserved_at_37[0x9];
 369
 370         u8         geneve_tlv_option_0_data[0x1];
 371         u8         reserved_at_41[0x4];
 372         u8         outer_first_mpls_over_udp[0x4];
 373         u8         outer_first_mpls_over_gre[0x4];
 374         u8         inner_first_mpls[0x4];
 375         u8         outer_first_mpls[0x4];
 376         u8         reserved_at_55[0x2];
 377         u8         outer_esp_spi[0x1];
 378         u8         reserved_at_58[0x2];
 379         u8         bth_dst_qp[0x1];
 380         u8         reserved_at_5b[0x5];
 381
 382         u8         reserved_at_60[0x18];
 383         u8         metadata_reg_c_7[0x1];
 384         u8         metadata_reg_c_6[0x1];
 385         u8         metadata_reg_c_5[0x1];
 386         u8         metadata_reg_c_4[0x1];
 387         u8         metadata_reg_c_3[0x1];
 388         u8         metadata_reg_c_2[0x1];
 389         u8         metadata_reg_c_1[0x1];
 390         u8         metadata_reg_c_0[0x1];
 391 };
 392
 393 struct mlx5_ifc_flow_table_prop_layout_bits {
 394         u8         ft_support[0x1];
 395         u8         reserved_at_1[0x1];
 396         u8         flow_counter[0x1];
 397         u8         flow_modify_en[0x1];
 398         u8         modify_root[0x1];
 399         u8         identified_miss_table_mode[0x1];
 400         u8         flow_table_modify[0x1];
 401         u8         reformat[0x1];
 402         u8         decap[0x1];
 403         u8         reserved_at_9[0x1];
 404         u8         pop_vlan[0x1];
 405         u8         push_vlan[0x1];
 406         u8         reserved_at_c[0x1];
 407         u8         pop_vlan_2[0x1];
 408         u8         push_vlan_2[0x1];
 409         u8         reformat_and_vlan_action[0x1];
 410         u8         reserved_at_10[0x1];
 411         u8         sw_owner[0x1];
 412         u8         reformat_l3_tunnel_to_l2[0x1];
 413         u8         reformat_l2_to_l3_tunnel[0x1];
 414         u8         reformat_and_modify_action[0x1];
 415         u8         ignore_flow_level[0x1];
 416         u8         reserved_at_16[0x1];
 417         u8         table_miss_action_domain[0x1];
 418         u8         termination_table[0x1];
 419         u8         reformat_and_fwd_to_table[0x1];
 420         u8         reserved_at_1a[0x2];
 421         u8         ipsec_encrypt[0x1];
 422         u8         ipsec_decrypt[0x1];
 423         u8         sw_owner_v2[0x1];
 424         u8         reserved_at_1f[0x1];
 425
 426         u8         termination_table_raw_traffic[0x1];
 427         u8         reserved_at_21[0x1];
 428         u8         log_max_ft_size[0x6];
 429         u8         log_max_modify_header_context[0x8];
 430         u8         max_modify_header_actions[0x8];
 431         u8         max_ft_level[0x8];
 432
 433         u8         reserved_at_40[0x20];
 434
 435         u8         reserved_at_60[0x18];
 436         u8         log_max_ft_num[0x8];
 437
 438         u8         reserved_at_80[0x18];
 439         u8         log_max_destination[0x8];
 440
 441         u8         log_max_flow_counter[0x8];
 442         u8         reserved_at_a8[0x10];
 443         u8         log_max_flow[0x8];
 444
 445         u8         reserved_at_c0[0x40];
 446
 447         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 448
 449         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 450 };
 451
 452 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 453         u8         send[0x1];
 454         u8         receive[0x1];
 455         u8         write[0x1];
 456         u8         read[0x1];
 457         u8         atomic[0x1];
 458         u8         srq_receive[0x1];
 459         u8         reserved_at_6[0x1a];
 460 };
 461
 462 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 463         u8         smac_47_16[0x20];
 464
 465         u8         smac_15_0[0x10];
 466         u8         ethertype[0x10];
 467
 468         u8         dmac_47_16[0x20];
 469
 470         u8         dmac_15_0[0x10];
 471         u8         first_prio[0x3];
 472         u8         first_cfi[0x1];
 473         u8         first_vid[0xc];
 474
 475         u8         ip_protocol[0x8];
 476         u8         ip_dscp[0x6];
 477         u8         ip_ecn[0x2];
 478         u8         cvlan_tag[0x1];
 479         u8         svlan_tag[0x1];
 480         u8         frag[0x1];
 481         u8         ip_version[0x4];
 482         u8         tcp_flags[0x9];
 483
 484         u8         tcp_sport[0x10];
 485         u8         tcp_dport[0x10];
 486
 487         u8         reserved_at_c0[0x18];
 488         u8         ttl_hoplimit[0x8];
 489
 490         u8         udp_sport[0x10];
 491         u8         udp_dport[0x10];
 492
 493         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 494
 495         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 496 };
 497
 498 struct mlx5_ifc_nvgre_key_bits {
 499         u8 hi[0x18];
 500         u8 lo[0x8];
 501 };
 502
 503 union mlx5_ifc_gre_key_bits {
 504         struct mlx5_ifc_nvgre_key_bits nvgre;
 505         u8 key[0x20];
 506 };
 507
 508 struct mlx5_ifc_fte_match_set_misc_bits {
 509         u8         gre_c_present[0x1];
 510         u8         reserved_at_1[0x1];
 511         u8         gre_k_present[0x1];
 512         u8         gre_s_present[0x1];
 513         u8         source_vhca_port[0x4];
 514         u8         source_sqn[0x18];
 515
 516         u8         source_eswitch_owner_vhca_id[0x10];
 517         u8         source_port[0x10];
 518
 519         u8         outer_second_prio[0x3];
 520         u8         outer_second_cfi[0x1];
 521         u8         outer_second_vid[0xc];
 522         u8         inner_second_prio[0x3];
 523         u8         inner_second_cfi[0x1];
 524         u8         inner_second_vid[0xc];
 525
 526         u8         outer_second_cvlan_tag[0x1];
 527         u8         inner_second_cvlan_tag[0x1];
 528         u8         outer_second_svlan_tag[0x1];
 529         u8         inner_second_svlan_tag[0x1];
 530         u8         reserved_at_64[0xc];
 531         u8         gre_protocol[0x10];
 532
 533         union mlx5_ifc_gre_key_bits gre_key;
 534
 535         u8         vxlan_vni[0x18];
 536         u8         reserved_at_b8[0x8];
 537
 538         u8         geneve_vni[0x18];
 539         u8         reserved_at_d8[0x7];
 540         u8         geneve_oam[0x1];
 541
 542         u8         reserved_at_e0[0xc];
 543         u8         outer_ipv6_flow_label[0x14];
 544
 545         u8         reserved_at_100[0xc];
 546         u8         inner_ipv6_flow_label[0x14];
 547
 548         u8         reserved_at_120[0xa];
 549         u8         geneve_opt_len[0x6];
 550         u8         geneve_protocol_type[0x10];
 551
 552         u8         reserved_at_140[0x8];
 553         u8         bth_dst_qp[0x18];
 554         u8         reserved_at_160[0x20];
 555         u8         outer_esp_spi[0x20];
 556         u8         reserved_at_1a0[0x60];
 557 };
 558
 559 struct mlx5_ifc_fte_match_mpls_bits {
 560         u8         mpls_label[0x14];
 561         u8         mpls_exp[0x3];
 562         u8         mpls_s_bos[0x1];
 563         u8         mpls_ttl[0x8];
 564 };
 565
 566 struct mlx5_ifc_fte_match_set_misc2_bits {
 567         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 568
 569         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 570
 571         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 572
 573         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 574
 575         u8         metadata_reg_c_7[0x20];
 576
 577         u8         metadata_reg_c_6[0x20];
 578
 579         u8         metadata_reg_c_5[0x20];
 580
 581         u8         metadata_reg_c_4[0x20];
 582
 583         u8         metadata_reg_c_3[0x20];
 584
 585         u8         metadata_reg_c_2[0x20];
 586
 587         u8         metadata_reg_c_1[0x20];
 588
 589         u8         metadata_reg_c_0[0x20];
 590
 591         u8         metadata_reg_a[0x20];
 592
 593         u8         reserved_at_1a0[0x60];
 594 };
 595
 596 struct mlx5_ifc_fte_match_set_misc3_bits {
 597         u8         inner_tcp_seq_num[0x20];
 598
 599         u8         outer_tcp_seq_num[0x20];
 600
 601         u8         inner_tcp_ack_num[0x20];
 602
 603         u8         outer_tcp_ack_num[0x20];
 604
 605         u8         reserved_at_80[0x8];
 606         u8         outer_vxlan_gpe_vni[0x18];
 607
 608         u8         outer_vxlan_gpe_next_protocol[0x8];
 609         u8         outer_vxlan_gpe_flags[0x8];
 610         u8         reserved_at_b0[0x10];
 611
 612         u8         icmp_header_data[0x20];
 613
 614         u8         icmpv6_header_data[0x20];
 615
 616         u8         icmp_type[0x8];
 617         u8         icmp_code[0x8];
 618         u8         icmpv6_type[0x8];
 619         u8         icmpv6_code[0x8];
 620
 621         u8         geneve_tlv_option_0_data[0x20];
 622
 623         u8         reserved_at_140[0xc0];
 624 };
 625
 626 struct mlx5_ifc_cmd_pas_bits {
 627         u8         pa_h[0x20];
 628
 629         u8         pa_l[0x14];
 630         u8         reserved_at_34[0xc];
 631 };
 632
 633 struct mlx5_ifc_uint64_bits {
 634         u8         hi[0x20];
 635
 636         u8         lo[0x20];
 637 };
 638
 639 enum {
 640         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 641         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 642         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 643         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 644         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 645         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 646         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 647         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 648         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 649         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 650 };
 651
 652 struct mlx5_ifc_ads_bits {
 653         u8         fl[0x1];
 654         u8         free_ar[0x1];
 655         u8         reserved_at_2[0xe];
 656         u8         pkey_index[0x10];
 657
 658         u8         reserved_at_20[0x8];
 659         u8         grh[0x1];
 660         u8         mlid[0x7];
 661         u8         rlid[0x10];
 662
 663         u8         ack_timeout[0x5];
 664         u8         reserved_at_45[0x3];
 665         u8         src_addr_index[0x8];
 666         u8         reserved_at_50[0x4];
 667         u8         stat_rate[0x4];
 668         u8         hop_limit[0x8];
 669
 670         u8         reserved_at_60[0x4];
 671         u8         tclass[0x8];
 672         u8         flow_label[0x14];
 673
 674         u8         rgid_rip[16][0x8];
 675
 676         u8         reserved_at_100[0x4];
 677         u8         f_dscp[0x1];
 678         u8         f_ecn[0x1];
 679         u8         reserved_at_106[0x1];
 680         u8         f_eth_prio[0x1];
 681         u8         ecn[0x2];
 682         u8         dscp[0x6];
 683         u8         udp_sport[0x10];
 684
 685         u8         dei_cfi[0x1];
 686         u8         eth_prio[0x3];
 687         u8         sl[0x4];
 688         u8         vhca_port_num[0x8];
 689         u8         rmac_47_32[0x10];
 690
 691         u8         rmac_31_0[0x20];
 692 };
 693
 694 struct mlx5_ifc_flow_table_nic_cap_bits {
 695         u8         nic_rx_multi_path_tirs[0x1];
 696         u8         nic_rx_multi_path_tirs_fts[0x1];
 697         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 698         u8         reserved_at_3[0x4];
 699         u8         sw_owner_reformat_supported[0x1];
 700         u8         reserved_at_8[0x18];
 701
 702         u8         encap_general_header[0x1];
 703         u8         reserved_at_21[0xa];
 704         u8         log_max_packet_reformat_context[0x5];
 705         u8         reserved_at_30[0x6];
 706         u8         max_encap_header_size[0xa];
 707         u8         reserved_at_40[0x1c0];
 708
 709         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 710
 711         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 712
 713         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 714
 715         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 716
 717         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 718
 719         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 720
 721         u8         reserved_at_e00[0x1200];
 722
 723         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 724
 725         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 726
 727         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 728
 729         u8         reserved_at_20c0[0x5f40];
 730 };
 731
 732 enum {
 733         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 734         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 735         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 736         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 737         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 738         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 739         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 740         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 741 };
 742
 743 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 744         u8      fdb_to_vport_reg_c_id[0x8];
 745         u8      reserved_at_8[0xd];
 746         u8      fdb_modify_header_fwd_to_table[0x1];
 747         u8      reserved_at_16[0x1];
 748         u8      flow_source[0x1];
 749         u8      reserved_at_18[0x2];
 750         u8      multi_fdb_encap[0x1];
 751         u8      egress_acl_forward_to_vport[0x1];
 752         u8      fdb_multi_path_to_table[0x1];
 753         u8      reserved_at_1d[0x3];
 754
 755         u8      reserved_at_20[0x1e0];
 756
 757         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 758
 759         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 760
 761         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 762
 763         u8      reserved_at_800[0x1000];
 764
 765         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 766
 767         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 768
 769         u8      sw_steering_uplink_icm_address_rx[0x40];
 770
 771         u8      sw_steering_uplink_icm_address_tx[0x40];
 772
 773         u8      reserved_at_1900[0x6700];
 774 };
 775
 776 enum {
 777         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 778         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 779 };
 780
 781 struct mlx5_ifc_e_switch_cap_bits {
 782         u8         vport_svlan_strip[0x1];
 783         u8         vport_cvlan_strip[0x1];
 784         u8         vport_svlan_insert[0x1];
 785         u8         vport_cvlan_insert_if_not_exist[0x1];
 786         u8         vport_cvlan_insert_overwrite[0x1];
 787         u8         reserved_at_5[0x3];
 788         u8         esw_uplink_ingress_acl[0x1];
 789         u8         reserved_at_9[0x10];
 790         u8         esw_functions_changed[0x1];
 791         u8         reserved_at_1a[0x1];
 792         u8         ecpf_vport_exists[0x1];
 793         u8         counter_eswitch_affinity[0x1];
 794         u8         merged_eswitch[0x1];
 795         u8         nic_vport_node_guid_modify[0x1];
 796         u8         nic_vport_port_guid_modify[0x1];
 797
 798         u8         vxlan_encap_decap[0x1];
 799         u8         nvgre_encap_decap[0x1];
 800         u8         reserved_at_22[0x1];
 801         u8         log_max_fdb_encap_uplink[0x5];
 802         u8         reserved_at_21[0x3];
 803         u8         log_max_packet_reformat_context[0x5];
 804         u8         reserved_2b[0x6];
 805         u8         max_encap_header_size[0xa];
 806
 807         u8         reserved_at_40[0xb];
 808         u8         log_max_esw_sf[0x5];
 809         u8         esw_sf_base_id[0x10];
 810
 811         u8         reserved_at_60[0x7a0];
 812
 813 };
 814
 815 struct mlx5_ifc_qos_cap_bits {
 816         u8         packet_pacing[0x1];
 817         u8         esw_scheduling[0x1];
 818         u8         esw_bw_share[0x1];
 819         u8         esw_rate_limit[0x1];
 820         u8         reserved_at_4[0x1];
 821         u8         packet_pacing_burst_bound[0x1];
 822         u8         packet_pacing_typical_size[0x1];
 823         u8         reserved_at_7[0x4];
 824         u8         packet_pacing_uid[0x1];
 825         u8         reserved_at_c[0x14];
 826
 827         u8         reserved_at_20[0x20];
 828
 829         u8         packet_pacing_max_rate[0x20];
 830
 831         u8         packet_pacing_min_rate[0x20];
 832
 833         u8         reserved_at_80[0x10];
 834         u8         packet_pacing_rate_table_size[0x10];
 835
 836         u8         esw_element_type[0x10];
 837         u8         esw_tsar_type[0x10];
 838
 839         u8         reserved_at_c0[0x10];
 840         u8         max_qos_para_vport[0x10];
 841
 842         u8         max_tsar_bw_share[0x20];
 843
 844         u8         reserved_at_100[0x700];
 845 };
 846
 847 struct mlx5_ifc_debug_cap_bits {
 848         u8         core_dump_general[0x1];
 849         u8         core_dump_qp[0x1];
 850         u8         reserved_at_2[0x7];
 851         u8         resource_dump[0x1];
 852         u8         reserved_at_a[0x16];
 853
 854         u8         reserved_at_20[0x2];
 855         u8         stall_detect[0x1];
 856         u8         reserved_at_23[0x1d];
 857
 858         u8         reserved_at_40[0x7c0];
 859 };
 860
 861 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 862         u8         csum_cap[0x1];
 863         u8         vlan_cap[0x1];
 864         u8         lro_cap[0x1];
 865         u8         lro_psh_flag[0x1];
 866         u8         lro_time_stamp[0x1];
 867         u8         reserved_at_5[0x2];
 868         u8         wqe_vlan_insert[0x1];
 869         u8         self_lb_en_modifiable[0x1];
 870         u8         reserved_at_9[0x2];
 871         u8         max_lso_cap[0x5];
 872         u8         multi_pkt_send_wqe[0x2];
 873         u8         wqe_inline_mode[0x2];
 874         u8         rss_ind_tbl_cap[0x4];
 875         u8         reg_umr_sq[0x1];
 876         u8         scatter_fcs[0x1];
 877         u8         enhanced_multi_pkt_send_wqe[0x1];
 878         u8         tunnel_lso_const_out_ip_id[0x1];
 879         u8         reserved_at_1c[0x2];
 880         u8         tunnel_stateless_gre[0x1];
 881         u8         tunnel_stateless_vxlan[0x1];
 882
 883         u8         swp[0x1];
 884         u8         swp_csum[0x1];
 885         u8         swp_lso[0x1];
 886         u8         cqe_checksum_full[0x1];
 887         u8         tunnel_stateless_geneve_tx[0x1];
 888         u8         tunnel_stateless_mpls_over_udp[0x1];
 889         u8         tunnel_stateless_mpls_over_gre[0x1];
 890         u8         tunnel_stateless_vxlan_gpe[0x1];
 891         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
 892         u8         tunnel_stateless_ip_over_ip[0x1];
 893         u8         insert_trailer[0x1];
 894         u8         reserved_at_2b[0x5];
 895         u8         max_vxlan_udp_ports[0x8];
 896         u8         reserved_at_38[0x6];
 897         u8         max_geneve_opt_len[0x1];
 898         u8         tunnel_stateless_geneve_rx[0x1];
 899
 900         u8         reserved_at_40[0x10];
 901         u8         lro_min_mss_size[0x10];
 902
 903         u8         reserved_at_60[0x120];
 904
 905         u8         lro_timer_supported_periods[4][0x20];
 906
 907         u8         reserved_at_200[0x600];
 908 };
 909
 910 struct mlx5_ifc_roce_cap_bits {
 911         u8         roce_apm[0x1];
 912         u8         reserved_at_1[0x3];
 913         u8         sw_r_roce_src_udp_port[0x1];
 914         u8         reserved_at_5[0x1b];
 915
 916         u8         reserved_at_20[0x60];
 917
 918         u8         reserved_at_80[0xc];
 919         u8         l3_type[0x4];
 920         u8         reserved_at_90[0x8];
 921         u8         roce_version[0x8];
 922
 923         u8         reserved_at_a0[0x10];
 924         u8         r_roce_dest_udp_port[0x10];
 925
 926         u8         r_roce_max_src_udp_port[0x10];
 927         u8         r_roce_min_src_udp_port[0x10];
 928
 929         u8         reserved_at_e0[0x10];
 930         u8         roce_address_table_size[0x10];
 931
 932         u8         reserved_at_100[0x700];
 933 };
 934
 935 struct mlx5_ifc_sync_steering_in_bits {
 936         u8         opcode[0x10];
 937         u8         uid[0x10];
 938
 939         u8         reserved_at_20[0x10];
 940         u8         op_mod[0x10];
 941
 942         u8         reserved_at_40[0xc0];
 943 };
 944
 945 struct mlx5_ifc_sync_steering_out_bits {
 946         u8         status[0x8];
 947         u8         reserved_at_8[0x18];
 948
 949         u8         syndrome[0x20];
 950
 951         u8         reserved_at_40[0x40];
 952 };
 953
 954 struct mlx5_ifc_device_mem_cap_bits {
 955         u8         memic[0x1];
 956         u8         reserved_at_1[0x1f];
 957
 958         u8         reserved_at_20[0xb];
 959         u8         log_min_memic_alloc_size[0x5];
 960         u8         reserved_at_30[0x8];
 961         u8         log_max_memic_addr_alignment[0x8];
 962
 963         u8         memic_bar_start_addr[0x40];
 964
 965         u8         memic_bar_size[0x20];
 966
 967         u8         max_memic_size[0x20];
 968
 969         u8         steering_sw_icm_start_address[0x40];
 970
 971         u8         reserved_at_100[0x8];
 972         u8         log_header_modify_sw_icm_size[0x8];
 973         u8         reserved_at_110[0x2];
 974         u8         log_sw_icm_alloc_granularity[0x6];
 975         u8         log_steering_sw_icm_size[0x8];
 976
 977         u8         reserved_at_120[0x20];
 978
 979         u8         header_modify_sw_icm_start_address[0x40];
 980
 981         u8         reserved_at_180[0x680];
 982 };
 983
 984 struct mlx5_ifc_device_event_cap_bits {
 985         u8         user_affiliated_events[4][0x40];
 986
 987         u8         user_unaffiliated_events[4][0x40];
 988 };
 989
 990 struct mlx5_ifc_virtio_emulation_cap_bits {
 991         u8         desc_tunnel_offload_type[0x1];
 992         u8         eth_frame_offload_type[0x1];
 993         u8         virtio_version_1_0[0x1];
 994         u8         device_features_bits_mask[0xd];
 995         u8         event_mode[0x8];
 996         u8         virtio_queue_type[0x8];
 997
 998         u8         max_tunnel_desc[0x10];
 999         u8         reserved_at_30[0x3];
1000         u8         log_doorbell_stride[0x5];
1001         u8         reserved_at_38[0x3];
1002         u8         log_doorbell_bar_size[0x5];
1003
1004         u8         doorbell_bar_offset[0x40];
1005
1006         u8         max_emulated_devices[0x8];
1007         u8         max_num_virtio_queues[0x18];
1008
1009         u8         reserved_at_a0[0x60];
1010
1011         u8         umem_1_buffer_param_a[0x20];
1012
1013         u8         umem_1_buffer_param_b[0x20];
1014
1015         u8         umem_2_buffer_param_a[0x20];
1016
1017         u8         umem_2_buffer_param_b[0x20];
1018
1019         u8         umem_3_buffer_param_a[0x20];
1020
1021         u8         umem_3_buffer_param_b[0x20];
1022
1023         u8         reserved_at_1c0[0x640];
1024 };
1025
1026 enum {
1027         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1028         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1029         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1030         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1031         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1032         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1033         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1034         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1035         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1036 };
1037
1038 enum {
1039         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1040         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1041         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1042         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1043         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1044         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1045         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1046         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1047         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1048 };
1049
1050 struct mlx5_ifc_atomic_caps_bits {
1051         u8         reserved_at_0[0x40];
1052
1053         u8         atomic_req_8B_endianness_mode[0x2];
1054         u8         reserved_at_42[0x4];
1055         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1056
1057         u8         reserved_at_47[0x19];
1058
1059         u8         reserved_at_60[0x20];
1060
1061         u8         reserved_at_80[0x10];
1062         u8         atomic_operations[0x10];
1063
1064         u8         reserved_at_a0[0x10];
1065         u8         atomic_size_qp[0x10];
1066
1067         u8         reserved_at_c0[0x10];
1068         u8         atomic_size_dc[0x10];
1069
1070         u8         reserved_at_e0[0x720];
1071 };
1072
1073 struct mlx5_ifc_odp_cap_bits {
1074         u8         reserved_at_0[0x40];
1075
1076         u8         sig[0x1];
1077         u8         reserved_at_41[0x1f];
1078
1079         u8         reserved_at_60[0x20];
1080
1081         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1082
1083         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1084
1085         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1086
1087         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1088
1089         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1090
1091         u8         reserved_at_120[0x6E0];
1092 };
1093
1094 struct mlx5_ifc_calc_op {
1095         u8        reserved_at_0[0x10];
1096         u8        reserved_at_10[0x9];
1097         u8        op_swap_endianness[0x1];
1098         u8        op_min[0x1];
1099         u8        op_xor[0x1];
1100         u8        op_or[0x1];
1101         u8        op_and[0x1];
1102         u8        op_max[0x1];
1103         u8        op_add[0x1];
1104 };
1105
1106 struct mlx5_ifc_vector_calc_cap_bits {
1107         u8         calc_matrix[0x1];
1108         u8         reserved_at_1[0x1f];
1109         u8         reserved_at_20[0x8];
1110         u8         max_vec_count[0x8];
1111         u8         reserved_at_30[0xd];
1112         u8         max_chunk_size[0x3];
1113         struct mlx5_ifc_calc_op calc0;
1114         struct mlx5_ifc_calc_op calc1;
1115         struct mlx5_ifc_calc_op calc2;
1116         struct mlx5_ifc_calc_op calc3;
1117
1118         u8         reserved_at_c0[0x720];
1119 };
1120
1121 struct mlx5_ifc_tls_cap_bits {
1122         u8         tls_1_2_aes_gcm_128[0x1];
1123         u8         tls_1_3_aes_gcm_128[0x1];
1124         u8         tls_1_2_aes_gcm_256[0x1];
1125         u8         tls_1_3_aes_gcm_256[0x1];
1126         u8         reserved_at_4[0x1c];
1127
1128         u8         reserved_at_20[0x7e0];
1129 };
1130
1131 struct mlx5_ifc_ipsec_cap_bits {
1132         u8         ipsec_full_offload[0x1];
1133         u8         ipsec_crypto_offload[0x1];
1134         u8         ipsec_esn[0x1];
1135         u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1136         u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1137         u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1138         u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1139         u8         reserved_at_7[0x4];
1140         u8         log_max_ipsec_offload[0x5];
1141         u8         reserved_at_10[0x10];
1142
1143         u8         min_log_ipsec_full_replay_window[0x8];
1144         u8         max_log_ipsec_full_replay_window[0x8];
1145         u8         reserved_at_30[0x7d0];
1146 };
1147
1148 enum {
1149         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1150         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1151         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1152         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1153 };
1154
1155 enum {
1156         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1157         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1158 };
1159
1160 enum {
1161         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1162         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1163         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1164         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1165         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1166 };
1167
1168 enum {
1169         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1170         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1171         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1172         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1173         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1174         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1175 };
1176
1177 enum {
1178         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1179         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1180 };
1181
1182 enum {
1183         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1184         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1185         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1186 };
1187
1188 enum {
1189         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1190         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1191 };
1192
1193 enum {
1194         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1195         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1196         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1197 };
1198
1199 enum {
1200         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1201         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1202         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1203         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1204 };
1205
1206 enum {
1207         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1208         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1209 };
1210
1211 #define MLX5_FC_BULK_SIZE_FACTOR 128
1212
1213 enum mlx5_fc_bulk_alloc_bitmask {
1214         MLX5_FC_BULK_128   = (1 << 0),
1215         MLX5_FC_BULK_256   = (1 << 1),
1216         MLX5_FC_BULK_512   = (1 << 2),
1217         MLX5_FC_BULK_1024  = (1 << 3),
1218         MLX5_FC_BULK_2048  = (1 << 4),
1219         MLX5_FC_BULK_4096  = (1 << 5),
1220         MLX5_FC_BULK_8192  = (1 << 6),
1221         MLX5_FC_BULK_16384 = (1 << 7),
1222 };
1223
1224 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1225
1226 struct mlx5_ifc_cmd_hca_cap_bits {
1227         u8         reserved_at_0[0x30];
1228         u8         vhca_id[0x10];
1229
1230         u8         reserved_at_40[0x40];
1231
1232         u8         log_max_srq_sz[0x8];
1233         u8         log_max_qp_sz[0x8];
1234         u8         event_cap[0x1];
1235         u8         reserved_at_91[0x7];
1236         u8         prio_tag_required[0x1];
1237         u8         reserved_at_99[0x2];
1238         u8         log_max_qp[0x5];
1239
1240         u8         reserved_at_a0[0x3];
1241         u8         ece_support[0x1];
1242         u8         reserved_at_a4[0x7];
1243         u8         log_max_srq[0x5];
1244         u8         reserved_at_b0[0x10];
1245
1246         u8         max_sgl_for_optimized_performance[0x8];
1247         u8         log_max_cq_sz[0x8];
1248         u8         relaxed_ordering_write_umr[0x1];
1249         u8         relaxed_ordering_read_umr[0x1];
1250         u8         reserved_at_d2[0x7];
1251         u8         virtio_net_device_emualtion_manager[0x1];
1252         u8         virtio_blk_device_emualtion_manager[0x1];
1253         u8         log_max_cq[0x5];
1254
1255         u8         log_max_eq_sz[0x8];
1256         u8         relaxed_ordering_write[0x1];
1257         u8         relaxed_ordering_read[0x1];
1258         u8         log_max_mkey[0x6];
1259         u8         reserved_at_f0[0x8];
1260         u8         dump_fill_mkey[0x1];
1261         u8         reserved_at_f9[0x2];
1262         u8         fast_teardown[0x1];
1263         u8         log_max_eq[0x4];
1264
1265         u8         max_indirection[0x8];
1266         u8         fixed_buffer_size[0x1];
1267         u8         log_max_mrw_sz[0x7];
1268         u8         force_teardown[0x1];
1269         u8         reserved_at_111[0x1];
1270         u8         log_max_bsf_list_size[0x6];
1271         u8         umr_extended_translation_offset[0x1];
1272         u8         null_mkey[0x1];
1273         u8         log_max_klm_list_size[0x6];
1274
1275         u8         reserved_at_120[0xa];
1276         u8         log_max_ra_req_dc[0x6];
1277         u8         reserved_at_130[0xa];
1278         u8         log_max_ra_res_dc[0x6];
1279
1280         u8         reserved_at_140[0x6];
1281         u8         release_all_pages[0x1];
1282         u8         reserved_at_147[0x2];
1283         u8         roce_accl[0x1];
1284         u8         log_max_ra_req_qp[0x6];
1285         u8         reserved_at_150[0xa];
1286         u8         log_max_ra_res_qp[0x6];
1287
1288         u8         end_pad[0x1];
1289         u8         cc_query_allowed[0x1];
1290         u8         cc_modify_allowed[0x1];
1291         u8         start_pad[0x1];
1292         u8         cache_line_128byte[0x1];
1293         u8         reserved_at_165[0x4];
1294         u8         rts2rts_qp_counters_set_id[0x1];
1295         u8         reserved_at_16a[0x2];
1296         u8         vnic_env_int_rq_oob[0x1];
1297         u8         sbcam_reg[0x1];
1298         u8         reserved_at_16e[0x1];
1299         u8         qcam_reg[0x1];
1300         u8         gid_table_size[0x10];
1301
1302         u8         out_of_seq_cnt[0x1];
1303         u8         vport_counters[0x1];
1304         u8         retransmission_q_counters[0x1];
1305         u8         debug[0x1];
1306         u8         modify_rq_counter_set_id[0x1];
1307         u8         rq_delay_drop[0x1];
1308         u8         max_qp_cnt[0xa];
1309         u8         pkey_table_size[0x10];
1310
1311         u8         vport_group_manager[0x1];
1312         u8         vhca_group_manager[0x1];
1313         u8         ib_virt[0x1];
1314         u8         eth_virt[0x1];
1315         u8         vnic_env_queue_counters[0x1];
1316         u8         ets[0x1];
1317         u8         nic_flow_table[0x1];
1318         u8         eswitch_manager[0x1];
1319         u8         device_memory[0x1];
1320         u8         mcam_reg[0x1];
1321         u8         pcam_reg[0x1];
1322         u8         local_ca_ack_delay[0x5];
1323         u8         port_module_event[0x1];
1324         u8         enhanced_error_q_counters[0x1];
1325         u8         ports_check[0x1];
1326         u8         reserved_at_1b3[0x1];
1327         u8         disable_link_up[0x1];
1328         u8         beacon_led[0x1];
1329         u8         port_type[0x2];
1330         u8         num_ports[0x8];
1331
1332         u8         reserved_at_1c0[0x1];
1333         u8         pps[0x1];
1334         u8         pps_modify[0x1];
1335         u8         log_max_msg[0x5];
1336         u8         reserved_at_1c8[0x4];
1337         u8         max_tc[0x4];
1338         u8         temp_warn_event[0x1];
1339         u8         dcbx[0x1];
1340         u8         general_notification_event[0x1];
1341         u8         reserved_at_1d3[0x2];
1342         u8         fpga[0x1];
1343         u8         rol_s[0x1];
1344         u8         rol_g[0x1];
1345         u8         reserved_at_1d8[0x1];
1346         u8         wol_s[0x1];
1347         u8         wol_g[0x1];
1348         u8         wol_a[0x1];
1349         u8         wol_b[0x1];
1350         u8         wol_m[0x1];
1351         u8         wol_u[0x1];
1352         u8         wol_p[0x1];
1353
1354         u8         stat_rate_support[0x10];
1355         u8         reserved_at_1f0[0x1];
1356         u8         pci_sync_for_fw_update_event[0x1];
1357         u8         reserved_at_1f2[0x6];
1358         u8         init2_lag_tx_port_affinity[0x1];
1359         u8         reserved_at_1fa[0x3];
1360         u8         cqe_version[0x4];
1361
1362         u8         compact_address_vector[0x1];
1363         u8         striding_rq[0x1];
1364         u8         reserved_at_202[0x1];
1365         u8         ipoib_enhanced_offloads[0x1];
1366         u8         ipoib_basic_offloads[0x1];
1367         u8         reserved_at_205[0x1];
1368         u8         repeated_block_disabled[0x1];
1369         u8         umr_modify_entity_size_disabled[0x1];
1370         u8         umr_modify_atomic_disabled[0x1];
1371         u8         umr_indirect_mkey_disabled[0x1];
1372         u8         umr_fence[0x2];
1373         u8         dc_req_scat_data_cqe[0x1];
1374         u8         reserved_at_20d[0x2];
1375         u8         drain_sigerr[0x1];
1376         u8         cmdif_checksum[0x2];
1377         u8         sigerr_cqe[0x1];
1378         u8         reserved_at_213[0x1];
1379         u8         wq_signature[0x1];
1380         u8         sctr_data_cqe[0x1];
1381         u8         reserved_at_216[0x1];
1382         u8         sho[0x1];
1383         u8         tph[0x1];
1384         u8         rf[0x1];
1385         u8         dct[0x1];
1386         u8         qos[0x1];
1387         u8         eth_net_offloads[0x1];
1388         u8         roce[0x1];
1389         u8         atomic[0x1];
1390         u8         reserved_at_21f[0x1];
1391
1392         u8         cq_oi[0x1];
1393         u8         cq_resize[0x1];
1394         u8         cq_moderation[0x1];
1395         u8         reserved_at_223[0x3];
1396         u8         cq_eq_remap[0x1];
1397         u8         pg[0x1];
1398         u8         block_lb_mc[0x1];
1399         u8         reserved_at_229[0x1];
1400         u8         scqe_break_moderation[0x1];
1401         u8         cq_period_start_from_cqe[0x1];
1402         u8         cd[0x1];
1403         u8         reserved_at_22d[0x1];
1404         u8         apm[0x1];
1405         u8         vector_calc[0x1];
1406         u8         umr_ptr_rlky[0x1];
1407         u8         imaicl[0x1];
1408         u8         qp_packet_based[0x1];
1409         u8         reserved_at_233[0x3];
1410         u8         qkv[0x1];
1411         u8         pkv[0x1];
1412         u8         set_deth_sqpn[0x1];
1413         u8         reserved_at_239[0x3];
1414         u8         xrc[0x1];
1415         u8         ud[0x1];
1416         u8         uc[0x1];
1417         u8         rc[0x1];
1418
1419         u8         uar_4k[0x1];
1420         u8         reserved_at_241[0x9];
1421         u8         uar_sz[0x6];
1422         u8         reserved_at_250[0x8];
1423         u8         log_pg_sz[0x8];
1424
1425         u8         bf[0x1];
1426         u8         driver_version[0x1];
1427         u8         pad_tx_eth_packet[0x1];
1428         u8         reserved_at_263[0x3];
1429         u8         mkey_by_name[0x1];
1430         u8         reserved_at_267[0x4];
1431
1432         u8         log_bf_reg_size[0x5];
1433
1434         u8         reserved_at_270[0x6];
1435         u8         lag_dct[0x2];
1436         u8         lag_tx_port_affinity[0x1];
1437         u8         reserved_at_279[0x2];
1438         u8         lag_master[0x1];
1439         u8         num_lag_ports[0x4];
1440
1441         u8         reserved_at_280[0x10];
1442         u8         max_wqe_sz_sq[0x10];
1443
1444         u8         reserved_at_2a0[0x10];
1445         u8         max_wqe_sz_rq[0x10];
1446
1447         u8         max_flow_counter_31_16[0x10];
1448         u8         max_wqe_sz_sq_dc[0x10];
1449
1450         u8         reserved_at_2e0[0x7];
1451         u8         max_qp_mcg[0x19];
1452
1453         u8         reserved_at_300[0x10];
1454         u8         flow_counter_bulk_alloc[0x8];
1455         u8         log_max_mcg[0x8];
1456
1457         u8         reserved_at_320[0x3];
1458         u8         log_max_transport_domain[0x5];
1459         u8         reserved_at_328[0x3];
1460         u8         log_max_pd[0x5];
1461         u8         reserved_at_330[0xb];
1462         u8         log_max_xrcd[0x5];
1463
1464         u8         nic_receive_steering_discard[0x1];
1465         u8         receive_discard_vport_down[0x1];
1466         u8         transmit_discard_vport_down[0x1];
1467         u8         reserved_at_343[0x5];
1468         u8         log_max_flow_counter_bulk[0x8];
1469         u8         max_flow_counter_15_0[0x10];
1470
1471
1472         u8         reserved_at_360[0x3];
1473         u8         log_max_rq[0x5];
1474         u8         reserved_at_368[0x3];
1475         u8         log_max_sq[0x5];
1476         u8         reserved_at_370[0x3];
1477         u8         log_max_tir[0x5];
1478         u8         reserved_at_378[0x3];
1479         u8         log_max_tis[0x5];
1480
1481         u8         basic_cyclic_rcv_wqe[0x1];
1482         u8         reserved_at_381[0x2];
1483         u8         log_max_rmp[0x5];
1484         u8         reserved_at_388[0x3];
1485         u8         log_max_rqt[0x5];
1486         u8         reserved_at_390[0x3];
1487         u8         log_max_rqt_size[0x5];
1488         u8         reserved_at_398[0x3];
1489         u8         log_max_tis_per_sq[0x5];
1490
1491         u8         ext_stride_num_range[0x1];
1492         u8         reserved_at_3a1[0x2];
1493         u8         log_max_stride_sz_rq[0x5];
1494         u8         reserved_at_3a8[0x3];
1495         u8         log_min_stride_sz_rq[0x5];
1496         u8         reserved_at_3b0[0x3];
1497         u8         log_max_stride_sz_sq[0x5];
1498         u8         reserved_at_3b8[0x3];
1499         u8         log_min_stride_sz_sq[0x5];
1500
1501         u8         hairpin[0x1];
1502         u8         reserved_at_3c1[0x2];
1503         u8         log_max_hairpin_queues[0x5];
1504         u8         reserved_at_3c8[0x3];
1505         u8         log_max_hairpin_wq_data_sz[0x5];
1506         u8         reserved_at_3d0[0x3];
1507         u8         log_max_hairpin_num_packets[0x5];
1508         u8         reserved_at_3d8[0x3];
1509         u8         log_max_wq_sz[0x5];
1510
1511         u8         nic_vport_change_event[0x1];
1512         u8         disable_local_lb_uc[0x1];
1513         u8         disable_local_lb_mc[0x1];
1514         u8         log_min_hairpin_wq_data_sz[0x5];
1515         u8         reserved_at_3e8[0x3];
1516         u8         log_max_vlan_list[0x5];
1517         u8         reserved_at_3f0[0x3];
1518         u8         log_max_current_mc_list[0x5];
1519         u8         reserved_at_3f8[0x3];
1520         u8         log_max_current_uc_list[0x5];
1521
1522         u8         general_obj_types[0x40];
1523
1524         u8         reserved_at_440[0x20];
1525
1526         u8         reserved_at_460[0x3];
1527         u8         log_max_uctx[0x5];
1528         u8         reserved_at_468[0x2];
1529         u8         ipsec_offload[0x1];
1530         u8         log_max_umem[0x5];
1531         u8         max_num_eqs[0x10];
1532
1533         u8         reserved_at_480[0x1];
1534         u8         tls_tx[0x1];
1535         u8         tls_rx[0x1];
1536         u8         log_max_l2_table[0x5];
1537         u8         reserved_at_488[0x8];
1538         u8         log_uar_page_sz[0x10];
1539
1540         u8         reserved_at_4a0[0x20];
1541         u8         device_frequency_mhz[0x20];
1542         u8         device_frequency_khz[0x20];
1543
1544         u8         reserved_at_500[0x20];
1545         u8         num_of_uars_per_page[0x20];
1546
1547         u8         flex_parser_protocols[0x20];
1548
1549         u8         max_geneve_tlv_options[0x8];
1550         u8         reserved_at_568[0x3];
1551         u8         max_geneve_tlv_option_data_len[0x5];
1552         u8         reserved_at_570[0x10];
1553
1554         u8         reserved_at_580[0x33];
1555         u8         log_max_dek[0x5];
1556         u8         reserved_at_5b8[0x4];
1557         u8         mini_cqe_resp_stride_index[0x1];
1558         u8         cqe_128_always[0x1];
1559         u8         cqe_compression_128[0x1];
1560         u8         cqe_compression[0x1];
1561
1562         u8         cqe_compression_timeout[0x10];
1563         u8         cqe_compression_max_num[0x10];
1564
1565         u8         reserved_at_5e0[0x10];
1566         u8         tag_matching[0x1];
1567         u8         rndv_offload_rc[0x1];
1568         u8         rndv_offload_dc[0x1];
1569         u8         log_tag_matching_list_sz[0x5];
1570         u8         reserved_at_5f8[0x3];
1571         u8         log_max_xrq[0x5];
1572
1573         u8         affiliate_nic_vport_criteria[0x8];
1574         u8         native_port_num[0x8];
1575         u8         num_vhca_ports[0x8];
1576         u8         reserved_at_618[0x6];
1577         u8         sw_owner_id[0x1];
1578         u8         reserved_at_61f[0x1];
1579
1580         u8         max_num_of_monitor_counters[0x10];
1581         u8         num_ppcnt_monitor_counters[0x10];
1582
1583         u8         reserved_at_640[0x10];
1584         u8         num_q_monitor_counters[0x10];
1585
1586         u8         reserved_at_660[0x20];
1587
1588         u8         sf[0x1];
1589         u8         sf_set_partition[0x1];
1590         u8         reserved_at_682[0x1];
1591         u8         log_max_sf[0x5];
1592         u8         reserved_at_688[0x8];
1593         u8         log_min_sf_size[0x8];
1594         u8         max_num_sf_partitions[0x8];
1595
1596         u8         uctx_cap[0x20];
1597
1598         u8         reserved_at_6c0[0x4];
1599         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1600         u8         flex_parser_id_icmp_dw1[0x4];
1601         u8         flex_parser_id_icmp_dw0[0x4];
1602         u8         flex_parser_id_icmpv6_dw1[0x4];
1603         u8         flex_parser_id_icmpv6_dw0[0x4];
1604         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1605         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1606
1607         u8         reserved_at_6e0[0x10];
1608         u8         sf_base_id[0x10];
1609
1610         u8         reserved_at_700[0x80];
1611         u8         vhca_tunnel_commands[0x40];
1612         u8         reserved_at_7c0[0x40];
1613 };
1614
1615 enum mlx5_flow_destination_type {
1616         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1617         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1618         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1619
1620         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1621         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1622         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1623 };
1624
1625 enum mlx5_flow_table_miss_action {
1626         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1627         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1628         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1629 };
1630
1631 struct mlx5_ifc_dest_format_struct_bits {
1632         u8         destination_type[0x8];
1633         u8         destination_id[0x18];
1634
1635         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1636         u8         packet_reformat[0x1];
1637         u8         reserved_at_22[0xe];
1638         u8         destination_eswitch_owner_vhca_id[0x10];
1639 };
1640
1641 struct mlx5_ifc_flow_counter_list_bits {
1642         u8         flow_counter_id[0x20];
1643
1644         u8         reserved_at_20[0x20];
1645 };
1646
1647 struct mlx5_ifc_extended_dest_format_bits {
1648         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1649
1650         u8         packet_reformat_id[0x20];
1651
1652         u8         reserved_at_60[0x20];
1653 };
1654
1655 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1656         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1657         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1658 };
1659
1660 struct mlx5_ifc_fte_match_param_bits {
1661         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1662
1663         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1664
1665         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1666
1667         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1668
1669         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1670
1671         u8         reserved_at_a00[0x600];
1672 };
1673
1674 enum {
1675         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1676         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1677         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1678         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1679         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1680 };
1681
1682 struct mlx5_ifc_rx_hash_field_select_bits {
1683         u8         l3_prot_type[0x1];
1684         u8         l4_prot_type[0x1];
1685         u8         selected_fields[0x1e];
1686 };
1687
1688 enum {
1689         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1690         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1691 };
1692
1693 enum {
1694         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1695         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1696 };
1697
1698 struct mlx5_ifc_wq_bits {
1699         u8         wq_type[0x4];
1700         u8         wq_signature[0x1];
1701         u8         end_padding_mode[0x2];
1702         u8         cd_slave[0x1];
1703         u8         reserved_at_8[0x18];
1704
1705         u8         hds_skip_first_sge[0x1];
1706         u8         log2_hds_buf_size[0x3];
1707         u8         reserved_at_24[0x7];
1708         u8         page_offset[0x5];
1709         u8         lwm[0x10];
1710
1711         u8         reserved_at_40[0x8];
1712         u8         pd[0x18];
1713
1714         u8         reserved_at_60[0x8];
1715         u8         uar_page[0x18];
1716
1717         u8         dbr_addr[0x40];
1718
1719         u8         hw_counter[0x20];
1720
1721         u8         sw_counter[0x20];
1722
1723         u8         reserved_at_100[0xc];
1724         u8         log_wq_stride[0x4];
1725         u8         reserved_at_110[0x3];
1726         u8         log_wq_pg_sz[0x5];
1727         u8         reserved_at_118[0x3];
1728         u8         log_wq_sz[0x5];
1729
1730         u8         dbr_umem_valid[0x1];
1731         u8         wq_umem_valid[0x1];
1732         u8         reserved_at_122[0x1];
1733         u8         log_hairpin_num_packets[0x5];
1734         u8         reserved_at_128[0x3];
1735         u8         log_hairpin_data_sz[0x5];
1736
1737         u8         reserved_at_130[0x4];
1738         u8         log_wqe_num_of_strides[0x4];
1739         u8         two_byte_shift_en[0x1];
1740         u8         reserved_at_139[0x4];
1741         u8         log_wqe_stride_size[0x3];
1742
1743         u8         reserved_at_140[0x4c0];
1744
1745         struct mlx5_ifc_cmd_pas_bits pas[];
1746 };
1747
1748 struct mlx5_ifc_rq_num_bits {
1749         u8         reserved_at_0[0x8];
1750         u8         rq_num[0x18];
1751 };
1752
1753 struct mlx5_ifc_mac_address_layout_bits {
1754         u8         reserved_at_0[0x10];
1755         u8         mac_addr_47_32[0x10];
1756
1757         u8         mac_addr_31_0[0x20];
1758 };
1759
1760 struct mlx5_ifc_vlan_layout_bits {
1761         u8         reserved_at_0[0x14];
1762         u8         vlan[0x0c];
1763
1764         u8         reserved_at_20[0x20];
1765 };
1766
1767 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1768         u8         reserved_at_0[0xa0];
1769
1770         u8         min_time_between_cnps[0x20];
1771
1772         u8         reserved_at_c0[0x12];
1773         u8         cnp_dscp[0x6];
1774         u8         reserved_at_d8[0x4];
1775         u8         cnp_prio_mode[0x1];
1776         u8         cnp_802p_prio[0x3];
1777
1778         u8         reserved_at_e0[0x720];
1779 };
1780
1781 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1782         u8         reserved_at_0[0x60];
1783
1784         u8         reserved_at_60[0x4];
1785         u8         clamp_tgt_rate[0x1];
1786         u8         reserved_at_65[0x3];
1787         u8         clamp_tgt_rate_after_time_inc[0x1];
1788         u8         reserved_at_69[0x17];
1789
1790         u8         reserved_at_80[0x20];
1791
1792         u8         rpg_time_reset[0x20];
1793
1794         u8         rpg_byte_reset[0x20];
1795
1796         u8         rpg_threshold[0x20];
1797
1798         u8         rpg_max_rate[0x20];
1799
1800         u8         rpg_ai_rate[0x20];
1801
1802         u8         rpg_hai_rate[0x20];
1803
1804         u8         rpg_gd[0x20];
1805
1806         u8         rpg_min_dec_fac[0x20];
1807
1808         u8         rpg_min_rate[0x20];
1809
1810         u8         reserved_at_1c0[0xe0];
1811
1812         u8         rate_to_set_on_first_cnp[0x20];
1813
1814         u8         dce_tcp_g[0x20];
1815
1816         u8         dce_tcp_rtt[0x20];
1817
1818         u8         rate_reduce_monitor_period[0x20];
1819
1820         u8         reserved_at_320[0x20];
1821
1822         u8         initial_alpha_value[0x20];
1823
1824         u8         reserved_at_360[0x4a0];
1825 };
1826
1827 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1828         u8         reserved_at_0[0x80];
1829
1830         u8         rppp_max_rps[0x20];
1831
1832         u8         rpg_time_reset[0x20];
1833
1834         u8         rpg_byte_reset[0x20];
1835
1836         u8         rpg_threshold[0x20];
1837
1838         u8         rpg_max_rate[0x20];
1839
1840         u8         rpg_ai_rate[0x20];
1841
1842         u8         rpg_hai_rate[0x20];
1843
1844         u8         rpg_gd[0x20];
1845
1846         u8         rpg_min_dec_fac[0x20];
1847
1848         u8         rpg_min_rate[0x20];
1849
1850         u8         reserved_at_1c0[0x640];
1851 };
1852
1853 enum {
1854         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1855         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1856         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1857 };
1858
1859 struct mlx5_ifc_resize_field_select_bits {
1860         u8         resize_field_select[0x20];
1861 };
1862
1863 struct mlx5_ifc_resource_dump_bits {
1864         u8         more_dump[0x1];
1865         u8         inline_dump[0x1];
1866         u8         reserved_at_2[0xa];
1867         u8         seq_num[0x4];
1868         u8         segment_type[0x10];
1869
1870         u8         reserved_at_20[0x10];
1871         u8         vhca_id[0x10];
1872
1873         u8         index1[0x20];
1874
1875         u8         index2[0x20];
1876
1877         u8         num_of_obj1[0x10];
1878         u8         num_of_obj2[0x10];
1879
1880         u8         reserved_at_a0[0x20];
1881
1882         u8         device_opaque[0x40];
1883
1884         u8         mkey[0x20];
1885
1886         u8         size[0x20];
1887
1888         u8         address[0x40];
1889
1890         u8         inline_data[52][0x20];
1891 };
1892
1893 struct mlx5_ifc_resource_dump_menu_record_bits {
1894         u8         reserved_at_0[0x4];
1895         u8         num_of_obj2_supports_active[0x1];
1896         u8         num_of_obj2_supports_all[0x1];
1897         u8         must_have_num_of_obj2[0x1];
1898         u8         support_num_of_obj2[0x1];
1899         u8         num_of_obj1_supports_active[0x1];
1900         u8         num_of_obj1_supports_all[0x1];
1901         u8         must_have_num_of_obj1[0x1];
1902         u8         support_num_of_obj1[0x1];
1903         u8         must_have_index2[0x1];
1904         u8         support_index2[0x1];
1905         u8         must_have_index1[0x1];
1906         u8         support_index1[0x1];
1907         u8         segment_type[0x10];
1908
1909         u8         segment_name[4][0x20];
1910
1911         u8         index1_name[4][0x20];
1912
1913         u8         index2_name[4][0x20];
1914 };
1915
1916 struct mlx5_ifc_resource_dump_segment_header_bits {
1917         u8         length_dw[0x10];
1918         u8         segment_type[0x10];
1919 };
1920
1921 struct mlx5_ifc_resource_dump_command_segment_bits {
1922         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1923
1924         u8         segment_called[0x10];
1925         u8         vhca_id[0x10];
1926
1927         u8         index1[0x20];
1928
1929         u8         index2[0x20];
1930
1931         u8         num_of_obj1[0x10];
1932         u8         num_of_obj2[0x10];
1933 };
1934
1935 struct mlx5_ifc_resource_dump_error_segment_bits {
1936         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1937
1938         u8         reserved_at_20[0x10];
1939         u8         syndrome_id[0x10];
1940
1941         u8         reserved_at_40[0x40];
1942
1943         u8         error[8][0x20];
1944 };
1945
1946 struct mlx5_ifc_resource_dump_info_segment_bits {
1947         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1948
1949         u8         reserved_at_20[0x18];
1950         u8         dump_version[0x8];
1951
1952         u8         hw_version[0x20];
1953
1954         u8         fw_version[0x20];
1955 };
1956
1957 struct mlx5_ifc_resource_dump_menu_segment_bits {
1958         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1959
1960         u8         reserved_at_20[0x10];
1961         u8         num_of_records[0x10];
1962
1963         struct mlx5_ifc_resource_dump_menu_record_bits record[];
1964 };
1965
1966 struct mlx5_ifc_resource_dump_resource_segment_bits {
1967         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1968
1969         u8         reserved_at_20[0x20];
1970
1971         u8         index1[0x20];
1972
1973         u8         index2[0x20];
1974
1975         u8         payload[][0x20];
1976 };
1977
1978 struct mlx5_ifc_resource_dump_terminate_segment_bits {
1979         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1980 };
1981
1982 struct mlx5_ifc_menu_resource_dump_response_bits {
1983         struct mlx5_ifc_resource_dump_info_segment_bits info;
1984         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
1985         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
1986         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
1987 };
1988
1989 enum {
1990         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1991         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1992         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1993         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1994 };
1995
1996 struct mlx5_ifc_modify_field_select_bits {
1997         u8         modify_field_select[0x20];
1998 };
1999
2000 struct mlx5_ifc_field_select_r_roce_np_bits {
2001         u8         field_select_r_roce_np[0x20];
2002 };
2003
2004 struct mlx5_ifc_field_select_r_roce_rp_bits {
2005         u8         field_select_r_roce_rp[0x20];
2006 };
2007
2008 enum {
2009         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2010         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2011         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2012         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2013         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2014         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2015         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2016         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2017         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2018         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2019 };
2020
2021 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2022         u8         field_select_8021qaurp[0x20];
2023 };
2024
2025 struct mlx5_ifc_phys_layer_cntrs_bits {
2026         u8         time_since_last_clear_high[0x20];
2027
2028         u8         time_since_last_clear_low[0x20];
2029
2030         u8         symbol_errors_high[0x20];
2031
2032         u8         symbol_errors_low[0x20];
2033
2034         u8         sync_headers_errors_high[0x20];
2035
2036         u8         sync_headers_errors_low[0x20];
2037
2038         u8         edpl_bip_errors_lane0_high[0x20];
2039
2040         u8         edpl_bip_errors_lane0_low[0x20];
2041
2042         u8         edpl_bip_errors_lane1_high[0x20];
2043
2044         u8         edpl_bip_errors_lane1_low[0x20];
2045
2046         u8         edpl_bip_errors_lane2_high[0x20];
2047
2048         u8         edpl_bip_errors_lane2_low[0x20];
2049
2050         u8         edpl_bip_errors_lane3_high[0x20];
2051
2052         u8         edpl_bip_errors_lane3_low[0x20];
2053
2054         u8         fc_fec_corrected_blocks_lane0_high[0x20];
2055
2056         u8         fc_fec_corrected_blocks_lane0_low[0x20];
2057
2058         u8         fc_fec_corrected_blocks_lane1_high[0x20];
2059
2060         u8         fc_fec_corrected_blocks_lane1_low[0x20];
2061
2062         u8         fc_fec_corrected_blocks_lane2_high[0x20];
2063
2064         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2065
2066         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2067
2068         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2069
2070         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2071
2072         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2073
2074         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2075
2076         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2077
2078         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2079
2080         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2081
2082         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2083
2084         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2085
2086         u8         rs_fec_corrected_blocks_high[0x20];
2087
2088         u8         rs_fec_corrected_blocks_low[0x20];
2089
2090         u8         rs_fec_uncorrectable_blocks_high[0x20];
2091
2092         u8         rs_fec_uncorrectable_blocks_low[0x20];
2093
2094         u8         rs_fec_no_errors_blocks_high[0x20];
2095
2096         u8         rs_fec_no_errors_blocks_low[0x20];
2097
2098         u8         rs_fec_single_error_blocks_high[0x20];
2099
2100         u8         rs_fec_single_error_blocks_low[0x20];
2101
2102         u8         rs_fec_corrected_symbols_total_high[0x20];
2103
2104         u8         rs_fec_corrected_symbols_total_low[0x20];
2105
2106         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2107
2108         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2109
2110         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2111
2112         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2113
2114         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2115
2116         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2117
2118         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2119
2120         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2121
2122         u8         link_down_events[0x20];
2123
2124         u8         successful_recovery_events[0x20];
2125
2126         u8         reserved_at_640[0x180];
2127 };
2128
2129 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2130         u8         time_since_last_clear_high[0x20];
2131
2132         u8         time_since_last_clear_low[0x20];
2133
2134         u8         phy_received_bits_high[0x20];
2135
2136         u8         phy_received_bits_low[0x20];
2137
2138         u8         phy_symbol_errors_high[0x20];
2139
2140         u8         phy_symbol_errors_low[0x20];
2141
2142         u8         phy_corrected_bits_high[0x20];
2143
2144         u8         phy_corrected_bits_low[0x20];
2145
2146         u8         phy_corrected_bits_lane0_high[0x20];
2147
2148         u8         phy_corrected_bits_lane0_low[0x20];
2149
2150         u8         phy_corrected_bits_lane1_high[0x20];
2151
2152         u8         phy_corrected_bits_lane1_low[0x20];
2153
2154         u8         phy_corrected_bits_lane2_high[0x20];
2155
2156         u8         phy_corrected_bits_lane2_low[0x20];
2157
2158         u8         phy_corrected_bits_lane3_high[0x20];
2159
2160         u8         phy_corrected_bits_lane3_low[0x20];
2161
2162         u8         reserved_at_200[0x5c0];
2163 };
2164
2165 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2166         u8         symbol_error_counter[0x10];
2167
2168         u8         link_error_recovery_counter[0x8];
2169
2170         u8         link_downed_counter[0x8];
2171
2172         u8         port_rcv_errors[0x10];
2173
2174         u8         port_rcv_remote_physical_errors[0x10];
2175
2176         u8         port_rcv_switch_relay_errors[0x10];
2177
2178         u8         port_xmit_discards[0x10];
2179
2180         u8         port_xmit_constraint_errors[0x8];
2181
2182         u8         port_rcv_constraint_errors[0x8];
2183
2184         u8         reserved_at_70[0x8];
2185
2186         u8         link_overrun_errors[0x8];
2187
2188         u8         reserved_at_80[0x10];
2189
2190         u8         vl_15_dropped[0x10];
2191
2192         u8         reserved_at_a0[0x80];
2193
2194         u8         port_xmit_wait[0x20];
2195 };
2196
2197 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2198         u8         transmit_queue_high[0x20];
2199
2200         u8         transmit_queue_low[0x20];
2201
2202         u8         no_buffer_discard_uc_high[0x20];
2203
2204         u8         no_buffer_discard_uc_low[0x20];
2205
2206         u8         reserved_at_80[0x740];
2207 };
2208
2209 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2210         u8         wred_discard_high[0x20];
2211
2212         u8         wred_discard_low[0x20];
2213
2214         u8         ecn_marked_tc_high[0x20];
2215
2216         u8         ecn_marked_tc_low[0x20];
2217
2218         u8         reserved_at_80[0x740];
2219 };
2220
2221 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2222         u8         rx_octets_high[0x20];
2223
2224         u8         rx_octets_low[0x20];
2225
2226         u8         reserved_at_40[0xc0];
2227
2228         u8         rx_frames_high[0x20];
2229
2230         u8         rx_frames_low[0x20];
2231
2232         u8         tx_octets_high[0x20];
2233
2234         u8         tx_octets_low[0x20];
2235
2236         u8         reserved_at_180[0xc0];
2237
2238         u8         tx_frames_high[0x20];
2239
2240         u8         tx_frames_low[0x20];
2241
2242         u8         rx_pause_high[0x20];
2243
2244         u8         rx_pause_low[0x20];
2245
2246         u8         rx_pause_duration_high[0x20];
2247
2248         u8         rx_pause_duration_low[0x20];
2249
2250         u8         tx_pause_high[0x20];
2251
2252         u8         tx_pause_low[0x20];
2253
2254         u8         tx_pause_duration_high[0x20];
2255
2256         u8         tx_pause_duration_low[0x20];
2257
2258         u8         rx_pause_transition_high[0x20];
2259
2260         u8         rx_pause_transition_low[0x20];
2261
2262         u8         rx_discards_high[0x20];
2263
2264         u8         rx_discards_low[0x20];
2265
2266         u8         device_stall_minor_watermark_cnt_high[0x20];
2267
2268         u8         device_stall_minor_watermark_cnt_low[0x20];
2269
2270         u8         device_stall_critical_watermark_cnt_high[0x20];
2271
2272         u8         device_stall_critical_watermark_cnt_low[0x20];
2273
2274         u8         reserved_at_480[0x340];
2275 };
2276
2277 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2278         u8         port_transmit_wait_high[0x20];
2279
2280         u8         port_transmit_wait_low[0x20];
2281
2282         u8         reserved_at_40[0x100];
2283
2284         u8         rx_buffer_almost_full_high[0x20];
2285
2286         u8         rx_buffer_almost_full_low[0x20];
2287
2288         u8         rx_buffer_full_high[0x20];
2289
2290         u8         rx_buffer_full_low[0x20];
2291
2292         u8         rx_icrc_encapsulated_high[0x20];
2293
2294         u8         rx_icrc_encapsulated_low[0x20];
2295
2296         u8         reserved_at_200[0x5c0];
2297 };
2298
2299 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2300         u8         dot3stats_alignment_errors_high[0x20];
2301
2302         u8         dot3stats_alignment_errors_low[0x20];
2303
2304         u8         dot3stats_fcs_errors_high[0x20];
2305
2306         u8         dot3stats_fcs_errors_low[0x20];
2307
2308         u8         dot3stats_single_collision_frames_high[0x20];
2309
2310         u8         dot3stats_single_collision_frames_low[0x20];
2311
2312         u8         dot3stats_multiple_collision_frames_high[0x20];
2313
2314         u8         dot3stats_multiple_collision_frames_low[0x20];
2315
2316         u8         dot3stats_sqe_test_errors_high[0x20];
2317
2318         u8         dot3stats_sqe_test_errors_low[0x20];
2319
2320         u8         dot3stats_deferred_transmissions_high[0x20];
2321
2322         u8         dot3stats_deferred_transmissions_low[0x20];
2323
2324         u8         dot3stats_late_collisions_high[0x20];
2325
2326         u8         dot3stats_late_collisions_low[0x20];
2327
2328         u8         dot3stats_excessive_collisions_high[0x20];
2329
2330         u8         dot3stats_excessive_collisions_low[0x20];
2331
2332         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2333
2334         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2335
2336         u8         dot3stats_carrier_sense_errors_high[0x20];
2337
2338         u8         dot3stats_carrier_sense_errors_low[0x20];
2339
2340         u8         dot3stats_frame_too_longs_high[0x20];
2341
2342         u8         dot3stats_frame_too_longs_low[0x20];
2343
2344         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2345
2346         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2347
2348         u8         dot3stats_symbol_errors_high[0x20];
2349
2350         u8         dot3stats_symbol_errors_low[0x20];
2351
2352         u8         dot3control_in_unknown_opcodes_high[0x20];
2353
2354         u8         dot3control_in_unknown_opcodes_low[0x20];
2355
2356         u8         dot3in_pause_frames_high[0x20];
2357
2358         u8         dot3in_pause_frames_low[0x20];
2359
2360         u8         dot3out_pause_frames_high[0x20];
2361
2362         u8         dot3out_pause_frames_low[0x20];
2363
2364         u8         reserved_at_400[0x3c0];
2365 };
2366
2367 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2368         u8         ether_stats_drop_events_high[0x20];
2369
2370         u8         ether_stats_drop_events_low[0x20];
2371
2372         u8         ether_stats_octets_high[0x20];
2373
2374         u8         ether_stats_octets_low[0x20];
2375
2376         u8         ether_stats_pkts_high[0x20];
2377
2378         u8         ether_stats_pkts_low[0x20];
2379
2380         u8         ether_stats_broadcast_pkts_high[0x20];
2381
2382         u8         ether_stats_broadcast_pkts_low[0x20];
2383
2384         u8         ether_stats_multicast_pkts_high[0x20];
2385
2386         u8         ether_stats_multicast_pkts_low[0x20];
2387
2388         u8         ether_stats_crc_align_errors_high[0x20];
2389
2390         u8         ether_stats_crc_align_errors_low[0x20];
2391
2392         u8         ether_stats_undersize_pkts_high[0x20];
2393
2394         u8         ether_stats_undersize_pkts_low[0x20];
2395
2396         u8         ether_stats_oversize_pkts_high[0x20];
2397
2398         u8         ether_stats_oversize_pkts_low[0x20];
2399
2400         u8         ether_stats_fragments_high[0x20];
2401
2402         u8         ether_stats_fragments_low[0x20];
2403
2404         u8         ether_stats_jabbers_high[0x20];
2405
2406         u8         ether_stats_jabbers_low[0x20];
2407
2408         u8         ether_stats_collisions_high[0x20];
2409
2410         u8         ether_stats_collisions_low[0x20];
2411
2412         u8         ether_stats_pkts64octets_high[0x20];
2413
2414         u8         ether_stats_pkts64octets_low[0x20];
2415
2416         u8         ether_stats_pkts65to127octets_high[0x20];
2417
2418         u8         ether_stats_pkts65to127octets_low[0x20];
2419
2420         u8         ether_stats_pkts128to255octets_high[0x20];
2421
2422         u8         ether_stats_pkts128to255octets_low[0x20];
2423
2424         u8         ether_stats_pkts256to511octets_high[0x20];
2425
2426         u8         ether_stats_pkts256to511octets_low[0x20];
2427
2428         u8         ether_stats_pkts512to1023octets_high[0x20];
2429
2430         u8         ether_stats_pkts512to1023octets_low[0x20];
2431
2432         u8         ether_stats_pkts1024to1518octets_high[0x20];
2433
2434         u8         ether_stats_pkts1024to1518octets_low[0x20];
2435
2436         u8         ether_stats_pkts1519to2047octets_high[0x20];
2437
2438         u8         ether_stats_pkts1519to2047octets_low[0x20];
2439
2440         u8         ether_stats_pkts2048to4095octets_high[0x20];
2441
2442         u8         ether_stats_pkts2048to4095octets_low[0x20];
2443
2444         u8         ether_stats_pkts4096to8191octets_high[0x20];
2445
2446         u8         ether_stats_pkts4096to8191octets_low[0x20];
2447
2448         u8         ether_stats_pkts8192to10239octets_high[0x20];
2449
2450         u8         ether_stats_pkts8192to10239octets_low[0x20];
2451
2452         u8         reserved_at_540[0x280];
2453 };
2454
2455 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2456         u8         if_in_octets_high[0x20];
2457
2458         u8         if_in_octets_low[0x20];
2459
2460         u8         if_in_ucast_pkts_high[0x20];
2461
2462         u8         if_in_ucast_pkts_low[0x20];
2463
2464         u8         if_in_discards_high[0x20];
2465
2466         u8         if_in_discards_low[0x20];
2467
2468         u8         if_in_errors_high[0x20];
2469
2470         u8         if_in_errors_low[0x20];
2471
2472         u8         if_in_unknown_protos_high[0x20];
2473
2474         u8         if_in_unknown_protos_low[0x20];
2475
2476         u8         if_out_octets_high[0x20];
2477
2478         u8         if_out_octets_low[0x20];
2479
2480         u8         if_out_ucast_pkts_high[0x20];
2481
2482         u8         if_out_ucast_pkts_low[0x20];
2483
2484         u8         if_out_discards_high[0x20];
2485
2486         u8         if_out_discards_low[0x20];
2487
2488         u8         if_out_errors_high[0x20];
2489
2490         u8         if_out_errors_low[0x20];
2491
2492         u8         if_in_multicast_pkts_high[0x20];
2493
2494         u8         if_in_multicast_pkts_low[0x20];
2495
2496         u8         if_in_broadcast_pkts_high[0x20];
2497
2498         u8         if_in_broadcast_pkts_low[0x20];
2499
2500         u8         if_out_multicast_pkts_high[0x20];
2501
2502         u8         if_out_multicast_pkts_low[0x20];
2503
2504         u8         if_out_broadcast_pkts_high[0x20];
2505
2506         u8         if_out_broadcast_pkts_low[0x20];
2507
2508         u8         reserved_at_340[0x480];
2509 };
2510
2511 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2512         u8         a_frames_transmitted_ok_high[0x20];
2513
2514         u8         a_frames_transmitted_ok_low[0x20];
2515
2516         u8         a_frames_received_ok_high[0x20];
2517
2518         u8         a_frames_received_ok_low[0x20];
2519
2520         u8         a_frame_check_sequence_errors_high[0x20];
2521
2522         u8         a_frame_check_sequence_errors_low[0x20];
2523
2524         u8         a_alignment_errors_high[0x20];
2525
2526         u8         a_alignment_errors_low[0x20];
2527
2528         u8         a_octets_transmitted_ok_high[0x20];
2529
2530         u8         a_octets_transmitted_ok_low[0x20];
2531
2532         u8         a_octets_received_ok_high[0x20];
2533
2534         u8         a_octets_received_ok_low[0x20];
2535
2536         u8         a_multicast_frames_xmitted_ok_high[0x20];
2537
2538         u8         a_multicast_frames_xmitted_ok_low[0x20];
2539
2540         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2541
2542         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2543
2544         u8         a_multicast_frames_received_ok_high[0x20];
2545
2546         u8         a_multicast_frames_received_ok_low[0x20];
2547
2548         u8         a_broadcast_frames_received_ok_high[0x20];
2549
2550         u8         a_broadcast_frames_received_ok_low[0x20];
2551
2552         u8         a_in_range_length_errors_high[0x20];
2553
2554         u8         a_in_range_length_errors_low[0x20];
2555
2556         u8         a_out_of_range_length_field_high[0x20];
2557
2558         u8         a_out_of_range_length_field_low[0x20];
2559
2560         u8         a_frame_too_long_errors_high[0x20];
2561
2562         u8         a_frame_too_long_errors_low[0x20];
2563
2564         u8         a_symbol_error_during_carrier_high[0x20];
2565
2566         u8         a_symbol_error_during_carrier_low[0x20];
2567
2568         u8         a_mac_control_frames_transmitted_high[0x20];
2569
2570         u8         a_mac_control_frames_transmitted_low[0x20];
2571
2572         u8         a_mac_control_frames_received_high[0x20];
2573
2574         u8         a_mac_control_frames_received_low[0x20];
2575
2576         u8         a_unsupported_opcodes_received_high[0x20];
2577
2578         u8         a_unsupported_opcodes_received_low[0x20];
2579
2580         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2581
2582         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2583
2584         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2585
2586         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2587
2588         u8         reserved_at_4c0[0x300];
2589 };
2590
2591 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2592         u8         life_time_counter_high[0x20];
2593
2594         u8         life_time_counter_low[0x20];
2595
2596         u8         rx_errors[0x20];
2597
2598         u8         tx_errors[0x20];
2599
2600         u8         l0_to_recovery_eieos[0x20];
2601
2602         u8         l0_to_recovery_ts[0x20];
2603
2604         u8         l0_to_recovery_framing[0x20];
2605
2606         u8         l0_to_recovery_retrain[0x20];
2607
2608         u8         crc_error_dllp[0x20];
2609
2610         u8         crc_error_tlp[0x20];
2611
2612         u8         tx_overflow_buffer_pkt_high[0x20];
2613
2614         u8         tx_overflow_buffer_pkt_low[0x20];
2615
2616         u8         outbound_stalled_reads[0x20];
2617
2618         u8         outbound_stalled_writes[0x20];
2619
2620         u8         outbound_stalled_reads_events[0x20];
2621
2622         u8         outbound_stalled_writes_events[0x20];
2623
2624         u8         reserved_at_200[0x5c0];
2625 };
2626
2627 struct mlx5_ifc_cmd_inter_comp_event_bits {
2628         u8         command_completion_vector[0x20];
2629
2630         u8         reserved_at_20[0xc0];
2631 };
2632
2633 struct mlx5_ifc_stall_vl_event_bits {
2634         u8         reserved_at_0[0x18];
2635         u8         port_num[0x1];
2636         u8         reserved_at_19[0x3];
2637         u8         vl[0x4];
2638
2639         u8         reserved_at_20[0xa0];
2640 };
2641
2642 struct mlx5_ifc_db_bf_congestion_event_bits {
2643         u8         event_subtype[0x8];
2644         u8         reserved_at_8[0x8];
2645         u8         congestion_level[0x8];
2646         u8         reserved_at_18[0x8];
2647
2648         u8         reserved_at_20[0xa0];
2649 };
2650
2651 struct mlx5_ifc_gpio_event_bits {
2652         u8         reserved_at_0[0x60];
2653
2654         u8         gpio_event_hi[0x20];
2655
2656         u8         gpio_event_lo[0x20];
2657
2658         u8         reserved_at_a0[0x40];
2659 };
2660
2661 struct mlx5_ifc_port_state_change_event_bits {
2662         u8         reserved_at_0[0x40];
2663
2664         u8         port_num[0x4];
2665         u8         reserved_at_44[0x1c];
2666
2667         u8         reserved_at_60[0x80];
2668 };
2669
2670 struct mlx5_ifc_dropped_packet_logged_bits {
2671         u8         reserved_at_0[0xe0];
2672 };
2673
2674 enum {
2675         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2676         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2677 };
2678
2679 struct mlx5_ifc_cq_error_bits {
2680         u8         reserved_at_0[0x8];
2681         u8         cqn[0x18];
2682
2683         u8         reserved_at_20[0x20];
2684
2685         u8         reserved_at_40[0x18];
2686         u8         syndrome[0x8];
2687
2688         u8         reserved_at_60[0x80];
2689 };
2690
2691 struct mlx5_ifc_rdma_page_fault_event_bits {
2692         u8         bytes_committed[0x20];
2693
2694         u8         r_key[0x20];
2695
2696         u8         reserved_at_40[0x10];
2697         u8         packet_len[0x10];
2698
2699         u8         rdma_op_len[0x20];
2700
2701         u8         rdma_va[0x40];
2702
2703         u8         reserved_at_c0[0x5];
2704         u8         rdma[0x1];
2705         u8         write[0x1];
2706         u8         requestor[0x1];
2707         u8         qp_number[0x18];
2708 };
2709
2710 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2711         u8         bytes_committed[0x20];
2712
2713         u8         reserved_at_20[0x10];
2714         u8         wqe_index[0x10];
2715
2716         u8         reserved_at_40[0x10];
2717         u8         len[0x10];
2718
2719         u8         reserved_at_60[0x60];
2720
2721         u8         reserved_at_c0[0x5];
2722         u8         rdma[0x1];
2723         u8         write_read[0x1];
2724         u8         requestor[0x1];
2725         u8         qpn[0x18];
2726 };
2727
2728 struct mlx5_ifc_qp_events_bits {
2729         u8         reserved_at_0[0xa0];
2730
2731         u8         type[0x8];
2732         u8         reserved_at_a8[0x18];
2733
2734         u8         reserved_at_c0[0x8];
2735         u8         qpn_rqn_sqn[0x18];
2736 };
2737
2738 struct mlx5_ifc_dct_events_bits {
2739         u8         reserved_at_0[0xc0];
2740
2741         u8         reserved_at_c0[0x8];
2742         u8         dct_number[0x18];
2743 };
2744
2745 struct mlx5_ifc_comp_event_bits {
2746         u8         reserved_at_0[0xc0];
2747
2748         u8         reserved_at_c0[0x8];
2749         u8         cq_number[0x18];
2750 };
2751
2752 enum {
2753         MLX5_QPC_STATE_RST        = 0x0,
2754         MLX5_QPC_STATE_INIT       = 0x1,
2755         MLX5_QPC_STATE_RTR        = 0x2,
2756         MLX5_QPC_STATE_RTS        = 0x3,
2757         MLX5_QPC_STATE_SQER       = 0x4,
2758         MLX5_QPC_STATE_ERR        = 0x6,
2759         MLX5_QPC_STATE_SQD        = 0x7,
2760         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2761 };
2762
2763 enum {
2764         MLX5_QPC_ST_RC            = 0x0,
2765         MLX5_QPC_ST_UC            = 0x1,
2766         MLX5_QPC_ST_UD            = 0x2,
2767         MLX5_QPC_ST_XRC           = 0x3,
2768         MLX5_QPC_ST_DCI           = 0x5,
2769         MLX5_QPC_ST_QP0           = 0x7,
2770         MLX5_QPC_ST_QP1           = 0x8,
2771         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2772         MLX5_QPC_ST_REG_UMR       = 0xc,
2773 };
2774
2775 enum {
2776         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2777         MLX5_QPC_PM_STATE_REARM     = 0x1,
2778         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2779         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2780 };
2781
2782 enum {
2783         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2784 };
2785
2786 enum {
2787         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2788         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2789 };
2790
2791 enum {
2792         MLX5_QPC_MTU_256_BYTES        = 0x1,
2793         MLX5_QPC_MTU_512_BYTES        = 0x2,
2794         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2795         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2796         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2797         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2798 };
2799
2800 enum {
2801         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2802         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2803         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2804         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2805         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2806         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2807         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2808         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2809 };
2810
2811 enum {
2812         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2813         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2814         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2815 };
2816
2817 enum {
2818         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2819         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2820         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2821 };
2822
2823 struct mlx5_ifc_qpc_bits {
2824         u8         state[0x4];
2825         u8         lag_tx_port_affinity[0x4];
2826         u8         st[0x8];
2827         u8         reserved_at_10[0x3];
2828         u8         pm_state[0x2];
2829         u8         reserved_at_15[0x1];
2830         u8         req_e2e_credit_mode[0x2];
2831         u8         offload_type[0x4];
2832         u8         end_padding_mode[0x2];
2833         u8         reserved_at_1e[0x2];
2834
2835         u8         wq_signature[0x1];
2836         u8         block_lb_mc[0x1];
2837         u8         atomic_like_write_en[0x1];
2838         u8         latency_sensitive[0x1];
2839         u8         reserved_at_24[0x1];
2840         u8         drain_sigerr[0x1];
2841         u8         reserved_at_26[0x2];
2842         u8         pd[0x18];
2843
2844         u8         mtu[0x3];
2845         u8         log_msg_max[0x5];
2846         u8         reserved_at_48[0x1];
2847         u8         log_rq_size[0x4];
2848         u8         log_rq_stride[0x3];
2849         u8         no_sq[0x1];
2850         u8         log_sq_size[0x4];
2851         u8         reserved_at_55[0x6];
2852         u8         rlky[0x1];
2853         u8         ulp_stateless_offload_mode[0x4];
2854
2855         u8         counter_set_id[0x8];
2856         u8         uar_page[0x18];
2857
2858         u8         reserved_at_80[0x8];
2859         u8         user_index[0x18];
2860
2861         u8         reserved_at_a0[0x3];
2862         u8         log_page_size[0x5];
2863         u8         remote_qpn[0x18];
2864
2865         struct mlx5_ifc_ads_bits primary_address_path;
2866
2867         struct mlx5_ifc_ads_bits secondary_address_path;
2868
2869         u8         log_ack_req_freq[0x4];
2870         u8         reserved_at_384[0x4];
2871         u8         log_sra_max[0x3];
2872         u8         reserved_at_38b[0x2];
2873         u8         retry_count[0x3];
2874         u8         rnr_retry[0x3];
2875         u8         reserved_at_393[0x1];
2876         u8         fre[0x1];
2877         u8         cur_rnr_retry[0x3];
2878         u8         cur_retry_count[0x3];
2879         u8         reserved_at_39b[0x5];
2880
2881         u8         reserved_at_3a0[0x20];
2882
2883         u8         reserved_at_3c0[0x8];
2884         u8         next_send_psn[0x18];
2885
2886         u8         reserved_at_3e0[0x8];
2887         u8         cqn_snd[0x18];
2888
2889         u8         reserved_at_400[0x8];
2890         u8         deth_sqpn[0x18];
2891
2892         u8         reserved_at_420[0x20];
2893
2894         u8         reserved_at_440[0x8];
2895         u8         last_acked_psn[0x18];
2896
2897         u8         reserved_at_460[0x8];
2898         u8         ssn[0x18];
2899
2900         u8         reserved_at_480[0x8];
2901         u8         log_rra_max[0x3];
2902         u8         reserved_at_48b[0x1];
2903         u8         atomic_mode[0x4];
2904         u8         rre[0x1];
2905         u8         rwe[0x1];
2906         u8         rae[0x1];
2907         u8         reserved_at_493[0x1];
2908         u8         page_offset[0x6];
2909         u8         reserved_at_49a[0x3];
2910         u8         cd_slave_receive[0x1];
2911         u8         cd_slave_send[0x1];
2912         u8         cd_master[0x1];
2913
2914         u8         reserved_at_4a0[0x3];
2915         u8         min_rnr_nak[0x5];
2916         u8         next_rcv_psn[0x18];
2917
2918         u8         reserved_at_4c0[0x8];
2919         u8         xrcd[0x18];
2920
2921         u8         reserved_at_4e0[0x8];
2922         u8         cqn_rcv[0x18];
2923
2924         u8         dbr_addr[0x40];
2925
2926         u8         q_key[0x20];
2927
2928         u8         reserved_at_560[0x5];
2929         u8         rq_type[0x3];
2930         u8         srqn_rmpn_xrqn[0x18];
2931
2932         u8         reserved_at_580[0x8];
2933         u8         rmsn[0x18];
2934
2935         u8         hw_sq_wqebb_counter[0x10];
2936         u8         sw_sq_wqebb_counter[0x10];
2937
2938         u8         hw_rq_counter[0x20];
2939
2940         u8         sw_rq_counter[0x20];
2941
2942         u8         reserved_at_600[0x20];
2943
2944         u8         reserved_at_620[0xf];
2945         u8         cgs[0x1];
2946         u8         cs_req[0x8];
2947         u8         cs_res[0x8];
2948
2949         u8         dc_access_key[0x40];
2950
2951         u8         reserved_at_680[0x3];
2952         u8         dbr_umem_valid[0x1];
2953
2954         u8         reserved_at_684[0xbc];
2955 };
2956
2957 struct mlx5_ifc_roce_addr_layout_bits {
2958         u8         source_l3_address[16][0x8];
2959
2960         u8         reserved_at_80[0x3];
2961         u8         vlan_valid[0x1];
2962         u8         vlan_id[0xc];
2963         u8         source_mac_47_32[0x10];
2964
2965         u8         source_mac_31_0[0x20];
2966
2967         u8         reserved_at_c0[0x14];
2968         u8         roce_l3_type[0x4];
2969         u8         roce_version[0x8];
2970
2971         u8         reserved_at_e0[0x20];
2972 };
2973
2974 union mlx5_ifc_hca_cap_union_bits {
2975         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2976         struct mlx5_ifc_odp_cap_bits odp_cap;
2977         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2978         struct mlx5_ifc_roce_cap_bits roce_cap;
2979         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2980         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2981         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2982         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2983         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2984         struct mlx5_ifc_qos_cap_bits qos_cap;
2985         struct mlx5_ifc_debug_cap_bits debug_cap;
2986         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2987         struct mlx5_ifc_tls_cap_bits tls_cap;
2988         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2989         struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
2990         u8         reserved_at_0[0x8000];
2991 };
2992
2993 enum {
2994         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2995         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2996         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2997         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2998         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2999         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3000         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3001         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3002         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3003         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3004         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3005         MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3006         MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3007 };
3008
3009 enum {
3010         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3011         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3012         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3013 };
3014
3015 struct mlx5_ifc_vlan_bits {
3016         u8         ethtype[0x10];
3017         u8         prio[0x3];
3018         u8         cfi[0x1];
3019         u8         vid[0xc];
3020 };
3021
3022 struct mlx5_ifc_flow_context_bits {
3023         struct mlx5_ifc_vlan_bits push_vlan;
3024
3025         u8         group_id[0x20];
3026
3027         u8         reserved_at_40[0x8];
3028         u8         flow_tag[0x18];
3029
3030         u8         reserved_at_60[0x10];
3031         u8         action[0x10];
3032
3033         u8         extended_destination[0x1];
3034         u8         reserved_at_81[0x1];
3035         u8         flow_source[0x2];
3036         u8         reserved_at_84[0x4];
3037         u8         destination_list_size[0x18];
3038
3039         u8         reserved_at_a0[0x8];
3040         u8         flow_counter_list_size[0x18];
3041
3042         u8         packet_reformat_id[0x20];
3043
3044         u8         modify_header_id[0x20];
3045
3046         struct mlx5_ifc_vlan_bits push_vlan_2;
3047
3048         u8         ipsec_obj_id[0x20];
3049         u8         reserved_at_140[0xc0];
3050
3051         struct mlx5_ifc_fte_match_param_bits match_value;
3052
3053         u8         reserved_at_1200[0x600];
3054
3055         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3056 };
3057
3058 enum {
3059         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3060         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3061 };
3062
3063 struct mlx5_ifc_xrc_srqc_bits {
3064         u8         state[0x4];
3065         u8         log_xrc_srq_size[0x4];
3066         u8         reserved_at_8[0x18];
3067
3068         u8         wq_signature[0x1];
3069         u8         cont_srq[0x1];
3070         u8         reserved_at_22[0x1];
3071         u8         rlky[0x1];
3072         u8         basic_cyclic_rcv_wqe[0x1];
3073         u8         log_rq_stride[0x3];
3074         u8         xrcd[0x18];
3075
3076         u8         page_offset[0x6];
3077         u8         reserved_at_46[0x1];
3078         u8         dbr_umem_valid[0x1];
3079         u8         cqn[0x18];
3080
3081         u8         reserved_at_60[0x20];
3082
3083         u8         user_index_equal_xrc_srqn[0x1];
3084         u8         reserved_at_81[0x1];
3085         u8         log_page_size[0x6];
3086         u8         user_index[0x18];
3087
3088         u8         reserved_at_a0[0x20];
3089
3090         u8         reserved_at_c0[0x8];
3091         u8         pd[0x18];
3092
3093         u8         lwm[0x10];
3094         u8         wqe_cnt[0x10];
3095
3096         u8         reserved_at_100[0x40];
3097
3098         u8         db_record_addr_h[0x20];
3099
3100         u8         db_record_addr_l[0x1e];
3101         u8         reserved_at_17e[0x2];
3102
3103         u8         reserved_at_180[0x80];
3104 };
3105
3106 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3107         u8         counter_error_queues[0x20];
3108
3109         u8         total_error_queues[0x20];
3110
3111         u8         send_queue_priority_update_flow[0x20];
3112
3113         u8         reserved_at_60[0x20];
3114
3115         u8         nic_receive_steering_discard[0x40];
3116
3117         u8         receive_discard_vport_down[0x40];
3118
3119         u8         transmit_discard_vport_down[0x40];
3120
3121         u8         reserved_at_140[0xa0];
3122
3123         u8         internal_rq_out_of_buffer[0x20];
3124
3125         u8         reserved_at_200[0xe00];
3126 };
3127
3128 struct mlx5_ifc_traffic_counter_bits {
3129         u8         packets[0x40];
3130
3131         u8         octets[0x40];
3132 };
3133
3134 struct mlx5_ifc_tisc_bits {
3135         u8         strict_lag_tx_port_affinity[0x1];
3136         u8         tls_en[0x1];
3137         u8         reserved_at_2[0x2];
3138         u8         lag_tx_port_affinity[0x04];
3139
3140         u8         reserved_at_8[0x4];
3141         u8         prio[0x4];
3142         u8         reserved_at_10[0x10];
3143
3144         u8         reserved_at_20[0x100];
3145
3146         u8         reserved_at_120[0x8];
3147         u8         transport_domain[0x18];
3148
3149         u8         reserved_at_140[0x8];
3150         u8         underlay_qpn[0x18];
3151
3152         u8         reserved_at_160[0x8];
3153         u8         pd[0x18];
3154
3155         u8         reserved_at_180[0x380];
3156 };
3157
3158 enum {
3159         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3160         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3161 };
3162
3163 enum {
3164         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
3165         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
3166 };
3167
3168 enum {
3169         MLX5_RX_HASH_FN_NONE           = 0x0,
3170         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3171         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3172 };
3173
3174 enum {
3175         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3176         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3177 };
3178
3179 struct mlx5_ifc_tirc_bits {
3180         u8         reserved_at_0[0x20];
3181
3182         u8         disp_type[0x4];
3183         u8         tls_en[0x1];
3184         u8         reserved_at_25[0x1b];
3185
3186         u8         reserved_at_40[0x40];
3187
3188         u8         reserved_at_80[0x4];
3189         u8         lro_timeout_period_usecs[0x10];
3190         u8         lro_enable_mask[0x4];
3191         u8         lro_max_ip_payload_size[0x8];
3192
3193         u8         reserved_at_a0[0x40];
3194
3195         u8         reserved_at_e0[0x8];
3196         u8         inline_rqn[0x18];
3197
3198         u8         rx_hash_symmetric[0x1];
3199         u8         reserved_at_101[0x1];
3200         u8         tunneled_offload_en[0x1];
3201         u8         reserved_at_103[0x5];
3202         u8         indirect_table[0x18];
3203
3204         u8         rx_hash_fn[0x4];
3205         u8         reserved_at_124[0x2];
3206         u8         self_lb_block[0x2];
3207         u8         transport_domain[0x18];
3208
3209         u8         rx_hash_toeplitz_key[10][0x20];
3210
3211         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3212
3213         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3214
3215         u8         reserved_at_2c0[0x4c0];
3216 };
3217
3218 enum {
3219         MLX5_SRQC_STATE_GOOD   = 0x0,
3220         MLX5_SRQC_STATE_ERROR  = 0x1,
3221 };
3222
3223 struct mlx5_ifc_srqc_bits {
3224         u8         state[0x4];
3225         u8         log_srq_size[0x4];
3226         u8         reserved_at_8[0x18];
3227
3228         u8         wq_signature[0x1];
3229         u8         cont_srq[0x1];
3230         u8         reserved_at_22[0x1];
3231         u8         rlky[0x1];
3232         u8         reserved_at_24[0x1];
3233         u8         log_rq_stride[0x3];
3234         u8         xrcd[0x18];
3235
3236         u8         page_offset[0x6];
3237         u8         reserved_at_46[0x2];
3238         u8         cqn[0x18];
3239
3240         u8         reserved_at_60[0x20];
3241
3242         u8         reserved_at_80[0x2];
3243         u8         log_page_size[0x6];
3244         u8         reserved_at_88[0x18];
3245
3246         u8         reserved_at_a0[0x20];
3247
3248         u8         reserved_at_c0[0x8];
3249         u8         pd[0x18];
3250
3251         u8         lwm[0x10];
3252         u8         wqe_cnt[0x10];
3253
3254         u8         reserved_at_100[0x40];
3255
3256         u8         dbr_addr[0x40];
3257
3258         u8         reserved_at_180[0x80];
3259 };
3260
3261 enum {
3262         MLX5_SQC_STATE_RST  = 0x0,
3263         MLX5_SQC_STATE_RDY  = 0x1,
3264         MLX5_SQC_STATE_ERR  = 0x3,
3265 };
3266
3267 struct mlx5_ifc_sqc_bits {
3268         u8         rlky[0x1];
3269         u8         cd_master[0x1];
3270         u8         fre[0x1];
3271         u8         flush_in_error_en[0x1];
3272         u8         allow_multi_pkt_send_wqe[0x1];
3273         u8         min_wqe_inline_mode[0x3];
3274         u8         state[0x4];
3275         u8         reg_umr[0x1];
3276         u8         allow_swp[0x1];
3277         u8         hairpin[0x1];
3278         u8         reserved_at_f[0x11];
3279
3280         u8         reserved_at_20[0x8];
3281         u8         user_index[0x18];
3282
3283         u8         reserved_at_40[0x8];
3284         u8         cqn[0x18];
3285
3286         u8         reserved_at_60[0x8];
3287         u8         hairpin_peer_rq[0x18];
3288
3289         u8         reserved_at_80[0x10];
3290         u8         hairpin_peer_vhca[0x10];
3291
3292         u8         reserved_at_a0[0x50];
3293
3294         u8         packet_pacing_rate_limit_index[0x10];
3295         u8         tis_lst_sz[0x10];
3296         u8         reserved_at_110[0x10];
3297
3298         u8         reserved_at_120[0x40];
3299
3300         u8         reserved_at_160[0x8];
3301         u8         tis_num_0[0x18];
3302
3303         struct mlx5_ifc_wq_bits wq;
3304 };
3305
3306 enum {
3307         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3308         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3309         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3310         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3311 };
3312
3313 enum {
3314         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3315         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3316         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3317         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3318 };
3319
3320 struct mlx5_ifc_scheduling_context_bits {
3321         u8         element_type[0x8];
3322         u8         reserved_at_8[0x18];
3323
3324         u8         element_attributes[0x20];
3325
3326         u8         parent_element_id[0x20];
3327
3328         u8         reserved_at_60[0x40];
3329
3330         u8         bw_share[0x20];
3331
3332         u8         max_average_bw[0x20];
3333
3334         u8         reserved_at_e0[0x120];
3335 };
3336
3337 struct mlx5_ifc_rqtc_bits {
3338         u8    reserved_at_0[0xa0];
3339
3340         u8    reserved_at_a0[0x5];
3341         u8    list_q_type[0x3];
3342         u8    reserved_at_a8[0x8];
3343         u8    rqt_max_size[0x10];
3344
3345         u8    rq_vhca_id_format[0x1];
3346         u8    reserved_at_c1[0xf];
3347         u8    rqt_actual_size[0x10];
3348
3349         u8    reserved_at_e0[0x6a0];
3350
3351         struct mlx5_ifc_rq_num_bits rq_num[];
3352 };
3353
3354 enum {
3355         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3356         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3357 };
3358
3359 enum {
3360         MLX5_RQC_STATE_RST  = 0x0,
3361         MLX5_RQC_STATE_RDY  = 0x1,
3362         MLX5_RQC_STATE_ERR  = 0x3,
3363 };
3364
3365 struct mlx5_ifc_rqc_bits {
3366         u8         rlky[0x1];
3367         u8         delay_drop_en[0x1];
3368         u8         scatter_fcs[0x1];
3369         u8         vsd[0x1];
3370         u8         mem_rq_type[0x4];
3371         u8         state[0x4];
3372         u8         reserved_at_c[0x1];
3373         u8         flush_in_error_en[0x1];
3374         u8         hairpin[0x1];
3375         u8         reserved_at_f[0x11];
3376
3377         u8         reserved_at_20[0x8];
3378         u8         user_index[0x18];
3379
3380         u8         reserved_at_40[0x8];
3381         u8         cqn[0x18];
3382
3383         u8         counter_set_id[0x8];
3384         u8         reserved_at_68[0x18];
3385
3386         u8         reserved_at_80[0x8];
3387         u8         rmpn[0x18];
3388
3389         u8         reserved_at_a0[0x8];
3390         u8         hairpin_peer_sq[0x18];
3391
3392         u8         reserved_at_c0[0x10];
3393         u8         hairpin_peer_vhca[0x10];
3394
3395         u8         reserved_at_e0[0xa0];
3396
3397         struct mlx5_ifc_wq_bits wq;
3398 };
3399
3400 enum {
3401         MLX5_RMPC_STATE_RDY  = 0x1,
3402         MLX5_RMPC_STATE_ERR  = 0x3,
3403 };
3404
3405 struct mlx5_ifc_rmpc_bits {
3406         u8         reserved_at_0[0x8];
3407         u8         state[0x4];
3408         u8         reserved_at_c[0x14];
3409
3410         u8         basic_cyclic_rcv_wqe[0x1];
3411         u8         reserved_at_21[0x1f];
3412
3413         u8         reserved_at_40[0x140];
3414
3415         struct mlx5_ifc_wq_bits wq;
3416 };
3417
3418 struct mlx5_ifc_nic_vport_context_bits {
3419         u8         reserved_at_0[0x5];
3420         u8         min_wqe_inline_mode[0x3];
3421         u8         reserved_at_8[0x15];
3422         u8         disable_mc_local_lb[0x1];
3423         u8         disable_uc_local_lb[0x1];
3424         u8         roce_en[0x1];
3425
3426         u8         arm_change_event[0x1];
3427         u8         reserved_at_21[0x1a];
3428         u8         event_on_mtu[0x1];
3429         u8         event_on_promisc_change[0x1];
3430         u8         event_on_vlan_change[0x1];
3431         u8         event_on_mc_address_change[0x1];
3432         u8         event_on_uc_address_change[0x1];
3433
3434         u8         reserved_at_40[0xc];
3435
3436         u8         affiliation_criteria[0x4];
3437         u8         affiliated_vhca_id[0x10];
3438
3439         u8         reserved_at_60[0xd0];
3440
3441         u8         mtu[0x10];
3442
3443         u8         system_image_guid[0x40];
3444         u8         port_guid[0x40];
3445         u8         node_guid[0x40];
3446
3447         u8         reserved_at_200[0x140];
3448         u8         qkey_violation_counter[0x10];
3449         u8         reserved_at_350[0x430];
3450
3451         u8         promisc_uc[0x1];
3452         u8         promisc_mc[0x1];
3453         u8         promisc_all[0x1];
3454         u8         reserved_at_783[0x2];
3455         u8         allowed_list_type[0x3];
3456         u8         reserved_at_788[0xc];
3457         u8         allowed_list_size[0xc];
3458
3459         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3460
3461         u8         reserved_at_7e0[0x20];
3462
3463         u8         current_uc_mac_address[][0x40];
3464 };
3465
3466 enum {
3467         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3468         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3469         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3470         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3471         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3472         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3473 };
3474
3475 struct mlx5_ifc_mkc_bits {
3476         u8         reserved_at_0[0x1];
3477         u8         free[0x1];
3478         u8         reserved_at_2[0x1];
3479         u8         access_mode_4_2[0x3];
3480         u8         reserved_at_6[0x7];
3481         u8         relaxed_ordering_write[0x1];
3482         u8         reserved_at_e[0x1];
3483         u8         small_fence_on_rdma_read_response[0x1];
3484         u8         umr_en[0x1];
3485         u8         a[0x1];
3486         u8         rw[0x1];
3487         u8         rr[0x1];
3488         u8         lw[0x1];
3489         u8         lr[0x1];
3490         u8         access_mode_1_0[0x2];
3491         u8         reserved_at_18[0x8];
3492
3493         u8         qpn[0x18];
3494         u8         mkey_7_0[0x8];
3495
3496         u8         reserved_at_40[0x20];
3497
3498         u8         length64[0x1];
3499         u8         bsf_en[0x1];
3500         u8         sync_umr[0x1];
3501         u8         reserved_at_63[0x2];
3502         u8         expected_sigerr_count[0x1];
3503         u8         reserved_at_66[0x1];
3504         u8         en_rinval[0x1];
3505         u8         pd[0x18];
3506
3507         u8         start_addr[0x40];
3508
3509         u8         len[0x40];
3510
3511         u8         bsf_octword_size[0x20];
3512
3513         u8         reserved_at_120[0x80];
3514
3515         u8         translations_octword_size[0x20];
3516
3517         u8         reserved_at_1c0[0x19];
3518         u8         relaxed_ordering_read[0x1];
3519         u8         reserved_at_1d9[0x1];
3520         u8         log_page_size[0x5];
3521
3522         u8         reserved_at_1e0[0x20];
3523 };
3524
3525 struct mlx5_ifc_pkey_bits {
3526         u8         reserved_at_0[0x10];
3527         u8         pkey[0x10];
3528 };
3529
3530 struct mlx5_ifc_array128_auto_bits {
3531         u8         array128_auto[16][0x8];
3532 };
3533
3534 struct mlx5_ifc_hca_vport_context_bits {
3535         u8         field_select[0x20];
3536
3537         u8         reserved_at_20[0xe0];
3538
3539         u8         sm_virt_aware[0x1];
3540         u8         has_smi[0x1];
3541         u8         has_raw[0x1];
3542         u8         grh_required[0x1];
3543         u8         reserved_at_104[0xc];
3544         u8         port_physical_state[0x4];
3545         u8         vport_state_policy[0x4];
3546         u8         port_state[0x4];
3547         u8         vport_state[0x4];
3548
3549         u8         reserved_at_120[0x20];
3550
3551         u8         system_image_guid[0x40];
3552
3553         u8         port_guid[0x40];
3554
3555         u8         node_guid[0x40];
3556
3557         u8         cap_mask1[0x20];
3558
3559         u8         cap_mask1_field_select[0x20];
3560
3561         u8         cap_mask2[0x20];
3562
3563         u8         cap_mask2_field_select[0x20];
3564
3565         u8         reserved_at_280[0x80];
3566
3567         u8         lid[0x10];
3568         u8         reserved_at_310[0x4];
3569         u8         init_type_reply[0x4];
3570         u8         lmc[0x3];
3571         u8         subnet_timeout[0x5];
3572
3573         u8         sm_lid[0x10];
3574         u8         sm_sl[0x4];
3575         u8         reserved_at_334[0xc];
3576
3577         u8         qkey_violation_counter[0x10];
3578         u8         pkey_violation_counter[0x10];
3579
3580         u8         reserved_at_360[0xca0];
3581 };
3582
3583 struct mlx5_ifc_esw_vport_context_bits {
3584         u8         fdb_to_vport_reg_c[0x1];
3585         u8         reserved_at_1[0x2];
3586         u8         vport_svlan_strip[0x1];
3587         u8         vport_cvlan_strip[0x1];
3588         u8         vport_svlan_insert[0x1];
3589         u8         vport_cvlan_insert[0x2];
3590         u8         fdb_to_vport_reg_c_id[0x8];
3591         u8         reserved_at_10[0x10];
3592
3593         u8         reserved_at_20[0x20];
3594
3595         u8         svlan_cfi[0x1];
3596         u8         svlan_pcp[0x3];
3597         u8         svlan_id[0xc];
3598         u8         cvlan_cfi[0x1];
3599         u8         cvlan_pcp[0x3];
3600         u8         cvlan_id[0xc];
3601
3602         u8         reserved_at_60[0x720];
3603
3604         u8         sw_steering_vport_icm_address_rx[0x40];
3605
3606         u8         sw_steering_vport_icm_address_tx[0x40];
3607 };
3608
3609 enum {
3610         MLX5_EQC_STATUS_OK                = 0x0,
3611         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3612 };
3613
3614 enum {
3615         MLX5_EQC_ST_ARMED  = 0x9,
3616         MLX5_EQC_ST_FIRED  = 0xa,
3617 };
3618
3619 struct mlx5_ifc_eqc_bits {
3620         u8         status[0x4];
3621         u8         reserved_at_4[0x9];
3622         u8         ec[0x1];
3623         u8         oi[0x1];
3624         u8         reserved_at_f[0x5];
3625         u8         st[0x4];
3626         u8         reserved_at_18[0x8];
3627
3628         u8         reserved_at_20[0x20];
3629
3630         u8         reserved_at_40[0x14];
3631         u8         page_offset[0x6];
3632         u8         reserved_at_5a[0x6];
3633
3634         u8         reserved_at_60[0x3];
3635         u8         log_eq_size[0x5];
3636         u8         uar_page[0x18];
3637
3638         u8         reserved_at_80[0x20];
3639
3640         u8         reserved_at_a0[0x18];
3641         u8         intr[0x8];
3642
3643         u8         reserved_at_c0[0x3];
3644         u8         log_page_size[0x5];
3645         u8         reserved_at_c8[0x18];
3646
3647         u8         reserved_at_e0[0x60];
3648
3649         u8         reserved_at_140[0x8];
3650         u8         consumer_counter[0x18];
3651
3652         u8         reserved_at_160[0x8];
3653         u8         producer_counter[0x18];
3654
3655         u8         reserved_at_180[0x80];
3656 };
3657
3658 enum {
3659         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3660         MLX5_DCTC_STATE_DRAINING  = 0x1,
3661         MLX5_DCTC_STATE_DRAINED   = 0x2,
3662 };
3663
3664 enum {
3665         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3666         MLX5_DCTC_CS_RES_NA         = 0x1,
3667         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3668 };
3669
3670 enum {
3671         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3672         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3673         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3674         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3675         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3676 };
3677
3678 struct mlx5_ifc_dctc_bits {
3679         u8         reserved_at_0[0x4];
3680         u8         state[0x4];
3681         u8         reserved_at_8[0x18];
3682
3683         u8         reserved_at_20[0x8];
3684         u8         user_index[0x18];
3685
3686         u8         reserved_at_40[0x8];
3687         u8         cqn[0x18];
3688
3689         u8         counter_set_id[0x8];
3690         u8         atomic_mode[0x4];
3691         u8         rre[0x1];
3692         u8         rwe[0x1];
3693         u8         rae[0x1];
3694         u8         atomic_like_write_en[0x1];
3695         u8         latency_sensitive[0x1];
3696         u8         rlky[0x1];
3697         u8         free_ar[0x1];
3698         u8         reserved_at_73[0xd];
3699
3700         u8         reserved_at_80[0x8];
3701         u8         cs_res[0x8];
3702         u8         reserved_at_90[0x3];
3703         u8         min_rnr_nak[0x5];
3704         u8         reserved_at_98[0x8];
3705
3706         u8         reserved_at_a0[0x8];
3707         u8         srqn_xrqn[0x18];
3708
3709         u8         reserved_at_c0[0x8];
3710         u8         pd[0x18];
3711
3712         u8         tclass[0x8];
3713         u8         reserved_at_e8[0x4];
3714         u8         flow_label[0x14];
3715
3716         u8         dc_access_key[0x40];
3717
3718         u8         reserved_at_140[0x5];
3719         u8         mtu[0x3];
3720         u8         port[0x8];
3721         u8         pkey_index[0x10];
3722
3723         u8         reserved_at_160[0x8];
3724         u8         my_addr_index[0x8];
3725         u8         reserved_at_170[0x8];
3726         u8         hop_limit[0x8];
3727
3728         u8         dc_access_key_violation_count[0x20];
3729
3730         u8         reserved_at_1a0[0x14];
3731         u8         dei_cfi[0x1];
3732         u8         eth_prio[0x3];
3733         u8         ecn[0x2];
3734         u8         dscp[0x6];
3735
3736         u8         reserved_at_1c0[0x20];
3737         u8         ece[0x20];
3738 };
3739
3740 enum {
3741         MLX5_CQC_STATUS_OK             = 0x0,
3742         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3743         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3744 };
3745
3746 enum {
3747         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3748         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3749 };
3750
3751 enum {
3752         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3753         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3754         MLX5_CQC_ST_FIRED                                 = 0xa,
3755 };
3756
3757 enum {
3758         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3759         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3760         MLX5_CQ_PERIOD_NUM_MODES
3761 };
3762
3763 struct mlx5_ifc_cqc_bits {
3764         u8         status[0x4];
3765         u8         reserved_at_4[0x2];
3766         u8         dbr_umem_valid[0x1];
3767         u8         reserved_at_7[0x1];
3768         u8         cqe_sz[0x3];
3769         u8         cc[0x1];
3770         u8         reserved_at_c[0x1];
3771         u8         scqe_break_moderation_en[0x1];
3772         u8         oi[0x1];
3773         u8         cq_period_mode[0x2];
3774         u8         cqe_comp_en[0x1];
3775         u8         mini_cqe_res_format[0x2];
3776         u8         st[0x4];
3777         u8         reserved_at_18[0x8];
3778
3779         u8         reserved_at_20[0x20];
3780
3781         u8         reserved_at_40[0x14];
3782         u8         page_offset[0x6];
3783         u8         reserved_at_5a[0x6];
3784
3785         u8         reserved_at_60[0x3];
3786         u8         log_cq_size[0x5];
3787         u8         uar_page[0x18];
3788
3789         u8         reserved_at_80[0x4];
3790         u8         cq_period[0xc];
3791         u8         cq_max_count[0x10];
3792
3793         u8         reserved_at_a0[0x18];
3794         u8         c_eqn[0x8];
3795
3796         u8         reserved_at_c0[0x3];
3797         u8         log_page_size[0x5];
3798         u8         reserved_at_c8[0x18];
3799
3800         u8         reserved_at_e0[0x20];
3801
3802         u8         reserved_at_100[0x8];
3803         u8         last_notified_index[0x18];
3804
3805         u8         reserved_at_120[0x8];
3806         u8         last_solicit_index[0x18];
3807
3808         u8         reserved_at_140[0x8];
3809         u8         consumer_counter[0x18];
3810
3811         u8         reserved_at_160[0x8];
3812         u8         producer_counter[0x18];
3813
3814         u8         reserved_at_180[0x40];
3815
3816         u8         dbr_addr[0x40];
3817 };
3818
3819 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3820         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3821         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3822         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3823         u8         reserved_at_0[0x800];
3824 };
3825
3826 struct mlx5_ifc_query_adapter_param_block_bits {
3827         u8         reserved_at_0[0xc0];
3828
3829         u8         reserved_at_c0[0x8];
3830         u8         ieee_vendor_id[0x18];
3831
3832         u8         reserved_at_e0[0x10];
3833         u8         vsd_vendor_id[0x10];
3834
3835         u8         vsd[208][0x8];
3836
3837         u8         vsd_contd_psid[16][0x8];
3838 };
3839
3840 enum {
3841         MLX5_XRQC_STATE_GOOD   = 0x0,
3842         MLX5_XRQC_STATE_ERROR  = 0x1,
3843 };
3844
3845 enum {
3846         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3847         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3848 };
3849
3850 enum {
3851         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3852 };
3853
3854 struct mlx5_ifc_tag_matching_topology_context_bits {
3855         u8         log_matching_list_sz[0x4];
3856         u8         reserved_at_4[0xc];
3857         u8         append_next_index[0x10];
3858
3859         u8         sw_phase_cnt[0x10];
3860         u8         hw_phase_cnt[0x10];
3861
3862         u8         reserved_at_40[0x40];
3863 };
3864
3865 struct mlx5_ifc_xrqc_bits {
3866         u8         state[0x4];
3867         u8         rlkey[0x1];
3868         u8         reserved_at_5[0xf];
3869         u8         topology[0x4];
3870         u8         reserved_at_18[0x4];
3871         u8         offload[0x4];
3872
3873         u8         reserved_at_20[0x8];
3874         u8         user_index[0x18];
3875
3876         u8         reserved_at_40[0x8];
3877         u8         cqn[0x18];
3878
3879         u8         reserved_at_60[0xa0];
3880
3881         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3882
3883         u8         reserved_at_180[0x280];
3884
3885         struct mlx5_ifc_wq_bits wq;
3886 };
3887
3888 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3889         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3890         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3891         u8         reserved_at_0[0x20];
3892 };
3893
3894 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3895         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3896         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3897         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3898         u8         reserved_at_0[0x20];
3899 };
3900
3901 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3902         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3903         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3904         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3905         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3906         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3907         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3908         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3909         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3910         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3911         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3912         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3913         u8         reserved_at_0[0x7c0];
3914 };
3915
3916 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3917         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3918         u8         reserved_at_0[0x7c0];
3919 };
3920
3921 union mlx5_ifc_event_auto_bits {
3922         struct mlx5_ifc_comp_event_bits comp_event;
3923         struct mlx5_ifc_dct_events_bits dct_events;
3924         struct mlx5_ifc_qp_events_bits qp_events;
3925         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3926         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3927         struct mlx5_ifc_cq_error_bits cq_error;
3928         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3929         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3930         struct mlx5_ifc_gpio_event_bits gpio_event;
3931         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3932         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3933         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3934         u8         reserved_at_0[0xe0];
3935 };
3936
3937 struct mlx5_ifc_health_buffer_bits {
3938         u8         reserved_at_0[0x100];
3939
3940         u8         assert_existptr[0x20];
3941
3942         u8         assert_callra[0x20];
3943
3944         u8         reserved_at_140[0x40];
3945
3946         u8         fw_version[0x20];
3947
3948         u8         hw_id[0x20];
3949
3950         u8         reserved_at_1c0[0x20];
3951
3952         u8         irisc_index[0x8];
3953         u8         synd[0x8];
3954         u8         ext_synd[0x10];
3955 };
3956
3957 struct mlx5_ifc_register_loopback_control_bits {
3958         u8         no_lb[0x1];
3959         u8         reserved_at_1[0x7];
3960         u8         port[0x8];
3961         u8         reserved_at_10[0x10];
3962
3963         u8         reserved_at_20[0x60];
3964 };
3965
3966 struct mlx5_ifc_vport_tc_element_bits {
3967         u8         traffic_class[0x4];
3968         u8         reserved_at_4[0xc];
3969         u8         vport_number[0x10];
3970 };
3971
3972 struct mlx5_ifc_vport_element_bits {
3973         u8         reserved_at_0[0x10];
3974         u8         vport_number[0x10];
3975 };
3976
3977 enum {
3978         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3979         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3980         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3981 };
3982
3983 struct mlx5_ifc_tsar_element_bits {
3984         u8         reserved_at_0[0x8];
3985         u8         tsar_type[0x8];
3986         u8         reserved_at_10[0x10];
3987 };
3988
3989 enum {
3990         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3991         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3992 };
3993
3994 struct mlx5_ifc_teardown_hca_out_bits {
3995         u8         status[0x8];
3996         u8         reserved_at_8[0x18];
3997
3998         u8         syndrome[0x20];
3999
4000         u8         reserved_at_40[0x3f];
4001
4002         u8         state[0x1];
4003 };
4004
4005 enum {
4006         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4007         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4008         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4009 };
4010
4011 struct mlx5_ifc_teardown_hca_in_bits {
4012         u8         opcode[0x10];
4013         u8         reserved_at_10[0x10];
4014
4015         u8         reserved_at_20[0x10];
4016         u8         op_mod[0x10];
4017
4018         u8         reserved_at_40[0x10];
4019         u8         profile[0x10];
4020
4021         u8         reserved_at_60[0x20];
4022 };
4023
4024 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4025         u8         status[0x8];
4026         u8         reserved_at_8[0x18];
4027
4028         u8         syndrome[0x20];
4029
4030         u8         reserved_at_40[0x40];
4031 };
4032
4033 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4034         u8         opcode[0x10];
4035         u8         uid[0x10];
4036
4037         u8         reserved_at_20[0x10];
4038         u8         op_mod[0x10];
4039
4040         u8         reserved_at_40[0x8];
4041         u8         qpn[0x18];
4042
4043         u8         reserved_at_60[0x20];
4044
4045         u8         opt_param_mask[0x20];
4046
4047         u8         reserved_at_a0[0x20];
4048
4049         struct mlx5_ifc_qpc_bits qpc;
4050
4051         u8         reserved_at_800[0x80];
4052 };
4053
4054 struct mlx5_ifc_sqd2rts_qp_out_bits {
4055         u8         status[0x8];
4056         u8         reserved_at_8[0x18];
4057
4058         u8         syndrome[0x20];
4059
4060         u8         reserved_at_40[0x40];
4061 };
4062
4063 struct mlx5_ifc_sqd2rts_qp_in_bits {
4064         u8         opcode[0x10];
4065         u8         uid[0x10];
4066
4067         u8         reserved_at_20[0x10];
4068         u8         op_mod[0x10];
4069
4070         u8         reserved_at_40[0x8];
4071         u8         qpn[0x18];
4072
4073         u8         reserved_at_60[0x20];
4074
4075         u8         opt_param_mask[0x20];
4076
4077         u8         reserved_at_a0[0x20];
4078
4079         struct mlx5_ifc_qpc_bits qpc;
4080
4081         u8         reserved_at_800[0x80];
4082 };
4083
4084 struct mlx5_ifc_set_roce_address_out_bits {
4085         u8         status[0x8];
4086         u8         reserved_at_8[0x18];
4087
4088         u8         syndrome[0x20];
4089
4090         u8         reserved_at_40[0x40];
4091 };
4092
4093 struct mlx5_ifc_set_roce_address_in_bits {
4094         u8         opcode[0x10];
4095         u8         reserved_at_10[0x10];
4096
4097         u8         reserved_at_20[0x10];
4098         u8         op_mod[0x10];
4099
4100         u8         roce_address_index[0x10];
4101         u8         reserved_at_50[0xc];
4102         u8         vhca_port_num[0x4];
4103
4104         u8         reserved_at_60[0x20];
4105
4106         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4107 };
4108
4109 struct mlx5_ifc_set_mad_demux_out_bits {
4110         u8         status[0x8];
4111         u8         reserved_at_8[0x18];
4112
4113         u8         syndrome[0x20];
4114
4115         u8         reserved_at_40[0x40];
4116 };
4117
4118 enum {
4119         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4120         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4121 };
4122
4123 struct mlx5_ifc_set_mad_demux_in_bits {
4124         u8         opcode[0x10];
4125         u8         reserved_at_10[0x10];
4126
4127         u8         reserved_at_20[0x10];
4128         u8         op_mod[0x10];
4129
4130         u8         reserved_at_40[0x20];
4131
4132         u8         reserved_at_60[0x6];
4133         u8         demux_mode[0x2];
4134         u8         reserved_at_68[0x18];
4135 };
4136
4137 struct mlx5_ifc_set_l2_table_entry_out_bits {
4138         u8         status[0x8];
4139         u8         reserved_at_8[0x18];
4140
4141         u8         syndrome[0x20];
4142
4143         u8         reserved_at_40[0x40];
4144 };
4145
4146 struct mlx5_ifc_set_l2_table_entry_in_bits {
4147         u8         opcode[0x10];
4148         u8         reserved_at_10[0x10];
4149
4150         u8         reserved_at_20[0x10];
4151         u8         op_mod[0x10];
4152
4153         u8         reserved_at_40[0x60];
4154
4155         u8         reserved_at_a0[0x8];
4156         u8         table_index[0x18];
4157
4158         u8         reserved_at_c0[0x20];
4159
4160         u8         reserved_at_e0[0x13];
4161         u8         vlan_valid[0x1];
4162         u8         vlan[0xc];
4163
4164         struct mlx5_ifc_mac_address_layout_bits mac_address;
4165
4166         u8         reserved_at_140[0xc0];
4167 };
4168
4169 struct mlx5_ifc_set_issi_out_bits {
4170         u8         status[0x8];
4171         u8         reserved_at_8[0x18];
4172
4173         u8         syndrome[0x20];
4174
4175         u8         reserved_at_40[0x40];
4176 };
4177
4178 struct mlx5_ifc_set_issi_in_bits {
4179         u8         opcode[0x10];
4180         u8         reserved_at_10[0x10];
4181
4182         u8         reserved_at_20[0x10];
4183         u8         op_mod[0x10];
4184
4185         u8         reserved_at_40[0x10];
4186         u8         current_issi[0x10];
4187
4188         u8         reserved_at_60[0x20];
4189 };
4190
4191 struct mlx5_ifc_set_hca_cap_out_bits {
4192         u8         status[0x8];
4193         u8         reserved_at_8[0x18];
4194
4195         u8         syndrome[0x20];
4196
4197         u8         reserved_at_40[0x40];
4198 };
4199
4200 struct mlx5_ifc_set_hca_cap_in_bits {
4201         u8         opcode[0x10];
4202         u8         reserved_at_10[0x10];
4203
4204         u8         reserved_at_20[0x10];
4205         u8         op_mod[0x10];
4206
4207         u8         reserved_at_40[0x40];
4208
4209         union mlx5_ifc_hca_cap_union_bits capability;
4210 };
4211
4212 enum {
4213         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4214         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4215         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4216         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4217         MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4218 };
4219
4220 struct mlx5_ifc_set_fte_out_bits {
4221         u8         status[0x8];
4222         u8         reserved_at_8[0x18];
4223
4224         u8         syndrome[0x20];
4225
4226         u8         reserved_at_40[0x40];
4227 };
4228
4229 struct mlx5_ifc_set_fte_in_bits {
4230         u8         opcode[0x10];
4231         u8         reserved_at_10[0x10];
4232
4233         u8         reserved_at_20[0x10];
4234         u8         op_mod[0x10];
4235
4236         u8         other_vport[0x1];
4237         u8         reserved_at_41[0xf];
4238         u8         vport_number[0x10];
4239
4240         u8         reserved_at_60[0x20];
4241
4242         u8         table_type[0x8];
4243         u8         reserved_at_88[0x18];
4244
4245         u8         reserved_at_a0[0x8];
4246         u8         table_id[0x18];
4247
4248         u8         ignore_flow_level[0x1];
4249         u8         reserved_at_c1[0x17];
4250         u8         modify_enable_mask[0x8];
4251
4252         u8         reserved_at_e0[0x20];
4253
4254         u8         flow_index[0x20];
4255
4256         u8         reserved_at_120[0xe0];
4257
4258         struct mlx5_ifc_flow_context_bits flow_context;
4259 };
4260
4261 struct mlx5_ifc_rts2rts_qp_out_bits {
4262         u8         status[0x8];
4263         u8         reserved_at_8[0x18];
4264
4265         u8         syndrome[0x20];
4266
4267         u8         reserved_at_40[0x20];
4268         u8         ece[0x20];
4269 };
4270
4271 struct mlx5_ifc_rts2rts_qp_in_bits {
4272         u8         opcode[0x10];
4273         u8         uid[0x10];
4274
4275         u8         reserved_at_20[0x10];
4276         u8         op_mod[0x10];
4277
4278         u8         reserved_at_40[0x8];
4279         u8         qpn[0x18];
4280
4281         u8         reserved_at_60[0x20];
4282
4283         u8         opt_param_mask[0x20];
4284
4285         u8         ece[0x20];
4286
4287         struct mlx5_ifc_qpc_bits qpc;
4288
4289         u8         reserved_at_800[0x80];
4290 };
4291
4292 struct mlx5_ifc_rtr2rts_qp_out_bits {
4293         u8         status[0x8];
4294         u8         reserved_at_8[0x18];
4295
4296         u8         syndrome[0x20];
4297
4298         u8         reserved_at_40[0x20];
4299         u8         ece[0x20];
4300 };
4301
4302 struct mlx5_ifc_rtr2rts_qp_in_bits {
4303         u8         opcode[0x10];
4304         u8         uid[0x10];
4305
4306         u8         reserved_at_20[0x10];
4307         u8         op_mod[0x10];
4308
4309         u8         reserved_at_40[0x8];
4310         u8         qpn[0x18];
4311
4312         u8         reserved_at_60[0x20];
4313
4314         u8         opt_param_mask[0x20];
4315
4316         u8         ece[0x20];
4317
4318         struct mlx5_ifc_qpc_bits qpc;
4319
4320         u8         reserved_at_800[0x80];
4321 };
4322
4323 struct mlx5_ifc_rst2init_qp_out_bits {
4324         u8         status[0x8];
4325         u8         reserved_at_8[0x18];
4326
4327         u8         syndrome[0x20];
4328
4329         u8         reserved_at_40[0x20];
4330         u8         ece[0x20];
4331 };
4332
4333 struct mlx5_ifc_rst2init_qp_in_bits {
4334         u8         opcode[0x10];
4335         u8         uid[0x10];
4336
4337         u8         reserved_at_20[0x10];
4338         u8         op_mod[0x10];
4339
4340         u8         reserved_at_40[0x8];
4341         u8         qpn[0x18];
4342
4343         u8         reserved_at_60[0x20];
4344
4345         u8         opt_param_mask[0x20];
4346
4347         u8         ece[0x20];
4348
4349         struct mlx5_ifc_qpc_bits qpc;
4350
4351         u8         reserved_at_800[0x80];
4352 };
4353
4354 struct mlx5_ifc_query_xrq_out_bits {
4355         u8         status[0x8];
4356         u8         reserved_at_8[0x18];
4357
4358         u8         syndrome[0x20];
4359
4360         u8         reserved_at_40[0x40];
4361
4362         struct mlx5_ifc_xrqc_bits xrq_context;
4363 };
4364
4365 struct mlx5_ifc_query_xrq_in_bits {
4366         u8         opcode[0x10];
4367         u8         reserved_at_10[0x10];
4368
4369         u8         reserved_at_20[0x10];
4370         u8         op_mod[0x10];
4371
4372         u8         reserved_at_40[0x8];
4373         u8         xrqn[0x18];
4374
4375         u8         reserved_at_60[0x20];
4376 };
4377
4378 struct mlx5_ifc_query_xrc_srq_out_bits {
4379         u8         status[0x8];
4380         u8         reserved_at_8[0x18];
4381
4382         u8         syndrome[0x20];
4383
4384         u8         reserved_at_40[0x40];
4385
4386         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4387
4388         u8         reserved_at_280[0x600];
4389
4390         u8         pas[][0x40];
4391 };
4392
4393 struct mlx5_ifc_query_xrc_srq_in_bits {
4394         u8         opcode[0x10];
4395         u8         reserved_at_10[0x10];
4396
4397         u8         reserved_at_20[0x10];
4398         u8         op_mod[0x10];
4399
4400         u8         reserved_at_40[0x8];
4401         u8         xrc_srqn[0x18];
4402
4403         u8         reserved_at_60[0x20];
4404 };
4405
4406 enum {
4407         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4408         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4409 };
4410
4411 struct mlx5_ifc_query_vport_state_out_bits {
4412         u8         status[0x8];
4413         u8         reserved_at_8[0x18];
4414
4415         u8         syndrome[0x20];
4416
4417         u8         reserved_at_40[0x20];
4418
4419         u8         reserved_at_60[0x18];
4420         u8         admin_state[0x4];
4421         u8         state[0x4];
4422 };
4423
4424 enum {
4425         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4426         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4427         MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4428 };
4429
4430 struct mlx5_ifc_arm_monitor_counter_in_bits {
4431         u8         opcode[0x10];
4432         u8         uid[0x10];
4433
4434         u8         reserved_at_20[0x10];
4435         u8         op_mod[0x10];
4436
4437         u8         reserved_at_40[0x20];
4438
4439         u8         reserved_at_60[0x20];
4440 };
4441
4442 struct mlx5_ifc_arm_monitor_counter_out_bits {
4443         u8         status[0x8];
4444         u8         reserved_at_8[0x18];
4445
4446         u8         syndrome[0x20];
4447
4448         u8         reserved_at_40[0x40];
4449 };
4450
4451 enum {
4452         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4453         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4454 };
4455
4456 enum mlx5_monitor_counter_ppcnt {
4457         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4458         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4459         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4460         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4461         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4462         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4463 };
4464
4465 enum {
4466         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4467 };
4468
4469 struct mlx5_ifc_monitor_counter_output_bits {
4470         u8         reserved_at_0[0x4];
4471         u8         type[0x4];
4472         u8         reserved_at_8[0x8];
4473         u8         counter[0x10];
4474
4475         u8         counter_group_id[0x20];
4476 };
4477
4478 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4479 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4480 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4481                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4482
4483 struct mlx5_ifc_set_monitor_counter_in_bits {
4484         u8         opcode[0x10];
4485         u8         uid[0x10];
4486
4487         u8         reserved_at_20[0x10];
4488         u8         op_mod[0x10];
4489
4490         u8         reserved_at_40[0x10];
4491         u8         num_of_counters[0x10];
4492
4493         u8         reserved_at_60[0x20];
4494
4495         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4496 };
4497
4498 struct mlx5_ifc_set_monitor_counter_out_bits {
4499         u8         status[0x8];
4500         u8         reserved_at_8[0x18];
4501
4502         u8         syndrome[0x20];
4503
4504         u8         reserved_at_40[0x40];
4505 };
4506
4507 struct mlx5_ifc_query_vport_state_in_bits {
4508         u8         opcode[0x10];
4509         u8         reserved_at_10[0x10];
4510
4511         u8         reserved_at_20[0x10];
4512         u8         op_mod[0x10];
4513
4514         u8         other_vport[0x1];
4515         u8         reserved_at_41[0xf];
4516         u8         vport_number[0x10];
4517
4518         u8         reserved_at_60[0x20];
4519 };
4520
4521 struct mlx5_ifc_query_vnic_env_out_bits {
4522         u8         status[0x8];
4523         u8         reserved_at_8[0x18];
4524
4525         u8         syndrome[0x20];
4526
4527         u8         reserved_at_40[0x40];
4528
4529         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4530 };
4531
4532 enum {
4533         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4534 };
4535
4536 struct mlx5_ifc_query_vnic_env_in_bits {
4537         u8         opcode[0x10];
4538         u8         reserved_at_10[0x10];
4539
4540         u8         reserved_at_20[0x10];
4541         u8         op_mod[0x10];
4542
4543         u8         other_vport[0x1];
4544         u8         reserved_at_41[0xf];
4545         u8         vport_number[0x10];
4546
4547         u8         reserved_at_60[0x20];
4548 };
4549
4550 struct mlx5_ifc_query_vport_counter_out_bits {
4551         u8         status[0x8];
4552         u8         reserved_at_8[0x18];
4553
4554         u8         syndrome[0x20];
4555
4556         u8         reserved_at_40[0x40];
4557
4558         struct mlx5_ifc_traffic_counter_bits received_errors;
4559
4560         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4561
4562         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4563
4564         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4565
4566         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4567
4568         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4569
4570         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4571
4572         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4573
4574         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4575
4576         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4577
4578         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4579
4580         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4581
4582         u8         reserved_at_680[0xa00];
4583 };
4584
4585 enum {
4586         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4587 };
4588
4589 struct mlx5_ifc_query_vport_counter_in_bits {
4590         u8         opcode[0x10];
4591         u8         reserved_at_10[0x10];
4592
4593         u8         reserved_at_20[0x10];
4594         u8         op_mod[0x10];
4595
4596         u8         other_vport[0x1];
4597         u8         reserved_at_41[0xb];
4598         u8         port_num[0x4];
4599         u8         vport_number[0x10];
4600
4601         u8         reserved_at_60[0x60];
4602
4603         u8         clear[0x1];
4604         u8         reserved_at_c1[0x1f];
4605
4606         u8         reserved_at_e0[0x20];
4607 };
4608
4609 struct mlx5_ifc_query_tis_out_bits {
4610         u8         status[0x8];
4611         u8         reserved_at_8[0x18];
4612
4613         u8         syndrome[0x20];
4614
4615         u8         reserved_at_40[0x40];
4616
4617         struct mlx5_ifc_tisc_bits tis_context;
4618 };
4619
4620 struct mlx5_ifc_query_tis_in_bits {
4621         u8         opcode[0x10];
4622         u8         reserved_at_10[0x10];
4623
4624         u8         reserved_at_20[0x10];
4625         u8         op_mod[0x10];
4626
4627         u8         reserved_at_40[0x8];
4628         u8         tisn[0x18];
4629
4630         u8         reserved_at_60[0x20];
4631 };
4632
4633 struct mlx5_ifc_query_tir_out_bits {
4634         u8         status[0x8];
4635         u8         reserved_at_8[0x18];
4636
4637         u8         syndrome[0x20];
4638
4639         u8         reserved_at_40[0xc0];
4640
4641         struct mlx5_ifc_tirc_bits tir_context;
4642 };
4643
4644 struct mlx5_ifc_query_tir_in_bits {
4645         u8         opcode[0x10];
4646         u8         reserved_at_10[0x10];
4647
4648         u8         reserved_at_20[0x10];
4649         u8         op_mod[0x10];
4650
4651         u8         reserved_at_40[0x8];
4652         u8         tirn[0x18];
4653
4654         u8         reserved_at_60[0x20];
4655 };
4656
4657 struct mlx5_ifc_query_srq_out_bits {
4658         u8         status[0x8];
4659         u8         reserved_at_8[0x18];
4660
4661         u8         syndrome[0x20];
4662
4663         u8         reserved_at_40[0x40];
4664
4665         struct mlx5_ifc_srqc_bits srq_context_entry;
4666
4667         u8         reserved_at_280[0x600];
4668
4669         u8         pas[][0x40];
4670 };
4671
4672 struct mlx5_ifc_query_srq_in_bits {
4673         u8         opcode[0x10];
4674         u8         reserved_at_10[0x10];
4675
4676         u8         reserved_at_20[0x10];
4677         u8         op_mod[0x10];
4678
4679         u8         reserved_at_40[0x8];
4680         u8         srqn[0x18];
4681
4682         u8         reserved_at_60[0x20];
4683 };
4684
4685 struct mlx5_ifc_query_sq_out_bits {
4686         u8         status[0x8];
4687         u8         reserved_at_8[0x18];
4688
4689         u8         syndrome[0x20];
4690
4691         u8         reserved_at_40[0xc0];
4692
4693         struct mlx5_ifc_sqc_bits sq_context;
4694 };
4695
4696 struct mlx5_ifc_query_sq_in_bits {
4697         u8         opcode[0x10];
4698         u8         reserved_at_10[0x10];
4699
4700         u8         reserved_at_20[0x10];
4701         u8         op_mod[0x10];
4702
4703         u8         reserved_at_40[0x8];
4704         u8         sqn[0x18];
4705
4706         u8         reserved_at_60[0x20];
4707 };
4708
4709 struct mlx5_ifc_query_special_contexts_out_bits {
4710         u8         status[0x8];
4711         u8         reserved_at_8[0x18];
4712
4713         u8         syndrome[0x20];
4714
4715         u8         dump_fill_mkey[0x20];
4716
4717         u8         resd_lkey[0x20];
4718
4719         u8         null_mkey[0x20];
4720
4721         u8         reserved_at_a0[0x60];
4722 };
4723
4724 struct mlx5_ifc_query_special_contexts_in_bits {
4725         u8         opcode[0x10];
4726         u8         reserved_at_10[0x10];
4727
4728         u8         reserved_at_20[0x10];
4729         u8         op_mod[0x10];
4730
4731         u8         reserved_at_40[0x40];
4732 };
4733
4734 struct mlx5_ifc_query_scheduling_element_out_bits {
4735         u8         opcode[0x10];
4736         u8         reserved_at_10[0x10];
4737
4738         u8         reserved_at_20[0x10];
4739         u8         op_mod[0x10];
4740
4741         u8         reserved_at_40[0xc0];
4742
4743         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4744
4745         u8         reserved_at_300[0x100];
4746 };
4747
4748 enum {
4749         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4750 };
4751
4752 struct mlx5_ifc_query_scheduling_element_in_bits {
4753         u8         opcode[0x10];
4754         u8         reserved_at_10[0x10];
4755
4756         u8         reserved_at_20[0x10];
4757         u8         op_mod[0x10];
4758
4759         u8         scheduling_hierarchy[0x8];
4760         u8         reserved_at_48[0x18];
4761
4762         u8         scheduling_element_id[0x20];
4763
4764         u8         reserved_at_80[0x180];
4765 };
4766
4767 struct mlx5_ifc_query_rqt_out_bits {
4768         u8         status[0x8];
4769         u8         reserved_at_8[0x18];
4770
4771         u8         syndrome[0x20];
4772
4773         u8         reserved_at_40[0xc0];
4774
4775         struct mlx5_ifc_rqtc_bits rqt_context;
4776 };
4777
4778 struct mlx5_ifc_query_rqt_in_bits {
4779         u8         opcode[0x10];
4780         u8         reserved_at_10[0x10];
4781
4782         u8         reserved_at_20[0x10];
4783         u8         op_mod[0x10];
4784
4785         u8         reserved_at_40[0x8];
4786         u8         rqtn[0x18];
4787
4788         u8         reserved_at_60[0x20];
4789 };
4790
4791 struct mlx5_ifc_query_rq_out_bits {
4792         u8         status[0x8];
4793         u8         reserved_at_8[0x18];
4794
4795         u8         syndrome[0x20];
4796
4797         u8         reserved_at_40[0xc0];
4798
4799         struct mlx5_ifc_rqc_bits rq_context;
4800 };
4801
4802 struct mlx5_ifc_query_rq_in_bits {
4803         u8         opcode[0x10];
4804         u8         reserved_at_10[0x10];
4805
4806         u8         reserved_at_20[0x10];
4807         u8         op_mod[0x10];
4808
4809         u8         reserved_at_40[0x8];
4810         u8         rqn[0x18];
4811
4812         u8         reserved_at_60[0x20];
4813 };
4814
4815 struct mlx5_ifc_query_roce_address_out_bits {
4816         u8         status[0x8];
4817         u8         reserved_at_8[0x18];
4818
4819         u8         syndrome[0x20];
4820
4821         u8         reserved_at_40[0x40];
4822
4823         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4824 };
4825
4826 struct mlx5_ifc_query_roce_address_in_bits {
4827         u8         opcode[0x10];
4828         u8         reserved_at_10[0x10];
4829
4830         u8         reserved_at_20[0x10];
4831         u8         op_mod[0x10];
4832
4833         u8         roce_address_index[0x10];
4834         u8         reserved_at_50[0xc];
4835         u8         vhca_port_num[0x4];
4836
4837         u8         reserved_at_60[0x20];
4838 };
4839
4840 struct mlx5_ifc_query_rmp_out_bits {
4841         u8         status[0x8];
4842         u8         reserved_at_8[0x18];
4843
4844         u8         syndrome[0x20];
4845
4846         u8         reserved_at_40[0xc0];
4847
4848         struct mlx5_ifc_rmpc_bits rmp_context;
4849 };
4850
4851 struct mlx5_ifc_query_rmp_in_bits {
4852         u8         opcode[0x10];
4853         u8         reserved_at_10[0x10];
4854
4855         u8         reserved_at_20[0x10];
4856         u8         op_mod[0x10];
4857
4858         u8         reserved_at_40[0x8];
4859         u8         rmpn[0x18];
4860
4861         u8         reserved_at_60[0x20];
4862 };
4863
4864 struct mlx5_ifc_query_qp_out_bits {
4865         u8         status[0x8];
4866         u8         reserved_at_8[0x18];
4867
4868         u8         syndrome[0x20];
4869
4870         u8         reserved_at_40[0x20];
4871         u8         ece[0x20];
4872
4873         u8         opt_param_mask[0x20];
4874
4875         u8         reserved_at_a0[0x20];
4876
4877         struct mlx5_ifc_qpc_bits qpc;
4878
4879         u8         reserved_at_800[0x80];
4880
4881         u8         pas[][0x40];
4882 };
4883
4884 struct mlx5_ifc_query_qp_in_bits {
4885         u8         opcode[0x10];
4886         u8         reserved_at_10[0x10];
4887
4888         u8         reserved_at_20[0x10];
4889         u8         op_mod[0x10];
4890
4891         u8         reserved_at_40[0x8];
4892         u8         qpn[0x18];
4893
4894         u8         reserved_at_60[0x20];
4895 };
4896
4897 struct mlx5_ifc_query_q_counter_out_bits {
4898         u8         status[0x8];
4899         u8         reserved_at_8[0x18];
4900
4901         u8         syndrome[0x20];
4902
4903         u8         reserved_at_40[0x40];
4904
4905         u8         rx_write_requests[0x20];
4906
4907         u8         reserved_at_a0[0x20];
4908
4909         u8         rx_read_requests[0x20];
4910
4911         u8         reserved_at_e0[0x20];
4912
4913         u8         rx_atomic_requests[0x20];
4914
4915         u8         reserved_at_120[0x20];
4916
4917         u8         rx_dct_connect[0x20];
4918
4919         u8         reserved_at_160[0x20];
4920
4921         u8         out_of_buffer[0x20];
4922
4923         u8         reserved_at_1a0[0x20];
4924
4925         u8         out_of_sequence[0x20];
4926
4927         u8         reserved_at_1e0[0x20];
4928
4929         u8         duplicate_request[0x20];
4930
4931         u8         reserved_at_220[0x20];
4932
4933         u8         rnr_nak_retry_err[0x20];
4934
4935         u8         reserved_at_260[0x20];
4936
4937         u8         packet_seq_err[0x20];
4938
4939         u8         reserved_at_2a0[0x20];
4940
4941         u8         implied_nak_seq_err[0x20];
4942
4943         u8         reserved_at_2e0[0x20];
4944
4945         u8         local_ack_timeout_err[0x20];
4946
4947         u8         reserved_at_320[0xa0];
4948
4949         u8         resp_local_length_error[0x20];
4950
4951         u8         req_local_length_error[0x20];
4952
4953         u8         resp_local_qp_error[0x20];
4954
4955         u8         local_operation_error[0x20];
4956
4957         u8         resp_local_protection[0x20];
4958
4959         u8         req_local_protection[0x20];
4960
4961         u8         resp_cqe_error[0x20];
4962
4963         u8         req_cqe_error[0x20];
4964
4965         u8         req_mw_binding[0x20];
4966
4967         u8         req_bad_response[0x20];
4968
4969         u8         req_remote_invalid_request[0x20];
4970
4971         u8         resp_remote_invalid_request[0x20];
4972
4973         u8         req_remote_access_errors[0x20];
4974
4975         u8         resp_remote_access_errors[0x20];
4976
4977         u8         req_remote_operation_errors[0x20];
4978
4979         u8         req_transport_retries_exceeded[0x20];
4980
4981         u8         cq_overflow[0x20];
4982
4983         u8         resp_cqe_flush_error[0x20];
4984
4985         u8         req_cqe_flush_error[0x20];
4986
4987         u8         reserved_at_620[0x20];
4988
4989         u8         roce_adp_retrans[0x20];
4990
4991         u8         roce_adp_retrans_to[0x20];
4992
4993         u8         roce_slow_restart[0x20];
4994
4995         u8         roce_slow_restart_cnps[0x20];
4996
4997         u8         roce_slow_restart_trans[0x20];
4998
4999         u8         reserved_at_6e0[0x120];
5000 };
5001
5002 struct mlx5_ifc_query_q_counter_in_bits {
5003         u8         opcode[0x10];
5004         u8         reserved_at_10[0x10];
5005
5006         u8         reserved_at_20[0x10];
5007         u8         op_mod[0x10];
5008
5009         u8         reserved_at_40[0x80];
5010
5011         u8         clear[0x1];
5012         u8         reserved_at_c1[0x1f];
5013
5014         u8         reserved_at_e0[0x18];
5015         u8         counter_set_id[0x8];
5016 };
5017
5018 struct mlx5_ifc_query_pages_out_bits {
5019         u8         status[0x8];
5020         u8         reserved_at_8[0x18];
5021
5022         u8         syndrome[0x20];
5023
5024         u8         embedded_cpu_function[0x1];
5025         u8         reserved_at_41[0xf];
5026         u8         function_id[0x10];
5027
5028         u8         num_pages[0x20];
5029 };
5030
5031 enum {
5032         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5033         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5034         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5035 };
5036
5037 struct mlx5_ifc_query_pages_in_bits {
5038         u8         opcode[0x10];
5039         u8         reserved_at_10[0x10];
5040
5041         u8         reserved_at_20[0x10];
5042         u8         op_mod[0x10];
5043
5044         u8         embedded_cpu_function[0x1];
5045         u8         reserved_at_41[0xf];
5046         u8         function_id[0x10];
5047
5048         u8         reserved_at_60[0x20];
5049 };
5050
5051 struct mlx5_ifc_query_nic_vport_context_out_bits {
5052         u8         status[0x8];
5053         u8         reserved_at_8[0x18];
5054
5055         u8         syndrome[0x20];
5056
5057         u8         reserved_at_40[0x40];
5058
5059         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5060 };
5061
5062 struct mlx5_ifc_query_nic_vport_context_in_bits {
5063         u8         opcode[0x10];
5064         u8         reserved_at_10[0x10];
5065
5066         u8         reserved_at_20[0x10];
5067         u8         op_mod[0x10];
5068
5069         u8         other_vport[0x1];
5070         u8         reserved_at_41[0xf];
5071         u8         vport_number[0x10];
5072
5073         u8         reserved_at_60[0x5];
5074         u8         allowed_list_type[0x3];
5075         u8         reserved_at_68[0x18];
5076 };
5077
5078 struct mlx5_ifc_query_mkey_out_bits {
5079         u8         status[0x8];
5080         u8         reserved_at_8[0x18];
5081
5082         u8         syndrome[0x20];
5083
5084         u8         reserved_at_40[0x40];
5085
5086         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5087
5088         u8         reserved_at_280[0x600];
5089
5090         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5091
5092         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5093 };
5094
5095 struct mlx5_ifc_query_mkey_in_bits {
5096         u8         opcode[0x10];
5097         u8         reserved_at_10[0x10];
5098
5099         u8         reserved_at_20[0x10];
5100         u8         op_mod[0x10];
5101
5102         u8         reserved_at_40[0x8];
5103         u8         mkey_index[0x18];
5104
5105         u8         pg_access[0x1];
5106         u8         reserved_at_61[0x1f];
5107 };
5108
5109 struct mlx5_ifc_query_mad_demux_out_bits {
5110         u8         status[0x8];
5111         u8         reserved_at_8[0x18];
5112
5113         u8         syndrome[0x20];
5114
5115         u8         reserved_at_40[0x40];
5116
5117         u8         mad_dumux_parameters_block[0x20];
5118 };
5119
5120 struct mlx5_ifc_query_mad_demux_in_bits {
5121         u8         opcode[0x10];
5122         u8         reserved_at_10[0x10];
5123
5124         u8         reserved_at_20[0x10];
5125         u8         op_mod[0x10];
5126
5127         u8         reserved_at_40[0x40];
5128 };
5129
5130 struct mlx5_ifc_query_l2_table_entry_out_bits {
5131         u8         status[0x8];
5132         u8         reserved_at_8[0x18];
5133
5134         u8         syndrome[0x20];
5135
5136         u8         reserved_at_40[0xa0];
5137
5138         u8         reserved_at_e0[0x13];
5139         u8         vlan_valid[0x1];
5140         u8         vlan[0xc];
5141
5142         struct mlx5_ifc_mac_address_layout_bits mac_address;
5143
5144         u8         reserved_at_140[0xc0];
5145 };
5146
5147 struct mlx5_ifc_query_l2_table_entry_in_bits {
5148         u8         opcode[0x10];
5149         u8         reserved_at_10[0x10];
5150
5151         u8         reserved_at_20[0x10];
5152         u8         op_mod[0x10];
5153
5154         u8         reserved_at_40[0x60];
5155
5156         u8         reserved_at_a0[0x8];
5157         u8         table_index[0x18];
5158
5159         u8         reserved_at_c0[0x140];
5160 };
5161
5162 struct mlx5_ifc_query_issi_out_bits {
5163         u8         status[0x8];
5164         u8         reserved_at_8[0x18];
5165
5166         u8         syndrome[0x20];
5167
5168         u8         reserved_at_40[0x10];
5169         u8         current_issi[0x10];
5170
5171         u8         reserved_at_60[0xa0];
5172
5173         u8         reserved_at_100[76][0x8];
5174         u8         supported_issi_dw0[0x20];
5175 };
5176
5177 struct mlx5_ifc_query_issi_in_bits {
5178         u8         opcode[0x10];
5179         u8         reserved_at_10[0x10];
5180
5181         u8         reserved_at_20[0x10];
5182         u8         op_mod[0x10];
5183
5184         u8         reserved_at_40[0x40];
5185 };
5186
5187 struct mlx5_ifc_set_driver_version_out_bits {
5188         u8         status[0x8];
5189         u8         reserved_0[0x18];
5190
5191         u8         syndrome[0x20];
5192         u8         reserved_1[0x40];
5193 };
5194
5195 struct mlx5_ifc_set_driver_version_in_bits {
5196         u8         opcode[0x10];
5197         u8         reserved_0[0x10];
5198
5199         u8         reserved_1[0x10];
5200         u8         op_mod[0x10];
5201
5202         u8         reserved_2[0x40];
5203         u8         driver_version[64][0x8];
5204 };
5205
5206 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5207         u8         status[0x8];
5208         u8         reserved_at_8[0x18];
5209
5210         u8         syndrome[0x20];
5211
5212         u8         reserved_at_40[0x40];
5213
5214         struct mlx5_ifc_pkey_bits pkey[];
5215 };
5216
5217 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5218         u8         opcode[0x10];
5219         u8         reserved_at_10[0x10];
5220
5221         u8         reserved_at_20[0x10];
5222         u8         op_mod[0x10];
5223
5224         u8         other_vport[0x1];
5225         u8         reserved_at_41[0xb];
5226         u8         port_num[0x4];
5227         u8         vport_number[0x10];
5228
5229         u8         reserved_at_60[0x10];
5230         u8         pkey_index[0x10];
5231 };
5232
5233 enum {
5234         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5235         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5236         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5237 };
5238
5239 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5240         u8         status[0x8];
5241         u8         reserved_at_8[0x18];
5242
5243         u8         syndrome[0x20];
5244
5245         u8         reserved_at_40[0x20];
5246
5247         u8         gids_num[0x10];
5248         u8         reserved_at_70[0x10];
5249
5250         struct mlx5_ifc_array128_auto_bits gid[];
5251 };
5252
5253 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5254         u8         opcode[0x10];
5255         u8         reserved_at_10[0x10];
5256
5257         u8         reserved_at_20[0x10];
5258         u8         op_mod[0x10];
5259
5260         u8         other_vport[0x1];
5261         u8         reserved_at_41[0xb];
5262         u8         port_num[0x4];
5263         u8         vport_number[0x10];
5264
5265         u8         reserved_at_60[0x10];
5266         u8         gid_index[0x10];
5267 };
5268
5269 struct mlx5_ifc_query_hca_vport_context_out_bits {
5270         u8         status[0x8];
5271         u8         reserved_at_8[0x18];
5272
5273         u8         syndrome[0x20];
5274
5275         u8         reserved_at_40[0x40];
5276
5277         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5278 };
5279
5280 struct mlx5_ifc_query_hca_vport_context_in_bits {
5281         u8         opcode[0x10];
5282         u8         reserved_at_10[0x10];
5283
5284         u8         reserved_at_20[0x10];
5285         u8         op_mod[0x10];
5286
5287         u8         other_vport[0x1];
5288         u8         reserved_at_41[0xb];
5289         u8         port_num[0x4];
5290         u8         vport_number[0x10];
5291
5292         u8         reserved_at_60[0x20];
5293 };
5294
5295 struct mlx5_ifc_query_hca_cap_out_bits {
5296         u8         status[0x8];
5297         u8         reserved_at_8[0x18];
5298
5299         u8         syndrome[0x20];
5300
5301         u8         reserved_at_40[0x40];
5302
5303         union mlx5_ifc_hca_cap_union_bits capability;
5304 };
5305
5306 struct mlx5_ifc_query_hca_cap_in_bits {
5307         u8         opcode[0x10];
5308         u8         reserved_at_10[0x10];
5309
5310         u8         reserved_at_20[0x10];
5311         u8         op_mod[0x10];
5312
5313         u8         other_function[0x1];
5314         u8         reserved_at_41[0xf];
5315         u8         function_id[0x10];
5316
5317         u8         reserved_at_60[0x20];
5318 };
5319
5320 struct mlx5_ifc_other_hca_cap_bits {
5321         u8         roce[0x1];
5322         u8         reserved_at_1[0x27f];
5323 };
5324
5325 struct mlx5_ifc_query_other_hca_cap_out_bits {
5326         u8         status[0x8];
5327         u8         reserved_at_8[0x18];
5328
5329         u8         syndrome[0x20];
5330
5331         u8         reserved_at_40[0x40];
5332
5333         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5334 };
5335
5336 struct mlx5_ifc_query_other_hca_cap_in_bits {
5337         u8         opcode[0x10];
5338         u8         reserved_at_10[0x10];
5339
5340         u8         reserved_at_20[0x10];
5341         u8         op_mod[0x10];
5342
5343         u8         reserved_at_40[0x10];
5344         u8         function_id[0x10];
5345
5346         u8         reserved_at_60[0x20];
5347 };
5348
5349 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5350         u8         status[0x8];
5351         u8         reserved_at_8[0x18];
5352
5353         u8         syndrome[0x20];
5354
5355         u8         reserved_at_40[0x40];
5356 };
5357
5358 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5359         u8         opcode[0x10];
5360         u8         reserved_at_10[0x10];
5361
5362         u8         reserved_at_20[0x10];
5363         u8         op_mod[0x10];
5364
5365         u8         reserved_at_40[0x10];
5366         u8         function_id[0x10];
5367         u8         field_select[0x20];
5368
5369         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5370 };
5371
5372 struct mlx5_ifc_flow_table_context_bits {
5373         u8         reformat_en[0x1];
5374         u8         decap_en[0x1];
5375         u8         sw_owner[0x1];
5376         u8         termination_table[0x1];
5377         u8         table_miss_action[0x4];
5378         u8         level[0x8];
5379         u8         reserved_at_10[0x8];
5380         u8         log_size[0x8];
5381
5382         u8         reserved_at_20[0x8];
5383         u8         table_miss_id[0x18];
5384
5385         u8         reserved_at_40[0x8];
5386         u8         lag_master_next_table_id[0x18];
5387
5388         u8         reserved_at_60[0x60];
5389
5390         u8         sw_owner_icm_root_1[0x40];
5391
5392         u8         sw_owner_icm_root_0[0x40];
5393
5394 };
5395
5396 struct mlx5_ifc_query_flow_table_out_bits {
5397         u8         status[0x8];
5398         u8         reserved_at_8[0x18];
5399
5400         u8         syndrome[0x20];
5401
5402         u8         reserved_at_40[0x80];
5403
5404         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5405 };
5406
5407 struct mlx5_ifc_query_flow_table_in_bits {
5408         u8         opcode[0x10];
5409         u8         reserved_at_10[0x10];
5410
5411         u8         reserved_at_20[0x10];
5412         u8         op_mod[0x10];
5413
5414         u8         reserved_at_40[0x40];
5415
5416         u8         table_type[0x8];
5417         u8         reserved_at_88[0x18];
5418
5419         u8         reserved_at_a0[0x8];
5420         u8         table_id[0x18];
5421
5422         u8         reserved_at_c0[0x140];
5423 };
5424
5425 struct mlx5_ifc_query_fte_out_bits {
5426         u8         status[0x8];
5427         u8         reserved_at_8[0x18];
5428
5429         u8         syndrome[0x20];
5430
5431         u8         reserved_at_40[0x1c0];
5432
5433         struct mlx5_ifc_flow_context_bits flow_context;
5434 };
5435
5436 struct mlx5_ifc_query_fte_in_bits {
5437         u8         opcode[0x10];
5438         u8         reserved_at_10[0x10];
5439
5440         u8         reserved_at_20[0x10];
5441         u8         op_mod[0x10];
5442
5443         u8         reserved_at_40[0x40];
5444
5445         u8         table_type[0x8];
5446         u8         reserved_at_88[0x18];
5447
5448         u8         reserved_at_a0[0x8];
5449         u8         table_id[0x18];
5450
5451         u8         reserved_at_c0[0x40];
5452
5453         u8         flow_index[0x20];
5454
5455         u8         reserved_at_120[0xe0];
5456 };
5457
5458 enum {
5459         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5460         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5461         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5462         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5463         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5464 };
5465
5466 struct mlx5_ifc_query_flow_group_out_bits {
5467         u8         status[0x8];
5468         u8         reserved_at_8[0x18];
5469
5470         u8         syndrome[0x20];
5471
5472         u8         reserved_at_40[0xa0];
5473
5474         u8         start_flow_index[0x20];
5475
5476         u8         reserved_at_100[0x20];
5477
5478         u8         end_flow_index[0x20];
5479
5480         u8         reserved_at_140[0xa0];
5481
5482         u8         reserved_at_1e0[0x18];
5483         u8         match_criteria_enable[0x8];
5484
5485         struct mlx5_ifc_fte_match_param_bits match_criteria;
5486
5487         u8         reserved_at_1200[0xe00];
5488 };
5489
5490 struct mlx5_ifc_query_flow_group_in_bits {
5491         u8         opcode[0x10];
5492         u8         reserved_at_10[0x10];
5493
5494         u8         reserved_at_20[0x10];
5495         u8         op_mod[0x10];
5496
5497         u8         reserved_at_40[0x40];
5498
5499         u8         table_type[0x8];
5500         u8         reserved_at_88[0x18];
5501
5502         u8         reserved_at_a0[0x8];
5503         u8         table_id[0x18];
5504
5505         u8         group_id[0x20];
5506
5507         u8         reserved_at_e0[0x120];
5508 };
5509
5510 struct mlx5_ifc_query_flow_counter_out_bits {
5511         u8         status[0x8];
5512         u8         reserved_at_8[0x18];
5513
5514         u8         syndrome[0x20];
5515
5516         u8         reserved_at_40[0x40];
5517
5518         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
5519 };
5520
5521 struct mlx5_ifc_query_flow_counter_in_bits {
5522         u8         opcode[0x10];
5523         u8         reserved_at_10[0x10];
5524
5525         u8         reserved_at_20[0x10];
5526         u8         op_mod[0x10];
5527
5528         u8         reserved_at_40[0x80];
5529
5530         u8         clear[0x1];
5531         u8         reserved_at_c1[0xf];
5532         u8         num_of_counters[0x10];
5533
5534         u8         flow_counter_id[0x20];
5535 };
5536
5537 struct mlx5_ifc_query_esw_vport_context_out_bits {
5538         u8         status[0x8];
5539         u8         reserved_at_8[0x18];
5540
5541         u8         syndrome[0x20];
5542
5543         u8         reserved_at_40[0x40];
5544
5545         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5546 };
5547
5548 struct mlx5_ifc_query_esw_vport_context_in_bits {
5549         u8         opcode[0x10];
5550         u8         reserved_at_10[0x10];
5551
5552         u8         reserved_at_20[0x10];
5553         u8         op_mod[0x10];
5554
5555         u8         other_vport[0x1];
5556         u8         reserved_at_41[0xf];
5557         u8         vport_number[0x10];
5558
5559         u8         reserved_at_60[0x20];
5560 };
5561
5562 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5563         u8         status[0x8];
5564         u8         reserved_at_8[0x18];
5565
5566         u8         syndrome[0x20];
5567
5568         u8         reserved_at_40[0x40];
5569 };
5570
5571 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5572         u8         reserved_at_0[0x1b];
5573         u8         fdb_to_vport_reg_c_id[0x1];
5574         u8         vport_cvlan_insert[0x1];
5575         u8         vport_svlan_insert[0x1];
5576         u8         vport_cvlan_strip[0x1];
5577         u8         vport_svlan_strip[0x1];
5578 };
5579
5580 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5581         u8         opcode[0x10];
5582         u8         reserved_at_10[0x10];
5583
5584         u8         reserved_at_20[0x10];
5585         u8         op_mod[0x10];
5586
5587         u8         other_vport[0x1];
5588         u8         reserved_at_41[0xf];
5589         u8         vport_number[0x10];
5590
5591         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5592
5593         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5594 };
5595
5596 struct mlx5_ifc_query_eq_out_bits {
5597         u8         status[0x8];
5598         u8         reserved_at_8[0x18];
5599
5600         u8         syndrome[0x20];
5601
5602         u8         reserved_at_40[0x40];
5603
5604         struct mlx5_ifc_eqc_bits eq_context_entry;
5605
5606         u8         reserved_at_280[0x40];
5607
5608         u8         event_bitmask[0x40];
5609
5610         u8         reserved_at_300[0x580];
5611
5612         u8         pas[][0x40];
5613 };
5614
5615 struct mlx5_ifc_query_eq_in_bits {
5616         u8         opcode[0x10];
5617         u8         reserved_at_10[0x10];
5618
5619         u8         reserved_at_20[0x10];
5620         u8         op_mod[0x10];
5621
5622         u8         reserved_at_40[0x18];
5623         u8         eq_number[0x8];
5624
5625         u8         reserved_at_60[0x20];
5626 };
5627
5628 struct mlx5_ifc_packet_reformat_context_in_bits {
5629         u8         reserved_at_0[0x5];
5630         u8         reformat_type[0x3];
5631         u8         reserved_at_8[0xe];
5632         u8         reformat_data_size[0xa];
5633
5634         u8         reserved_at_20[0x10];
5635         u8         reformat_data[2][0x8];
5636
5637         u8         more_reformat_data[][0x8];
5638 };
5639
5640 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5641         u8         status[0x8];
5642         u8         reserved_at_8[0x18];
5643
5644         u8         syndrome[0x20];
5645
5646         u8         reserved_at_40[0xa0];
5647
5648         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
5649 };
5650
5651 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5652         u8         opcode[0x10];
5653         u8         reserved_at_10[0x10];
5654
5655         u8         reserved_at_20[0x10];
5656         u8         op_mod[0x10];
5657
5658         u8         packet_reformat_id[0x20];
5659
5660         u8         reserved_at_60[0xa0];
5661 };
5662
5663 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5664         u8         status[0x8];
5665         u8         reserved_at_8[0x18];
5666
5667         u8         syndrome[0x20];
5668
5669         u8         packet_reformat_id[0x20];
5670
5671         u8         reserved_at_60[0x20];
5672 };
5673
5674 enum mlx5_reformat_ctx_type {
5675         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5676         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5677         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5678         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5679         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5680 };
5681
5682 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5683         u8         opcode[0x10];
5684         u8         reserved_at_10[0x10];
5685
5686         u8         reserved_at_20[0x10];
5687         u8         op_mod[0x10];
5688
5689         u8         reserved_at_40[0xa0];
5690
5691         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5692 };
5693
5694 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5695         u8         status[0x8];
5696         u8         reserved_at_8[0x18];
5697
5698         u8         syndrome[0x20];
5699
5700         u8         reserved_at_40[0x40];
5701 };
5702
5703 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5704         u8         opcode[0x10];
5705         u8         reserved_at_10[0x10];
5706
5707         u8         reserved_20[0x10];
5708         u8         op_mod[0x10];
5709
5710         u8         packet_reformat_id[0x20];
5711
5712         u8         reserved_60[0x20];
5713 };
5714
5715 struct mlx5_ifc_set_action_in_bits {
5716         u8         action_type[0x4];
5717         u8         field[0xc];
5718         u8         reserved_at_10[0x3];
5719         u8         offset[0x5];
5720         u8         reserved_at_18[0x3];
5721         u8         length[0x5];
5722
5723         u8         data[0x20];
5724 };
5725
5726 struct mlx5_ifc_add_action_in_bits {
5727         u8         action_type[0x4];
5728         u8         field[0xc];
5729         u8         reserved_at_10[0x10];
5730
5731         u8         data[0x20];
5732 };
5733
5734 struct mlx5_ifc_copy_action_in_bits {
5735         u8         action_type[0x4];
5736         u8         src_field[0xc];
5737         u8         reserved_at_10[0x3];
5738         u8         src_offset[0x5];
5739         u8         reserved_at_18[0x3];
5740         u8         length[0x5];
5741
5742         u8         reserved_at_20[0x4];
5743         u8         dst_field[0xc];
5744         u8         reserved_at_30[0x3];
5745         u8         dst_offset[0x5];
5746         u8         reserved_at_38[0x8];
5747 };
5748
5749 union mlx5_ifc_set_add_copy_action_in_auto_bits {
5750         struct mlx5_ifc_set_action_in_bits  set_action_in;
5751         struct mlx5_ifc_add_action_in_bits  add_action_in;
5752         struct mlx5_ifc_copy_action_in_bits copy_action_in;
5753         u8         reserved_at_0[0x40];
5754 };
5755
5756 enum {
5757         MLX5_ACTION_TYPE_SET   = 0x1,
5758         MLX5_ACTION_TYPE_ADD   = 0x2,
5759         MLX5_ACTION_TYPE_COPY  = 0x3,
5760 };
5761
5762 enum {
5763         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5764         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5765         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5766         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5767         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5768         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5769         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5770         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5771         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5772         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5773         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5774         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5775         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5776         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5777         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5778         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5779         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5780         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5781         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5782         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5783         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5784         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5785         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5786         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5787         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5788         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5789         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5790         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5791         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5792         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
5793         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
5794         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
5795         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
5796         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
5797         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
5798         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
5799         MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
5800 };
5801
5802 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5803         u8         status[0x8];
5804         u8         reserved_at_8[0x18];
5805
5806         u8         syndrome[0x20];
5807
5808         u8         modify_header_id[0x20];
5809
5810         u8         reserved_at_60[0x20];
5811 };
5812
5813 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5814         u8         opcode[0x10];
5815         u8         reserved_at_10[0x10];
5816
5817         u8         reserved_at_20[0x10];
5818         u8         op_mod[0x10];
5819
5820         u8         reserved_at_40[0x20];
5821
5822         u8         table_type[0x8];
5823         u8         reserved_at_68[0x10];
5824         u8         num_of_actions[0x8];
5825
5826         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
5827 };
5828
5829 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5830         u8         status[0x8];
5831         u8         reserved_at_8[0x18];
5832
5833         u8         syndrome[0x20];
5834
5835         u8         reserved_at_40[0x40];
5836 };
5837
5838 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5839         u8         opcode[0x10];
5840         u8         reserved_at_10[0x10];
5841
5842         u8         reserved_at_20[0x10];
5843         u8         op_mod[0x10];
5844
5845         u8         modify_header_id[0x20];
5846
5847         u8         reserved_at_60[0x20];
5848 };
5849
5850 struct mlx5_ifc_query_dct_out_bits {
5851         u8         status[0x8];
5852         u8         reserved_at_8[0x18];
5853
5854         u8         syndrome[0x20];
5855
5856         u8         reserved_at_40[0x40];
5857
5858         struct mlx5_ifc_dctc_bits dct_context_entry;
5859
5860         u8         reserved_at_280[0x180];
5861 };
5862
5863 struct mlx5_ifc_query_dct_in_bits {
5864         u8         opcode[0x10];
5865         u8         reserved_at_10[0x10];
5866
5867         u8         reserved_at_20[0x10];
5868         u8         op_mod[0x10];
5869
5870         u8         reserved_at_40[0x8];
5871         u8         dctn[0x18];
5872
5873         u8         reserved_at_60[0x20];
5874 };
5875
5876 struct mlx5_ifc_query_cq_out_bits {
5877         u8         status[0x8];
5878         u8         reserved_at_8[0x18];
5879
5880         u8         syndrome[0x20];
5881
5882         u8         reserved_at_40[0x40];
5883
5884         struct mlx5_ifc_cqc_bits cq_context;
5885
5886         u8         reserved_at_280[0x600];
5887
5888         u8         pas[][0x40];
5889 };
5890
5891 struct mlx5_ifc_query_cq_in_bits {
5892         u8         opcode[0x10];
5893         u8         reserved_at_10[0x10];
5894
5895         u8         reserved_at_20[0x10];
5896         u8         op_mod[0x10];
5897
5898         u8         reserved_at_40[0x8];
5899         u8         cqn[0x18];
5900
5901         u8         reserved_at_60[0x20];
5902 };
5903
5904 struct mlx5_ifc_query_cong_status_out_bits {
5905         u8         status[0x8];
5906         u8         reserved_at_8[0x18];
5907
5908         u8         syndrome[0x20];
5909
5910         u8         reserved_at_40[0x20];
5911
5912         u8         enable[0x1];
5913         u8         tag_enable[0x1];
5914         u8         reserved_at_62[0x1e];
5915 };
5916
5917 struct mlx5_ifc_query_cong_status_in_bits {
5918         u8         opcode[0x10];
5919         u8         reserved_at_10[0x10];
5920
5921         u8         reserved_at_20[0x10];
5922         u8         op_mod[0x10];
5923
5924         u8         reserved_at_40[0x18];
5925         u8         priority[0x4];
5926         u8         cong_protocol[0x4];
5927
5928         u8         reserved_at_60[0x20];
5929 };
5930
5931 struct mlx5_ifc_query_cong_statistics_out_bits {
5932         u8         status[0x8];
5933         u8         reserved_at_8[0x18];
5934
5935         u8         syndrome[0x20];
5936
5937         u8         reserved_at_40[0x40];
5938
5939         u8         rp_cur_flows[0x20];
5940
5941         u8         sum_flows[0x20];
5942
5943         u8         rp_cnp_ignored_high[0x20];
5944
5945         u8         rp_cnp_ignored_low[0x20];
5946
5947         u8         rp_cnp_handled_high[0x20];
5948
5949         u8         rp_cnp_handled_low[0x20];
5950
5951         u8         reserved_at_140[0x100];
5952
5953         u8         time_stamp_high[0x20];
5954
5955         u8         time_stamp_low[0x20];
5956
5957         u8         accumulators_period[0x20];
5958
5959         u8         np_ecn_marked_roce_packets_high[0x20];
5960
5961         u8         np_ecn_marked_roce_packets_low[0x20];
5962
5963         u8         np_cnp_sent_high[0x20];
5964
5965         u8         np_cnp_sent_low[0x20];
5966
5967         u8         reserved_at_320[0x560];
5968 };
5969
5970 struct mlx5_ifc_query_cong_statistics_in_bits {
5971         u8         opcode[0x10];
5972         u8         reserved_at_10[0x10];
5973
5974         u8         reserved_at_20[0x10];
5975         u8         op_mod[0x10];
5976
5977         u8         clear[0x1];
5978         u8         reserved_at_41[0x1f];
5979
5980         u8         reserved_at_60[0x20];
5981 };
5982
5983 struct mlx5_ifc_query_cong_params_out_bits {
5984         u8         status[0x8];
5985         u8         reserved_at_8[0x18];
5986
5987         u8         syndrome[0x20];
5988
5989         u8         reserved_at_40[0x40];
5990
5991         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5992 };
5993
5994 struct mlx5_ifc_query_cong_params_in_bits {
5995         u8         opcode[0x10];
5996         u8         reserved_at_10[0x10];
5997
5998         u8         reserved_at_20[0x10];
5999         u8         op_mod[0x10];
6000
6001         u8         reserved_at_40[0x1c];
6002         u8         cong_protocol[0x4];
6003
6004         u8         reserved_at_60[0x20];
6005 };
6006
6007 struct mlx5_ifc_query_adapter_out_bits {
6008         u8         status[0x8];
6009         u8         reserved_at_8[0x18];
6010
6011         u8         syndrome[0x20];
6012
6013         u8         reserved_at_40[0x40];
6014
6015         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6016 };
6017
6018 struct mlx5_ifc_query_adapter_in_bits {
6019         u8         opcode[0x10];
6020         u8         reserved_at_10[0x10];
6021
6022         u8         reserved_at_20[0x10];
6023         u8         op_mod[0x10];
6024
6025         u8         reserved_at_40[0x40];
6026 };
6027
6028 struct mlx5_ifc_qp_2rst_out_bits {
6029         u8         status[0x8];
6030         u8         reserved_at_8[0x18];
6031
6032         u8         syndrome[0x20];
6033
6034         u8         reserved_at_40[0x40];
6035 };
6036
6037 struct mlx5_ifc_qp_2rst_in_bits {
6038         u8         opcode[0x10];
6039         u8         uid[0x10];
6040
6041         u8         reserved_at_20[0x10];
6042         u8         op_mod[0x10];
6043
6044         u8         reserved_at_40[0x8];
6045         u8         qpn[0x18];
6046
6047         u8         reserved_at_60[0x20];
6048 };
6049
6050 struct mlx5_ifc_qp_2err_out_bits {
6051         u8         status[0x8];
6052         u8         reserved_at_8[0x18];
6053
6054         u8         syndrome[0x20];
6055
6056         u8         reserved_at_40[0x40];
6057 };
6058
6059 struct mlx5_ifc_qp_2err_in_bits {
6060         u8         opcode[0x10];
6061         u8         uid[0x10];
6062
6063         u8         reserved_at_20[0x10];
6064         u8         op_mod[0x10];
6065
6066         u8         reserved_at_40[0x8];
6067         u8         qpn[0x18];
6068
6069         u8         reserved_at_60[0x20];
6070 };
6071
6072 struct mlx5_ifc_page_fault_resume_out_bits {
6073         u8         status[0x8];
6074         u8         reserved_at_8[0x18];
6075
6076         u8         syndrome[0x20];
6077
6078         u8         reserved_at_40[0x40];
6079 };
6080
6081 struct mlx5_ifc_page_fault_resume_in_bits {
6082         u8         opcode[0x10];
6083         u8         reserved_at_10[0x10];
6084
6085         u8         reserved_at_20[0x10];
6086         u8         op_mod[0x10];
6087
6088         u8         error[0x1];
6089         u8         reserved_at_41[0x4];
6090         u8         page_fault_type[0x3];
6091         u8         wq_number[0x18];
6092
6093         u8         reserved_at_60[0x8];
6094         u8         token[0x18];
6095 };
6096
6097 struct mlx5_ifc_nop_out_bits {
6098         u8         status[0x8];
6099         u8         reserved_at_8[0x18];
6100
6101         u8         syndrome[0x20];
6102
6103         u8         reserved_at_40[0x40];
6104 };
6105
6106 struct mlx5_ifc_nop_in_bits {
6107         u8         opcode[0x10];
6108         u8         reserved_at_10[0x10];
6109
6110         u8         reserved_at_20[0x10];
6111         u8         op_mod[0x10];
6112
6113         u8         reserved_at_40[0x40];
6114 };
6115
6116 struct mlx5_ifc_modify_vport_state_out_bits {
6117         u8         status[0x8];
6118         u8         reserved_at_8[0x18];
6119
6120         u8         syndrome[0x20];
6121
6122         u8         reserved_at_40[0x40];
6123 };
6124
6125 struct mlx5_ifc_modify_vport_state_in_bits {
6126         u8         opcode[0x10];
6127         u8         reserved_at_10[0x10];
6128
6129         u8         reserved_at_20[0x10];
6130         u8         op_mod[0x10];
6131
6132         u8         other_vport[0x1];
6133         u8         reserved_at_41[0xf];
6134         u8         vport_number[0x10];
6135
6136         u8         reserved_at_60[0x18];
6137         u8         admin_state[0x4];
6138         u8         reserved_at_7c[0x4];
6139 };
6140
6141 struct mlx5_ifc_modify_tis_out_bits {
6142         u8         status[0x8];
6143         u8         reserved_at_8[0x18];
6144
6145         u8         syndrome[0x20];
6146
6147         u8         reserved_at_40[0x40];
6148 };
6149
6150 struct mlx5_ifc_modify_tis_bitmask_bits {
6151         u8         reserved_at_0[0x20];
6152
6153         u8         reserved_at_20[0x1d];
6154         u8         lag_tx_port_affinity[0x1];
6155         u8         strict_lag_tx_port_affinity[0x1];
6156         u8         prio[0x1];
6157 };
6158
6159 struct mlx5_ifc_modify_tis_in_bits {
6160         u8         opcode[0x10];
6161         u8         uid[0x10];
6162
6163         u8         reserved_at_20[0x10];
6164         u8         op_mod[0x10];
6165
6166         u8         reserved_at_40[0x8];
6167         u8         tisn[0x18];
6168
6169         u8         reserved_at_60[0x20];
6170
6171         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6172
6173         u8         reserved_at_c0[0x40];
6174
6175         struct mlx5_ifc_tisc_bits ctx;
6176 };
6177
6178 struct mlx5_ifc_modify_tir_bitmask_bits {
6179         u8         reserved_at_0[0x20];
6180
6181         u8         reserved_at_20[0x1b];
6182         u8         self_lb_en[0x1];
6183         u8         reserved_at_3c[0x1];
6184         u8         hash[0x1];
6185         u8         reserved_at_3e[0x1];
6186         u8         lro[0x1];
6187 };
6188
6189 struct mlx5_ifc_modify_tir_out_bits {
6190         u8         status[0x8];
6191         u8         reserved_at_8[0x18];
6192
6193         u8         syndrome[0x20];
6194
6195         u8         reserved_at_40[0x40];
6196 };
6197
6198 struct mlx5_ifc_modify_tir_in_bits {
6199         u8         opcode[0x10];
6200         u8         uid[0x10];
6201
6202         u8         reserved_at_20[0x10];
6203         u8         op_mod[0x10];
6204
6205         u8         reserved_at_40[0x8];
6206         u8         tirn[0x18];
6207
6208         u8         reserved_at_60[0x20];
6209
6210         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6211
6212         u8         reserved_at_c0[0x40];
6213
6214         struct mlx5_ifc_tirc_bits ctx;
6215 };
6216
6217 struct mlx5_ifc_modify_sq_out_bits {
6218         u8         status[0x8];
6219         u8         reserved_at_8[0x18];
6220
6221         u8         syndrome[0x20];
6222
6223         u8         reserved_at_40[0x40];
6224 };
6225
6226 struct mlx5_ifc_modify_sq_in_bits {
6227         u8         opcode[0x10];
6228         u8         uid[0x10];
6229
6230         u8         reserved_at_20[0x10];
6231         u8         op_mod[0x10];
6232
6233         u8         sq_state[0x4];
6234         u8         reserved_at_44[0x4];
6235         u8         sqn[0x18];
6236
6237         u8         reserved_at_60[0x20];
6238
6239         u8         modify_bitmask[0x40];
6240
6241         u8         reserved_at_c0[0x40];
6242
6243         struct mlx5_ifc_sqc_bits ctx;
6244 };
6245
6246 struct mlx5_ifc_modify_scheduling_element_out_bits {
6247         u8         status[0x8];
6248         u8         reserved_at_8[0x18];
6249
6250         u8         syndrome[0x20];
6251
6252         u8         reserved_at_40[0x1c0];
6253 };
6254
6255 enum {
6256         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6257         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6258 };
6259
6260 struct mlx5_ifc_modify_scheduling_element_in_bits {
6261         u8         opcode[0x10];
6262         u8         reserved_at_10[0x10];
6263
6264         u8         reserved_at_20[0x10];
6265         u8         op_mod[0x10];
6266
6267         u8         scheduling_hierarchy[0x8];
6268         u8         reserved_at_48[0x18];
6269
6270         u8         scheduling_element_id[0x20];
6271
6272         u8         reserved_at_80[0x20];
6273
6274         u8         modify_bitmask[0x20];
6275
6276         u8         reserved_at_c0[0x40];
6277
6278         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6279
6280         u8         reserved_at_300[0x100];
6281 };
6282
6283 struct mlx5_ifc_modify_rqt_out_bits {
6284         u8         status[0x8];
6285         u8         reserved_at_8[0x18];
6286
6287         u8         syndrome[0x20];
6288
6289         u8         reserved_at_40[0x40];
6290 };
6291
6292 struct mlx5_ifc_rqt_bitmask_bits {
6293         u8         reserved_at_0[0x20];
6294
6295         u8         reserved_at_20[0x1f];
6296         u8         rqn_list[0x1];
6297 };
6298
6299 struct mlx5_ifc_modify_rqt_in_bits {
6300         u8         opcode[0x10];
6301         u8         uid[0x10];
6302
6303         u8         reserved_at_20[0x10];
6304         u8         op_mod[0x10];
6305
6306         u8         reserved_at_40[0x8];
6307         u8         rqtn[0x18];
6308
6309         u8         reserved_at_60[0x20];
6310
6311         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6312
6313         u8         reserved_at_c0[0x40];
6314
6315         struct mlx5_ifc_rqtc_bits ctx;
6316 };
6317
6318 struct mlx5_ifc_modify_rq_out_bits {
6319         u8         status[0x8];
6320         u8         reserved_at_8[0x18];
6321
6322         u8         syndrome[0x20];
6323
6324         u8         reserved_at_40[0x40];
6325 };
6326
6327 enum {
6328         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6329         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6330         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6331 };
6332
6333 struct mlx5_ifc_modify_rq_in_bits {
6334         u8         opcode[0x10];
6335         u8         uid[0x10];
6336
6337         u8         reserved_at_20[0x10];
6338         u8         op_mod[0x10];
6339
6340         u8         rq_state[0x4];
6341         u8         reserved_at_44[0x4];
6342         u8         rqn[0x18];
6343
6344         u8         reserved_at_60[0x20];
6345
6346         u8         modify_bitmask[0x40];
6347
6348         u8         reserved_at_c0[0x40];
6349
6350         struct mlx5_ifc_rqc_bits ctx;
6351 };
6352
6353 struct mlx5_ifc_modify_rmp_out_bits {
6354         u8         status[0x8];
6355         u8         reserved_at_8[0x18];
6356
6357         u8         syndrome[0x20];
6358
6359         u8         reserved_at_40[0x40];
6360 };
6361
6362 struct mlx5_ifc_rmp_bitmask_bits {
6363         u8         reserved_at_0[0x20];
6364
6365         u8         reserved_at_20[0x1f];
6366         u8         lwm[0x1];
6367 };
6368
6369 struct mlx5_ifc_modify_rmp_in_bits {
6370         u8         opcode[0x10];
6371         u8         uid[0x10];
6372
6373         u8         reserved_at_20[0x10];
6374         u8         op_mod[0x10];
6375
6376         u8         rmp_state[0x4];
6377         u8         reserved_at_44[0x4];
6378         u8         rmpn[0x18];
6379
6380         u8         reserved_at_60[0x20];
6381
6382         struct mlx5_ifc_rmp_bitmask_bits bitmask;
6383
6384         u8         reserved_at_c0[0x40];
6385
6386         struct mlx5_ifc_rmpc_bits ctx;
6387 };
6388
6389 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6390         u8         status[0x8];
6391         u8         reserved_at_8[0x18];
6392
6393         u8         syndrome[0x20];
6394
6395         u8         reserved_at_40[0x40];
6396 };
6397
6398 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6399         u8         reserved_at_0[0x12];
6400         u8         affiliation[0x1];
6401         u8         reserved_at_13[0x1];
6402         u8         disable_uc_local_lb[0x1];
6403         u8         disable_mc_local_lb[0x1];
6404         u8         node_guid[0x1];
6405         u8         port_guid[0x1];
6406         u8         min_inline[0x1];
6407         u8         mtu[0x1];
6408         u8         change_event[0x1];
6409         u8         promisc[0x1];
6410         u8         permanent_address[0x1];
6411         u8         addresses_list[0x1];
6412         u8         roce_en[0x1];
6413         u8         reserved_at_1f[0x1];
6414 };
6415
6416 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6417         u8         opcode[0x10];
6418         u8         reserved_at_10[0x10];
6419
6420         u8         reserved_at_20[0x10];
6421         u8         op_mod[0x10];
6422
6423         u8         other_vport[0x1];
6424         u8         reserved_at_41[0xf];
6425         u8         vport_number[0x10];
6426
6427         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6428
6429         u8         reserved_at_80[0x780];
6430
6431         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6432 };
6433
6434 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6435         u8         status[0x8];
6436         u8         reserved_at_8[0x18];
6437
6438         u8         syndrome[0x20];
6439
6440         u8         reserved_at_40[0x40];
6441 };
6442
6443 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6444         u8         opcode[0x10];
6445         u8         reserved_at_10[0x10];
6446
6447         u8         reserved_at_20[0x10];
6448         u8         op_mod[0x10];
6449
6450         u8         other_vport[0x1];
6451         u8         reserved_at_41[0xb];
6452         u8         port_num[0x4];
6453         u8         vport_number[0x10];
6454
6455         u8         reserved_at_60[0x20];
6456
6457         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6458 };
6459
6460 struct mlx5_ifc_modify_cq_out_bits {
6461         u8         status[0x8];
6462         u8         reserved_at_8[0x18];
6463
6464         u8         syndrome[0x20];
6465
6466         u8         reserved_at_40[0x40];
6467 };
6468
6469 enum {
6470         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6471         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6472 };
6473
6474 struct mlx5_ifc_modify_cq_in_bits {
6475         u8         opcode[0x10];
6476         u8         uid[0x10];
6477
6478         u8         reserved_at_20[0x10];
6479         u8         op_mod[0x10];
6480
6481         u8         reserved_at_40[0x8];
6482         u8         cqn[0x18];
6483
6484         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6485
6486         struct mlx5_ifc_cqc_bits cq_context;
6487
6488         u8         reserved_at_280[0x60];
6489
6490         u8         cq_umem_valid[0x1];
6491         u8         reserved_at_2e1[0x1f];
6492
6493         u8         reserved_at_300[0x580];
6494
6495         u8         pas[][0x40];
6496 };
6497
6498 struct mlx5_ifc_modify_cong_status_out_bits {
6499         u8         status[0x8];
6500         u8         reserved_at_8[0x18];
6501
6502         u8         syndrome[0x20];
6503
6504         u8         reserved_at_40[0x40];
6505 };
6506
6507 struct mlx5_ifc_modify_cong_status_in_bits {
6508         u8         opcode[0x10];
6509         u8         reserved_at_10[0x10];
6510
6511         u8         reserved_at_20[0x10];
6512         u8         op_mod[0x10];
6513
6514         u8         reserved_at_40[0x18];
6515         u8         priority[0x4];
6516         u8         cong_protocol[0x4];
6517
6518         u8         enable[0x1];
6519         u8         tag_enable[0x1];
6520         u8         reserved_at_62[0x1e];
6521 };
6522
6523 struct mlx5_ifc_modify_cong_params_out_bits {
6524         u8         status[0x8];
6525         u8         reserved_at_8[0x18];
6526
6527         u8         syndrome[0x20];
6528
6529         u8         reserved_at_40[0x40];
6530 };
6531
6532 struct mlx5_ifc_modify_cong_params_in_bits {
6533         u8         opcode[0x10];
6534         u8         reserved_at_10[0x10];
6535
6536         u8         reserved_at_20[0x10];
6537         u8         op_mod[0x10];
6538
6539         u8         reserved_at_40[0x1c];
6540         u8         cong_protocol[0x4];
6541
6542         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6543
6544         u8         reserved_at_80[0x80];
6545
6546         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6547 };
6548
6549 struct mlx5_ifc_manage_pages_out_bits {
6550         u8         status[0x8];
6551         u8         reserved_at_8[0x18];
6552
6553         u8         syndrome[0x20];
6554
6555         u8         output_num_entries[0x20];
6556
6557         u8         reserved_at_60[0x20];
6558
6559         u8         pas[][0x40];
6560 };
6561
6562 enum {
6563         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6564         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6565         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6566 };
6567
6568 struct mlx5_ifc_manage_pages_in_bits {
6569         u8         opcode[0x10];
6570         u8         reserved_at_10[0x10];
6571
6572         u8         reserved_at_20[0x10];
6573         u8         op_mod[0x10];
6574
6575         u8         embedded_cpu_function[0x1];
6576         u8         reserved_at_41[0xf];
6577         u8         function_id[0x10];
6578
6579         u8         input_num_entries[0x20];
6580
6581         u8         pas[][0x40];
6582 };
6583
6584 struct mlx5_ifc_mad_ifc_out_bits {
6585         u8         status[0x8];
6586         u8         reserved_at_8[0x18];
6587
6588         u8         syndrome[0x20];
6589
6590         u8         reserved_at_40[0x40];
6591
6592         u8         response_mad_packet[256][0x8];
6593 };
6594
6595 struct mlx5_ifc_mad_ifc_in_bits {
6596         u8         opcode[0x10];
6597         u8         reserved_at_10[0x10];
6598
6599         u8         reserved_at_20[0x10];
6600         u8         op_mod[0x10];
6601
6602         u8         remote_lid[0x10];
6603         u8         reserved_at_50[0x8];
6604         u8         port[0x8];
6605
6606         u8         reserved_at_60[0x20];
6607
6608         u8         mad[256][0x8];
6609 };
6610
6611 struct mlx5_ifc_init_hca_out_bits {
6612         u8         status[0x8];
6613         u8         reserved_at_8[0x18];
6614
6615         u8         syndrome[0x20];
6616
6617         u8         reserved_at_40[0x40];
6618 };
6619
6620 struct mlx5_ifc_init_hca_in_bits {
6621         u8         opcode[0x10];
6622         u8         reserved_at_10[0x10];
6623
6624         u8         reserved_at_20[0x10];
6625         u8         op_mod[0x10];
6626
6627         u8         reserved_at_40[0x40];
6628         u8         sw_owner_id[4][0x20];
6629 };
6630
6631 struct mlx5_ifc_init2rtr_qp_out_bits {
6632         u8         status[0x8];
6633         u8         reserved_at_8[0x18];
6634
6635         u8         syndrome[0x20];
6636
6637         u8         reserved_at_40[0x20];
6638         u8         ece[0x20];
6639 };
6640
6641 struct mlx5_ifc_init2rtr_qp_in_bits {
6642         u8         opcode[0x10];
6643         u8         uid[0x10];
6644
6645         u8         reserved_at_20[0x10];
6646         u8         op_mod[0x10];
6647
6648         u8         reserved_at_40[0x8];
6649         u8         qpn[0x18];
6650
6651         u8         reserved_at_60[0x20];
6652
6653         u8         opt_param_mask[0x20];
6654
6655         u8         ece[0x20];
6656
6657         struct mlx5_ifc_qpc_bits qpc;
6658
6659         u8         reserved_at_800[0x80];
6660 };
6661
6662 struct mlx5_ifc_init2init_qp_out_bits {
6663         u8         status[0x8];
6664         u8         reserved_at_8[0x18];
6665
6666         u8         syndrome[0x20];
6667
6668         u8         reserved_at_40[0x20];
6669         u8         ece[0x20];
6670 };
6671
6672 struct mlx5_ifc_init2init_qp_in_bits {
6673         u8         opcode[0x10];
6674         u8         uid[0x10];
6675
6676         u8         reserved_at_20[0x10];
6677         u8         op_mod[0x10];
6678
6679         u8         reserved_at_40[0x8];
6680         u8         qpn[0x18];
6681
6682         u8         reserved_at_60[0x20];
6683
6684         u8         opt_param_mask[0x20];
6685
6686         u8         ece[0x20];
6687
6688         struct mlx5_ifc_qpc_bits qpc;
6689
6690         u8         reserved_at_800[0x80];
6691 };
6692
6693 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6694         u8         status[0x8];
6695         u8         reserved_at_8[0x18];
6696
6697         u8         syndrome[0x20];
6698
6699         u8         reserved_at_40[0x40];
6700
6701         u8         packet_headers_log[128][0x8];
6702
6703         u8         packet_syndrome[64][0x8];
6704 };
6705
6706 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6707         u8         opcode[0x10];
6708         u8         reserved_at_10[0x10];
6709
6710         u8         reserved_at_20[0x10];
6711         u8         op_mod[0x10];
6712
6713         u8         reserved_at_40[0x40];
6714 };
6715
6716 struct mlx5_ifc_gen_eqe_in_bits {
6717         u8         opcode[0x10];
6718         u8         reserved_at_10[0x10];
6719
6720         u8         reserved_at_20[0x10];
6721         u8         op_mod[0x10];
6722
6723         u8         reserved_at_40[0x18];
6724         u8         eq_number[0x8];
6725
6726         u8         reserved_at_60[0x20];
6727
6728         u8         eqe[64][0x8];
6729 };
6730
6731 struct mlx5_ifc_gen_eq_out_bits {
6732         u8         status[0x8];
6733         u8         reserved_at_8[0x18];
6734
6735         u8         syndrome[0x20];
6736
6737         u8         reserved_at_40[0x40];
6738 };
6739
6740 struct mlx5_ifc_enable_hca_out_bits {
6741         u8         status[0x8];
6742         u8         reserved_at_8[0x18];
6743
6744         u8         syndrome[0x20];
6745
6746         u8         reserved_at_40[0x20];
6747 };
6748
6749 struct mlx5_ifc_enable_hca_in_bits {
6750         u8         opcode[0x10];
6751         u8         reserved_at_10[0x10];
6752
6753         u8         reserved_at_20[0x10];
6754         u8         op_mod[0x10];
6755
6756         u8         embedded_cpu_function[0x1];
6757         u8         reserved_at_41[0xf];
6758         u8         function_id[0x10];
6759
6760         u8         reserved_at_60[0x20];
6761 };
6762
6763 struct mlx5_ifc_drain_dct_out_bits {
6764         u8         status[0x8];
6765         u8         reserved_at_8[0x18];
6766
6767         u8         syndrome[0x20];
6768
6769         u8         reserved_at_40[0x40];
6770 };
6771
6772 struct mlx5_ifc_drain_dct_in_bits {
6773         u8         opcode[0x10];
6774         u8         uid[0x10];
6775
6776         u8         reserved_at_20[0x10];
6777         u8         op_mod[0x10];
6778
6779         u8         reserved_at_40[0x8];
6780         u8         dctn[0x18];
6781
6782         u8         reserved_at_60[0x20];
6783 };
6784
6785 struct mlx5_ifc_disable_hca_out_bits {
6786         u8         status[0x8];
6787         u8         reserved_at_8[0x18];
6788
6789         u8         syndrome[0x20];
6790
6791         u8         reserved_at_40[0x20];
6792 };
6793
6794 struct mlx5_ifc_disable_hca_in_bits {
6795         u8         opcode[0x10];
6796         u8         reserved_at_10[0x10];
6797
6798         u8         reserved_at_20[0x10];
6799         u8         op_mod[0x10];
6800
6801         u8         embedded_cpu_function[0x1];
6802         u8         reserved_at_41[0xf];
6803         u8         function_id[0x10];
6804
6805         u8         reserved_at_60[0x20];
6806 };
6807
6808 struct mlx5_ifc_detach_from_mcg_out_bits {
6809         u8         status[0x8];
6810         u8         reserved_at_8[0x18];
6811
6812         u8         syndrome[0x20];
6813
6814         u8         reserved_at_40[0x40];
6815 };
6816
6817 struct mlx5_ifc_detach_from_mcg_in_bits {
6818         u8         opcode[0x10];
6819         u8         uid[0x10];
6820
6821         u8         reserved_at_20[0x10];
6822         u8         op_mod[0x10];
6823
6824         u8         reserved_at_40[0x8];
6825         u8         qpn[0x18];
6826
6827         u8         reserved_at_60[0x20];
6828
6829         u8         multicast_gid[16][0x8];
6830 };
6831
6832 struct mlx5_ifc_destroy_xrq_out_bits {
6833         u8         status[0x8];
6834         u8         reserved_at_8[0x18];
6835
6836         u8         syndrome[0x20];
6837
6838         u8         reserved_at_40[0x40];
6839 };
6840
6841 struct mlx5_ifc_destroy_xrq_in_bits {
6842         u8         opcode[0x10];
6843         u8         uid[0x10];
6844
6845         u8         reserved_at_20[0x10];
6846         u8         op_mod[0x10];
6847
6848         u8         reserved_at_40[0x8];
6849         u8         xrqn[0x18];
6850
6851         u8         reserved_at_60[0x20];
6852 };
6853
6854 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6855         u8         status[0x8];
6856         u8         reserved_at_8[0x18];
6857
6858         u8         syndrome[0x20];
6859
6860         u8         reserved_at_40[0x40];
6861 };
6862
6863 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6864         u8         opcode[0x10];
6865         u8         uid[0x10];
6866
6867         u8         reserved_at_20[0x10];
6868         u8         op_mod[0x10];
6869
6870         u8         reserved_at_40[0x8];
6871         u8         xrc_srqn[0x18];
6872
6873         u8         reserved_at_60[0x20];
6874 };
6875
6876 struct mlx5_ifc_destroy_tis_out_bits {
6877         u8         status[0x8];
6878         u8         reserved_at_8[0x18];
6879
6880         u8         syndrome[0x20];
6881
6882         u8         reserved_at_40[0x40];
6883 };
6884
6885 struct mlx5_ifc_destroy_tis_in_bits {
6886         u8         opcode[0x10];
6887         u8         uid[0x10];
6888
6889         u8         reserved_at_20[0x10];
6890         u8         op_mod[0x10];
6891
6892         u8         reserved_at_40[0x8];
6893         u8         tisn[0x18];
6894
6895         u8         reserved_at_60[0x20];
6896 };
6897
6898 struct mlx5_ifc_destroy_tir_out_bits {
6899         u8         status[0x8];
6900         u8         reserved_at_8[0x18];
6901
6902         u8         syndrome[0x20];
6903
6904         u8         reserved_at_40[0x40];
6905 };
6906
6907 struct mlx5_ifc_destroy_tir_in_bits {
6908         u8         opcode[0x10];
6909         u8         uid[0x10];
6910
6911         u8         reserved_at_20[0x10];
6912         u8         op_mod[0x10];
6913
6914         u8         reserved_at_40[0x8];
6915         u8         tirn[0x18];
6916
6917         u8         reserved_at_60[0x20];
6918 };
6919
6920 struct mlx5_ifc_destroy_srq_out_bits {
6921         u8         status[0x8];
6922         u8         reserved_at_8[0x18];
6923
6924         u8         syndrome[0x20];
6925
6926         u8         reserved_at_40[0x40];
6927 };
6928
6929 struct mlx5_ifc_destroy_srq_in_bits {
6930         u8         opcode[0x10];
6931         u8         uid[0x10];
6932
6933         u8         reserved_at_20[0x10];
6934         u8         op_mod[0x10];
6935
6936         u8         reserved_at_40[0x8];
6937         u8         srqn[0x18];
6938
6939         u8         reserved_at_60[0x20];
6940 };
6941
6942 struct mlx5_ifc_destroy_sq_out_bits {
6943         u8         status[0x8];
6944         u8         reserved_at_8[0x18];
6945
6946         u8         syndrome[0x20];
6947
6948         u8         reserved_at_40[0x40];
6949 };
6950
6951 struct mlx5_ifc_destroy_sq_in_bits {
6952         u8         opcode[0x10];
6953         u8         uid[0x10];
6954
6955         u8         reserved_at_20[0x10];
6956         u8         op_mod[0x10];
6957
6958         u8         reserved_at_40[0x8];
6959         u8         sqn[0x18];
6960
6961         u8         reserved_at_60[0x20];
6962 };
6963
6964 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6965         u8         status[0x8];
6966         u8         reserved_at_8[0x18];
6967
6968         u8         syndrome[0x20];
6969
6970         u8         reserved_at_40[0x1c0];
6971 };
6972
6973 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6974         u8         opcode[0x10];
6975         u8         reserved_at_10[0x10];
6976
6977         u8         reserved_at_20[0x10];
6978         u8         op_mod[0x10];
6979
6980         u8         scheduling_hierarchy[0x8];
6981         u8         reserved_at_48[0x18];
6982
6983         u8         scheduling_element_id[0x20];
6984
6985         u8         reserved_at_80[0x180];
6986 };
6987
6988 struct mlx5_ifc_destroy_rqt_out_bits {
6989         u8         status[0x8];
6990         u8         reserved_at_8[0x18];
6991
6992         u8         syndrome[0x20];
6993
6994         u8         reserved_at_40[0x40];
6995 };
6996
6997 struct mlx5_ifc_destroy_rqt_in_bits {
6998         u8         opcode[0x10];
6999         u8         uid[0x10];
7000
7001         u8         reserved_at_20[0x10];
7002         u8         op_mod[0x10];
7003
7004         u8         reserved_at_40[0x8];
7005         u8         rqtn[0x18];
7006
7007         u8         reserved_at_60[0x20];
7008 };
7009
7010 struct mlx5_ifc_destroy_rq_out_bits {
7011         u8         status[0x8];
7012         u8         reserved_at_8[0x18];
7013
7014         u8         syndrome[0x20];
7015
7016         u8         reserved_at_40[0x40];
7017 };
7018
7019 struct mlx5_ifc_destroy_rq_in_bits {
7020         u8         opcode[0x10];
7021         u8         uid[0x10];
7022
7023         u8         reserved_at_20[0x10];
7024         u8         op_mod[0x10];
7025
7026         u8         reserved_at_40[0x8];
7027         u8         rqn[0x18];
7028
7029         u8         reserved_at_60[0x20];
7030 };
7031
7032 struct mlx5_ifc_set_delay_drop_params_in_bits {
7033         u8         opcode[0x10];
7034         u8         reserved_at_10[0x10];
7035
7036         u8         reserved_at_20[0x10];
7037         u8         op_mod[0x10];
7038
7039         u8         reserved_at_40[0x20];
7040
7041         u8         reserved_at_60[0x10];
7042         u8         delay_drop_timeout[0x10];
7043 };
7044
7045 struct mlx5_ifc_set_delay_drop_params_out_bits {
7046         u8         status[0x8];
7047         u8         reserved_at_8[0x18];
7048
7049         u8         syndrome[0x20];
7050
7051         u8         reserved_at_40[0x40];
7052 };
7053
7054 struct mlx5_ifc_destroy_rmp_out_bits {
7055         u8         status[0x8];
7056         u8         reserved_at_8[0x18];
7057
7058         u8         syndrome[0x20];
7059
7060         u8         reserved_at_40[0x40];
7061 };
7062
7063 struct mlx5_ifc_destroy_rmp_in_bits {
7064         u8         opcode[0x10];
7065         u8         uid[0x10];
7066
7067         u8         reserved_at_20[0x10];
7068         u8         op_mod[0x10];
7069
7070         u8         reserved_at_40[0x8];
7071         u8         rmpn[0x18];
7072
7073         u8         reserved_at_60[0x20];
7074 };
7075
7076 struct mlx5_ifc_destroy_qp_out_bits {
7077         u8         status[0x8];
7078         u8         reserved_at_8[0x18];
7079
7080         u8         syndrome[0x20];
7081
7082         u8         reserved_at_40[0x40];
7083 };
7084
7085 struct mlx5_ifc_destroy_qp_in_bits {
7086         u8         opcode[0x10];
7087         u8         uid[0x10];
7088
7089         u8         reserved_at_20[0x10];
7090         u8         op_mod[0x10];
7091
7092         u8         reserved_at_40[0x8];
7093         u8         qpn[0x18];
7094
7095         u8         reserved_at_60[0x20];
7096 };
7097
7098 struct mlx5_ifc_destroy_psv_out_bits {
7099         u8         status[0x8];
7100         u8         reserved_at_8[0x18];
7101
7102         u8         syndrome[0x20];
7103
7104         u8         reserved_at_40[0x40];
7105 };
7106
7107 struct mlx5_ifc_destroy_psv_in_bits {
7108         u8         opcode[0x10];
7109         u8         reserved_at_10[0x10];
7110
7111         u8         reserved_at_20[0x10];
7112         u8         op_mod[0x10];
7113
7114         u8         reserved_at_40[0x8];
7115         u8         psvn[0x18];
7116
7117         u8         reserved_at_60[0x20];
7118 };
7119
7120 struct mlx5_ifc_destroy_mkey_out_bits {
7121         u8         status[0x8];
7122         u8         reserved_at_8[0x18];
7123
7124         u8         syndrome[0x20];
7125
7126         u8         reserved_at_40[0x40];
7127 };
7128
7129 struct mlx5_ifc_destroy_mkey_in_bits {
7130         u8         opcode[0x10];
7131         u8         uid[0x10];
7132
7133         u8         reserved_at_20[0x10];
7134         u8         op_mod[0x10];
7135
7136         u8         reserved_at_40[0x8];
7137         u8         mkey_index[0x18];
7138
7139         u8         reserved_at_60[0x20];
7140 };
7141
7142 struct mlx5_ifc_destroy_flow_table_out_bits {
7143         u8         status[0x8];
7144         u8         reserved_at_8[0x18];
7145
7146         u8         syndrome[0x20];
7147
7148         u8         reserved_at_40[0x40];
7149 };
7150
7151 struct mlx5_ifc_destroy_flow_table_in_bits {
7152         u8         opcode[0x10];
7153         u8         reserved_at_10[0x10];
7154
7155         u8         reserved_at_20[0x10];
7156         u8         op_mod[0x10];
7157
7158         u8         other_vport[0x1];
7159         u8         reserved_at_41[0xf];
7160         u8         vport_number[0x10];
7161
7162         u8         reserved_at_60[0x20];
7163
7164         u8         table_type[0x8];
7165         u8         reserved_at_88[0x18];
7166
7167         u8         reserved_at_a0[0x8];
7168         u8         table_id[0x18];
7169
7170         u8         reserved_at_c0[0x140];
7171 };
7172
7173 struct mlx5_ifc_destroy_flow_group_out_bits {
7174         u8         status[0x8];
7175         u8         reserved_at_8[0x18];
7176
7177         u8         syndrome[0x20];
7178
7179         u8         reserved_at_40[0x40];
7180 };
7181
7182 struct mlx5_ifc_destroy_flow_group_in_bits {
7183         u8         opcode[0x10];
7184         u8         reserved_at_10[0x10];
7185
7186         u8         reserved_at_20[0x10];
7187         u8         op_mod[0x10];
7188
7189         u8         other_vport[0x1];
7190         u8         reserved_at_41[0xf];
7191         u8         vport_number[0x10];
7192
7193         u8         reserved_at_60[0x20];
7194
7195         u8         table_type[0x8];
7196         u8         reserved_at_88[0x18];
7197
7198         u8         reserved_at_a0[0x8];
7199         u8         table_id[0x18];
7200
7201         u8         group_id[0x20];
7202
7203         u8         reserved_at_e0[0x120];
7204 };
7205
7206 struct mlx5_ifc_destroy_eq_out_bits {
7207         u8         status[0x8];
7208         u8         reserved_at_8[0x18];
7209
7210         u8         syndrome[0x20];
7211
7212         u8         reserved_at_40[0x40];
7213 };
7214
7215 struct mlx5_ifc_destroy_eq_in_bits {
7216         u8         opcode[0x10];
7217         u8         reserved_at_10[0x10];
7218
7219         u8         reserved_at_20[0x10];
7220         u8         op_mod[0x10];
7221
7222         u8         reserved_at_40[0x18];
7223         u8         eq_number[0x8];
7224
7225         u8         reserved_at_60[0x20];
7226 };
7227
7228 struct mlx5_ifc_destroy_dct_out_bits {
7229         u8         status[0x8];
7230         u8         reserved_at_8[0x18];
7231
7232         u8         syndrome[0x20];
7233
7234         u8         reserved_at_40[0x40];
7235 };
7236
7237 struct mlx5_ifc_destroy_dct_in_bits {
7238         u8         opcode[0x10];
7239         u8         uid[0x10];
7240
7241         u8         reserved_at_20[0x10];
7242         u8         op_mod[0x10];
7243
7244         u8         reserved_at_40[0x8];
7245         u8         dctn[0x18];
7246
7247         u8         reserved_at_60[0x20];
7248 };
7249
7250 struct mlx5_ifc_destroy_cq_out_bits {
7251         u8         status[0x8];
7252         u8         reserved_at_8[0x18];
7253
7254         u8         syndrome[0x20];
7255
7256         u8         reserved_at_40[0x40];
7257 };
7258
7259 struct mlx5_ifc_destroy_cq_in_bits {
7260         u8         opcode[0x10];
7261         u8         uid[0x10];
7262
7263         u8         reserved_at_20[0x10];
7264         u8         op_mod[0x10];
7265
7266         u8         reserved_at_40[0x8];
7267         u8         cqn[0x18];
7268
7269         u8         reserved_at_60[0x20];
7270 };
7271
7272 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7273         u8         status[0x8];
7274         u8         reserved_at_8[0x18];
7275
7276         u8         syndrome[0x20];
7277
7278         u8         reserved_at_40[0x40];
7279 };
7280
7281 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7282         u8         opcode[0x10];
7283         u8         reserved_at_10[0x10];
7284
7285         u8         reserved_at_20[0x10];
7286         u8         op_mod[0x10];
7287
7288         u8         reserved_at_40[0x20];
7289
7290         u8         reserved_at_60[0x10];
7291         u8         vxlan_udp_port[0x10];
7292 };
7293
7294 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7295         u8         status[0x8];
7296         u8         reserved_at_8[0x18];
7297
7298         u8         syndrome[0x20];
7299
7300         u8         reserved_at_40[0x40];
7301 };
7302
7303 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7304         u8         opcode[0x10];
7305         u8         reserved_at_10[0x10];
7306
7307         u8         reserved_at_20[0x10];
7308         u8         op_mod[0x10];
7309
7310         u8         reserved_at_40[0x60];
7311
7312         u8         reserved_at_a0[0x8];
7313         u8         table_index[0x18];
7314
7315         u8         reserved_at_c0[0x140];
7316 };
7317
7318 struct mlx5_ifc_delete_fte_out_bits {
7319         u8         status[0x8];
7320         u8         reserved_at_8[0x18];
7321
7322         u8         syndrome[0x20];
7323
7324         u8         reserved_at_40[0x40];
7325 };
7326
7327 struct mlx5_ifc_delete_fte_in_bits {
7328         u8         opcode[0x10];
7329         u8         reserved_at_10[0x10];
7330
7331         u8         reserved_at_20[0x10];
7332         u8         op_mod[0x10];
7333
7334         u8         other_vport[0x1];
7335         u8         reserved_at_41[0xf];
7336         u8         vport_number[0x10];
7337
7338         u8         reserved_at_60[0x20];
7339
7340         u8         table_type[0x8];
7341         u8         reserved_at_88[0x18];
7342
7343         u8         reserved_at_a0[0x8];
7344         u8         table_id[0x18];
7345
7346         u8         reserved_at_c0[0x40];
7347
7348         u8         flow_index[0x20];
7349
7350         u8         reserved_at_120[0xe0];
7351 };
7352
7353 struct mlx5_ifc_dealloc_xrcd_out_bits {
7354         u8         status[0x8];
7355         u8         reserved_at_8[0x18];
7356
7357         u8         syndrome[0x20];
7358
7359         u8         reserved_at_40[0x40];
7360 };
7361
7362 struct mlx5_ifc_dealloc_xrcd_in_bits {
7363         u8         opcode[0x10];
7364         u8         uid[0x10];
7365
7366         u8         reserved_at_20[0x10];
7367         u8         op_mod[0x10];
7368
7369         u8         reserved_at_40[0x8];
7370         u8         xrcd[0x18];
7371
7372         u8         reserved_at_60[0x20];
7373 };
7374
7375 struct mlx5_ifc_dealloc_uar_out_bits {
7376         u8         status[0x8];
7377         u8         reserved_at_8[0x18];
7378
7379         u8         syndrome[0x20];
7380
7381         u8         reserved_at_40[0x40];
7382 };
7383
7384 struct mlx5_ifc_dealloc_uar_in_bits {
7385         u8         opcode[0x10];
7386         u8         reserved_at_10[0x10];
7387
7388         u8         reserved_at_20[0x10];
7389         u8         op_mod[0x10];
7390
7391         u8         reserved_at_40[0x8];
7392         u8         uar[0x18];
7393
7394         u8         reserved_at_60[0x20];
7395 };
7396
7397 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7398         u8         status[0x8];
7399         u8         reserved_at_8[0x18];
7400
7401         u8         syndrome[0x20];
7402
7403         u8         reserved_at_40[0x40];
7404 };
7405
7406 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7407         u8         opcode[0x10];
7408         u8         uid[0x10];
7409
7410         u8         reserved_at_20[0x10];
7411         u8         op_mod[0x10];
7412
7413         u8         reserved_at_40[0x8];
7414         u8         transport_domain[0x18];
7415
7416         u8         reserved_at_60[0x20];
7417 };
7418
7419 struct mlx5_ifc_dealloc_q_counter_out_bits {
7420         u8         status[0x8];
7421         u8         reserved_at_8[0x18];
7422
7423         u8         syndrome[0x20];
7424
7425         u8         reserved_at_40[0x40];
7426 };
7427
7428 struct mlx5_ifc_dealloc_q_counter_in_bits {
7429         u8         opcode[0x10];
7430         u8         reserved_at_10[0x10];
7431
7432         u8         reserved_at_20[0x10];
7433         u8         op_mod[0x10];
7434
7435         u8         reserved_at_40[0x18];
7436         u8         counter_set_id[0x8];
7437
7438         u8         reserved_at_60[0x20];
7439 };
7440
7441 struct mlx5_ifc_dealloc_pd_out_bits {
7442         u8         status[0x8];
7443         u8         reserved_at_8[0x18];
7444
7445         u8         syndrome[0x20];
7446
7447         u8         reserved_at_40[0x40];
7448 };
7449
7450 struct mlx5_ifc_dealloc_pd_in_bits {
7451         u8         opcode[0x10];
7452         u8         uid[0x10];
7453
7454         u8         reserved_at_20[0x10];
7455         u8         op_mod[0x10];
7456
7457         u8         reserved_at_40[0x8];
7458         u8         pd[0x18];
7459
7460         u8         reserved_at_60[0x20];
7461 };
7462
7463 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7464         u8         status[0x8];
7465         u8         reserved_at_8[0x18];
7466
7467         u8         syndrome[0x20];
7468
7469         u8         reserved_at_40[0x40];
7470 };
7471
7472 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7473         u8         opcode[0x10];
7474         u8         reserved_at_10[0x10];
7475
7476         u8         reserved_at_20[0x10];
7477         u8         op_mod[0x10];
7478
7479         u8         flow_counter_id[0x20];
7480
7481         u8         reserved_at_60[0x20];
7482 };
7483
7484 struct mlx5_ifc_create_xrq_out_bits {
7485         u8         status[0x8];
7486         u8         reserved_at_8[0x18];
7487
7488         u8         syndrome[0x20];
7489
7490         u8         reserved_at_40[0x8];
7491         u8         xrqn[0x18];
7492
7493         u8         reserved_at_60[0x20];
7494 };
7495
7496 struct mlx5_ifc_create_xrq_in_bits {
7497         u8         opcode[0x10];
7498         u8         uid[0x10];
7499
7500         u8         reserved_at_20[0x10];
7501         u8         op_mod[0x10];
7502
7503         u8         reserved_at_40[0x40];
7504
7505         struct mlx5_ifc_xrqc_bits xrq_context;
7506 };
7507
7508 struct mlx5_ifc_create_xrc_srq_out_bits {
7509         u8         status[0x8];
7510         u8         reserved_at_8[0x18];
7511
7512         u8         syndrome[0x20];
7513
7514         u8         reserved_at_40[0x8];
7515         u8         xrc_srqn[0x18];
7516
7517         u8         reserved_at_60[0x20];
7518 };
7519
7520 struct mlx5_ifc_create_xrc_srq_in_bits {
7521         u8         opcode[0x10];
7522         u8         uid[0x10];
7523
7524         u8         reserved_at_20[0x10];
7525         u8         op_mod[0x10];
7526
7527         u8         reserved_at_40[0x40];
7528
7529         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7530
7531         u8         reserved_at_280[0x60];
7532
7533         u8         xrc_srq_umem_valid[0x1];
7534         u8         reserved_at_2e1[0x1f];
7535
7536         u8         reserved_at_300[0x580];
7537
7538         u8         pas[][0x40];
7539 };
7540
7541 struct mlx5_ifc_create_tis_out_bits {
7542         u8         status[0x8];
7543         u8         reserved_at_8[0x18];
7544
7545         u8         syndrome[0x20];
7546
7547         u8         reserved_at_40[0x8];
7548         u8         tisn[0x18];
7549
7550         u8         reserved_at_60[0x20];
7551 };
7552
7553 struct mlx5_ifc_create_tis_in_bits {
7554         u8         opcode[0x10];
7555         u8         uid[0x10];
7556
7557         u8         reserved_at_20[0x10];
7558         u8         op_mod[0x10];
7559
7560         u8         reserved_at_40[0xc0];
7561
7562         struct mlx5_ifc_tisc_bits ctx;
7563 };
7564
7565 struct mlx5_ifc_create_tir_out_bits {
7566         u8         status[0x8];
7567         u8         icm_address_63_40[0x18];
7568
7569         u8         syndrome[0x20];
7570
7571         u8         icm_address_39_32[0x8];
7572         u8         tirn[0x18];
7573
7574         u8         icm_address_31_0[0x20];
7575 };
7576
7577 struct mlx5_ifc_create_tir_in_bits {
7578         u8         opcode[0x10];
7579         u8         uid[0x10];
7580
7581         u8         reserved_at_20[0x10];
7582         u8         op_mod[0x10];
7583
7584         u8         reserved_at_40[0xc0];
7585
7586         struct mlx5_ifc_tirc_bits ctx;
7587 };
7588
7589 struct mlx5_ifc_create_srq_out_bits {
7590         u8         status[0x8];
7591         u8         reserved_at_8[0x18];
7592
7593         u8         syndrome[0x20];
7594
7595         u8         reserved_at_40[0x8];
7596         u8         srqn[0x18];
7597
7598         u8         reserved_at_60[0x20];
7599 };
7600
7601 struct mlx5_ifc_create_srq_in_bits {
7602         u8         opcode[0x10];
7603         u8         uid[0x10];
7604
7605         u8         reserved_at_20[0x10];
7606         u8         op_mod[0x10];
7607
7608         u8         reserved_at_40[0x40];
7609
7610         struct mlx5_ifc_srqc_bits srq_context_entry;
7611
7612         u8         reserved_at_280[0x600];
7613
7614         u8         pas[][0x40];
7615 };
7616
7617 struct mlx5_ifc_create_sq_out_bits {
7618         u8         status[0x8];
7619         u8         reserved_at_8[0x18];
7620
7621         u8         syndrome[0x20];
7622
7623         u8         reserved_at_40[0x8];
7624         u8         sqn[0x18];
7625
7626         u8         reserved_at_60[0x20];
7627 };
7628
7629 struct mlx5_ifc_create_sq_in_bits {
7630         u8         opcode[0x10];
7631         u8         uid[0x10];
7632
7633         u8         reserved_at_20[0x10];
7634         u8         op_mod[0x10];
7635
7636         u8         reserved_at_40[0xc0];
7637
7638         struct mlx5_ifc_sqc_bits ctx;
7639 };
7640
7641 struct mlx5_ifc_create_scheduling_element_out_bits {
7642         u8         status[0x8];
7643         u8         reserved_at_8[0x18];
7644
7645         u8         syndrome[0x20];
7646
7647         u8         reserved_at_40[0x40];
7648
7649         u8         scheduling_element_id[0x20];
7650
7651         u8         reserved_at_a0[0x160];
7652 };
7653
7654 struct mlx5_ifc_create_scheduling_element_in_bits {
7655         u8         opcode[0x10];
7656         u8         reserved_at_10[0x10];
7657
7658         u8         reserved_at_20[0x10];
7659         u8         op_mod[0x10];
7660
7661         u8         scheduling_hierarchy[0x8];
7662         u8         reserved_at_48[0x18];
7663
7664         u8         reserved_at_60[0xa0];
7665
7666         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7667
7668         u8         reserved_at_300[0x100];
7669 };
7670
7671 struct mlx5_ifc_create_rqt_out_bits {
7672         u8         status[0x8];
7673         u8         reserved_at_8[0x18];
7674
7675         u8         syndrome[0x20];
7676
7677         u8         reserved_at_40[0x8];
7678         u8         rqtn[0x18];
7679
7680         u8         reserved_at_60[0x20];
7681 };
7682
7683 struct mlx5_ifc_create_rqt_in_bits {
7684         u8         opcode[0x10];
7685         u8         uid[0x10];
7686
7687         u8         reserved_at_20[0x10];
7688         u8         op_mod[0x10];
7689
7690         u8         reserved_at_40[0xc0];
7691
7692         struct mlx5_ifc_rqtc_bits rqt_context;
7693 };
7694
7695 struct mlx5_ifc_create_rq_out_bits {
7696         u8         status[0x8];
7697         u8         reserved_at_8[0x18];
7698
7699         u8         syndrome[0x20];
7700
7701         u8         reserved_at_40[0x8];
7702         u8         rqn[0x18];
7703
7704         u8         reserved_at_60[0x20];
7705 };
7706
7707 struct mlx5_ifc_create_rq_in_bits {
7708         u8         opcode[0x10];
7709         u8         uid[0x10];
7710
7711         u8         reserved_at_20[0x10];
7712         u8         op_mod[0x10];
7713
7714         u8         reserved_at_40[0xc0];
7715
7716         struct mlx5_ifc_rqc_bits ctx;
7717 };
7718
7719 struct mlx5_ifc_create_rmp_out_bits {
7720         u8         status[0x8];
7721         u8         reserved_at_8[0x18];
7722
7723         u8         syndrome[0x20];
7724
7725         u8         reserved_at_40[0x8];
7726         u8         rmpn[0x18];
7727
7728         u8         reserved_at_60[0x20];
7729 };
7730
7731 struct mlx5_ifc_create_rmp_in_bits {
7732         u8         opcode[0x10];
7733         u8         uid[0x10];
7734
7735         u8         reserved_at_20[0x10];
7736         u8         op_mod[0x10];
7737
7738         u8         reserved_at_40[0xc0];
7739
7740         struct mlx5_ifc_rmpc_bits ctx;
7741 };
7742
7743 struct mlx5_ifc_create_qp_out_bits {
7744         u8         status[0x8];
7745         u8         reserved_at_8[0x18];
7746
7747         u8         syndrome[0x20];
7748
7749         u8         reserved_at_40[0x8];
7750         u8         qpn[0x18];
7751
7752         u8         ece[0x20];
7753 };
7754
7755 struct mlx5_ifc_create_qp_in_bits {
7756         u8         opcode[0x10];
7757         u8         uid[0x10];
7758
7759         u8         reserved_at_20[0x10];
7760         u8         op_mod[0x10];
7761
7762         u8         reserved_at_40[0x8];
7763         u8         input_qpn[0x18];
7764
7765         u8         reserved_at_60[0x20];
7766         u8         opt_param_mask[0x20];
7767
7768         u8         ece[0x20];
7769
7770         struct mlx5_ifc_qpc_bits qpc;
7771
7772         u8         reserved_at_800[0x60];
7773
7774         u8         wq_umem_valid[0x1];
7775         u8         reserved_at_861[0x1f];
7776
7777         u8         pas[][0x40];
7778 };
7779
7780 struct mlx5_ifc_create_psv_out_bits {
7781         u8         status[0x8];
7782         u8         reserved_at_8[0x18];
7783
7784         u8         syndrome[0x20];
7785
7786         u8         reserved_at_40[0x40];
7787
7788         u8         reserved_at_80[0x8];
7789         u8         psv0_index[0x18];
7790
7791         u8         reserved_at_a0[0x8];
7792         u8         psv1_index[0x18];
7793
7794         u8         reserved_at_c0[0x8];
7795         u8         psv2_index[0x18];
7796
7797         u8         reserved_at_e0[0x8];
7798         u8         psv3_index[0x18];
7799 };
7800
7801 struct mlx5_ifc_create_psv_in_bits {
7802         u8         opcode[0x10];
7803         u8         reserved_at_10[0x10];
7804
7805         u8         reserved_at_20[0x10];
7806         u8         op_mod[0x10];
7807
7808         u8         num_psv[0x4];
7809         u8         reserved_at_44[0x4];
7810         u8         pd[0x18];
7811
7812         u8         reserved_at_60[0x20];
7813 };
7814
7815 struct mlx5_ifc_create_mkey_out_bits {
7816         u8         status[0x8];
7817         u8         reserved_at_8[0x18];
7818
7819         u8         syndrome[0x20];
7820
7821         u8         reserved_at_40[0x8];
7822         u8         mkey_index[0x18];
7823
7824         u8         reserved_at_60[0x20];
7825 };
7826
7827 struct mlx5_ifc_create_mkey_in_bits {
7828         u8         opcode[0x10];
7829         u8         uid[0x10];
7830
7831         u8         reserved_at_20[0x10];
7832         u8         op_mod[0x10];
7833
7834         u8         reserved_at_40[0x20];
7835
7836         u8         pg_access[0x1];
7837         u8         mkey_umem_valid[0x1];
7838         u8         reserved_at_62[0x1e];
7839
7840         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7841
7842         u8         reserved_at_280[0x80];
7843
7844         u8         translations_octword_actual_size[0x20];
7845
7846         u8         reserved_at_320[0x560];
7847
7848         u8         klm_pas_mtt[][0x20];
7849 };
7850
7851 enum {
7852         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
7853         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
7854         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
7855         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
7856         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
7857         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
7858         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
7859 };
7860
7861 struct mlx5_ifc_create_flow_table_out_bits {
7862         u8         status[0x8];
7863         u8         icm_address_63_40[0x18];
7864
7865         u8         syndrome[0x20];
7866
7867         u8         icm_address_39_32[0x8];
7868         u8         table_id[0x18];
7869
7870         u8         icm_address_31_0[0x20];
7871 };
7872
7873 struct mlx5_ifc_create_flow_table_in_bits {
7874         u8         opcode[0x10];
7875         u8         reserved_at_10[0x10];
7876
7877         u8         reserved_at_20[0x10];
7878         u8         op_mod[0x10];
7879
7880         u8         other_vport[0x1];
7881         u8         reserved_at_41[0xf];
7882         u8         vport_number[0x10];
7883
7884         u8         reserved_at_60[0x20];
7885
7886         u8         table_type[0x8];
7887         u8         reserved_at_88[0x18];
7888
7889         u8         reserved_at_a0[0x20];
7890
7891         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7892 };
7893
7894 struct mlx5_ifc_create_flow_group_out_bits {
7895         u8         status[0x8];
7896         u8         reserved_at_8[0x18];
7897
7898         u8         syndrome[0x20];
7899
7900         u8         reserved_at_40[0x8];
7901         u8         group_id[0x18];
7902
7903         u8         reserved_at_60[0x20];
7904 };
7905
7906 enum {
7907         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7908         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7909         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7910         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7911 };
7912
7913 struct mlx5_ifc_create_flow_group_in_bits {
7914         u8         opcode[0x10];
7915         u8         reserved_at_10[0x10];
7916
7917         u8         reserved_at_20[0x10];
7918         u8         op_mod[0x10];
7919
7920         u8         other_vport[0x1];
7921         u8         reserved_at_41[0xf];
7922         u8         vport_number[0x10];
7923
7924         u8         reserved_at_60[0x20];
7925
7926         u8         table_type[0x8];
7927         u8         reserved_at_88[0x18];
7928
7929         u8         reserved_at_a0[0x8];
7930         u8         table_id[0x18];
7931
7932         u8         source_eswitch_owner_vhca_id_valid[0x1];
7933
7934         u8         reserved_at_c1[0x1f];
7935
7936         u8         start_flow_index[0x20];
7937
7938         u8         reserved_at_100[0x20];
7939
7940         u8         end_flow_index[0x20];
7941
7942         u8         reserved_at_140[0xa0];
7943
7944         u8         reserved_at_1e0[0x18];
7945         u8         match_criteria_enable[0x8];
7946
7947         struct mlx5_ifc_fte_match_param_bits match_criteria;
7948
7949         u8         reserved_at_1200[0xe00];
7950 };
7951
7952 struct mlx5_ifc_create_eq_out_bits {
7953         u8         status[0x8];
7954         u8         reserved_at_8[0x18];
7955
7956         u8         syndrome[0x20];
7957
7958         u8         reserved_at_40[0x18];
7959         u8         eq_number[0x8];
7960
7961         u8         reserved_at_60[0x20];
7962 };
7963
7964 struct mlx5_ifc_create_eq_in_bits {
7965         u8         opcode[0x10];
7966         u8         uid[0x10];
7967
7968         u8         reserved_at_20[0x10];
7969         u8         op_mod[0x10];
7970
7971         u8         reserved_at_40[0x40];
7972
7973         struct mlx5_ifc_eqc_bits eq_context_entry;
7974
7975         u8         reserved_at_280[0x40];
7976
7977         u8         event_bitmask[4][0x40];
7978
7979         u8         reserved_at_3c0[0x4c0];
7980
7981         u8         pas[][0x40];
7982 };
7983
7984 struct mlx5_ifc_create_dct_out_bits {
7985         u8         status[0x8];
7986         u8         reserved_at_8[0x18];
7987
7988         u8         syndrome[0x20];
7989
7990         u8         reserved_at_40[0x8];
7991         u8         dctn[0x18];
7992
7993         u8         ece[0x20];
7994 };
7995
7996 struct mlx5_ifc_create_dct_in_bits {
7997         u8         opcode[0x10];
7998         u8         uid[0x10];
7999
8000         u8         reserved_at_20[0x10];
8001         u8         op_mod[0x10];
8002
8003         u8         reserved_at_40[0x40];
8004
8005         struct mlx5_ifc_dctc_bits dct_context_entry;
8006
8007         u8         reserved_at_280[0x180];
8008 };
8009
8010 struct mlx5_ifc_create_cq_out_bits {
8011         u8         status[0x8];
8012         u8         reserved_at_8[0x18];
8013
8014         u8         syndrome[0x20];
8015
8016         u8         reserved_at_40[0x8];
8017         u8         cqn[0x18];
8018
8019         u8         reserved_at_60[0x20];
8020 };
8021
8022 struct mlx5_ifc_create_cq_in_bits {
8023         u8         opcode[0x10];
8024         u8         uid[0x10];
8025
8026         u8         reserved_at_20[0x10];
8027         u8         op_mod[0x10];
8028
8029         u8         reserved_at_40[0x40];
8030
8031         struct mlx5_ifc_cqc_bits cq_context;
8032
8033         u8         reserved_at_280[0x60];
8034
8035         u8         cq_umem_valid[0x1];
8036         u8         reserved_at_2e1[0x59f];
8037
8038         u8         pas[][0x40];
8039 };
8040
8041 struct mlx5_ifc_config_int_moderation_out_bits {
8042         u8         status[0x8];
8043         u8         reserved_at_8[0x18];
8044
8045         u8         syndrome[0x20];
8046
8047         u8         reserved_at_40[0x4];
8048         u8         min_delay[0xc];
8049         u8         int_vector[0x10];
8050
8051         u8         reserved_at_60[0x20];
8052 };
8053
8054 enum {
8055         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8056         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8057 };
8058
8059 struct mlx5_ifc_config_int_moderation_in_bits {
8060         u8         opcode[0x10];
8061         u8         reserved_at_10[0x10];
8062
8063         u8         reserved_at_20[0x10];
8064         u8         op_mod[0x10];
8065
8066         u8         reserved_at_40[0x4];
8067         u8         min_delay[0xc];
8068         u8         int_vector[0x10];
8069
8070         u8         reserved_at_60[0x20];
8071 };
8072
8073 struct mlx5_ifc_attach_to_mcg_out_bits {
8074         u8         status[0x8];
8075         u8         reserved_at_8[0x18];
8076
8077         u8         syndrome[0x20];
8078
8079         u8         reserved_at_40[0x40];
8080 };
8081
8082 struct mlx5_ifc_attach_to_mcg_in_bits {
8083         u8         opcode[0x10];
8084         u8         uid[0x10];
8085
8086         u8         reserved_at_20[0x10];
8087         u8         op_mod[0x10];
8088
8089         u8         reserved_at_40[0x8];
8090         u8         qpn[0x18];
8091
8092         u8         reserved_at_60[0x20];
8093
8094         u8         multicast_gid[16][0x8];
8095 };
8096
8097 struct mlx5_ifc_arm_xrq_out_bits {
8098         u8         status[0x8];
8099         u8         reserved_at_8[0x18];
8100
8101         u8         syndrome[0x20];
8102
8103         u8         reserved_at_40[0x40];
8104 };
8105
8106 struct mlx5_ifc_arm_xrq_in_bits {
8107         u8         opcode[0x10];
8108         u8         reserved_at_10[0x10];
8109
8110         u8         reserved_at_20[0x10];
8111         u8         op_mod[0x10];
8112
8113         u8         reserved_at_40[0x8];
8114         u8         xrqn[0x18];
8115
8116         u8         reserved_at_60[0x10];
8117         u8         lwm[0x10];
8118 };
8119
8120 struct mlx5_ifc_arm_xrc_srq_out_bits {
8121         u8         status[0x8];
8122         u8         reserved_at_8[0x18];
8123
8124         u8         syndrome[0x20];
8125
8126         u8         reserved_at_40[0x40];
8127 };
8128
8129 enum {
8130         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8131 };
8132
8133 struct mlx5_ifc_arm_xrc_srq_in_bits {
8134         u8         opcode[0x10];
8135         u8         uid[0x10];
8136
8137         u8         reserved_at_20[0x10];
8138         u8         op_mod[0x10];
8139
8140         u8         reserved_at_40[0x8];
8141         u8         xrc_srqn[0x18];
8142
8143         u8         reserved_at_60[0x10];
8144         u8         lwm[0x10];
8145 };
8146
8147 struct mlx5_ifc_arm_rq_out_bits {
8148         u8         status[0x8];
8149         u8         reserved_at_8[0x18];
8150
8151         u8         syndrome[0x20];
8152
8153         u8         reserved_at_40[0x40];
8154 };
8155
8156 enum {
8157         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8158         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8159 };
8160
8161 struct mlx5_ifc_arm_rq_in_bits {
8162         u8         opcode[0x10];
8163         u8         uid[0x10];
8164
8165         u8         reserved_at_20[0x10];
8166         u8         op_mod[0x10];
8167
8168         u8         reserved_at_40[0x8];
8169         u8         srq_number[0x18];
8170
8171         u8         reserved_at_60[0x10];
8172         u8         lwm[0x10];
8173 };
8174
8175 struct mlx5_ifc_arm_dct_out_bits {
8176         u8         status[0x8];
8177         u8         reserved_at_8[0x18];
8178
8179         u8         syndrome[0x20];
8180
8181         u8         reserved_at_40[0x40];
8182 };
8183
8184 struct mlx5_ifc_arm_dct_in_bits {
8185         u8         opcode[0x10];
8186         u8         reserved_at_10[0x10];
8187
8188         u8         reserved_at_20[0x10];
8189         u8         op_mod[0x10];
8190
8191         u8         reserved_at_40[0x8];
8192         u8         dct_number[0x18];
8193
8194         u8         reserved_at_60[0x20];
8195 };
8196
8197 struct mlx5_ifc_alloc_xrcd_out_bits {
8198         u8         status[0x8];
8199         u8         reserved_at_8[0x18];
8200
8201         u8         syndrome[0x20];
8202
8203         u8         reserved_at_40[0x8];
8204         u8         xrcd[0x18];
8205
8206         u8         reserved_at_60[0x20];
8207 };
8208
8209 struct mlx5_ifc_alloc_xrcd_in_bits {
8210         u8         opcode[0x10];
8211         u8         uid[0x10];
8212
8213         u8         reserved_at_20[0x10];
8214         u8         op_mod[0x10];
8215
8216         u8         reserved_at_40[0x40];
8217 };
8218
8219 struct mlx5_ifc_alloc_uar_out_bits {
8220         u8         status[0x8];
8221         u8         reserved_at_8[0x18];
8222
8223         u8         syndrome[0x20];
8224
8225         u8         reserved_at_40[0x8];
8226         u8         uar[0x18];
8227
8228         u8         reserved_at_60[0x20];
8229 };
8230
8231 struct mlx5_ifc_alloc_uar_in_bits {
8232         u8         opcode[0x10];
8233         u8         reserved_at_10[0x10];
8234
8235         u8         reserved_at_20[0x10];
8236         u8         op_mod[0x10];
8237
8238         u8         reserved_at_40[0x40];
8239 };
8240
8241 struct mlx5_ifc_alloc_transport_domain_out_bits {
8242         u8         status[0x8];
8243         u8         reserved_at_8[0x18];
8244
8245         u8         syndrome[0x20];
8246
8247         u8         reserved_at_40[0x8];
8248         u8         transport_domain[0x18];
8249
8250         u8         reserved_at_60[0x20];
8251 };
8252
8253 struct mlx5_ifc_alloc_transport_domain_in_bits {
8254         u8         opcode[0x10];
8255         u8         uid[0x10];
8256
8257         u8         reserved_at_20[0x10];
8258         u8         op_mod[0x10];
8259
8260         u8         reserved_at_40[0x40];
8261 };
8262
8263 struct mlx5_ifc_alloc_q_counter_out_bits {
8264         u8         status[0x8];
8265         u8         reserved_at_8[0x18];
8266
8267         u8         syndrome[0x20];
8268
8269         u8         reserved_at_40[0x18];
8270         u8         counter_set_id[0x8];
8271
8272         u8         reserved_at_60[0x20];
8273 };
8274
8275 struct mlx5_ifc_alloc_q_counter_in_bits {
8276         u8         opcode[0x10];
8277         u8         uid[0x10];
8278
8279         u8         reserved_at_20[0x10];
8280         u8         op_mod[0x10];
8281
8282         u8         reserved_at_40[0x40];
8283 };
8284
8285 struct mlx5_ifc_alloc_pd_out_bits {
8286         u8         status[0x8];
8287         u8         reserved_at_8[0x18];
8288
8289         u8         syndrome[0x20];
8290
8291         u8         reserved_at_40[0x8];
8292         u8         pd[0x18];
8293
8294         u8         reserved_at_60[0x20];
8295 };
8296
8297 struct mlx5_ifc_alloc_pd_in_bits {
8298         u8         opcode[0x10];
8299         u8         uid[0x10];
8300
8301         u8         reserved_at_20[0x10];
8302         u8         op_mod[0x10];
8303
8304         u8         reserved_at_40[0x40];
8305 };
8306
8307 struct mlx5_ifc_alloc_flow_counter_out_bits {
8308         u8         status[0x8];
8309         u8         reserved_at_8[0x18];
8310
8311         u8         syndrome[0x20];
8312
8313         u8         flow_counter_id[0x20];
8314
8315         u8         reserved_at_60[0x20];
8316 };
8317
8318 struct mlx5_ifc_alloc_flow_counter_in_bits {
8319         u8         opcode[0x10];
8320         u8         reserved_at_10[0x10];
8321
8322         u8         reserved_at_20[0x10];
8323         u8         op_mod[0x10];
8324
8325         u8         reserved_at_40[0x38];
8326         u8         flow_counter_bulk[0x8];
8327 };
8328
8329 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8330         u8         status[0x8];
8331         u8         reserved_at_8[0x18];
8332
8333         u8         syndrome[0x20];
8334
8335         u8         reserved_at_40[0x40];
8336 };
8337
8338 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8339         u8         opcode[0x10];
8340         u8         reserved_at_10[0x10];
8341
8342         u8         reserved_at_20[0x10];
8343         u8         op_mod[0x10];
8344
8345         u8         reserved_at_40[0x20];
8346
8347         u8         reserved_at_60[0x10];
8348         u8         vxlan_udp_port[0x10];
8349 };
8350
8351 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8352         u8         status[0x8];
8353         u8         reserved_at_8[0x18];
8354
8355         u8         syndrome[0x20];
8356
8357         u8         reserved_at_40[0x40];
8358 };
8359
8360 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8361         u8         rate_limit[0x20];
8362
8363         u8         burst_upper_bound[0x20];
8364
8365         u8         reserved_at_40[0x10];
8366         u8         typical_packet_size[0x10];
8367
8368         u8         reserved_at_60[0x120];
8369 };
8370
8371 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8372         u8         opcode[0x10];
8373         u8         uid[0x10];
8374
8375         u8         reserved_at_20[0x10];
8376         u8         op_mod[0x10];
8377
8378         u8         reserved_at_40[0x10];
8379         u8         rate_limit_index[0x10];
8380
8381         u8         reserved_at_60[0x20];
8382
8383         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8384 };
8385
8386 struct mlx5_ifc_access_register_out_bits {
8387         u8         status[0x8];
8388         u8         reserved_at_8[0x18];
8389
8390         u8         syndrome[0x20];
8391
8392         u8         reserved_at_40[0x40];
8393
8394         u8         register_data[][0x20];
8395 };
8396
8397 enum {
8398         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8399         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8400 };
8401
8402 struct mlx5_ifc_access_register_in_bits {
8403         u8         opcode[0x10];
8404         u8         reserved_at_10[0x10];
8405
8406         u8         reserved_at_20[0x10];
8407         u8         op_mod[0x10];
8408
8409         u8         reserved_at_40[0x10];
8410         u8         register_id[0x10];
8411
8412         u8         argument[0x20];
8413
8414         u8         register_data[][0x20];
8415 };
8416
8417 struct mlx5_ifc_sltp_reg_bits {
8418         u8         status[0x4];
8419         u8         version[0x4];
8420         u8         local_port[0x8];
8421         u8         pnat[0x2];
8422         u8         reserved_at_12[0x2];
8423         u8         lane[0x4];
8424         u8         reserved_at_18[0x8];
8425
8426         u8         reserved_at_20[0x20];
8427
8428         u8         reserved_at_40[0x7];
8429         u8         polarity[0x1];
8430         u8         ob_tap0[0x8];
8431         u8         ob_tap1[0x8];
8432         u8         ob_tap2[0x8];
8433
8434         u8         reserved_at_60[0xc];
8435         u8         ob_preemp_mode[0x4];
8436         u8         ob_reg[0x8];
8437         u8         ob_bias[0x8];
8438
8439         u8         reserved_at_80[0x20];
8440 };
8441
8442 struct mlx5_ifc_slrg_reg_bits {
8443         u8         status[0x4];
8444         u8         version[0x4];
8445         u8         local_port[0x8];
8446         u8         pnat[0x2];
8447         u8         reserved_at_12[0x2];
8448         u8         lane[0x4];
8449         u8         reserved_at_18[0x8];
8450
8451         u8         time_to_link_up[0x10];
8452         u8         reserved_at_30[0xc];
8453         u8         grade_lane_speed[0x4];
8454
8455         u8         grade_version[0x8];
8456         u8         grade[0x18];
8457
8458         u8         reserved_at_60[0x4];
8459         u8         height_grade_type[0x4];
8460         u8         height_grade[0x18];
8461
8462         u8         height_dz[0x10];
8463         u8         height_dv[0x10];
8464
8465         u8         reserved_at_a0[0x10];
8466         u8         height_sigma[0x10];
8467
8468         u8         reserved_at_c0[0x20];
8469
8470         u8         reserved_at_e0[0x4];
8471         u8         phase_grade_type[0x4];
8472         u8         phase_grade[0x18];
8473
8474         u8         reserved_at_100[0x8];
8475         u8         phase_eo_pos[0x8];
8476         u8         reserved_at_110[0x8];
8477         u8         phase_eo_neg[0x8];
8478
8479         u8         ffe_set_tested[0x10];
8480         u8         test_errors_per_lane[0x10];
8481 };
8482
8483 struct mlx5_ifc_pvlc_reg_bits {
8484         u8         reserved_at_0[0x8];
8485         u8         local_port[0x8];
8486         u8         reserved_at_10[0x10];
8487
8488         u8         reserved_at_20[0x1c];
8489         u8         vl_hw_cap[0x4];
8490
8491         u8         reserved_at_40[0x1c];
8492         u8         vl_admin[0x4];
8493
8494         u8         reserved_at_60[0x1c];
8495         u8         vl_operational[0x4];
8496 };
8497
8498 struct mlx5_ifc_pude_reg_bits {
8499         u8         swid[0x8];
8500         u8         local_port[0x8];
8501         u8         reserved_at_10[0x4];
8502         u8         admin_status[0x4];
8503         u8         reserved_at_18[0x4];
8504         u8         oper_status[0x4];
8505
8506         u8         reserved_at_20[0x60];
8507 };
8508
8509 struct mlx5_ifc_ptys_reg_bits {
8510         u8         reserved_at_0[0x1];
8511         u8         an_disable_admin[0x1];
8512         u8         an_disable_cap[0x1];
8513         u8         reserved_at_3[0x5];
8514         u8         local_port[0x8];
8515         u8         reserved_at_10[0xd];
8516         u8         proto_mask[0x3];
8517
8518         u8         an_status[0x4];
8519         u8         reserved_at_24[0xc];
8520         u8         data_rate_oper[0x10];
8521
8522         u8         ext_eth_proto_capability[0x20];
8523
8524         u8         eth_proto_capability[0x20];
8525
8526         u8         ib_link_width_capability[0x10];
8527         u8         ib_proto_capability[0x10];
8528
8529         u8         ext_eth_proto_admin[0x20];
8530
8531         u8         eth_proto_admin[0x20];
8532
8533         u8         ib_link_width_admin[0x10];
8534         u8         ib_proto_admin[0x10];
8535
8536         u8         ext_eth_proto_oper[0x20];
8537
8538         u8         eth_proto_oper[0x20];
8539
8540         u8         ib_link_width_oper[0x10];
8541         u8         ib_proto_oper[0x10];
8542
8543         u8         reserved_at_160[0x1c];
8544         u8         connector_type[0x4];
8545
8546         u8         eth_proto_lp_advertise[0x20];
8547
8548         u8         reserved_at_1a0[0x60];
8549 };
8550
8551 struct mlx5_ifc_mlcr_reg_bits {
8552         u8         reserved_at_0[0x8];
8553         u8         local_port[0x8];
8554         u8         reserved_at_10[0x20];
8555
8556         u8         beacon_duration[0x10];
8557         u8         reserved_at_40[0x10];
8558
8559         u8         beacon_remain[0x10];
8560 };
8561
8562 struct mlx5_ifc_ptas_reg_bits {
8563         u8         reserved_at_0[0x20];
8564
8565         u8         algorithm_options[0x10];
8566         u8         reserved_at_30[0x4];
8567         u8         repetitions_mode[0x4];
8568         u8         num_of_repetitions[0x8];
8569
8570         u8         grade_version[0x8];
8571         u8         height_grade_type[0x4];
8572         u8         phase_grade_type[0x4];
8573         u8         height_grade_weight[0x8];
8574         u8         phase_grade_weight[0x8];
8575
8576         u8         gisim_measure_bits[0x10];
8577         u8         adaptive_tap_measure_bits[0x10];
8578
8579         u8         ber_bath_high_error_threshold[0x10];
8580         u8         ber_bath_mid_error_threshold[0x10];
8581
8582         u8         ber_bath_low_error_threshold[0x10];
8583         u8         one_ratio_high_threshold[0x10];
8584
8585         u8         one_ratio_high_mid_threshold[0x10];
8586         u8         one_ratio_low_mid_threshold[0x10];
8587
8588         u8         one_ratio_low_threshold[0x10];
8589         u8         ndeo_error_threshold[0x10];
8590
8591         u8         mixer_offset_step_size[0x10];
8592         u8         reserved_at_110[0x8];
8593         u8         mix90_phase_for_voltage_bath[0x8];
8594
8595         u8         mixer_offset_start[0x10];
8596         u8         mixer_offset_end[0x10];
8597
8598         u8         reserved_at_140[0x15];
8599         u8         ber_test_time[0xb];
8600 };
8601
8602 struct mlx5_ifc_pspa_reg_bits {
8603         u8         swid[0x8];
8604         u8         local_port[0x8];
8605         u8         sub_port[0x8];
8606         u8         reserved_at_18[0x8];
8607
8608         u8         reserved_at_20[0x20];
8609 };
8610
8611 struct mlx5_ifc_pqdr_reg_bits {
8612         u8         reserved_at_0[0x8];
8613         u8         local_port[0x8];
8614         u8         reserved_at_10[0x5];
8615         u8         prio[0x3];
8616         u8         reserved_at_18[0x6];
8617         u8         mode[0x2];
8618
8619         u8         reserved_at_20[0x20];
8620
8621         u8         reserved_at_40[0x10];
8622         u8         min_threshold[0x10];
8623
8624         u8         reserved_at_60[0x10];
8625         u8         max_threshold[0x10];
8626
8627         u8         reserved_at_80[0x10];
8628         u8         mark_probability_denominator[0x10];
8629
8630         u8         reserved_at_a0[0x60];
8631 };
8632
8633 struct mlx5_ifc_ppsc_reg_bits {
8634         u8         reserved_at_0[0x8];
8635         u8         local_port[0x8];
8636         u8         reserved_at_10[0x10];
8637
8638         u8         reserved_at_20[0x60];
8639
8640         u8         reserved_at_80[0x1c];
8641         u8         wrps_admin[0x4];
8642
8643         u8         reserved_at_a0[0x1c];
8644         u8         wrps_status[0x4];
8645
8646         u8         reserved_at_c0[0x8];
8647         u8         up_threshold[0x8];
8648         u8         reserved_at_d0[0x8];
8649         u8         down_threshold[0x8];
8650
8651         u8         reserved_at_e0[0x20];
8652
8653         u8         reserved_at_100[0x1c];
8654         u8         srps_admin[0x4];
8655
8656         u8         reserved_at_120[0x1c];
8657         u8         srps_status[0x4];
8658
8659         u8         reserved_at_140[0x40];
8660 };
8661
8662 struct mlx5_ifc_pplr_reg_bits {
8663         u8         reserved_at_0[0x8];
8664         u8         local_port[0x8];
8665         u8         reserved_at_10[0x10];
8666
8667         u8         reserved_at_20[0x8];
8668         u8         lb_cap[0x8];
8669         u8         reserved_at_30[0x8];
8670         u8         lb_en[0x8];
8671 };
8672
8673 struct mlx5_ifc_pplm_reg_bits {
8674         u8         reserved_at_0[0x8];
8675         u8         local_port[0x8];
8676         u8         reserved_at_10[0x10];
8677
8678         u8         reserved_at_20[0x20];
8679
8680         u8         port_profile_mode[0x8];
8681         u8         static_port_profile[0x8];
8682         u8         active_port_profile[0x8];
8683         u8         reserved_at_58[0x8];
8684
8685         u8         retransmission_active[0x8];
8686         u8         fec_mode_active[0x18];
8687
8688         u8         rs_fec_correction_bypass_cap[0x4];
8689         u8         reserved_at_84[0x8];
8690         u8         fec_override_cap_56g[0x4];
8691         u8         fec_override_cap_100g[0x4];
8692         u8         fec_override_cap_50g[0x4];
8693         u8         fec_override_cap_25g[0x4];
8694         u8         fec_override_cap_10g_40g[0x4];
8695
8696         u8         rs_fec_correction_bypass_admin[0x4];
8697         u8         reserved_at_a4[0x8];
8698         u8         fec_override_admin_56g[0x4];
8699         u8         fec_override_admin_100g[0x4];
8700         u8         fec_override_admin_50g[0x4];
8701         u8         fec_override_admin_25g[0x4];
8702         u8         fec_override_admin_10g_40g[0x4];
8703
8704         u8         fec_override_cap_400g_8x[0x10];
8705         u8         fec_override_cap_200g_4x[0x10];
8706
8707         u8         fec_override_cap_100g_2x[0x10];
8708         u8         fec_override_cap_50g_1x[0x10];
8709
8710         u8         fec_override_admin_400g_8x[0x10];
8711         u8         fec_override_admin_200g_4x[0x10];
8712
8713         u8         fec_override_admin_100g_2x[0x10];
8714         u8         fec_override_admin_50g_1x[0x10];
8715 };
8716
8717 struct mlx5_ifc_ppcnt_reg_bits {
8718         u8         swid[0x8];
8719         u8         local_port[0x8];
8720         u8         pnat[0x2];
8721         u8         reserved_at_12[0x8];
8722         u8         grp[0x6];
8723
8724         u8         clr[0x1];
8725         u8         reserved_at_21[0x1c];
8726         u8         prio_tc[0x3];
8727
8728         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8729 };
8730
8731 struct mlx5_ifc_mpein_reg_bits {
8732         u8         reserved_at_0[0x2];
8733         u8         depth[0x6];
8734         u8         pcie_index[0x8];
8735         u8         node[0x8];
8736         u8         reserved_at_18[0x8];
8737
8738         u8         capability_mask[0x20];
8739
8740         u8         reserved_at_40[0x8];
8741         u8         link_width_enabled[0x8];
8742         u8         link_speed_enabled[0x10];
8743
8744         u8         lane0_physical_position[0x8];
8745         u8         link_width_active[0x8];
8746         u8         link_speed_active[0x10];
8747
8748         u8         num_of_pfs[0x10];
8749         u8         num_of_vfs[0x10];
8750
8751         u8         bdf0[0x10];
8752         u8         reserved_at_b0[0x10];
8753
8754         u8         max_read_request_size[0x4];
8755         u8         max_payload_size[0x4];
8756         u8         reserved_at_c8[0x5];
8757         u8         pwr_status[0x3];
8758         u8         port_type[0x4];
8759         u8         reserved_at_d4[0xb];
8760         u8         lane_reversal[0x1];
8761
8762         u8         reserved_at_e0[0x14];
8763         u8         pci_power[0xc];
8764
8765         u8         reserved_at_100[0x20];
8766
8767         u8         device_status[0x10];
8768         u8         port_state[0x8];
8769         u8         reserved_at_138[0x8];
8770
8771         u8         reserved_at_140[0x10];
8772         u8         receiver_detect_result[0x10];
8773
8774         u8         reserved_at_160[0x20];
8775 };
8776
8777 struct mlx5_ifc_mpcnt_reg_bits {
8778         u8         reserved_at_0[0x8];
8779         u8         pcie_index[0x8];
8780         u8         reserved_at_10[0xa];
8781         u8         grp[0x6];
8782
8783         u8         clr[0x1];
8784         u8         reserved_at_21[0x1f];
8785
8786         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8787 };
8788
8789 struct mlx5_ifc_ppad_reg_bits {
8790         u8         reserved_at_0[0x3];
8791         u8         single_mac[0x1];
8792         u8         reserved_at_4[0x4];
8793         u8         local_port[0x8];
8794         u8         mac_47_32[0x10];
8795
8796         u8         mac_31_0[0x20];
8797
8798         u8         reserved_at_40[0x40];
8799 };
8800
8801 struct mlx5_ifc_pmtu_reg_bits {
8802         u8         reserved_at_0[0x8];
8803         u8         local_port[0x8];
8804         u8         reserved_at_10[0x10];
8805
8806         u8         max_mtu[0x10];
8807         u8         reserved_at_30[0x10];
8808
8809         u8         admin_mtu[0x10];
8810         u8         reserved_at_50[0x10];
8811
8812         u8         oper_mtu[0x10];
8813         u8         reserved_at_70[0x10];
8814 };
8815
8816 struct mlx5_ifc_pmpr_reg_bits {
8817         u8         reserved_at_0[0x8];
8818         u8         module[0x8];
8819         u8         reserved_at_10[0x10];
8820
8821         u8         reserved_at_20[0x18];
8822         u8         attenuation_5g[0x8];
8823
8824         u8         reserved_at_40[0x18];
8825         u8         attenuation_7g[0x8];
8826
8827         u8         reserved_at_60[0x18];
8828         u8         attenuation_12g[0x8];
8829 };
8830
8831 struct mlx5_ifc_pmpe_reg_bits {
8832         u8         reserved_at_0[0x8];
8833         u8         module[0x8];
8834         u8         reserved_at_10[0xc];
8835         u8         module_status[0x4];
8836
8837         u8         reserved_at_20[0x60];
8838 };
8839
8840 struct mlx5_ifc_pmpc_reg_bits {
8841         u8         module_state_updated[32][0x8];
8842 };
8843
8844 struct mlx5_ifc_pmlpn_reg_bits {
8845         u8         reserved_at_0[0x4];
8846         u8         mlpn_status[0x4];
8847         u8         local_port[0x8];
8848         u8         reserved_at_10[0x10];
8849
8850         u8         e[0x1];
8851         u8         reserved_at_21[0x1f];
8852 };
8853
8854 struct mlx5_ifc_pmlp_reg_bits {
8855         u8         rxtx[0x1];
8856         u8         reserved_at_1[0x7];
8857         u8         local_port[0x8];
8858         u8         reserved_at_10[0x8];
8859         u8         width[0x8];
8860
8861         u8         lane0_module_mapping[0x20];
8862
8863         u8         lane1_module_mapping[0x20];
8864
8865         u8         lane2_module_mapping[0x20];
8866
8867         u8         lane3_module_mapping[0x20];
8868
8869         u8         reserved_at_a0[0x160];
8870 };
8871
8872 struct mlx5_ifc_pmaos_reg_bits {
8873         u8         reserved_at_0[0x8];
8874         u8         module[0x8];
8875         u8         reserved_at_10[0x4];
8876         u8         admin_status[0x4];
8877         u8         reserved_at_18[0x4];
8878         u8         oper_status[0x4];
8879
8880         u8         ase[0x1];
8881         u8         ee[0x1];
8882         u8         reserved_at_22[0x1c];
8883         u8         e[0x2];
8884
8885         u8         reserved_at_40[0x40];
8886 };
8887
8888 struct mlx5_ifc_plpc_reg_bits {
8889         u8         reserved_at_0[0x4];
8890         u8         profile_id[0xc];
8891         u8         reserved_at_10[0x4];
8892         u8         proto_mask[0x4];
8893         u8         reserved_at_18[0x8];
8894
8895         u8         reserved_at_20[0x10];
8896         u8         lane_speed[0x10];
8897
8898         u8         reserved_at_40[0x17];
8899         u8         lpbf[0x1];
8900         u8         fec_mode_policy[0x8];
8901
8902         u8         retransmission_capability[0x8];
8903         u8         fec_mode_capability[0x18];
8904
8905         u8         retransmission_support_admin[0x8];
8906         u8         fec_mode_support_admin[0x18];
8907
8908         u8         retransmission_request_admin[0x8];
8909         u8         fec_mode_request_admin[0x18];
8910
8911         u8         reserved_at_c0[0x80];
8912 };
8913
8914 struct mlx5_ifc_plib_reg_bits {
8915         u8         reserved_at_0[0x8];
8916         u8         local_port[0x8];
8917         u8         reserved_at_10[0x8];
8918         u8         ib_port[0x8];
8919
8920         u8         reserved_at_20[0x60];
8921 };
8922
8923 struct mlx5_ifc_plbf_reg_bits {
8924         u8         reserved_at_0[0x8];
8925         u8         local_port[0x8];
8926         u8         reserved_at_10[0xd];
8927         u8         lbf_mode[0x3];
8928
8929         u8         reserved_at_20[0x20];
8930 };
8931
8932 struct mlx5_ifc_pipg_reg_bits {
8933         u8         reserved_at_0[0x8];
8934         u8         local_port[0x8];
8935         u8         reserved_at_10[0x10];
8936
8937         u8         dic[0x1];
8938         u8         reserved_at_21[0x19];
8939         u8         ipg[0x4];
8940         u8         reserved_at_3e[0x2];
8941 };
8942
8943 struct mlx5_ifc_pifr_reg_bits {
8944         u8         reserved_at_0[0x8];
8945         u8         local_port[0x8];
8946         u8         reserved_at_10[0x10];
8947
8948         u8         reserved_at_20[0xe0];
8949
8950         u8         port_filter[8][0x20];
8951
8952         u8         port_filter_update_en[8][0x20];
8953 };
8954
8955 struct mlx5_ifc_pfcc_reg_bits {
8956         u8         reserved_at_0[0x8];
8957         u8         local_port[0x8];
8958         u8         reserved_at_10[0xb];
8959         u8         ppan_mask_n[0x1];
8960         u8         minor_stall_mask[0x1];
8961         u8         critical_stall_mask[0x1];
8962         u8         reserved_at_1e[0x2];
8963
8964         u8         ppan[0x4];
8965         u8         reserved_at_24[0x4];
8966         u8         prio_mask_tx[0x8];
8967         u8         reserved_at_30[0x8];
8968         u8         prio_mask_rx[0x8];
8969
8970         u8         pptx[0x1];
8971         u8         aptx[0x1];
8972         u8         pptx_mask_n[0x1];
8973         u8         reserved_at_43[0x5];
8974         u8         pfctx[0x8];
8975         u8         reserved_at_50[0x10];
8976
8977         u8         pprx[0x1];
8978         u8         aprx[0x1];
8979         u8         pprx_mask_n[0x1];
8980         u8         reserved_at_63[0x5];
8981         u8         pfcrx[0x8];
8982         u8         reserved_at_70[0x10];
8983
8984         u8         device_stall_minor_watermark[0x10];
8985         u8         device_stall_critical_watermark[0x10];
8986
8987         u8         reserved_at_a0[0x60];
8988 };
8989
8990 struct mlx5_ifc_pelc_reg_bits {
8991         u8         op[0x4];
8992         u8         reserved_at_4[0x4];
8993         u8         local_port[0x8];
8994         u8         reserved_at_10[0x10];
8995
8996         u8         op_admin[0x8];
8997         u8         op_capability[0x8];
8998         u8         op_request[0x8];
8999         u8         op_active[0x8];
9000
9001         u8         admin[0x40];
9002
9003         u8         capability[0x40];
9004
9005         u8         request[0x40];
9006
9007         u8         active[0x40];
9008
9009         u8         reserved_at_140[0x80];
9010 };
9011
9012 struct mlx5_ifc_peir_reg_bits {
9013         u8         reserved_at_0[0x8];
9014         u8         local_port[0x8];
9015         u8         reserved_at_10[0x10];
9016
9017         u8         reserved_at_20[0xc];
9018         u8         error_count[0x4];
9019         u8         reserved_at_30[0x10];
9020
9021         u8         reserved_at_40[0xc];
9022         u8         lane[0x4];
9023         u8         reserved_at_50[0x8];
9024         u8         error_type[0x8];
9025 };
9026
9027 struct mlx5_ifc_mpegc_reg_bits {
9028         u8         reserved_at_0[0x30];
9029         u8         field_select[0x10];
9030
9031         u8         tx_overflow_sense[0x1];
9032         u8         mark_cqe[0x1];
9033         u8         mark_cnp[0x1];
9034         u8         reserved_at_43[0x1b];
9035         u8         tx_lossy_overflow_oper[0x2];
9036
9037         u8         reserved_at_60[0x100];
9038 };
9039
9040 struct mlx5_ifc_pcam_enhanced_features_bits {
9041         u8         reserved_at_0[0x68];
9042         u8         fec_50G_per_lane_in_pplm[0x1];
9043         u8         reserved_at_69[0x4];
9044         u8         rx_icrc_encapsulated_counter[0x1];
9045         u8         reserved_at_6e[0x4];
9046         u8         ptys_extended_ethernet[0x1];
9047         u8         reserved_at_73[0x3];
9048         u8         pfcc_mask[0x1];
9049         u8         reserved_at_77[0x3];
9050         u8         per_lane_error_counters[0x1];
9051         u8         rx_buffer_fullness_counters[0x1];
9052         u8         ptys_connector_type[0x1];
9053         u8         reserved_at_7d[0x1];
9054         u8         ppcnt_discard_group[0x1];
9055         u8         ppcnt_statistical_group[0x1];
9056 };
9057
9058 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9059         u8         port_access_reg_cap_mask_127_to_96[0x20];
9060         u8         port_access_reg_cap_mask_95_to_64[0x20];
9061
9062         u8         port_access_reg_cap_mask_63_to_36[0x1c];
9063         u8         pplm[0x1];
9064         u8         port_access_reg_cap_mask_34_to_32[0x3];
9065
9066         u8         port_access_reg_cap_mask_31_to_13[0x13];
9067         u8         pbmc[0x1];
9068         u8         pptb[0x1];
9069         u8         port_access_reg_cap_mask_10_to_09[0x2];
9070         u8         ppcnt[0x1];
9071         u8         port_access_reg_cap_mask_07_to_00[0x8];
9072 };
9073
9074 struct mlx5_ifc_pcam_reg_bits {
9075         u8         reserved_at_0[0x8];
9076         u8         feature_group[0x8];
9077         u8         reserved_at_10[0x8];
9078         u8         access_reg_group[0x8];
9079
9080         u8         reserved_at_20[0x20];
9081
9082         union {
9083                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9084                 u8         reserved_at_0[0x80];
9085         } port_access_reg_cap_mask;
9086
9087         u8         reserved_at_c0[0x80];
9088
9089         union {
9090                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9091                 u8         reserved_at_0[0x80];
9092         } feature_cap_mask;
9093
9094         u8         reserved_at_1c0[0xc0];
9095 };
9096
9097 struct mlx5_ifc_mcam_enhanced_features_bits {
9098         u8         reserved_at_0[0x6e];
9099         u8         pci_status_and_power[0x1];
9100         u8         reserved_at_6f[0x5];
9101         u8         mark_tx_action_cnp[0x1];
9102         u8         mark_tx_action_cqe[0x1];
9103         u8         dynamic_tx_overflow[0x1];
9104         u8         reserved_at_77[0x4];
9105         u8         pcie_outbound_stalled[0x1];
9106         u8         tx_overflow_buffer_pkt[0x1];
9107         u8         mtpps_enh_out_per_adj[0x1];
9108         u8         mtpps_fs[0x1];
9109         u8         pcie_performance_group[0x1];
9110 };
9111
9112 struct mlx5_ifc_mcam_access_reg_bits {
9113         u8         reserved_at_0[0x1c];
9114         u8         mcda[0x1];
9115         u8         mcc[0x1];
9116         u8         mcqi[0x1];
9117         u8         mcqs[0x1];
9118
9119         u8         regs_95_to_87[0x9];
9120         u8         mpegc[0x1];
9121         u8         regs_85_to_68[0x12];
9122         u8         tracer_registers[0x4];
9123
9124         u8         regs_63_to_32[0x20];
9125         u8         regs_31_to_0[0x20];
9126 };
9127
9128 struct mlx5_ifc_mcam_access_reg_bits1 {
9129         u8         regs_127_to_96[0x20];
9130
9131         u8         regs_95_to_64[0x20];
9132
9133         u8         regs_63_to_32[0x20];
9134
9135         u8         regs_31_to_0[0x20];
9136 };
9137
9138 struct mlx5_ifc_mcam_access_reg_bits2 {
9139         u8         regs_127_to_99[0x1d];
9140         u8         mirc[0x1];
9141         u8         regs_97_to_96[0x2];
9142
9143         u8         regs_95_to_64[0x20];
9144
9145         u8         regs_63_to_32[0x20];
9146
9147         u8         regs_31_to_0[0x20];
9148 };
9149
9150 struct mlx5_ifc_mcam_reg_bits {
9151         u8         reserved_at_0[0x8];
9152         u8         feature_group[0x8];
9153         u8         reserved_at_10[0x8];
9154         u8         access_reg_group[0x8];
9155
9156         u8         reserved_at_20[0x20];
9157
9158         union {
9159                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9160                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9161                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9162                 u8         reserved_at_0[0x80];
9163         } mng_access_reg_cap_mask;
9164
9165         u8         reserved_at_c0[0x80];
9166
9167         union {
9168                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9169                 u8         reserved_at_0[0x80];
9170         } mng_feature_cap_mask;
9171
9172         u8         reserved_at_1c0[0x80];
9173 };
9174
9175 struct mlx5_ifc_qcam_access_reg_cap_mask {
9176         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9177         u8         qpdpm[0x1];
9178         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9179         u8         qdpm[0x1];
9180         u8         qpts[0x1];
9181         u8         qcap[0x1];
9182         u8         qcam_access_reg_cap_mask_0[0x1];
9183 };
9184
9185 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9186         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9187         u8         qpts_trust_both[0x1];
9188 };
9189
9190 struct mlx5_ifc_qcam_reg_bits {
9191         u8         reserved_at_0[0x8];
9192         u8         feature_group[0x8];
9193         u8         reserved_at_10[0x8];
9194         u8         access_reg_group[0x8];
9195         u8         reserved_at_20[0x20];
9196
9197         union {
9198                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9199                 u8  reserved_at_0[0x80];
9200         } qos_access_reg_cap_mask;
9201
9202         u8         reserved_at_c0[0x80];
9203
9204         union {
9205                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9206                 u8  reserved_at_0[0x80];
9207         } qos_feature_cap_mask;
9208
9209         u8         reserved_at_1c0[0x80];
9210 };
9211
9212 struct mlx5_ifc_core_dump_reg_bits {
9213         u8         reserved_at_0[0x18];
9214         u8         core_dump_type[0x8];
9215
9216         u8         reserved_at_20[0x30];
9217         u8         vhca_id[0x10];
9218
9219         u8         reserved_at_60[0x8];
9220         u8         qpn[0x18];
9221         u8         reserved_at_80[0x180];
9222 };
9223
9224 struct mlx5_ifc_pcap_reg_bits {
9225         u8         reserved_at_0[0x8];
9226         u8         local_port[0x8];
9227         u8         reserved_at_10[0x10];
9228
9229         u8         port_capability_mask[4][0x20];
9230 };
9231
9232 struct mlx5_ifc_paos_reg_bits {
9233         u8         swid[0x8];
9234         u8         local_port[0x8];
9235         u8         reserved_at_10[0x4];
9236         u8         admin_status[0x4];
9237         u8         reserved_at_18[0x4];
9238         u8         oper_status[0x4];
9239
9240         u8         ase[0x1];
9241         u8         ee[0x1];
9242         u8         reserved_at_22[0x1c];
9243         u8         e[0x2];
9244
9245         u8         reserved_at_40[0x40];
9246 };
9247
9248 struct mlx5_ifc_pamp_reg_bits {
9249         u8         reserved_at_0[0x8];
9250         u8         opamp_group[0x8];
9251         u8         reserved_at_10[0xc];
9252         u8         opamp_group_type[0x4];
9253
9254         u8         start_index[0x10];
9255         u8         reserved_at_30[0x4];
9256         u8         num_of_indices[0xc];
9257
9258         u8         index_data[18][0x10];
9259 };
9260
9261 struct mlx5_ifc_pcmr_reg_bits {
9262         u8         reserved_at_0[0x8];
9263         u8         local_port[0x8];
9264         u8         reserved_at_10[0x10];
9265         u8         entropy_force_cap[0x1];
9266         u8         entropy_calc_cap[0x1];
9267         u8         entropy_gre_calc_cap[0x1];
9268         u8         reserved_at_23[0x1b];
9269         u8         fcs_cap[0x1];
9270         u8         reserved_at_3f[0x1];
9271         u8         entropy_force[0x1];
9272         u8         entropy_calc[0x1];
9273         u8         entropy_gre_calc[0x1];
9274         u8         reserved_at_43[0x1b];
9275         u8         fcs_chk[0x1];
9276         u8         reserved_at_5f[0x1];
9277 };
9278
9279 struct mlx5_ifc_lane_2_module_mapping_bits {
9280         u8         reserved_at_0[0x6];
9281         u8         rx_lane[0x2];
9282         u8         reserved_at_8[0x6];
9283         u8         tx_lane[0x2];
9284         u8         reserved_at_10[0x8];
9285         u8         module[0x8];
9286 };
9287
9288 struct mlx5_ifc_bufferx_reg_bits {
9289         u8         reserved_at_0[0x6];
9290         u8         lossy[0x1];
9291         u8         epsb[0x1];
9292         u8         reserved_at_8[0xc];
9293         u8         size[0xc];
9294
9295         u8         xoff_threshold[0x10];
9296         u8         xon_threshold[0x10];
9297 };
9298
9299 struct mlx5_ifc_set_node_in_bits {
9300         u8         node_description[64][0x8];
9301 };
9302
9303 struct mlx5_ifc_register_power_settings_bits {
9304         u8         reserved_at_0[0x18];
9305         u8         power_settings_level[0x8];
9306
9307         u8         reserved_at_20[0x60];
9308 };
9309
9310 struct mlx5_ifc_register_host_endianness_bits {
9311         u8         he[0x1];
9312         u8         reserved_at_1[0x1f];
9313
9314         u8         reserved_at_20[0x60];
9315 };
9316
9317 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9318         u8         reserved_at_0[0x20];
9319
9320         u8         mkey[0x20];
9321
9322         u8         addressh_63_32[0x20];
9323
9324         u8         addressl_31_0[0x20];
9325 };
9326
9327 struct mlx5_ifc_ud_adrs_vector_bits {
9328         u8         dc_key[0x40];
9329
9330         u8         ext[0x1];
9331         u8         reserved_at_41[0x7];
9332         u8         destination_qp_dct[0x18];
9333
9334         u8         static_rate[0x4];
9335         u8         sl_eth_prio[0x4];
9336         u8         fl[0x1];
9337         u8         mlid[0x7];
9338         u8         rlid_udp_sport[0x10];
9339
9340         u8         reserved_at_80[0x20];
9341
9342         u8         rmac_47_16[0x20];
9343
9344         u8         rmac_15_0[0x10];
9345         u8         tclass[0x8];
9346         u8         hop_limit[0x8];
9347
9348         u8         reserved_at_e0[0x1];
9349         u8         grh[0x1];
9350         u8         reserved_at_e2[0x2];
9351         u8         src_addr_index[0x8];
9352         u8         flow_label[0x14];
9353
9354         u8         rgid_rip[16][0x8];
9355 };
9356
9357 struct mlx5_ifc_pages_req_event_bits {
9358         u8         reserved_at_0[0x10];
9359         u8         function_id[0x10];
9360
9361         u8         num_pages[0x20];
9362
9363         u8         reserved_at_40[0xa0];
9364 };
9365
9366 struct mlx5_ifc_eqe_bits {
9367         u8         reserved_at_0[0x8];
9368         u8         event_type[0x8];
9369         u8         reserved_at_10[0x8];
9370         u8         event_sub_type[0x8];
9371
9372         u8         reserved_at_20[0xe0];
9373
9374         union mlx5_ifc_event_auto_bits event_data;
9375
9376         u8         reserved_at_1e0[0x10];
9377         u8         signature[0x8];
9378         u8         reserved_at_1f8[0x7];
9379         u8         owner[0x1];
9380 };
9381
9382 enum {
9383         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9384 };
9385
9386 struct mlx5_ifc_cmd_queue_entry_bits {
9387         u8         type[0x8];
9388         u8         reserved_at_8[0x18];
9389
9390         u8         input_length[0x20];
9391
9392         u8         input_mailbox_pointer_63_32[0x20];
9393
9394         u8         input_mailbox_pointer_31_9[0x17];
9395         u8         reserved_at_77[0x9];
9396
9397         u8         command_input_inline_data[16][0x8];
9398
9399         u8         command_output_inline_data[16][0x8];
9400
9401         u8         output_mailbox_pointer_63_32[0x20];
9402
9403         u8         output_mailbox_pointer_31_9[0x17];
9404         u8         reserved_at_1b7[0x9];
9405
9406         u8         output_length[0x20];
9407
9408         u8         token[0x8];
9409         u8         signature[0x8];
9410         u8         reserved_at_1f0[0x8];
9411         u8         status[0x7];
9412         u8         ownership[0x1];
9413 };
9414
9415 struct mlx5_ifc_cmd_out_bits {
9416         u8         status[0x8];
9417         u8         reserved_at_8[0x18];
9418
9419         u8         syndrome[0x20];
9420
9421         u8         command_output[0x20];
9422 };
9423
9424 struct mlx5_ifc_cmd_in_bits {
9425         u8         opcode[0x10];
9426         u8         reserved_at_10[0x10];
9427
9428         u8         reserved_at_20[0x10];
9429         u8         op_mod[0x10];
9430
9431         u8         command[][0x20];
9432 };
9433
9434 struct mlx5_ifc_cmd_if_box_bits {
9435         u8         mailbox_data[512][0x8];
9436
9437         u8         reserved_at_1000[0x180];
9438
9439         u8         next_pointer_63_32[0x20];
9440
9441         u8         next_pointer_31_10[0x16];
9442         u8         reserved_at_11b6[0xa];
9443
9444         u8         block_number[0x20];
9445
9446         u8         reserved_at_11e0[0x8];
9447         u8         token[0x8];
9448         u8         ctrl_signature[0x8];
9449         u8         signature[0x8];
9450 };
9451
9452 struct mlx5_ifc_mtt_bits {
9453         u8         ptag_63_32[0x20];
9454
9455         u8         ptag_31_8[0x18];
9456         u8         reserved_at_38[0x6];
9457         u8         wr_en[0x1];
9458         u8         rd_en[0x1];
9459 };
9460
9461 struct mlx5_ifc_query_wol_rol_out_bits {
9462         u8         status[0x8];
9463         u8         reserved_at_8[0x18];
9464
9465         u8         syndrome[0x20];
9466
9467         u8         reserved_at_40[0x10];
9468         u8         rol_mode[0x8];
9469         u8         wol_mode[0x8];
9470
9471         u8         reserved_at_60[0x20];
9472 };
9473
9474 struct mlx5_ifc_query_wol_rol_in_bits {
9475         u8         opcode[0x10];
9476         u8         reserved_at_10[0x10];
9477
9478         u8         reserved_at_20[0x10];
9479         u8         op_mod[0x10];
9480
9481         u8         reserved_at_40[0x40];
9482 };
9483
9484 struct mlx5_ifc_set_wol_rol_out_bits {
9485         u8         status[0x8];
9486         u8         reserved_at_8[0x18];
9487
9488         u8         syndrome[0x20];
9489
9490         u8         reserved_at_40[0x40];
9491 };
9492
9493 struct mlx5_ifc_set_wol_rol_in_bits {
9494         u8         opcode[0x10];
9495         u8         reserved_at_10[0x10];
9496
9497         u8         reserved_at_20[0x10];
9498         u8         op_mod[0x10];
9499
9500         u8         rol_mode_valid[0x1];
9501         u8         wol_mode_valid[0x1];
9502         u8         reserved_at_42[0xe];
9503         u8         rol_mode[0x8];
9504         u8         wol_mode[0x8];
9505
9506         u8         reserved_at_60[0x20];
9507 };
9508
9509 enum {
9510         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9511         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9512         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9513 };
9514
9515 enum {
9516         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9517         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9518         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9519 };
9520
9521 enum {
9522         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
9523         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
9524         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
9525         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
9526         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
9527         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
9528         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
9529         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
9530         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
9531         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
9532         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
9533 };
9534
9535 struct mlx5_ifc_initial_seg_bits {
9536         u8         fw_rev_minor[0x10];
9537         u8         fw_rev_major[0x10];
9538
9539         u8         cmd_interface_rev[0x10];
9540         u8         fw_rev_subminor[0x10];
9541
9542         u8         reserved_at_40[0x40];
9543
9544         u8         cmdq_phy_addr_63_32[0x20];
9545
9546         u8         cmdq_phy_addr_31_12[0x14];
9547         u8         reserved_at_b4[0x2];
9548         u8         nic_interface[0x2];
9549         u8         log_cmdq_size[0x4];
9550         u8         log_cmdq_stride[0x4];
9551
9552         u8         command_doorbell_vector[0x20];
9553
9554         u8         reserved_at_e0[0xf00];
9555
9556         u8         initializing[0x1];
9557         u8         reserved_at_fe1[0x4];
9558         u8         nic_interface_supported[0x3];
9559         u8         embedded_cpu[0x1];
9560         u8         reserved_at_fe9[0x17];
9561
9562         struct mlx5_ifc_health_buffer_bits health_buffer;
9563
9564         u8         no_dram_nic_offset[0x20];
9565
9566         u8         reserved_at_1220[0x6e40];
9567
9568         u8         reserved_at_8060[0x1f];
9569         u8         clear_int[0x1];
9570
9571         u8         health_syndrome[0x8];
9572         u8         health_counter[0x18];
9573
9574         u8         reserved_at_80a0[0x17fc0];
9575 };
9576
9577 struct mlx5_ifc_mtpps_reg_bits {
9578         u8         reserved_at_0[0xc];
9579         u8         cap_number_of_pps_pins[0x4];
9580         u8         reserved_at_10[0x4];
9581         u8         cap_max_num_of_pps_in_pins[0x4];
9582         u8         reserved_at_18[0x4];
9583         u8         cap_max_num_of_pps_out_pins[0x4];
9584
9585         u8         reserved_at_20[0x24];
9586         u8         cap_pin_3_mode[0x4];
9587         u8         reserved_at_48[0x4];
9588         u8         cap_pin_2_mode[0x4];
9589         u8         reserved_at_50[0x4];
9590         u8         cap_pin_1_mode[0x4];
9591         u8         reserved_at_58[0x4];
9592         u8         cap_pin_0_mode[0x4];
9593
9594         u8         reserved_at_60[0x4];
9595         u8         cap_pin_7_mode[0x4];
9596         u8         reserved_at_68[0x4];
9597         u8         cap_pin_6_mode[0x4];
9598         u8         reserved_at_70[0x4];
9599         u8         cap_pin_5_mode[0x4];
9600         u8         reserved_at_78[0x4];
9601         u8         cap_pin_4_mode[0x4];
9602
9603         u8         field_select[0x20];
9604         u8         reserved_at_a0[0x60];
9605
9606         u8         enable[0x1];
9607         u8         reserved_at_101[0xb];
9608         u8         pattern[0x4];
9609         u8         reserved_at_110[0x4];
9610         u8         pin_mode[0x4];
9611         u8         pin[0x8];
9612
9613         u8         reserved_at_120[0x20];
9614
9615         u8         time_stamp[0x40];
9616
9617         u8         out_pulse_duration[0x10];
9618         u8         out_periodic_adjustment[0x10];
9619         u8         enhanced_out_periodic_adjustment[0x20];
9620
9621         u8         reserved_at_1c0[0x20];
9622 };
9623
9624 struct mlx5_ifc_mtppse_reg_bits {
9625         u8         reserved_at_0[0x18];
9626         u8         pin[0x8];
9627         u8         event_arm[0x1];
9628         u8         reserved_at_21[0x1b];
9629         u8         event_generation_mode[0x4];
9630         u8         reserved_at_40[0x40];
9631 };
9632
9633 struct mlx5_ifc_mcqs_reg_bits {
9634         u8         last_index_flag[0x1];
9635         u8         reserved_at_1[0x7];
9636         u8         fw_device[0x8];
9637         u8         component_index[0x10];
9638
9639         u8         reserved_at_20[0x10];
9640         u8         identifier[0x10];
9641
9642         u8         reserved_at_40[0x17];
9643         u8         component_status[0x5];
9644         u8         component_update_state[0x4];
9645
9646         u8         last_update_state_changer_type[0x4];
9647         u8         last_update_state_changer_host_id[0x4];
9648         u8         reserved_at_68[0x18];
9649 };
9650
9651 struct mlx5_ifc_mcqi_cap_bits {
9652         u8         supported_info_bitmask[0x20];
9653
9654         u8         component_size[0x20];
9655
9656         u8         max_component_size[0x20];
9657
9658         u8         log_mcda_word_size[0x4];
9659         u8         reserved_at_64[0xc];
9660         u8         mcda_max_write_size[0x10];
9661
9662         u8         rd_en[0x1];
9663         u8         reserved_at_81[0x1];
9664         u8         match_chip_id[0x1];
9665         u8         match_psid[0x1];
9666         u8         check_user_timestamp[0x1];
9667         u8         match_base_guid_mac[0x1];
9668         u8         reserved_at_86[0x1a];
9669 };
9670
9671 struct mlx5_ifc_mcqi_version_bits {
9672         u8         reserved_at_0[0x2];
9673         u8         build_time_valid[0x1];
9674         u8         user_defined_time_valid[0x1];
9675         u8         reserved_at_4[0x14];
9676         u8         version_string_length[0x8];
9677
9678         u8         version[0x20];
9679
9680         u8         build_time[0x40];
9681
9682         u8         user_defined_time[0x40];
9683
9684         u8         build_tool_version[0x20];
9685
9686         u8         reserved_at_e0[0x20];
9687
9688         u8         version_string[92][0x8];
9689 };
9690
9691 struct mlx5_ifc_mcqi_activation_method_bits {
9692         u8         pending_server_ac_power_cycle[0x1];
9693         u8         pending_server_dc_power_cycle[0x1];
9694         u8         pending_server_reboot[0x1];
9695         u8         pending_fw_reset[0x1];
9696         u8         auto_activate[0x1];
9697         u8         all_hosts_sync[0x1];
9698         u8         device_hw_reset[0x1];
9699         u8         reserved_at_7[0x19];
9700 };
9701
9702 union mlx5_ifc_mcqi_reg_data_bits {
9703         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9704         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9705         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9706 };
9707
9708 struct mlx5_ifc_mcqi_reg_bits {
9709         u8         read_pending_component[0x1];
9710         u8         reserved_at_1[0xf];
9711         u8         component_index[0x10];
9712
9713         u8         reserved_at_20[0x20];
9714
9715         u8         reserved_at_40[0x1b];
9716         u8         info_type[0x5];
9717
9718         u8         info_size[0x20];
9719
9720         u8         offset[0x20];
9721
9722         u8         reserved_at_a0[0x10];
9723         u8         data_size[0x10];
9724
9725         union mlx5_ifc_mcqi_reg_data_bits data[];
9726 };
9727
9728 struct mlx5_ifc_mcc_reg_bits {
9729         u8         reserved_at_0[0x4];
9730         u8         time_elapsed_since_last_cmd[0xc];
9731         u8         reserved_at_10[0x8];
9732         u8         instruction[0x8];
9733
9734         u8         reserved_at_20[0x10];
9735         u8         component_index[0x10];
9736
9737         u8         reserved_at_40[0x8];
9738         u8         update_handle[0x18];
9739
9740         u8         handle_owner_type[0x4];
9741         u8         handle_owner_host_id[0x4];
9742         u8         reserved_at_68[0x1];
9743         u8         control_progress[0x7];
9744         u8         error_code[0x8];
9745         u8         reserved_at_78[0x4];
9746         u8         control_state[0x4];
9747
9748         u8         component_size[0x20];
9749
9750         u8         reserved_at_a0[0x60];
9751 };
9752
9753 struct mlx5_ifc_mcda_reg_bits {
9754         u8         reserved_at_0[0x8];
9755         u8         update_handle[0x18];
9756
9757         u8         offset[0x20];
9758
9759         u8         reserved_at_40[0x10];
9760         u8         size[0x10];
9761
9762         u8         reserved_at_60[0x20];
9763
9764         u8         data[][0x20];
9765 };
9766
9767 enum {
9768         MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
9769         MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
9770 };
9771
9772 enum {
9773         MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
9774         MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
9775         MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
9776 };
9777
9778 struct mlx5_ifc_mfrl_reg_bits {
9779         u8         reserved_at_0[0x20];
9780
9781         u8         reserved_at_20[0x2];
9782         u8         pci_sync_for_fw_update_start[0x1];
9783         u8         pci_sync_for_fw_update_resp[0x2];
9784         u8         rst_type_sel[0x3];
9785         u8         reserved_at_28[0x8];
9786         u8         reset_type[0x8];
9787         u8         reset_level[0x8];
9788 };
9789
9790 struct mlx5_ifc_mirc_reg_bits {
9791         u8         reserved_at_0[0x18];
9792         u8         status_code[0x8];
9793
9794         u8         reserved_at_20[0x20];
9795 };
9796
9797 union mlx5_ifc_ports_control_registers_document_bits {
9798         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9799         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9800         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9801         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9802         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9803         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9804         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9805         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9806         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9807         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9808         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9809         struct mlx5_ifc_paos_reg_bits paos_reg;
9810         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9811         struct mlx5_ifc_peir_reg_bits peir_reg;
9812         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9813         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9814         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9815         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9816         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9817         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9818         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9819         struct mlx5_ifc_plib_reg_bits plib_reg;
9820         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9821         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9822         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9823         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9824         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9825         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9826         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9827         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9828         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9829         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9830         struct mlx5_ifc_mpein_reg_bits mpein_reg;
9831         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9832         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9833         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9834         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9835         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9836         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9837         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9838         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9839         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9840         struct mlx5_ifc_pude_reg_bits pude_reg;
9841         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9842         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9843         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9844         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9845         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9846         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9847         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9848         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9849         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9850         struct mlx5_ifc_mcc_reg_bits mcc_reg;
9851         struct mlx5_ifc_mcda_reg_bits mcda_reg;
9852         struct mlx5_ifc_mirc_reg_bits mirc_reg;
9853         struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
9854         u8         reserved_at_0[0x60e0];
9855 };
9856
9857 union mlx5_ifc_debug_enhancements_document_bits {
9858         struct mlx5_ifc_health_buffer_bits health_buffer;
9859         u8         reserved_at_0[0x200];
9860 };
9861
9862 union mlx5_ifc_uplink_pci_interface_document_bits {
9863         struct mlx5_ifc_initial_seg_bits initial_seg;
9864         u8         reserved_at_0[0x20060];
9865 };
9866
9867 struct mlx5_ifc_set_flow_table_root_out_bits {
9868         u8         status[0x8];
9869         u8         reserved_at_8[0x18];
9870
9871         u8         syndrome[0x20];
9872
9873         u8         reserved_at_40[0x40];
9874 };
9875
9876 struct mlx5_ifc_set_flow_table_root_in_bits {
9877         u8         opcode[0x10];
9878         u8         reserved_at_10[0x10];
9879
9880         u8         reserved_at_20[0x10];
9881         u8         op_mod[0x10];
9882
9883         u8         other_vport[0x1];
9884         u8         reserved_at_41[0xf];
9885         u8         vport_number[0x10];
9886
9887         u8         reserved_at_60[0x20];
9888
9889         u8         table_type[0x8];
9890         u8         reserved_at_88[0x18];
9891
9892         u8         reserved_at_a0[0x8];
9893         u8         table_id[0x18];
9894
9895         u8         reserved_at_c0[0x8];
9896         u8         underlay_qpn[0x18];
9897         u8         reserved_at_e0[0x120];
9898 };
9899
9900 enum {
9901         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
9902         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9903 };
9904
9905 struct mlx5_ifc_modify_flow_table_out_bits {
9906         u8         status[0x8];
9907         u8         reserved_at_8[0x18];
9908
9909         u8         syndrome[0x20];
9910
9911         u8         reserved_at_40[0x40];
9912 };
9913
9914 struct mlx5_ifc_modify_flow_table_in_bits {
9915         u8         opcode[0x10];
9916         u8         reserved_at_10[0x10];
9917
9918         u8         reserved_at_20[0x10];
9919         u8         op_mod[0x10];
9920
9921         u8         other_vport[0x1];
9922         u8         reserved_at_41[0xf];
9923         u8         vport_number[0x10];
9924
9925         u8         reserved_at_60[0x10];
9926         u8         modify_field_select[0x10];
9927
9928         u8         table_type[0x8];
9929         u8         reserved_at_88[0x18];
9930
9931         u8         reserved_at_a0[0x8];
9932         u8         table_id[0x18];
9933
9934         struct mlx5_ifc_flow_table_context_bits flow_table_context;
9935 };
9936
9937 struct mlx5_ifc_ets_tcn_config_reg_bits {
9938         u8         g[0x1];
9939         u8         b[0x1];
9940         u8         r[0x1];
9941         u8         reserved_at_3[0x9];
9942         u8         group[0x4];
9943         u8         reserved_at_10[0x9];
9944         u8         bw_allocation[0x7];
9945
9946         u8         reserved_at_20[0xc];
9947         u8         max_bw_units[0x4];
9948         u8         reserved_at_30[0x8];
9949         u8         max_bw_value[0x8];
9950 };
9951
9952 struct mlx5_ifc_ets_global_config_reg_bits {
9953         u8         reserved_at_0[0x2];
9954         u8         r[0x1];
9955         u8         reserved_at_3[0x1d];
9956
9957         u8         reserved_at_20[0xc];
9958         u8         max_bw_units[0x4];
9959         u8         reserved_at_30[0x8];
9960         u8         max_bw_value[0x8];
9961 };
9962
9963 struct mlx5_ifc_qetc_reg_bits {
9964         u8                                         reserved_at_0[0x8];
9965         u8                                         port_number[0x8];
9966         u8                                         reserved_at_10[0x30];
9967
9968         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9969         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9970 };
9971
9972 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9973         u8         e[0x1];
9974         u8         reserved_at_01[0x0b];
9975         u8         prio[0x04];
9976 };
9977
9978 struct mlx5_ifc_qpdpm_reg_bits {
9979         u8                                     reserved_at_0[0x8];
9980         u8                                     local_port[0x8];
9981         u8                                     reserved_at_10[0x10];
9982         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9983 };
9984
9985 struct mlx5_ifc_qpts_reg_bits {
9986         u8         reserved_at_0[0x8];
9987         u8         local_port[0x8];
9988         u8         reserved_at_10[0x2d];
9989         u8         trust_state[0x3];
9990 };
9991
9992 struct mlx5_ifc_pptb_reg_bits {
9993         u8         reserved_at_0[0x2];
9994         u8         mm[0x2];
9995         u8         reserved_at_4[0x4];
9996         u8         local_port[0x8];
9997         u8         reserved_at_10[0x6];
9998         u8         cm[0x1];
9999         u8         um[0x1];
10000         u8         pm[0x8];
10001
10002         u8         prio_x_buff[0x20];
10003
10004         u8         pm_msb[0x8];
10005         u8         reserved_at_48[0x10];
10006         u8         ctrl_buff[0x4];
10007         u8         untagged_buff[0x4];
10008 };
10009
10010 struct mlx5_ifc_sbcam_reg_bits {
10011         u8         reserved_at_0[0x8];
10012         u8         feature_group[0x8];
10013         u8         reserved_at_10[0x8];
10014         u8         access_reg_group[0x8];
10015
10016         u8         reserved_at_20[0x20];
10017
10018         u8         sb_access_reg_cap_mask[4][0x20];
10019
10020         u8         reserved_at_c0[0x80];
10021
10022         u8         sb_feature_cap_mask[4][0x20];
10023
10024         u8         reserved_at_1c0[0x40];
10025
10026         u8         cap_total_buffer_size[0x20];
10027
10028         u8         cap_cell_size[0x10];
10029         u8         cap_max_pg_buffers[0x8];
10030         u8         cap_num_pool_supported[0x8];
10031
10032         u8         reserved_at_240[0x8];
10033         u8         cap_sbsr_stat_size[0x8];
10034         u8         cap_max_tclass_data[0x8];
10035         u8         cap_max_cpu_ingress_tclass_sb[0x8];
10036 };
10037
10038 struct mlx5_ifc_pbmc_reg_bits {
10039         u8         reserved_at_0[0x8];
10040         u8         local_port[0x8];
10041         u8         reserved_at_10[0x10];
10042
10043         u8         xoff_timer_value[0x10];
10044         u8         xoff_refresh[0x10];
10045
10046         u8         reserved_at_40[0x9];
10047         u8         fullness_threshold[0x7];
10048         u8         port_buffer_size[0x10];
10049
10050         struct mlx5_ifc_bufferx_reg_bits buffer[10];
10051
10052         u8         reserved_at_2e0[0x40];
10053 };
10054
10055 struct mlx5_ifc_qtct_reg_bits {
10056         u8         reserved_at_0[0x8];
10057         u8         port_number[0x8];
10058         u8         reserved_at_10[0xd];
10059         u8         prio[0x3];
10060
10061         u8         reserved_at_20[0x1d];
10062         u8         tclass[0x3];
10063 };
10064
10065 struct mlx5_ifc_mcia_reg_bits {
10066         u8         l[0x1];
10067         u8         reserved_at_1[0x7];
10068         u8         module[0x8];
10069         u8         reserved_at_10[0x8];
10070         u8         status[0x8];
10071
10072         u8         i2c_device_address[0x8];
10073         u8         page_number[0x8];
10074         u8         device_address[0x10];
10075
10076         u8         reserved_at_40[0x10];
10077         u8         size[0x10];
10078
10079         u8         reserved_at_60[0x20];
10080
10081         u8         dword_0[0x20];
10082         u8         dword_1[0x20];
10083         u8         dword_2[0x20];
10084         u8         dword_3[0x20];
10085         u8         dword_4[0x20];
10086         u8         dword_5[0x20];
10087         u8         dword_6[0x20];
10088         u8         dword_7[0x20];
10089         u8         dword_8[0x20];
10090         u8         dword_9[0x20];
10091         u8         dword_10[0x20];
10092         u8         dword_11[0x20];
10093 };
10094
10095 struct mlx5_ifc_dcbx_param_bits {
10096         u8         dcbx_cee_cap[0x1];
10097         u8         dcbx_ieee_cap[0x1];
10098         u8         dcbx_standby_cap[0x1];
10099         u8         reserved_at_3[0x5];
10100         u8         port_number[0x8];
10101         u8         reserved_at_10[0xa];
10102         u8         max_application_table_size[6];
10103         u8         reserved_at_20[0x15];
10104         u8         version_oper[0x3];
10105         u8         reserved_at_38[5];
10106         u8         version_admin[0x3];
10107         u8         willing_admin[0x1];
10108         u8         reserved_at_41[0x3];
10109         u8         pfc_cap_oper[0x4];
10110         u8         reserved_at_48[0x4];
10111         u8         pfc_cap_admin[0x4];
10112         u8         reserved_at_50[0x4];
10113         u8         num_of_tc_oper[0x4];
10114         u8         reserved_at_58[0x4];
10115         u8         num_of_tc_admin[0x4];
10116         u8         remote_willing[0x1];
10117         u8         reserved_at_61[3];
10118         u8         remote_pfc_cap[4];
10119         u8         reserved_at_68[0x14];
10120         u8         remote_num_of_tc[0x4];
10121         u8         reserved_at_80[0x18];
10122         u8         error[0x8];
10123         u8         reserved_at_a0[0x160];
10124 };
10125
10126 struct mlx5_ifc_lagc_bits {
10127         u8         reserved_at_0[0x1d];
10128         u8         lag_state[0x3];
10129
10130         u8         reserved_at_20[0x14];
10131         u8         tx_remap_affinity_2[0x4];
10132         u8         reserved_at_38[0x4];
10133         u8         tx_remap_affinity_1[0x4];
10134 };
10135
10136 struct mlx5_ifc_create_lag_out_bits {
10137         u8         status[0x8];
10138         u8         reserved_at_8[0x18];
10139
10140         u8         syndrome[0x20];
10141
10142         u8         reserved_at_40[0x40];
10143 };
10144
10145 struct mlx5_ifc_create_lag_in_bits {
10146         u8         opcode[0x10];
10147         u8         reserved_at_10[0x10];
10148
10149         u8         reserved_at_20[0x10];
10150         u8         op_mod[0x10];
10151
10152         struct mlx5_ifc_lagc_bits ctx;
10153 };
10154
10155 struct mlx5_ifc_modify_lag_out_bits {
10156         u8         status[0x8];
10157         u8         reserved_at_8[0x18];
10158
10159         u8         syndrome[0x20];
10160
10161         u8         reserved_at_40[0x40];
10162 };
10163
10164 struct mlx5_ifc_modify_lag_in_bits {
10165         u8         opcode[0x10];
10166         u8         reserved_at_10[0x10];
10167
10168         u8         reserved_at_20[0x10];
10169         u8         op_mod[0x10];
10170
10171         u8         reserved_at_40[0x20];
10172         u8         field_select[0x20];
10173
10174         struct mlx5_ifc_lagc_bits ctx;
10175 };
10176
10177 struct mlx5_ifc_query_lag_out_bits {
10178         u8         status[0x8];
10179         u8         reserved_at_8[0x18];
10180
10181         u8         syndrome[0x20];
10182
10183         struct mlx5_ifc_lagc_bits ctx;
10184 };
10185
10186 struct mlx5_ifc_query_lag_in_bits {
10187         u8         opcode[0x10];
10188         u8         reserved_at_10[0x10];
10189
10190         u8         reserved_at_20[0x10];
10191         u8         op_mod[0x10];
10192
10193         u8         reserved_at_40[0x40];
10194 };
10195
10196 struct mlx5_ifc_destroy_lag_out_bits {
10197         u8         status[0x8];
10198         u8         reserved_at_8[0x18];
10199
10200         u8         syndrome[0x20];
10201
10202         u8         reserved_at_40[0x40];
10203 };
10204
10205 struct mlx5_ifc_destroy_lag_in_bits {
10206         u8         opcode[0x10];
10207         u8         reserved_at_10[0x10];
10208
10209         u8         reserved_at_20[0x10];
10210         u8         op_mod[0x10];
10211
10212         u8         reserved_at_40[0x40];
10213 };
10214
10215 struct mlx5_ifc_create_vport_lag_out_bits {
10216         u8         status[0x8];
10217         u8         reserved_at_8[0x18];
10218
10219         u8         syndrome[0x20];
10220
10221         u8         reserved_at_40[0x40];
10222 };
10223
10224 struct mlx5_ifc_create_vport_lag_in_bits {
10225         u8         opcode[0x10];
10226         u8         reserved_at_10[0x10];
10227
10228         u8         reserved_at_20[0x10];
10229         u8         op_mod[0x10];
10230
10231         u8         reserved_at_40[0x40];
10232 };
10233
10234 struct mlx5_ifc_destroy_vport_lag_out_bits {
10235         u8         status[0x8];
10236         u8         reserved_at_8[0x18];
10237
10238         u8         syndrome[0x20];
10239
10240         u8         reserved_at_40[0x40];
10241 };
10242
10243 struct mlx5_ifc_destroy_vport_lag_in_bits {
10244         u8         opcode[0x10];
10245         u8         reserved_at_10[0x10];
10246
10247         u8         reserved_at_20[0x10];
10248         u8         op_mod[0x10];
10249
10250         u8         reserved_at_40[0x40];
10251 };
10252
10253 struct mlx5_ifc_alloc_memic_in_bits {
10254         u8         opcode[0x10];
10255         u8         reserved_at_10[0x10];
10256
10257         u8         reserved_at_20[0x10];
10258         u8         op_mod[0x10];
10259
10260         u8         reserved_at_30[0x20];
10261
10262         u8         reserved_at_40[0x18];
10263         u8         log_memic_addr_alignment[0x8];
10264
10265         u8         range_start_addr[0x40];
10266
10267         u8         range_size[0x20];
10268
10269         u8         memic_size[0x20];
10270 };
10271
10272 struct mlx5_ifc_alloc_memic_out_bits {
10273         u8         status[0x8];
10274         u8         reserved_at_8[0x18];
10275
10276         u8         syndrome[0x20];
10277
10278         u8         memic_start_addr[0x40];
10279 };
10280
10281 struct mlx5_ifc_dealloc_memic_in_bits {
10282         u8         opcode[0x10];
10283         u8         reserved_at_10[0x10];
10284
10285         u8         reserved_at_20[0x10];
10286         u8         op_mod[0x10];
10287
10288         u8         reserved_at_40[0x40];
10289
10290         u8         memic_start_addr[0x40];
10291
10292         u8         memic_size[0x20];
10293
10294         u8         reserved_at_e0[0x20];
10295 };
10296
10297 struct mlx5_ifc_dealloc_memic_out_bits {
10298         u8         status[0x8];
10299         u8         reserved_at_8[0x18];
10300
10301         u8         syndrome[0x20];
10302
10303         u8         reserved_at_40[0x40];
10304 };
10305
10306 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10307         u8         opcode[0x10];
10308         u8         uid[0x10];
10309
10310         u8         vhca_tunnel_id[0x10];
10311         u8         obj_type[0x10];
10312
10313         u8         obj_id[0x20];
10314
10315         u8         reserved_at_60[0x20];
10316 };
10317
10318 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10319         u8         status[0x8];
10320         u8         reserved_at_8[0x18];
10321
10322         u8         syndrome[0x20];
10323
10324         u8         obj_id[0x20];
10325
10326         u8         reserved_at_60[0x20];
10327 };
10328
10329 struct mlx5_ifc_umem_bits {
10330         u8         reserved_at_0[0x80];
10331
10332         u8         reserved_at_80[0x1b];
10333         u8         log_page_size[0x5];
10334
10335         u8         page_offset[0x20];
10336
10337         u8         num_of_mtt[0x40];
10338
10339         struct mlx5_ifc_mtt_bits  mtt[];
10340 };
10341
10342 struct mlx5_ifc_uctx_bits {
10343         u8         cap[0x20];
10344
10345         u8         reserved_at_20[0x160];
10346 };
10347
10348 struct mlx5_ifc_sw_icm_bits {
10349         u8         modify_field_select[0x40];
10350
10351         u8         reserved_at_40[0x18];
10352         u8         log_sw_icm_size[0x8];
10353
10354         u8         reserved_at_60[0x20];
10355
10356         u8         sw_icm_start_addr[0x40];
10357
10358         u8         reserved_at_c0[0x140];
10359 };
10360
10361 struct mlx5_ifc_geneve_tlv_option_bits {
10362         u8         modify_field_select[0x40];
10363
10364         u8         reserved_at_40[0x18];
10365         u8         geneve_option_fte_index[0x8];
10366
10367         u8         option_class[0x10];
10368         u8         option_type[0x8];
10369         u8         reserved_at_78[0x3];
10370         u8         option_data_length[0x5];
10371
10372         u8         reserved_at_80[0x180];
10373 };
10374
10375 struct mlx5_ifc_create_umem_in_bits {
10376         u8         opcode[0x10];
10377         u8         uid[0x10];
10378
10379         u8         reserved_at_20[0x10];
10380         u8         op_mod[0x10];
10381
10382         u8         reserved_at_40[0x40];
10383
10384         struct mlx5_ifc_umem_bits  umem;
10385 };
10386
10387 struct mlx5_ifc_create_umem_out_bits {
10388         u8         status[0x8];
10389         u8         reserved_at_8[0x18];
10390
10391         u8         syndrome[0x20];
10392
10393         u8         reserved_at_40[0x8];
10394         u8         umem_id[0x18];
10395
10396         u8         reserved_at_60[0x20];
10397 };
10398
10399 struct mlx5_ifc_destroy_umem_in_bits {
10400         u8        opcode[0x10];
10401         u8        uid[0x10];
10402
10403         u8        reserved_at_20[0x10];
10404         u8        op_mod[0x10];
10405
10406         u8        reserved_at_40[0x8];
10407         u8        umem_id[0x18];
10408
10409         u8        reserved_at_60[0x20];
10410 };
10411
10412 struct mlx5_ifc_destroy_umem_out_bits {
10413         u8        status[0x8];
10414         u8        reserved_at_8[0x18];
10415
10416         u8        syndrome[0x20];
10417
10418         u8        reserved_at_40[0x40];
10419 };
10420
10421 struct mlx5_ifc_create_uctx_in_bits {
10422         u8         opcode[0x10];
10423         u8         reserved_at_10[0x10];
10424
10425         u8         reserved_at_20[0x10];
10426         u8         op_mod[0x10];
10427
10428         u8         reserved_at_40[0x40];
10429
10430         struct mlx5_ifc_uctx_bits  uctx;
10431 };
10432
10433 struct mlx5_ifc_create_uctx_out_bits {
10434         u8         status[0x8];
10435         u8         reserved_at_8[0x18];
10436
10437         u8         syndrome[0x20];
10438
10439         u8         reserved_at_40[0x10];
10440         u8         uid[0x10];
10441
10442         u8         reserved_at_60[0x20];
10443 };
10444
10445 struct mlx5_ifc_destroy_uctx_in_bits {
10446         u8         opcode[0x10];
10447         u8         reserved_at_10[0x10];
10448
10449         u8         reserved_at_20[0x10];
10450         u8         op_mod[0x10];
10451
10452         u8         reserved_at_40[0x10];
10453         u8         uid[0x10];
10454
10455         u8         reserved_at_60[0x20];
10456 };
10457
10458 struct mlx5_ifc_destroy_uctx_out_bits {
10459         u8         status[0x8];
10460         u8         reserved_at_8[0x18];
10461
10462         u8         syndrome[0x20];
10463
10464         u8          reserved_at_40[0x40];
10465 };
10466
10467 struct mlx5_ifc_create_sw_icm_in_bits {
10468         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10469         struct mlx5_ifc_sw_icm_bits                   sw_icm;
10470 };
10471
10472 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10473         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10474         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
10475 };
10476
10477 struct mlx5_ifc_mtrc_string_db_param_bits {
10478         u8         string_db_base_address[0x20];
10479
10480         u8         reserved_at_20[0x8];
10481         u8         string_db_size[0x18];
10482 };
10483
10484 struct mlx5_ifc_mtrc_cap_bits {
10485         u8         trace_owner[0x1];
10486         u8         trace_to_memory[0x1];
10487         u8         reserved_at_2[0x4];
10488         u8         trc_ver[0x2];
10489         u8         reserved_at_8[0x14];
10490         u8         num_string_db[0x4];
10491
10492         u8         first_string_trace[0x8];
10493         u8         num_string_trace[0x8];
10494         u8         reserved_at_30[0x28];
10495
10496         u8         log_max_trace_buffer_size[0x8];
10497
10498         u8         reserved_at_60[0x20];
10499
10500         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10501
10502         u8         reserved_at_280[0x180];
10503 };
10504
10505 struct mlx5_ifc_mtrc_conf_bits {
10506         u8         reserved_at_0[0x1c];
10507         u8         trace_mode[0x4];
10508         u8         reserved_at_20[0x18];
10509         u8         log_trace_buffer_size[0x8];
10510         u8         trace_mkey[0x20];
10511         u8         reserved_at_60[0x3a0];
10512 };
10513
10514 struct mlx5_ifc_mtrc_stdb_bits {
10515         u8         string_db_index[0x4];
10516         u8         reserved_at_4[0x4];
10517         u8         read_size[0x18];
10518         u8         start_offset[0x20];
10519         u8         string_db_data[];
10520 };
10521
10522 struct mlx5_ifc_mtrc_ctrl_bits {
10523         u8         trace_status[0x2];
10524         u8         reserved_at_2[0x2];
10525         u8         arm_event[0x1];
10526         u8         reserved_at_5[0xb];
10527         u8         modify_field_select[0x10];
10528         u8         reserved_at_20[0x2b];
10529         u8         current_timestamp52_32[0x15];
10530         u8         current_timestamp31_0[0x20];
10531         u8         reserved_at_80[0x180];
10532 };
10533
10534 struct mlx5_ifc_host_params_context_bits {
10535         u8         host_number[0x8];
10536         u8         reserved_at_8[0x7];
10537         u8         host_pf_disabled[0x1];
10538         u8         host_num_of_vfs[0x10];
10539
10540         u8         host_total_vfs[0x10];
10541         u8         host_pci_bus[0x10];
10542
10543         u8         reserved_at_40[0x10];
10544         u8         host_pci_device[0x10];
10545
10546         u8         reserved_at_60[0x10];
10547         u8         host_pci_function[0x10];
10548
10549         u8         reserved_at_80[0x180];
10550 };
10551
10552 struct mlx5_ifc_query_esw_functions_in_bits {
10553         u8         opcode[0x10];
10554         u8         reserved_at_10[0x10];
10555
10556         u8         reserved_at_20[0x10];
10557         u8         op_mod[0x10];
10558
10559         u8         reserved_at_40[0x40];
10560 };
10561
10562 struct mlx5_ifc_query_esw_functions_out_bits {
10563         u8         status[0x8];
10564         u8         reserved_at_8[0x18];
10565
10566         u8         syndrome[0x20];
10567
10568         u8         reserved_at_40[0x40];
10569
10570         struct mlx5_ifc_host_params_context_bits host_params_context;
10571
10572         u8         reserved_at_280[0x180];
10573         u8         host_sf_enable[][0x40];
10574 };
10575
10576 struct mlx5_ifc_sf_partition_bits {
10577         u8         reserved_at_0[0x10];
10578         u8         log_num_sf[0x8];
10579         u8         log_sf_bar_size[0x8];
10580 };
10581
10582 struct mlx5_ifc_query_sf_partitions_out_bits {
10583         u8         status[0x8];
10584         u8         reserved_at_8[0x18];
10585
10586         u8         syndrome[0x20];
10587
10588         u8         reserved_at_40[0x18];
10589         u8         num_sf_partitions[0x8];
10590
10591         u8         reserved_at_60[0x20];
10592
10593         struct mlx5_ifc_sf_partition_bits sf_partition[];
10594 };
10595
10596 struct mlx5_ifc_query_sf_partitions_in_bits {
10597         u8         opcode[0x10];
10598         u8         reserved_at_10[0x10];
10599
10600         u8         reserved_at_20[0x10];
10601         u8         op_mod[0x10];
10602
10603         u8         reserved_at_40[0x40];
10604 };
10605
10606 struct mlx5_ifc_dealloc_sf_out_bits {
10607         u8         status[0x8];
10608         u8         reserved_at_8[0x18];
10609
10610         u8         syndrome[0x20];
10611
10612         u8         reserved_at_40[0x40];
10613 };
10614
10615 struct mlx5_ifc_dealloc_sf_in_bits {
10616         u8         opcode[0x10];
10617         u8         reserved_at_10[0x10];
10618
10619         u8         reserved_at_20[0x10];
10620         u8         op_mod[0x10];
10621
10622         u8         reserved_at_40[0x10];
10623         u8         function_id[0x10];
10624
10625         u8         reserved_at_60[0x20];
10626 };
10627
10628 struct mlx5_ifc_alloc_sf_out_bits {
10629         u8         status[0x8];
10630         u8         reserved_at_8[0x18];
10631
10632         u8         syndrome[0x20];
10633
10634         u8         reserved_at_40[0x40];
10635 };
10636
10637 struct mlx5_ifc_alloc_sf_in_bits {
10638         u8         opcode[0x10];
10639         u8         reserved_at_10[0x10];
10640
10641         u8         reserved_at_20[0x10];
10642         u8         op_mod[0x10];
10643
10644         u8         reserved_at_40[0x10];
10645         u8         function_id[0x10];
10646
10647         u8         reserved_at_60[0x20];
10648 };
10649
10650 struct mlx5_ifc_affiliated_event_header_bits {
10651         u8         reserved_at_0[0x10];
10652         u8         obj_type[0x10];
10653
10654         u8         obj_id[0x20];
10655 };
10656
10657 enum {
10658         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10659         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
10660 };
10661
10662 enum {
10663         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10664         MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
10665 };
10666
10667 enum {
10668         MLX5_IPSEC_OBJECT_ICV_LEN_16B,
10669         MLX5_IPSEC_OBJECT_ICV_LEN_12B,
10670         MLX5_IPSEC_OBJECT_ICV_LEN_8B,
10671 };
10672
10673 struct mlx5_ifc_ipsec_obj_bits {
10674         u8         modify_field_select[0x40];
10675         u8         full_offload[0x1];
10676         u8         reserved_at_41[0x1];
10677         u8         esn_en[0x1];
10678         u8         esn_overlap[0x1];
10679         u8         reserved_at_44[0x2];
10680         u8         icv_length[0x2];
10681         u8         reserved_at_48[0x4];
10682         u8         aso_return_reg[0x4];
10683         u8         reserved_at_50[0x10];
10684
10685         u8         esn_msb[0x20];
10686
10687         u8         reserved_at_80[0x8];
10688         u8         dekn[0x18];
10689
10690         u8         salt[0x20];
10691
10692         u8         implicit_iv[0x40];
10693
10694         u8         reserved_at_100[0x700];
10695 };
10696
10697 struct mlx5_ifc_create_ipsec_obj_in_bits {
10698         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10699         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10700 };
10701
10702 enum {
10703         MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
10704         MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
10705 };
10706
10707 struct mlx5_ifc_query_ipsec_obj_out_bits {
10708         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
10709         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10710 };
10711
10712 struct mlx5_ifc_modify_ipsec_obj_in_bits {
10713         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10714         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10715 };
10716
10717 struct mlx5_ifc_encryption_key_obj_bits {
10718         u8         modify_field_select[0x40];
10719
10720         u8         reserved_at_40[0x14];
10721         u8         key_size[0x4];
10722         u8         reserved_at_58[0x4];
10723         u8         key_type[0x4];
10724
10725         u8         reserved_at_60[0x8];
10726         u8         pd[0x18];
10727
10728         u8         reserved_at_80[0x180];
10729         u8         key[8][0x20];
10730
10731         u8         reserved_at_300[0x500];
10732 };
10733
10734 struct mlx5_ifc_create_encryption_key_in_bits {
10735         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10736         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10737 };
10738
10739 enum {
10740         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10741         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10742 };
10743
10744 enum {
10745         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
10746         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
10747 };
10748
10749 struct mlx5_ifc_tls_static_params_bits {
10750         u8         const_2[0x2];
10751         u8         tls_version[0x4];
10752         u8         const_1[0x2];
10753         u8         reserved_at_8[0x14];
10754         u8         encryption_standard[0x4];
10755
10756         u8         reserved_at_20[0x20];
10757
10758         u8         initial_record_number[0x40];
10759
10760         u8         resync_tcp_sn[0x20];
10761
10762         u8         gcm_iv[0x20];
10763
10764         u8         implicit_iv[0x40];
10765
10766         u8         reserved_at_100[0x8];
10767         u8         dek_index[0x18];
10768
10769         u8         reserved_at_120[0xe0];
10770 };
10771
10772 struct mlx5_ifc_tls_progress_params_bits {
10773         u8         next_record_tcp_sn[0x20];
10774
10775         u8         hw_resync_tcp_sn[0x20];
10776
10777         u8         record_tracker_state[0x2];
10778         u8         auth_state[0x2];
10779         u8         reserved_at_44[0x4];
10780         u8         hw_offset_record_number[0x18];
10781 };
10782
10783 enum {
10784         MLX5_MTT_PERM_READ      = 1 << 0,
10785         MLX5_MTT_PERM_WRITE     = 1 << 1,
10786         MLX5_MTT_PERM_RW        = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
10787 };
10788
10789 #endif /* MLX5_IFC_H */