include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77 };
  78
  79 enum {
  80         MLX5_SHARED_RESOURCE_UID = 0xffff,
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  85 };
  86
  87 enum {
  88         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  89 };
  90
  91 enum {
  92         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  93         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  94         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  95         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  96         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  97         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  98         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  99         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 100         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 101         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 102         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 103         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 104         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 105         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 106         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 107         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 108         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 109         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 110         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 111         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 112         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 113         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 114         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 115         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 116         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 117         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 118         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 119         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 120         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 121         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 122         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 123         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 124         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 125         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 126         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 127         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 128         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 129         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 130         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 131         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 132         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 133         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 134         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 135         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 136         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 137         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 138         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 139         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 140         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 141         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 142         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 143         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 144         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 145         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 146         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 147         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 148         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 149         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 150         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 151         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 152         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 153         MLX5_CMD_OP_QUERY_HOST_PARAMS             = 0x740,
 154         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 155         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 156         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 157         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 158         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 159         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 160         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 161         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 162         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 163         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 164         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 165         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 166         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 167         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 168         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 169         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 170         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 171         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 172         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 173         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 174         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 175         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 176         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 177         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 178         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 179         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 180         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 181         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 182         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 183         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 184         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 185         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 186         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 187         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 188         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 189         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 190         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 191         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 192         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 193         MLX5_CMD_OP_NOP                           = 0x80d,
 194         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 195         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 196         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 197         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 198         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 199         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 200         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 201         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 202         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 203         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 204         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 205         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 206         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 207         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 208         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 209         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 210         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 211         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 212         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 213         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 214         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 215         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 216         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 217         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 218         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 219         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 220         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 221         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 222         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 223         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 224         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 225         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 226         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 227         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 228         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 229         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 230         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 231         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 232         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 233         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 234         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 235         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 236         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 237         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 238         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 239         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 240         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 241         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 242         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 243         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 244         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 245         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 246         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 247         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 248         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 249         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 250         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 251         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 252         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 253         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 254         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 255         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 256         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 257         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 258         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 259         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 260         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 261         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 262         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 263         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 264         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 265         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 266         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 267         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 268         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 269         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 270         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 271         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 272         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 273         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 274         MLX5_CMD_OP_MAX
 275 };
 276
 277 /* Valid range for general commands that don't work over an object */
 278 enum {
 279         MLX5_CMD_OP_GENERAL_START = 0xb00,
 280         MLX5_CMD_OP_GENERAL_END = 0xd00,
 281 };
 282
 283 struct mlx5_ifc_flow_table_fields_supported_bits {
 284         u8         outer_dmac[0x1];
 285         u8         outer_smac[0x1];
 286         u8         outer_ether_type[0x1];
 287         u8         outer_ip_version[0x1];
 288         u8         outer_first_prio[0x1];
 289         u8         outer_first_cfi[0x1];
 290         u8         outer_first_vid[0x1];
 291         u8         outer_ipv4_ttl[0x1];
 292         u8         outer_second_prio[0x1];
 293         u8         outer_second_cfi[0x1];
 294         u8         outer_second_vid[0x1];
 295         u8         reserved_at_b[0x1];
 296         u8         outer_sip[0x1];
 297         u8         outer_dip[0x1];
 298         u8         outer_frag[0x1];
 299         u8         outer_ip_protocol[0x1];
 300         u8         outer_ip_ecn[0x1];
 301         u8         outer_ip_dscp[0x1];
 302         u8         outer_udp_sport[0x1];
 303         u8         outer_udp_dport[0x1];
 304         u8         outer_tcp_sport[0x1];
 305         u8         outer_tcp_dport[0x1];
 306         u8         outer_tcp_flags[0x1];
 307         u8         outer_gre_protocol[0x1];
 308         u8         outer_gre_key[0x1];
 309         u8         outer_vxlan_vni[0x1];
 310         u8         reserved_at_1a[0x5];
 311         u8         source_eswitch_port[0x1];
 312
 313         u8         inner_dmac[0x1];
 314         u8         inner_smac[0x1];
 315         u8         inner_ether_type[0x1];
 316         u8         inner_ip_version[0x1];
 317         u8         inner_first_prio[0x1];
 318         u8         inner_first_cfi[0x1];
 319         u8         inner_first_vid[0x1];
 320         u8         reserved_at_27[0x1];
 321         u8         inner_second_prio[0x1];
 322         u8         inner_second_cfi[0x1];
 323         u8         inner_second_vid[0x1];
 324         u8         reserved_at_2b[0x1];
 325         u8         inner_sip[0x1];
 326         u8         inner_dip[0x1];
 327         u8         inner_frag[0x1];
 328         u8         inner_ip_protocol[0x1];
 329         u8         inner_ip_ecn[0x1];
 330         u8         inner_ip_dscp[0x1];
 331         u8         inner_udp_sport[0x1];
 332         u8         inner_udp_dport[0x1];
 333         u8         inner_tcp_sport[0x1];
 334         u8         inner_tcp_dport[0x1];
 335         u8         inner_tcp_flags[0x1];
 336         u8         reserved_at_37[0x9];
 337
 338         u8         reserved_at_40[0x5];
 339         u8         outer_first_mpls_over_udp[0x4];
 340         u8         outer_first_mpls_over_gre[0x4];
 341         u8         inner_first_mpls[0x4];
 342         u8         outer_first_mpls[0x4];
 343         u8         reserved_at_55[0x2];
 344         u8         outer_esp_spi[0x1];
 345         u8         reserved_at_58[0x2];
 346         u8         bth_dst_qp[0x1];
 347
 348         u8         reserved_at_5b[0x25];
 349 };
 350
 351 struct mlx5_ifc_flow_table_prop_layout_bits {
 352         u8         ft_support[0x1];
 353         u8         reserved_at_1[0x1];
 354         u8         flow_counter[0x1];
 355         u8         flow_modify_en[0x1];
 356         u8         modify_root[0x1];
 357         u8         identified_miss_table_mode[0x1];
 358         u8         flow_table_modify[0x1];
 359         u8         reformat[0x1];
 360         u8         decap[0x1];
 361         u8         reserved_at_9[0x1];
 362         u8         pop_vlan[0x1];
 363         u8         push_vlan[0x1];
 364         u8         reserved_at_c[0x1];
 365         u8         pop_vlan_2[0x1];
 366         u8         push_vlan_2[0x1];
 367         u8         reformat_and_vlan_action[0x1];
 368         u8         reserved_at_10[0x1];
 369         u8         sw_owner[0x1];
 370         u8         reformat_l3_tunnel_to_l2[0x1];
 371         u8         reformat_l2_to_l3_tunnel[0x1];
 372         u8         reformat_and_modify_action[0x1];
 373         u8         reserved_at_15[0x2];
 374         u8         table_miss_action_domain[0x1];
 375         u8         reserved_at_18[0x8];
 376         u8         reserved_at_20[0x2];
 377         u8         log_max_ft_size[0x6];
 378         u8         log_max_modify_header_context[0x8];
 379         u8         max_modify_header_actions[0x8];
 380         u8         max_ft_level[0x8];
 381
 382         u8         reserved_at_40[0x20];
 383
 384         u8         reserved_at_60[0x18];
 385         u8         log_max_ft_num[0x8];
 386
 387         u8         reserved_at_80[0x18];
 388         u8         log_max_destination[0x8];
 389
 390         u8         log_max_flow_counter[0x8];
 391         u8         reserved_at_a8[0x10];
 392         u8         log_max_flow[0x8];
 393
 394         u8         reserved_at_c0[0x40];
 395
 396         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 397
 398         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 399 };
 400
 401 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 402         u8         send[0x1];
 403         u8         receive[0x1];
 404         u8         write[0x1];
 405         u8         read[0x1];
 406         u8         atomic[0x1];
 407         u8         srq_receive[0x1];
 408         u8         reserved_at_6[0x1a];
 409 };
 410
 411 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 412         u8         smac_47_16[0x20];
 413
 414         u8         smac_15_0[0x10];
 415         u8         ethertype[0x10];
 416
 417         u8         dmac_47_16[0x20];
 418
 419         u8         dmac_15_0[0x10];
 420         u8         first_prio[0x3];
 421         u8         first_cfi[0x1];
 422         u8         first_vid[0xc];
 423
 424         u8         ip_protocol[0x8];
 425         u8         ip_dscp[0x6];
 426         u8         ip_ecn[0x2];
 427         u8         cvlan_tag[0x1];
 428         u8         svlan_tag[0x1];
 429         u8         frag[0x1];
 430         u8         ip_version[0x4];
 431         u8         tcp_flags[0x9];
 432
 433         u8         tcp_sport[0x10];
 434         u8         tcp_dport[0x10];
 435
 436         u8         reserved_at_c0[0x18];
 437         u8         ttl_hoplimit[0x8];
 438
 439         u8         udp_sport[0x10];
 440         u8         udp_dport[0x10];
 441
 442         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 443
 444         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 445 };
 446
 447 struct mlx5_ifc_nvgre_key_bits {
 448         u8 hi[0x18];
 449         u8 lo[0x8];
 450 };
 451
 452 union mlx5_ifc_gre_key_bits {
 453         struct mlx5_ifc_nvgre_key_bits nvgre;
 454         u8 key[0x20];
 455 };
 456
 457 struct mlx5_ifc_fte_match_set_misc_bits {
 458         u8         reserved_at_0[0x8];
 459         u8         source_sqn[0x18];
 460
 461         u8         source_eswitch_owner_vhca_id[0x10];
 462         u8         source_port[0x10];
 463
 464         u8         outer_second_prio[0x3];
 465         u8         outer_second_cfi[0x1];
 466         u8         outer_second_vid[0xc];
 467         u8         inner_second_prio[0x3];
 468         u8         inner_second_cfi[0x1];
 469         u8         inner_second_vid[0xc];
 470
 471         u8         outer_second_cvlan_tag[0x1];
 472         u8         inner_second_cvlan_tag[0x1];
 473         u8         outer_second_svlan_tag[0x1];
 474         u8         inner_second_svlan_tag[0x1];
 475         u8         reserved_at_64[0xc];
 476         u8         gre_protocol[0x10];
 477
 478         union mlx5_ifc_gre_key_bits gre_key;
 479
 480         u8         vxlan_vni[0x18];
 481         u8         reserved_at_b8[0x8];
 482
 483         u8         reserved_at_c0[0x20];
 484
 485         u8         reserved_at_e0[0xc];
 486         u8         outer_ipv6_flow_label[0x14];
 487
 488         u8         reserved_at_100[0xc];
 489         u8         inner_ipv6_flow_label[0x14];
 490
 491         u8         reserved_at_120[0x28];
 492         u8         bth_dst_qp[0x18];
 493         u8         reserved_at_160[0x20];
 494         u8         outer_esp_spi[0x20];
 495         u8         reserved_at_1a0[0x60];
 496 };
 497
 498 struct mlx5_ifc_fte_match_mpls_bits {
 499         u8         mpls_label[0x14];
 500         u8         mpls_exp[0x3];
 501         u8         mpls_s_bos[0x1];
 502         u8         mpls_ttl[0x8];
 503 };
 504
 505 struct mlx5_ifc_fte_match_set_misc2_bits {
 506         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 507
 508         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 509
 510         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 511
 512         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 513
 514         u8         reserved_at_80[0x100];
 515
 516         u8         metadata_reg_a[0x20];
 517
 518         u8         reserved_at_1a0[0x60];
 519 };
 520
 521 struct mlx5_ifc_cmd_pas_bits {
 522         u8         pa_h[0x20];
 523
 524         u8         pa_l[0x14];
 525         u8         reserved_at_34[0xc];
 526 };
 527
 528 struct mlx5_ifc_uint64_bits {
 529         u8         hi[0x20];
 530
 531         u8         lo[0x20];
 532 };
 533
 534 enum {
 535         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 536         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 537         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 538         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 539         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 540         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 541         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 542         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 543         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 544         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 545 };
 546
 547 struct mlx5_ifc_ads_bits {
 548         u8         fl[0x1];
 549         u8         free_ar[0x1];
 550         u8         reserved_at_2[0xe];
 551         u8         pkey_index[0x10];
 552
 553         u8         reserved_at_20[0x8];
 554         u8         grh[0x1];
 555         u8         mlid[0x7];
 556         u8         rlid[0x10];
 557
 558         u8         ack_timeout[0x5];
 559         u8         reserved_at_45[0x3];
 560         u8         src_addr_index[0x8];
 561         u8         reserved_at_50[0x4];
 562         u8         stat_rate[0x4];
 563         u8         hop_limit[0x8];
 564
 565         u8         reserved_at_60[0x4];
 566         u8         tclass[0x8];
 567         u8         flow_label[0x14];
 568
 569         u8         rgid_rip[16][0x8];
 570
 571         u8         reserved_at_100[0x4];
 572         u8         f_dscp[0x1];
 573         u8         f_ecn[0x1];
 574         u8         reserved_at_106[0x1];
 575         u8         f_eth_prio[0x1];
 576         u8         ecn[0x2];
 577         u8         dscp[0x6];
 578         u8         udp_sport[0x10];
 579
 580         u8         dei_cfi[0x1];
 581         u8         eth_prio[0x3];
 582         u8         sl[0x4];
 583         u8         vhca_port_num[0x8];
 584         u8         rmac_47_32[0x10];
 585
 586         u8         rmac_31_0[0x20];
 587 };
 588
 589 struct mlx5_ifc_flow_table_nic_cap_bits {
 590         u8         nic_rx_multi_path_tirs[0x1];
 591         u8         nic_rx_multi_path_tirs_fts[0x1];
 592         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 593         u8         reserved_at_3[0x1d];
 594         u8         encap_general_header[0x1];
 595         u8         reserved_at_21[0xa];
 596         u8         log_max_packet_reformat_context[0x5];
 597         u8         reserved_at_30[0x6];
 598         u8         max_encap_header_size[0xa];
 599         u8         reserved_at_40[0x1c0];
 600
 601         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 602
 603         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 604
 605         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 606
 607         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 608
 609         u8         reserved_at_a00[0x200];
 610
 611         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 612
 613         u8         reserved_at_e00[0x7200];
 614 };
 615
 616 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 617         u8      reserved_at_0[0x1a];
 618         u8      multi_fdb_encap[0x1];
 619         u8      reserved_at_1b[0x1];
 620         u8      fdb_multi_path_to_table[0x1];
 621         u8      reserved_at_1d[0x3];
 622
 623         u8      reserved_at_20[0x1e0];
 624
 625         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 626
 627         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 628
 629         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 630
 631         u8      reserved_at_800[0x7800];
 632 };
 633
 634 enum {
 635         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 636         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 637 };
 638
 639 struct mlx5_ifc_e_switch_cap_bits {
 640         u8         vport_svlan_strip[0x1];
 641         u8         vport_cvlan_strip[0x1];
 642         u8         vport_svlan_insert[0x1];
 643         u8         vport_cvlan_insert_if_not_exist[0x1];
 644         u8         vport_cvlan_insert_overwrite[0x1];
 645         u8         reserved_at_5[0x16];
 646         u8         ecpf_vport_exists[0x1];
 647         u8         counter_eswitch_affinity[0x1];
 648         u8         merged_eswitch[0x1];
 649         u8         nic_vport_node_guid_modify[0x1];
 650         u8         nic_vport_port_guid_modify[0x1];
 651
 652         u8         vxlan_encap_decap[0x1];
 653         u8         nvgre_encap_decap[0x1];
 654         u8         reserved_at_22[0x1];
 655         u8         log_max_fdb_encap_uplink[0x5];
 656         u8         reserved_at_21[0x3];
 657         u8         log_max_packet_reformat_context[0x5];
 658         u8         reserved_2b[0x6];
 659         u8         max_encap_header_size[0xa];
 660
 661         u8         reserved_40[0x7c0];
 662
 663 };
 664
 665 struct mlx5_ifc_qos_cap_bits {
 666         u8         packet_pacing[0x1];
 667         u8         esw_scheduling[0x1];
 668         u8         esw_bw_share[0x1];
 669         u8         esw_rate_limit[0x1];
 670         u8         reserved_at_4[0x1];
 671         u8         packet_pacing_burst_bound[0x1];
 672         u8         packet_pacing_typical_size[0x1];
 673         u8         reserved_at_7[0x19];
 674
 675         u8         reserved_at_20[0x20];
 676
 677         u8         packet_pacing_max_rate[0x20];
 678
 679         u8         packet_pacing_min_rate[0x20];
 680
 681         u8         reserved_at_80[0x10];
 682         u8         packet_pacing_rate_table_size[0x10];
 683
 684         u8         esw_element_type[0x10];
 685         u8         esw_tsar_type[0x10];
 686
 687         u8         reserved_at_c0[0x10];
 688         u8         max_qos_para_vport[0x10];
 689
 690         u8         max_tsar_bw_share[0x20];
 691
 692         u8         reserved_at_100[0x700];
 693 };
 694
 695 struct mlx5_ifc_debug_cap_bits {
 696         u8         reserved_at_0[0x20];
 697
 698         u8         reserved_at_20[0x2];
 699         u8         stall_detect[0x1];
 700         u8         reserved_at_23[0x1d];
 701
 702         u8         reserved_at_40[0x7c0];
 703 };
 704
 705 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 706         u8         csum_cap[0x1];
 707         u8         vlan_cap[0x1];
 708         u8         lro_cap[0x1];
 709         u8         lro_psh_flag[0x1];
 710         u8         lro_time_stamp[0x1];
 711         u8         reserved_at_5[0x2];
 712         u8         wqe_vlan_insert[0x1];
 713         u8         self_lb_en_modifiable[0x1];
 714         u8         reserved_at_9[0x2];
 715         u8         max_lso_cap[0x5];
 716         u8         multi_pkt_send_wqe[0x2];
 717         u8         wqe_inline_mode[0x2];
 718         u8         rss_ind_tbl_cap[0x4];
 719         u8         reg_umr_sq[0x1];
 720         u8         scatter_fcs[0x1];
 721         u8         enhanced_multi_pkt_send_wqe[0x1];
 722         u8         tunnel_lso_const_out_ip_id[0x1];
 723         u8         reserved_at_1c[0x2];
 724         u8         tunnel_stateless_gre[0x1];
 725         u8         tunnel_stateless_vxlan[0x1];
 726
 727         u8         swp[0x1];
 728         u8         swp_csum[0x1];
 729         u8         swp_lso[0x1];
 730         u8         reserved_at_23[0xd];
 731         u8         max_vxlan_udp_ports[0x8];
 732         u8         reserved_at_38[0x6];
 733         u8         max_geneve_opt_len[0x1];
 734         u8         tunnel_stateless_geneve_rx[0x1];
 735
 736         u8         reserved_at_40[0x10];
 737         u8         lro_min_mss_size[0x10];
 738
 739         u8         reserved_at_60[0x120];
 740
 741         u8         lro_timer_supported_periods[4][0x20];
 742
 743         u8         reserved_at_200[0x600];
 744 };
 745
 746 struct mlx5_ifc_roce_cap_bits {
 747         u8         roce_apm[0x1];
 748         u8         reserved_at_1[0x1f];
 749
 750         u8         reserved_at_20[0x60];
 751
 752         u8         reserved_at_80[0xc];
 753         u8         l3_type[0x4];
 754         u8         reserved_at_90[0x8];
 755         u8         roce_version[0x8];
 756
 757         u8         reserved_at_a0[0x10];
 758         u8         r_roce_dest_udp_port[0x10];
 759
 760         u8         r_roce_max_src_udp_port[0x10];
 761         u8         r_roce_min_src_udp_port[0x10];
 762
 763         u8         reserved_at_e0[0x10];
 764         u8         roce_address_table_size[0x10];
 765
 766         u8         reserved_at_100[0x700];
 767 };
 768
 769 struct mlx5_ifc_device_mem_cap_bits {
 770         u8         memic[0x1];
 771         u8         reserved_at_1[0x1f];
 772
 773         u8         reserved_at_20[0xb];
 774         u8         log_min_memic_alloc_size[0x5];
 775         u8         reserved_at_30[0x8];
 776         u8         log_max_memic_addr_alignment[0x8];
 777
 778         u8         memic_bar_start_addr[0x40];
 779
 780         u8         memic_bar_size[0x20];
 781
 782         u8         max_memic_size[0x20];
 783
 784         u8         steering_sw_icm_start_address[0x40];
 785
 786         u8         reserved_at_100[0x8];
 787         u8         log_header_modify_sw_icm_size[0x8];
 788         u8         reserved_at_110[0x2];
 789         u8         log_sw_icm_alloc_granularity[0x6];
 790         u8         log_steering_sw_icm_size[0x8];
 791
 792         u8         reserved_at_120[0x20];
 793
 794         u8         header_modify_sw_icm_start_address[0x40];
 795
 796         u8         reserved_at_180[0x680];
 797 };
 798
 799 enum {
 800         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 801         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 802         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 803         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 804         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 805         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 806         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 807         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 808         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 809 };
 810
 811 enum {
 812         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 813         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 814         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 815         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 816         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 817         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 818         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 819         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 820         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 821 };
 822
 823 struct mlx5_ifc_atomic_caps_bits {
 824         u8         reserved_at_0[0x40];
 825
 826         u8         atomic_req_8B_endianness_mode[0x2];
 827         u8         reserved_at_42[0x4];
 828         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 829
 830         u8         reserved_at_47[0x19];
 831
 832         u8         reserved_at_60[0x20];
 833
 834         u8         reserved_at_80[0x10];
 835         u8         atomic_operations[0x10];
 836
 837         u8         reserved_at_a0[0x10];
 838         u8         atomic_size_qp[0x10];
 839
 840         u8         reserved_at_c0[0x10];
 841         u8         atomic_size_dc[0x10];
 842
 843         u8         reserved_at_e0[0x720];
 844 };
 845
 846 struct mlx5_ifc_odp_cap_bits {
 847         u8         reserved_at_0[0x40];
 848
 849         u8         sig[0x1];
 850         u8         reserved_at_41[0x1f];
 851
 852         u8         reserved_at_60[0x20];
 853
 854         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 855
 856         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 857
 858         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 859
 860         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
 861
 862         u8         reserved_at_100[0x700];
 863 };
 864
 865 struct mlx5_ifc_calc_op {
 866         u8        reserved_at_0[0x10];
 867         u8        reserved_at_10[0x9];
 868         u8        op_swap_endianness[0x1];
 869         u8        op_min[0x1];
 870         u8        op_xor[0x1];
 871         u8        op_or[0x1];
 872         u8        op_and[0x1];
 873         u8        op_max[0x1];
 874         u8        op_add[0x1];
 875 };
 876
 877 struct mlx5_ifc_vector_calc_cap_bits {
 878         u8         calc_matrix[0x1];
 879         u8         reserved_at_1[0x1f];
 880         u8         reserved_at_20[0x8];
 881         u8         max_vec_count[0x8];
 882         u8         reserved_at_30[0xd];
 883         u8         max_chunk_size[0x3];
 884         struct mlx5_ifc_calc_op calc0;
 885         struct mlx5_ifc_calc_op calc1;
 886         struct mlx5_ifc_calc_op calc2;
 887         struct mlx5_ifc_calc_op calc3;
 888
 889         u8         reserved_at_c0[0x720];
 890 };
 891
 892 enum {
 893         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 894         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 895         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 896         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 897 };
 898
 899 enum {
 900         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 901         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 902 };
 903
 904 enum {
 905         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 906         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 907         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 908         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 909         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 910 };
 911
 912 enum {
 913         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 914         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 915         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 916         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 917         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 918         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 919 };
 920
 921 enum {
 922         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 923         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 924 };
 925
 926 enum {
 927         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 928         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 929         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 930 };
 931
 932 enum {
 933         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 934         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 935 };
 936
 937 enum {
 938         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 939         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 940         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 941 };
 942
 943 enum {
 944         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
 945         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
 946 };
 947
 948 struct mlx5_ifc_cmd_hca_cap_bits {
 949         u8         reserved_at_0[0x30];
 950         u8         vhca_id[0x10];
 951
 952         u8         reserved_at_40[0x40];
 953
 954         u8         log_max_srq_sz[0x8];
 955         u8         log_max_qp_sz[0x8];
 956         u8         reserved_at_90[0x8];
 957         u8         prio_tag_required[0x1];
 958         u8         reserved_at_99[0x2];
 959         u8         log_max_qp[0x5];
 960
 961         u8         reserved_at_a0[0xb];
 962         u8         log_max_srq[0x5];
 963         u8         reserved_at_b0[0x10];
 964
 965         u8         reserved_at_c0[0x8];
 966         u8         log_max_cq_sz[0x8];
 967         u8         reserved_at_d0[0xb];
 968         u8         log_max_cq[0x5];
 969
 970         u8         log_max_eq_sz[0x8];
 971         u8         reserved_at_e8[0x2];
 972         u8         log_max_mkey[0x6];
 973         u8         reserved_at_f0[0x8];
 974         u8         dump_fill_mkey[0x1];
 975         u8         reserved_at_f9[0x2];
 976         u8         fast_teardown[0x1];
 977         u8         log_max_eq[0x4];
 978
 979         u8         max_indirection[0x8];
 980         u8         fixed_buffer_size[0x1];
 981         u8         log_max_mrw_sz[0x7];
 982         u8         force_teardown[0x1];
 983         u8         reserved_at_111[0x1];
 984         u8         log_max_bsf_list_size[0x6];
 985         u8         umr_extended_translation_offset[0x1];
 986         u8         null_mkey[0x1];
 987         u8         log_max_klm_list_size[0x6];
 988
 989         u8         reserved_at_120[0xa];
 990         u8         log_max_ra_req_dc[0x6];
 991         u8         reserved_at_130[0xa];
 992         u8         log_max_ra_res_dc[0x6];
 993
 994         u8         reserved_at_140[0xa];
 995         u8         log_max_ra_req_qp[0x6];
 996         u8         reserved_at_150[0xa];
 997         u8         log_max_ra_res_qp[0x6];
 998
 999         u8         end_pad[0x1];
1000         u8         cc_query_allowed[0x1];
1001         u8         cc_modify_allowed[0x1];
1002         u8         start_pad[0x1];
1003         u8         cache_line_128byte[0x1];
1004         u8         reserved_at_165[0xa];
1005         u8         qcam_reg[0x1];
1006         u8         gid_table_size[0x10];
1007
1008         u8         out_of_seq_cnt[0x1];
1009         u8         vport_counters[0x1];
1010         u8         retransmission_q_counters[0x1];
1011         u8         debug[0x1];
1012         u8         modify_rq_counter_set_id[0x1];
1013         u8         rq_delay_drop[0x1];
1014         u8         max_qp_cnt[0xa];
1015         u8         pkey_table_size[0x10];
1016
1017         u8         vport_group_manager[0x1];
1018         u8         vhca_group_manager[0x1];
1019         u8         ib_virt[0x1];
1020         u8         eth_virt[0x1];
1021         u8         vnic_env_queue_counters[0x1];
1022         u8         ets[0x1];
1023         u8         nic_flow_table[0x1];
1024         u8         eswitch_manager[0x1];
1025         u8         device_memory[0x1];
1026         u8         mcam_reg[0x1];
1027         u8         pcam_reg[0x1];
1028         u8         local_ca_ack_delay[0x5];
1029         u8         port_module_event[0x1];
1030         u8         enhanced_error_q_counters[0x1];
1031         u8         ports_check[0x1];
1032         u8         reserved_at_1b3[0x1];
1033         u8         disable_link_up[0x1];
1034         u8         beacon_led[0x1];
1035         u8         port_type[0x2];
1036         u8         num_ports[0x8];
1037
1038         u8         reserved_at_1c0[0x1];
1039         u8         pps[0x1];
1040         u8         pps_modify[0x1];
1041         u8         log_max_msg[0x5];
1042         u8         reserved_at_1c8[0x4];
1043         u8         max_tc[0x4];
1044         u8         temp_warn_event[0x1];
1045         u8         dcbx[0x1];
1046         u8         general_notification_event[0x1];
1047         u8         reserved_at_1d3[0x2];
1048         u8         fpga[0x1];
1049         u8         rol_s[0x1];
1050         u8         rol_g[0x1];
1051         u8         reserved_at_1d8[0x1];
1052         u8         wol_s[0x1];
1053         u8         wol_g[0x1];
1054         u8         wol_a[0x1];
1055         u8         wol_b[0x1];
1056         u8         wol_m[0x1];
1057         u8         wol_u[0x1];
1058         u8         wol_p[0x1];
1059
1060         u8         stat_rate_support[0x10];
1061         u8         reserved_at_1f0[0xc];
1062         u8         cqe_version[0x4];
1063
1064         u8         compact_address_vector[0x1];
1065         u8         striding_rq[0x1];
1066         u8         reserved_at_202[0x1];
1067         u8         ipoib_enhanced_offloads[0x1];
1068         u8         ipoib_basic_offloads[0x1];
1069         u8         reserved_at_205[0x1];
1070         u8         repeated_block_disabled[0x1];
1071         u8         umr_modify_entity_size_disabled[0x1];
1072         u8         umr_modify_atomic_disabled[0x1];
1073         u8         umr_indirect_mkey_disabled[0x1];
1074         u8         umr_fence[0x2];
1075         u8         dc_req_scat_data_cqe[0x1];
1076         u8         reserved_at_20d[0x2];
1077         u8         drain_sigerr[0x1];
1078         u8         cmdif_checksum[0x2];
1079         u8         sigerr_cqe[0x1];
1080         u8         reserved_at_213[0x1];
1081         u8         wq_signature[0x1];
1082         u8         sctr_data_cqe[0x1];
1083         u8         reserved_at_216[0x1];
1084         u8         sho[0x1];
1085         u8         tph[0x1];
1086         u8         rf[0x1];
1087         u8         dct[0x1];
1088         u8         qos[0x1];
1089         u8         eth_net_offloads[0x1];
1090         u8         roce[0x1];
1091         u8         atomic[0x1];
1092         u8         reserved_at_21f[0x1];
1093
1094         u8         cq_oi[0x1];
1095         u8         cq_resize[0x1];
1096         u8         cq_moderation[0x1];
1097         u8         reserved_at_223[0x3];
1098         u8         cq_eq_remap[0x1];
1099         u8         pg[0x1];
1100         u8         block_lb_mc[0x1];
1101         u8         reserved_at_229[0x1];
1102         u8         scqe_break_moderation[0x1];
1103         u8         cq_period_start_from_cqe[0x1];
1104         u8         cd[0x1];
1105         u8         reserved_at_22d[0x1];
1106         u8         apm[0x1];
1107         u8         vector_calc[0x1];
1108         u8         umr_ptr_rlky[0x1];
1109         u8         imaicl[0x1];
1110         u8         qp_packet_based[0x1];
1111         u8         reserved_at_233[0x3];
1112         u8         qkv[0x1];
1113         u8         pkv[0x1];
1114         u8         set_deth_sqpn[0x1];
1115         u8         reserved_at_239[0x3];
1116         u8         xrc[0x1];
1117         u8         ud[0x1];
1118         u8         uc[0x1];
1119         u8         rc[0x1];
1120
1121         u8         uar_4k[0x1];
1122         u8         reserved_at_241[0x9];
1123         u8         uar_sz[0x6];
1124         u8         reserved_at_250[0x8];
1125         u8         log_pg_sz[0x8];
1126
1127         u8         bf[0x1];
1128         u8         driver_version[0x1];
1129         u8         pad_tx_eth_packet[0x1];
1130         u8         reserved_at_263[0x8];
1131         u8         log_bf_reg_size[0x5];
1132
1133         u8         reserved_at_270[0xb];
1134         u8         lag_master[0x1];
1135         u8         num_lag_ports[0x4];
1136
1137         u8         reserved_at_280[0x10];
1138         u8         max_wqe_sz_sq[0x10];
1139
1140         u8         reserved_at_2a0[0x10];
1141         u8         max_wqe_sz_rq[0x10];
1142
1143         u8         max_flow_counter_31_16[0x10];
1144         u8         max_wqe_sz_sq_dc[0x10];
1145
1146         u8         reserved_at_2e0[0x7];
1147         u8         max_qp_mcg[0x19];
1148
1149         u8         reserved_at_300[0x18];
1150         u8         log_max_mcg[0x8];
1151
1152         u8         reserved_at_320[0x3];
1153         u8         log_max_transport_domain[0x5];
1154         u8         reserved_at_328[0x3];
1155         u8         log_max_pd[0x5];
1156         u8         reserved_at_330[0xb];
1157         u8         log_max_xrcd[0x5];
1158
1159         u8         nic_receive_steering_discard[0x1];
1160         u8         receive_discard_vport_down[0x1];
1161         u8         transmit_discard_vport_down[0x1];
1162         u8         reserved_at_343[0x5];
1163         u8         log_max_flow_counter_bulk[0x8];
1164         u8         max_flow_counter_15_0[0x10];
1165
1166
1167         u8         reserved_at_360[0x3];
1168         u8         log_max_rq[0x5];
1169         u8         reserved_at_368[0x3];
1170         u8         log_max_sq[0x5];
1171         u8         reserved_at_370[0x3];
1172         u8         log_max_tir[0x5];
1173         u8         reserved_at_378[0x3];
1174         u8         log_max_tis[0x5];
1175
1176         u8         basic_cyclic_rcv_wqe[0x1];
1177         u8         reserved_at_381[0x2];
1178         u8         log_max_rmp[0x5];
1179         u8         reserved_at_388[0x3];
1180         u8         log_max_rqt[0x5];
1181         u8         reserved_at_390[0x3];
1182         u8         log_max_rqt_size[0x5];
1183         u8         reserved_at_398[0x3];
1184         u8         log_max_tis_per_sq[0x5];
1185
1186         u8         ext_stride_num_range[0x1];
1187         u8         reserved_at_3a1[0x2];
1188         u8         log_max_stride_sz_rq[0x5];
1189         u8         reserved_at_3a8[0x3];
1190         u8         log_min_stride_sz_rq[0x5];
1191         u8         reserved_at_3b0[0x3];
1192         u8         log_max_stride_sz_sq[0x5];
1193         u8         reserved_at_3b8[0x3];
1194         u8         log_min_stride_sz_sq[0x5];
1195
1196         u8         hairpin[0x1];
1197         u8         reserved_at_3c1[0x2];
1198         u8         log_max_hairpin_queues[0x5];
1199         u8         reserved_at_3c8[0x3];
1200         u8         log_max_hairpin_wq_data_sz[0x5];
1201         u8         reserved_at_3d0[0x3];
1202         u8         log_max_hairpin_num_packets[0x5];
1203         u8         reserved_at_3d8[0x3];
1204         u8         log_max_wq_sz[0x5];
1205
1206         u8         nic_vport_change_event[0x1];
1207         u8         disable_local_lb_uc[0x1];
1208         u8         disable_local_lb_mc[0x1];
1209         u8         log_min_hairpin_wq_data_sz[0x5];
1210         u8         reserved_at_3e8[0x3];
1211         u8         log_max_vlan_list[0x5];
1212         u8         reserved_at_3f0[0x3];
1213         u8         log_max_current_mc_list[0x5];
1214         u8         reserved_at_3f8[0x3];
1215         u8         log_max_current_uc_list[0x5];
1216
1217         u8         general_obj_types[0x40];
1218
1219         u8         reserved_at_440[0x20];
1220
1221         u8         reserved_at_460[0x3];
1222         u8         log_max_uctx[0x5];
1223         u8         reserved_at_468[0x3];
1224         u8         log_max_umem[0x5];
1225         u8         max_num_eqs[0x10];
1226
1227         u8         reserved_at_480[0x3];
1228         u8         log_max_l2_table[0x5];
1229         u8         reserved_at_488[0x8];
1230         u8         log_uar_page_sz[0x10];
1231
1232         u8         reserved_at_4a0[0x20];
1233         u8         device_frequency_mhz[0x20];
1234         u8         device_frequency_khz[0x20];
1235
1236         u8         reserved_at_500[0x20];
1237         u8         num_of_uars_per_page[0x20];
1238
1239         u8         flex_parser_protocols[0x20];
1240         u8         reserved_at_560[0x20];
1241
1242         u8         reserved_at_580[0x3c];
1243         u8         mini_cqe_resp_stride_index[0x1];
1244         u8         cqe_128_always[0x1];
1245         u8         cqe_compression_128[0x1];
1246         u8         cqe_compression[0x1];
1247
1248         u8         cqe_compression_timeout[0x10];
1249         u8         cqe_compression_max_num[0x10];
1250
1251         u8         reserved_at_5e0[0x10];
1252         u8         tag_matching[0x1];
1253         u8         rndv_offload_rc[0x1];
1254         u8         rndv_offload_dc[0x1];
1255         u8         log_tag_matching_list_sz[0x5];
1256         u8         reserved_at_5f8[0x3];
1257         u8         log_max_xrq[0x5];
1258
1259         u8         affiliate_nic_vport_criteria[0x8];
1260         u8         native_port_num[0x8];
1261         u8         num_vhca_ports[0x8];
1262         u8         reserved_at_618[0x6];
1263         u8         sw_owner_id[0x1];
1264         u8         reserved_at_61f[0x1];
1265
1266         u8         max_num_of_monitor_counters[0x10];
1267         u8         num_ppcnt_monitor_counters[0x10];
1268
1269         u8         reserved_at_640[0x10];
1270         u8         num_q_monitor_counters[0x10];
1271
1272         u8         reserved_at_660[0x40];
1273
1274         u8         uctx_cap[0x20];
1275
1276         u8         reserved_at_6c0[0x140];
1277 };
1278
1279 enum mlx5_flow_destination_type {
1280         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1281         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1282         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1283
1284         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1285         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1286         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1287 };
1288
1289 enum mlx5_flow_table_miss_action {
1290         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1291         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1292         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1293 };
1294
1295 struct mlx5_ifc_dest_format_struct_bits {
1296         u8         destination_type[0x8];
1297         u8         destination_id[0x18];
1298
1299         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1300         u8         packet_reformat[0x1];
1301         u8         reserved_at_22[0xe];
1302         u8         destination_eswitch_owner_vhca_id[0x10];
1303 };
1304
1305 struct mlx5_ifc_flow_counter_list_bits {
1306         u8         flow_counter_id[0x20];
1307
1308         u8         reserved_at_20[0x20];
1309 };
1310
1311 struct mlx5_ifc_extended_dest_format_bits {
1312         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1313
1314         u8         packet_reformat_id[0x20];
1315
1316         u8         reserved_at_60[0x20];
1317 };
1318
1319 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1320         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1321         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1322         u8         reserved_at_0[0x40];
1323 };
1324
1325 struct mlx5_ifc_fte_match_param_bits {
1326         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1327
1328         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1329
1330         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1331
1332         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1333
1334         u8         reserved_at_800[0x800];
1335 };
1336
1337 enum {
1338         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1339         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1340         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1341         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1342         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1343 };
1344
1345 struct mlx5_ifc_rx_hash_field_select_bits {
1346         u8         l3_prot_type[0x1];
1347         u8         l4_prot_type[0x1];
1348         u8         selected_fields[0x1e];
1349 };
1350
1351 enum {
1352         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1353         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1354 };
1355
1356 enum {
1357         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1358         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1359 };
1360
1361 struct mlx5_ifc_wq_bits {
1362         u8         wq_type[0x4];
1363         u8         wq_signature[0x1];
1364         u8         end_padding_mode[0x2];
1365         u8         cd_slave[0x1];
1366         u8         reserved_at_8[0x18];
1367
1368         u8         hds_skip_first_sge[0x1];
1369         u8         log2_hds_buf_size[0x3];
1370         u8         reserved_at_24[0x7];
1371         u8         page_offset[0x5];
1372         u8         lwm[0x10];
1373
1374         u8         reserved_at_40[0x8];
1375         u8         pd[0x18];
1376
1377         u8         reserved_at_60[0x8];
1378         u8         uar_page[0x18];
1379
1380         u8         dbr_addr[0x40];
1381
1382         u8         hw_counter[0x20];
1383
1384         u8         sw_counter[0x20];
1385
1386         u8         reserved_at_100[0xc];
1387         u8         log_wq_stride[0x4];
1388         u8         reserved_at_110[0x3];
1389         u8         log_wq_pg_sz[0x5];
1390         u8         reserved_at_118[0x3];
1391         u8         log_wq_sz[0x5];
1392
1393         u8         dbr_umem_valid[0x1];
1394         u8         wq_umem_valid[0x1];
1395         u8         reserved_at_122[0x1];
1396         u8         log_hairpin_num_packets[0x5];
1397         u8         reserved_at_128[0x3];
1398         u8         log_hairpin_data_sz[0x5];
1399
1400         u8         reserved_at_130[0x4];
1401         u8         log_wqe_num_of_strides[0x4];
1402         u8         two_byte_shift_en[0x1];
1403         u8         reserved_at_139[0x4];
1404         u8         log_wqe_stride_size[0x3];
1405
1406         u8         reserved_at_140[0x4c0];
1407
1408         struct mlx5_ifc_cmd_pas_bits pas[0];
1409 };
1410
1411 struct mlx5_ifc_rq_num_bits {
1412         u8         reserved_at_0[0x8];
1413         u8         rq_num[0x18];
1414 };
1415
1416 struct mlx5_ifc_mac_address_layout_bits {
1417         u8         reserved_at_0[0x10];
1418         u8         mac_addr_47_32[0x10];
1419
1420         u8         mac_addr_31_0[0x20];
1421 };
1422
1423 struct mlx5_ifc_vlan_layout_bits {
1424         u8         reserved_at_0[0x14];
1425         u8         vlan[0x0c];
1426
1427         u8         reserved_at_20[0x20];
1428 };
1429
1430 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1431         u8         reserved_at_0[0xa0];
1432
1433         u8         min_time_between_cnps[0x20];
1434
1435         u8         reserved_at_c0[0x12];
1436         u8         cnp_dscp[0x6];
1437         u8         reserved_at_d8[0x4];
1438         u8         cnp_prio_mode[0x1];
1439         u8         cnp_802p_prio[0x3];
1440
1441         u8         reserved_at_e0[0x720];
1442 };
1443
1444 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1445         u8         reserved_at_0[0x60];
1446
1447         u8         reserved_at_60[0x4];
1448         u8         clamp_tgt_rate[0x1];
1449         u8         reserved_at_65[0x3];
1450         u8         clamp_tgt_rate_after_time_inc[0x1];
1451         u8         reserved_at_69[0x17];
1452
1453         u8         reserved_at_80[0x20];
1454
1455         u8         rpg_time_reset[0x20];
1456
1457         u8         rpg_byte_reset[0x20];
1458
1459         u8         rpg_threshold[0x20];
1460
1461         u8         rpg_max_rate[0x20];
1462
1463         u8         rpg_ai_rate[0x20];
1464
1465         u8         rpg_hai_rate[0x20];
1466
1467         u8         rpg_gd[0x20];
1468
1469         u8         rpg_min_dec_fac[0x20];
1470
1471         u8         rpg_min_rate[0x20];
1472
1473         u8         reserved_at_1c0[0xe0];
1474
1475         u8         rate_to_set_on_first_cnp[0x20];
1476
1477         u8         dce_tcp_g[0x20];
1478
1479         u8         dce_tcp_rtt[0x20];
1480
1481         u8         rate_reduce_monitor_period[0x20];
1482
1483         u8         reserved_at_320[0x20];
1484
1485         u8         initial_alpha_value[0x20];
1486
1487         u8         reserved_at_360[0x4a0];
1488 };
1489
1490 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1491         u8         reserved_at_0[0x80];
1492
1493         u8         rppp_max_rps[0x20];
1494
1495         u8         rpg_time_reset[0x20];
1496
1497         u8         rpg_byte_reset[0x20];
1498
1499         u8         rpg_threshold[0x20];
1500
1501         u8         rpg_max_rate[0x20];
1502
1503         u8         rpg_ai_rate[0x20];
1504
1505         u8         rpg_hai_rate[0x20];
1506
1507         u8         rpg_gd[0x20];
1508
1509         u8         rpg_min_dec_fac[0x20];
1510
1511         u8         rpg_min_rate[0x20];
1512
1513         u8         reserved_at_1c0[0x640];
1514 };
1515
1516 enum {
1517         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1518         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1519         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1520 };
1521
1522 struct mlx5_ifc_resize_field_select_bits {
1523         u8         resize_field_select[0x20];
1524 };
1525
1526 enum {
1527         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1528         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1529         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1530         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1531 };
1532
1533 struct mlx5_ifc_modify_field_select_bits {
1534         u8         modify_field_select[0x20];
1535 };
1536
1537 struct mlx5_ifc_field_select_r_roce_np_bits {
1538         u8         field_select_r_roce_np[0x20];
1539 };
1540
1541 struct mlx5_ifc_field_select_r_roce_rp_bits {
1542         u8         field_select_r_roce_rp[0x20];
1543 };
1544
1545 enum {
1546         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1547         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1548         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1549         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1550         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1551         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1552         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1553         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1554         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1555         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1556 };
1557
1558 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1559         u8         field_select_8021qaurp[0x20];
1560 };
1561
1562 struct mlx5_ifc_phys_layer_cntrs_bits {
1563         u8         time_since_last_clear_high[0x20];
1564
1565         u8         time_since_last_clear_low[0x20];
1566
1567         u8         symbol_errors_high[0x20];
1568
1569         u8         symbol_errors_low[0x20];
1570
1571         u8         sync_headers_errors_high[0x20];
1572
1573         u8         sync_headers_errors_low[0x20];
1574
1575         u8         edpl_bip_errors_lane0_high[0x20];
1576
1577         u8         edpl_bip_errors_lane0_low[0x20];
1578
1579         u8         edpl_bip_errors_lane1_high[0x20];
1580
1581         u8         edpl_bip_errors_lane1_low[0x20];
1582
1583         u8         edpl_bip_errors_lane2_high[0x20];
1584
1585         u8         edpl_bip_errors_lane2_low[0x20];
1586
1587         u8         edpl_bip_errors_lane3_high[0x20];
1588
1589         u8         edpl_bip_errors_lane3_low[0x20];
1590
1591         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1592
1593         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1594
1595         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1596
1597         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1598
1599         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1600
1601         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1602
1603         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1604
1605         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1606
1607         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1608
1609         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1610
1611         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1612
1613         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1614
1615         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1616
1617         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1618
1619         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1620
1621         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1622
1623         u8         rs_fec_corrected_blocks_high[0x20];
1624
1625         u8         rs_fec_corrected_blocks_low[0x20];
1626
1627         u8         rs_fec_uncorrectable_blocks_high[0x20];
1628
1629         u8         rs_fec_uncorrectable_blocks_low[0x20];
1630
1631         u8         rs_fec_no_errors_blocks_high[0x20];
1632
1633         u8         rs_fec_no_errors_blocks_low[0x20];
1634
1635         u8         rs_fec_single_error_blocks_high[0x20];
1636
1637         u8         rs_fec_single_error_blocks_low[0x20];
1638
1639         u8         rs_fec_corrected_symbols_total_high[0x20];
1640
1641         u8         rs_fec_corrected_symbols_total_low[0x20];
1642
1643         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1644
1645         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1646
1647         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1648
1649         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1650
1651         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1652
1653         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1654
1655         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1656
1657         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1658
1659         u8         link_down_events[0x20];
1660
1661         u8         successful_recovery_events[0x20];
1662
1663         u8         reserved_at_640[0x180];
1664 };
1665
1666 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1667         u8         time_since_last_clear_high[0x20];
1668
1669         u8         time_since_last_clear_low[0x20];
1670
1671         u8         phy_received_bits_high[0x20];
1672
1673         u8         phy_received_bits_low[0x20];
1674
1675         u8         phy_symbol_errors_high[0x20];
1676
1677         u8         phy_symbol_errors_low[0x20];
1678
1679         u8         phy_corrected_bits_high[0x20];
1680
1681         u8         phy_corrected_bits_low[0x20];
1682
1683         u8         phy_corrected_bits_lane0_high[0x20];
1684
1685         u8         phy_corrected_bits_lane0_low[0x20];
1686
1687         u8         phy_corrected_bits_lane1_high[0x20];
1688
1689         u8         phy_corrected_bits_lane1_low[0x20];
1690
1691         u8         phy_corrected_bits_lane2_high[0x20];
1692
1693         u8         phy_corrected_bits_lane2_low[0x20];
1694
1695         u8         phy_corrected_bits_lane3_high[0x20];
1696
1697         u8         phy_corrected_bits_lane3_low[0x20];
1698
1699         u8         reserved_at_200[0x5c0];
1700 };
1701
1702 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1703         u8         symbol_error_counter[0x10];
1704
1705         u8         link_error_recovery_counter[0x8];
1706
1707         u8         link_downed_counter[0x8];
1708
1709         u8         port_rcv_errors[0x10];
1710
1711         u8         port_rcv_remote_physical_errors[0x10];
1712
1713         u8         port_rcv_switch_relay_errors[0x10];
1714
1715         u8         port_xmit_discards[0x10];
1716
1717         u8         port_xmit_constraint_errors[0x8];
1718
1719         u8         port_rcv_constraint_errors[0x8];
1720
1721         u8         reserved_at_70[0x8];
1722
1723         u8         link_overrun_errors[0x8];
1724
1725         u8         reserved_at_80[0x10];
1726
1727         u8         vl_15_dropped[0x10];
1728
1729         u8         reserved_at_a0[0x80];
1730
1731         u8         port_xmit_wait[0x20];
1732 };
1733
1734 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1735         u8         transmit_queue_high[0x20];
1736
1737         u8         transmit_queue_low[0x20];
1738
1739         u8         reserved_at_40[0x780];
1740 };
1741
1742 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1743         u8         rx_octets_high[0x20];
1744
1745         u8         rx_octets_low[0x20];
1746
1747         u8         reserved_at_40[0xc0];
1748
1749         u8         rx_frames_high[0x20];
1750
1751         u8         rx_frames_low[0x20];
1752
1753         u8         tx_octets_high[0x20];
1754
1755         u8         tx_octets_low[0x20];
1756
1757         u8         reserved_at_180[0xc0];
1758
1759         u8         tx_frames_high[0x20];
1760
1761         u8         tx_frames_low[0x20];
1762
1763         u8         rx_pause_high[0x20];
1764
1765         u8         rx_pause_low[0x20];
1766
1767         u8         rx_pause_duration_high[0x20];
1768
1769         u8         rx_pause_duration_low[0x20];
1770
1771         u8         tx_pause_high[0x20];
1772
1773         u8         tx_pause_low[0x20];
1774
1775         u8         tx_pause_duration_high[0x20];
1776
1777         u8         tx_pause_duration_low[0x20];
1778
1779         u8         rx_pause_transition_high[0x20];
1780
1781         u8         rx_pause_transition_low[0x20];
1782
1783         u8         reserved_at_3c0[0x40];
1784
1785         u8         device_stall_minor_watermark_cnt_high[0x20];
1786
1787         u8         device_stall_minor_watermark_cnt_low[0x20];
1788
1789         u8         device_stall_critical_watermark_cnt_high[0x20];
1790
1791         u8         device_stall_critical_watermark_cnt_low[0x20];
1792
1793         u8         reserved_at_480[0x340];
1794 };
1795
1796 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1797         u8         port_transmit_wait_high[0x20];
1798
1799         u8         port_transmit_wait_low[0x20];
1800
1801         u8         reserved_at_40[0x100];
1802
1803         u8         rx_buffer_almost_full_high[0x20];
1804
1805         u8         rx_buffer_almost_full_low[0x20];
1806
1807         u8         rx_buffer_full_high[0x20];
1808
1809         u8         rx_buffer_full_low[0x20];
1810
1811         u8         rx_icrc_encapsulated_high[0x20];
1812
1813         u8         rx_icrc_encapsulated_low[0x20];
1814
1815         u8         reserved_at_200[0x5c0];
1816 };
1817
1818 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1819         u8         dot3stats_alignment_errors_high[0x20];
1820
1821         u8         dot3stats_alignment_errors_low[0x20];
1822
1823         u8         dot3stats_fcs_errors_high[0x20];
1824
1825         u8         dot3stats_fcs_errors_low[0x20];
1826
1827         u8         dot3stats_single_collision_frames_high[0x20];
1828
1829         u8         dot3stats_single_collision_frames_low[0x20];
1830
1831         u8         dot3stats_multiple_collision_frames_high[0x20];
1832
1833         u8         dot3stats_multiple_collision_frames_low[0x20];
1834
1835         u8         dot3stats_sqe_test_errors_high[0x20];
1836
1837         u8         dot3stats_sqe_test_errors_low[0x20];
1838
1839         u8         dot3stats_deferred_transmissions_high[0x20];
1840
1841         u8         dot3stats_deferred_transmissions_low[0x20];
1842
1843         u8         dot3stats_late_collisions_high[0x20];
1844
1845         u8         dot3stats_late_collisions_low[0x20];
1846
1847         u8         dot3stats_excessive_collisions_high[0x20];
1848
1849         u8         dot3stats_excessive_collisions_low[0x20];
1850
1851         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1852
1853         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1854
1855         u8         dot3stats_carrier_sense_errors_high[0x20];
1856
1857         u8         dot3stats_carrier_sense_errors_low[0x20];
1858
1859         u8         dot3stats_frame_too_longs_high[0x20];
1860
1861         u8         dot3stats_frame_too_longs_low[0x20];
1862
1863         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1864
1865         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1866
1867         u8         dot3stats_symbol_errors_high[0x20];
1868
1869         u8         dot3stats_symbol_errors_low[0x20];
1870
1871         u8         dot3control_in_unknown_opcodes_high[0x20];
1872
1873         u8         dot3control_in_unknown_opcodes_low[0x20];
1874
1875         u8         dot3in_pause_frames_high[0x20];
1876
1877         u8         dot3in_pause_frames_low[0x20];
1878
1879         u8         dot3out_pause_frames_high[0x20];
1880
1881         u8         dot3out_pause_frames_low[0x20];
1882
1883         u8         reserved_at_400[0x3c0];
1884 };
1885
1886 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1887         u8         ether_stats_drop_events_high[0x20];
1888
1889         u8         ether_stats_drop_events_low[0x20];
1890
1891         u8         ether_stats_octets_high[0x20];
1892
1893         u8         ether_stats_octets_low[0x20];
1894
1895         u8         ether_stats_pkts_high[0x20];
1896
1897         u8         ether_stats_pkts_low[0x20];
1898
1899         u8         ether_stats_broadcast_pkts_high[0x20];
1900
1901         u8         ether_stats_broadcast_pkts_low[0x20];
1902
1903         u8         ether_stats_multicast_pkts_high[0x20];
1904
1905         u8         ether_stats_multicast_pkts_low[0x20];
1906
1907         u8         ether_stats_crc_align_errors_high[0x20];
1908
1909         u8         ether_stats_crc_align_errors_low[0x20];
1910
1911         u8         ether_stats_undersize_pkts_high[0x20];
1912
1913         u8         ether_stats_undersize_pkts_low[0x20];
1914
1915         u8         ether_stats_oversize_pkts_high[0x20];
1916
1917         u8         ether_stats_oversize_pkts_low[0x20];
1918
1919         u8         ether_stats_fragments_high[0x20];
1920
1921         u8         ether_stats_fragments_low[0x20];
1922
1923         u8         ether_stats_jabbers_high[0x20];
1924
1925         u8         ether_stats_jabbers_low[0x20];
1926
1927         u8         ether_stats_collisions_high[0x20];
1928
1929         u8         ether_stats_collisions_low[0x20];
1930
1931         u8         ether_stats_pkts64octets_high[0x20];
1932
1933         u8         ether_stats_pkts64octets_low[0x20];
1934
1935         u8         ether_stats_pkts65to127octets_high[0x20];
1936
1937         u8         ether_stats_pkts65to127octets_low[0x20];
1938
1939         u8         ether_stats_pkts128to255octets_high[0x20];
1940
1941         u8         ether_stats_pkts128to255octets_low[0x20];
1942
1943         u8         ether_stats_pkts256to511octets_high[0x20];
1944
1945         u8         ether_stats_pkts256to511octets_low[0x20];
1946
1947         u8         ether_stats_pkts512to1023octets_high[0x20];
1948
1949         u8         ether_stats_pkts512to1023octets_low[0x20];
1950
1951         u8         ether_stats_pkts1024to1518octets_high[0x20];
1952
1953         u8         ether_stats_pkts1024to1518octets_low[0x20];
1954
1955         u8         ether_stats_pkts1519to2047octets_high[0x20];
1956
1957         u8         ether_stats_pkts1519to2047octets_low[0x20];
1958
1959         u8         ether_stats_pkts2048to4095octets_high[0x20];
1960
1961         u8         ether_stats_pkts2048to4095octets_low[0x20];
1962
1963         u8         ether_stats_pkts4096to8191octets_high[0x20];
1964
1965         u8         ether_stats_pkts4096to8191octets_low[0x20];
1966
1967         u8         ether_stats_pkts8192to10239octets_high[0x20];
1968
1969         u8         ether_stats_pkts8192to10239octets_low[0x20];
1970
1971         u8         reserved_at_540[0x280];
1972 };
1973
1974 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1975         u8         if_in_octets_high[0x20];
1976
1977         u8         if_in_octets_low[0x20];
1978
1979         u8         if_in_ucast_pkts_high[0x20];
1980
1981         u8         if_in_ucast_pkts_low[0x20];
1982
1983         u8         if_in_discards_high[0x20];
1984
1985         u8         if_in_discards_low[0x20];
1986
1987         u8         if_in_errors_high[0x20];
1988
1989         u8         if_in_errors_low[0x20];
1990
1991         u8         if_in_unknown_protos_high[0x20];
1992
1993         u8         if_in_unknown_protos_low[0x20];
1994
1995         u8         if_out_octets_high[0x20];
1996
1997         u8         if_out_octets_low[0x20];
1998
1999         u8         if_out_ucast_pkts_high[0x20];
2000
2001         u8         if_out_ucast_pkts_low[0x20];
2002
2003         u8         if_out_discards_high[0x20];
2004
2005         u8         if_out_discards_low[0x20];
2006
2007         u8         if_out_errors_high[0x20];
2008
2009         u8         if_out_errors_low[0x20];
2010
2011         u8         if_in_multicast_pkts_high[0x20];
2012
2013         u8         if_in_multicast_pkts_low[0x20];
2014
2015         u8         if_in_broadcast_pkts_high[0x20];
2016
2017         u8         if_in_broadcast_pkts_low[0x20];
2018
2019         u8         if_out_multicast_pkts_high[0x20];
2020
2021         u8         if_out_multicast_pkts_low[0x20];
2022
2023         u8         if_out_broadcast_pkts_high[0x20];
2024
2025         u8         if_out_broadcast_pkts_low[0x20];
2026
2027         u8         reserved_at_340[0x480];
2028 };
2029
2030 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2031         u8         a_frames_transmitted_ok_high[0x20];
2032
2033         u8         a_frames_transmitted_ok_low[0x20];
2034
2035         u8         a_frames_received_ok_high[0x20];
2036
2037         u8         a_frames_received_ok_low[0x20];
2038
2039         u8         a_frame_check_sequence_errors_high[0x20];
2040
2041         u8         a_frame_check_sequence_errors_low[0x20];
2042
2043         u8         a_alignment_errors_high[0x20];
2044
2045         u8         a_alignment_errors_low[0x20];
2046
2047         u8         a_octets_transmitted_ok_high[0x20];
2048
2049         u8         a_octets_transmitted_ok_low[0x20];
2050
2051         u8         a_octets_received_ok_high[0x20];
2052
2053         u8         a_octets_received_ok_low[0x20];
2054
2055         u8         a_multicast_frames_xmitted_ok_high[0x20];
2056
2057         u8         a_multicast_frames_xmitted_ok_low[0x20];
2058
2059         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2060
2061         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2062
2063         u8         a_multicast_frames_received_ok_high[0x20];
2064
2065         u8         a_multicast_frames_received_ok_low[0x20];
2066
2067         u8         a_broadcast_frames_received_ok_high[0x20];
2068
2069         u8         a_broadcast_frames_received_ok_low[0x20];
2070
2071         u8         a_in_range_length_errors_high[0x20];
2072
2073         u8         a_in_range_length_errors_low[0x20];
2074
2075         u8         a_out_of_range_length_field_high[0x20];
2076
2077         u8         a_out_of_range_length_field_low[0x20];
2078
2079         u8         a_frame_too_long_errors_high[0x20];
2080
2081         u8         a_frame_too_long_errors_low[0x20];
2082
2083         u8         a_symbol_error_during_carrier_high[0x20];
2084
2085         u8         a_symbol_error_during_carrier_low[0x20];
2086
2087         u8         a_mac_control_frames_transmitted_high[0x20];
2088
2089         u8         a_mac_control_frames_transmitted_low[0x20];
2090
2091         u8         a_mac_control_frames_received_high[0x20];
2092
2093         u8         a_mac_control_frames_received_low[0x20];
2094
2095         u8         a_unsupported_opcodes_received_high[0x20];
2096
2097         u8         a_unsupported_opcodes_received_low[0x20];
2098
2099         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2100
2101         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2102
2103         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2104
2105         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2106
2107         u8         reserved_at_4c0[0x300];
2108 };
2109
2110 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2111         u8         life_time_counter_high[0x20];
2112
2113         u8         life_time_counter_low[0x20];
2114
2115         u8         rx_errors[0x20];
2116
2117         u8         tx_errors[0x20];
2118
2119         u8         l0_to_recovery_eieos[0x20];
2120
2121         u8         l0_to_recovery_ts[0x20];
2122
2123         u8         l0_to_recovery_framing[0x20];
2124
2125         u8         l0_to_recovery_retrain[0x20];
2126
2127         u8         crc_error_dllp[0x20];
2128
2129         u8         crc_error_tlp[0x20];
2130
2131         u8         tx_overflow_buffer_pkt_high[0x20];
2132
2133         u8         tx_overflow_buffer_pkt_low[0x20];
2134
2135         u8         outbound_stalled_reads[0x20];
2136
2137         u8         outbound_stalled_writes[0x20];
2138
2139         u8         outbound_stalled_reads_events[0x20];
2140
2141         u8         outbound_stalled_writes_events[0x20];
2142
2143         u8         reserved_at_200[0x5c0];
2144 };
2145
2146 struct mlx5_ifc_cmd_inter_comp_event_bits {
2147         u8         command_completion_vector[0x20];
2148
2149         u8         reserved_at_20[0xc0];
2150 };
2151
2152 struct mlx5_ifc_stall_vl_event_bits {
2153         u8         reserved_at_0[0x18];
2154         u8         port_num[0x1];
2155         u8         reserved_at_19[0x3];
2156         u8         vl[0x4];
2157
2158         u8         reserved_at_20[0xa0];
2159 };
2160
2161 struct mlx5_ifc_db_bf_congestion_event_bits {
2162         u8         event_subtype[0x8];
2163         u8         reserved_at_8[0x8];
2164         u8         congestion_level[0x8];
2165         u8         reserved_at_18[0x8];
2166
2167         u8         reserved_at_20[0xa0];
2168 };
2169
2170 struct mlx5_ifc_gpio_event_bits {
2171         u8         reserved_at_0[0x60];
2172
2173         u8         gpio_event_hi[0x20];
2174
2175         u8         gpio_event_lo[0x20];
2176
2177         u8         reserved_at_a0[0x40];
2178 };
2179
2180 struct mlx5_ifc_port_state_change_event_bits {
2181         u8         reserved_at_0[0x40];
2182
2183         u8         port_num[0x4];
2184         u8         reserved_at_44[0x1c];
2185
2186         u8         reserved_at_60[0x80];
2187 };
2188
2189 struct mlx5_ifc_dropped_packet_logged_bits {
2190         u8         reserved_at_0[0xe0];
2191 };
2192
2193 enum {
2194         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2195         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2196 };
2197
2198 struct mlx5_ifc_cq_error_bits {
2199         u8         reserved_at_0[0x8];
2200         u8         cqn[0x18];
2201
2202         u8         reserved_at_20[0x20];
2203
2204         u8         reserved_at_40[0x18];
2205         u8         syndrome[0x8];
2206
2207         u8         reserved_at_60[0x80];
2208 };
2209
2210 struct mlx5_ifc_rdma_page_fault_event_bits {
2211         u8         bytes_committed[0x20];
2212
2213         u8         r_key[0x20];
2214
2215         u8         reserved_at_40[0x10];
2216         u8         packet_len[0x10];
2217
2218         u8         rdma_op_len[0x20];
2219
2220         u8         rdma_va[0x40];
2221
2222         u8         reserved_at_c0[0x5];
2223         u8         rdma[0x1];
2224         u8         write[0x1];
2225         u8         requestor[0x1];
2226         u8         qp_number[0x18];
2227 };
2228
2229 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2230         u8         bytes_committed[0x20];
2231
2232         u8         reserved_at_20[0x10];
2233         u8         wqe_index[0x10];
2234
2235         u8         reserved_at_40[0x10];
2236         u8         len[0x10];
2237
2238         u8         reserved_at_60[0x60];
2239
2240         u8         reserved_at_c0[0x5];
2241         u8         rdma[0x1];
2242         u8         write_read[0x1];
2243         u8         requestor[0x1];
2244         u8         qpn[0x18];
2245 };
2246
2247 struct mlx5_ifc_qp_events_bits {
2248         u8         reserved_at_0[0xa0];
2249
2250         u8         type[0x8];
2251         u8         reserved_at_a8[0x18];
2252
2253         u8         reserved_at_c0[0x8];
2254         u8         qpn_rqn_sqn[0x18];
2255 };
2256
2257 struct mlx5_ifc_dct_events_bits {
2258         u8         reserved_at_0[0xc0];
2259
2260         u8         reserved_at_c0[0x8];
2261         u8         dct_number[0x18];
2262 };
2263
2264 struct mlx5_ifc_comp_event_bits {
2265         u8         reserved_at_0[0xc0];
2266
2267         u8         reserved_at_c0[0x8];
2268         u8         cq_number[0x18];
2269 };
2270
2271 enum {
2272         MLX5_QPC_STATE_RST        = 0x0,
2273         MLX5_QPC_STATE_INIT       = 0x1,
2274         MLX5_QPC_STATE_RTR        = 0x2,
2275         MLX5_QPC_STATE_RTS        = 0x3,
2276         MLX5_QPC_STATE_SQER       = 0x4,
2277         MLX5_QPC_STATE_ERR        = 0x6,
2278         MLX5_QPC_STATE_SQD        = 0x7,
2279         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2280 };
2281
2282 enum {
2283         MLX5_QPC_ST_RC            = 0x0,
2284         MLX5_QPC_ST_UC            = 0x1,
2285         MLX5_QPC_ST_UD            = 0x2,
2286         MLX5_QPC_ST_XRC           = 0x3,
2287         MLX5_QPC_ST_DCI           = 0x5,
2288         MLX5_QPC_ST_QP0           = 0x7,
2289         MLX5_QPC_ST_QP1           = 0x8,
2290         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2291         MLX5_QPC_ST_REG_UMR       = 0xc,
2292 };
2293
2294 enum {
2295         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2296         MLX5_QPC_PM_STATE_REARM     = 0x1,
2297         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2298         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2299 };
2300
2301 enum {
2302         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2303 };
2304
2305 enum {
2306         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2307         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2308 };
2309
2310 enum {
2311         MLX5_QPC_MTU_256_BYTES        = 0x1,
2312         MLX5_QPC_MTU_512_BYTES        = 0x2,
2313         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2314         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2315         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2316         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2317 };
2318
2319 enum {
2320         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2321         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2322         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2323         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2324         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2325         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2326         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2327         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2328 };
2329
2330 enum {
2331         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2332         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2333         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2334 };
2335
2336 enum {
2337         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2338         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2339         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2340 };
2341
2342 struct mlx5_ifc_qpc_bits {
2343         u8         state[0x4];
2344         u8         lag_tx_port_affinity[0x4];
2345         u8         st[0x8];
2346         u8         reserved_at_10[0x3];
2347         u8         pm_state[0x2];
2348         u8         reserved_at_15[0x1];
2349         u8         req_e2e_credit_mode[0x2];
2350         u8         offload_type[0x4];
2351         u8         end_padding_mode[0x2];
2352         u8         reserved_at_1e[0x2];
2353
2354         u8         wq_signature[0x1];
2355         u8         block_lb_mc[0x1];
2356         u8         atomic_like_write_en[0x1];
2357         u8         latency_sensitive[0x1];
2358         u8         reserved_at_24[0x1];
2359         u8         drain_sigerr[0x1];
2360         u8         reserved_at_26[0x2];
2361         u8         pd[0x18];
2362
2363         u8         mtu[0x3];
2364         u8         log_msg_max[0x5];
2365         u8         reserved_at_48[0x1];
2366         u8         log_rq_size[0x4];
2367         u8         log_rq_stride[0x3];
2368         u8         no_sq[0x1];
2369         u8         log_sq_size[0x4];
2370         u8         reserved_at_55[0x6];
2371         u8         rlky[0x1];
2372         u8         ulp_stateless_offload_mode[0x4];
2373
2374         u8         counter_set_id[0x8];
2375         u8         uar_page[0x18];
2376
2377         u8         reserved_at_80[0x8];
2378         u8         user_index[0x18];
2379
2380         u8         reserved_at_a0[0x3];
2381         u8         log_page_size[0x5];
2382         u8         remote_qpn[0x18];
2383
2384         struct mlx5_ifc_ads_bits primary_address_path;
2385
2386         struct mlx5_ifc_ads_bits secondary_address_path;
2387
2388         u8         log_ack_req_freq[0x4];
2389         u8         reserved_at_384[0x4];
2390         u8         log_sra_max[0x3];
2391         u8         reserved_at_38b[0x2];
2392         u8         retry_count[0x3];
2393         u8         rnr_retry[0x3];
2394         u8         reserved_at_393[0x1];
2395         u8         fre[0x1];
2396         u8         cur_rnr_retry[0x3];
2397         u8         cur_retry_count[0x3];
2398         u8         reserved_at_39b[0x5];
2399
2400         u8         reserved_at_3a0[0x20];
2401
2402         u8         reserved_at_3c0[0x8];
2403         u8         next_send_psn[0x18];
2404
2405         u8         reserved_at_3e0[0x8];
2406         u8         cqn_snd[0x18];
2407
2408         u8         reserved_at_400[0x8];
2409         u8         deth_sqpn[0x18];
2410
2411         u8         reserved_at_420[0x20];
2412
2413         u8         reserved_at_440[0x8];
2414         u8         last_acked_psn[0x18];
2415
2416         u8         reserved_at_460[0x8];
2417         u8         ssn[0x18];
2418
2419         u8         reserved_at_480[0x8];
2420         u8         log_rra_max[0x3];
2421         u8         reserved_at_48b[0x1];
2422         u8         atomic_mode[0x4];
2423         u8         rre[0x1];
2424         u8         rwe[0x1];
2425         u8         rae[0x1];
2426         u8         reserved_at_493[0x1];
2427         u8         page_offset[0x6];
2428         u8         reserved_at_49a[0x3];
2429         u8         cd_slave_receive[0x1];
2430         u8         cd_slave_send[0x1];
2431         u8         cd_master[0x1];
2432
2433         u8         reserved_at_4a0[0x3];
2434         u8         min_rnr_nak[0x5];
2435         u8         next_rcv_psn[0x18];
2436
2437         u8         reserved_at_4c0[0x8];
2438         u8         xrcd[0x18];
2439
2440         u8         reserved_at_4e0[0x8];
2441         u8         cqn_rcv[0x18];
2442
2443         u8         dbr_addr[0x40];
2444
2445         u8         q_key[0x20];
2446
2447         u8         reserved_at_560[0x5];
2448         u8         rq_type[0x3];
2449         u8         srqn_rmpn_xrqn[0x18];
2450
2451         u8         reserved_at_580[0x8];
2452         u8         rmsn[0x18];
2453
2454         u8         hw_sq_wqebb_counter[0x10];
2455         u8         sw_sq_wqebb_counter[0x10];
2456
2457         u8         hw_rq_counter[0x20];
2458
2459         u8         sw_rq_counter[0x20];
2460
2461         u8         reserved_at_600[0x20];
2462
2463         u8         reserved_at_620[0xf];
2464         u8         cgs[0x1];
2465         u8         cs_req[0x8];
2466         u8         cs_res[0x8];
2467
2468         u8         dc_access_key[0x40];
2469
2470         u8         reserved_at_680[0x3];
2471         u8         dbr_umem_valid[0x1];
2472
2473         u8         reserved_at_684[0xbc];
2474 };
2475
2476 struct mlx5_ifc_roce_addr_layout_bits {
2477         u8         source_l3_address[16][0x8];
2478
2479         u8         reserved_at_80[0x3];
2480         u8         vlan_valid[0x1];
2481         u8         vlan_id[0xc];
2482         u8         source_mac_47_32[0x10];
2483
2484         u8         source_mac_31_0[0x20];
2485
2486         u8         reserved_at_c0[0x14];
2487         u8         roce_l3_type[0x4];
2488         u8         roce_version[0x8];
2489
2490         u8         reserved_at_e0[0x20];
2491 };
2492
2493 union mlx5_ifc_hca_cap_union_bits {
2494         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2495         struct mlx5_ifc_odp_cap_bits odp_cap;
2496         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2497         struct mlx5_ifc_roce_cap_bits roce_cap;
2498         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2499         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2500         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2501         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2502         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2503         struct mlx5_ifc_qos_cap_bits qos_cap;
2504         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2505         u8         reserved_at_0[0x8000];
2506 };
2507
2508 enum {
2509         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2510         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2511         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2512         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2513         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2514         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2515         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2516         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2517         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2518         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2519         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2520 };
2521
2522 struct mlx5_ifc_vlan_bits {
2523         u8         ethtype[0x10];
2524         u8         prio[0x3];
2525         u8         cfi[0x1];
2526         u8         vid[0xc];
2527 };
2528
2529 struct mlx5_ifc_flow_context_bits {
2530         struct mlx5_ifc_vlan_bits push_vlan;
2531
2532         u8         group_id[0x20];
2533
2534         u8         reserved_at_40[0x8];
2535         u8         flow_tag[0x18];
2536
2537         u8         reserved_at_60[0x10];
2538         u8         action[0x10];
2539
2540         u8         extended_destination[0x1];
2541         u8         reserved_at_80[0x7];
2542         u8         destination_list_size[0x18];
2543
2544         u8         reserved_at_a0[0x8];
2545         u8         flow_counter_list_size[0x18];
2546
2547         u8         packet_reformat_id[0x20];
2548
2549         u8         modify_header_id[0x20];
2550
2551         struct mlx5_ifc_vlan_bits push_vlan_2;
2552
2553         u8         reserved_at_120[0xe0];
2554
2555         struct mlx5_ifc_fte_match_param_bits match_value;
2556
2557         u8         reserved_at_1200[0x600];
2558
2559         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2560 };
2561
2562 enum {
2563         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2564         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2565 };
2566
2567 struct mlx5_ifc_xrc_srqc_bits {
2568         u8         state[0x4];
2569         u8         log_xrc_srq_size[0x4];
2570         u8         reserved_at_8[0x18];
2571
2572         u8         wq_signature[0x1];
2573         u8         cont_srq[0x1];
2574         u8         reserved_at_22[0x1];
2575         u8         rlky[0x1];
2576         u8         basic_cyclic_rcv_wqe[0x1];
2577         u8         log_rq_stride[0x3];
2578         u8         xrcd[0x18];
2579
2580         u8         page_offset[0x6];
2581         u8         reserved_at_46[0x1];
2582         u8         dbr_umem_valid[0x1];
2583         u8         cqn[0x18];
2584
2585         u8         reserved_at_60[0x20];
2586
2587         u8         user_index_equal_xrc_srqn[0x1];
2588         u8         reserved_at_81[0x1];
2589         u8         log_page_size[0x6];
2590         u8         user_index[0x18];
2591
2592         u8         reserved_at_a0[0x20];
2593
2594         u8         reserved_at_c0[0x8];
2595         u8         pd[0x18];
2596
2597         u8         lwm[0x10];
2598         u8         wqe_cnt[0x10];
2599
2600         u8         reserved_at_100[0x40];
2601
2602         u8         db_record_addr_h[0x20];
2603
2604         u8         db_record_addr_l[0x1e];
2605         u8         reserved_at_17e[0x2];
2606
2607         u8         reserved_at_180[0x80];
2608 };
2609
2610 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2611         u8         counter_error_queues[0x20];
2612
2613         u8         total_error_queues[0x20];
2614
2615         u8         send_queue_priority_update_flow[0x20];
2616
2617         u8         reserved_at_60[0x20];
2618
2619         u8         nic_receive_steering_discard[0x40];
2620
2621         u8         receive_discard_vport_down[0x40];
2622
2623         u8         transmit_discard_vport_down[0x40];
2624
2625         u8         reserved_at_140[0xec0];
2626 };
2627
2628 struct mlx5_ifc_traffic_counter_bits {
2629         u8         packets[0x40];
2630
2631         u8         octets[0x40];
2632 };
2633
2634 struct mlx5_ifc_tisc_bits {
2635         u8         strict_lag_tx_port_affinity[0x1];
2636         u8         reserved_at_1[0x3];
2637         u8         lag_tx_port_affinity[0x04];
2638
2639         u8         reserved_at_8[0x4];
2640         u8         prio[0x4];
2641         u8         reserved_at_10[0x10];
2642
2643         u8         reserved_at_20[0x100];
2644
2645         u8         reserved_at_120[0x8];
2646         u8         transport_domain[0x18];
2647
2648         u8         reserved_at_140[0x8];
2649         u8         underlay_qpn[0x18];
2650         u8         reserved_at_160[0x3a0];
2651 };
2652
2653 enum {
2654         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2655         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2656 };
2657
2658 enum {
2659         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2660         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2661 };
2662
2663 enum {
2664         MLX5_RX_HASH_FN_NONE           = 0x0,
2665         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2666         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2667 };
2668
2669 enum {
2670         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2671         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2672 };
2673
2674 struct mlx5_ifc_tirc_bits {
2675         u8         reserved_at_0[0x20];
2676
2677         u8         disp_type[0x4];
2678         u8         reserved_at_24[0x1c];
2679
2680         u8         reserved_at_40[0x40];
2681
2682         u8         reserved_at_80[0x4];
2683         u8         lro_timeout_period_usecs[0x10];
2684         u8         lro_enable_mask[0x4];
2685         u8         lro_max_ip_payload_size[0x8];
2686
2687         u8         reserved_at_a0[0x40];
2688
2689         u8         reserved_at_e0[0x8];
2690         u8         inline_rqn[0x18];
2691
2692         u8         rx_hash_symmetric[0x1];
2693         u8         reserved_at_101[0x1];
2694         u8         tunneled_offload_en[0x1];
2695         u8         reserved_at_103[0x5];
2696         u8         indirect_table[0x18];
2697
2698         u8         rx_hash_fn[0x4];
2699         u8         reserved_at_124[0x2];
2700         u8         self_lb_block[0x2];
2701         u8         transport_domain[0x18];
2702
2703         u8         rx_hash_toeplitz_key[10][0x20];
2704
2705         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2706
2707         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2708
2709         u8         reserved_at_2c0[0x4c0];
2710 };
2711
2712 enum {
2713         MLX5_SRQC_STATE_GOOD   = 0x0,
2714         MLX5_SRQC_STATE_ERROR  = 0x1,
2715 };
2716
2717 struct mlx5_ifc_srqc_bits {
2718         u8         state[0x4];
2719         u8         log_srq_size[0x4];
2720         u8         reserved_at_8[0x18];
2721
2722         u8         wq_signature[0x1];
2723         u8         cont_srq[0x1];
2724         u8         reserved_at_22[0x1];
2725         u8         rlky[0x1];
2726         u8         reserved_at_24[0x1];
2727         u8         log_rq_stride[0x3];
2728         u8         xrcd[0x18];
2729
2730         u8         page_offset[0x6];
2731         u8         reserved_at_46[0x2];
2732         u8         cqn[0x18];
2733
2734         u8         reserved_at_60[0x20];
2735
2736         u8         reserved_at_80[0x2];
2737         u8         log_page_size[0x6];
2738         u8         reserved_at_88[0x18];
2739
2740         u8         reserved_at_a0[0x20];
2741
2742         u8         reserved_at_c0[0x8];
2743         u8         pd[0x18];
2744
2745         u8         lwm[0x10];
2746         u8         wqe_cnt[0x10];
2747
2748         u8         reserved_at_100[0x40];
2749
2750         u8         dbr_addr[0x40];
2751
2752         u8         reserved_at_180[0x80];
2753 };
2754
2755 enum {
2756         MLX5_SQC_STATE_RST  = 0x0,
2757         MLX5_SQC_STATE_RDY  = 0x1,
2758         MLX5_SQC_STATE_ERR  = 0x3,
2759 };
2760
2761 struct mlx5_ifc_sqc_bits {
2762         u8         rlky[0x1];
2763         u8         cd_master[0x1];
2764         u8         fre[0x1];
2765         u8         flush_in_error_en[0x1];
2766         u8         allow_multi_pkt_send_wqe[0x1];
2767         u8         min_wqe_inline_mode[0x3];
2768         u8         state[0x4];
2769         u8         reg_umr[0x1];
2770         u8         allow_swp[0x1];
2771         u8         hairpin[0x1];
2772         u8         reserved_at_f[0x11];
2773
2774         u8         reserved_at_20[0x8];
2775         u8         user_index[0x18];
2776
2777         u8         reserved_at_40[0x8];
2778         u8         cqn[0x18];
2779
2780         u8         reserved_at_60[0x8];
2781         u8         hairpin_peer_rq[0x18];
2782
2783         u8         reserved_at_80[0x10];
2784         u8         hairpin_peer_vhca[0x10];
2785
2786         u8         reserved_at_a0[0x50];
2787
2788         u8         packet_pacing_rate_limit_index[0x10];
2789         u8         tis_lst_sz[0x10];
2790         u8         reserved_at_110[0x10];
2791
2792         u8         reserved_at_120[0x40];
2793
2794         u8         reserved_at_160[0x8];
2795         u8         tis_num_0[0x18];
2796
2797         struct mlx5_ifc_wq_bits wq;
2798 };
2799
2800 enum {
2801         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2802         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2803         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2804         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2805 };
2806
2807 struct mlx5_ifc_scheduling_context_bits {
2808         u8         element_type[0x8];
2809         u8         reserved_at_8[0x18];
2810
2811         u8         element_attributes[0x20];
2812
2813         u8         parent_element_id[0x20];
2814
2815         u8         reserved_at_60[0x40];
2816
2817         u8         bw_share[0x20];
2818
2819         u8         max_average_bw[0x20];
2820
2821         u8         reserved_at_e0[0x120];
2822 };
2823
2824 struct mlx5_ifc_rqtc_bits {
2825         u8         reserved_at_0[0xa0];
2826
2827         u8         reserved_at_a0[0x10];
2828         u8         rqt_max_size[0x10];
2829
2830         u8         reserved_at_c0[0x10];
2831         u8         rqt_actual_size[0x10];
2832
2833         u8         reserved_at_e0[0x6a0];
2834
2835         struct mlx5_ifc_rq_num_bits rq_num[0];
2836 };
2837
2838 enum {
2839         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2840         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2841 };
2842
2843 enum {
2844         MLX5_RQC_STATE_RST  = 0x0,
2845         MLX5_RQC_STATE_RDY  = 0x1,
2846         MLX5_RQC_STATE_ERR  = 0x3,
2847 };
2848
2849 struct mlx5_ifc_rqc_bits {
2850         u8         rlky[0x1];
2851         u8         delay_drop_en[0x1];
2852         u8         scatter_fcs[0x1];
2853         u8         vsd[0x1];
2854         u8         mem_rq_type[0x4];
2855         u8         state[0x4];
2856         u8         reserved_at_c[0x1];
2857         u8         flush_in_error_en[0x1];
2858         u8         hairpin[0x1];
2859         u8         reserved_at_f[0x11];
2860
2861         u8         reserved_at_20[0x8];
2862         u8         user_index[0x18];
2863
2864         u8         reserved_at_40[0x8];
2865         u8         cqn[0x18];
2866
2867         u8         counter_set_id[0x8];
2868         u8         reserved_at_68[0x18];
2869
2870         u8         reserved_at_80[0x8];
2871         u8         rmpn[0x18];
2872
2873         u8         reserved_at_a0[0x8];
2874         u8         hairpin_peer_sq[0x18];
2875
2876         u8         reserved_at_c0[0x10];
2877         u8         hairpin_peer_vhca[0x10];
2878
2879         u8         reserved_at_e0[0xa0];
2880
2881         struct mlx5_ifc_wq_bits wq;
2882 };
2883
2884 enum {
2885         MLX5_RMPC_STATE_RDY  = 0x1,
2886         MLX5_RMPC_STATE_ERR  = 0x3,
2887 };
2888
2889 struct mlx5_ifc_rmpc_bits {
2890         u8         reserved_at_0[0x8];
2891         u8         state[0x4];
2892         u8         reserved_at_c[0x14];
2893
2894         u8         basic_cyclic_rcv_wqe[0x1];
2895         u8         reserved_at_21[0x1f];
2896
2897         u8         reserved_at_40[0x140];
2898
2899         struct mlx5_ifc_wq_bits wq;
2900 };
2901
2902 struct mlx5_ifc_nic_vport_context_bits {
2903         u8         reserved_at_0[0x5];
2904         u8         min_wqe_inline_mode[0x3];
2905         u8         reserved_at_8[0x15];
2906         u8         disable_mc_local_lb[0x1];
2907         u8         disable_uc_local_lb[0x1];
2908         u8         roce_en[0x1];
2909
2910         u8         arm_change_event[0x1];
2911         u8         reserved_at_21[0x1a];
2912         u8         event_on_mtu[0x1];
2913         u8         event_on_promisc_change[0x1];
2914         u8         event_on_vlan_change[0x1];
2915         u8         event_on_mc_address_change[0x1];
2916         u8         event_on_uc_address_change[0x1];
2917
2918         u8         reserved_at_40[0xc];
2919
2920         u8         affiliation_criteria[0x4];
2921         u8         affiliated_vhca_id[0x10];
2922
2923         u8         reserved_at_60[0xd0];
2924
2925         u8         mtu[0x10];
2926
2927         u8         system_image_guid[0x40];
2928         u8         port_guid[0x40];
2929         u8         node_guid[0x40];
2930
2931         u8         reserved_at_200[0x140];
2932         u8         qkey_violation_counter[0x10];
2933         u8         reserved_at_350[0x430];
2934
2935         u8         promisc_uc[0x1];
2936         u8         promisc_mc[0x1];
2937         u8         promisc_all[0x1];
2938         u8         reserved_at_783[0x2];
2939         u8         allowed_list_type[0x3];
2940         u8         reserved_at_788[0xc];
2941         u8         allowed_list_size[0xc];
2942
2943         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2944
2945         u8         reserved_at_7e0[0x20];
2946
2947         u8         current_uc_mac_address[0][0x40];
2948 };
2949
2950 enum {
2951         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2952         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2953         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2954         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2955         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
2956         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2957 };
2958
2959 struct mlx5_ifc_mkc_bits {
2960         u8         reserved_at_0[0x1];
2961         u8         free[0x1];
2962         u8         reserved_at_2[0x1];
2963         u8         access_mode_4_2[0x3];
2964         u8         reserved_at_6[0x7];
2965         u8         relaxed_ordering_write[0x1];
2966         u8         reserved_at_e[0x1];
2967         u8         small_fence_on_rdma_read_response[0x1];
2968         u8         umr_en[0x1];
2969         u8         a[0x1];
2970         u8         rw[0x1];
2971         u8         rr[0x1];
2972         u8         lw[0x1];
2973         u8         lr[0x1];
2974         u8         access_mode_1_0[0x2];
2975         u8         reserved_at_18[0x8];
2976
2977         u8         qpn[0x18];
2978         u8         mkey_7_0[0x8];
2979
2980         u8         reserved_at_40[0x20];
2981
2982         u8         length64[0x1];
2983         u8         bsf_en[0x1];
2984         u8         sync_umr[0x1];
2985         u8         reserved_at_63[0x2];
2986         u8         expected_sigerr_count[0x1];
2987         u8         reserved_at_66[0x1];
2988         u8         en_rinval[0x1];
2989         u8         pd[0x18];
2990
2991         u8         start_addr[0x40];
2992
2993         u8         len[0x40];
2994
2995         u8         bsf_octword_size[0x20];
2996
2997         u8         reserved_at_120[0x80];
2998
2999         u8         translations_octword_size[0x20];
3000
3001         u8         reserved_at_1c0[0x1b];
3002         u8         log_page_size[0x5];
3003
3004         u8         reserved_at_1e0[0x20];
3005 };
3006
3007 struct mlx5_ifc_pkey_bits {
3008         u8         reserved_at_0[0x10];
3009         u8         pkey[0x10];
3010 };
3011
3012 struct mlx5_ifc_array128_auto_bits {
3013         u8         array128_auto[16][0x8];
3014 };
3015
3016 struct mlx5_ifc_hca_vport_context_bits {
3017         u8         field_select[0x20];
3018
3019         u8         reserved_at_20[0xe0];
3020
3021         u8         sm_virt_aware[0x1];
3022         u8         has_smi[0x1];
3023         u8         has_raw[0x1];
3024         u8         grh_required[0x1];
3025         u8         reserved_at_104[0xc];
3026         u8         port_physical_state[0x4];
3027         u8         vport_state_policy[0x4];
3028         u8         port_state[0x4];
3029         u8         vport_state[0x4];
3030
3031         u8         reserved_at_120[0x20];
3032
3033         u8         system_image_guid[0x40];
3034
3035         u8         port_guid[0x40];
3036
3037         u8         node_guid[0x40];
3038
3039         u8         cap_mask1[0x20];
3040
3041         u8         cap_mask1_field_select[0x20];
3042
3043         u8         cap_mask2[0x20];
3044
3045         u8         cap_mask2_field_select[0x20];
3046
3047         u8         reserved_at_280[0x80];
3048
3049         u8         lid[0x10];
3050         u8         reserved_at_310[0x4];
3051         u8         init_type_reply[0x4];
3052         u8         lmc[0x3];
3053         u8         subnet_timeout[0x5];
3054
3055         u8         sm_lid[0x10];
3056         u8         sm_sl[0x4];
3057         u8         reserved_at_334[0xc];
3058
3059         u8         qkey_violation_counter[0x10];
3060         u8         pkey_violation_counter[0x10];
3061
3062         u8         reserved_at_360[0xca0];
3063 };
3064
3065 struct mlx5_ifc_esw_vport_context_bits {
3066         u8         reserved_at_0[0x3];
3067         u8         vport_svlan_strip[0x1];
3068         u8         vport_cvlan_strip[0x1];
3069         u8         vport_svlan_insert[0x1];
3070         u8         vport_cvlan_insert[0x2];
3071         u8         reserved_at_8[0x18];
3072
3073         u8         reserved_at_20[0x20];
3074
3075         u8         svlan_cfi[0x1];
3076         u8         svlan_pcp[0x3];
3077         u8         svlan_id[0xc];
3078         u8         cvlan_cfi[0x1];
3079         u8         cvlan_pcp[0x3];
3080         u8         cvlan_id[0xc];
3081
3082         u8         reserved_at_60[0x7a0];
3083 };
3084
3085 enum {
3086         MLX5_EQC_STATUS_OK                = 0x0,
3087         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3088 };
3089
3090 enum {
3091         MLX5_EQC_ST_ARMED  = 0x9,
3092         MLX5_EQC_ST_FIRED  = 0xa,
3093 };
3094
3095 struct mlx5_ifc_eqc_bits {
3096         u8         status[0x4];
3097         u8         reserved_at_4[0x9];
3098         u8         ec[0x1];
3099         u8         oi[0x1];
3100         u8         reserved_at_f[0x5];
3101         u8         st[0x4];
3102         u8         reserved_at_18[0x8];
3103
3104         u8         reserved_at_20[0x20];
3105
3106         u8         reserved_at_40[0x14];
3107         u8         page_offset[0x6];
3108         u8         reserved_at_5a[0x6];
3109
3110         u8         reserved_at_60[0x3];
3111         u8         log_eq_size[0x5];
3112         u8         uar_page[0x18];
3113
3114         u8         reserved_at_80[0x20];
3115
3116         u8         reserved_at_a0[0x18];
3117         u8         intr[0x8];
3118
3119         u8         reserved_at_c0[0x3];
3120         u8         log_page_size[0x5];
3121         u8         reserved_at_c8[0x18];
3122
3123         u8         reserved_at_e0[0x60];
3124
3125         u8         reserved_at_140[0x8];
3126         u8         consumer_counter[0x18];
3127
3128         u8         reserved_at_160[0x8];
3129         u8         producer_counter[0x18];
3130
3131         u8         reserved_at_180[0x80];
3132 };
3133
3134 enum {
3135         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3136         MLX5_DCTC_STATE_DRAINING  = 0x1,
3137         MLX5_DCTC_STATE_DRAINED   = 0x2,
3138 };
3139
3140 enum {
3141         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3142         MLX5_DCTC_CS_RES_NA         = 0x1,
3143         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3144 };
3145
3146 enum {
3147         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3148         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3149         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3150         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3151         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3152 };
3153
3154 struct mlx5_ifc_dctc_bits {
3155         u8         reserved_at_0[0x4];
3156         u8         state[0x4];
3157         u8         reserved_at_8[0x18];
3158
3159         u8         reserved_at_20[0x8];
3160         u8         user_index[0x18];
3161
3162         u8         reserved_at_40[0x8];
3163         u8         cqn[0x18];
3164
3165         u8         counter_set_id[0x8];
3166         u8         atomic_mode[0x4];
3167         u8         rre[0x1];
3168         u8         rwe[0x1];
3169         u8         rae[0x1];
3170         u8         atomic_like_write_en[0x1];
3171         u8         latency_sensitive[0x1];
3172         u8         rlky[0x1];
3173         u8         free_ar[0x1];
3174         u8         reserved_at_73[0xd];
3175
3176         u8         reserved_at_80[0x8];
3177         u8         cs_res[0x8];
3178         u8         reserved_at_90[0x3];
3179         u8         min_rnr_nak[0x5];
3180         u8         reserved_at_98[0x8];
3181
3182         u8         reserved_at_a0[0x8];
3183         u8         srqn_xrqn[0x18];
3184
3185         u8         reserved_at_c0[0x8];
3186         u8         pd[0x18];
3187
3188         u8         tclass[0x8];
3189         u8         reserved_at_e8[0x4];
3190         u8         flow_label[0x14];
3191
3192         u8         dc_access_key[0x40];
3193
3194         u8         reserved_at_140[0x5];
3195         u8         mtu[0x3];
3196         u8         port[0x8];
3197         u8         pkey_index[0x10];
3198
3199         u8         reserved_at_160[0x8];
3200         u8         my_addr_index[0x8];
3201         u8         reserved_at_170[0x8];
3202         u8         hop_limit[0x8];
3203
3204         u8         dc_access_key_violation_count[0x20];
3205
3206         u8         reserved_at_1a0[0x14];
3207         u8         dei_cfi[0x1];
3208         u8         eth_prio[0x3];
3209         u8         ecn[0x2];
3210         u8         dscp[0x6];
3211
3212         u8         reserved_at_1c0[0x40];
3213 };
3214
3215 enum {
3216         MLX5_CQC_STATUS_OK             = 0x0,
3217         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3218         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3219 };
3220
3221 enum {
3222         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3223         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3224 };
3225
3226 enum {
3227         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3228         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3229         MLX5_CQC_ST_FIRED                                 = 0xa,
3230 };
3231
3232 enum {
3233         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3234         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3235         MLX5_CQ_PERIOD_NUM_MODES
3236 };
3237
3238 struct mlx5_ifc_cqc_bits {
3239         u8         status[0x4];
3240         u8         reserved_at_4[0x2];
3241         u8         dbr_umem_valid[0x1];
3242         u8         reserved_at_7[0x1];
3243         u8         cqe_sz[0x3];
3244         u8         cc[0x1];
3245         u8         reserved_at_c[0x1];
3246         u8         scqe_break_moderation_en[0x1];
3247         u8         oi[0x1];
3248         u8         cq_period_mode[0x2];
3249         u8         cqe_comp_en[0x1];
3250         u8         mini_cqe_res_format[0x2];
3251         u8         st[0x4];
3252         u8         reserved_at_18[0x8];
3253
3254         u8         reserved_at_20[0x20];
3255
3256         u8         reserved_at_40[0x14];
3257         u8         page_offset[0x6];
3258         u8         reserved_at_5a[0x6];
3259
3260         u8         reserved_at_60[0x3];
3261         u8         log_cq_size[0x5];
3262         u8         uar_page[0x18];
3263
3264         u8         reserved_at_80[0x4];
3265         u8         cq_period[0xc];
3266         u8         cq_max_count[0x10];
3267
3268         u8         reserved_at_a0[0x18];
3269         u8         c_eqn[0x8];
3270
3271         u8         reserved_at_c0[0x3];
3272         u8         log_page_size[0x5];
3273         u8         reserved_at_c8[0x18];
3274
3275         u8         reserved_at_e0[0x20];
3276
3277         u8         reserved_at_100[0x8];
3278         u8         last_notified_index[0x18];
3279
3280         u8         reserved_at_120[0x8];
3281         u8         last_solicit_index[0x18];
3282
3283         u8         reserved_at_140[0x8];
3284         u8         consumer_counter[0x18];
3285
3286         u8         reserved_at_160[0x8];
3287         u8         producer_counter[0x18];
3288
3289         u8         reserved_at_180[0x40];
3290
3291         u8         dbr_addr[0x40];
3292 };
3293
3294 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3295         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3296         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3297         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3298         u8         reserved_at_0[0x800];
3299 };
3300
3301 struct mlx5_ifc_query_adapter_param_block_bits {
3302         u8         reserved_at_0[0xc0];
3303
3304         u8         reserved_at_c0[0x8];
3305         u8         ieee_vendor_id[0x18];
3306
3307         u8         reserved_at_e0[0x10];
3308         u8         vsd_vendor_id[0x10];
3309
3310         u8         vsd[208][0x8];
3311
3312         u8         vsd_contd_psid[16][0x8];
3313 };
3314
3315 enum {
3316         MLX5_XRQC_STATE_GOOD   = 0x0,
3317         MLX5_XRQC_STATE_ERROR  = 0x1,
3318 };
3319
3320 enum {
3321         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3322         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3323 };
3324
3325 enum {
3326         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3327 };
3328
3329 struct mlx5_ifc_tag_matching_topology_context_bits {
3330         u8         log_matching_list_sz[0x4];
3331         u8         reserved_at_4[0xc];
3332         u8         append_next_index[0x10];
3333
3334         u8         sw_phase_cnt[0x10];
3335         u8         hw_phase_cnt[0x10];
3336
3337         u8         reserved_at_40[0x40];
3338 };
3339
3340 struct mlx5_ifc_xrqc_bits {
3341         u8         state[0x4];
3342         u8         rlkey[0x1];
3343         u8         reserved_at_5[0xf];
3344         u8         topology[0x4];
3345         u8         reserved_at_18[0x4];
3346         u8         offload[0x4];
3347
3348         u8         reserved_at_20[0x8];
3349         u8         user_index[0x18];
3350
3351         u8         reserved_at_40[0x8];
3352         u8         cqn[0x18];
3353
3354         u8         reserved_at_60[0xa0];
3355
3356         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3357
3358         u8         reserved_at_180[0x280];
3359
3360         struct mlx5_ifc_wq_bits wq;
3361 };
3362
3363 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3364         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3365         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3366         u8         reserved_at_0[0x20];
3367 };
3368
3369 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3370         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3371         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3372         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3373         u8         reserved_at_0[0x20];
3374 };
3375
3376 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3377         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3378         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3379         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3380         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3381         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3382         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3383         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3384         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3385         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3386         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3387         u8         reserved_at_0[0x7c0];
3388 };
3389
3390 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3391         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3392         u8         reserved_at_0[0x7c0];
3393 };
3394
3395 union mlx5_ifc_event_auto_bits {
3396         struct mlx5_ifc_comp_event_bits comp_event;
3397         struct mlx5_ifc_dct_events_bits dct_events;
3398         struct mlx5_ifc_qp_events_bits qp_events;
3399         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3400         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3401         struct mlx5_ifc_cq_error_bits cq_error;
3402         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3403         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3404         struct mlx5_ifc_gpio_event_bits gpio_event;
3405         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3406         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3407         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3408         u8         reserved_at_0[0xe0];
3409 };
3410
3411 struct mlx5_ifc_health_buffer_bits {
3412         u8         reserved_at_0[0x100];
3413
3414         u8         assert_existptr[0x20];
3415
3416         u8         assert_callra[0x20];
3417
3418         u8         reserved_at_140[0x40];
3419
3420         u8         fw_version[0x20];
3421
3422         u8         hw_id[0x20];
3423
3424         u8         reserved_at_1c0[0x20];
3425
3426         u8         irisc_index[0x8];
3427         u8         synd[0x8];
3428         u8         ext_synd[0x10];
3429 };
3430
3431 struct mlx5_ifc_register_loopback_control_bits {
3432         u8         no_lb[0x1];
3433         u8         reserved_at_1[0x7];
3434         u8         port[0x8];
3435         u8         reserved_at_10[0x10];
3436
3437         u8         reserved_at_20[0x60];
3438 };
3439
3440 struct mlx5_ifc_vport_tc_element_bits {
3441         u8         traffic_class[0x4];
3442         u8         reserved_at_4[0xc];
3443         u8         vport_number[0x10];
3444 };
3445
3446 struct mlx5_ifc_vport_element_bits {
3447         u8         reserved_at_0[0x10];
3448         u8         vport_number[0x10];
3449 };
3450
3451 enum {
3452         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3453         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3454         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3455 };
3456
3457 struct mlx5_ifc_tsar_element_bits {
3458         u8         reserved_at_0[0x8];
3459         u8         tsar_type[0x8];
3460         u8         reserved_at_10[0x10];
3461 };
3462
3463 enum {
3464         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3465         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3466 };
3467
3468 struct mlx5_ifc_teardown_hca_out_bits {
3469         u8         status[0x8];
3470         u8         reserved_at_8[0x18];
3471
3472         u8         syndrome[0x20];
3473
3474         u8         reserved_at_40[0x3f];
3475
3476         u8         state[0x1];
3477 };
3478
3479 enum {
3480         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3481         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3482         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3483 };
3484
3485 struct mlx5_ifc_teardown_hca_in_bits {
3486         u8         opcode[0x10];
3487         u8         reserved_at_10[0x10];
3488
3489         u8         reserved_at_20[0x10];
3490         u8         op_mod[0x10];
3491
3492         u8         reserved_at_40[0x10];
3493         u8         profile[0x10];
3494
3495         u8         reserved_at_60[0x20];
3496 };
3497
3498 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3499         u8         status[0x8];
3500         u8         reserved_at_8[0x18];
3501
3502         u8         syndrome[0x20];
3503
3504         u8         reserved_at_40[0x40];
3505 };
3506
3507 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3508         u8         opcode[0x10];
3509         u8         uid[0x10];
3510
3511         u8         reserved_at_20[0x10];
3512         u8         op_mod[0x10];
3513
3514         u8         reserved_at_40[0x8];
3515         u8         qpn[0x18];
3516
3517         u8         reserved_at_60[0x20];
3518
3519         u8         opt_param_mask[0x20];
3520
3521         u8         reserved_at_a0[0x20];
3522
3523         struct mlx5_ifc_qpc_bits qpc;
3524
3525         u8         reserved_at_800[0x80];
3526 };
3527
3528 struct mlx5_ifc_sqd2rts_qp_out_bits {
3529         u8         status[0x8];
3530         u8         reserved_at_8[0x18];
3531
3532         u8         syndrome[0x20];
3533
3534         u8         reserved_at_40[0x40];
3535 };
3536
3537 struct mlx5_ifc_sqd2rts_qp_in_bits {
3538         u8         opcode[0x10];
3539         u8         uid[0x10];
3540
3541         u8         reserved_at_20[0x10];
3542         u8         op_mod[0x10];
3543
3544         u8         reserved_at_40[0x8];
3545         u8         qpn[0x18];
3546
3547         u8         reserved_at_60[0x20];
3548
3549         u8         opt_param_mask[0x20];
3550
3551         u8         reserved_at_a0[0x20];
3552
3553         struct mlx5_ifc_qpc_bits qpc;
3554
3555         u8         reserved_at_800[0x80];
3556 };
3557
3558 struct mlx5_ifc_set_roce_address_out_bits {
3559         u8         status[0x8];
3560         u8         reserved_at_8[0x18];
3561
3562         u8         syndrome[0x20];
3563
3564         u8         reserved_at_40[0x40];
3565 };
3566
3567 struct mlx5_ifc_set_roce_address_in_bits {
3568         u8         opcode[0x10];
3569         u8         reserved_at_10[0x10];
3570
3571         u8         reserved_at_20[0x10];
3572         u8         op_mod[0x10];
3573
3574         u8         roce_address_index[0x10];
3575         u8         reserved_at_50[0xc];
3576         u8         vhca_port_num[0x4];
3577
3578         u8         reserved_at_60[0x20];
3579
3580         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3581 };
3582
3583 struct mlx5_ifc_set_mad_demux_out_bits {
3584         u8         status[0x8];
3585         u8         reserved_at_8[0x18];
3586
3587         u8         syndrome[0x20];
3588
3589         u8         reserved_at_40[0x40];
3590 };
3591
3592 enum {
3593         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3594         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3595 };
3596
3597 struct mlx5_ifc_set_mad_demux_in_bits {
3598         u8         opcode[0x10];
3599         u8         reserved_at_10[0x10];
3600
3601         u8         reserved_at_20[0x10];
3602         u8         op_mod[0x10];
3603
3604         u8         reserved_at_40[0x20];
3605
3606         u8         reserved_at_60[0x6];
3607         u8         demux_mode[0x2];
3608         u8         reserved_at_68[0x18];
3609 };
3610
3611 struct mlx5_ifc_set_l2_table_entry_out_bits {
3612         u8         status[0x8];
3613         u8         reserved_at_8[0x18];
3614
3615         u8         syndrome[0x20];
3616
3617         u8         reserved_at_40[0x40];
3618 };
3619
3620 struct mlx5_ifc_set_l2_table_entry_in_bits {
3621         u8         opcode[0x10];
3622         u8         reserved_at_10[0x10];
3623
3624         u8         reserved_at_20[0x10];
3625         u8         op_mod[0x10];
3626
3627         u8         reserved_at_40[0x60];
3628
3629         u8         reserved_at_a0[0x8];
3630         u8         table_index[0x18];
3631
3632         u8         reserved_at_c0[0x20];
3633
3634         u8         reserved_at_e0[0x13];
3635         u8         vlan_valid[0x1];
3636         u8         vlan[0xc];
3637
3638         struct mlx5_ifc_mac_address_layout_bits mac_address;
3639
3640         u8         reserved_at_140[0xc0];
3641 };
3642
3643 struct mlx5_ifc_set_issi_out_bits {
3644         u8         status[0x8];
3645         u8         reserved_at_8[0x18];
3646
3647         u8         syndrome[0x20];
3648
3649         u8         reserved_at_40[0x40];
3650 };
3651
3652 struct mlx5_ifc_set_issi_in_bits {
3653         u8         opcode[0x10];
3654         u8         reserved_at_10[0x10];
3655
3656         u8         reserved_at_20[0x10];
3657         u8         op_mod[0x10];
3658
3659         u8         reserved_at_40[0x10];
3660         u8         current_issi[0x10];
3661
3662         u8         reserved_at_60[0x20];
3663 };
3664
3665 struct mlx5_ifc_set_hca_cap_out_bits {
3666         u8         status[0x8];
3667         u8         reserved_at_8[0x18];
3668
3669         u8         syndrome[0x20];
3670
3671         u8         reserved_at_40[0x40];
3672 };
3673
3674 struct mlx5_ifc_set_hca_cap_in_bits {
3675         u8         opcode[0x10];
3676         u8         reserved_at_10[0x10];
3677
3678         u8         reserved_at_20[0x10];
3679         u8         op_mod[0x10];
3680
3681         u8         reserved_at_40[0x40];
3682
3683         union mlx5_ifc_hca_cap_union_bits capability;
3684 };
3685
3686 enum {
3687         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3688         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3689         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3690         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3691 };
3692
3693 struct mlx5_ifc_set_fte_out_bits {
3694         u8         status[0x8];
3695         u8         reserved_at_8[0x18];
3696
3697         u8         syndrome[0x20];
3698
3699         u8         reserved_at_40[0x40];
3700 };
3701
3702 struct mlx5_ifc_set_fte_in_bits {
3703         u8         opcode[0x10];
3704         u8         reserved_at_10[0x10];
3705
3706         u8         reserved_at_20[0x10];
3707         u8         op_mod[0x10];
3708
3709         u8         other_vport[0x1];
3710         u8         reserved_at_41[0xf];
3711         u8         vport_number[0x10];
3712
3713         u8         reserved_at_60[0x20];
3714
3715         u8         table_type[0x8];
3716         u8         reserved_at_88[0x18];
3717
3718         u8         reserved_at_a0[0x8];
3719         u8         table_id[0x18];
3720
3721         u8         reserved_at_c0[0x18];
3722         u8         modify_enable_mask[0x8];
3723
3724         u8         reserved_at_e0[0x20];
3725
3726         u8         flow_index[0x20];
3727
3728         u8         reserved_at_120[0xe0];
3729
3730         struct mlx5_ifc_flow_context_bits flow_context;
3731 };
3732
3733 struct mlx5_ifc_rts2rts_qp_out_bits {
3734         u8         status[0x8];
3735         u8         reserved_at_8[0x18];
3736
3737         u8         syndrome[0x20];
3738
3739         u8         reserved_at_40[0x40];
3740 };
3741
3742 struct mlx5_ifc_rts2rts_qp_in_bits {
3743         u8         opcode[0x10];
3744         u8         uid[0x10];
3745
3746         u8         reserved_at_20[0x10];
3747         u8         op_mod[0x10];
3748
3749         u8         reserved_at_40[0x8];
3750         u8         qpn[0x18];
3751
3752         u8         reserved_at_60[0x20];
3753
3754         u8         opt_param_mask[0x20];
3755
3756         u8         reserved_at_a0[0x20];
3757
3758         struct mlx5_ifc_qpc_bits qpc;
3759
3760         u8         reserved_at_800[0x80];
3761 };
3762
3763 struct mlx5_ifc_rtr2rts_qp_out_bits {
3764         u8         status[0x8];
3765         u8         reserved_at_8[0x18];
3766
3767         u8         syndrome[0x20];
3768
3769         u8         reserved_at_40[0x40];
3770 };
3771
3772 struct mlx5_ifc_rtr2rts_qp_in_bits {
3773         u8         opcode[0x10];
3774         u8         uid[0x10];
3775
3776         u8         reserved_at_20[0x10];
3777         u8         op_mod[0x10];
3778
3779         u8         reserved_at_40[0x8];
3780         u8         qpn[0x18];
3781
3782         u8         reserved_at_60[0x20];
3783
3784         u8         opt_param_mask[0x20];
3785
3786         u8         reserved_at_a0[0x20];
3787
3788         struct mlx5_ifc_qpc_bits qpc;
3789
3790         u8         reserved_at_800[0x80];
3791 };
3792
3793 struct mlx5_ifc_rst2init_qp_out_bits {
3794         u8         status[0x8];
3795         u8         reserved_at_8[0x18];
3796
3797         u8         syndrome[0x20];
3798
3799         u8         reserved_at_40[0x40];
3800 };
3801
3802 struct mlx5_ifc_rst2init_qp_in_bits {
3803         u8         opcode[0x10];
3804         u8         uid[0x10];
3805
3806         u8         reserved_at_20[0x10];
3807         u8         op_mod[0x10];
3808
3809         u8         reserved_at_40[0x8];
3810         u8         qpn[0x18];
3811
3812         u8         reserved_at_60[0x20];
3813
3814         u8         opt_param_mask[0x20];
3815
3816         u8         reserved_at_a0[0x20];
3817
3818         struct mlx5_ifc_qpc_bits qpc;
3819
3820         u8         reserved_at_800[0x80];
3821 };
3822
3823 struct mlx5_ifc_query_xrq_out_bits {
3824         u8         status[0x8];
3825         u8         reserved_at_8[0x18];
3826
3827         u8         syndrome[0x20];
3828
3829         u8         reserved_at_40[0x40];
3830
3831         struct mlx5_ifc_xrqc_bits xrq_context;
3832 };
3833
3834 struct mlx5_ifc_query_xrq_in_bits {
3835         u8         opcode[0x10];
3836         u8         reserved_at_10[0x10];
3837
3838         u8         reserved_at_20[0x10];
3839         u8         op_mod[0x10];
3840
3841         u8         reserved_at_40[0x8];
3842         u8         xrqn[0x18];
3843
3844         u8         reserved_at_60[0x20];
3845 };
3846
3847 struct mlx5_ifc_query_xrc_srq_out_bits {
3848         u8         status[0x8];
3849         u8         reserved_at_8[0x18];
3850
3851         u8         syndrome[0x20];
3852
3853         u8         reserved_at_40[0x40];
3854
3855         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3856
3857         u8         reserved_at_280[0x600];
3858
3859         u8         pas[0][0x40];
3860 };
3861
3862 struct mlx5_ifc_query_xrc_srq_in_bits {
3863         u8         opcode[0x10];
3864         u8         reserved_at_10[0x10];
3865
3866         u8         reserved_at_20[0x10];
3867         u8         op_mod[0x10];
3868
3869         u8         reserved_at_40[0x8];
3870         u8         xrc_srqn[0x18];
3871
3872         u8         reserved_at_60[0x20];
3873 };
3874
3875 enum {
3876         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3877         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3878 };
3879
3880 struct mlx5_ifc_query_vport_state_out_bits {
3881         u8         status[0x8];
3882         u8         reserved_at_8[0x18];
3883
3884         u8         syndrome[0x20];
3885
3886         u8         reserved_at_40[0x20];
3887
3888         u8         reserved_at_60[0x18];
3889         u8         admin_state[0x4];
3890         u8         state[0x4];
3891 };
3892
3893 enum {
3894         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
3895         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
3896 };
3897
3898 struct mlx5_ifc_arm_monitor_counter_in_bits {
3899         u8         opcode[0x10];
3900         u8         uid[0x10];
3901
3902         u8         reserved_at_20[0x10];
3903         u8         op_mod[0x10];
3904
3905         u8         reserved_at_40[0x20];
3906
3907         u8         reserved_at_60[0x20];
3908 };
3909
3910 struct mlx5_ifc_arm_monitor_counter_out_bits {
3911         u8         status[0x8];
3912         u8         reserved_at_8[0x18];
3913
3914         u8         syndrome[0x20];
3915
3916         u8         reserved_at_40[0x40];
3917 };
3918
3919 enum {
3920         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
3921         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
3922 };
3923
3924 enum mlx5_monitor_counter_ppcnt {
3925         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
3926         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
3927         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
3928         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
3929         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
3930         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
3931 };
3932
3933 enum {
3934         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
3935 };
3936
3937 struct mlx5_ifc_monitor_counter_output_bits {
3938         u8         reserved_at_0[0x4];
3939         u8         type[0x4];
3940         u8         reserved_at_8[0x8];
3941         u8         counter[0x10];
3942
3943         u8         counter_group_id[0x20];
3944 };
3945
3946 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
3947 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
3948 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
3949                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
3950
3951 struct mlx5_ifc_set_monitor_counter_in_bits {
3952         u8         opcode[0x10];
3953         u8         uid[0x10];
3954
3955         u8         reserved_at_20[0x10];
3956         u8         op_mod[0x10];
3957
3958         u8         reserved_at_40[0x10];
3959         u8         num_of_counters[0x10];
3960
3961         u8         reserved_at_60[0x20];
3962
3963         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
3964 };
3965
3966 struct mlx5_ifc_set_monitor_counter_out_bits {
3967         u8         status[0x8];
3968         u8         reserved_at_8[0x18];
3969
3970         u8         syndrome[0x20];
3971
3972         u8         reserved_at_40[0x40];
3973 };
3974
3975 struct mlx5_ifc_query_vport_state_in_bits {
3976         u8         opcode[0x10];
3977         u8         reserved_at_10[0x10];
3978
3979         u8         reserved_at_20[0x10];
3980         u8         op_mod[0x10];
3981
3982         u8         other_vport[0x1];
3983         u8         reserved_at_41[0xf];
3984         u8         vport_number[0x10];
3985
3986         u8         reserved_at_60[0x20];
3987 };
3988
3989 struct mlx5_ifc_query_vnic_env_out_bits {
3990         u8         status[0x8];
3991         u8         reserved_at_8[0x18];
3992
3993         u8         syndrome[0x20];
3994
3995         u8         reserved_at_40[0x40];
3996
3997         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3998 };
3999
4000 enum {
4001         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4002 };
4003
4004 struct mlx5_ifc_query_vnic_env_in_bits {
4005         u8         opcode[0x10];
4006         u8         reserved_at_10[0x10];
4007
4008         u8         reserved_at_20[0x10];
4009         u8         op_mod[0x10];
4010
4011         u8         other_vport[0x1];
4012         u8         reserved_at_41[0xf];
4013         u8         vport_number[0x10];
4014
4015         u8         reserved_at_60[0x20];
4016 };
4017
4018 struct mlx5_ifc_query_vport_counter_out_bits {
4019         u8         status[0x8];
4020         u8         reserved_at_8[0x18];
4021
4022         u8         syndrome[0x20];
4023
4024         u8         reserved_at_40[0x40];
4025
4026         struct mlx5_ifc_traffic_counter_bits received_errors;
4027
4028         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4029
4030         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4031
4032         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4033
4034         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4035
4036         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4037
4038         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4039
4040         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4041
4042         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4043
4044         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4045
4046         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4047
4048         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4049
4050         u8         reserved_at_680[0xa00];
4051 };
4052
4053 enum {
4054         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4055 };
4056
4057 struct mlx5_ifc_query_vport_counter_in_bits {
4058         u8         opcode[0x10];
4059         u8         reserved_at_10[0x10];
4060
4061         u8         reserved_at_20[0x10];
4062         u8         op_mod[0x10];
4063
4064         u8         other_vport[0x1];
4065         u8         reserved_at_41[0xb];
4066         u8         port_num[0x4];
4067         u8         vport_number[0x10];
4068
4069         u8         reserved_at_60[0x60];
4070
4071         u8         clear[0x1];
4072         u8         reserved_at_c1[0x1f];
4073
4074         u8         reserved_at_e0[0x20];
4075 };
4076
4077 struct mlx5_ifc_query_tis_out_bits {
4078         u8         status[0x8];
4079         u8         reserved_at_8[0x18];
4080
4081         u8         syndrome[0x20];
4082
4083         u8         reserved_at_40[0x40];
4084
4085         struct mlx5_ifc_tisc_bits tis_context;
4086 };
4087
4088 struct mlx5_ifc_query_tis_in_bits {
4089         u8         opcode[0x10];
4090         u8         reserved_at_10[0x10];
4091
4092         u8         reserved_at_20[0x10];
4093         u8         op_mod[0x10];
4094
4095         u8         reserved_at_40[0x8];
4096         u8         tisn[0x18];
4097
4098         u8         reserved_at_60[0x20];
4099 };
4100
4101 struct mlx5_ifc_query_tir_out_bits {
4102         u8         status[0x8];
4103         u8         reserved_at_8[0x18];
4104
4105         u8         syndrome[0x20];
4106
4107         u8         reserved_at_40[0xc0];
4108
4109         struct mlx5_ifc_tirc_bits tir_context;
4110 };
4111
4112 struct mlx5_ifc_query_tir_in_bits {
4113         u8         opcode[0x10];
4114         u8         reserved_at_10[0x10];
4115
4116         u8         reserved_at_20[0x10];
4117         u8         op_mod[0x10];
4118
4119         u8         reserved_at_40[0x8];
4120         u8         tirn[0x18];
4121
4122         u8         reserved_at_60[0x20];
4123 };
4124
4125 struct mlx5_ifc_query_srq_out_bits {
4126         u8         status[0x8];
4127         u8         reserved_at_8[0x18];
4128
4129         u8         syndrome[0x20];
4130
4131         u8         reserved_at_40[0x40];
4132
4133         struct mlx5_ifc_srqc_bits srq_context_entry;
4134
4135         u8         reserved_at_280[0x600];
4136
4137         u8         pas[0][0x40];
4138 };
4139
4140 struct mlx5_ifc_query_srq_in_bits {
4141         u8         opcode[0x10];
4142         u8         reserved_at_10[0x10];
4143
4144         u8         reserved_at_20[0x10];
4145         u8         op_mod[0x10];
4146
4147         u8         reserved_at_40[0x8];
4148         u8         srqn[0x18];
4149
4150         u8         reserved_at_60[0x20];
4151 };
4152
4153 struct mlx5_ifc_query_sq_out_bits {
4154         u8         status[0x8];
4155         u8         reserved_at_8[0x18];
4156
4157         u8         syndrome[0x20];
4158
4159         u8         reserved_at_40[0xc0];
4160
4161         struct mlx5_ifc_sqc_bits sq_context;
4162 };
4163
4164 struct mlx5_ifc_query_sq_in_bits {
4165         u8         opcode[0x10];
4166         u8         reserved_at_10[0x10];
4167
4168         u8         reserved_at_20[0x10];
4169         u8         op_mod[0x10];
4170
4171         u8         reserved_at_40[0x8];
4172         u8         sqn[0x18];
4173
4174         u8         reserved_at_60[0x20];
4175 };
4176
4177 struct mlx5_ifc_query_special_contexts_out_bits {
4178         u8         status[0x8];
4179         u8         reserved_at_8[0x18];
4180
4181         u8         syndrome[0x20];
4182
4183         u8         dump_fill_mkey[0x20];
4184
4185         u8         resd_lkey[0x20];
4186
4187         u8         null_mkey[0x20];
4188
4189         u8         reserved_at_a0[0x60];
4190 };
4191
4192 struct mlx5_ifc_query_special_contexts_in_bits {
4193         u8         opcode[0x10];
4194         u8         reserved_at_10[0x10];
4195
4196         u8         reserved_at_20[0x10];
4197         u8         op_mod[0x10];
4198
4199         u8         reserved_at_40[0x40];
4200 };
4201
4202 struct mlx5_ifc_query_scheduling_element_out_bits {
4203         u8         opcode[0x10];
4204         u8         reserved_at_10[0x10];
4205
4206         u8         reserved_at_20[0x10];
4207         u8         op_mod[0x10];
4208
4209         u8         reserved_at_40[0xc0];
4210
4211         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4212
4213         u8         reserved_at_300[0x100];
4214 };
4215
4216 enum {
4217         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4218 };
4219
4220 struct mlx5_ifc_query_scheduling_element_in_bits {
4221         u8         opcode[0x10];
4222         u8         reserved_at_10[0x10];
4223
4224         u8         reserved_at_20[0x10];
4225         u8         op_mod[0x10];
4226
4227         u8         scheduling_hierarchy[0x8];
4228         u8         reserved_at_48[0x18];
4229
4230         u8         scheduling_element_id[0x20];
4231
4232         u8         reserved_at_80[0x180];
4233 };
4234
4235 struct mlx5_ifc_query_rqt_out_bits {
4236         u8         status[0x8];
4237         u8         reserved_at_8[0x18];
4238
4239         u8         syndrome[0x20];
4240
4241         u8         reserved_at_40[0xc0];
4242
4243         struct mlx5_ifc_rqtc_bits rqt_context;
4244 };
4245
4246 struct mlx5_ifc_query_rqt_in_bits {
4247         u8         opcode[0x10];
4248         u8         reserved_at_10[0x10];
4249
4250         u8         reserved_at_20[0x10];
4251         u8         op_mod[0x10];
4252
4253         u8         reserved_at_40[0x8];
4254         u8         rqtn[0x18];
4255
4256         u8         reserved_at_60[0x20];
4257 };
4258
4259 struct mlx5_ifc_query_rq_out_bits {
4260         u8         status[0x8];
4261         u8         reserved_at_8[0x18];
4262
4263         u8         syndrome[0x20];
4264
4265         u8         reserved_at_40[0xc0];
4266
4267         struct mlx5_ifc_rqc_bits rq_context;
4268 };
4269
4270 struct mlx5_ifc_query_rq_in_bits {
4271         u8         opcode[0x10];
4272         u8         reserved_at_10[0x10];
4273
4274         u8         reserved_at_20[0x10];
4275         u8         op_mod[0x10];
4276
4277         u8         reserved_at_40[0x8];
4278         u8         rqn[0x18];
4279
4280         u8         reserved_at_60[0x20];
4281 };
4282
4283 struct mlx5_ifc_query_roce_address_out_bits {
4284         u8         status[0x8];
4285         u8         reserved_at_8[0x18];
4286
4287         u8         syndrome[0x20];
4288
4289         u8         reserved_at_40[0x40];
4290
4291         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4292 };
4293
4294 struct mlx5_ifc_query_roce_address_in_bits {
4295         u8         opcode[0x10];
4296         u8         reserved_at_10[0x10];
4297
4298         u8         reserved_at_20[0x10];
4299         u8         op_mod[0x10];
4300
4301         u8         roce_address_index[0x10];
4302         u8         reserved_at_50[0xc];
4303         u8         vhca_port_num[0x4];
4304
4305         u8         reserved_at_60[0x20];
4306 };
4307
4308 struct mlx5_ifc_query_rmp_out_bits {
4309         u8         status[0x8];
4310         u8         reserved_at_8[0x18];
4311
4312         u8         syndrome[0x20];
4313
4314         u8         reserved_at_40[0xc0];
4315
4316         struct mlx5_ifc_rmpc_bits rmp_context;
4317 };
4318
4319 struct mlx5_ifc_query_rmp_in_bits {
4320         u8         opcode[0x10];
4321         u8         reserved_at_10[0x10];
4322
4323         u8         reserved_at_20[0x10];
4324         u8         op_mod[0x10];
4325
4326         u8         reserved_at_40[0x8];
4327         u8         rmpn[0x18];
4328
4329         u8         reserved_at_60[0x20];
4330 };
4331
4332 struct mlx5_ifc_query_qp_out_bits {
4333         u8         status[0x8];
4334         u8         reserved_at_8[0x18];
4335
4336         u8         syndrome[0x20];
4337
4338         u8         reserved_at_40[0x40];
4339
4340         u8         opt_param_mask[0x20];
4341
4342         u8         reserved_at_a0[0x20];
4343
4344         struct mlx5_ifc_qpc_bits qpc;
4345
4346         u8         reserved_at_800[0x80];
4347
4348         u8         pas[0][0x40];
4349 };
4350
4351 struct mlx5_ifc_query_qp_in_bits {
4352         u8         opcode[0x10];
4353         u8         reserved_at_10[0x10];
4354
4355         u8         reserved_at_20[0x10];
4356         u8         op_mod[0x10];
4357
4358         u8         reserved_at_40[0x8];
4359         u8         qpn[0x18];
4360
4361         u8         reserved_at_60[0x20];
4362 };
4363
4364 struct mlx5_ifc_query_q_counter_out_bits {
4365         u8         status[0x8];
4366         u8         reserved_at_8[0x18];
4367
4368         u8         syndrome[0x20];
4369
4370         u8         reserved_at_40[0x40];
4371
4372         u8         rx_write_requests[0x20];
4373
4374         u8         reserved_at_a0[0x20];
4375
4376         u8         rx_read_requests[0x20];
4377
4378         u8         reserved_at_e0[0x20];
4379
4380         u8         rx_atomic_requests[0x20];
4381
4382         u8         reserved_at_120[0x20];
4383
4384         u8         rx_dct_connect[0x20];
4385
4386         u8         reserved_at_160[0x20];
4387
4388         u8         out_of_buffer[0x20];
4389
4390         u8         reserved_at_1a0[0x20];
4391
4392         u8         out_of_sequence[0x20];
4393
4394         u8         reserved_at_1e0[0x20];
4395
4396         u8         duplicate_request[0x20];
4397
4398         u8         reserved_at_220[0x20];
4399
4400         u8         rnr_nak_retry_err[0x20];
4401
4402         u8         reserved_at_260[0x20];
4403
4404         u8         packet_seq_err[0x20];
4405
4406         u8         reserved_at_2a0[0x20];
4407
4408         u8         implied_nak_seq_err[0x20];
4409
4410         u8         reserved_at_2e0[0x20];
4411
4412         u8         local_ack_timeout_err[0x20];
4413
4414         u8         reserved_at_320[0xa0];
4415
4416         u8         resp_local_length_error[0x20];
4417
4418         u8         req_local_length_error[0x20];
4419
4420         u8         resp_local_qp_error[0x20];
4421
4422         u8         local_operation_error[0x20];
4423
4424         u8         resp_local_protection[0x20];
4425
4426         u8         req_local_protection[0x20];
4427
4428         u8         resp_cqe_error[0x20];
4429
4430         u8         req_cqe_error[0x20];
4431
4432         u8         req_mw_binding[0x20];
4433
4434         u8         req_bad_response[0x20];
4435
4436         u8         req_remote_invalid_request[0x20];
4437
4438         u8         resp_remote_invalid_request[0x20];
4439
4440         u8         req_remote_access_errors[0x20];
4441
4442         u8         resp_remote_access_errors[0x20];
4443
4444         u8         req_remote_operation_errors[0x20];
4445
4446         u8         req_transport_retries_exceeded[0x20];
4447
4448         u8         cq_overflow[0x20];
4449
4450         u8         resp_cqe_flush_error[0x20];
4451
4452         u8         req_cqe_flush_error[0x20];
4453
4454         u8         reserved_at_620[0x1e0];
4455 };
4456
4457 struct mlx5_ifc_query_q_counter_in_bits {
4458         u8         opcode[0x10];
4459         u8         reserved_at_10[0x10];
4460
4461         u8         reserved_at_20[0x10];
4462         u8         op_mod[0x10];
4463
4464         u8         reserved_at_40[0x80];
4465
4466         u8         clear[0x1];
4467         u8         reserved_at_c1[0x1f];
4468
4469         u8         reserved_at_e0[0x18];
4470         u8         counter_set_id[0x8];
4471 };
4472
4473 struct mlx5_ifc_query_pages_out_bits {
4474         u8         status[0x8];
4475         u8         reserved_at_8[0x18];
4476
4477         u8         syndrome[0x20];
4478
4479         u8         embedded_cpu_function[0x1];
4480         u8         reserved_at_41[0xf];
4481         u8         function_id[0x10];
4482
4483         u8         num_pages[0x20];
4484 };
4485
4486 enum {
4487         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4488         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4489         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4490 };
4491
4492 struct mlx5_ifc_query_pages_in_bits {
4493         u8         opcode[0x10];
4494         u8         reserved_at_10[0x10];
4495
4496         u8         reserved_at_20[0x10];
4497         u8         op_mod[0x10];
4498
4499         u8         embedded_cpu_function[0x1];
4500         u8         reserved_at_41[0xf];
4501         u8         function_id[0x10];
4502
4503         u8         reserved_at_60[0x20];
4504 };
4505
4506 struct mlx5_ifc_query_nic_vport_context_out_bits {
4507         u8         status[0x8];
4508         u8         reserved_at_8[0x18];
4509
4510         u8         syndrome[0x20];
4511
4512         u8         reserved_at_40[0x40];
4513
4514         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4515 };
4516
4517 struct mlx5_ifc_query_nic_vport_context_in_bits {
4518         u8         opcode[0x10];
4519         u8         reserved_at_10[0x10];
4520
4521         u8         reserved_at_20[0x10];
4522         u8         op_mod[0x10];
4523
4524         u8         other_vport[0x1];
4525         u8         reserved_at_41[0xf];
4526         u8         vport_number[0x10];
4527
4528         u8         reserved_at_60[0x5];
4529         u8         allowed_list_type[0x3];
4530         u8         reserved_at_68[0x18];
4531 };
4532
4533 struct mlx5_ifc_query_mkey_out_bits {
4534         u8         status[0x8];
4535         u8         reserved_at_8[0x18];
4536
4537         u8         syndrome[0x20];
4538
4539         u8         reserved_at_40[0x40];
4540
4541         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4542
4543         u8         reserved_at_280[0x600];
4544
4545         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4546
4547         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4548 };
4549
4550 struct mlx5_ifc_query_mkey_in_bits {
4551         u8         opcode[0x10];
4552         u8         reserved_at_10[0x10];
4553
4554         u8         reserved_at_20[0x10];
4555         u8         op_mod[0x10];
4556
4557         u8         reserved_at_40[0x8];
4558         u8         mkey_index[0x18];
4559
4560         u8         pg_access[0x1];
4561         u8         reserved_at_61[0x1f];
4562 };
4563
4564 struct mlx5_ifc_query_mad_demux_out_bits {
4565         u8         status[0x8];
4566         u8         reserved_at_8[0x18];
4567
4568         u8         syndrome[0x20];
4569
4570         u8         reserved_at_40[0x40];
4571
4572         u8         mad_dumux_parameters_block[0x20];
4573 };
4574
4575 struct mlx5_ifc_query_mad_demux_in_bits {
4576         u8         opcode[0x10];
4577         u8         reserved_at_10[0x10];
4578
4579         u8         reserved_at_20[0x10];
4580         u8         op_mod[0x10];
4581
4582         u8         reserved_at_40[0x40];
4583 };
4584
4585 struct mlx5_ifc_query_l2_table_entry_out_bits {
4586         u8         status[0x8];
4587         u8         reserved_at_8[0x18];
4588
4589         u8         syndrome[0x20];
4590
4591         u8         reserved_at_40[0xa0];
4592
4593         u8         reserved_at_e0[0x13];
4594         u8         vlan_valid[0x1];
4595         u8         vlan[0xc];
4596
4597         struct mlx5_ifc_mac_address_layout_bits mac_address;
4598
4599         u8         reserved_at_140[0xc0];
4600 };
4601
4602 struct mlx5_ifc_query_l2_table_entry_in_bits {
4603         u8         opcode[0x10];
4604         u8         reserved_at_10[0x10];
4605
4606         u8         reserved_at_20[0x10];
4607         u8         op_mod[0x10];
4608
4609         u8         reserved_at_40[0x60];
4610
4611         u8         reserved_at_a0[0x8];
4612         u8         table_index[0x18];
4613
4614         u8         reserved_at_c0[0x140];
4615 };
4616
4617 struct mlx5_ifc_query_issi_out_bits {
4618         u8         status[0x8];
4619         u8         reserved_at_8[0x18];
4620
4621         u8         syndrome[0x20];
4622
4623         u8         reserved_at_40[0x10];
4624         u8         current_issi[0x10];
4625
4626         u8         reserved_at_60[0xa0];
4627
4628         u8         reserved_at_100[76][0x8];
4629         u8         supported_issi_dw0[0x20];
4630 };
4631
4632 struct mlx5_ifc_query_issi_in_bits {
4633         u8         opcode[0x10];
4634         u8         reserved_at_10[0x10];
4635
4636         u8         reserved_at_20[0x10];
4637         u8         op_mod[0x10];
4638
4639         u8         reserved_at_40[0x40];
4640 };
4641
4642 struct mlx5_ifc_set_driver_version_out_bits {
4643         u8         status[0x8];
4644         u8         reserved_0[0x18];
4645
4646         u8         syndrome[0x20];
4647         u8         reserved_1[0x40];
4648 };
4649
4650 struct mlx5_ifc_set_driver_version_in_bits {
4651         u8         opcode[0x10];
4652         u8         reserved_0[0x10];
4653
4654         u8         reserved_1[0x10];
4655         u8         op_mod[0x10];
4656
4657         u8         reserved_2[0x40];
4658         u8         driver_version[64][0x8];
4659 };
4660
4661 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4662         u8         status[0x8];
4663         u8         reserved_at_8[0x18];
4664
4665         u8         syndrome[0x20];
4666
4667         u8         reserved_at_40[0x40];
4668
4669         struct mlx5_ifc_pkey_bits pkey[0];
4670 };
4671
4672 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4673         u8         opcode[0x10];
4674         u8         reserved_at_10[0x10];
4675
4676         u8         reserved_at_20[0x10];
4677         u8         op_mod[0x10];
4678
4679         u8         other_vport[0x1];
4680         u8         reserved_at_41[0xb];
4681         u8         port_num[0x4];
4682         u8         vport_number[0x10];
4683
4684         u8         reserved_at_60[0x10];
4685         u8         pkey_index[0x10];
4686 };
4687
4688 enum {
4689         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4690         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4691         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4692 };
4693
4694 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4695         u8         status[0x8];
4696         u8         reserved_at_8[0x18];
4697
4698         u8         syndrome[0x20];
4699
4700         u8         reserved_at_40[0x20];
4701
4702         u8         gids_num[0x10];
4703         u8         reserved_at_70[0x10];
4704
4705         struct mlx5_ifc_array128_auto_bits gid[0];
4706 };
4707
4708 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4709         u8         opcode[0x10];
4710         u8         reserved_at_10[0x10];
4711
4712         u8         reserved_at_20[0x10];
4713         u8         op_mod[0x10];
4714
4715         u8         other_vport[0x1];
4716         u8         reserved_at_41[0xb];
4717         u8         port_num[0x4];
4718         u8         vport_number[0x10];
4719
4720         u8         reserved_at_60[0x10];
4721         u8         gid_index[0x10];
4722 };
4723
4724 struct mlx5_ifc_query_hca_vport_context_out_bits {
4725         u8         status[0x8];
4726         u8         reserved_at_8[0x18];
4727
4728         u8         syndrome[0x20];
4729
4730         u8         reserved_at_40[0x40];
4731
4732         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4733 };
4734
4735 struct mlx5_ifc_query_hca_vport_context_in_bits {
4736         u8         opcode[0x10];
4737         u8         reserved_at_10[0x10];
4738
4739         u8         reserved_at_20[0x10];
4740         u8         op_mod[0x10];
4741
4742         u8         other_vport[0x1];
4743         u8         reserved_at_41[0xb];
4744         u8         port_num[0x4];
4745         u8         vport_number[0x10];
4746
4747         u8         reserved_at_60[0x20];
4748 };
4749
4750 struct mlx5_ifc_query_hca_cap_out_bits {
4751         u8         status[0x8];
4752         u8         reserved_at_8[0x18];
4753
4754         u8         syndrome[0x20];
4755
4756         u8         reserved_at_40[0x40];
4757
4758         union mlx5_ifc_hca_cap_union_bits capability;
4759 };
4760
4761 struct mlx5_ifc_query_hca_cap_in_bits {
4762         u8         opcode[0x10];
4763         u8         reserved_at_10[0x10];
4764
4765         u8         reserved_at_20[0x10];
4766         u8         op_mod[0x10];
4767
4768         u8         reserved_at_40[0x40];
4769 };
4770
4771 struct mlx5_ifc_query_flow_table_out_bits {
4772         u8         status[0x8];
4773         u8         reserved_at_8[0x18];
4774
4775         u8         syndrome[0x20];
4776
4777         u8         reserved_at_40[0x80];
4778
4779         u8         reserved_at_c0[0x8];
4780         u8         level[0x8];
4781         u8         reserved_at_d0[0x8];
4782         u8         log_size[0x8];
4783
4784         u8         reserved_at_e0[0x120];
4785 };
4786
4787 struct mlx5_ifc_query_flow_table_in_bits {
4788         u8         opcode[0x10];
4789         u8         reserved_at_10[0x10];
4790
4791         u8         reserved_at_20[0x10];
4792         u8         op_mod[0x10];
4793
4794         u8         reserved_at_40[0x40];
4795
4796         u8         table_type[0x8];
4797         u8         reserved_at_88[0x18];
4798
4799         u8         reserved_at_a0[0x8];
4800         u8         table_id[0x18];
4801
4802         u8         reserved_at_c0[0x140];
4803 };
4804
4805 struct mlx5_ifc_query_fte_out_bits {
4806         u8         status[0x8];
4807         u8         reserved_at_8[0x18];
4808
4809         u8         syndrome[0x20];
4810
4811         u8         reserved_at_40[0x1c0];
4812
4813         struct mlx5_ifc_flow_context_bits flow_context;
4814 };
4815
4816 struct mlx5_ifc_query_fte_in_bits {
4817         u8         opcode[0x10];
4818         u8         reserved_at_10[0x10];
4819
4820         u8         reserved_at_20[0x10];
4821         u8         op_mod[0x10];
4822
4823         u8         reserved_at_40[0x40];
4824
4825         u8         table_type[0x8];
4826         u8         reserved_at_88[0x18];
4827
4828         u8         reserved_at_a0[0x8];
4829         u8         table_id[0x18];
4830
4831         u8         reserved_at_c0[0x40];
4832
4833         u8         flow_index[0x20];
4834
4835         u8         reserved_at_120[0xe0];
4836 };
4837
4838 enum {
4839         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4840         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4841         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4842         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
4843 };
4844
4845 struct mlx5_ifc_query_flow_group_out_bits {
4846         u8         status[0x8];
4847         u8         reserved_at_8[0x18];
4848
4849         u8         syndrome[0x20];
4850
4851         u8         reserved_at_40[0xa0];
4852
4853         u8         start_flow_index[0x20];
4854
4855         u8         reserved_at_100[0x20];
4856
4857         u8         end_flow_index[0x20];
4858
4859         u8         reserved_at_140[0xa0];
4860
4861         u8         reserved_at_1e0[0x18];
4862         u8         match_criteria_enable[0x8];
4863
4864         struct mlx5_ifc_fte_match_param_bits match_criteria;
4865
4866         u8         reserved_at_1200[0xe00];
4867 };
4868
4869 struct mlx5_ifc_query_flow_group_in_bits {
4870         u8         opcode[0x10];
4871         u8         reserved_at_10[0x10];
4872
4873         u8         reserved_at_20[0x10];
4874         u8         op_mod[0x10];
4875
4876         u8         reserved_at_40[0x40];
4877
4878         u8         table_type[0x8];
4879         u8         reserved_at_88[0x18];
4880
4881         u8         reserved_at_a0[0x8];
4882         u8         table_id[0x18];
4883
4884         u8         group_id[0x20];
4885
4886         u8         reserved_at_e0[0x120];
4887 };
4888
4889 struct mlx5_ifc_query_flow_counter_out_bits {
4890         u8         status[0x8];
4891         u8         reserved_at_8[0x18];
4892
4893         u8         syndrome[0x20];
4894
4895         u8         reserved_at_40[0x40];
4896
4897         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4898 };
4899
4900 struct mlx5_ifc_query_flow_counter_in_bits {
4901         u8         opcode[0x10];
4902         u8         reserved_at_10[0x10];
4903
4904         u8         reserved_at_20[0x10];
4905         u8         op_mod[0x10];
4906
4907         u8         reserved_at_40[0x80];
4908
4909         u8         clear[0x1];
4910         u8         reserved_at_c1[0xf];
4911         u8         num_of_counters[0x10];
4912
4913         u8         flow_counter_id[0x20];
4914 };
4915
4916 struct mlx5_ifc_query_esw_vport_context_out_bits {
4917         u8         status[0x8];
4918         u8         reserved_at_8[0x18];
4919
4920         u8         syndrome[0x20];
4921
4922         u8         reserved_at_40[0x40];
4923
4924         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4925 };
4926
4927 struct mlx5_ifc_query_esw_vport_context_in_bits {
4928         u8         opcode[0x10];
4929         u8         reserved_at_10[0x10];
4930
4931         u8         reserved_at_20[0x10];
4932         u8         op_mod[0x10];
4933
4934         u8         other_vport[0x1];
4935         u8         reserved_at_41[0xf];
4936         u8         vport_number[0x10];
4937
4938         u8         reserved_at_60[0x20];
4939 };
4940
4941 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4942         u8         status[0x8];
4943         u8         reserved_at_8[0x18];
4944
4945         u8         syndrome[0x20];
4946
4947         u8         reserved_at_40[0x40];
4948 };
4949
4950 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4951         u8         reserved_at_0[0x1c];
4952         u8         vport_cvlan_insert[0x1];
4953         u8         vport_svlan_insert[0x1];
4954         u8         vport_cvlan_strip[0x1];
4955         u8         vport_svlan_strip[0x1];
4956 };
4957
4958 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4959         u8         opcode[0x10];
4960         u8         reserved_at_10[0x10];
4961
4962         u8         reserved_at_20[0x10];
4963         u8         op_mod[0x10];
4964
4965         u8         other_vport[0x1];
4966         u8         reserved_at_41[0xf];
4967         u8         vport_number[0x10];
4968
4969         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4970
4971         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4972 };
4973
4974 struct mlx5_ifc_query_eq_out_bits {
4975         u8         status[0x8];
4976         u8         reserved_at_8[0x18];
4977
4978         u8         syndrome[0x20];
4979
4980         u8         reserved_at_40[0x40];
4981
4982         struct mlx5_ifc_eqc_bits eq_context_entry;
4983
4984         u8         reserved_at_280[0x40];
4985
4986         u8         event_bitmask[0x40];
4987
4988         u8         reserved_at_300[0x580];
4989
4990         u8         pas[0][0x40];
4991 };
4992
4993 struct mlx5_ifc_query_eq_in_bits {
4994         u8         opcode[0x10];
4995         u8         reserved_at_10[0x10];
4996
4997         u8         reserved_at_20[0x10];
4998         u8         op_mod[0x10];
4999
5000         u8         reserved_at_40[0x18];
5001         u8         eq_number[0x8];
5002
5003         u8         reserved_at_60[0x20];
5004 };
5005
5006 struct mlx5_ifc_packet_reformat_context_in_bits {
5007         u8         reserved_at_0[0x5];
5008         u8         reformat_type[0x3];
5009         u8         reserved_at_8[0xe];
5010         u8         reformat_data_size[0xa];
5011
5012         u8         reserved_at_20[0x10];
5013         u8         reformat_data[2][0x8];
5014
5015         u8         more_reformat_data[0][0x8];
5016 };
5017
5018 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5019         u8         status[0x8];
5020         u8         reserved_at_8[0x18];
5021
5022         u8         syndrome[0x20];
5023
5024         u8         reserved_at_40[0xa0];
5025
5026         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5027 };
5028
5029 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5030         u8         opcode[0x10];
5031         u8         reserved_at_10[0x10];
5032
5033         u8         reserved_at_20[0x10];
5034         u8         op_mod[0x10];
5035
5036         u8         packet_reformat_id[0x20];
5037
5038         u8         reserved_at_60[0xa0];
5039 };
5040
5041 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5042         u8         status[0x8];
5043         u8         reserved_at_8[0x18];
5044
5045         u8         syndrome[0x20];
5046
5047         u8         packet_reformat_id[0x20];
5048
5049         u8         reserved_at_60[0x20];
5050 };
5051
5052 enum {
5053         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5054         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5055         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5056         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5057         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5058 };
5059
5060 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5061         u8         opcode[0x10];
5062         u8         reserved_at_10[0x10];
5063
5064         u8         reserved_at_20[0x10];
5065         u8         op_mod[0x10];
5066
5067         u8         reserved_at_40[0xa0];
5068
5069         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5070 };
5071
5072 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5073         u8         status[0x8];
5074         u8         reserved_at_8[0x18];
5075
5076         u8         syndrome[0x20];
5077
5078         u8         reserved_at_40[0x40];
5079 };
5080
5081 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5082         u8         opcode[0x10];
5083         u8         reserved_at_10[0x10];
5084
5085         u8         reserved_20[0x10];
5086         u8         op_mod[0x10];
5087
5088         u8         packet_reformat_id[0x20];
5089
5090         u8         reserved_60[0x20];
5091 };
5092
5093 struct mlx5_ifc_set_action_in_bits {
5094         u8         action_type[0x4];
5095         u8         field[0xc];
5096         u8         reserved_at_10[0x3];
5097         u8         offset[0x5];
5098         u8         reserved_at_18[0x3];
5099         u8         length[0x5];
5100
5101         u8         data[0x20];
5102 };
5103
5104 struct mlx5_ifc_add_action_in_bits {
5105         u8         action_type[0x4];
5106         u8         field[0xc];
5107         u8         reserved_at_10[0x10];
5108
5109         u8         data[0x20];
5110 };
5111
5112 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5113         struct mlx5_ifc_set_action_in_bits set_action_in;
5114         struct mlx5_ifc_add_action_in_bits add_action_in;
5115         u8         reserved_at_0[0x40];
5116 };
5117
5118 enum {
5119         MLX5_ACTION_TYPE_SET   = 0x1,
5120         MLX5_ACTION_TYPE_ADD   = 0x2,
5121 };
5122
5123 enum {
5124         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5125         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5126         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5127         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5128         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5129         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5130         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5131         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5132         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5133         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5134         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5135         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5136         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5137         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5138         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5139         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5140         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5141         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5142         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5143         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5144         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5145         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5146         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5147 };
5148
5149 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5150         u8         status[0x8];
5151         u8         reserved_at_8[0x18];
5152
5153         u8         syndrome[0x20];
5154
5155         u8         modify_header_id[0x20];
5156
5157         u8         reserved_at_60[0x20];
5158 };
5159
5160 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5161         u8         opcode[0x10];
5162         u8         reserved_at_10[0x10];
5163
5164         u8         reserved_at_20[0x10];
5165         u8         op_mod[0x10];
5166
5167         u8         reserved_at_40[0x20];
5168
5169         u8         table_type[0x8];
5170         u8         reserved_at_68[0x10];
5171         u8         num_of_actions[0x8];
5172
5173         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5174 };
5175
5176 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5177         u8         status[0x8];
5178         u8         reserved_at_8[0x18];
5179
5180         u8         syndrome[0x20];
5181
5182         u8         reserved_at_40[0x40];
5183 };
5184
5185 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5186         u8         opcode[0x10];
5187         u8         reserved_at_10[0x10];
5188
5189         u8         reserved_at_20[0x10];
5190         u8         op_mod[0x10];
5191
5192         u8         modify_header_id[0x20];
5193
5194         u8         reserved_at_60[0x20];
5195 };
5196
5197 struct mlx5_ifc_query_dct_out_bits {
5198         u8         status[0x8];
5199         u8         reserved_at_8[0x18];
5200
5201         u8         syndrome[0x20];
5202
5203         u8         reserved_at_40[0x40];
5204
5205         struct mlx5_ifc_dctc_bits dct_context_entry;
5206
5207         u8         reserved_at_280[0x180];
5208 };
5209
5210 struct mlx5_ifc_query_dct_in_bits {
5211         u8         opcode[0x10];
5212         u8         reserved_at_10[0x10];
5213
5214         u8         reserved_at_20[0x10];
5215         u8         op_mod[0x10];
5216
5217         u8         reserved_at_40[0x8];
5218         u8         dctn[0x18];
5219
5220         u8         reserved_at_60[0x20];
5221 };
5222
5223 struct mlx5_ifc_query_cq_out_bits {
5224         u8         status[0x8];
5225         u8         reserved_at_8[0x18];
5226
5227         u8         syndrome[0x20];
5228
5229         u8         reserved_at_40[0x40];
5230
5231         struct mlx5_ifc_cqc_bits cq_context;
5232
5233         u8         reserved_at_280[0x600];
5234
5235         u8         pas[0][0x40];
5236 };
5237
5238 struct mlx5_ifc_query_cq_in_bits {
5239         u8         opcode[0x10];
5240         u8         reserved_at_10[0x10];
5241
5242         u8         reserved_at_20[0x10];
5243         u8         op_mod[0x10];
5244
5245         u8         reserved_at_40[0x8];
5246         u8         cqn[0x18];
5247
5248         u8         reserved_at_60[0x20];
5249 };
5250
5251 struct mlx5_ifc_query_cong_status_out_bits {
5252         u8         status[0x8];
5253         u8         reserved_at_8[0x18];
5254
5255         u8         syndrome[0x20];
5256
5257         u8         reserved_at_40[0x20];
5258
5259         u8         enable[0x1];
5260         u8         tag_enable[0x1];
5261         u8         reserved_at_62[0x1e];
5262 };
5263
5264 struct mlx5_ifc_query_cong_status_in_bits {
5265         u8         opcode[0x10];
5266         u8         reserved_at_10[0x10];
5267
5268         u8         reserved_at_20[0x10];
5269         u8         op_mod[0x10];
5270
5271         u8         reserved_at_40[0x18];
5272         u8         priority[0x4];
5273         u8         cong_protocol[0x4];
5274
5275         u8         reserved_at_60[0x20];
5276 };
5277
5278 struct mlx5_ifc_query_cong_statistics_out_bits {
5279         u8         status[0x8];
5280         u8         reserved_at_8[0x18];
5281
5282         u8         syndrome[0x20];
5283
5284         u8         reserved_at_40[0x40];
5285
5286         u8         rp_cur_flows[0x20];
5287
5288         u8         sum_flows[0x20];
5289
5290         u8         rp_cnp_ignored_high[0x20];
5291
5292         u8         rp_cnp_ignored_low[0x20];
5293
5294         u8         rp_cnp_handled_high[0x20];
5295
5296         u8         rp_cnp_handled_low[0x20];
5297
5298         u8         reserved_at_140[0x100];
5299
5300         u8         time_stamp_high[0x20];
5301
5302         u8         time_stamp_low[0x20];
5303
5304         u8         accumulators_period[0x20];
5305
5306         u8         np_ecn_marked_roce_packets_high[0x20];
5307
5308         u8         np_ecn_marked_roce_packets_low[0x20];
5309
5310         u8         np_cnp_sent_high[0x20];
5311
5312         u8         np_cnp_sent_low[0x20];
5313
5314         u8         reserved_at_320[0x560];
5315 };
5316
5317 struct mlx5_ifc_query_cong_statistics_in_bits {
5318         u8         opcode[0x10];
5319         u8         reserved_at_10[0x10];
5320
5321         u8         reserved_at_20[0x10];
5322         u8         op_mod[0x10];
5323
5324         u8         clear[0x1];
5325         u8         reserved_at_41[0x1f];
5326
5327         u8         reserved_at_60[0x20];
5328 };
5329
5330 struct mlx5_ifc_query_cong_params_out_bits {
5331         u8         status[0x8];
5332         u8         reserved_at_8[0x18];
5333
5334         u8         syndrome[0x20];
5335
5336         u8         reserved_at_40[0x40];
5337
5338         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5339 };
5340
5341 struct mlx5_ifc_query_cong_params_in_bits {
5342         u8         opcode[0x10];
5343         u8         reserved_at_10[0x10];
5344
5345         u8         reserved_at_20[0x10];
5346         u8         op_mod[0x10];
5347
5348         u8         reserved_at_40[0x1c];
5349         u8         cong_protocol[0x4];
5350
5351         u8         reserved_at_60[0x20];
5352 };
5353
5354 struct mlx5_ifc_query_adapter_out_bits {
5355         u8         status[0x8];
5356         u8         reserved_at_8[0x18];
5357
5358         u8         syndrome[0x20];
5359
5360         u8         reserved_at_40[0x40];
5361
5362         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5363 };
5364
5365 struct mlx5_ifc_query_adapter_in_bits {
5366         u8         opcode[0x10];
5367         u8         reserved_at_10[0x10];
5368
5369         u8         reserved_at_20[0x10];
5370         u8         op_mod[0x10];
5371
5372         u8         reserved_at_40[0x40];
5373 };
5374
5375 struct mlx5_ifc_qp_2rst_out_bits {
5376         u8         status[0x8];
5377         u8         reserved_at_8[0x18];
5378
5379         u8         syndrome[0x20];
5380
5381         u8         reserved_at_40[0x40];
5382 };
5383
5384 struct mlx5_ifc_qp_2rst_in_bits {
5385         u8         opcode[0x10];
5386         u8         uid[0x10];
5387
5388         u8         reserved_at_20[0x10];
5389         u8         op_mod[0x10];
5390
5391         u8         reserved_at_40[0x8];
5392         u8         qpn[0x18];
5393
5394         u8         reserved_at_60[0x20];
5395 };
5396
5397 struct mlx5_ifc_qp_2err_out_bits {
5398         u8         status[0x8];
5399         u8         reserved_at_8[0x18];
5400
5401         u8         syndrome[0x20];
5402
5403         u8         reserved_at_40[0x40];
5404 };
5405
5406 struct mlx5_ifc_qp_2err_in_bits {
5407         u8         opcode[0x10];
5408         u8         uid[0x10];
5409
5410         u8         reserved_at_20[0x10];
5411         u8         op_mod[0x10];
5412
5413         u8         reserved_at_40[0x8];
5414         u8         qpn[0x18];
5415
5416         u8         reserved_at_60[0x20];
5417 };
5418
5419 struct mlx5_ifc_page_fault_resume_out_bits {
5420         u8         status[0x8];
5421         u8         reserved_at_8[0x18];
5422
5423         u8         syndrome[0x20];
5424
5425         u8         reserved_at_40[0x40];
5426 };
5427
5428 struct mlx5_ifc_page_fault_resume_in_bits {
5429         u8         opcode[0x10];
5430         u8         reserved_at_10[0x10];
5431
5432         u8         reserved_at_20[0x10];
5433         u8         op_mod[0x10];
5434
5435         u8         error[0x1];
5436         u8         reserved_at_41[0x4];
5437         u8         page_fault_type[0x3];
5438         u8         wq_number[0x18];
5439
5440         u8         reserved_at_60[0x8];
5441         u8         token[0x18];
5442 };
5443
5444 struct mlx5_ifc_nop_out_bits {
5445         u8         status[0x8];
5446         u8         reserved_at_8[0x18];
5447
5448         u8         syndrome[0x20];
5449
5450         u8         reserved_at_40[0x40];
5451 };
5452
5453 struct mlx5_ifc_nop_in_bits {
5454         u8         opcode[0x10];
5455         u8         reserved_at_10[0x10];
5456
5457         u8         reserved_at_20[0x10];
5458         u8         op_mod[0x10];
5459
5460         u8         reserved_at_40[0x40];
5461 };
5462
5463 struct mlx5_ifc_modify_vport_state_out_bits {
5464         u8         status[0x8];
5465         u8         reserved_at_8[0x18];
5466
5467         u8         syndrome[0x20];
5468
5469         u8         reserved_at_40[0x40];
5470 };
5471
5472 struct mlx5_ifc_modify_vport_state_in_bits {
5473         u8         opcode[0x10];
5474         u8         reserved_at_10[0x10];
5475
5476         u8         reserved_at_20[0x10];
5477         u8         op_mod[0x10];
5478
5479         u8         other_vport[0x1];
5480         u8         reserved_at_41[0xf];
5481         u8         vport_number[0x10];
5482
5483         u8         reserved_at_60[0x18];
5484         u8         admin_state[0x4];
5485         u8         reserved_at_7c[0x4];
5486 };
5487
5488 struct mlx5_ifc_modify_tis_out_bits {
5489         u8         status[0x8];
5490         u8         reserved_at_8[0x18];
5491
5492         u8         syndrome[0x20];
5493
5494         u8         reserved_at_40[0x40];
5495 };
5496
5497 struct mlx5_ifc_modify_tis_bitmask_bits {
5498         u8         reserved_at_0[0x20];
5499
5500         u8         reserved_at_20[0x1d];
5501         u8         lag_tx_port_affinity[0x1];
5502         u8         strict_lag_tx_port_affinity[0x1];
5503         u8         prio[0x1];
5504 };
5505
5506 struct mlx5_ifc_modify_tis_in_bits {
5507         u8         opcode[0x10];
5508         u8         uid[0x10];
5509
5510         u8         reserved_at_20[0x10];
5511         u8         op_mod[0x10];
5512
5513         u8         reserved_at_40[0x8];
5514         u8         tisn[0x18];
5515
5516         u8         reserved_at_60[0x20];
5517
5518         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5519
5520         u8         reserved_at_c0[0x40];
5521
5522         struct mlx5_ifc_tisc_bits ctx;
5523 };
5524
5525 struct mlx5_ifc_modify_tir_bitmask_bits {
5526         u8         reserved_at_0[0x20];
5527
5528         u8         reserved_at_20[0x1b];
5529         u8         self_lb_en[0x1];
5530         u8         reserved_at_3c[0x1];
5531         u8         hash[0x1];
5532         u8         reserved_at_3e[0x1];
5533         u8         lro[0x1];
5534 };
5535
5536 struct mlx5_ifc_modify_tir_out_bits {
5537         u8         status[0x8];
5538         u8         reserved_at_8[0x18];
5539
5540         u8         syndrome[0x20];
5541
5542         u8         reserved_at_40[0x40];
5543 };
5544
5545 struct mlx5_ifc_modify_tir_in_bits {
5546         u8         opcode[0x10];
5547         u8         uid[0x10];
5548
5549         u8         reserved_at_20[0x10];
5550         u8         op_mod[0x10];
5551
5552         u8         reserved_at_40[0x8];
5553         u8         tirn[0x18];
5554
5555         u8         reserved_at_60[0x20];
5556
5557         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5558
5559         u8         reserved_at_c0[0x40];
5560
5561         struct mlx5_ifc_tirc_bits ctx;
5562 };
5563
5564 struct mlx5_ifc_modify_sq_out_bits {
5565         u8         status[0x8];
5566         u8         reserved_at_8[0x18];
5567
5568         u8         syndrome[0x20];
5569
5570         u8         reserved_at_40[0x40];
5571 };
5572
5573 struct mlx5_ifc_modify_sq_in_bits {
5574         u8         opcode[0x10];
5575         u8         uid[0x10];
5576
5577         u8         reserved_at_20[0x10];
5578         u8         op_mod[0x10];
5579
5580         u8         sq_state[0x4];
5581         u8         reserved_at_44[0x4];
5582         u8         sqn[0x18];
5583
5584         u8         reserved_at_60[0x20];
5585
5586         u8         modify_bitmask[0x40];
5587
5588         u8         reserved_at_c0[0x40];
5589
5590         struct mlx5_ifc_sqc_bits ctx;
5591 };
5592
5593 struct mlx5_ifc_modify_scheduling_element_out_bits {
5594         u8         status[0x8];
5595         u8         reserved_at_8[0x18];
5596
5597         u8         syndrome[0x20];
5598
5599         u8         reserved_at_40[0x1c0];
5600 };
5601
5602 enum {
5603         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5604         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5605 };
5606
5607 struct mlx5_ifc_modify_scheduling_element_in_bits {
5608         u8         opcode[0x10];
5609         u8         reserved_at_10[0x10];
5610
5611         u8         reserved_at_20[0x10];
5612         u8         op_mod[0x10];
5613
5614         u8         scheduling_hierarchy[0x8];
5615         u8         reserved_at_48[0x18];
5616
5617         u8         scheduling_element_id[0x20];
5618
5619         u8         reserved_at_80[0x20];
5620
5621         u8         modify_bitmask[0x20];
5622
5623         u8         reserved_at_c0[0x40];
5624
5625         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5626
5627         u8         reserved_at_300[0x100];
5628 };
5629
5630 struct mlx5_ifc_modify_rqt_out_bits {
5631         u8         status[0x8];
5632         u8         reserved_at_8[0x18];
5633
5634         u8         syndrome[0x20];
5635
5636         u8         reserved_at_40[0x40];
5637 };
5638
5639 struct mlx5_ifc_rqt_bitmask_bits {
5640         u8         reserved_at_0[0x20];
5641
5642         u8         reserved_at_20[0x1f];
5643         u8         rqn_list[0x1];
5644 };
5645
5646 struct mlx5_ifc_modify_rqt_in_bits {
5647         u8         opcode[0x10];
5648         u8         uid[0x10];
5649
5650         u8         reserved_at_20[0x10];
5651         u8         op_mod[0x10];
5652
5653         u8         reserved_at_40[0x8];
5654         u8         rqtn[0x18];
5655
5656         u8         reserved_at_60[0x20];
5657
5658         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5659
5660         u8         reserved_at_c0[0x40];
5661
5662         struct mlx5_ifc_rqtc_bits ctx;
5663 };
5664
5665 struct mlx5_ifc_modify_rq_out_bits {
5666         u8         status[0x8];
5667         u8         reserved_at_8[0x18];
5668
5669         u8         syndrome[0x20];
5670
5671         u8         reserved_at_40[0x40];
5672 };
5673
5674 enum {
5675         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5676         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5677         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5678 };
5679
5680 struct mlx5_ifc_modify_rq_in_bits {
5681         u8         opcode[0x10];
5682         u8         uid[0x10];
5683
5684         u8         reserved_at_20[0x10];
5685         u8         op_mod[0x10];
5686
5687         u8         rq_state[0x4];
5688         u8         reserved_at_44[0x4];
5689         u8         rqn[0x18];
5690
5691         u8         reserved_at_60[0x20];
5692
5693         u8         modify_bitmask[0x40];
5694
5695         u8         reserved_at_c0[0x40];
5696
5697         struct mlx5_ifc_rqc_bits ctx;
5698 };
5699
5700 struct mlx5_ifc_modify_rmp_out_bits {
5701         u8         status[0x8];
5702         u8         reserved_at_8[0x18];
5703
5704         u8         syndrome[0x20];
5705
5706         u8         reserved_at_40[0x40];
5707 };
5708
5709 struct mlx5_ifc_rmp_bitmask_bits {
5710         u8         reserved_at_0[0x20];
5711
5712         u8         reserved_at_20[0x1f];
5713         u8         lwm[0x1];
5714 };
5715
5716 struct mlx5_ifc_modify_rmp_in_bits {
5717         u8         opcode[0x10];
5718         u8         uid[0x10];
5719
5720         u8         reserved_at_20[0x10];
5721         u8         op_mod[0x10];
5722
5723         u8         rmp_state[0x4];
5724         u8         reserved_at_44[0x4];
5725         u8         rmpn[0x18];
5726
5727         u8         reserved_at_60[0x20];
5728
5729         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5730
5731         u8         reserved_at_c0[0x40];
5732
5733         struct mlx5_ifc_rmpc_bits ctx;
5734 };
5735
5736 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5737         u8         status[0x8];
5738         u8         reserved_at_8[0x18];
5739
5740         u8         syndrome[0x20];
5741
5742         u8         reserved_at_40[0x40];
5743 };
5744
5745 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5746         u8         reserved_at_0[0x12];
5747         u8         affiliation[0x1];
5748         u8         reserved_at_13[0x1];
5749         u8         disable_uc_local_lb[0x1];
5750         u8         disable_mc_local_lb[0x1];
5751         u8         node_guid[0x1];
5752         u8         port_guid[0x1];
5753         u8         min_inline[0x1];
5754         u8         mtu[0x1];
5755         u8         change_event[0x1];
5756         u8         promisc[0x1];
5757         u8         permanent_address[0x1];
5758         u8         addresses_list[0x1];
5759         u8         roce_en[0x1];
5760         u8         reserved_at_1f[0x1];
5761 };
5762
5763 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5764         u8         opcode[0x10];
5765         u8         reserved_at_10[0x10];
5766
5767         u8         reserved_at_20[0x10];
5768         u8         op_mod[0x10];
5769
5770         u8         other_vport[0x1];
5771         u8         reserved_at_41[0xf];
5772         u8         vport_number[0x10];
5773
5774         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5775
5776         u8         reserved_at_80[0x780];
5777
5778         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5779 };
5780
5781 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5782         u8         status[0x8];
5783         u8         reserved_at_8[0x18];
5784
5785         u8         syndrome[0x20];
5786
5787         u8         reserved_at_40[0x40];
5788 };
5789
5790 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5791         u8         opcode[0x10];
5792         u8         reserved_at_10[0x10];
5793
5794         u8         reserved_at_20[0x10];
5795         u8         op_mod[0x10];
5796
5797         u8         other_vport[0x1];
5798         u8         reserved_at_41[0xb];
5799         u8         port_num[0x4];
5800         u8         vport_number[0x10];
5801
5802         u8         reserved_at_60[0x20];
5803
5804         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5805 };
5806
5807 struct mlx5_ifc_modify_cq_out_bits {
5808         u8         status[0x8];
5809         u8         reserved_at_8[0x18];
5810
5811         u8         syndrome[0x20];
5812
5813         u8         reserved_at_40[0x40];
5814 };
5815
5816 enum {
5817         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5818         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5819 };
5820
5821 struct mlx5_ifc_modify_cq_in_bits {
5822         u8         opcode[0x10];
5823         u8         uid[0x10];
5824
5825         u8         reserved_at_20[0x10];
5826         u8         op_mod[0x10];
5827
5828         u8         reserved_at_40[0x8];
5829         u8         cqn[0x18];
5830
5831         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5832
5833         struct mlx5_ifc_cqc_bits cq_context;
5834
5835         u8         reserved_at_280[0x40];
5836
5837         u8         cq_umem_valid[0x1];
5838         u8         reserved_at_2c1[0x5bf];
5839
5840         u8         pas[0][0x40];
5841 };
5842
5843 struct mlx5_ifc_modify_cong_status_out_bits {
5844         u8         status[0x8];
5845         u8         reserved_at_8[0x18];
5846
5847         u8         syndrome[0x20];
5848
5849         u8         reserved_at_40[0x40];
5850 };
5851
5852 struct mlx5_ifc_modify_cong_status_in_bits {
5853         u8         opcode[0x10];
5854         u8         reserved_at_10[0x10];
5855
5856         u8         reserved_at_20[0x10];
5857         u8         op_mod[0x10];
5858
5859         u8         reserved_at_40[0x18];
5860         u8         priority[0x4];
5861         u8         cong_protocol[0x4];
5862
5863         u8         enable[0x1];
5864         u8         tag_enable[0x1];
5865         u8         reserved_at_62[0x1e];
5866 };
5867
5868 struct mlx5_ifc_modify_cong_params_out_bits {
5869         u8         status[0x8];
5870         u8         reserved_at_8[0x18];
5871
5872         u8         syndrome[0x20];
5873
5874         u8         reserved_at_40[0x40];
5875 };
5876
5877 struct mlx5_ifc_modify_cong_params_in_bits {
5878         u8         opcode[0x10];
5879         u8         reserved_at_10[0x10];
5880
5881         u8         reserved_at_20[0x10];
5882         u8         op_mod[0x10];
5883
5884         u8         reserved_at_40[0x1c];
5885         u8         cong_protocol[0x4];
5886
5887         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5888
5889         u8         reserved_at_80[0x80];
5890
5891         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5892 };
5893
5894 struct mlx5_ifc_manage_pages_out_bits {
5895         u8         status[0x8];
5896         u8         reserved_at_8[0x18];
5897
5898         u8         syndrome[0x20];
5899
5900         u8         output_num_entries[0x20];
5901
5902         u8         reserved_at_60[0x20];
5903
5904         u8         pas[0][0x40];
5905 };
5906
5907 enum {
5908         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5909         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5910         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5911 };
5912
5913 struct mlx5_ifc_manage_pages_in_bits {
5914         u8         opcode[0x10];
5915         u8         reserved_at_10[0x10];
5916
5917         u8         reserved_at_20[0x10];
5918         u8         op_mod[0x10];
5919
5920         u8         embedded_cpu_function[0x1];
5921         u8         reserved_at_41[0xf];
5922         u8         function_id[0x10];
5923
5924         u8         input_num_entries[0x20];
5925
5926         u8         pas[0][0x40];
5927 };
5928
5929 struct mlx5_ifc_mad_ifc_out_bits {
5930         u8         status[0x8];
5931         u8         reserved_at_8[0x18];
5932
5933         u8         syndrome[0x20];
5934
5935         u8         reserved_at_40[0x40];
5936
5937         u8         response_mad_packet[256][0x8];
5938 };
5939
5940 struct mlx5_ifc_mad_ifc_in_bits {
5941         u8         opcode[0x10];
5942         u8         reserved_at_10[0x10];
5943
5944         u8         reserved_at_20[0x10];
5945         u8         op_mod[0x10];
5946
5947         u8         remote_lid[0x10];
5948         u8         reserved_at_50[0x8];
5949         u8         port[0x8];
5950
5951         u8         reserved_at_60[0x20];
5952
5953         u8         mad[256][0x8];
5954 };
5955
5956 struct mlx5_ifc_init_hca_out_bits {
5957         u8         status[0x8];
5958         u8         reserved_at_8[0x18];
5959
5960         u8         syndrome[0x20];
5961
5962         u8         reserved_at_40[0x40];
5963 };
5964
5965 struct mlx5_ifc_init_hca_in_bits {
5966         u8         opcode[0x10];
5967         u8         reserved_at_10[0x10];
5968
5969         u8         reserved_at_20[0x10];
5970         u8         op_mod[0x10];
5971
5972         u8         reserved_at_40[0x40];
5973         u8         sw_owner_id[4][0x20];
5974 };
5975
5976 struct mlx5_ifc_init2rtr_qp_out_bits {
5977         u8         status[0x8];
5978         u8         reserved_at_8[0x18];
5979
5980         u8         syndrome[0x20];
5981
5982         u8         reserved_at_40[0x40];
5983 };
5984
5985 struct mlx5_ifc_init2rtr_qp_in_bits {
5986         u8         opcode[0x10];
5987         u8         uid[0x10];
5988
5989         u8         reserved_at_20[0x10];
5990         u8         op_mod[0x10];
5991
5992         u8         reserved_at_40[0x8];
5993         u8         qpn[0x18];
5994
5995         u8         reserved_at_60[0x20];
5996
5997         u8         opt_param_mask[0x20];
5998
5999         u8         reserved_at_a0[0x20];
6000
6001         struct mlx5_ifc_qpc_bits qpc;
6002
6003         u8         reserved_at_800[0x80];
6004 };
6005
6006 struct mlx5_ifc_init2init_qp_out_bits {
6007         u8         status[0x8];
6008         u8         reserved_at_8[0x18];
6009
6010         u8         syndrome[0x20];
6011
6012         u8         reserved_at_40[0x40];
6013 };
6014
6015 struct mlx5_ifc_init2init_qp_in_bits {
6016         u8         opcode[0x10];
6017         u8         uid[0x10];
6018
6019         u8         reserved_at_20[0x10];
6020         u8         op_mod[0x10];
6021
6022         u8         reserved_at_40[0x8];
6023         u8         qpn[0x18];
6024
6025         u8         reserved_at_60[0x20];
6026
6027         u8         opt_param_mask[0x20];
6028
6029         u8         reserved_at_a0[0x20];
6030
6031         struct mlx5_ifc_qpc_bits qpc;
6032
6033         u8         reserved_at_800[0x80];
6034 };
6035
6036 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6037         u8         status[0x8];
6038         u8         reserved_at_8[0x18];
6039
6040         u8         syndrome[0x20];
6041
6042         u8         reserved_at_40[0x40];
6043
6044         u8         packet_headers_log[128][0x8];
6045
6046         u8         packet_syndrome[64][0x8];
6047 };
6048
6049 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6050         u8         opcode[0x10];
6051         u8         reserved_at_10[0x10];
6052
6053         u8         reserved_at_20[0x10];
6054         u8         op_mod[0x10];
6055
6056         u8         reserved_at_40[0x40];
6057 };
6058
6059 struct mlx5_ifc_gen_eqe_in_bits {
6060         u8         opcode[0x10];
6061         u8         reserved_at_10[0x10];
6062
6063         u8         reserved_at_20[0x10];
6064         u8         op_mod[0x10];
6065
6066         u8         reserved_at_40[0x18];
6067         u8         eq_number[0x8];
6068
6069         u8         reserved_at_60[0x20];
6070
6071         u8         eqe[64][0x8];
6072 };
6073
6074 struct mlx5_ifc_gen_eq_out_bits {
6075         u8         status[0x8];
6076         u8         reserved_at_8[0x18];
6077
6078         u8         syndrome[0x20];
6079
6080         u8         reserved_at_40[0x40];
6081 };
6082
6083 struct mlx5_ifc_enable_hca_out_bits {
6084         u8         status[0x8];
6085         u8         reserved_at_8[0x18];
6086
6087         u8         syndrome[0x20];
6088
6089         u8         reserved_at_40[0x20];
6090 };
6091
6092 struct mlx5_ifc_enable_hca_in_bits {
6093         u8         opcode[0x10];
6094         u8         reserved_at_10[0x10];
6095
6096         u8         reserved_at_20[0x10];
6097         u8         op_mod[0x10];
6098
6099         u8         embedded_cpu_function[0x1];
6100         u8         reserved_at_41[0xf];
6101         u8         function_id[0x10];
6102
6103         u8         reserved_at_60[0x20];
6104 };
6105
6106 struct mlx5_ifc_drain_dct_out_bits {
6107         u8         status[0x8];
6108         u8         reserved_at_8[0x18];
6109
6110         u8         syndrome[0x20];
6111
6112         u8         reserved_at_40[0x40];
6113 };
6114
6115 struct mlx5_ifc_drain_dct_in_bits {
6116         u8         opcode[0x10];
6117         u8         uid[0x10];
6118
6119         u8         reserved_at_20[0x10];
6120         u8         op_mod[0x10];
6121
6122         u8         reserved_at_40[0x8];
6123         u8         dctn[0x18];
6124
6125         u8         reserved_at_60[0x20];
6126 };
6127
6128 struct mlx5_ifc_disable_hca_out_bits {
6129         u8         status[0x8];
6130         u8         reserved_at_8[0x18];
6131
6132         u8         syndrome[0x20];
6133
6134         u8         reserved_at_40[0x20];
6135 };
6136
6137 struct mlx5_ifc_disable_hca_in_bits {
6138         u8         opcode[0x10];
6139         u8         reserved_at_10[0x10];
6140
6141         u8         reserved_at_20[0x10];
6142         u8         op_mod[0x10];
6143
6144         u8         embedded_cpu_function[0x1];
6145         u8         reserved_at_41[0xf];
6146         u8         function_id[0x10];
6147
6148         u8         reserved_at_60[0x20];
6149 };
6150
6151 struct mlx5_ifc_detach_from_mcg_out_bits {
6152         u8         status[0x8];
6153         u8         reserved_at_8[0x18];
6154
6155         u8         syndrome[0x20];
6156
6157         u8         reserved_at_40[0x40];
6158 };
6159
6160 struct mlx5_ifc_detach_from_mcg_in_bits {
6161         u8         opcode[0x10];
6162         u8         uid[0x10];
6163
6164         u8         reserved_at_20[0x10];
6165         u8         op_mod[0x10];
6166
6167         u8         reserved_at_40[0x8];
6168         u8         qpn[0x18];
6169
6170         u8         reserved_at_60[0x20];
6171
6172         u8         multicast_gid[16][0x8];
6173 };
6174
6175 struct mlx5_ifc_destroy_xrq_out_bits {
6176         u8         status[0x8];
6177         u8         reserved_at_8[0x18];
6178
6179         u8         syndrome[0x20];
6180
6181         u8         reserved_at_40[0x40];
6182 };
6183
6184 struct mlx5_ifc_destroy_xrq_in_bits {
6185         u8         opcode[0x10];
6186         u8         uid[0x10];
6187
6188         u8         reserved_at_20[0x10];
6189         u8         op_mod[0x10];
6190
6191         u8         reserved_at_40[0x8];
6192         u8         xrqn[0x18];
6193
6194         u8         reserved_at_60[0x20];
6195 };
6196
6197 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6198         u8         status[0x8];
6199         u8         reserved_at_8[0x18];
6200
6201         u8         syndrome[0x20];
6202
6203         u8         reserved_at_40[0x40];
6204 };
6205
6206 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6207         u8         opcode[0x10];
6208         u8         uid[0x10];
6209
6210         u8         reserved_at_20[0x10];
6211         u8         op_mod[0x10];
6212
6213         u8         reserved_at_40[0x8];
6214         u8         xrc_srqn[0x18];
6215
6216         u8         reserved_at_60[0x20];
6217 };
6218
6219 struct mlx5_ifc_destroy_tis_out_bits {
6220         u8         status[0x8];
6221         u8         reserved_at_8[0x18];
6222
6223         u8         syndrome[0x20];
6224
6225         u8         reserved_at_40[0x40];
6226 };
6227
6228 struct mlx5_ifc_destroy_tis_in_bits {
6229         u8         opcode[0x10];
6230         u8         uid[0x10];
6231
6232         u8         reserved_at_20[0x10];
6233         u8         op_mod[0x10];
6234
6235         u8         reserved_at_40[0x8];
6236         u8         tisn[0x18];
6237
6238         u8         reserved_at_60[0x20];
6239 };
6240
6241 struct mlx5_ifc_destroy_tir_out_bits {
6242         u8         status[0x8];
6243         u8         reserved_at_8[0x18];
6244
6245         u8         syndrome[0x20];
6246
6247         u8         reserved_at_40[0x40];
6248 };
6249
6250 struct mlx5_ifc_destroy_tir_in_bits {
6251         u8         opcode[0x10];
6252         u8         uid[0x10];
6253
6254         u8         reserved_at_20[0x10];
6255         u8         op_mod[0x10];
6256
6257         u8         reserved_at_40[0x8];
6258         u8         tirn[0x18];
6259
6260         u8         reserved_at_60[0x20];
6261 };
6262
6263 struct mlx5_ifc_destroy_srq_out_bits {
6264         u8         status[0x8];
6265         u8         reserved_at_8[0x18];
6266
6267         u8         syndrome[0x20];
6268
6269         u8         reserved_at_40[0x40];
6270 };
6271
6272 struct mlx5_ifc_destroy_srq_in_bits {
6273         u8         opcode[0x10];
6274         u8         uid[0x10];
6275
6276         u8         reserved_at_20[0x10];
6277         u8         op_mod[0x10];
6278
6279         u8         reserved_at_40[0x8];
6280         u8         srqn[0x18];
6281
6282         u8         reserved_at_60[0x20];
6283 };
6284
6285 struct mlx5_ifc_destroy_sq_out_bits {
6286         u8         status[0x8];
6287         u8         reserved_at_8[0x18];
6288
6289         u8         syndrome[0x20];
6290
6291         u8         reserved_at_40[0x40];
6292 };
6293
6294 struct mlx5_ifc_destroy_sq_in_bits {
6295         u8         opcode[0x10];
6296         u8         uid[0x10];
6297
6298         u8         reserved_at_20[0x10];
6299         u8         op_mod[0x10];
6300
6301         u8         reserved_at_40[0x8];
6302         u8         sqn[0x18];
6303
6304         u8         reserved_at_60[0x20];
6305 };
6306
6307 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6308         u8         status[0x8];
6309         u8         reserved_at_8[0x18];
6310
6311         u8         syndrome[0x20];
6312
6313         u8         reserved_at_40[0x1c0];
6314 };
6315
6316 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6317         u8         opcode[0x10];
6318         u8         reserved_at_10[0x10];
6319
6320         u8         reserved_at_20[0x10];
6321         u8         op_mod[0x10];
6322
6323         u8         scheduling_hierarchy[0x8];
6324         u8         reserved_at_48[0x18];
6325
6326         u8         scheduling_element_id[0x20];
6327
6328         u8         reserved_at_80[0x180];
6329 };
6330
6331 struct mlx5_ifc_destroy_rqt_out_bits {
6332         u8         status[0x8];
6333         u8         reserved_at_8[0x18];
6334
6335         u8         syndrome[0x20];
6336
6337         u8         reserved_at_40[0x40];
6338 };
6339
6340 struct mlx5_ifc_destroy_rqt_in_bits {
6341         u8         opcode[0x10];
6342         u8         uid[0x10];
6343
6344         u8         reserved_at_20[0x10];
6345         u8         op_mod[0x10];
6346
6347         u8         reserved_at_40[0x8];
6348         u8         rqtn[0x18];
6349
6350         u8         reserved_at_60[0x20];
6351 };
6352
6353 struct mlx5_ifc_destroy_rq_out_bits {
6354         u8         status[0x8];
6355         u8         reserved_at_8[0x18];
6356
6357         u8         syndrome[0x20];
6358
6359         u8         reserved_at_40[0x40];
6360 };
6361
6362 struct mlx5_ifc_destroy_rq_in_bits {
6363         u8         opcode[0x10];
6364         u8         uid[0x10];
6365
6366         u8         reserved_at_20[0x10];
6367         u8         op_mod[0x10];
6368
6369         u8         reserved_at_40[0x8];
6370         u8         rqn[0x18];
6371
6372         u8         reserved_at_60[0x20];
6373 };
6374
6375 struct mlx5_ifc_set_delay_drop_params_in_bits {
6376         u8         opcode[0x10];
6377         u8         reserved_at_10[0x10];
6378
6379         u8         reserved_at_20[0x10];
6380         u8         op_mod[0x10];
6381
6382         u8         reserved_at_40[0x20];
6383
6384         u8         reserved_at_60[0x10];
6385         u8         delay_drop_timeout[0x10];
6386 };
6387
6388 struct mlx5_ifc_set_delay_drop_params_out_bits {
6389         u8         status[0x8];
6390         u8         reserved_at_8[0x18];
6391
6392         u8         syndrome[0x20];
6393
6394         u8         reserved_at_40[0x40];
6395 };
6396
6397 struct mlx5_ifc_destroy_rmp_out_bits {
6398         u8         status[0x8];
6399         u8         reserved_at_8[0x18];
6400
6401         u8         syndrome[0x20];
6402
6403         u8         reserved_at_40[0x40];
6404 };
6405
6406 struct mlx5_ifc_destroy_rmp_in_bits {
6407         u8         opcode[0x10];
6408         u8         uid[0x10];
6409
6410         u8         reserved_at_20[0x10];
6411         u8         op_mod[0x10];
6412
6413         u8         reserved_at_40[0x8];
6414         u8         rmpn[0x18];
6415
6416         u8         reserved_at_60[0x20];
6417 };
6418
6419 struct mlx5_ifc_destroy_qp_out_bits {
6420         u8         status[0x8];
6421         u8         reserved_at_8[0x18];
6422
6423         u8         syndrome[0x20];
6424
6425         u8         reserved_at_40[0x40];
6426 };
6427
6428 struct mlx5_ifc_destroy_qp_in_bits {
6429         u8         opcode[0x10];
6430         u8         uid[0x10];
6431
6432         u8         reserved_at_20[0x10];
6433         u8         op_mod[0x10];
6434
6435         u8         reserved_at_40[0x8];
6436         u8         qpn[0x18];
6437
6438         u8         reserved_at_60[0x20];
6439 };
6440
6441 struct mlx5_ifc_destroy_psv_out_bits {
6442         u8         status[0x8];
6443         u8         reserved_at_8[0x18];
6444
6445         u8         syndrome[0x20];
6446
6447         u8         reserved_at_40[0x40];
6448 };
6449
6450 struct mlx5_ifc_destroy_psv_in_bits {
6451         u8         opcode[0x10];
6452         u8         reserved_at_10[0x10];
6453
6454         u8         reserved_at_20[0x10];
6455         u8         op_mod[0x10];
6456
6457         u8         reserved_at_40[0x8];
6458         u8         psvn[0x18];
6459
6460         u8         reserved_at_60[0x20];
6461 };
6462
6463 struct mlx5_ifc_destroy_mkey_out_bits {
6464         u8         status[0x8];
6465         u8         reserved_at_8[0x18];
6466
6467         u8         syndrome[0x20];
6468
6469         u8         reserved_at_40[0x40];
6470 };
6471
6472 struct mlx5_ifc_destroy_mkey_in_bits {
6473         u8         opcode[0x10];
6474         u8         reserved_at_10[0x10];
6475
6476         u8         reserved_at_20[0x10];
6477         u8         op_mod[0x10];
6478
6479         u8         reserved_at_40[0x8];
6480         u8         mkey_index[0x18];
6481
6482         u8         reserved_at_60[0x20];
6483 };
6484
6485 struct mlx5_ifc_destroy_flow_table_out_bits {
6486         u8         status[0x8];
6487         u8         reserved_at_8[0x18];
6488
6489         u8         syndrome[0x20];
6490
6491         u8         reserved_at_40[0x40];
6492 };
6493
6494 struct mlx5_ifc_destroy_flow_table_in_bits {
6495         u8         opcode[0x10];
6496         u8         reserved_at_10[0x10];
6497
6498         u8         reserved_at_20[0x10];
6499         u8         op_mod[0x10];
6500
6501         u8         other_vport[0x1];
6502         u8         reserved_at_41[0xf];
6503         u8         vport_number[0x10];
6504
6505         u8         reserved_at_60[0x20];
6506
6507         u8         table_type[0x8];
6508         u8         reserved_at_88[0x18];
6509
6510         u8         reserved_at_a0[0x8];
6511         u8         table_id[0x18];
6512
6513         u8         reserved_at_c0[0x140];
6514 };
6515
6516 struct mlx5_ifc_destroy_flow_group_out_bits {
6517         u8         status[0x8];
6518         u8         reserved_at_8[0x18];
6519
6520         u8         syndrome[0x20];
6521
6522         u8         reserved_at_40[0x40];
6523 };
6524
6525 struct mlx5_ifc_destroy_flow_group_in_bits {
6526         u8         opcode[0x10];
6527         u8         reserved_at_10[0x10];
6528
6529         u8         reserved_at_20[0x10];
6530         u8         op_mod[0x10];
6531
6532         u8         other_vport[0x1];
6533         u8         reserved_at_41[0xf];
6534         u8         vport_number[0x10];
6535
6536         u8         reserved_at_60[0x20];
6537
6538         u8         table_type[0x8];
6539         u8         reserved_at_88[0x18];
6540
6541         u8         reserved_at_a0[0x8];
6542         u8         table_id[0x18];
6543
6544         u8         group_id[0x20];
6545
6546         u8         reserved_at_e0[0x120];
6547 };
6548
6549 struct mlx5_ifc_destroy_eq_out_bits {
6550         u8         status[0x8];
6551         u8         reserved_at_8[0x18];
6552
6553         u8         syndrome[0x20];
6554
6555         u8         reserved_at_40[0x40];
6556 };
6557
6558 struct mlx5_ifc_destroy_eq_in_bits {
6559         u8         opcode[0x10];
6560         u8         reserved_at_10[0x10];
6561
6562         u8         reserved_at_20[0x10];
6563         u8         op_mod[0x10];
6564
6565         u8         reserved_at_40[0x18];
6566         u8         eq_number[0x8];
6567
6568         u8         reserved_at_60[0x20];
6569 };
6570
6571 struct mlx5_ifc_destroy_dct_out_bits {
6572         u8         status[0x8];
6573         u8         reserved_at_8[0x18];
6574
6575         u8         syndrome[0x20];
6576
6577         u8         reserved_at_40[0x40];
6578 };
6579
6580 struct mlx5_ifc_destroy_dct_in_bits {
6581         u8         opcode[0x10];
6582         u8         uid[0x10];
6583
6584         u8         reserved_at_20[0x10];
6585         u8         op_mod[0x10];
6586
6587         u8         reserved_at_40[0x8];
6588         u8         dctn[0x18];
6589
6590         u8         reserved_at_60[0x20];
6591 };
6592
6593 struct mlx5_ifc_destroy_cq_out_bits {
6594         u8         status[0x8];
6595         u8         reserved_at_8[0x18];
6596
6597         u8         syndrome[0x20];
6598
6599         u8         reserved_at_40[0x40];
6600 };
6601
6602 struct mlx5_ifc_destroy_cq_in_bits {
6603         u8         opcode[0x10];
6604         u8         uid[0x10];
6605
6606         u8         reserved_at_20[0x10];
6607         u8         op_mod[0x10];
6608
6609         u8         reserved_at_40[0x8];
6610         u8         cqn[0x18];
6611
6612         u8         reserved_at_60[0x20];
6613 };
6614
6615 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6616         u8         status[0x8];
6617         u8         reserved_at_8[0x18];
6618
6619         u8         syndrome[0x20];
6620
6621         u8         reserved_at_40[0x40];
6622 };
6623
6624 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6625         u8         opcode[0x10];
6626         u8         reserved_at_10[0x10];
6627
6628         u8         reserved_at_20[0x10];
6629         u8         op_mod[0x10];
6630
6631         u8         reserved_at_40[0x20];
6632
6633         u8         reserved_at_60[0x10];
6634         u8         vxlan_udp_port[0x10];
6635 };
6636
6637 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6638         u8         status[0x8];
6639         u8         reserved_at_8[0x18];
6640
6641         u8         syndrome[0x20];
6642
6643         u8         reserved_at_40[0x40];
6644 };
6645
6646 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6647         u8         opcode[0x10];
6648         u8         reserved_at_10[0x10];
6649
6650         u8         reserved_at_20[0x10];
6651         u8         op_mod[0x10];
6652
6653         u8         reserved_at_40[0x60];
6654
6655         u8         reserved_at_a0[0x8];
6656         u8         table_index[0x18];
6657
6658         u8         reserved_at_c0[0x140];
6659 };
6660
6661 struct mlx5_ifc_delete_fte_out_bits {
6662         u8         status[0x8];
6663         u8         reserved_at_8[0x18];
6664
6665         u8         syndrome[0x20];
6666
6667         u8         reserved_at_40[0x40];
6668 };
6669
6670 struct mlx5_ifc_delete_fte_in_bits {
6671         u8         opcode[0x10];
6672         u8         reserved_at_10[0x10];
6673
6674         u8         reserved_at_20[0x10];
6675         u8         op_mod[0x10];
6676
6677         u8         other_vport[0x1];
6678         u8         reserved_at_41[0xf];
6679         u8         vport_number[0x10];
6680
6681         u8         reserved_at_60[0x20];
6682
6683         u8         table_type[0x8];
6684         u8         reserved_at_88[0x18];
6685
6686         u8         reserved_at_a0[0x8];
6687         u8         table_id[0x18];
6688
6689         u8         reserved_at_c0[0x40];
6690
6691         u8         flow_index[0x20];
6692
6693         u8         reserved_at_120[0xe0];
6694 };
6695
6696 struct mlx5_ifc_dealloc_xrcd_out_bits {
6697         u8         status[0x8];
6698         u8         reserved_at_8[0x18];
6699
6700         u8         syndrome[0x20];
6701
6702         u8         reserved_at_40[0x40];
6703 };
6704
6705 struct mlx5_ifc_dealloc_xrcd_in_bits {
6706         u8         opcode[0x10];
6707         u8         uid[0x10];
6708
6709         u8         reserved_at_20[0x10];
6710         u8         op_mod[0x10];
6711
6712         u8         reserved_at_40[0x8];
6713         u8         xrcd[0x18];
6714
6715         u8         reserved_at_60[0x20];
6716 };
6717
6718 struct mlx5_ifc_dealloc_uar_out_bits {
6719         u8         status[0x8];
6720         u8         reserved_at_8[0x18];
6721
6722         u8         syndrome[0x20];
6723
6724         u8         reserved_at_40[0x40];
6725 };
6726
6727 struct mlx5_ifc_dealloc_uar_in_bits {
6728         u8         opcode[0x10];
6729         u8         reserved_at_10[0x10];
6730
6731         u8         reserved_at_20[0x10];
6732         u8         op_mod[0x10];
6733
6734         u8         reserved_at_40[0x8];
6735         u8         uar[0x18];
6736
6737         u8         reserved_at_60[0x20];
6738 };
6739
6740 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6741         u8         status[0x8];
6742         u8         reserved_at_8[0x18];
6743
6744         u8         syndrome[0x20];
6745
6746         u8         reserved_at_40[0x40];
6747 };
6748
6749 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6750         u8         opcode[0x10];
6751         u8         uid[0x10];
6752
6753         u8         reserved_at_20[0x10];
6754         u8         op_mod[0x10];
6755
6756         u8         reserved_at_40[0x8];
6757         u8         transport_domain[0x18];
6758
6759         u8         reserved_at_60[0x20];
6760 };
6761
6762 struct mlx5_ifc_dealloc_q_counter_out_bits {
6763         u8         status[0x8];
6764         u8         reserved_at_8[0x18];
6765
6766         u8         syndrome[0x20];
6767
6768         u8         reserved_at_40[0x40];
6769 };
6770
6771 struct mlx5_ifc_dealloc_q_counter_in_bits {
6772         u8         opcode[0x10];
6773         u8         reserved_at_10[0x10];
6774
6775         u8         reserved_at_20[0x10];
6776         u8         op_mod[0x10];
6777
6778         u8         reserved_at_40[0x18];
6779         u8         counter_set_id[0x8];
6780
6781         u8         reserved_at_60[0x20];
6782 };
6783
6784 struct mlx5_ifc_dealloc_pd_out_bits {
6785         u8         status[0x8];
6786         u8         reserved_at_8[0x18];
6787
6788         u8         syndrome[0x20];
6789
6790         u8         reserved_at_40[0x40];
6791 };
6792
6793 struct mlx5_ifc_dealloc_pd_in_bits {
6794         u8         opcode[0x10];
6795         u8         uid[0x10];
6796
6797         u8         reserved_at_20[0x10];
6798         u8         op_mod[0x10];
6799
6800         u8         reserved_at_40[0x8];
6801         u8         pd[0x18];
6802
6803         u8         reserved_at_60[0x20];
6804 };
6805
6806 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6807         u8         status[0x8];
6808         u8         reserved_at_8[0x18];
6809
6810         u8         syndrome[0x20];
6811
6812         u8         reserved_at_40[0x40];
6813 };
6814
6815 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6816         u8         opcode[0x10];
6817         u8         reserved_at_10[0x10];
6818
6819         u8         reserved_at_20[0x10];
6820         u8         op_mod[0x10];
6821
6822         u8         flow_counter_id[0x20];
6823
6824         u8         reserved_at_60[0x20];
6825 };
6826
6827 struct mlx5_ifc_create_xrq_out_bits {
6828         u8         status[0x8];
6829         u8         reserved_at_8[0x18];
6830
6831         u8         syndrome[0x20];
6832
6833         u8         reserved_at_40[0x8];
6834         u8         xrqn[0x18];
6835
6836         u8         reserved_at_60[0x20];
6837 };
6838
6839 struct mlx5_ifc_create_xrq_in_bits {
6840         u8         opcode[0x10];
6841         u8         uid[0x10];
6842
6843         u8         reserved_at_20[0x10];
6844         u8         op_mod[0x10];
6845
6846         u8         reserved_at_40[0x40];
6847
6848         struct mlx5_ifc_xrqc_bits xrq_context;
6849 };
6850
6851 struct mlx5_ifc_create_xrc_srq_out_bits {
6852         u8         status[0x8];
6853         u8         reserved_at_8[0x18];
6854
6855         u8         syndrome[0x20];
6856
6857         u8         reserved_at_40[0x8];
6858         u8         xrc_srqn[0x18];
6859
6860         u8         reserved_at_60[0x20];
6861 };
6862
6863 struct mlx5_ifc_create_xrc_srq_in_bits {
6864         u8         opcode[0x10];
6865         u8         uid[0x10];
6866
6867         u8         reserved_at_20[0x10];
6868         u8         op_mod[0x10];
6869
6870         u8         reserved_at_40[0x40];
6871
6872         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6873
6874         u8         reserved_at_280[0x60];
6875
6876         u8         xrc_srq_umem_valid[0x1];
6877         u8         reserved_at_2e1[0x1f];
6878
6879         u8         reserved_at_300[0x580];
6880
6881         u8         pas[0][0x40];
6882 };
6883
6884 struct mlx5_ifc_create_tis_out_bits {
6885         u8         status[0x8];
6886         u8         reserved_at_8[0x18];
6887
6888         u8         syndrome[0x20];
6889
6890         u8         reserved_at_40[0x8];
6891         u8         tisn[0x18];
6892
6893         u8         reserved_at_60[0x20];
6894 };
6895
6896 struct mlx5_ifc_create_tis_in_bits {
6897         u8         opcode[0x10];
6898         u8         uid[0x10];
6899
6900         u8         reserved_at_20[0x10];
6901         u8         op_mod[0x10];
6902
6903         u8         reserved_at_40[0xc0];
6904
6905         struct mlx5_ifc_tisc_bits ctx;
6906 };
6907
6908 struct mlx5_ifc_create_tir_out_bits {
6909         u8         status[0x8];
6910         u8         icm_address_63_40[0x18];
6911
6912         u8         syndrome[0x20];
6913
6914         u8         icm_address_39_32[0x8];
6915         u8         tirn[0x18];
6916
6917         u8         icm_address_31_0[0x20];
6918 };
6919
6920 struct mlx5_ifc_create_tir_in_bits {
6921         u8         opcode[0x10];
6922         u8         uid[0x10];
6923
6924         u8         reserved_at_20[0x10];
6925         u8         op_mod[0x10];
6926
6927         u8         reserved_at_40[0xc0];
6928
6929         struct mlx5_ifc_tirc_bits ctx;
6930 };
6931
6932 struct mlx5_ifc_create_srq_out_bits {
6933         u8         status[0x8];
6934         u8         reserved_at_8[0x18];
6935
6936         u8         syndrome[0x20];
6937
6938         u8         reserved_at_40[0x8];
6939         u8         srqn[0x18];
6940
6941         u8         reserved_at_60[0x20];
6942 };
6943
6944 struct mlx5_ifc_create_srq_in_bits {
6945         u8         opcode[0x10];
6946         u8         uid[0x10];
6947
6948         u8         reserved_at_20[0x10];
6949         u8         op_mod[0x10];
6950
6951         u8         reserved_at_40[0x40];
6952
6953         struct mlx5_ifc_srqc_bits srq_context_entry;
6954
6955         u8         reserved_at_280[0x600];
6956
6957         u8         pas[0][0x40];
6958 };
6959
6960 struct mlx5_ifc_create_sq_out_bits {
6961         u8         status[0x8];
6962         u8         reserved_at_8[0x18];
6963
6964         u8         syndrome[0x20];
6965
6966         u8         reserved_at_40[0x8];
6967         u8         sqn[0x18];
6968
6969         u8         reserved_at_60[0x20];
6970 };
6971
6972 struct mlx5_ifc_create_sq_in_bits {
6973         u8         opcode[0x10];
6974         u8         uid[0x10];
6975
6976         u8         reserved_at_20[0x10];
6977         u8         op_mod[0x10];
6978
6979         u8         reserved_at_40[0xc0];
6980
6981         struct mlx5_ifc_sqc_bits ctx;
6982 };
6983
6984 struct mlx5_ifc_create_scheduling_element_out_bits {
6985         u8         status[0x8];
6986         u8         reserved_at_8[0x18];
6987
6988         u8         syndrome[0x20];
6989
6990         u8         reserved_at_40[0x40];
6991
6992         u8         scheduling_element_id[0x20];
6993
6994         u8         reserved_at_a0[0x160];
6995 };
6996
6997 struct mlx5_ifc_create_scheduling_element_in_bits {
6998         u8         opcode[0x10];
6999         u8         reserved_at_10[0x10];
7000
7001         u8         reserved_at_20[0x10];
7002         u8         op_mod[0x10];
7003
7004         u8         scheduling_hierarchy[0x8];
7005         u8         reserved_at_48[0x18];
7006
7007         u8         reserved_at_60[0xa0];
7008
7009         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7010
7011         u8         reserved_at_300[0x100];
7012 };
7013
7014 struct mlx5_ifc_create_rqt_out_bits {
7015         u8         status[0x8];
7016         u8         reserved_at_8[0x18];
7017
7018         u8         syndrome[0x20];
7019
7020         u8         reserved_at_40[0x8];
7021         u8         rqtn[0x18];
7022
7023         u8         reserved_at_60[0x20];
7024 };
7025
7026 struct mlx5_ifc_create_rqt_in_bits {
7027         u8         opcode[0x10];
7028         u8         uid[0x10];
7029
7030         u8         reserved_at_20[0x10];
7031         u8         op_mod[0x10];
7032
7033         u8         reserved_at_40[0xc0];
7034
7035         struct mlx5_ifc_rqtc_bits rqt_context;
7036 };
7037
7038 struct mlx5_ifc_create_rq_out_bits {
7039         u8         status[0x8];
7040         u8         reserved_at_8[0x18];
7041
7042         u8         syndrome[0x20];
7043
7044         u8         reserved_at_40[0x8];
7045         u8         rqn[0x18];
7046
7047         u8         reserved_at_60[0x20];
7048 };
7049
7050 struct mlx5_ifc_create_rq_in_bits {
7051         u8         opcode[0x10];
7052         u8         uid[0x10];
7053
7054         u8         reserved_at_20[0x10];
7055         u8         op_mod[0x10];
7056
7057         u8         reserved_at_40[0xc0];
7058
7059         struct mlx5_ifc_rqc_bits ctx;
7060 };
7061
7062 struct mlx5_ifc_create_rmp_out_bits {
7063         u8         status[0x8];
7064         u8         reserved_at_8[0x18];
7065
7066         u8         syndrome[0x20];
7067
7068         u8         reserved_at_40[0x8];
7069         u8         rmpn[0x18];
7070
7071         u8         reserved_at_60[0x20];
7072 };
7073
7074 struct mlx5_ifc_create_rmp_in_bits {
7075         u8         opcode[0x10];
7076         u8         uid[0x10];
7077
7078         u8         reserved_at_20[0x10];
7079         u8         op_mod[0x10];
7080
7081         u8         reserved_at_40[0xc0];
7082
7083         struct mlx5_ifc_rmpc_bits ctx;
7084 };
7085
7086 struct mlx5_ifc_create_qp_out_bits {
7087         u8         status[0x8];
7088         u8         reserved_at_8[0x18];
7089
7090         u8         syndrome[0x20];
7091
7092         u8         reserved_at_40[0x8];
7093         u8         qpn[0x18];
7094
7095         u8         reserved_at_60[0x20];
7096 };
7097
7098 struct mlx5_ifc_create_qp_in_bits {
7099         u8         opcode[0x10];
7100         u8         uid[0x10];
7101
7102         u8         reserved_at_20[0x10];
7103         u8         op_mod[0x10];
7104
7105         u8         reserved_at_40[0x40];
7106
7107         u8         opt_param_mask[0x20];
7108
7109         u8         reserved_at_a0[0x20];
7110
7111         struct mlx5_ifc_qpc_bits qpc;
7112
7113         u8         reserved_at_800[0x60];
7114
7115         u8         wq_umem_valid[0x1];
7116         u8         reserved_at_861[0x1f];
7117
7118         u8         pas[0][0x40];
7119 };
7120
7121 struct mlx5_ifc_create_psv_out_bits {
7122         u8         status[0x8];
7123         u8         reserved_at_8[0x18];
7124
7125         u8         syndrome[0x20];
7126
7127         u8         reserved_at_40[0x40];
7128
7129         u8         reserved_at_80[0x8];
7130         u8         psv0_index[0x18];
7131
7132         u8         reserved_at_a0[0x8];
7133         u8         psv1_index[0x18];
7134
7135         u8         reserved_at_c0[0x8];
7136         u8         psv2_index[0x18];
7137
7138         u8         reserved_at_e0[0x8];
7139         u8         psv3_index[0x18];
7140 };
7141
7142 struct mlx5_ifc_create_psv_in_bits {
7143         u8         opcode[0x10];
7144         u8         reserved_at_10[0x10];
7145
7146         u8         reserved_at_20[0x10];
7147         u8         op_mod[0x10];
7148
7149         u8         num_psv[0x4];
7150         u8         reserved_at_44[0x4];
7151         u8         pd[0x18];
7152
7153         u8         reserved_at_60[0x20];
7154 };
7155
7156 struct mlx5_ifc_create_mkey_out_bits {
7157         u8         status[0x8];
7158         u8         reserved_at_8[0x18];
7159
7160         u8         syndrome[0x20];
7161
7162         u8         reserved_at_40[0x8];
7163         u8         mkey_index[0x18];
7164
7165         u8         reserved_at_60[0x20];
7166 };
7167
7168 struct mlx5_ifc_create_mkey_in_bits {
7169         u8         opcode[0x10];
7170         u8         reserved_at_10[0x10];
7171
7172         u8         reserved_at_20[0x10];
7173         u8         op_mod[0x10];
7174
7175         u8         reserved_at_40[0x20];
7176
7177         u8         pg_access[0x1];
7178         u8         mkey_umem_valid[0x1];
7179         u8         reserved_at_62[0x1e];
7180
7181         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7182
7183         u8         reserved_at_280[0x80];
7184
7185         u8         translations_octword_actual_size[0x20];
7186
7187         u8         reserved_at_320[0x560];
7188
7189         u8         klm_pas_mtt[0][0x20];
7190 };
7191
7192 struct mlx5_ifc_create_flow_table_out_bits {
7193         u8         status[0x8];
7194         u8         reserved_at_8[0x18];
7195
7196         u8         syndrome[0x20];
7197
7198         u8         reserved_at_40[0x8];
7199         u8         table_id[0x18];
7200
7201         u8         reserved_at_60[0x20];
7202 };
7203
7204 struct mlx5_ifc_flow_table_context_bits {
7205         u8         reformat_en[0x1];
7206         u8         decap_en[0x1];
7207         u8         reserved_at_2[0x2];
7208         u8         table_miss_action[0x4];
7209         u8         level[0x8];
7210         u8         reserved_at_10[0x8];
7211         u8         log_size[0x8];
7212
7213         u8         reserved_at_20[0x8];
7214         u8         table_miss_id[0x18];
7215
7216         u8         reserved_at_40[0x8];
7217         u8         lag_master_next_table_id[0x18];
7218
7219         u8         reserved_at_60[0xe0];
7220 };
7221
7222 struct mlx5_ifc_create_flow_table_in_bits {
7223         u8         opcode[0x10];
7224         u8         reserved_at_10[0x10];
7225
7226         u8         reserved_at_20[0x10];
7227         u8         op_mod[0x10];
7228
7229         u8         other_vport[0x1];
7230         u8         reserved_at_41[0xf];
7231         u8         vport_number[0x10];
7232
7233         u8         reserved_at_60[0x20];
7234
7235         u8         table_type[0x8];
7236         u8         reserved_at_88[0x18];
7237
7238         u8         reserved_at_a0[0x20];
7239
7240         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7241 };
7242
7243 struct mlx5_ifc_create_flow_group_out_bits {
7244         u8         status[0x8];
7245         u8         reserved_at_8[0x18];
7246
7247         u8         syndrome[0x20];
7248
7249         u8         reserved_at_40[0x8];
7250         u8         group_id[0x18];
7251
7252         u8         reserved_at_60[0x20];
7253 };
7254
7255 enum {
7256         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7257         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7258         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7259         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7260 };
7261
7262 struct mlx5_ifc_create_flow_group_in_bits {
7263         u8         opcode[0x10];
7264         u8         reserved_at_10[0x10];
7265
7266         u8         reserved_at_20[0x10];
7267         u8         op_mod[0x10];
7268
7269         u8         other_vport[0x1];
7270         u8         reserved_at_41[0xf];
7271         u8         vport_number[0x10];
7272
7273         u8         reserved_at_60[0x20];
7274
7275         u8         table_type[0x8];
7276         u8         reserved_at_88[0x18];
7277
7278         u8         reserved_at_a0[0x8];
7279         u8         table_id[0x18];
7280
7281         u8         source_eswitch_owner_vhca_id_valid[0x1];
7282
7283         u8         reserved_at_c1[0x1f];
7284
7285         u8         start_flow_index[0x20];
7286
7287         u8         reserved_at_100[0x20];
7288
7289         u8         end_flow_index[0x20];
7290
7291         u8         reserved_at_140[0xa0];
7292
7293         u8         reserved_at_1e0[0x18];
7294         u8         match_criteria_enable[0x8];
7295
7296         struct mlx5_ifc_fte_match_param_bits match_criteria;
7297
7298         u8         reserved_at_1200[0xe00];
7299 };
7300
7301 struct mlx5_ifc_create_eq_out_bits {
7302         u8         status[0x8];
7303         u8         reserved_at_8[0x18];
7304
7305         u8         syndrome[0x20];
7306
7307         u8         reserved_at_40[0x18];
7308         u8         eq_number[0x8];
7309
7310         u8         reserved_at_60[0x20];
7311 };
7312
7313 struct mlx5_ifc_create_eq_in_bits {
7314         u8         opcode[0x10];
7315         u8         reserved_at_10[0x10];
7316
7317         u8         reserved_at_20[0x10];
7318         u8         op_mod[0x10];
7319
7320         u8         reserved_at_40[0x40];
7321
7322         struct mlx5_ifc_eqc_bits eq_context_entry;
7323
7324         u8         reserved_at_280[0x40];
7325
7326         u8         event_bitmask[0x40];
7327
7328         u8         reserved_at_300[0x580];
7329
7330         u8         pas[0][0x40];
7331 };
7332
7333 struct mlx5_ifc_create_dct_out_bits {
7334         u8         status[0x8];
7335         u8         reserved_at_8[0x18];
7336
7337         u8         syndrome[0x20];
7338
7339         u8         reserved_at_40[0x8];
7340         u8         dctn[0x18];
7341
7342         u8         reserved_at_60[0x20];
7343 };
7344
7345 struct mlx5_ifc_create_dct_in_bits {
7346         u8         opcode[0x10];
7347         u8         uid[0x10];
7348
7349         u8         reserved_at_20[0x10];
7350         u8         op_mod[0x10];
7351
7352         u8         reserved_at_40[0x40];
7353
7354         struct mlx5_ifc_dctc_bits dct_context_entry;
7355
7356         u8         reserved_at_280[0x180];
7357 };
7358
7359 struct mlx5_ifc_create_cq_out_bits {
7360         u8         status[0x8];
7361         u8         reserved_at_8[0x18];
7362
7363         u8         syndrome[0x20];
7364
7365         u8         reserved_at_40[0x8];
7366         u8         cqn[0x18];
7367
7368         u8         reserved_at_60[0x20];
7369 };
7370
7371 struct mlx5_ifc_create_cq_in_bits {
7372         u8         opcode[0x10];
7373         u8         uid[0x10];
7374
7375         u8         reserved_at_20[0x10];
7376         u8         op_mod[0x10];
7377
7378         u8         reserved_at_40[0x40];
7379
7380         struct mlx5_ifc_cqc_bits cq_context;
7381
7382         u8         reserved_at_280[0x60];
7383
7384         u8         cq_umem_valid[0x1];
7385         u8         reserved_at_2e1[0x59f];
7386
7387         u8         pas[0][0x40];
7388 };
7389
7390 struct mlx5_ifc_config_int_moderation_out_bits {
7391         u8         status[0x8];
7392         u8         reserved_at_8[0x18];
7393
7394         u8         syndrome[0x20];
7395
7396         u8         reserved_at_40[0x4];
7397         u8         min_delay[0xc];
7398         u8         int_vector[0x10];
7399
7400         u8         reserved_at_60[0x20];
7401 };
7402
7403 enum {
7404         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7405         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7406 };
7407
7408 struct mlx5_ifc_config_int_moderation_in_bits {
7409         u8         opcode[0x10];
7410         u8         reserved_at_10[0x10];
7411
7412         u8         reserved_at_20[0x10];
7413         u8         op_mod[0x10];
7414
7415         u8         reserved_at_40[0x4];
7416         u8         min_delay[0xc];
7417         u8         int_vector[0x10];
7418
7419         u8         reserved_at_60[0x20];
7420 };
7421
7422 struct mlx5_ifc_attach_to_mcg_out_bits {
7423         u8         status[0x8];
7424         u8         reserved_at_8[0x18];
7425
7426         u8         syndrome[0x20];
7427
7428         u8         reserved_at_40[0x40];
7429 };
7430
7431 struct mlx5_ifc_attach_to_mcg_in_bits {
7432         u8         opcode[0x10];
7433         u8         uid[0x10];
7434
7435         u8         reserved_at_20[0x10];
7436         u8         op_mod[0x10];
7437
7438         u8         reserved_at_40[0x8];
7439         u8         qpn[0x18];
7440
7441         u8         reserved_at_60[0x20];
7442
7443         u8         multicast_gid[16][0x8];
7444 };
7445
7446 struct mlx5_ifc_arm_xrq_out_bits {
7447         u8         status[0x8];
7448         u8         reserved_at_8[0x18];
7449
7450         u8         syndrome[0x20];
7451
7452         u8         reserved_at_40[0x40];
7453 };
7454
7455 struct mlx5_ifc_arm_xrq_in_bits {
7456         u8         opcode[0x10];
7457         u8         reserved_at_10[0x10];
7458
7459         u8         reserved_at_20[0x10];
7460         u8         op_mod[0x10];
7461
7462         u8         reserved_at_40[0x8];
7463         u8         xrqn[0x18];
7464
7465         u8         reserved_at_60[0x10];
7466         u8         lwm[0x10];
7467 };
7468
7469 struct mlx5_ifc_arm_xrc_srq_out_bits {
7470         u8         status[0x8];
7471         u8         reserved_at_8[0x18];
7472
7473         u8         syndrome[0x20];
7474
7475         u8         reserved_at_40[0x40];
7476 };
7477
7478 enum {
7479         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7480 };
7481
7482 struct mlx5_ifc_arm_xrc_srq_in_bits {
7483         u8         opcode[0x10];
7484         u8         uid[0x10];
7485
7486         u8         reserved_at_20[0x10];
7487         u8         op_mod[0x10];
7488
7489         u8         reserved_at_40[0x8];
7490         u8         xrc_srqn[0x18];
7491
7492         u8         reserved_at_60[0x10];
7493         u8         lwm[0x10];
7494 };
7495
7496 struct mlx5_ifc_arm_rq_out_bits {
7497         u8         status[0x8];
7498         u8         reserved_at_8[0x18];
7499
7500         u8         syndrome[0x20];
7501
7502         u8         reserved_at_40[0x40];
7503 };
7504
7505 enum {
7506         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7507         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7508 };
7509
7510 struct mlx5_ifc_arm_rq_in_bits {
7511         u8         opcode[0x10];
7512         u8         uid[0x10];
7513
7514         u8         reserved_at_20[0x10];
7515         u8         op_mod[0x10];
7516
7517         u8         reserved_at_40[0x8];
7518         u8         srq_number[0x18];
7519
7520         u8         reserved_at_60[0x10];
7521         u8         lwm[0x10];
7522 };
7523
7524 struct mlx5_ifc_arm_dct_out_bits {
7525         u8         status[0x8];
7526         u8         reserved_at_8[0x18];
7527
7528         u8         syndrome[0x20];
7529
7530         u8         reserved_at_40[0x40];
7531 };
7532
7533 struct mlx5_ifc_arm_dct_in_bits {
7534         u8         opcode[0x10];
7535         u8         reserved_at_10[0x10];
7536
7537         u8         reserved_at_20[0x10];
7538         u8         op_mod[0x10];
7539
7540         u8         reserved_at_40[0x8];
7541         u8         dct_number[0x18];
7542
7543         u8         reserved_at_60[0x20];
7544 };
7545
7546 struct mlx5_ifc_alloc_xrcd_out_bits {
7547         u8         status[0x8];
7548         u8         reserved_at_8[0x18];
7549
7550         u8         syndrome[0x20];
7551
7552         u8         reserved_at_40[0x8];
7553         u8         xrcd[0x18];
7554
7555         u8         reserved_at_60[0x20];
7556 };
7557
7558 struct mlx5_ifc_alloc_xrcd_in_bits {
7559         u8         opcode[0x10];
7560         u8         uid[0x10];
7561
7562         u8         reserved_at_20[0x10];
7563         u8         op_mod[0x10];
7564
7565         u8         reserved_at_40[0x40];
7566 };
7567
7568 struct mlx5_ifc_alloc_uar_out_bits {
7569         u8         status[0x8];
7570         u8         reserved_at_8[0x18];
7571
7572         u8         syndrome[0x20];
7573
7574         u8         reserved_at_40[0x8];
7575         u8         uar[0x18];
7576
7577         u8         reserved_at_60[0x20];
7578 };
7579
7580 struct mlx5_ifc_alloc_uar_in_bits {
7581         u8         opcode[0x10];
7582         u8         reserved_at_10[0x10];
7583
7584         u8         reserved_at_20[0x10];
7585         u8         op_mod[0x10];
7586
7587         u8         reserved_at_40[0x40];
7588 };
7589
7590 struct mlx5_ifc_alloc_transport_domain_out_bits {
7591         u8         status[0x8];
7592         u8         reserved_at_8[0x18];
7593
7594         u8         syndrome[0x20];
7595
7596         u8         reserved_at_40[0x8];
7597         u8         transport_domain[0x18];
7598
7599         u8         reserved_at_60[0x20];
7600 };
7601
7602 struct mlx5_ifc_alloc_transport_domain_in_bits {
7603         u8         opcode[0x10];
7604         u8         uid[0x10];
7605
7606         u8         reserved_at_20[0x10];
7607         u8         op_mod[0x10];
7608
7609         u8         reserved_at_40[0x40];
7610 };
7611
7612 struct mlx5_ifc_alloc_q_counter_out_bits {
7613         u8         status[0x8];
7614         u8         reserved_at_8[0x18];
7615
7616         u8         syndrome[0x20];
7617
7618         u8         reserved_at_40[0x18];
7619         u8         counter_set_id[0x8];
7620
7621         u8         reserved_at_60[0x20];
7622 };
7623
7624 struct mlx5_ifc_alloc_q_counter_in_bits {
7625         u8         opcode[0x10];
7626         u8         uid[0x10];
7627
7628         u8         reserved_at_20[0x10];
7629         u8         op_mod[0x10];
7630
7631         u8         reserved_at_40[0x40];
7632 };
7633
7634 struct mlx5_ifc_alloc_pd_out_bits {
7635         u8         status[0x8];
7636         u8         reserved_at_8[0x18];
7637
7638         u8         syndrome[0x20];
7639
7640         u8         reserved_at_40[0x8];
7641         u8         pd[0x18];
7642
7643         u8         reserved_at_60[0x20];
7644 };
7645
7646 struct mlx5_ifc_alloc_pd_in_bits {
7647         u8         opcode[0x10];
7648         u8         uid[0x10];
7649
7650         u8         reserved_at_20[0x10];
7651         u8         op_mod[0x10];
7652
7653         u8         reserved_at_40[0x40];
7654 };
7655
7656 struct mlx5_ifc_alloc_flow_counter_out_bits {
7657         u8         status[0x8];
7658         u8         reserved_at_8[0x18];
7659
7660         u8         syndrome[0x20];
7661
7662         u8         flow_counter_id[0x20];
7663
7664         u8         reserved_at_60[0x20];
7665 };
7666
7667 struct mlx5_ifc_alloc_flow_counter_in_bits {
7668         u8         opcode[0x10];
7669         u8         reserved_at_10[0x10];
7670
7671         u8         reserved_at_20[0x10];
7672         u8         op_mod[0x10];
7673
7674         u8         reserved_at_40[0x40];
7675 };
7676
7677 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7678         u8         status[0x8];
7679         u8         reserved_at_8[0x18];
7680
7681         u8         syndrome[0x20];
7682
7683         u8         reserved_at_40[0x40];
7684 };
7685
7686 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7687         u8         opcode[0x10];
7688         u8         reserved_at_10[0x10];
7689
7690         u8         reserved_at_20[0x10];
7691         u8         op_mod[0x10];
7692
7693         u8         reserved_at_40[0x20];
7694
7695         u8         reserved_at_60[0x10];
7696         u8         vxlan_udp_port[0x10];
7697 };
7698
7699 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7700         u8         status[0x8];
7701         u8         reserved_at_8[0x18];
7702
7703         u8         syndrome[0x20];
7704
7705         u8         reserved_at_40[0x40];
7706 };
7707
7708 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7709         u8         opcode[0x10];
7710         u8         reserved_at_10[0x10];
7711
7712         u8         reserved_at_20[0x10];
7713         u8         op_mod[0x10];
7714
7715         u8         reserved_at_40[0x10];
7716         u8         rate_limit_index[0x10];
7717
7718         u8         reserved_at_60[0x20];
7719
7720         u8         rate_limit[0x20];
7721
7722         u8         burst_upper_bound[0x20];
7723
7724         u8         reserved_at_c0[0x10];
7725         u8         typical_packet_size[0x10];
7726
7727         u8         reserved_at_e0[0x120];
7728 };
7729
7730 struct mlx5_ifc_access_register_out_bits {
7731         u8         status[0x8];
7732         u8         reserved_at_8[0x18];
7733
7734         u8         syndrome[0x20];
7735
7736         u8         reserved_at_40[0x40];
7737
7738         u8         register_data[0][0x20];
7739 };
7740
7741 enum {
7742         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7743         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7744 };
7745
7746 struct mlx5_ifc_access_register_in_bits {
7747         u8         opcode[0x10];
7748         u8         reserved_at_10[0x10];
7749
7750         u8         reserved_at_20[0x10];
7751         u8         op_mod[0x10];
7752
7753         u8         reserved_at_40[0x10];
7754         u8         register_id[0x10];
7755
7756         u8         argument[0x20];
7757
7758         u8         register_data[0][0x20];
7759 };
7760
7761 struct mlx5_ifc_sltp_reg_bits {
7762         u8         status[0x4];
7763         u8         version[0x4];
7764         u8         local_port[0x8];
7765         u8         pnat[0x2];
7766         u8         reserved_at_12[0x2];
7767         u8         lane[0x4];
7768         u8         reserved_at_18[0x8];
7769
7770         u8         reserved_at_20[0x20];
7771
7772         u8         reserved_at_40[0x7];
7773         u8         polarity[0x1];
7774         u8         ob_tap0[0x8];
7775         u8         ob_tap1[0x8];
7776         u8         ob_tap2[0x8];
7777
7778         u8         reserved_at_60[0xc];
7779         u8         ob_preemp_mode[0x4];
7780         u8         ob_reg[0x8];
7781         u8         ob_bias[0x8];
7782
7783         u8         reserved_at_80[0x20];
7784 };
7785
7786 struct mlx5_ifc_slrg_reg_bits {
7787         u8         status[0x4];
7788         u8         version[0x4];
7789         u8         local_port[0x8];
7790         u8         pnat[0x2];
7791         u8         reserved_at_12[0x2];
7792         u8         lane[0x4];
7793         u8         reserved_at_18[0x8];
7794
7795         u8         time_to_link_up[0x10];
7796         u8         reserved_at_30[0xc];
7797         u8         grade_lane_speed[0x4];
7798
7799         u8         grade_version[0x8];
7800         u8         grade[0x18];
7801
7802         u8         reserved_at_60[0x4];
7803         u8         height_grade_type[0x4];
7804         u8         height_grade[0x18];
7805
7806         u8         height_dz[0x10];
7807         u8         height_dv[0x10];
7808
7809         u8         reserved_at_a0[0x10];
7810         u8         height_sigma[0x10];
7811
7812         u8         reserved_at_c0[0x20];
7813
7814         u8         reserved_at_e0[0x4];
7815         u8         phase_grade_type[0x4];
7816         u8         phase_grade[0x18];
7817
7818         u8         reserved_at_100[0x8];
7819         u8         phase_eo_pos[0x8];
7820         u8         reserved_at_110[0x8];
7821         u8         phase_eo_neg[0x8];
7822
7823         u8         ffe_set_tested[0x10];
7824         u8         test_errors_per_lane[0x10];
7825 };
7826
7827 struct mlx5_ifc_pvlc_reg_bits {
7828         u8         reserved_at_0[0x8];
7829         u8         local_port[0x8];
7830         u8         reserved_at_10[0x10];
7831
7832         u8         reserved_at_20[0x1c];
7833         u8         vl_hw_cap[0x4];
7834
7835         u8         reserved_at_40[0x1c];
7836         u8         vl_admin[0x4];
7837
7838         u8         reserved_at_60[0x1c];
7839         u8         vl_operational[0x4];
7840 };
7841
7842 struct mlx5_ifc_pude_reg_bits {
7843         u8         swid[0x8];
7844         u8         local_port[0x8];
7845         u8         reserved_at_10[0x4];
7846         u8         admin_status[0x4];
7847         u8         reserved_at_18[0x4];
7848         u8         oper_status[0x4];
7849
7850         u8         reserved_at_20[0x60];
7851 };
7852
7853 struct mlx5_ifc_ptys_reg_bits {
7854         u8         reserved_at_0[0x1];
7855         u8         an_disable_admin[0x1];
7856         u8         an_disable_cap[0x1];
7857         u8         reserved_at_3[0x5];
7858         u8         local_port[0x8];
7859         u8         reserved_at_10[0xd];
7860         u8         proto_mask[0x3];
7861
7862         u8         an_status[0x4];
7863         u8         reserved_at_24[0x1c];
7864
7865         u8         ext_eth_proto_capability[0x20];
7866
7867         u8         eth_proto_capability[0x20];
7868
7869         u8         ib_link_width_capability[0x10];
7870         u8         ib_proto_capability[0x10];
7871
7872         u8         ext_eth_proto_admin[0x20];
7873
7874         u8         eth_proto_admin[0x20];
7875
7876         u8         ib_link_width_admin[0x10];
7877         u8         ib_proto_admin[0x10];
7878
7879         u8         ext_eth_proto_oper[0x20];
7880
7881         u8         eth_proto_oper[0x20];
7882
7883         u8         ib_link_width_oper[0x10];
7884         u8         ib_proto_oper[0x10];
7885
7886         u8         reserved_at_160[0x1c];
7887         u8         connector_type[0x4];
7888
7889         u8         eth_proto_lp_advertise[0x20];
7890
7891         u8         reserved_at_1a0[0x60];
7892 };
7893
7894 struct mlx5_ifc_mlcr_reg_bits {
7895         u8         reserved_at_0[0x8];
7896         u8         local_port[0x8];
7897         u8         reserved_at_10[0x20];
7898
7899         u8         beacon_duration[0x10];
7900         u8         reserved_at_40[0x10];
7901
7902         u8         beacon_remain[0x10];
7903 };
7904
7905 struct mlx5_ifc_ptas_reg_bits {
7906         u8         reserved_at_0[0x20];
7907
7908         u8         algorithm_options[0x10];
7909         u8         reserved_at_30[0x4];
7910         u8         repetitions_mode[0x4];
7911         u8         num_of_repetitions[0x8];
7912
7913         u8         grade_version[0x8];
7914         u8         height_grade_type[0x4];
7915         u8         phase_grade_type[0x4];
7916         u8         height_grade_weight[0x8];
7917         u8         phase_grade_weight[0x8];
7918
7919         u8         gisim_measure_bits[0x10];
7920         u8         adaptive_tap_measure_bits[0x10];
7921
7922         u8         ber_bath_high_error_threshold[0x10];
7923         u8         ber_bath_mid_error_threshold[0x10];
7924
7925         u8         ber_bath_low_error_threshold[0x10];
7926         u8         one_ratio_high_threshold[0x10];
7927
7928         u8         one_ratio_high_mid_threshold[0x10];
7929         u8         one_ratio_low_mid_threshold[0x10];
7930
7931         u8         one_ratio_low_threshold[0x10];
7932         u8         ndeo_error_threshold[0x10];
7933
7934         u8         mixer_offset_step_size[0x10];
7935         u8         reserved_at_110[0x8];
7936         u8         mix90_phase_for_voltage_bath[0x8];
7937
7938         u8         mixer_offset_start[0x10];
7939         u8         mixer_offset_end[0x10];
7940
7941         u8         reserved_at_140[0x15];
7942         u8         ber_test_time[0xb];
7943 };
7944
7945 struct mlx5_ifc_pspa_reg_bits {
7946         u8         swid[0x8];
7947         u8         local_port[0x8];
7948         u8         sub_port[0x8];
7949         u8         reserved_at_18[0x8];
7950
7951         u8         reserved_at_20[0x20];
7952 };
7953
7954 struct mlx5_ifc_pqdr_reg_bits {
7955         u8         reserved_at_0[0x8];
7956         u8         local_port[0x8];
7957         u8         reserved_at_10[0x5];
7958         u8         prio[0x3];
7959         u8         reserved_at_18[0x6];
7960         u8         mode[0x2];
7961
7962         u8         reserved_at_20[0x20];
7963
7964         u8         reserved_at_40[0x10];
7965         u8         min_threshold[0x10];
7966
7967         u8         reserved_at_60[0x10];
7968         u8         max_threshold[0x10];
7969
7970         u8         reserved_at_80[0x10];
7971         u8         mark_probability_denominator[0x10];
7972
7973         u8         reserved_at_a0[0x60];
7974 };
7975
7976 struct mlx5_ifc_ppsc_reg_bits {
7977         u8         reserved_at_0[0x8];
7978         u8         local_port[0x8];
7979         u8         reserved_at_10[0x10];
7980
7981         u8         reserved_at_20[0x60];
7982
7983         u8         reserved_at_80[0x1c];
7984         u8         wrps_admin[0x4];
7985
7986         u8         reserved_at_a0[0x1c];
7987         u8         wrps_status[0x4];
7988
7989         u8         reserved_at_c0[0x8];
7990         u8         up_threshold[0x8];
7991         u8         reserved_at_d0[0x8];
7992         u8         down_threshold[0x8];
7993
7994         u8         reserved_at_e0[0x20];
7995
7996         u8         reserved_at_100[0x1c];
7997         u8         srps_admin[0x4];
7998
7999         u8         reserved_at_120[0x1c];
8000         u8         srps_status[0x4];
8001
8002         u8         reserved_at_140[0x40];
8003 };
8004
8005 struct mlx5_ifc_pplr_reg_bits {
8006         u8         reserved_at_0[0x8];
8007         u8         local_port[0x8];
8008         u8         reserved_at_10[0x10];
8009
8010         u8         reserved_at_20[0x8];
8011         u8         lb_cap[0x8];
8012         u8         reserved_at_30[0x8];
8013         u8         lb_en[0x8];
8014 };
8015
8016 struct mlx5_ifc_pplm_reg_bits {
8017         u8         reserved_at_0[0x8];
8018         u8         local_port[0x8];
8019         u8         reserved_at_10[0x10];
8020
8021         u8         reserved_at_20[0x20];
8022
8023         u8         port_profile_mode[0x8];
8024         u8         static_port_profile[0x8];
8025         u8         active_port_profile[0x8];
8026         u8         reserved_at_58[0x8];
8027
8028         u8         retransmission_active[0x8];
8029         u8         fec_mode_active[0x18];
8030
8031         u8         rs_fec_correction_bypass_cap[0x4];
8032         u8         reserved_at_84[0x8];
8033         u8         fec_override_cap_56g[0x4];
8034         u8         fec_override_cap_100g[0x4];
8035         u8         fec_override_cap_50g[0x4];
8036         u8         fec_override_cap_25g[0x4];
8037         u8         fec_override_cap_10g_40g[0x4];
8038
8039         u8         rs_fec_correction_bypass_admin[0x4];
8040         u8         reserved_at_a4[0x8];
8041         u8         fec_override_admin_56g[0x4];
8042         u8         fec_override_admin_100g[0x4];
8043         u8         fec_override_admin_50g[0x4];
8044         u8         fec_override_admin_25g[0x4];
8045         u8         fec_override_admin_10g_40g[0x4];
8046 };
8047
8048 struct mlx5_ifc_ppcnt_reg_bits {
8049         u8         swid[0x8];
8050         u8         local_port[0x8];
8051         u8         pnat[0x2];
8052         u8         reserved_at_12[0x8];
8053         u8         grp[0x6];
8054
8055         u8         clr[0x1];
8056         u8         reserved_at_21[0x1c];
8057         u8         prio_tc[0x3];
8058
8059         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8060 };
8061
8062 struct mlx5_ifc_mpein_reg_bits {
8063         u8         reserved_at_0[0x2];
8064         u8         depth[0x6];
8065         u8         pcie_index[0x8];
8066         u8         node[0x8];
8067         u8         reserved_at_18[0x8];
8068
8069         u8         capability_mask[0x20];
8070
8071         u8         reserved_at_40[0x8];
8072         u8         link_width_enabled[0x8];
8073         u8         link_speed_enabled[0x10];
8074
8075         u8         lane0_physical_position[0x8];
8076         u8         link_width_active[0x8];
8077         u8         link_speed_active[0x10];
8078
8079         u8         num_of_pfs[0x10];
8080         u8         num_of_vfs[0x10];
8081
8082         u8         bdf0[0x10];
8083         u8         reserved_at_b0[0x10];
8084
8085         u8         max_read_request_size[0x4];
8086         u8         max_payload_size[0x4];
8087         u8         reserved_at_c8[0x5];
8088         u8         pwr_status[0x3];
8089         u8         port_type[0x4];
8090         u8         reserved_at_d4[0xb];
8091         u8         lane_reversal[0x1];
8092
8093         u8         reserved_at_e0[0x14];
8094         u8         pci_power[0xc];
8095
8096         u8         reserved_at_100[0x20];
8097
8098         u8         device_status[0x10];
8099         u8         port_state[0x8];
8100         u8         reserved_at_138[0x8];
8101
8102         u8         reserved_at_140[0x10];
8103         u8         receiver_detect_result[0x10];
8104
8105         u8         reserved_at_160[0x20];
8106 };
8107
8108 struct mlx5_ifc_mpcnt_reg_bits {
8109         u8         reserved_at_0[0x8];
8110         u8         pcie_index[0x8];
8111         u8         reserved_at_10[0xa];
8112         u8         grp[0x6];
8113
8114         u8         clr[0x1];
8115         u8         reserved_at_21[0x1f];
8116
8117         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8118 };
8119
8120 struct mlx5_ifc_ppad_reg_bits {
8121         u8         reserved_at_0[0x3];
8122         u8         single_mac[0x1];
8123         u8         reserved_at_4[0x4];
8124         u8         local_port[0x8];
8125         u8         mac_47_32[0x10];
8126
8127         u8         mac_31_0[0x20];
8128
8129         u8         reserved_at_40[0x40];
8130 };
8131
8132 struct mlx5_ifc_pmtu_reg_bits {
8133         u8         reserved_at_0[0x8];
8134         u8         local_port[0x8];
8135         u8         reserved_at_10[0x10];
8136
8137         u8         max_mtu[0x10];
8138         u8         reserved_at_30[0x10];
8139
8140         u8         admin_mtu[0x10];
8141         u8         reserved_at_50[0x10];
8142
8143         u8         oper_mtu[0x10];
8144         u8         reserved_at_70[0x10];
8145 };
8146
8147 struct mlx5_ifc_pmpr_reg_bits {
8148         u8         reserved_at_0[0x8];
8149         u8         module[0x8];
8150         u8         reserved_at_10[0x10];
8151
8152         u8         reserved_at_20[0x18];
8153         u8         attenuation_5g[0x8];
8154
8155         u8         reserved_at_40[0x18];
8156         u8         attenuation_7g[0x8];
8157
8158         u8         reserved_at_60[0x18];
8159         u8         attenuation_12g[0x8];
8160 };
8161
8162 struct mlx5_ifc_pmpe_reg_bits {
8163         u8         reserved_at_0[0x8];
8164         u8         module[0x8];
8165         u8         reserved_at_10[0xc];
8166         u8         module_status[0x4];
8167
8168         u8         reserved_at_20[0x60];
8169 };
8170
8171 struct mlx5_ifc_pmpc_reg_bits {
8172         u8         module_state_updated[32][0x8];
8173 };
8174
8175 struct mlx5_ifc_pmlpn_reg_bits {
8176         u8         reserved_at_0[0x4];
8177         u8         mlpn_status[0x4];
8178         u8         local_port[0x8];
8179         u8         reserved_at_10[0x10];
8180
8181         u8         e[0x1];
8182         u8         reserved_at_21[0x1f];
8183 };
8184
8185 struct mlx5_ifc_pmlp_reg_bits {
8186         u8         rxtx[0x1];
8187         u8         reserved_at_1[0x7];
8188         u8         local_port[0x8];
8189         u8         reserved_at_10[0x8];
8190         u8         width[0x8];
8191
8192         u8         lane0_module_mapping[0x20];
8193
8194         u8         lane1_module_mapping[0x20];
8195
8196         u8         lane2_module_mapping[0x20];
8197
8198         u8         lane3_module_mapping[0x20];
8199
8200         u8         reserved_at_a0[0x160];
8201 };
8202
8203 struct mlx5_ifc_pmaos_reg_bits {
8204         u8         reserved_at_0[0x8];
8205         u8         module[0x8];
8206         u8         reserved_at_10[0x4];
8207         u8         admin_status[0x4];
8208         u8         reserved_at_18[0x4];
8209         u8         oper_status[0x4];
8210
8211         u8         ase[0x1];
8212         u8         ee[0x1];
8213         u8         reserved_at_22[0x1c];
8214         u8         e[0x2];
8215
8216         u8         reserved_at_40[0x40];
8217 };
8218
8219 struct mlx5_ifc_plpc_reg_bits {
8220         u8         reserved_at_0[0x4];
8221         u8         profile_id[0xc];
8222         u8         reserved_at_10[0x4];
8223         u8         proto_mask[0x4];
8224         u8         reserved_at_18[0x8];
8225
8226         u8         reserved_at_20[0x10];
8227         u8         lane_speed[0x10];
8228
8229         u8         reserved_at_40[0x17];
8230         u8         lpbf[0x1];
8231         u8         fec_mode_policy[0x8];
8232
8233         u8         retransmission_capability[0x8];
8234         u8         fec_mode_capability[0x18];
8235
8236         u8         retransmission_support_admin[0x8];
8237         u8         fec_mode_support_admin[0x18];
8238
8239         u8         retransmission_request_admin[0x8];
8240         u8         fec_mode_request_admin[0x18];
8241
8242         u8         reserved_at_c0[0x80];
8243 };
8244
8245 struct mlx5_ifc_plib_reg_bits {
8246         u8         reserved_at_0[0x8];
8247         u8         local_port[0x8];
8248         u8         reserved_at_10[0x8];
8249         u8         ib_port[0x8];
8250
8251         u8         reserved_at_20[0x60];
8252 };
8253
8254 struct mlx5_ifc_plbf_reg_bits {
8255         u8         reserved_at_0[0x8];
8256         u8         local_port[0x8];
8257         u8         reserved_at_10[0xd];
8258         u8         lbf_mode[0x3];
8259
8260         u8         reserved_at_20[0x20];
8261 };
8262
8263 struct mlx5_ifc_pipg_reg_bits {
8264         u8         reserved_at_0[0x8];
8265         u8         local_port[0x8];
8266         u8         reserved_at_10[0x10];
8267
8268         u8         dic[0x1];
8269         u8         reserved_at_21[0x19];
8270         u8         ipg[0x4];
8271         u8         reserved_at_3e[0x2];
8272 };
8273
8274 struct mlx5_ifc_pifr_reg_bits {
8275         u8         reserved_at_0[0x8];
8276         u8         local_port[0x8];
8277         u8         reserved_at_10[0x10];
8278
8279         u8         reserved_at_20[0xe0];
8280
8281         u8         port_filter[8][0x20];
8282
8283         u8         port_filter_update_en[8][0x20];
8284 };
8285
8286 struct mlx5_ifc_pfcc_reg_bits {
8287         u8         reserved_at_0[0x8];
8288         u8         local_port[0x8];
8289         u8         reserved_at_10[0xb];
8290         u8         ppan_mask_n[0x1];
8291         u8         minor_stall_mask[0x1];
8292         u8         critical_stall_mask[0x1];
8293         u8         reserved_at_1e[0x2];
8294
8295         u8         ppan[0x4];
8296         u8         reserved_at_24[0x4];
8297         u8         prio_mask_tx[0x8];
8298         u8         reserved_at_30[0x8];
8299         u8         prio_mask_rx[0x8];
8300
8301         u8         pptx[0x1];
8302         u8         aptx[0x1];
8303         u8         pptx_mask_n[0x1];
8304         u8         reserved_at_43[0x5];
8305         u8         pfctx[0x8];
8306         u8         reserved_at_50[0x10];
8307
8308         u8         pprx[0x1];
8309         u8         aprx[0x1];
8310         u8         pprx_mask_n[0x1];
8311         u8         reserved_at_63[0x5];
8312         u8         pfcrx[0x8];
8313         u8         reserved_at_70[0x10];
8314
8315         u8         device_stall_minor_watermark[0x10];
8316         u8         device_stall_critical_watermark[0x10];
8317
8318         u8         reserved_at_a0[0x60];
8319 };
8320
8321 struct mlx5_ifc_pelc_reg_bits {
8322         u8         op[0x4];
8323         u8         reserved_at_4[0x4];
8324         u8         local_port[0x8];
8325         u8         reserved_at_10[0x10];
8326
8327         u8         op_admin[0x8];
8328         u8         op_capability[0x8];
8329         u8         op_request[0x8];
8330         u8         op_active[0x8];
8331
8332         u8         admin[0x40];
8333
8334         u8         capability[0x40];
8335
8336         u8         request[0x40];
8337
8338         u8         active[0x40];
8339
8340         u8         reserved_at_140[0x80];
8341 };
8342
8343 struct mlx5_ifc_peir_reg_bits {
8344         u8         reserved_at_0[0x8];
8345         u8         local_port[0x8];
8346         u8         reserved_at_10[0x10];
8347
8348         u8         reserved_at_20[0xc];
8349         u8         error_count[0x4];
8350         u8         reserved_at_30[0x10];
8351
8352         u8         reserved_at_40[0xc];
8353         u8         lane[0x4];
8354         u8         reserved_at_50[0x8];
8355         u8         error_type[0x8];
8356 };
8357
8358 struct mlx5_ifc_mpegc_reg_bits {
8359         u8         reserved_at_0[0x30];
8360         u8         field_select[0x10];
8361
8362         u8         tx_overflow_sense[0x1];
8363         u8         mark_cqe[0x1];
8364         u8         mark_cnp[0x1];
8365         u8         reserved_at_43[0x1b];
8366         u8         tx_lossy_overflow_oper[0x2];
8367
8368         u8         reserved_at_60[0x100];
8369 };
8370
8371 struct mlx5_ifc_pcam_enhanced_features_bits {
8372         u8         reserved_at_0[0x6d];
8373         u8         rx_icrc_encapsulated_counter[0x1];
8374         u8         reserved_at_6e[0x4];
8375         u8         ptys_extended_ethernet[0x1];
8376         u8         reserved_at_73[0x3];
8377         u8         pfcc_mask[0x1];
8378         u8         reserved_at_77[0x3];
8379         u8         per_lane_error_counters[0x1];
8380         u8         rx_buffer_fullness_counters[0x1];
8381         u8         ptys_connector_type[0x1];
8382         u8         reserved_at_7d[0x1];
8383         u8         ppcnt_discard_group[0x1];
8384         u8         ppcnt_statistical_group[0x1];
8385 };
8386
8387 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8388         u8         port_access_reg_cap_mask_127_to_96[0x20];
8389         u8         port_access_reg_cap_mask_95_to_64[0x20];
8390
8391         u8         port_access_reg_cap_mask_63_to_36[0x1c];
8392         u8         pplm[0x1];
8393         u8         port_access_reg_cap_mask_34_to_32[0x3];
8394
8395         u8         port_access_reg_cap_mask_31_to_13[0x13];
8396         u8         pbmc[0x1];
8397         u8         pptb[0x1];
8398         u8         port_access_reg_cap_mask_10_to_09[0x2];
8399         u8         ppcnt[0x1];
8400         u8         port_access_reg_cap_mask_07_to_00[0x8];
8401 };
8402
8403 struct mlx5_ifc_pcam_reg_bits {
8404         u8         reserved_at_0[0x8];
8405         u8         feature_group[0x8];
8406         u8         reserved_at_10[0x8];
8407         u8         access_reg_group[0x8];
8408
8409         u8         reserved_at_20[0x20];
8410
8411         union {
8412                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8413                 u8         reserved_at_0[0x80];
8414         } port_access_reg_cap_mask;
8415
8416         u8         reserved_at_c0[0x80];
8417
8418         union {
8419                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8420                 u8         reserved_at_0[0x80];
8421         } feature_cap_mask;
8422
8423         u8         reserved_at_1c0[0xc0];
8424 };
8425
8426 struct mlx5_ifc_mcam_enhanced_features_bits {
8427         u8         reserved_at_0[0x6e];
8428         u8         pci_status_and_power[0x1];
8429         u8         reserved_at_6f[0x5];
8430         u8         mark_tx_action_cnp[0x1];
8431         u8         mark_tx_action_cqe[0x1];
8432         u8         dynamic_tx_overflow[0x1];
8433         u8         reserved_at_77[0x4];
8434         u8         pcie_outbound_stalled[0x1];
8435         u8         tx_overflow_buffer_pkt[0x1];
8436         u8         mtpps_enh_out_per_adj[0x1];
8437         u8         mtpps_fs[0x1];
8438         u8         pcie_performance_group[0x1];
8439 };
8440
8441 struct mlx5_ifc_mcam_access_reg_bits {
8442         u8         reserved_at_0[0x1c];
8443         u8         mcda[0x1];
8444         u8         mcc[0x1];
8445         u8         mcqi[0x1];
8446         u8         reserved_at_1f[0x1];
8447
8448         u8         regs_95_to_87[0x9];
8449         u8         mpegc[0x1];
8450         u8         regs_85_to_68[0x12];
8451         u8         tracer_registers[0x4];
8452
8453         u8         regs_63_to_32[0x20];
8454         u8         regs_31_to_0[0x20];
8455 };
8456
8457 struct mlx5_ifc_mcam_reg_bits {
8458         u8         reserved_at_0[0x8];
8459         u8         feature_group[0x8];
8460         u8         reserved_at_10[0x8];
8461         u8         access_reg_group[0x8];
8462
8463         u8         reserved_at_20[0x20];
8464
8465         union {
8466                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8467                 u8         reserved_at_0[0x80];
8468         } mng_access_reg_cap_mask;
8469
8470         u8         reserved_at_c0[0x80];
8471
8472         union {
8473                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8474                 u8         reserved_at_0[0x80];
8475         } mng_feature_cap_mask;
8476
8477         u8         reserved_at_1c0[0x80];
8478 };
8479
8480 struct mlx5_ifc_qcam_access_reg_cap_mask {
8481         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8482         u8         qpdpm[0x1];
8483         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8484         u8         qdpm[0x1];
8485         u8         qpts[0x1];
8486         u8         qcap[0x1];
8487         u8         qcam_access_reg_cap_mask_0[0x1];
8488 };
8489
8490 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8491         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8492         u8         qpts_trust_both[0x1];
8493 };
8494
8495 struct mlx5_ifc_qcam_reg_bits {
8496         u8         reserved_at_0[0x8];
8497         u8         feature_group[0x8];
8498         u8         reserved_at_10[0x8];
8499         u8         access_reg_group[0x8];
8500         u8         reserved_at_20[0x20];
8501
8502         union {
8503                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8504                 u8  reserved_at_0[0x80];
8505         } qos_access_reg_cap_mask;
8506
8507         u8         reserved_at_c0[0x80];
8508
8509         union {
8510                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8511                 u8  reserved_at_0[0x80];
8512         } qos_feature_cap_mask;
8513
8514         u8         reserved_at_1c0[0x80];
8515 };
8516
8517 struct mlx5_ifc_pcap_reg_bits {
8518         u8         reserved_at_0[0x8];
8519         u8         local_port[0x8];
8520         u8         reserved_at_10[0x10];
8521
8522         u8         port_capability_mask[4][0x20];
8523 };
8524
8525 struct mlx5_ifc_paos_reg_bits {
8526         u8         swid[0x8];
8527         u8         local_port[0x8];
8528         u8         reserved_at_10[0x4];
8529         u8         admin_status[0x4];
8530         u8         reserved_at_18[0x4];
8531         u8         oper_status[0x4];
8532
8533         u8         ase[0x1];
8534         u8         ee[0x1];
8535         u8         reserved_at_22[0x1c];
8536         u8         e[0x2];
8537
8538         u8         reserved_at_40[0x40];
8539 };
8540
8541 struct mlx5_ifc_pamp_reg_bits {
8542         u8         reserved_at_0[0x8];
8543         u8         opamp_group[0x8];
8544         u8         reserved_at_10[0xc];
8545         u8         opamp_group_type[0x4];
8546
8547         u8         start_index[0x10];
8548         u8         reserved_at_30[0x4];
8549         u8         num_of_indices[0xc];
8550
8551         u8         index_data[18][0x10];
8552 };
8553
8554 struct mlx5_ifc_pcmr_reg_bits {
8555         u8         reserved_at_0[0x8];
8556         u8         local_port[0x8];
8557         u8         reserved_at_10[0x10];
8558         u8         entropy_force_cap[0x1];
8559         u8         entropy_calc_cap[0x1];
8560         u8         entropy_gre_calc_cap[0x1];
8561         u8         reserved_at_23[0x1b];
8562         u8         fcs_cap[0x1];
8563         u8         reserved_at_3f[0x1];
8564         u8         entropy_force[0x1];
8565         u8         entropy_calc[0x1];
8566         u8         entropy_gre_calc[0x1];
8567         u8         reserved_at_43[0x1b];
8568         u8         fcs_chk[0x1];
8569         u8         reserved_at_5f[0x1];
8570 };
8571
8572 struct mlx5_ifc_lane_2_module_mapping_bits {
8573         u8         reserved_at_0[0x6];
8574         u8         rx_lane[0x2];
8575         u8         reserved_at_8[0x6];
8576         u8         tx_lane[0x2];
8577         u8         reserved_at_10[0x8];
8578         u8         module[0x8];
8579 };
8580
8581 struct mlx5_ifc_bufferx_reg_bits {
8582         u8         reserved_at_0[0x6];
8583         u8         lossy[0x1];
8584         u8         epsb[0x1];
8585         u8         reserved_at_8[0xc];
8586         u8         size[0xc];
8587
8588         u8         xoff_threshold[0x10];
8589         u8         xon_threshold[0x10];
8590 };
8591
8592 struct mlx5_ifc_set_node_in_bits {
8593         u8         node_description[64][0x8];
8594 };
8595
8596 struct mlx5_ifc_register_power_settings_bits {
8597         u8         reserved_at_0[0x18];
8598         u8         power_settings_level[0x8];
8599
8600         u8         reserved_at_20[0x60];
8601 };
8602
8603 struct mlx5_ifc_register_host_endianness_bits {
8604         u8         he[0x1];
8605         u8         reserved_at_1[0x1f];
8606
8607         u8         reserved_at_20[0x60];
8608 };
8609
8610 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8611         u8         reserved_at_0[0x20];
8612
8613         u8         mkey[0x20];
8614
8615         u8         addressh_63_32[0x20];
8616
8617         u8         addressl_31_0[0x20];
8618 };
8619
8620 struct mlx5_ifc_ud_adrs_vector_bits {
8621         u8         dc_key[0x40];
8622
8623         u8         ext[0x1];
8624         u8         reserved_at_41[0x7];
8625         u8         destination_qp_dct[0x18];
8626
8627         u8         static_rate[0x4];
8628         u8         sl_eth_prio[0x4];
8629         u8         fl[0x1];
8630         u8         mlid[0x7];
8631         u8         rlid_udp_sport[0x10];
8632
8633         u8         reserved_at_80[0x20];
8634
8635         u8         rmac_47_16[0x20];
8636
8637         u8         rmac_15_0[0x10];
8638         u8         tclass[0x8];
8639         u8         hop_limit[0x8];
8640
8641         u8         reserved_at_e0[0x1];
8642         u8         grh[0x1];
8643         u8         reserved_at_e2[0x2];
8644         u8         src_addr_index[0x8];
8645         u8         flow_label[0x14];
8646
8647         u8         rgid_rip[16][0x8];
8648 };
8649
8650 struct mlx5_ifc_pages_req_event_bits {
8651         u8         reserved_at_0[0x10];
8652         u8         function_id[0x10];
8653
8654         u8         num_pages[0x20];
8655
8656         u8         reserved_at_40[0xa0];
8657 };
8658
8659 struct mlx5_ifc_eqe_bits {
8660         u8         reserved_at_0[0x8];
8661         u8         event_type[0x8];
8662         u8         reserved_at_10[0x8];
8663         u8         event_sub_type[0x8];
8664
8665         u8         reserved_at_20[0xe0];
8666
8667         union mlx5_ifc_event_auto_bits event_data;
8668
8669         u8         reserved_at_1e0[0x10];
8670         u8         signature[0x8];
8671         u8         reserved_at_1f8[0x7];
8672         u8         owner[0x1];
8673 };
8674
8675 enum {
8676         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8677 };
8678
8679 struct mlx5_ifc_cmd_queue_entry_bits {
8680         u8         type[0x8];
8681         u8         reserved_at_8[0x18];
8682
8683         u8         input_length[0x20];
8684
8685         u8         input_mailbox_pointer_63_32[0x20];
8686
8687         u8         input_mailbox_pointer_31_9[0x17];
8688         u8         reserved_at_77[0x9];
8689
8690         u8         command_input_inline_data[16][0x8];
8691
8692         u8         command_output_inline_data[16][0x8];
8693
8694         u8         output_mailbox_pointer_63_32[0x20];
8695
8696         u8         output_mailbox_pointer_31_9[0x17];
8697         u8         reserved_at_1b7[0x9];
8698
8699         u8         output_length[0x20];
8700
8701         u8         token[0x8];
8702         u8         signature[0x8];
8703         u8         reserved_at_1f0[0x8];
8704         u8         status[0x7];
8705         u8         ownership[0x1];
8706 };
8707
8708 struct mlx5_ifc_cmd_out_bits {
8709         u8         status[0x8];
8710         u8         reserved_at_8[0x18];
8711
8712         u8         syndrome[0x20];
8713
8714         u8         command_output[0x20];
8715 };
8716
8717 struct mlx5_ifc_cmd_in_bits {
8718         u8         opcode[0x10];
8719         u8         reserved_at_10[0x10];
8720
8721         u8         reserved_at_20[0x10];
8722         u8         op_mod[0x10];
8723
8724         u8         command[0][0x20];
8725 };
8726
8727 struct mlx5_ifc_cmd_if_box_bits {
8728         u8         mailbox_data[512][0x8];
8729
8730         u8         reserved_at_1000[0x180];
8731
8732         u8         next_pointer_63_32[0x20];
8733
8734         u8         next_pointer_31_10[0x16];
8735         u8         reserved_at_11b6[0xa];
8736
8737         u8         block_number[0x20];
8738
8739         u8         reserved_at_11e0[0x8];
8740         u8         token[0x8];
8741         u8         ctrl_signature[0x8];
8742         u8         signature[0x8];
8743 };
8744
8745 struct mlx5_ifc_mtt_bits {
8746         u8         ptag_63_32[0x20];
8747
8748         u8         ptag_31_8[0x18];
8749         u8         reserved_at_38[0x6];
8750         u8         wr_en[0x1];
8751         u8         rd_en[0x1];
8752 };
8753
8754 struct mlx5_ifc_query_wol_rol_out_bits {
8755         u8         status[0x8];
8756         u8         reserved_at_8[0x18];
8757
8758         u8         syndrome[0x20];
8759
8760         u8         reserved_at_40[0x10];
8761         u8         rol_mode[0x8];
8762         u8         wol_mode[0x8];
8763
8764         u8         reserved_at_60[0x20];
8765 };
8766
8767 struct mlx5_ifc_query_wol_rol_in_bits {
8768         u8         opcode[0x10];
8769         u8         reserved_at_10[0x10];
8770
8771         u8         reserved_at_20[0x10];
8772         u8         op_mod[0x10];
8773
8774         u8         reserved_at_40[0x40];
8775 };
8776
8777 struct mlx5_ifc_set_wol_rol_out_bits {
8778         u8         status[0x8];
8779         u8         reserved_at_8[0x18];
8780
8781         u8         syndrome[0x20];
8782
8783         u8         reserved_at_40[0x40];
8784 };
8785
8786 struct mlx5_ifc_set_wol_rol_in_bits {
8787         u8         opcode[0x10];
8788         u8         reserved_at_10[0x10];
8789
8790         u8         reserved_at_20[0x10];
8791         u8         op_mod[0x10];
8792
8793         u8         rol_mode_valid[0x1];
8794         u8         wol_mode_valid[0x1];
8795         u8         reserved_at_42[0xe];
8796         u8         rol_mode[0x8];
8797         u8         wol_mode[0x8];
8798
8799         u8         reserved_at_60[0x20];
8800 };
8801
8802 enum {
8803         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8804         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8805         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8806 };
8807
8808 enum {
8809         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8810         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8811         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8812 };
8813
8814 enum {
8815         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8816         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8817         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8818         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8819         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8820         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8821         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8822         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8823         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8824         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8825         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8826 };
8827
8828 struct mlx5_ifc_initial_seg_bits {
8829         u8         fw_rev_minor[0x10];
8830         u8         fw_rev_major[0x10];
8831
8832         u8         cmd_interface_rev[0x10];
8833         u8         fw_rev_subminor[0x10];
8834
8835         u8         reserved_at_40[0x40];
8836
8837         u8         cmdq_phy_addr_63_32[0x20];
8838
8839         u8         cmdq_phy_addr_31_12[0x14];
8840         u8         reserved_at_b4[0x2];
8841         u8         nic_interface[0x2];
8842         u8         log_cmdq_size[0x4];
8843         u8         log_cmdq_stride[0x4];
8844
8845         u8         command_doorbell_vector[0x20];
8846
8847         u8         reserved_at_e0[0xf00];
8848
8849         u8         initializing[0x1];
8850         u8         reserved_at_fe1[0x4];
8851         u8         nic_interface_supported[0x3];
8852         u8         embedded_cpu[0x1];
8853         u8         reserved_at_fe9[0x17];
8854
8855         struct mlx5_ifc_health_buffer_bits health_buffer;
8856
8857         u8         no_dram_nic_offset[0x20];
8858
8859         u8         reserved_at_1220[0x6e40];
8860
8861         u8         reserved_at_8060[0x1f];
8862         u8         clear_int[0x1];
8863
8864         u8         health_syndrome[0x8];
8865         u8         health_counter[0x18];
8866
8867         u8         reserved_at_80a0[0x17fc0];
8868 };
8869
8870 struct mlx5_ifc_mtpps_reg_bits {
8871         u8         reserved_at_0[0xc];
8872         u8         cap_number_of_pps_pins[0x4];
8873         u8         reserved_at_10[0x4];
8874         u8         cap_max_num_of_pps_in_pins[0x4];
8875         u8         reserved_at_18[0x4];
8876         u8         cap_max_num_of_pps_out_pins[0x4];
8877
8878         u8         reserved_at_20[0x24];
8879         u8         cap_pin_3_mode[0x4];
8880         u8         reserved_at_48[0x4];
8881         u8         cap_pin_2_mode[0x4];
8882         u8         reserved_at_50[0x4];
8883         u8         cap_pin_1_mode[0x4];
8884         u8         reserved_at_58[0x4];
8885         u8         cap_pin_0_mode[0x4];
8886
8887         u8         reserved_at_60[0x4];
8888         u8         cap_pin_7_mode[0x4];
8889         u8         reserved_at_68[0x4];
8890         u8         cap_pin_6_mode[0x4];
8891         u8         reserved_at_70[0x4];
8892         u8         cap_pin_5_mode[0x4];
8893         u8         reserved_at_78[0x4];
8894         u8         cap_pin_4_mode[0x4];
8895
8896         u8         field_select[0x20];
8897         u8         reserved_at_a0[0x60];
8898
8899         u8         enable[0x1];
8900         u8         reserved_at_101[0xb];
8901         u8         pattern[0x4];
8902         u8         reserved_at_110[0x4];
8903         u8         pin_mode[0x4];
8904         u8         pin[0x8];
8905
8906         u8         reserved_at_120[0x20];
8907
8908         u8         time_stamp[0x40];
8909
8910         u8         out_pulse_duration[0x10];
8911         u8         out_periodic_adjustment[0x10];
8912         u8         enhanced_out_periodic_adjustment[0x20];
8913
8914         u8         reserved_at_1c0[0x20];
8915 };
8916
8917 struct mlx5_ifc_mtppse_reg_bits {
8918         u8         reserved_at_0[0x18];
8919         u8         pin[0x8];
8920         u8         event_arm[0x1];
8921         u8         reserved_at_21[0x1b];
8922         u8         event_generation_mode[0x4];
8923         u8         reserved_at_40[0x40];
8924 };
8925
8926 struct mlx5_ifc_mcqi_cap_bits {
8927         u8         supported_info_bitmask[0x20];
8928
8929         u8         component_size[0x20];
8930
8931         u8         max_component_size[0x20];
8932
8933         u8         log_mcda_word_size[0x4];
8934         u8         reserved_at_64[0xc];
8935         u8         mcda_max_write_size[0x10];
8936
8937         u8         rd_en[0x1];
8938         u8         reserved_at_81[0x1];
8939         u8         match_chip_id[0x1];
8940         u8         match_psid[0x1];
8941         u8         check_user_timestamp[0x1];
8942         u8         match_base_guid_mac[0x1];
8943         u8         reserved_at_86[0x1a];
8944 };
8945
8946 struct mlx5_ifc_mcqi_reg_bits {
8947         u8         read_pending_component[0x1];
8948         u8         reserved_at_1[0xf];
8949         u8         component_index[0x10];
8950
8951         u8         reserved_at_20[0x20];
8952
8953         u8         reserved_at_40[0x1b];
8954         u8         info_type[0x5];
8955
8956         u8         info_size[0x20];
8957
8958         u8         offset[0x20];
8959
8960         u8         reserved_at_a0[0x10];
8961         u8         data_size[0x10];
8962
8963         u8         data[0][0x20];
8964 };
8965
8966 struct mlx5_ifc_mcc_reg_bits {
8967         u8         reserved_at_0[0x4];
8968         u8         time_elapsed_since_last_cmd[0xc];
8969         u8         reserved_at_10[0x8];
8970         u8         instruction[0x8];
8971
8972         u8         reserved_at_20[0x10];
8973         u8         component_index[0x10];
8974
8975         u8         reserved_at_40[0x8];
8976         u8         update_handle[0x18];
8977
8978         u8         handle_owner_type[0x4];
8979         u8         handle_owner_host_id[0x4];
8980         u8         reserved_at_68[0x1];
8981         u8         control_progress[0x7];
8982         u8         error_code[0x8];
8983         u8         reserved_at_78[0x4];
8984         u8         control_state[0x4];
8985
8986         u8         component_size[0x20];
8987
8988         u8         reserved_at_a0[0x60];
8989 };
8990
8991 struct mlx5_ifc_mcda_reg_bits {
8992         u8         reserved_at_0[0x8];
8993         u8         update_handle[0x18];
8994
8995         u8         offset[0x20];
8996
8997         u8         reserved_at_40[0x10];
8998         u8         size[0x10];
8999
9000         u8         reserved_at_60[0x20];
9001
9002         u8         data[0][0x20];
9003 };
9004
9005 union mlx5_ifc_ports_control_registers_document_bits {
9006         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9007         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9008         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9009         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9010         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9011         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9012         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9013         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
9014         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9015         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9016         struct mlx5_ifc_paos_reg_bits paos_reg;
9017         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9018         struct mlx5_ifc_peir_reg_bits peir_reg;
9019         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9020         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9021         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9022         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9023         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9024         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9025         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9026         struct mlx5_ifc_plib_reg_bits plib_reg;
9027         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9028         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9029         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9030         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9031         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9032         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9033         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9034         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9035         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9036         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9037         struct mlx5_ifc_mpein_reg_bits mpein_reg;
9038         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9039         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9040         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9041         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9042         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9043         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9044         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9045         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9046         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9047         struct mlx5_ifc_pude_reg_bits pude_reg;
9048         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9049         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9050         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9051         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9052         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9053         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9054         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9055         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9056         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9057         struct mlx5_ifc_mcc_reg_bits mcc_reg;
9058         struct mlx5_ifc_mcda_reg_bits mcda_reg;
9059         u8         reserved_at_0[0x60e0];
9060 };
9061
9062 union mlx5_ifc_debug_enhancements_document_bits {
9063         struct mlx5_ifc_health_buffer_bits health_buffer;
9064         u8         reserved_at_0[0x200];
9065 };
9066
9067 union mlx5_ifc_uplink_pci_interface_document_bits {
9068         struct mlx5_ifc_initial_seg_bits initial_seg;
9069         u8         reserved_at_0[0x20060];
9070 };
9071
9072 struct mlx5_ifc_set_flow_table_root_out_bits {
9073         u8         status[0x8];
9074         u8         reserved_at_8[0x18];
9075
9076         u8         syndrome[0x20];
9077
9078         u8         reserved_at_40[0x40];
9079 };
9080
9081 struct mlx5_ifc_set_flow_table_root_in_bits {
9082         u8         opcode[0x10];
9083         u8         reserved_at_10[0x10];
9084
9085         u8         reserved_at_20[0x10];
9086         u8         op_mod[0x10];
9087
9088         u8         other_vport[0x1];
9089         u8         reserved_at_41[0xf];
9090         u8         vport_number[0x10];
9091
9092         u8         reserved_at_60[0x20];
9093
9094         u8         table_type[0x8];
9095         u8         reserved_at_88[0x18];
9096
9097         u8         reserved_at_a0[0x8];
9098         u8         table_id[0x18];
9099
9100         u8         reserved_at_c0[0x8];
9101         u8         underlay_qpn[0x18];
9102         u8         reserved_at_e0[0x120];
9103 };
9104
9105 enum {
9106         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
9107         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9108 };
9109
9110 struct mlx5_ifc_modify_flow_table_out_bits {
9111         u8         status[0x8];
9112         u8         reserved_at_8[0x18];
9113
9114         u8         syndrome[0x20];
9115
9116         u8         reserved_at_40[0x40];
9117 };
9118
9119 struct mlx5_ifc_modify_flow_table_in_bits {
9120         u8         opcode[0x10];
9121         u8         reserved_at_10[0x10];
9122
9123         u8         reserved_at_20[0x10];
9124         u8         op_mod[0x10];
9125
9126         u8         other_vport[0x1];
9127         u8         reserved_at_41[0xf];
9128         u8         vport_number[0x10];
9129
9130         u8         reserved_at_60[0x10];
9131         u8         modify_field_select[0x10];
9132
9133         u8         table_type[0x8];
9134         u8         reserved_at_88[0x18];
9135
9136         u8         reserved_at_a0[0x8];
9137         u8         table_id[0x18];
9138
9139         struct mlx5_ifc_flow_table_context_bits flow_table_context;
9140 };
9141
9142 struct mlx5_ifc_ets_tcn_config_reg_bits {
9143         u8         g[0x1];
9144         u8         b[0x1];
9145         u8         r[0x1];
9146         u8         reserved_at_3[0x9];
9147         u8         group[0x4];
9148         u8         reserved_at_10[0x9];
9149         u8         bw_allocation[0x7];
9150
9151         u8         reserved_at_20[0xc];
9152         u8         max_bw_units[0x4];
9153         u8         reserved_at_30[0x8];
9154         u8         max_bw_value[0x8];
9155 };
9156
9157 struct mlx5_ifc_ets_global_config_reg_bits {
9158         u8         reserved_at_0[0x2];
9159         u8         r[0x1];
9160         u8         reserved_at_3[0x1d];
9161
9162         u8         reserved_at_20[0xc];
9163         u8         max_bw_units[0x4];
9164         u8         reserved_at_30[0x8];
9165         u8         max_bw_value[0x8];
9166 };
9167
9168 struct mlx5_ifc_qetc_reg_bits {
9169         u8                                         reserved_at_0[0x8];
9170         u8                                         port_number[0x8];
9171         u8                                         reserved_at_10[0x30];
9172
9173         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9174         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9175 };
9176
9177 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9178         u8         e[0x1];
9179         u8         reserved_at_01[0x0b];
9180         u8         prio[0x04];
9181 };
9182
9183 struct mlx5_ifc_qpdpm_reg_bits {
9184         u8                                     reserved_at_0[0x8];
9185         u8                                     local_port[0x8];
9186         u8                                     reserved_at_10[0x10];
9187         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9188 };
9189
9190 struct mlx5_ifc_qpts_reg_bits {
9191         u8         reserved_at_0[0x8];
9192         u8         local_port[0x8];
9193         u8         reserved_at_10[0x2d];
9194         u8         trust_state[0x3];
9195 };
9196
9197 struct mlx5_ifc_pptb_reg_bits {
9198         u8         reserved_at_0[0x2];
9199         u8         mm[0x2];
9200         u8         reserved_at_4[0x4];
9201         u8         local_port[0x8];
9202         u8         reserved_at_10[0x6];
9203         u8         cm[0x1];
9204         u8         um[0x1];
9205         u8         pm[0x8];
9206
9207         u8         prio_x_buff[0x20];
9208
9209         u8         pm_msb[0x8];
9210         u8         reserved_at_48[0x10];
9211         u8         ctrl_buff[0x4];
9212         u8         untagged_buff[0x4];
9213 };
9214
9215 struct mlx5_ifc_pbmc_reg_bits {
9216         u8         reserved_at_0[0x8];
9217         u8         local_port[0x8];
9218         u8         reserved_at_10[0x10];
9219
9220         u8         xoff_timer_value[0x10];
9221         u8         xoff_refresh[0x10];
9222
9223         u8         reserved_at_40[0x9];
9224         u8         fullness_threshold[0x7];
9225         u8         port_buffer_size[0x10];
9226
9227         struct mlx5_ifc_bufferx_reg_bits buffer[10];
9228
9229         u8         reserved_at_2e0[0x40];
9230 };
9231
9232 struct mlx5_ifc_qtct_reg_bits {
9233         u8         reserved_at_0[0x8];
9234         u8         port_number[0x8];
9235         u8         reserved_at_10[0xd];
9236         u8         prio[0x3];
9237
9238         u8         reserved_at_20[0x1d];
9239         u8         tclass[0x3];
9240 };
9241
9242 struct mlx5_ifc_mcia_reg_bits {
9243         u8         l[0x1];
9244         u8         reserved_at_1[0x7];
9245         u8         module[0x8];
9246         u8         reserved_at_10[0x8];
9247         u8         status[0x8];
9248
9249         u8         i2c_device_address[0x8];
9250         u8         page_number[0x8];
9251         u8         device_address[0x10];
9252
9253         u8         reserved_at_40[0x10];
9254         u8         size[0x10];
9255
9256         u8         reserved_at_60[0x20];
9257
9258         u8         dword_0[0x20];
9259         u8         dword_1[0x20];
9260         u8         dword_2[0x20];
9261         u8         dword_3[0x20];
9262         u8         dword_4[0x20];
9263         u8         dword_5[0x20];
9264         u8         dword_6[0x20];
9265         u8         dword_7[0x20];
9266         u8         dword_8[0x20];
9267         u8         dword_9[0x20];
9268         u8         dword_10[0x20];
9269         u8         dword_11[0x20];
9270 };
9271
9272 struct mlx5_ifc_dcbx_param_bits {
9273         u8         dcbx_cee_cap[0x1];
9274         u8         dcbx_ieee_cap[0x1];
9275         u8         dcbx_standby_cap[0x1];
9276         u8         reserved_at_3[0x5];
9277         u8         port_number[0x8];
9278         u8         reserved_at_10[0xa];
9279         u8         max_application_table_size[6];
9280         u8         reserved_at_20[0x15];
9281         u8         version_oper[0x3];
9282         u8         reserved_at_38[5];
9283         u8         version_admin[0x3];
9284         u8         willing_admin[0x1];
9285         u8         reserved_at_41[0x3];
9286         u8         pfc_cap_oper[0x4];
9287         u8         reserved_at_48[0x4];
9288         u8         pfc_cap_admin[0x4];
9289         u8         reserved_at_50[0x4];
9290         u8         num_of_tc_oper[0x4];
9291         u8         reserved_at_58[0x4];
9292         u8         num_of_tc_admin[0x4];
9293         u8         remote_willing[0x1];
9294         u8         reserved_at_61[3];
9295         u8         remote_pfc_cap[4];
9296         u8         reserved_at_68[0x14];
9297         u8         remote_num_of_tc[0x4];
9298         u8         reserved_at_80[0x18];
9299         u8         error[0x8];
9300         u8         reserved_at_a0[0x160];
9301 };
9302
9303 struct mlx5_ifc_lagc_bits {
9304         u8         reserved_at_0[0x1d];
9305         u8         lag_state[0x3];
9306
9307         u8         reserved_at_20[0x14];
9308         u8         tx_remap_affinity_2[0x4];
9309         u8         reserved_at_38[0x4];
9310         u8         tx_remap_affinity_1[0x4];
9311 };
9312
9313 struct mlx5_ifc_create_lag_out_bits {
9314         u8         status[0x8];
9315         u8         reserved_at_8[0x18];
9316
9317         u8         syndrome[0x20];
9318
9319         u8         reserved_at_40[0x40];
9320 };
9321
9322 struct mlx5_ifc_create_lag_in_bits {
9323         u8         opcode[0x10];
9324         u8         reserved_at_10[0x10];
9325
9326         u8         reserved_at_20[0x10];
9327         u8         op_mod[0x10];
9328
9329         struct mlx5_ifc_lagc_bits ctx;
9330 };
9331
9332 struct mlx5_ifc_modify_lag_out_bits {
9333         u8         status[0x8];
9334         u8         reserved_at_8[0x18];
9335
9336         u8         syndrome[0x20];
9337
9338         u8         reserved_at_40[0x40];
9339 };
9340
9341 struct mlx5_ifc_modify_lag_in_bits {
9342         u8         opcode[0x10];
9343         u8         reserved_at_10[0x10];
9344
9345         u8         reserved_at_20[0x10];
9346         u8         op_mod[0x10];
9347
9348         u8         reserved_at_40[0x20];
9349         u8         field_select[0x20];
9350
9351         struct mlx5_ifc_lagc_bits ctx;
9352 };
9353
9354 struct mlx5_ifc_query_lag_out_bits {
9355         u8         status[0x8];
9356         u8         reserved_at_8[0x18];
9357
9358         u8         syndrome[0x20];
9359
9360         u8         reserved_at_40[0x40];
9361
9362         struct mlx5_ifc_lagc_bits ctx;
9363 };
9364
9365 struct mlx5_ifc_query_lag_in_bits {
9366         u8         opcode[0x10];
9367         u8         reserved_at_10[0x10];
9368
9369         u8         reserved_at_20[0x10];
9370         u8         op_mod[0x10];
9371
9372         u8         reserved_at_40[0x40];
9373 };
9374
9375 struct mlx5_ifc_destroy_lag_out_bits {
9376         u8         status[0x8];
9377         u8         reserved_at_8[0x18];
9378
9379         u8         syndrome[0x20];
9380
9381         u8         reserved_at_40[0x40];
9382 };
9383
9384 struct mlx5_ifc_destroy_lag_in_bits {
9385         u8         opcode[0x10];
9386         u8         reserved_at_10[0x10];
9387
9388         u8         reserved_at_20[0x10];
9389         u8         op_mod[0x10];
9390
9391         u8         reserved_at_40[0x40];
9392 };
9393
9394 struct mlx5_ifc_create_vport_lag_out_bits {
9395         u8         status[0x8];
9396         u8         reserved_at_8[0x18];
9397
9398         u8         syndrome[0x20];
9399
9400         u8         reserved_at_40[0x40];
9401 };
9402
9403 struct mlx5_ifc_create_vport_lag_in_bits {
9404         u8         opcode[0x10];
9405         u8         reserved_at_10[0x10];
9406
9407         u8         reserved_at_20[0x10];
9408         u8         op_mod[0x10];
9409
9410         u8         reserved_at_40[0x40];
9411 };
9412
9413 struct mlx5_ifc_destroy_vport_lag_out_bits {
9414         u8         status[0x8];
9415         u8         reserved_at_8[0x18];
9416
9417         u8         syndrome[0x20];
9418
9419         u8         reserved_at_40[0x40];
9420 };
9421
9422 struct mlx5_ifc_destroy_vport_lag_in_bits {
9423         u8         opcode[0x10];
9424         u8         reserved_at_10[0x10];
9425
9426         u8         reserved_at_20[0x10];
9427         u8         op_mod[0x10];
9428
9429         u8         reserved_at_40[0x40];
9430 };
9431
9432 struct mlx5_ifc_alloc_memic_in_bits {
9433         u8         opcode[0x10];
9434         u8         reserved_at_10[0x10];
9435
9436         u8         reserved_at_20[0x10];
9437         u8         op_mod[0x10];
9438
9439         u8         reserved_at_30[0x20];
9440
9441         u8         reserved_at_40[0x18];
9442         u8         log_memic_addr_alignment[0x8];
9443
9444         u8         range_start_addr[0x40];
9445
9446         u8         range_size[0x20];
9447
9448         u8         memic_size[0x20];
9449 };
9450
9451 struct mlx5_ifc_alloc_memic_out_bits {
9452         u8         status[0x8];
9453         u8         reserved_at_8[0x18];
9454
9455         u8         syndrome[0x20];
9456
9457         u8         memic_start_addr[0x40];
9458 };
9459
9460 struct mlx5_ifc_dealloc_memic_in_bits {
9461         u8         opcode[0x10];
9462         u8         reserved_at_10[0x10];
9463
9464         u8         reserved_at_20[0x10];
9465         u8         op_mod[0x10];
9466
9467         u8         reserved_at_40[0x40];
9468
9469         u8         memic_start_addr[0x40];
9470
9471         u8         memic_size[0x20];
9472
9473         u8         reserved_at_e0[0x20];
9474 };
9475
9476 struct mlx5_ifc_dealloc_memic_out_bits {
9477         u8         status[0x8];
9478         u8         reserved_at_8[0x18];
9479
9480         u8         syndrome[0x20];
9481
9482         u8         reserved_at_40[0x40];
9483 };
9484
9485 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9486         u8         opcode[0x10];
9487         u8         uid[0x10];
9488
9489         u8         reserved_at_20[0x10];
9490         u8         obj_type[0x10];
9491
9492         u8         obj_id[0x20];
9493
9494         u8         reserved_at_60[0x20];
9495 };
9496
9497 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9498         u8         status[0x8];
9499         u8         reserved_at_8[0x18];
9500
9501         u8         syndrome[0x20];
9502
9503         u8         obj_id[0x20];
9504
9505         u8         reserved_at_60[0x20];
9506 };
9507
9508 struct mlx5_ifc_umem_bits {
9509         u8         reserved_at_0[0x80];
9510
9511         u8         reserved_at_80[0x1b];
9512         u8         log_page_size[0x5];
9513
9514         u8         page_offset[0x20];
9515
9516         u8         num_of_mtt[0x40];
9517
9518         struct mlx5_ifc_mtt_bits  mtt[0];
9519 };
9520
9521 struct mlx5_ifc_uctx_bits {
9522         u8         cap[0x20];
9523
9524         u8         reserved_at_20[0x160];
9525 };
9526
9527 struct mlx5_ifc_sw_icm_bits {
9528         u8         modify_field_select[0x40];
9529
9530         u8         reserved_at_40[0x18];
9531         u8         log_sw_icm_size[0x8];
9532
9533         u8         reserved_at_60[0x20];
9534
9535         u8         sw_icm_start_addr[0x40];
9536
9537         u8         reserved_at_c0[0x140];
9538 };
9539
9540 struct mlx5_ifc_create_umem_in_bits {
9541         u8         opcode[0x10];
9542         u8         uid[0x10];
9543
9544         u8         reserved_at_20[0x10];
9545         u8         op_mod[0x10];
9546
9547         u8         reserved_at_40[0x40];
9548
9549         struct mlx5_ifc_umem_bits  umem;
9550 };
9551
9552 struct mlx5_ifc_create_uctx_in_bits {
9553         u8         opcode[0x10];
9554         u8         reserved_at_10[0x10];
9555
9556         u8         reserved_at_20[0x10];
9557         u8         op_mod[0x10];
9558
9559         u8         reserved_at_40[0x40];
9560
9561         struct mlx5_ifc_uctx_bits  uctx;
9562 };
9563
9564 struct mlx5_ifc_destroy_uctx_in_bits {
9565         u8         opcode[0x10];
9566         u8         reserved_at_10[0x10];
9567
9568         u8         reserved_at_20[0x10];
9569         u8         op_mod[0x10];
9570
9571         u8         reserved_at_40[0x10];
9572         u8         uid[0x10];
9573
9574         u8         reserved_at_60[0x20];
9575 };
9576
9577 struct mlx5_ifc_create_sw_icm_in_bits {
9578         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9579         struct mlx5_ifc_sw_icm_bits                   sw_icm;
9580 };
9581
9582 struct mlx5_ifc_mtrc_string_db_param_bits {
9583         u8         string_db_base_address[0x20];
9584
9585         u8         reserved_at_20[0x8];
9586         u8         string_db_size[0x18];
9587 };
9588
9589 struct mlx5_ifc_mtrc_cap_bits {
9590         u8         trace_owner[0x1];
9591         u8         trace_to_memory[0x1];
9592         u8         reserved_at_2[0x4];
9593         u8         trc_ver[0x2];
9594         u8         reserved_at_8[0x14];
9595         u8         num_string_db[0x4];
9596
9597         u8         first_string_trace[0x8];
9598         u8         num_string_trace[0x8];
9599         u8         reserved_at_30[0x28];
9600
9601         u8         log_max_trace_buffer_size[0x8];
9602
9603         u8         reserved_at_60[0x20];
9604
9605         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9606
9607         u8         reserved_at_280[0x180];
9608 };
9609
9610 struct mlx5_ifc_mtrc_conf_bits {
9611         u8         reserved_at_0[0x1c];
9612         u8         trace_mode[0x4];
9613         u8         reserved_at_20[0x18];
9614         u8         log_trace_buffer_size[0x8];
9615         u8         trace_mkey[0x20];
9616         u8         reserved_at_60[0x3a0];
9617 };
9618
9619 struct mlx5_ifc_mtrc_stdb_bits {
9620         u8         string_db_index[0x4];
9621         u8         reserved_at_4[0x4];
9622         u8         read_size[0x18];
9623         u8         start_offset[0x20];
9624         u8         string_db_data[0];
9625 };
9626
9627 struct mlx5_ifc_mtrc_ctrl_bits {
9628         u8         trace_status[0x2];
9629         u8         reserved_at_2[0x2];
9630         u8         arm_event[0x1];
9631         u8         reserved_at_5[0xb];
9632         u8         modify_field_select[0x10];
9633         u8         reserved_at_20[0x2b];
9634         u8         current_timestamp52_32[0x15];
9635         u8         current_timestamp31_0[0x20];
9636         u8         reserved_at_80[0x180];
9637 };
9638
9639 struct mlx5_ifc_host_params_context_bits {
9640         u8         host_number[0x8];
9641         u8         reserved_at_8[0x8];
9642         u8         host_num_of_vfs[0x10];
9643
9644         u8         reserved_at_20[0x10];
9645         u8         host_pci_bus[0x10];
9646
9647         u8         reserved_at_40[0x10];
9648         u8         host_pci_device[0x10];
9649
9650         u8         reserved_at_60[0x10];
9651         u8         host_pci_function[0x10];
9652
9653         u8         reserved_at_80[0x180];
9654 };
9655
9656 struct mlx5_ifc_query_host_params_in_bits {
9657         u8         opcode[0x10];
9658         u8         reserved_at_10[0x10];
9659
9660         u8         reserved_at_20[0x10];
9661         u8         op_mod[0x10];
9662
9663         u8         reserved_at_40[0x40];
9664 };
9665
9666 struct mlx5_ifc_query_host_params_out_bits {
9667         u8         status[0x8];
9668         u8         reserved_at_8[0x18];
9669
9670         u8         syndrome[0x20];
9671
9672         u8         reserved_at_40[0x40];
9673
9674         struct mlx5_ifc_host_params_context_bits host_params_context;
9675
9676         u8         reserved_at_280[0x180];
9677 };
9678
9679 #endif /* MLX5_IFC_H */