2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
81 MLX5_SHARED_RESOURCE_UID = 0xffff,
85 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
97 MLX5_OBJ_TYPE_MKEY = 0xff01,
98 MLX5_OBJ_TYPE_QP = 0xff02,
99 MLX5_OBJ_TYPE_PSV = 0xff03,
100 MLX5_OBJ_TYPE_RMP = 0xff04,
101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
102 MLX5_OBJ_TYPE_RQ = 0xff06,
103 MLX5_OBJ_TYPE_SQ = 0xff07,
104 MLX5_OBJ_TYPE_TIR = 0xff08,
105 MLX5_OBJ_TYPE_TIS = 0xff09,
106 MLX5_OBJ_TYPE_DCT = 0xff0a,
107 MLX5_OBJ_TYPE_XRQ = 0xff0b,
108 MLX5_OBJ_TYPE_RQT = 0xff0e,
109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
110 MLX5_OBJ_TYPE_CQ = 0xff10,
114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
116 MLX5_CMD_OP_INIT_HCA = 0x102,
117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
118 MLX5_CMD_OP_ENABLE_HCA = 0x104,
119 MLX5_CMD_OP_DISABLE_HCA = 0x105,
120 MLX5_CMD_OP_QUERY_PAGES = 0x107,
121 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
122 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
123 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
124 MLX5_CMD_OP_SET_ISSI = 0x10b,
125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
127 MLX5_CMD_OP_ALLOC_SF = 0x113,
128 MLX5_CMD_OP_DEALLOC_SF = 0x114,
129 MLX5_CMD_OP_CREATE_MKEY = 0x200,
130 MLX5_CMD_OP_QUERY_MKEY = 0x201,
131 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
136 MLX5_CMD_OP_MODIFY_MEMIC = 0x207,
137 MLX5_CMD_OP_CREATE_EQ = 0x301,
138 MLX5_CMD_OP_DESTROY_EQ = 0x302,
139 MLX5_CMD_OP_QUERY_EQ = 0x303,
140 MLX5_CMD_OP_GEN_EQE = 0x304,
141 MLX5_CMD_OP_CREATE_CQ = 0x400,
142 MLX5_CMD_OP_DESTROY_CQ = 0x401,
143 MLX5_CMD_OP_QUERY_CQ = 0x402,
144 MLX5_CMD_OP_MODIFY_CQ = 0x403,
145 MLX5_CMD_OP_CREATE_QP = 0x500,
146 MLX5_CMD_OP_DESTROY_QP = 0x501,
147 MLX5_CMD_OP_RST2INIT_QP = 0x502,
148 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
149 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
150 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
151 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
152 MLX5_CMD_OP_2ERR_QP = 0x507,
153 MLX5_CMD_OP_2RST_QP = 0x50a,
154 MLX5_CMD_OP_QUERY_QP = 0x50b,
155 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
156 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
157 MLX5_CMD_OP_CREATE_PSV = 0x600,
158 MLX5_CMD_OP_DESTROY_PSV = 0x601,
159 MLX5_CMD_OP_CREATE_SRQ = 0x700,
160 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
161 MLX5_CMD_OP_QUERY_SRQ = 0x702,
162 MLX5_CMD_OP_ARM_RQ = 0x703,
163 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
164 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
165 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
166 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
167 MLX5_CMD_OP_CREATE_DCT = 0x710,
168 MLX5_CMD_OP_DESTROY_DCT = 0x711,
169 MLX5_CMD_OP_DRAIN_DCT = 0x712,
170 MLX5_CMD_OP_QUERY_DCT = 0x713,
171 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
172 MLX5_CMD_OP_CREATE_XRQ = 0x717,
173 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
174 MLX5_CMD_OP_QUERY_XRQ = 0x719,
175 MLX5_CMD_OP_ARM_XRQ = 0x71a,
176 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
177 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
178 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
179 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
180 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
181 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
182 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
183 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
184 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
185 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
186 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
187 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
188 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
189 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
190 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
191 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
192 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
193 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
194 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
195 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
196 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
197 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
198 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
199 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
200 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
201 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
202 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
203 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
204 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
205 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
206 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
207 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
208 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
209 MLX5_CMD_OP_ALLOC_PD = 0x800,
210 MLX5_CMD_OP_DEALLOC_PD = 0x801,
211 MLX5_CMD_OP_ALLOC_UAR = 0x802,
212 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
213 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
214 MLX5_CMD_OP_ACCESS_REG = 0x805,
215 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
216 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
217 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
218 MLX5_CMD_OP_MAD_IFC = 0x50d,
219 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
220 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
221 MLX5_CMD_OP_NOP = 0x80d,
222 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
223 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
224 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
225 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
226 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
227 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
228 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
229 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
230 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
231 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
232 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
233 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
234 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
235 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
236 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
237 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
238 MLX5_CMD_OP_CREATE_LAG = 0x840,
239 MLX5_CMD_OP_MODIFY_LAG = 0x841,
240 MLX5_CMD_OP_QUERY_LAG = 0x842,
241 MLX5_CMD_OP_DESTROY_LAG = 0x843,
242 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
243 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
244 MLX5_CMD_OP_CREATE_TIR = 0x900,
245 MLX5_CMD_OP_MODIFY_TIR = 0x901,
246 MLX5_CMD_OP_DESTROY_TIR = 0x902,
247 MLX5_CMD_OP_QUERY_TIR = 0x903,
248 MLX5_CMD_OP_CREATE_SQ = 0x904,
249 MLX5_CMD_OP_MODIFY_SQ = 0x905,
250 MLX5_CMD_OP_DESTROY_SQ = 0x906,
251 MLX5_CMD_OP_QUERY_SQ = 0x907,
252 MLX5_CMD_OP_CREATE_RQ = 0x908,
253 MLX5_CMD_OP_MODIFY_RQ = 0x909,
254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
255 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
256 MLX5_CMD_OP_QUERY_RQ = 0x90b,
257 MLX5_CMD_OP_CREATE_RMP = 0x90c,
258 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
259 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
260 MLX5_CMD_OP_QUERY_RMP = 0x90f,
261 MLX5_CMD_OP_CREATE_TIS = 0x912,
262 MLX5_CMD_OP_MODIFY_TIS = 0x913,
263 MLX5_CMD_OP_DESTROY_TIS = 0x914,
264 MLX5_CMD_OP_QUERY_TIS = 0x915,
265 MLX5_CMD_OP_CREATE_RQT = 0x916,
266 MLX5_CMD_OP_MODIFY_RQT = 0x917,
267 MLX5_CMD_OP_DESTROY_RQT = 0x918,
268 MLX5_CMD_OP_QUERY_RQT = 0x919,
269 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
270 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
271 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
272 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
273 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
274 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
275 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
276 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
277 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
278 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
279 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
280 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
281 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
282 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
283 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
284 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
285 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
286 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
287 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
288 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
289 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
290 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
291 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
292 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
293 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
295 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
296 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
297 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
298 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
299 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
300 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
301 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
302 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
303 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
304 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
308 /* Valid range for general commands that don't work over an object */
310 MLX5_CMD_OP_GENERAL_START = 0xb00,
311 MLX5_CMD_OP_GENERAL_END = 0xd00,
314 struct mlx5_ifc_flow_table_fields_supported_bits {
317 u8 outer_ether_type[0x1];
318 u8 outer_ip_version[0x1];
319 u8 outer_first_prio[0x1];
320 u8 outer_first_cfi[0x1];
321 u8 outer_first_vid[0x1];
322 u8 outer_ipv4_ttl[0x1];
323 u8 outer_second_prio[0x1];
324 u8 outer_second_cfi[0x1];
325 u8 outer_second_vid[0x1];
326 u8 reserved_at_b[0x1];
330 u8 outer_ip_protocol[0x1];
331 u8 outer_ip_ecn[0x1];
332 u8 outer_ip_dscp[0x1];
333 u8 outer_udp_sport[0x1];
334 u8 outer_udp_dport[0x1];
335 u8 outer_tcp_sport[0x1];
336 u8 outer_tcp_dport[0x1];
337 u8 outer_tcp_flags[0x1];
338 u8 outer_gre_protocol[0x1];
339 u8 outer_gre_key[0x1];
340 u8 outer_vxlan_vni[0x1];
341 u8 outer_geneve_vni[0x1];
342 u8 outer_geneve_oam[0x1];
343 u8 outer_geneve_protocol_type[0x1];
344 u8 outer_geneve_opt_len[0x1];
345 u8 reserved_at_1e[0x1];
346 u8 source_eswitch_port[0x1];
350 u8 inner_ether_type[0x1];
351 u8 inner_ip_version[0x1];
352 u8 inner_first_prio[0x1];
353 u8 inner_first_cfi[0x1];
354 u8 inner_first_vid[0x1];
355 u8 reserved_at_27[0x1];
356 u8 inner_second_prio[0x1];
357 u8 inner_second_cfi[0x1];
358 u8 inner_second_vid[0x1];
359 u8 reserved_at_2b[0x1];
363 u8 inner_ip_protocol[0x1];
364 u8 inner_ip_ecn[0x1];
365 u8 inner_ip_dscp[0x1];
366 u8 inner_udp_sport[0x1];
367 u8 inner_udp_dport[0x1];
368 u8 inner_tcp_sport[0x1];
369 u8 inner_tcp_dport[0x1];
370 u8 inner_tcp_flags[0x1];
371 u8 reserved_at_37[0x9];
373 u8 geneve_tlv_option_0_data[0x1];
374 u8 reserved_at_41[0x4];
375 u8 outer_first_mpls_over_udp[0x4];
376 u8 outer_first_mpls_over_gre[0x4];
377 u8 inner_first_mpls[0x4];
378 u8 outer_first_mpls[0x4];
379 u8 reserved_at_55[0x2];
380 u8 outer_esp_spi[0x1];
381 u8 reserved_at_58[0x2];
383 u8 reserved_at_5b[0x5];
385 u8 reserved_at_60[0x18];
386 u8 metadata_reg_c_7[0x1];
387 u8 metadata_reg_c_6[0x1];
388 u8 metadata_reg_c_5[0x1];
389 u8 metadata_reg_c_4[0x1];
390 u8 metadata_reg_c_3[0x1];
391 u8 metadata_reg_c_2[0x1];
392 u8 metadata_reg_c_1[0x1];
393 u8 metadata_reg_c_0[0x1];
396 struct mlx5_ifc_flow_table_prop_layout_bits {
398 u8 reserved_at_1[0x1];
399 u8 flow_counter[0x1];
400 u8 flow_modify_en[0x1];
402 u8 identified_miss_table_mode[0x1];
403 u8 flow_table_modify[0x1];
406 u8 reserved_at_9[0x1];
409 u8 reserved_at_c[0x1];
412 u8 reformat_and_vlan_action[0x1];
413 u8 reserved_at_10[0x1];
415 u8 reformat_l3_tunnel_to_l2[0x1];
416 u8 reformat_l2_to_l3_tunnel[0x1];
417 u8 reformat_and_modify_action[0x1];
418 u8 ignore_flow_level[0x1];
419 u8 reserved_at_16[0x1];
420 u8 table_miss_action_domain[0x1];
421 u8 termination_table[0x1];
422 u8 reformat_and_fwd_to_table[0x1];
423 u8 reserved_at_1a[0x2];
424 u8 ipsec_encrypt[0x1];
425 u8 ipsec_decrypt[0x1];
427 u8 reserved_at_1f[0x1];
429 u8 termination_table_raw_traffic[0x1];
430 u8 reserved_at_21[0x1];
431 u8 log_max_ft_size[0x6];
432 u8 log_max_modify_header_context[0x8];
433 u8 max_modify_header_actions[0x8];
434 u8 max_ft_level[0x8];
436 u8 reserved_at_40[0x20];
438 u8 reserved_at_60[0x18];
439 u8 log_max_ft_num[0x8];
441 u8 reserved_at_80[0x10];
442 u8 log_max_flow_counter[0x8];
443 u8 log_max_destination[0x8];
445 u8 reserved_at_a0[0x18];
446 u8 log_max_flow[0x8];
448 u8 reserved_at_c0[0x40];
450 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
452 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
455 struct mlx5_ifc_odp_per_transport_service_cap_bits {
462 u8 reserved_at_6[0x1a];
465 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
490 u8 reserved_at_c0[0x18];
491 u8 ttl_hoplimit[0x8];
496 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
498 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
501 struct mlx5_ifc_nvgre_key_bits {
506 union mlx5_ifc_gre_key_bits {
507 struct mlx5_ifc_nvgre_key_bits nvgre;
511 struct mlx5_ifc_fte_match_set_misc_bits {
512 u8 gre_c_present[0x1];
513 u8 reserved_at_1[0x1];
514 u8 gre_k_present[0x1];
515 u8 gre_s_present[0x1];
516 u8 source_vhca_port[0x4];
519 u8 source_eswitch_owner_vhca_id[0x10];
520 u8 source_port[0x10];
522 u8 outer_second_prio[0x3];
523 u8 outer_second_cfi[0x1];
524 u8 outer_second_vid[0xc];
525 u8 inner_second_prio[0x3];
526 u8 inner_second_cfi[0x1];
527 u8 inner_second_vid[0xc];
529 u8 outer_second_cvlan_tag[0x1];
530 u8 inner_second_cvlan_tag[0x1];
531 u8 outer_second_svlan_tag[0x1];
532 u8 inner_second_svlan_tag[0x1];
533 u8 reserved_at_64[0xc];
534 u8 gre_protocol[0x10];
536 union mlx5_ifc_gre_key_bits gre_key;
539 u8 reserved_at_b8[0x8];
542 u8 reserved_at_d8[0x7];
545 u8 reserved_at_e0[0xc];
546 u8 outer_ipv6_flow_label[0x14];
548 u8 reserved_at_100[0xc];
549 u8 inner_ipv6_flow_label[0x14];
551 u8 reserved_at_120[0xa];
552 u8 geneve_opt_len[0x6];
553 u8 geneve_protocol_type[0x10];
555 u8 reserved_at_140[0x8];
557 u8 reserved_at_160[0x20];
558 u8 outer_esp_spi[0x20];
559 u8 reserved_at_1a0[0x60];
562 struct mlx5_ifc_fte_match_mpls_bits {
569 struct mlx5_ifc_fte_match_set_misc2_bits {
570 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
572 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
574 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
576 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
578 u8 metadata_reg_c_7[0x20];
580 u8 metadata_reg_c_6[0x20];
582 u8 metadata_reg_c_5[0x20];
584 u8 metadata_reg_c_4[0x20];
586 u8 metadata_reg_c_3[0x20];
588 u8 metadata_reg_c_2[0x20];
590 u8 metadata_reg_c_1[0x20];
592 u8 metadata_reg_c_0[0x20];
594 u8 metadata_reg_a[0x20];
596 u8 reserved_at_1a0[0x60];
599 struct mlx5_ifc_fte_match_set_misc3_bits {
600 u8 inner_tcp_seq_num[0x20];
602 u8 outer_tcp_seq_num[0x20];
604 u8 inner_tcp_ack_num[0x20];
606 u8 outer_tcp_ack_num[0x20];
608 u8 reserved_at_80[0x8];
609 u8 outer_vxlan_gpe_vni[0x18];
611 u8 outer_vxlan_gpe_next_protocol[0x8];
612 u8 outer_vxlan_gpe_flags[0x8];
613 u8 reserved_at_b0[0x10];
615 u8 icmp_header_data[0x20];
617 u8 icmpv6_header_data[0x20];
624 u8 geneve_tlv_option_0_data[0x20];
628 u8 gtpu_msg_type[0x8];
629 u8 gtpu_msg_flags[0x8];
630 u8 reserved_at_170[0x10];
634 u8 gtpu_first_ext_dw_0[0x20];
638 u8 reserved_at_1e0[0x20];
641 struct mlx5_ifc_fte_match_set_misc4_bits {
642 u8 prog_sample_field_value_0[0x20];
644 u8 prog_sample_field_id_0[0x20];
646 u8 prog_sample_field_value_1[0x20];
648 u8 prog_sample_field_id_1[0x20];
650 u8 prog_sample_field_value_2[0x20];
652 u8 prog_sample_field_id_2[0x20];
654 u8 prog_sample_field_value_3[0x20];
656 u8 prog_sample_field_id_3[0x20];
658 u8 reserved_at_100[0x100];
661 struct mlx5_ifc_cmd_pas_bits {
665 u8 reserved_at_34[0xc];
668 struct mlx5_ifc_uint64_bits {
675 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
676 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
677 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
678 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
679 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
680 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
681 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
682 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
683 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
684 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
687 struct mlx5_ifc_ads_bits {
690 u8 reserved_at_2[0xe];
693 u8 reserved_at_20[0x8];
699 u8 reserved_at_45[0x3];
700 u8 src_addr_index[0x8];
701 u8 reserved_at_50[0x4];
705 u8 reserved_at_60[0x4];
709 u8 rgid_rip[16][0x8];
711 u8 reserved_at_100[0x4];
714 u8 reserved_at_106[0x1];
723 u8 vhca_port_num[0x8];
729 struct mlx5_ifc_flow_table_nic_cap_bits {
730 u8 nic_rx_multi_path_tirs[0x1];
731 u8 nic_rx_multi_path_tirs_fts[0x1];
732 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
733 u8 reserved_at_3[0x4];
734 u8 sw_owner_reformat_supported[0x1];
735 u8 reserved_at_8[0x18];
737 u8 encap_general_header[0x1];
738 u8 reserved_at_21[0xa];
739 u8 log_max_packet_reformat_context[0x5];
740 u8 reserved_at_30[0x6];
741 u8 max_encap_header_size[0xa];
742 u8 reserved_at_40[0x1c0];
744 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
746 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
748 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
750 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
752 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
754 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
756 u8 reserved_at_e00[0x1200];
758 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
760 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
762 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
764 u8 reserved_at_20c0[0x5f40];
768 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
769 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
770 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
771 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
772 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
773 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
774 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
775 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
778 struct mlx5_ifc_flow_table_eswitch_cap_bits {
779 u8 fdb_to_vport_reg_c_id[0x8];
780 u8 reserved_at_8[0xd];
781 u8 fdb_modify_header_fwd_to_table[0x1];
782 u8 reserved_at_16[0x1];
784 u8 reserved_at_18[0x2];
785 u8 multi_fdb_encap[0x1];
786 u8 egress_acl_forward_to_vport[0x1];
787 u8 fdb_multi_path_to_table[0x1];
788 u8 reserved_at_1d[0x3];
790 u8 reserved_at_20[0x1e0];
792 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
794 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
796 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
798 u8 reserved_at_800[0x1000];
800 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
802 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
804 u8 sw_steering_uplink_icm_address_rx[0x40];
806 u8 sw_steering_uplink_icm_address_tx[0x40];
808 u8 reserved_at_1900[0x6700];
812 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
813 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
816 struct mlx5_ifc_e_switch_cap_bits {
817 u8 vport_svlan_strip[0x1];
818 u8 vport_cvlan_strip[0x1];
819 u8 vport_svlan_insert[0x1];
820 u8 vport_cvlan_insert_if_not_exist[0x1];
821 u8 vport_cvlan_insert_overwrite[0x1];
822 u8 reserved_at_5[0x2];
823 u8 esw_shared_ingress_acl[0x1];
824 u8 esw_uplink_ingress_acl[0x1];
825 u8 root_ft_on_other_esw[0x1];
826 u8 reserved_at_a[0xf];
827 u8 esw_functions_changed[0x1];
828 u8 reserved_at_1a[0x1];
829 u8 ecpf_vport_exists[0x1];
830 u8 counter_eswitch_affinity[0x1];
831 u8 merged_eswitch[0x1];
832 u8 nic_vport_node_guid_modify[0x1];
833 u8 nic_vport_port_guid_modify[0x1];
835 u8 vxlan_encap_decap[0x1];
836 u8 nvgre_encap_decap[0x1];
837 u8 reserved_at_22[0x1];
838 u8 log_max_fdb_encap_uplink[0x5];
839 u8 reserved_at_21[0x3];
840 u8 log_max_packet_reformat_context[0x5];
842 u8 max_encap_header_size[0xa];
844 u8 reserved_at_40[0xb];
845 u8 log_max_esw_sf[0x5];
846 u8 esw_sf_base_id[0x10];
848 u8 reserved_at_60[0x7a0];
852 struct mlx5_ifc_qos_cap_bits {
853 u8 packet_pacing[0x1];
854 u8 esw_scheduling[0x1];
855 u8 esw_bw_share[0x1];
856 u8 esw_rate_limit[0x1];
857 u8 reserved_at_4[0x1];
858 u8 packet_pacing_burst_bound[0x1];
859 u8 packet_pacing_typical_size[0x1];
860 u8 reserved_at_7[0x1];
861 u8 nic_sq_scheduling[0x1];
862 u8 nic_bw_share[0x1];
863 u8 nic_rate_limit[0x1];
864 u8 packet_pacing_uid[0x1];
865 u8 reserved_at_c[0x14];
867 u8 reserved_at_20[0xb];
868 u8 log_max_qos_nic_queue_group[0x5];
869 u8 reserved_at_30[0x10];
871 u8 packet_pacing_max_rate[0x20];
873 u8 packet_pacing_min_rate[0x20];
875 u8 reserved_at_80[0x10];
876 u8 packet_pacing_rate_table_size[0x10];
878 u8 esw_element_type[0x10];
879 u8 esw_tsar_type[0x10];
881 u8 reserved_at_c0[0x10];
882 u8 max_qos_para_vport[0x10];
884 u8 max_tsar_bw_share[0x20];
886 u8 reserved_at_100[0x700];
889 struct mlx5_ifc_debug_cap_bits {
890 u8 core_dump_general[0x1];
891 u8 core_dump_qp[0x1];
892 u8 reserved_at_2[0x7];
893 u8 resource_dump[0x1];
894 u8 reserved_at_a[0x16];
896 u8 reserved_at_20[0x2];
897 u8 stall_detect[0x1];
898 u8 reserved_at_23[0x1d];
900 u8 reserved_at_40[0x7c0];
903 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
907 u8 lro_psh_flag[0x1];
908 u8 lro_time_stamp[0x1];
909 u8 reserved_at_5[0x2];
910 u8 wqe_vlan_insert[0x1];
911 u8 self_lb_en_modifiable[0x1];
912 u8 reserved_at_9[0x2];
914 u8 multi_pkt_send_wqe[0x2];
915 u8 wqe_inline_mode[0x2];
916 u8 rss_ind_tbl_cap[0x4];
919 u8 enhanced_multi_pkt_send_wqe[0x1];
920 u8 tunnel_lso_const_out_ip_id[0x1];
921 u8 reserved_at_1c[0x2];
922 u8 tunnel_stateless_gre[0x1];
923 u8 tunnel_stateless_vxlan[0x1];
928 u8 cqe_checksum_full[0x1];
929 u8 tunnel_stateless_geneve_tx[0x1];
930 u8 tunnel_stateless_mpls_over_udp[0x1];
931 u8 tunnel_stateless_mpls_over_gre[0x1];
932 u8 tunnel_stateless_vxlan_gpe[0x1];
933 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
934 u8 tunnel_stateless_ip_over_ip[0x1];
935 u8 insert_trailer[0x1];
936 u8 reserved_at_2b[0x1];
937 u8 tunnel_stateless_ip_over_ip_rx[0x1];
938 u8 tunnel_stateless_ip_over_ip_tx[0x1];
939 u8 reserved_at_2e[0x2];
940 u8 max_vxlan_udp_ports[0x8];
941 u8 reserved_at_38[0x6];
942 u8 max_geneve_opt_len[0x1];
943 u8 tunnel_stateless_geneve_rx[0x1];
945 u8 reserved_at_40[0x10];
946 u8 lro_min_mss_size[0x10];
948 u8 reserved_at_60[0x120];
950 u8 lro_timer_supported_periods[4][0x20];
952 u8 reserved_at_200[0x600];
956 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
957 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
958 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
961 struct mlx5_ifc_roce_cap_bits {
963 u8 reserved_at_1[0x3];
964 u8 sw_r_roce_src_udp_port[0x1];
965 u8 fl_rc_qp_when_roce_disabled[0x1];
966 u8 fl_rc_qp_when_roce_enabled[0x1];
967 u8 reserved_at_7[0x17];
968 u8 qp_ts_format[0x2];
970 u8 reserved_at_20[0x60];
972 u8 reserved_at_80[0xc];
974 u8 reserved_at_90[0x8];
975 u8 roce_version[0x8];
977 u8 reserved_at_a0[0x10];
978 u8 r_roce_dest_udp_port[0x10];
980 u8 r_roce_max_src_udp_port[0x10];
981 u8 r_roce_min_src_udp_port[0x10];
983 u8 reserved_at_e0[0x10];
984 u8 roce_address_table_size[0x10];
986 u8 reserved_at_100[0x700];
989 struct mlx5_ifc_sync_steering_in_bits {
993 u8 reserved_at_20[0x10];
996 u8 reserved_at_40[0xc0];
999 struct mlx5_ifc_sync_steering_out_bits {
1001 u8 reserved_at_8[0x18];
1005 u8 reserved_at_40[0x40];
1008 struct mlx5_ifc_device_mem_cap_bits {
1010 u8 reserved_at_1[0x1f];
1012 u8 reserved_at_20[0xb];
1013 u8 log_min_memic_alloc_size[0x5];
1014 u8 reserved_at_30[0x8];
1015 u8 log_max_memic_addr_alignment[0x8];
1017 u8 memic_bar_start_addr[0x40];
1019 u8 memic_bar_size[0x20];
1021 u8 max_memic_size[0x20];
1023 u8 steering_sw_icm_start_address[0x40];
1025 u8 reserved_at_100[0x8];
1026 u8 log_header_modify_sw_icm_size[0x8];
1027 u8 reserved_at_110[0x2];
1028 u8 log_sw_icm_alloc_granularity[0x6];
1029 u8 log_steering_sw_icm_size[0x8];
1031 u8 reserved_at_120[0x20];
1033 u8 header_modify_sw_icm_start_address[0x40];
1035 u8 reserved_at_180[0x80];
1037 u8 memic_operations[0x20];
1039 u8 reserved_at_220[0x5e0];
1042 struct mlx5_ifc_device_event_cap_bits {
1043 u8 user_affiliated_events[4][0x40];
1045 u8 user_unaffiliated_events[4][0x40];
1048 struct mlx5_ifc_virtio_emulation_cap_bits {
1049 u8 desc_tunnel_offload_type[0x1];
1050 u8 eth_frame_offload_type[0x1];
1051 u8 virtio_version_1_0[0x1];
1052 u8 device_features_bits_mask[0xd];
1054 u8 virtio_queue_type[0x8];
1056 u8 max_tunnel_desc[0x10];
1057 u8 reserved_at_30[0x3];
1058 u8 log_doorbell_stride[0x5];
1059 u8 reserved_at_38[0x3];
1060 u8 log_doorbell_bar_size[0x5];
1062 u8 doorbell_bar_offset[0x40];
1064 u8 max_emulated_devices[0x8];
1065 u8 max_num_virtio_queues[0x18];
1067 u8 reserved_at_a0[0x60];
1069 u8 umem_1_buffer_param_a[0x20];
1071 u8 umem_1_buffer_param_b[0x20];
1073 u8 umem_2_buffer_param_a[0x20];
1075 u8 umem_2_buffer_param_b[0x20];
1077 u8 umem_3_buffer_param_a[0x20];
1079 u8 umem_3_buffer_param_b[0x20];
1081 u8 reserved_at_1c0[0x640];
1085 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1086 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1087 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1088 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1089 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1090 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1091 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1092 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1093 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1097 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1098 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1099 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1100 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1101 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1102 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1103 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1104 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1105 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1108 struct mlx5_ifc_atomic_caps_bits {
1109 u8 reserved_at_0[0x40];
1111 u8 atomic_req_8B_endianness_mode[0x2];
1112 u8 reserved_at_42[0x4];
1113 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1115 u8 reserved_at_47[0x19];
1117 u8 reserved_at_60[0x20];
1119 u8 reserved_at_80[0x10];
1120 u8 atomic_operations[0x10];
1122 u8 reserved_at_a0[0x10];
1123 u8 atomic_size_qp[0x10];
1125 u8 reserved_at_c0[0x10];
1126 u8 atomic_size_dc[0x10];
1128 u8 reserved_at_e0[0x720];
1131 struct mlx5_ifc_odp_cap_bits {
1132 u8 reserved_at_0[0x40];
1135 u8 reserved_at_41[0x1f];
1137 u8 reserved_at_60[0x20];
1139 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1141 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1143 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1145 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1147 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1149 u8 reserved_at_120[0x6E0];
1152 struct mlx5_ifc_calc_op {
1153 u8 reserved_at_0[0x10];
1154 u8 reserved_at_10[0x9];
1155 u8 op_swap_endianness[0x1];
1164 struct mlx5_ifc_vector_calc_cap_bits {
1165 u8 calc_matrix[0x1];
1166 u8 reserved_at_1[0x1f];
1167 u8 reserved_at_20[0x8];
1168 u8 max_vec_count[0x8];
1169 u8 reserved_at_30[0xd];
1170 u8 max_chunk_size[0x3];
1171 struct mlx5_ifc_calc_op calc0;
1172 struct mlx5_ifc_calc_op calc1;
1173 struct mlx5_ifc_calc_op calc2;
1174 struct mlx5_ifc_calc_op calc3;
1176 u8 reserved_at_c0[0x720];
1179 struct mlx5_ifc_tls_cap_bits {
1180 u8 tls_1_2_aes_gcm_128[0x1];
1181 u8 tls_1_3_aes_gcm_128[0x1];
1182 u8 tls_1_2_aes_gcm_256[0x1];
1183 u8 tls_1_3_aes_gcm_256[0x1];
1184 u8 reserved_at_4[0x1c];
1186 u8 reserved_at_20[0x7e0];
1189 struct mlx5_ifc_ipsec_cap_bits {
1190 u8 ipsec_full_offload[0x1];
1191 u8 ipsec_crypto_offload[0x1];
1193 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1194 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1195 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1196 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1197 u8 reserved_at_7[0x4];
1198 u8 log_max_ipsec_offload[0x5];
1199 u8 reserved_at_10[0x10];
1201 u8 min_log_ipsec_full_replay_window[0x8];
1202 u8 max_log_ipsec_full_replay_window[0x8];
1203 u8 reserved_at_30[0x7d0];
1207 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1208 MLX5_WQ_TYPE_CYCLIC = 0x1,
1209 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1210 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1214 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1215 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1219 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1220 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1221 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1222 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1223 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1227 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1228 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1229 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1230 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1231 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1232 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1236 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1237 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1241 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1242 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1243 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1247 MLX5_CAP_PORT_TYPE_IB = 0x0,
1248 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1252 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1253 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1254 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1258 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
1259 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4,
1260 mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5,
1261 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1262 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1263 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1264 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1265 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11,
1266 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16,
1267 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1268 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18,
1269 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19,
1273 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1274 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1277 #define MLX5_FC_BULK_SIZE_FACTOR 128
1279 enum mlx5_fc_bulk_alloc_bitmask {
1280 MLX5_FC_BULK_128 = (1 << 0),
1281 MLX5_FC_BULK_256 = (1 << 1),
1282 MLX5_FC_BULK_512 = (1 << 2),
1283 MLX5_FC_BULK_1024 = (1 << 3),
1284 MLX5_FC_BULK_2048 = (1 << 4),
1285 MLX5_FC_BULK_4096 = (1 << 5),
1286 MLX5_FC_BULK_8192 = (1 << 6),
1287 MLX5_FC_BULK_16384 = (1 << 7),
1290 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1293 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1294 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1298 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1299 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1300 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1304 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1305 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1306 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1309 struct mlx5_ifc_cmd_hca_cap_bits {
1310 u8 reserved_at_0[0x1f];
1311 u8 vhca_resource_manager[0x1];
1313 u8 reserved_at_20[0x3];
1314 u8 event_on_vhca_state_teardown_request[0x1];
1315 u8 event_on_vhca_state_in_use[0x1];
1316 u8 event_on_vhca_state_active[0x1];
1317 u8 event_on_vhca_state_allocated[0x1];
1318 u8 event_on_vhca_state_invalid[0x1];
1319 u8 reserved_at_28[0x8];
1322 u8 reserved_at_40[0x40];
1324 u8 log_max_srq_sz[0x8];
1325 u8 log_max_qp_sz[0x8];
1327 u8 reserved_at_91[0x2];
1328 u8 isolate_vl_tc_new[0x1];
1329 u8 reserved_at_94[0x4];
1330 u8 prio_tag_required[0x1];
1331 u8 reserved_at_99[0x2];
1334 u8 reserved_at_a0[0x3];
1335 u8 ece_support[0x1];
1336 u8 reserved_at_a4[0x5];
1337 u8 reg_c_preserve[0x1];
1338 u8 reserved_at_aa[0x1];
1339 u8 log_max_srq[0x5];
1340 u8 reserved_at_b0[0x1];
1341 u8 uplink_follow[0x1];
1342 u8 ts_cqe_to_dest_cqn[0x1];
1343 u8 reserved_at_b3[0xd];
1345 u8 max_sgl_for_optimized_performance[0x8];
1346 u8 log_max_cq_sz[0x8];
1347 u8 relaxed_ordering_write_umr[0x1];
1348 u8 relaxed_ordering_read_umr[0x1];
1349 u8 reserved_at_d2[0x7];
1350 u8 virtio_net_device_emualtion_manager[0x1];
1351 u8 virtio_blk_device_emualtion_manager[0x1];
1354 u8 log_max_eq_sz[0x8];
1355 u8 relaxed_ordering_write[0x1];
1356 u8 relaxed_ordering_read[0x1];
1357 u8 log_max_mkey[0x6];
1358 u8 reserved_at_f0[0x8];
1359 u8 dump_fill_mkey[0x1];
1360 u8 reserved_at_f9[0x2];
1361 u8 fast_teardown[0x1];
1364 u8 max_indirection[0x8];
1365 u8 fixed_buffer_size[0x1];
1366 u8 log_max_mrw_sz[0x7];
1367 u8 force_teardown[0x1];
1368 u8 reserved_at_111[0x1];
1369 u8 log_max_bsf_list_size[0x6];
1370 u8 umr_extended_translation_offset[0x1];
1372 u8 log_max_klm_list_size[0x6];
1374 u8 reserved_at_120[0xa];
1375 u8 log_max_ra_req_dc[0x6];
1376 u8 reserved_at_130[0xa];
1377 u8 log_max_ra_res_dc[0x6];
1379 u8 reserved_at_140[0x6];
1380 u8 release_all_pages[0x1];
1381 u8 reserved_at_147[0x2];
1383 u8 log_max_ra_req_qp[0x6];
1384 u8 reserved_at_150[0xa];
1385 u8 log_max_ra_res_qp[0x6];
1388 u8 cc_query_allowed[0x1];
1389 u8 cc_modify_allowed[0x1];
1391 u8 cache_line_128byte[0x1];
1392 u8 reserved_at_165[0x4];
1393 u8 rts2rts_qp_counters_set_id[0x1];
1394 u8 reserved_at_16a[0x2];
1395 u8 vnic_env_int_rq_oob[0x1];
1397 u8 reserved_at_16e[0x1];
1399 u8 gid_table_size[0x10];
1401 u8 out_of_seq_cnt[0x1];
1402 u8 vport_counters[0x1];
1403 u8 retransmission_q_counters[0x1];
1405 u8 modify_rq_counter_set_id[0x1];
1406 u8 rq_delay_drop[0x1];
1408 u8 pkey_table_size[0x10];
1410 u8 vport_group_manager[0x1];
1411 u8 vhca_group_manager[0x1];
1414 u8 vnic_env_queue_counters[0x1];
1416 u8 nic_flow_table[0x1];
1417 u8 eswitch_manager[0x1];
1418 u8 device_memory[0x1];
1421 u8 local_ca_ack_delay[0x5];
1422 u8 port_module_event[0x1];
1423 u8 enhanced_error_q_counters[0x1];
1424 u8 ports_check[0x1];
1425 u8 reserved_at_1b3[0x1];
1426 u8 disable_link_up[0x1];
1431 u8 reserved_at_1c0[0x1];
1434 u8 log_max_msg[0x5];
1435 u8 reserved_at_1c8[0x4];
1437 u8 temp_warn_event[0x1];
1439 u8 general_notification_event[0x1];
1440 u8 reserved_at_1d3[0x2];
1444 u8 reserved_at_1d8[0x1];
1453 u8 stat_rate_support[0x10];
1454 u8 reserved_at_1f0[0x1];
1455 u8 pci_sync_for_fw_update_event[0x1];
1456 u8 reserved_at_1f2[0x6];
1457 u8 init2_lag_tx_port_affinity[0x1];
1458 u8 reserved_at_1fa[0x3];
1459 u8 cqe_version[0x4];
1461 u8 compact_address_vector[0x1];
1462 u8 striding_rq[0x1];
1463 u8 reserved_at_202[0x1];
1464 u8 ipoib_enhanced_offloads[0x1];
1465 u8 ipoib_basic_offloads[0x1];
1466 u8 reserved_at_205[0x1];
1467 u8 repeated_block_disabled[0x1];
1468 u8 umr_modify_entity_size_disabled[0x1];
1469 u8 umr_modify_atomic_disabled[0x1];
1470 u8 umr_indirect_mkey_disabled[0x1];
1472 u8 dc_req_scat_data_cqe[0x1];
1473 u8 reserved_at_20d[0x2];
1474 u8 drain_sigerr[0x1];
1475 u8 cmdif_checksum[0x2];
1477 u8 reserved_at_213[0x1];
1478 u8 wq_signature[0x1];
1479 u8 sctr_data_cqe[0x1];
1480 u8 reserved_at_216[0x1];
1486 u8 eth_net_offloads[0x1];
1489 u8 reserved_at_21f[0x1];
1493 u8 cq_moderation[0x1];
1494 u8 reserved_at_223[0x3];
1495 u8 cq_eq_remap[0x1];
1497 u8 block_lb_mc[0x1];
1498 u8 reserved_at_229[0x1];
1499 u8 scqe_break_moderation[0x1];
1500 u8 cq_period_start_from_cqe[0x1];
1502 u8 reserved_at_22d[0x1];
1504 u8 vector_calc[0x1];
1505 u8 umr_ptr_rlky[0x1];
1507 u8 qp_packet_based[0x1];
1508 u8 reserved_at_233[0x3];
1511 u8 set_deth_sqpn[0x1];
1512 u8 reserved_at_239[0x3];
1519 u8 reserved_at_241[0x9];
1521 u8 reserved_at_250[0x8];
1525 u8 driver_version[0x1];
1526 u8 pad_tx_eth_packet[0x1];
1527 u8 reserved_at_263[0x3];
1528 u8 mkey_by_name[0x1];
1529 u8 reserved_at_267[0x4];
1531 u8 log_bf_reg_size[0x5];
1533 u8 reserved_at_270[0x6];
1535 u8 lag_tx_port_affinity[0x1];
1536 u8 lag_native_fdb_selection[0x1];
1537 u8 reserved_at_27a[0x1];
1539 u8 num_lag_ports[0x4];
1541 u8 reserved_at_280[0x10];
1542 u8 max_wqe_sz_sq[0x10];
1544 u8 reserved_at_2a0[0x10];
1545 u8 max_wqe_sz_rq[0x10];
1547 u8 max_flow_counter_31_16[0x10];
1548 u8 max_wqe_sz_sq_dc[0x10];
1550 u8 reserved_at_2e0[0x7];
1551 u8 max_qp_mcg[0x19];
1553 u8 reserved_at_300[0x10];
1554 u8 flow_counter_bulk_alloc[0x8];
1555 u8 log_max_mcg[0x8];
1557 u8 reserved_at_320[0x3];
1558 u8 log_max_transport_domain[0x5];
1559 u8 reserved_at_328[0x3];
1561 u8 reserved_at_330[0xb];
1562 u8 log_max_xrcd[0x5];
1564 u8 nic_receive_steering_discard[0x1];
1565 u8 receive_discard_vport_down[0x1];
1566 u8 transmit_discard_vport_down[0x1];
1567 u8 reserved_at_343[0x5];
1568 u8 log_max_flow_counter_bulk[0x8];
1569 u8 max_flow_counter_15_0[0x10];
1572 u8 reserved_at_360[0x3];
1574 u8 reserved_at_368[0x3];
1576 u8 reserved_at_370[0x3];
1577 u8 log_max_tir[0x5];
1578 u8 reserved_at_378[0x3];
1579 u8 log_max_tis[0x5];
1581 u8 basic_cyclic_rcv_wqe[0x1];
1582 u8 reserved_at_381[0x2];
1583 u8 log_max_rmp[0x5];
1584 u8 reserved_at_388[0x3];
1585 u8 log_max_rqt[0x5];
1586 u8 reserved_at_390[0x3];
1587 u8 log_max_rqt_size[0x5];
1588 u8 reserved_at_398[0x3];
1589 u8 log_max_tis_per_sq[0x5];
1591 u8 ext_stride_num_range[0x1];
1592 u8 reserved_at_3a1[0x2];
1593 u8 log_max_stride_sz_rq[0x5];
1594 u8 reserved_at_3a8[0x3];
1595 u8 log_min_stride_sz_rq[0x5];
1596 u8 reserved_at_3b0[0x3];
1597 u8 log_max_stride_sz_sq[0x5];
1598 u8 reserved_at_3b8[0x3];
1599 u8 log_min_stride_sz_sq[0x5];
1602 u8 reserved_at_3c1[0x2];
1603 u8 log_max_hairpin_queues[0x5];
1604 u8 reserved_at_3c8[0x3];
1605 u8 log_max_hairpin_wq_data_sz[0x5];
1606 u8 reserved_at_3d0[0x3];
1607 u8 log_max_hairpin_num_packets[0x5];
1608 u8 reserved_at_3d8[0x3];
1609 u8 log_max_wq_sz[0x5];
1611 u8 nic_vport_change_event[0x1];
1612 u8 disable_local_lb_uc[0x1];
1613 u8 disable_local_lb_mc[0x1];
1614 u8 log_min_hairpin_wq_data_sz[0x5];
1615 u8 reserved_at_3e8[0x2];
1617 u8 log_max_vlan_list[0x5];
1618 u8 reserved_at_3f0[0x3];
1619 u8 log_max_current_mc_list[0x5];
1620 u8 reserved_at_3f8[0x3];
1621 u8 log_max_current_uc_list[0x5];
1623 u8 general_obj_types[0x40];
1625 u8 sq_ts_format[0x2];
1626 u8 rq_ts_format[0x2];
1627 u8 steering_format_version[0x4];
1628 u8 create_qp_start_hint[0x18];
1630 u8 reserved_at_460[0x3];
1631 u8 log_max_uctx[0x5];
1632 u8 reserved_at_468[0x2];
1633 u8 ipsec_offload[0x1];
1634 u8 log_max_umem[0x5];
1635 u8 max_num_eqs[0x10];
1637 u8 reserved_at_480[0x1];
1640 u8 log_max_l2_table[0x5];
1641 u8 reserved_at_488[0x8];
1642 u8 log_uar_page_sz[0x10];
1644 u8 reserved_at_4a0[0x20];
1645 u8 device_frequency_mhz[0x20];
1646 u8 device_frequency_khz[0x20];
1648 u8 reserved_at_500[0x20];
1649 u8 num_of_uars_per_page[0x20];
1651 u8 flex_parser_protocols[0x20];
1653 u8 max_geneve_tlv_options[0x8];
1654 u8 reserved_at_568[0x3];
1655 u8 max_geneve_tlv_option_data_len[0x5];
1656 u8 reserved_at_570[0x10];
1658 u8 reserved_at_580[0x33];
1659 u8 log_max_dek[0x5];
1660 u8 reserved_at_5b8[0x4];
1661 u8 mini_cqe_resp_stride_index[0x1];
1662 u8 cqe_128_always[0x1];
1663 u8 cqe_compression_128[0x1];
1664 u8 cqe_compression[0x1];
1666 u8 cqe_compression_timeout[0x10];
1667 u8 cqe_compression_max_num[0x10];
1669 u8 reserved_at_5e0[0x8];
1670 u8 flex_parser_id_gtpu_dw_0[0x4];
1671 u8 reserved_at_5ec[0x4];
1672 u8 tag_matching[0x1];
1673 u8 rndv_offload_rc[0x1];
1674 u8 rndv_offload_dc[0x1];
1675 u8 log_tag_matching_list_sz[0x5];
1676 u8 reserved_at_5f8[0x3];
1677 u8 log_max_xrq[0x5];
1679 u8 affiliate_nic_vport_criteria[0x8];
1680 u8 native_port_num[0x8];
1681 u8 num_vhca_ports[0x8];
1682 u8 flex_parser_id_gtpu_teid[0x4];
1683 u8 reserved_at_61c[0x2];
1684 u8 sw_owner_id[0x1];
1685 u8 reserved_at_61f[0x1];
1687 u8 max_num_of_monitor_counters[0x10];
1688 u8 num_ppcnt_monitor_counters[0x10];
1690 u8 max_num_sf[0x10];
1691 u8 num_q_monitor_counters[0x10];
1693 u8 reserved_at_660[0x20];
1696 u8 sf_set_partition[0x1];
1697 u8 reserved_at_682[0x1];
1700 u8 reserved_at_689[0x7];
1701 u8 log_min_sf_size[0x8];
1702 u8 max_num_sf_partitions[0x8];
1706 u8 reserved_at_6c0[0x4];
1707 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1708 u8 flex_parser_id_icmp_dw1[0x4];
1709 u8 flex_parser_id_icmp_dw0[0x4];
1710 u8 flex_parser_id_icmpv6_dw1[0x4];
1711 u8 flex_parser_id_icmpv6_dw0[0x4];
1712 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1713 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1715 u8 reserved_at_6e0[0x10];
1716 u8 sf_base_id[0x10];
1718 u8 flex_parser_id_gtpu_dw_2[0x4];
1719 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4];
1720 u8 num_total_dynamic_vf_msix[0x18];
1721 u8 reserved_at_720[0x14];
1722 u8 dynamic_msix_table_size[0xc];
1723 u8 reserved_at_740[0xc];
1724 u8 min_dynamic_vf_msix_table_size[0x4];
1725 u8 reserved_at_750[0x4];
1726 u8 max_dynamic_vf_msix_table_size[0xc];
1728 u8 reserved_at_760[0x20];
1729 u8 vhca_tunnel_commands[0x40];
1730 u8 reserved_at_7c0[0x40];
1733 enum mlx5_flow_destination_type {
1734 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1735 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1736 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1737 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1739 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1740 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1741 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1744 enum mlx5_flow_table_miss_action {
1745 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1746 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1747 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1750 struct mlx5_ifc_dest_format_struct_bits {
1751 u8 destination_type[0x8];
1752 u8 destination_id[0x18];
1754 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1755 u8 packet_reformat[0x1];
1756 u8 reserved_at_22[0xe];
1757 u8 destination_eswitch_owner_vhca_id[0x10];
1760 struct mlx5_ifc_flow_counter_list_bits {
1761 u8 flow_counter_id[0x20];
1763 u8 reserved_at_20[0x20];
1766 struct mlx5_ifc_extended_dest_format_bits {
1767 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1769 u8 packet_reformat_id[0x20];
1771 u8 reserved_at_60[0x20];
1774 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1775 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1776 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1779 struct mlx5_ifc_fte_match_param_bits {
1780 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1782 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1784 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1786 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1788 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1790 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1792 u8 reserved_at_c00[0x400];
1796 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1797 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1798 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1799 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1800 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1803 struct mlx5_ifc_rx_hash_field_select_bits {
1804 u8 l3_prot_type[0x1];
1805 u8 l4_prot_type[0x1];
1806 u8 selected_fields[0x1e];
1810 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1811 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1815 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1816 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1819 struct mlx5_ifc_wq_bits {
1821 u8 wq_signature[0x1];
1822 u8 end_padding_mode[0x2];
1824 u8 reserved_at_8[0x18];
1826 u8 hds_skip_first_sge[0x1];
1827 u8 log2_hds_buf_size[0x3];
1828 u8 reserved_at_24[0x7];
1829 u8 page_offset[0x5];
1832 u8 reserved_at_40[0x8];
1835 u8 reserved_at_60[0x8];
1840 u8 hw_counter[0x20];
1842 u8 sw_counter[0x20];
1844 u8 reserved_at_100[0xc];
1845 u8 log_wq_stride[0x4];
1846 u8 reserved_at_110[0x3];
1847 u8 log_wq_pg_sz[0x5];
1848 u8 reserved_at_118[0x3];
1851 u8 dbr_umem_valid[0x1];
1852 u8 wq_umem_valid[0x1];
1853 u8 reserved_at_122[0x1];
1854 u8 log_hairpin_num_packets[0x5];
1855 u8 reserved_at_128[0x3];
1856 u8 log_hairpin_data_sz[0x5];
1858 u8 reserved_at_130[0x4];
1859 u8 log_wqe_num_of_strides[0x4];
1860 u8 two_byte_shift_en[0x1];
1861 u8 reserved_at_139[0x4];
1862 u8 log_wqe_stride_size[0x3];
1864 u8 reserved_at_140[0x4c0];
1866 struct mlx5_ifc_cmd_pas_bits pas[];
1869 struct mlx5_ifc_rq_num_bits {
1870 u8 reserved_at_0[0x8];
1874 struct mlx5_ifc_mac_address_layout_bits {
1875 u8 reserved_at_0[0x10];
1876 u8 mac_addr_47_32[0x10];
1878 u8 mac_addr_31_0[0x20];
1881 struct mlx5_ifc_vlan_layout_bits {
1882 u8 reserved_at_0[0x14];
1885 u8 reserved_at_20[0x20];
1888 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1889 u8 reserved_at_0[0xa0];
1891 u8 min_time_between_cnps[0x20];
1893 u8 reserved_at_c0[0x12];
1895 u8 reserved_at_d8[0x4];
1896 u8 cnp_prio_mode[0x1];
1897 u8 cnp_802p_prio[0x3];
1899 u8 reserved_at_e0[0x720];
1902 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1903 u8 reserved_at_0[0x60];
1905 u8 reserved_at_60[0x4];
1906 u8 clamp_tgt_rate[0x1];
1907 u8 reserved_at_65[0x3];
1908 u8 clamp_tgt_rate_after_time_inc[0x1];
1909 u8 reserved_at_69[0x17];
1911 u8 reserved_at_80[0x20];
1913 u8 rpg_time_reset[0x20];
1915 u8 rpg_byte_reset[0x20];
1917 u8 rpg_threshold[0x20];
1919 u8 rpg_max_rate[0x20];
1921 u8 rpg_ai_rate[0x20];
1923 u8 rpg_hai_rate[0x20];
1927 u8 rpg_min_dec_fac[0x20];
1929 u8 rpg_min_rate[0x20];
1931 u8 reserved_at_1c0[0xe0];
1933 u8 rate_to_set_on_first_cnp[0x20];
1937 u8 dce_tcp_rtt[0x20];
1939 u8 rate_reduce_monitor_period[0x20];
1941 u8 reserved_at_320[0x20];
1943 u8 initial_alpha_value[0x20];
1945 u8 reserved_at_360[0x4a0];
1948 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1949 u8 reserved_at_0[0x80];
1951 u8 rppp_max_rps[0x20];
1953 u8 rpg_time_reset[0x20];
1955 u8 rpg_byte_reset[0x20];
1957 u8 rpg_threshold[0x20];
1959 u8 rpg_max_rate[0x20];
1961 u8 rpg_ai_rate[0x20];
1963 u8 rpg_hai_rate[0x20];
1967 u8 rpg_min_dec_fac[0x20];
1969 u8 rpg_min_rate[0x20];
1971 u8 reserved_at_1c0[0x640];
1975 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1976 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1977 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1980 struct mlx5_ifc_resize_field_select_bits {
1981 u8 resize_field_select[0x20];
1984 struct mlx5_ifc_resource_dump_bits {
1986 u8 inline_dump[0x1];
1987 u8 reserved_at_2[0xa];
1989 u8 segment_type[0x10];
1991 u8 reserved_at_20[0x10];
1998 u8 num_of_obj1[0x10];
1999 u8 num_of_obj2[0x10];
2001 u8 reserved_at_a0[0x20];
2003 u8 device_opaque[0x40];
2011 u8 inline_data[52][0x20];
2014 struct mlx5_ifc_resource_dump_menu_record_bits {
2015 u8 reserved_at_0[0x4];
2016 u8 num_of_obj2_supports_active[0x1];
2017 u8 num_of_obj2_supports_all[0x1];
2018 u8 must_have_num_of_obj2[0x1];
2019 u8 support_num_of_obj2[0x1];
2020 u8 num_of_obj1_supports_active[0x1];
2021 u8 num_of_obj1_supports_all[0x1];
2022 u8 must_have_num_of_obj1[0x1];
2023 u8 support_num_of_obj1[0x1];
2024 u8 must_have_index2[0x1];
2025 u8 support_index2[0x1];
2026 u8 must_have_index1[0x1];
2027 u8 support_index1[0x1];
2028 u8 segment_type[0x10];
2030 u8 segment_name[4][0x20];
2032 u8 index1_name[4][0x20];
2034 u8 index2_name[4][0x20];
2037 struct mlx5_ifc_resource_dump_segment_header_bits {
2039 u8 segment_type[0x10];
2042 struct mlx5_ifc_resource_dump_command_segment_bits {
2043 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2045 u8 segment_called[0x10];
2052 u8 num_of_obj1[0x10];
2053 u8 num_of_obj2[0x10];
2056 struct mlx5_ifc_resource_dump_error_segment_bits {
2057 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2059 u8 reserved_at_20[0x10];
2060 u8 syndrome_id[0x10];
2062 u8 reserved_at_40[0x40];
2067 struct mlx5_ifc_resource_dump_info_segment_bits {
2068 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2070 u8 reserved_at_20[0x18];
2071 u8 dump_version[0x8];
2073 u8 hw_version[0x20];
2075 u8 fw_version[0x20];
2078 struct mlx5_ifc_resource_dump_menu_segment_bits {
2079 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2081 u8 reserved_at_20[0x10];
2082 u8 num_of_records[0x10];
2084 struct mlx5_ifc_resource_dump_menu_record_bits record[];
2087 struct mlx5_ifc_resource_dump_resource_segment_bits {
2088 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2090 u8 reserved_at_20[0x20];
2099 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2100 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2103 struct mlx5_ifc_menu_resource_dump_response_bits {
2104 struct mlx5_ifc_resource_dump_info_segment_bits info;
2105 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2106 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2107 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2111 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2112 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2113 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2114 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2117 struct mlx5_ifc_modify_field_select_bits {
2118 u8 modify_field_select[0x20];
2121 struct mlx5_ifc_field_select_r_roce_np_bits {
2122 u8 field_select_r_roce_np[0x20];
2125 struct mlx5_ifc_field_select_r_roce_rp_bits {
2126 u8 field_select_r_roce_rp[0x20];
2130 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2131 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2132 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2133 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2134 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2135 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2136 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2137 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2138 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2139 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2142 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2143 u8 field_select_8021qaurp[0x20];
2146 struct mlx5_ifc_phys_layer_cntrs_bits {
2147 u8 time_since_last_clear_high[0x20];
2149 u8 time_since_last_clear_low[0x20];
2151 u8 symbol_errors_high[0x20];
2153 u8 symbol_errors_low[0x20];
2155 u8 sync_headers_errors_high[0x20];
2157 u8 sync_headers_errors_low[0x20];
2159 u8 edpl_bip_errors_lane0_high[0x20];
2161 u8 edpl_bip_errors_lane0_low[0x20];
2163 u8 edpl_bip_errors_lane1_high[0x20];
2165 u8 edpl_bip_errors_lane1_low[0x20];
2167 u8 edpl_bip_errors_lane2_high[0x20];
2169 u8 edpl_bip_errors_lane2_low[0x20];
2171 u8 edpl_bip_errors_lane3_high[0x20];
2173 u8 edpl_bip_errors_lane3_low[0x20];
2175 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2177 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2179 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2181 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2183 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2185 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2187 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2189 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2191 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2193 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2195 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2197 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2199 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2201 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2203 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2205 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2207 u8 rs_fec_corrected_blocks_high[0x20];
2209 u8 rs_fec_corrected_blocks_low[0x20];
2211 u8 rs_fec_uncorrectable_blocks_high[0x20];
2213 u8 rs_fec_uncorrectable_blocks_low[0x20];
2215 u8 rs_fec_no_errors_blocks_high[0x20];
2217 u8 rs_fec_no_errors_blocks_low[0x20];
2219 u8 rs_fec_single_error_blocks_high[0x20];
2221 u8 rs_fec_single_error_blocks_low[0x20];
2223 u8 rs_fec_corrected_symbols_total_high[0x20];
2225 u8 rs_fec_corrected_symbols_total_low[0x20];
2227 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2229 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2231 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2233 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2235 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2237 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2239 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2241 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2243 u8 link_down_events[0x20];
2245 u8 successful_recovery_events[0x20];
2247 u8 reserved_at_640[0x180];
2250 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2251 u8 time_since_last_clear_high[0x20];
2253 u8 time_since_last_clear_low[0x20];
2255 u8 phy_received_bits_high[0x20];
2257 u8 phy_received_bits_low[0x20];
2259 u8 phy_symbol_errors_high[0x20];
2261 u8 phy_symbol_errors_low[0x20];
2263 u8 phy_corrected_bits_high[0x20];
2265 u8 phy_corrected_bits_low[0x20];
2267 u8 phy_corrected_bits_lane0_high[0x20];
2269 u8 phy_corrected_bits_lane0_low[0x20];
2271 u8 phy_corrected_bits_lane1_high[0x20];
2273 u8 phy_corrected_bits_lane1_low[0x20];
2275 u8 phy_corrected_bits_lane2_high[0x20];
2277 u8 phy_corrected_bits_lane2_low[0x20];
2279 u8 phy_corrected_bits_lane3_high[0x20];
2281 u8 phy_corrected_bits_lane3_low[0x20];
2283 u8 reserved_at_200[0x5c0];
2286 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2287 u8 symbol_error_counter[0x10];
2289 u8 link_error_recovery_counter[0x8];
2291 u8 link_downed_counter[0x8];
2293 u8 port_rcv_errors[0x10];
2295 u8 port_rcv_remote_physical_errors[0x10];
2297 u8 port_rcv_switch_relay_errors[0x10];
2299 u8 port_xmit_discards[0x10];
2301 u8 port_xmit_constraint_errors[0x8];
2303 u8 port_rcv_constraint_errors[0x8];
2305 u8 reserved_at_70[0x8];
2307 u8 link_overrun_errors[0x8];
2309 u8 reserved_at_80[0x10];
2311 u8 vl_15_dropped[0x10];
2313 u8 reserved_at_a0[0x80];
2315 u8 port_xmit_wait[0x20];
2318 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2319 u8 transmit_queue_high[0x20];
2321 u8 transmit_queue_low[0x20];
2323 u8 no_buffer_discard_uc_high[0x20];
2325 u8 no_buffer_discard_uc_low[0x20];
2327 u8 reserved_at_80[0x740];
2330 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2331 u8 wred_discard_high[0x20];
2333 u8 wred_discard_low[0x20];
2335 u8 ecn_marked_tc_high[0x20];
2337 u8 ecn_marked_tc_low[0x20];
2339 u8 reserved_at_80[0x740];
2342 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2343 u8 rx_octets_high[0x20];
2345 u8 rx_octets_low[0x20];
2347 u8 reserved_at_40[0xc0];
2349 u8 rx_frames_high[0x20];
2351 u8 rx_frames_low[0x20];
2353 u8 tx_octets_high[0x20];
2355 u8 tx_octets_low[0x20];
2357 u8 reserved_at_180[0xc0];
2359 u8 tx_frames_high[0x20];
2361 u8 tx_frames_low[0x20];
2363 u8 rx_pause_high[0x20];
2365 u8 rx_pause_low[0x20];
2367 u8 rx_pause_duration_high[0x20];
2369 u8 rx_pause_duration_low[0x20];
2371 u8 tx_pause_high[0x20];
2373 u8 tx_pause_low[0x20];
2375 u8 tx_pause_duration_high[0x20];
2377 u8 tx_pause_duration_low[0x20];
2379 u8 rx_pause_transition_high[0x20];
2381 u8 rx_pause_transition_low[0x20];
2383 u8 rx_discards_high[0x20];
2385 u8 rx_discards_low[0x20];
2387 u8 device_stall_minor_watermark_cnt_high[0x20];
2389 u8 device_stall_minor_watermark_cnt_low[0x20];
2391 u8 device_stall_critical_watermark_cnt_high[0x20];
2393 u8 device_stall_critical_watermark_cnt_low[0x20];
2395 u8 reserved_at_480[0x340];
2398 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2399 u8 port_transmit_wait_high[0x20];
2401 u8 port_transmit_wait_low[0x20];
2403 u8 reserved_at_40[0x100];
2405 u8 rx_buffer_almost_full_high[0x20];
2407 u8 rx_buffer_almost_full_low[0x20];
2409 u8 rx_buffer_full_high[0x20];
2411 u8 rx_buffer_full_low[0x20];
2413 u8 rx_icrc_encapsulated_high[0x20];
2415 u8 rx_icrc_encapsulated_low[0x20];
2417 u8 reserved_at_200[0x5c0];
2420 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2421 u8 dot3stats_alignment_errors_high[0x20];
2423 u8 dot3stats_alignment_errors_low[0x20];
2425 u8 dot3stats_fcs_errors_high[0x20];
2427 u8 dot3stats_fcs_errors_low[0x20];
2429 u8 dot3stats_single_collision_frames_high[0x20];
2431 u8 dot3stats_single_collision_frames_low[0x20];
2433 u8 dot3stats_multiple_collision_frames_high[0x20];
2435 u8 dot3stats_multiple_collision_frames_low[0x20];
2437 u8 dot3stats_sqe_test_errors_high[0x20];
2439 u8 dot3stats_sqe_test_errors_low[0x20];
2441 u8 dot3stats_deferred_transmissions_high[0x20];
2443 u8 dot3stats_deferred_transmissions_low[0x20];
2445 u8 dot3stats_late_collisions_high[0x20];
2447 u8 dot3stats_late_collisions_low[0x20];
2449 u8 dot3stats_excessive_collisions_high[0x20];
2451 u8 dot3stats_excessive_collisions_low[0x20];
2453 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2455 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2457 u8 dot3stats_carrier_sense_errors_high[0x20];
2459 u8 dot3stats_carrier_sense_errors_low[0x20];
2461 u8 dot3stats_frame_too_longs_high[0x20];
2463 u8 dot3stats_frame_too_longs_low[0x20];
2465 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2467 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2469 u8 dot3stats_symbol_errors_high[0x20];
2471 u8 dot3stats_symbol_errors_low[0x20];
2473 u8 dot3control_in_unknown_opcodes_high[0x20];
2475 u8 dot3control_in_unknown_opcodes_low[0x20];
2477 u8 dot3in_pause_frames_high[0x20];
2479 u8 dot3in_pause_frames_low[0x20];
2481 u8 dot3out_pause_frames_high[0x20];
2483 u8 dot3out_pause_frames_low[0x20];
2485 u8 reserved_at_400[0x3c0];
2488 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2489 u8 ether_stats_drop_events_high[0x20];
2491 u8 ether_stats_drop_events_low[0x20];
2493 u8 ether_stats_octets_high[0x20];
2495 u8 ether_stats_octets_low[0x20];
2497 u8 ether_stats_pkts_high[0x20];
2499 u8 ether_stats_pkts_low[0x20];
2501 u8 ether_stats_broadcast_pkts_high[0x20];
2503 u8 ether_stats_broadcast_pkts_low[0x20];
2505 u8 ether_stats_multicast_pkts_high[0x20];
2507 u8 ether_stats_multicast_pkts_low[0x20];
2509 u8 ether_stats_crc_align_errors_high[0x20];
2511 u8 ether_stats_crc_align_errors_low[0x20];
2513 u8 ether_stats_undersize_pkts_high[0x20];
2515 u8 ether_stats_undersize_pkts_low[0x20];
2517 u8 ether_stats_oversize_pkts_high[0x20];
2519 u8 ether_stats_oversize_pkts_low[0x20];
2521 u8 ether_stats_fragments_high[0x20];
2523 u8 ether_stats_fragments_low[0x20];
2525 u8 ether_stats_jabbers_high[0x20];
2527 u8 ether_stats_jabbers_low[0x20];
2529 u8 ether_stats_collisions_high[0x20];
2531 u8 ether_stats_collisions_low[0x20];
2533 u8 ether_stats_pkts64octets_high[0x20];
2535 u8 ether_stats_pkts64octets_low[0x20];
2537 u8 ether_stats_pkts65to127octets_high[0x20];
2539 u8 ether_stats_pkts65to127octets_low[0x20];
2541 u8 ether_stats_pkts128to255octets_high[0x20];
2543 u8 ether_stats_pkts128to255octets_low[0x20];
2545 u8 ether_stats_pkts256to511octets_high[0x20];
2547 u8 ether_stats_pkts256to511octets_low[0x20];
2549 u8 ether_stats_pkts512to1023octets_high[0x20];
2551 u8 ether_stats_pkts512to1023octets_low[0x20];
2553 u8 ether_stats_pkts1024to1518octets_high[0x20];
2555 u8 ether_stats_pkts1024to1518octets_low[0x20];
2557 u8 ether_stats_pkts1519to2047octets_high[0x20];
2559 u8 ether_stats_pkts1519to2047octets_low[0x20];
2561 u8 ether_stats_pkts2048to4095octets_high[0x20];
2563 u8 ether_stats_pkts2048to4095octets_low[0x20];
2565 u8 ether_stats_pkts4096to8191octets_high[0x20];
2567 u8 ether_stats_pkts4096to8191octets_low[0x20];
2569 u8 ether_stats_pkts8192to10239octets_high[0x20];
2571 u8 ether_stats_pkts8192to10239octets_low[0x20];
2573 u8 reserved_at_540[0x280];
2576 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2577 u8 if_in_octets_high[0x20];
2579 u8 if_in_octets_low[0x20];
2581 u8 if_in_ucast_pkts_high[0x20];
2583 u8 if_in_ucast_pkts_low[0x20];
2585 u8 if_in_discards_high[0x20];
2587 u8 if_in_discards_low[0x20];
2589 u8 if_in_errors_high[0x20];
2591 u8 if_in_errors_low[0x20];
2593 u8 if_in_unknown_protos_high[0x20];
2595 u8 if_in_unknown_protos_low[0x20];
2597 u8 if_out_octets_high[0x20];
2599 u8 if_out_octets_low[0x20];
2601 u8 if_out_ucast_pkts_high[0x20];
2603 u8 if_out_ucast_pkts_low[0x20];
2605 u8 if_out_discards_high[0x20];
2607 u8 if_out_discards_low[0x20];
2609 u8 if_out_errors_high[0x20];
2611 u8 if_out_errors_low[0x20];
2613 u8 if_in_multicast_pkts_high[0x20];
2615 u8 if_in_multicast_pkts_low[0x20];
2617 u8 if_in_broadcast_pkts_high[0x20];
2619 u8 if_in_broadcast_pkts_low[0x20];
2621 u8 if_out_multicast_pkts_high[0x20];
2623 u8 if_out_multicast_pkts_low[0x20];
2625 u8 if_out_broadcast_pkts_high[0x20];
2627 u8 if_out_broadcast_pkts_low[0x20];
2629 u8 reserved_at_340[0x480];
2632 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2633 u8 a_frames_transmitted_ok_high[0x20];
2635 u8 a_frames_transmitted_ok_low[0x20];
2637 u8 a_frames_received_ok_high[0x20];
2639 u8 a_frames_received_ok_low[0x20];
2641 u8 a_frame_check_sequence_errors_high[0x20];
2643 u8 a_frame_check_sequence_errors_low[0x20];
2645 u8 a_alignment_errors_high[0x20];
2647 u8 a_alignment_errors_low[0x20];
2649 u8 a_octets_transmitted_ok_high[0x20];
2651 u8 a_octets_transmitted_ok_low[0x20];
2653 u8 a_octets_received_ok_high[0x20];
2655 u8 a_octets_received_ok_low[0x20];
2657 u8 a_multicast_frames_xmitted_ok_high[0x20];
2659 u8 a_multicast_frames_xmitted_ok_low[0x20];
2661 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2663 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2665 u8 a_multicast_frames_received_ok_high[0x20];
2667 u8 a_multicast_frames_received_ok_low[0x20];
2669 u8 a_broadcast_frames_received_ok_high[0x20];
2671 u8 a_broadcast_frames_received_ok_low[0x20];
2673 u8 a_in_range_length_errors_high[0x20];
2675 u8 a_in_range_length_errors_low[0x20];
2677 u8 a_out_of_range_length_field_high[0x20];
2679 u8 a_out_of_range_length_field_low[0x20];
2681 u8 a_frame_too_long_errors_high[0x20];
2683 u8 a_frame_too_long_errors_low[0x20];
2685 u8 a_symbol_error_during_carrier_high[0x20];
2687 u8 a_symbol_error_during_carrier_low[0x20];
2689 u8 a_mac_control_frames_transmitted_high[0x20];
2691 u8 a_mac_control_frames_transmitted_low[0x20];
2693 u8 a_mac_control_frames_received_high[0x20];
2695 u8 a_mac_control_frames_received_low[0x20];
2697 u8 a_unsupported_opcodes_received_high[0x20];
2699 u8 a_unsupported_opcodes_received_low[0x20];
2701 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2703 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2705 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2707 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2709 u8 reserved_at_4c0[0x300];
2712 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2713 u8 life_time_counter_high[0x20];
2715 u8 life_time_counter_low[0x20];
2721 u8 l0_to_recovery_eieos[0x20];
2723 u8 l0_to_recovery_ts[0x20];
2725 u8 l0_to_recovery_framing[0x20];
2727 u8 l0_to_recovery_retrain[0x20];
2729 u8 crc_error_dllp[0x20];
2731 u8 crc_error_tlp[0x20];
2733 u8 tx_overflow_buffer_pkt_high[0x20];
2735 u8 tx_overflow_buffer_pkt_low[0x20];
2737 u8 outbound_stalled_reads[0x20];
2739 u8 outbound_stalled_writes[0x20];
2741 u8 outbound_stalled_reads_events[0x20];
2743 u8 outbound_stalled_writes_events[0x20];
2745 u8 reserved_at_200[0x5c0];
2748 struct mlx5_ifc_cmd_inter_comp_event_bits {
2749 u8 command_completion_vector[0x20];
2751 u8 reserved_at_20[0xc0];
2754 struct mlx5_ifc_stall_vl_event_bits {
2755 u8 reserved_at_0[0x18];
2757 u8 reserved_at_19[0x3];
2760 u8 reserved_at_20[0xa0];
2763 struct mlx5_ifc_db_bf_congestion_event_bits {
2764 u8 event_subtype[0x8];
2765 u8 reserved_at_8[0x8];
2766 u8 congestion_level[0x8];
2767 u8 reserved_at_18[0x8];
2769 u8 reserved_at_20[0xa0];
2772 struct mlx5_ifc_gpio_event_bits {
2773 u8 reserved_at_0[0x60];
2775 u8 gpio_event_hi[0x20];
2777 u8 gpio_event_lo[0x20];
2779 u8 reserved_at_a0[0x40];
2782 struct mlx5_ifc_port_state_change_event_bits {
2783 u8 reserved_at_0[0x40];
2786 u8 reserved_at_44[0x1c];
2788 u8 reserved_at_60[0x80];
2791 struct mlx5_ifc_dropped_packet_logged_bits {
2792 u8 reserved_at_0[0xe0];
2796 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2797 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2800 struct mlx5_ifc_cq_error_bits {
2801 u8 reserved_at_0[0x8];
2804 u8 reserved_at_20[0x20];
2806 u8 reserved_at_40[0x18];
2809 u8 reserved_at_60[0x80];
2812 struct mlx5_ifc_rdma_page_fault_event_bits {
2813 u8 bytes_committed[0x20];
2817 u8 reserved_at_40[0x10];
2818 u8 packet_len[0x10];
2820 u8 rdma_op_len[0x20];
2824 u8 reserved_at_c0[0x5];
2831 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2832 u8 bytes_committed[0x20];
2834 u8 reserved_at_20[0x10];
2837 u8 reserved_at_40[0x10];
2840 u8 reserved_at_60[0x60];
2842 u8 reserved_at_c0[0x5];
2849 struct mlx5_ifc_qp_events_bits {
2850 u8 reserved_at_0[0xa0];
2853 u8 reserved_at_a8[0x18];
2855 u8 reserved_at_c0[0x8];
2856 u8 qpn_rqn_sqn[0x18];
2859 struct mlx5_ifc_dct_events_bits {
2860 u8 reserved_at_0[0xc0];
2862 u8 reserved_at_c0[0x8];
2863 u8 dct_number[0x18];
2866 struct mlx5_ifc_comp_event_bits {
2867 u8 reserved_at_0[0xc0];
2869 u8 reserved_at_c0[0x8];
2874 MLX5_QPC_STATE_RST = 0x0,
2875 MLX5_QPC_STATE_INIT = 0x1,
2876 MLX5_QPC_STATE_RTR = 0x2,
2877 MLX5_QPC_STATE_RTS = 0x3,
2878 MLX5_QPC_STATE_SQER = 0x4,
2879 MLX5_QPC_STATE_ERR = 0x6,
2880 MLX5_QPC_STATE_SQD = 0x7,
2881 MLX5_QPC_STATE_SUSPENDED = 0x9,
2885 MLX5_QPC_ST_RC = 0x0,
2886 MLX5_QPC_ST_UC = 0x1,
2887 MLX5_QPC_ST_UD = 0x2,
2888 MLX5_QPC_ST_XRC = 0x3,
2889 MLX5_QPC_ST_DCI = 0x5,
2890 MLX5_QPC_ST_QP0 = 0x7,
2891 MLX5_QPC_ST_QP1 = 0x8,
2892 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2893 MLX5_QPC_ST_REG_UMR = 0xc,
2897 MLX5_QPC_PM_STATE_ARMED = 0x0,
2898 MLX5_QPC_PM_STATE_REARM = 0x1,
2899 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2900 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2904 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2908 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2909 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2913 MLX5_QPC_MTU_256_BYTES = 0x1,
2914 MLX5_QPC_MTU_512_BYTES = 0x2,
2915 MLX5_QPC_MTU_1K_BYTES = 0x3,
2916 MLX5_QPC_MTU_2K_BYTES = 0x4,
2917 MLX5_QPC_MTU_4K_BYTES = 0x5,
2918 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2922 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2923 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2924 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2925 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2926 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2927 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2928 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2929 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2933 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2934 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2935 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2939 MLX5_QPC_CS_RES_DISABLE = 0x0,
2940 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2941 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2945 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2946 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
2947 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
2950 struct mlx5_ifc_qpc_bits {
2952 u8 lag_tx_port_affinity[0x4];
2954 u8 reserved_at_10[0x2];
2955 u8 isolate_vl_tc[0x1];
2957 u8 reserved_at_15[0x1];
2958 u8 req_e2e_credit_mode[0x2];
2959 u8 offload_type[0x4];
2960 u8 end_padding_mode[0x2];
2961 u8 reserved_at_1e[0x2];
2963 u8 wq_signature[0x1];
2964 u8 block_lb_mc[0x1];
2965 u8 atomic_like_write_en[0x1];
2966 u8 latency_sensitive[0x1];
2967 u8 reserved_at_24[0x1];
2968 u8 drain_sigerr[0x1];
2969 u8 reserved_at_26[0x2];
2973 u8 log_msg_max[0x5];
2974 u8 reserved_at_48[0x1];
2975 u8 log_rq_size[0x4];
2976 u8 log_rq_stride[0x3];
2978 u8 log_sq_size[0x4];
2979 u8 reserved_at_55[0x3];
2981 u8 reserved_at_5a[0x1];
2983 u8 ulp_stateless_offload_mode[0x4];
2985 u8 counter_set_id[0x8];
2988 u8 reserved_at_80[0x8];
2989 u8 user_index[0x18];
2991 u8 reserved_at_a0[0x3];
2992 u8 log_page_size[0x5];
2993 u8 remote_qpn[0x18];
2995 struct mlx5_ifc_ads_bits primary_address_path;
2997 struct mlx5_ifc_ads_bits secondary_address_path;
2999 u8 log_ack_req_freq[0x4];
3000 u8 reserved_at_384[0x4];
3001 u8 log_sra_max[0x3];
3002 u8 reserved_at_38b[0x2];
3003 u8 retry_count[0x3];
3005 u8 reserved_at_393[0x1];
3007 u8 cur_rnr_retry[0x3];
3008 u8 cur_retry_count[0x3];
3009 u8 reserved_at_39b[0x5];
3011 u8 reserved_at_3a0[0x20];
3013 u8 reserved_at_3c0[0x8];
3014 u8 next_send_psn[0x18];
3016 u8 reserved_at_3e0[0x8];
3019 u8 reserved_at_400[0x8];
3022 u8 reserved_at_420[0x20];
3024 u8 reserved_at_440[0x8];
3025 u8 last_acked_psn[0x18];
3027 u8 reserved_at_460[0x8];
3030 u8 reserved_at_480[0x8];
3031 u8 log_rra_max[0x3];
3032 u8 reserved_at_48b[0x1];
3033 u8 atomic_mode[0x4];
3037 u8 reserved_at_493[0x1];
3038 u8 page_offset[0x6];
3039 u8 reserved_at_49a[0x3];
3040 u8 cd_slave_receive[0x1];
3041 u8 cd_slave_send[0x1];
3044 u8 reserved_at_4a0[0x3];
3045 u8 min_rnr_nak[0x5];
3046 u8 next_rcv_psn[0x18];
3048 u8 reserved_at_4c0[0x8];
3051 u8 reserved_at_4e0[0x8];
3058 u8 reserved_at_560[0x5];
3060 u8 srqn_rmpn_xrqn[0x18];
3062 u8 reserved_at_580[0x8];
3065 u8 hw_sq_wqebb_counter[0x10];
3066 u8 sw_sq_wqebb_counter[0x10];
3068 u8 hw_rq_counter[0x20];
3070 u8 sw_rq_counter[0x20];
3072 u8 reserved_at_600[0x20];
3074 u8 reserved_at_620[0xf];
3079 u8 dc_access_key[0x40];
3081 u8 reserved_at_680[0x3];
3082 u8 dbr_umem_valid[0x1];
3084 u8 reserved_at_684[0xbc];
3087 struct mlx5_ifc_roce_addr_layout_bits {
3088 u8 source_l3_address[16][0x8];
3090 u8 reserved_at_80[0x3];
3093 u8 source_mac_47_32[0x10];
3095 u8 source_mac_31_0[0x20];
3097 u8 reserved_at_c0[0x14];
3098 u8 roce_l3_type[0x4];
3099 u8 roce_version[0x8];
3101 u8 reserved_at_e0[0x20];
3104 union mlx5_ifc_hca_cap_union_bits {
3105 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3106 struct mlx5_ifc_odp_cap_bits odp_cap;
3107 struct mlx5_ifc_atomic_caps_bits atomic_caps;
3108 struct mlx5_ifc_roce_cap_bits roce_cap;
3109 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3110 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3111 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3112 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3113 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3114 struct mlx5_ifc_qos_cap_bits qos_cap;
3115 struct mlx5_ifc_debug_cap_bits debug_cap;
3116 struct mlx5_ifc_fpga_cap_bits fpga_cap;
3117 struct mlx5_ifc_tls_cap_bits tls_cap;
3118 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3119 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3120 u8 reserved_at_0[0x8000];
3124 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3125 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3126 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
3127 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
3128 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3129 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
3130 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
3131 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3132 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3133 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3134 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3135 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3136 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3140 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3141 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3142 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3145 struct mlx5_ifc_vlan_bits {
3152 struct mlx5_ifc_flow_context_bits {
3153 struct mlx5_ifc_vlan_bits push_vlan;
3157 u8 reserved_at_40[0x8];
3160 u8 reserved_at_60[0x10];
3163 u8 extended_destination[0x1];
3164 u8 reserved_at_81[0x1];
3165 u8 flow_source[0x2];
3166 u8 reserved_at_84[0x4];
3167 u8 destination_list_size[0x18];
3169 u8 reserved_at_a0[0x8];
3170 u8 flow_counter_list_size[0x18];
3172 u8 packet_reformat_id[0x20];
3174 u8 modify_header_id[0x20];
3176 struct mlx5_ifc_vlan_bits push_vlan_2;
3178 u8 ipsec_obj_id[0x20];
3179 u8 reserved_at_140[0xc0];
3181 struct mlx5_ifc_fte_match_param_bits match_value;
3183 u8 reserved_at_1200[0x600];
3185 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3189 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3190 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3193 struct mlx5_ifc_xrc_srqc_bits {
3195 u8 log_xrc_srq_size[0x4];
3196 u8 reserved_at_8[0x18];
3198 u8 wq_signature[0x1];
3200 u8 reserved_at_22[0x1];
3202 u8 basic_cyclic_rcv_wqe[0x1];
3203 u8 log_rq_stride[0x3];
3206 u8 page_offset[0x6];
3207 u8 reserved_at_46[0x1];
3208 u8 dbr_umem_valid[0x1];
3211 u8 reserved_at_60[0x20];
3213 u8 user_index_equal_xrc_srqn[0x1];
3214 u8 reserved_at_81[0x1];
3215 u8 log_page_size[0x6];
3216 u8 user_index[0x18];
3218 u8 reserved_at_a0[0x20];
3220 u8 reserved_at_c0[0x8];
3226 u8 reserved_at_100[0x40];
3228 u8 db_record_addr_h[0x20];
3230 u8 db_record_addr_l[0x1e];
3231 u8 reserved_at_17e[0x2];
3233 u8 reserved_at_180[0x80];
3236 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3237 u8 counter_error_queues[0x20];
3239 u8 total_error_queues[0x20];
3241 u8 send_queue_priority_update_flow[0x20];
3243 u8 reserved_at_60[0x20];
3245 u8 nic_receive_steering_discard[0x40];
3247 u8 receive_discard_vport_down[0x40];
3249 u8 transmit_discard_vport_down[0x40];
3251 u8 reserved_at_140[0xa0];
3253 u8 internal_rq_out_of_buffer[0x20];
3255 u8 reserved_at_200[0xe00];
3258 struct mlx5_ifc_traffic_counter_bits {
3264 struct mlx5_ifc_tisc_bits {
3265 u8 strict_lag_tx_port_affinity[0x1];
3267 u8 reserved_at_2[0x2];
3268 u8 lag_tx_port_affinity[0x04];
3270 u8 reserved_at_8[0x4];
3272 u8 reserved_at_10[0x10];
3274 u8 reserved_at_20[0x100];
3276 u8 reserved_at_120[0x8];
3277 u8 transport_domain[0x18];
3279 u8 reserved_at_140[0x8];
3280 u8 underlay_qpn[0x18];
3282 u8 reserved_at_160[0x8];
3285 u8 reserved_at_180[0x380];
3289 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3290 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3294 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
3295 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
3299 MLX5_RX_HASH_FN_NONE = 0x0,
3300 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3301 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
3305 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3306 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
3309 struct mlx5_ifc_tirc_bits {
3310 u8 reserved_at_0[0x20];
3314 u8 reserved_at_25[0x1b];
3316 u8 reserved_at_40[0x40];
3318 u8 reserved_at_80[0x4];
3319 u8 lro_timeout_period_usecs[0x10];
3320 u8 lro_enable_mask[0x4];
3321 u8 lro_max_ip_payload_size[0x8];
3323 u8 reserved_at_a0[0x40];
3325 u8 reserved_at_e0[0x8];
3326 u8 inline_rqn[0x18];
3328 u8 rx_hash_symmetric[0x1];
3329 u8 reserved_at_101[0x1];
3330 u8 tunneled_offload_en[0x1];
3331 u8 reserved_at_103[0x5];
3332 u8 indirect_table[0x18];
3335 u8 reserved_at_124[0x2];
3336 u8 self_lb_block[0x2];
3337 u8 transport_domain[0x18];
3339 u8 rx_hash_toeplitz_key[10][0x20];
3341 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3343 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3345 u8 reserved_at_2c0[0x4c0];
3349 MLX5_SRQC_STATE_GOOD = 0x0,
3350 MLX5_SRQC_STATE_ERROR = 0x1,
3353 struct mlx5_ifc_srqc_bits {
3355 u8 log_srq_size[0x4];
3356 u8 reserved_at_8[0x18];
3358 u8 wq_signature[0x1];
3360 u8 reserved_at_22[0x1];
3362 u8 reserved_at_24[0x1];
3363 u8 log_rq_stride[0x3];
3366 u8 page_offset[0x6];
3367 u8 reserved_at_46[0x2];
3370 u8 reserved_at_60[0x20];
3372 u8 reserved_at_80[0x2];
3373 u8 log_page_size[0x6];
3374 u8 reserved_at_88[0x18];
3376 u8 reserved_at_a0[0x20];
3378 u8 reserved_at_c0[0x8];
3384 u8 reserved_at_100[0x40];
3388 u8 reserved_at_180[0x80];
3392 MLX5_SQC_STATE_RST = 0x0,
3393 MLX5_SQC_STATE_RDY = 0x1,
3394 MLX5_SQC_STATE_ERR = 0x3,
3398 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3399 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
3400 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
3403 struct mlx5_ifc_sqc_bits {
3407 u8 flush_in_error_en[0x1];
3408 u8 allow_multi_pkt_send_wqe[0x1];
3409 u8 min_wqe_inline_mode[0x3];
3414 u8 reserved_at_f[0xb];
3416 u8 reserved_at_1c[0x4];
3418 u8 reserved_at_20[0x8];
3419 u8 user_index[0x18];
3421 u8 reserved_at_40[0x8];
3424 u8 reserved_at_60[0x8];
3425 u8 hairpin_peer_rq[0x18];
3427 u8 reserved_at_80[0x10];
3428 u8 hairpin_peer_vhca[0x10];
3430 u8 reserved_at_a0[0x20];
3432 u8 reserved_at_c0[0x8];
3433 u8 ts_cqe_to_dest_cqn[0x18];
3435 u8 reserved_at_e0[0x10];
3436 u8 packet_pacing_rate_limit_index[0x10];
3437 u8 tis_lst_sz[0x10];
3438 u8 qos_queue_group_id[0x10];
3440 u8 reserved_at_120[0x40];
3442 u8 reserved_at_160[0x8];
3445 struct mlx5_ifc_wq_bits wq;
3449 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3450 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3451 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3452 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3453 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3457 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3458 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3459 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3460 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3463 struct mlx5_ifc_scheduling_context_bits {
3464 u8 element_type[0x8];
3465 u8 reserved_at_8[0x18];
3467 u8 element_attributes[0x20];
3469 u8 parent_element_id[0x20];
3471 u8 reserved_at_60[0x40];
3475 u8 max_average_bw[0x20];
3477 u8 reserved_at_e0[0x120];
3480 struct mlx5_ifc_rqtc_bits {
3481 u8 reserved_at_0[0xa0];
3483 u8 reserved_at_a0[0x5];
3484 u8 list_q_type[0x3];
3485 u8 reserved_at_a8[0x8];
3486 u8 rqt_max_size[0x10];
3488 u8 rq_vhca_id_format[0x1];
3489 u8 reserved_at_c1[0xf];
3490 u8 rqt_actual_size[0x10];
3492 u8 reserved_at_e0[0x6a0];
3494 struct mlx5_ifc_rq_num_bits rq_num[];
3498 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3499 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3503 MLX5_RQC_STATE_RST = 0x0,
3504 MLX5_RQC_STATE_RDY = 0x1,
3505 MLX5_RQC_STATE_ERR = 0x3,
3509 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3510 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
3511 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
3514 struct mlx5_ifc_rqc_bits {
3516 u8 delay_drop_en[0x1];
3517 u8 scatter_fcs[0x1];
3519 u8 mem_rq_type[0x4];
3521 u8 reserved_at_c[0x1];
3522 u8 flush_in_error_en[0x1];
3524 u8 reserved_at_f[0xb];
3526 u8 reserved_at_1c[0x4];
3528 u8 reserved_at_20[0x8];
3529 u8 user_index[0x18];
3531 u8 reserved_at_40[0x8];
3534 u8 counter_set_id[0x8];
3535 u8 reserved_at_68[0x18];
3537 u8 reserved_at_80[0x8];
3540 u8 reserved_at_a0[0x8];
3541 u8 hairpin_peer_sq[0x18];
3543 u8 reserved_at_c0[0x10];
3544 u8 hairpin_peer_vhca[0x10];
3546 u8 reserved_at_e0[0xa0];
3548 struct mlx5_ifc_wq_bits wq;
3552 MLX5_RMPC_STATE_RDY = 0x1,
3553 MLX5_RMPC_STATE_ERR = 0x3,
3556 struct mlx5_ifc_rmpc_bits {
3557 u8 reserved_at_0[0x8];
3559 u8 reserved_at_c[0x14];
3561 u8 basic_cyclic_rcv_wqe[0x1];
3562 u8 reserved_at_21[0x1f];
3564 u8 reserved_at_40[0x140];
3566 struct mlx5_ifc_wq_bits wq;
3569 struct mlx5_ifc_nic_vport_context_bits {
3570 u8 reserved_at_0[0x5];
3571 u8 min_wqe_inline_mode[0x3];
3572 u8 reserved_at_8[0x15];
3573 u8 disable_mc_local_lb[0x1];
3574 u8 disable_uc_local_lb[0x1];
3577 u8 arm_change_event[0x1];
3578 u8 reserved_at_21[0x1a];
3579 u8 event_on_mtu[0x1];
3580 u8 event_on_promisc_change[0x1];
3581 u8 event_on_vlan_change[0x1];
3582 u8 event_on_mc_address_change[0x1];
3583 u8 event_on_uc_address_change[0x1];
3585 u8 reserved_at_40[0xc];
3587 u8 affiliation_criteria[0x4];
3588 u8 affiliated_vhca_id[0x10];
3590 u8 reserved_at_60[0xd0];
3594 u8 system_image_guid[0x40];
3598 u8 reserved_at_200[0x140];
3599 u8 qkey_violation_counter[0x10];
3600 u8 reserved_at_350[0x430];
3604 u8 promisc_all[0x1];
3605 u8 reserved_at_783[0x2];
3606 u8 allowed_list_type[0x3];
3607 u8 reserved_at_788[0xc];
3608 u8 allowed_list_size[0xc];
3610 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3612 u8 reserved_at_7e0[0x20];
3614 u8 current_uc_mac_address[][0x40];
3618 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3619 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3620 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3621 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3622 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3623 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3626 struct mlx5_ifc_mkc_bits {
3627 u8 reserved_at_0[0x1];
3629 u8 reserved_at_2[0x1];
3630 u8 access_mode_4_2[0x3];
3631 u8 reserved_at_6[0x7];
3632 u8 relaxed_ordering_write[0x1];
3633 u8 reserved_at_e[0x1];
3634 u8 small_fence_on_rdma_read_response[0x1];
3641 u8 access_mode_1_0[0x2];
3642 u8 reserved_at_18[0x8];
3647 u8 reserved_at_40[0x20];
3652 u8 reserved_at_63[0x2];
3653 u8 expected_sigerr_count[0x1];
3654 u8 reserved_at_66[0x1];
3658 u8 start_addr[0x40];
3662 u8 bsf_octword_size[0x20];
3664 u8 reserved_at_120[0x80];
3666 u8 translations_octword_size[0x20];
3668 u8 reserved_at_1c0[0x19];
3669 u8 relaxed_ordering_read[0x1];
3670 u8 reserved_at_1d9[0x1];
3671 u8 log_page_size[0x5];
3673 u8 reserved_at_1e0[0x20];
3676 struct mlx5_ifc_pkey_bits {
3677 u8 reserved_at_0[0x10];
3681 struct mlx5_ifc_array128_auto_bits {
3682 u8 array128_auto[16][0x8];
3685 struct mlx5_ifc_hca_vport_context_bits {
3686 u8 field_select[0x20];
3688 u8 reserved_at_20[0xe0];
3690 u8 sm_virt_aware[0x1];
3693 u8 grh_required[0x1];
3694 u8 reserved_at_104[0xc];
3695 u8 port_physical_state[0x4];
3696 u8 vport_state_policy[0x4];
3698 u8 vport_state[0x4];
3700 u8 reserved_at_120[0x20];
3702 u8 system_image_guid[0x40];
3710 u8 cap_mask1_field_select[0x20];
3714 u8 cap_mask2_field_select[0x20];
3716 u8 reserved_at_280[0x80];
3719 u8 reserved_at_310[0x4];
3720 u8 init_type_reply[0x4];
3722 u8 subnet_timeout[0x5];
3726 u8 reserved_at_334[0xc];
3728 u8 qkey_violation_counter[0x10];
3729 u8 pkey_violation_counter[0x10];
3731 u8 reserved_at_360[0xca0];
3734 struct mlx5_ifc_esw_vport_context_bits {
3735 u8 fdb_to_vport_reg_c[0x1];
3736 u8 reserved_at_1[0x2];
3737 u8 vport_svlan_strip[0x1];
3738 u8 vport_cvlan_strip[0x1];
3739 u8 vport_svlan_insert[0x1];
3740 u8 vport_cvlan_insert[0x2];
3741 u8 fdb_to_vport_reg_c_id[0x8];
3742 u8 reserved_at_10[0x10];
3744 u8 reserved_at_20[0x20];
3753 u8 reserved_at_60[0x720];
3755 u8 sw_steering_vport_icm_address_rx[0x40];
3757 u8 sw_steering_vport_icm_address_tx[0x40];
3761 MLX5_EQC_STATUS_OK = 0x0,
3762 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3766 MLX5_EQC_ST_ARMED = 0x9,
3767 MLX5_EQC_ST_FIRED = 0xa,
3770 struct mlx5_ifc_eqc_bits {
3772 u8 reserved_at_4[0x9];
3775 u8 reserved_at_f[0x5];
3777 u8 reserved_at_18[0x8];
3779 u8 reserved_at_20[0x20];
3781 u8 reserved_at_40[0x14];
3782 u8 page_offset[0x6];
3783 u8 reserved_at_5a[0x6];
3785 u8 reserved_at_60[0x3];
3786 u8 log_eq_size[0x5];
3789 u8 reserved_at_80[0x20];
3791 u8 reserved_at_a0[0x18];
3794 u8 reserved_at_c0[0x3];
3795 u8 log_page_size[0x5];
3796 u8 reserved_at_c8[0x18];
3798 u8 reserved_at_e0[0x60];
3800 u8 reserved_at_140[0x8];
3801 u8 consumer_counter[0x18];
3803 u8 reserved_at_160[0x8];
3804 u8 producer_counter[0x18];
3806 u8 reserved_at_180[0x80];
3810 MLX5_DCTC_STATE_ACTIVE = 0x0,
3811 MLX5_DCTC_STATE_DRAINING = 0x1,
3812 MLX5_DCTC_STATE_DRAINED = 0x2,
3816 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3817 MLX5_DCTC_CS_RES_NA = 0x1,
3818 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3822 MLX5_DCTC_MTU_256_BYTES = 0x1,
3823 MLX5_DCTC_MTU_512_BYTES = 0x2,
3824 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3825 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3826 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3829 struct mlx5_ifc_dctc_bits {
3830 u8 reserved_at_0[0x4];
3832 u8 reserved_at_8[0x18];
3834 u8 reserved_at_20[0x8];
3835 u8 user_index[0x18];
3837 u8 reserved_at_40[0x8];
3840 u8 counter_set_id[0x8];
3841 u8 atomic_mode[0x4];
3845 u8 atomic_like_write_en[0x1];
3846 u8 latency_sensitive[0x1];
3849 u8 reserved_at_73[0xd];
3851 u8 reserved_at_80[0x8];
3853 u8 reserved_at_90[0x3];
3854 u8 min_rnr_nak[0x5];
3855 u8 reserved_at_98[0x8];
3857 u8 reserved_at_a0[0x8];
3860 u8 reserved_at_c0[0x8];
3864 u8 reserved_at_e8[0x4];
3865 u8 flow_label[0x14];
3867 u8 dc_access_key[0x40];
3869 u8 reserved_at_140[0x5];
3872 u8 pkey_index[0x10];
3874 u8 reserved_at_160[0x8];
3875 u8 my_addr_index[0x8];
3876 u8 reserved_at_170[0x8];
3879 u8 dc_access_key_violation_count[0x20];
3881 u8 reserved_at_1a0[0x14];
3887 u8 reserved_at_1c0[0x20];
3892 MLX5_CQC_STATUS_OK = 0x0,
3893 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3894 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3898 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3899 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3903 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3904 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3905 MLX5_CQC_ST_FIRED = 0xa,
3909 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3910 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3911 MLX5_CQ_PERIOD_NUM_MODES
3914 struct mlx5_ifc_cqc_bits {
3916 u8 reserved_at_4[0x2];
3917 u8 dbr_umem_valid[0x1];
3918 u8 apu_thread_cq[0x1];
3921 u8 reserved_at_c[0x1];
3922 u8 scqe_break_moderation_en[0x1];
3924 u8 cq_period_mode[0x2];
3925 u8 cqe_comp_en[0x1];
3926 u8 mini_cqe_res_format[0x2];
3928 u8 reserved_at_18[0x8];
3930 u8 reserved_at_20[0x20];
3932 u8 reserved_at_40[0x14];
3933 u8 page_offset[0x6];
3934 u8 reserved_at_5a[0x6];
3936 u8 reserved_at_60[0x3];
3937 u8 log_cq_size[0x5];
3940 u8 reserved_at_80[0x4];
3942 u8 cq_max_count[0x10];
3944 u8 reserved_at_a0[0x18];
3947 u8 reserved_at_c0[0x3];
3948 u8 log_page_size[0x5];
3949 u8 reserved_at_c8[0x18];
3951 u8 reserved_at_e0[0x20];
3953 u8 reserved_at_100[0x8];
3954 u8 last_notified_index[0x18];
3956 u8 reserved_at_120[0x8];
3957 u8 last_solicit_index[0x18];
3959 u8 reserved_at_140[0x8];
3960 u8 consumer_counter[0x18];
3962 u8 reserved_at_160[0x8];
3963 u8 producer_counter[0x18];
3965 u8 reserved_at_180[0x40];
3970 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3971 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3972 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3973 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3974 u8 reserved_at_0[0x800];
3977 struct mlx5_ifc_query_adapter_param_block_bits {
3978 u8 reserved_at_0[0xc0];
3980 u8 reserved_at_c0[0x8];
3981 u8 ieee_vendor_id[0x18];
3983 u8 reserved_at_e0[0x10];
3984 u8 vsd_vendor_id[0x10];
3988 u8 vsd_contd_psid[16][0x8];
3992 MLX5_XRQC_STATE_GOOD = 0x0,
3993 MLX5_XRQC_STATE_ERROR = 0x1,
3997 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3998 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
4002 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4005 struct mlx5_ifc_tag_matching_topology_context_bits {
4006 u8 log_matching_list_sz[0x4];
4007 u8 reserved_at_4[0xc];
4008 u8 append_next_index[0x10];
4010 u8 sw_phase_cnt[0x10];
4011 u8 hw_phase_cnt[0x10];
4013 u8 reserved_at_40[0x40];
4016 struct mlx5_ifc_xrqc_bits {
4019 u8 reserved_at_5[0xf];
4021 u8 reserved_at_18[0x4];
4024 u8 reserved_at_20[0x8];
4025 u8 user_index[0x18];
4027 u8 reserved_at_40[0x8];
4030 u8 reserved_at_60[0xa0];
4032 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4034 u8 reserved_at_180[0x280];
4036 struct mlx5_ifc_wq_bits wq;
4039 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4040 struct mlx5_ifc_modify_field_select_bits modify_field_select;
4041 struct mlx5_ifc_resize_field_select_bits resize_field_select;
4042 u8 reserved_at_0[0x20];
4045 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4046 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4047 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4048 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4049 u8 reserved_at_0[0x20];
4052 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4053 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4054 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4055 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4056 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4057 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4058 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4059 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4060 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4061 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4062 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4063 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4064 u8 reserved_at_0[0x7c0];
4067 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4068 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4069 u8 reserved_at_0[0x7c0];
4072 union mlx5_ifc_event_auto_bits {
4073 struct mlx5_ifc_comp_event_bits comp_event;
4074 struct mlx5_ifc_dct_events_bits dct_events;
4075 struct mlx5_ifc_qp_events_bits qp_events;
4076 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4077 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4078 struct mlx5_ifc_cq_error_bits cq_error;
4079 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4080 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4081 struct mlx5_ifc_gpio_event_bits gpio_event;
4082 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4083 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4084 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4085 u8 reserved_at_0[0xe0];
4088 struct mlx5_ifc_health_buffer_bits {
4089 u8 reserved_at_0[0x100];
4091 u8 assert_existptr[0x20];
4093 u8 assert_callra[0x20];
4095 u8 reserved_at_140[0x40];
4097 u8 fw_version[0x20];
4101 u8 reserved_at_1c0[0x20];
4103 u8 irisc_index[0x8];
4108 struct mlx5_ifc_register_loopback_control_bits {
4110 u8 reserved_at_1[0x7];
4112 u8 reserved_at_10[0x10];
4114 u8 reserved_at_20[0x60];
4117 struct mlx5_ifc_vport_tc_element_bits {
4118 u8 traffic_class[0x4];
4119 u8 reserved_at_4[0xc];
4120 u8 vport_number[0x10];
4123 struct mlx5_ifc_vport_element_bits {
4124 u8 reserved_at_0[0x10];
4125 u8 vport_number[0x10];
4129 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4130 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4131 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4134 struct mlx5_ifc_tsar_element_bits {
4135 u8 reserved_at_0[0x8];
4137 u8 reserved_at_10[0x10];
4141 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4142 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4145 struct mlx5_ifc_teardown_hca_out_bits {
4147 u8 reserved_at_8[0x18];
4151 u8 reserved_at_40[0x3f];
4157 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
4158 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
4159 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4162 struct mlx5_ifc_teardown_hca_in_bits {
4164 u8 reserved_at_10[0x10];
4166 u8 reserved_at_20[0x10];
4169 u8 reserved_at_40[0x10];
4172 u8 reserved_at_60[0x20];
4175 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4177 u8 reserved_at_8[0x18];
4181 u8 reserved_at_40[0x40];
4184 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4188 u8 reserved_at_20[0x10];
4191 u8 reserved_at_40[0x8];
4194 u8 reserved_at_60[0x20];
4196 u8 opt_param_mask[0x20];
4198 u8 reserved_at_a0[0x20];
4200 struct mlx5_ifc_qpc_bits qpc;
4202 u8 reserved_at_800[0x80];
4205 struct mlx5_ifc_sqd2rts_qp_out_bits {
4207 u8 reserved_at_8[0x18];
4211 u8 reserved_at_40[0x40];
4214 struct mlx5_ifc_sqd2rts_qp_in_bits {
4218 u8 reserved_at_20[0x10];
4221 u8 reserved_at_40[0x8];
4224 u8 reserved_at_60[0x20];
4226 u8 opt_param_mask[0x20];
4228 u8 reserved_at_a0[0x20];
4230 struct mlx5_ifc_qpc_bits qpc;
4232 u8 reserved_at_800[0x80];
4235 struct mlx5_ifc_set_roce_address_out_bits {
4237 u8 reserved_at_8[0x18];
4241 u8 reserved_at_40[0x40];
4244 struct mlx5_ifc_set_roce_address_in_bits {
4246 u8 reserved_at_10[0x10];
4248 u8 reserved_at_20[0x10];
4251 u8 roce_address_index[0x10];
4252 u8 reserved_at_50[0xc];
4253 u8 vhca_port_num[0x4];
4255 u8 reserved_at_60[0x20];
4257 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4260 struct mlx5_ifc_set_mad_demux_out_bits {
4262 u8 reserved_at_8[0x18];
4266 u8 reserved_at_40[0x40];
4270 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4271 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4274 struct mlx5_ifc_set_mad_demux_in_bits {
4276 u8 reserved_at_10[0x10];
4278 u8 reserved_at_20[0x10];
4281 u8 reserved_at_40[0x20];
4283 u8 reserved_at_60[0x6];
4285 u8 reserved_at_68[0x18];
4288 struct mlx5_ifc_set_l2_table_entry_out_bits {
4290 u8 reserved_at_8[0x18];
4294 u8 reserved_at_40[0x40];
4297 struct mlx5_ifc_set_l2_table_entry_in_bits {
4299 u8 reserved_at_10[0x10];
4301 u8 reserved_at_20[0x10];
4304 u8 reserved_at_40[0x60];
4306 u8 reserved_at_a0[0x8];
4307 u8 table_index[0x18];
4309 u8 reserved_at_c0[0x20];
4311 u8 reserved_at_e0[0x13];
4315 struct mlx5_ifc_mac_address_layout_bits mac_address;
4317 u8 reserved_at_140[0xc0];
4320 struct mlx5_ifc_set_issi_out_bits {
4322 u8 reserved_at_8[0x18];
4326 u8 reserved_at_40[0x40];
4329 struct mlx5_ifc_set_issi_in_bits {
4331 u8 reserved_at_10[0x10];
4333 u8 reserved_at_20[0x10];
4336 u8 reserved_at_40[0x10];
4337 u8 current_issi[0x10];
4339 u8 reserved_at_60[0x20];
4342 struct mlx5_ifc_set_hca_cap_out_bits {
4344 u8 reserved_at_8[0x18];
4348 u8 reserved_at_40[0x40];
4351 struct mlx5_ifc_set_hca_cap_in_bits {
4353 u8 reserved_at_10[0x10];
4355 u8 reserved_at_20[0x10];
4358 u8 other_function[0x1];
4359 u8 reserved_at_41[0xf];
4360 u8 function_id[0x10];
4362 u8 reserved_at_60[0x20];
4364 union mlx5_ifc_hca_cap_union_bits capability;
4368 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4369 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4370 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
4371 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4372 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
4375 struct mlx5_ifc_set_fte_out_bits {
4377 u8 reserved_at_8[0x18];
4381 u8 reserved_at_40[0x40];
4384 struct mlx5_ifc_set_fte_in_bits {
4386 u8 reserved_at_10[0x10];
4388 u8 reserved_at_20[0x10];
4391 u8 other_vport[0x1];
4392 u8 reserved_at_41[0xf];
4393 u8 vport_number[0x10];
4395 u8 reserved_at_60[0x20];
4398 u8 reserved_at_88[0x18];
4400 u8 reserved_at_a0[0x8];
4403 u8 ignore_flow_level[0x1];
4404 u8 reserved_at_c1[0x17];
4405 u8 modify_enable_mask[0x8];
4407 u8 reserved_at_e0[0x20];
4409 u8 flow_index[0x20];
4411 u8 reserved_at_120[0xe0];
4413 struct mlx5_ifc_flow_context_bits flow_context;
4416 struct mlx5_ifc_rts2rts_qp_out_bits {
4418 u8 reserved_at_8[0x18];
4422 u8 reserved_at_40[0x20];
4426 struct mlx5_ifc_rts2rts_qp_in_bits {
4430 u8 reserved_at_20[0x10];
4433 u8 reserved_at_40[0x8];
4436 u8 reserved_at_60[0x20];
4438 u8 opt_param_mask[0x20];
4442 struct mlx5_ifc_qpc_bits qpc;
4444 u8 reserved_at_800[0x80];
4447 struct mlx5_ifc_rtr2rts_qp_out_bits {
4449 u8 reserved_at_8[0x18];
4453 u8 reserved_at_40[0x20];
4457 struct mlx5_ifc_rtr2rts_qp_in_bits {
4461 u8 reserved_at_20[0x10];
4464 u8 reserved_at_40[0x8];
4467 u8 reserved_at_60[0x20];
4469 u8 opt_param_mask[0x20];
4473 struct mlx5_ifc_qpc_bits qpc;
4475 u8 reserved_at_800[0x80];
4478 struct mlx5_ifc_rst2init_qp_out_bits {
4480 u8 reserved_at_8[0x18];
4484 u8 reserved_at_40[0x20];
4488 struct mlx5_ifc_rst2init_qp_in_bits {
4492 u8 reserved_at_20[0x10];
4495 u8 reserved_at_40[0x8];
4498 u8 reserved_at_60[0x20];
4500 u8 opt_param_mask[0x20];
4504 struct mlx5_ifc_qpc_bits qpc;
4506 u8 reserved_at_800[0x80];
4509 struct mlx5_ifc_query_xrq_out_bits {
4511 u8 reserved_at_8[0x18];
4515 u8 reserved_at_40[0x40];
4517 struct mlx5_ifc_xrqc_bits xrq_context;
4520 struct mlx5_ifc_query_xrq_in_bits {
4522 u8 reserved_at_10[0x10];
4524 u8 reserved_at_20[0x10];
4527 u8 reserved_at_40[0x8];
4530 u8 reserved_at_60[0x20];
4533 struct mlx5_ifc_query_xrc_srq_out_bits {
4535 u8 reserved_at_8[0x18];
4539 u8 reserved_at_40[0x40];
4541 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4543 u8 reserved_at_280[0x600];
4548 struct mlx5_ifc_query_xrc_srq_in_bits {
4550 u8 reserved_at_10[0x10];
4552 u8 reserved_at_20[0x10];
4555 u8 reserved_at_40[0x8];
4558 u8 reserved_at_60[0x20];
4562 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4563 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4566 struct mlx5_ifc_query_vport_state_out_bits {
4568 u8 reserved_at_8[0x18];
4572 u8 reserved_at_40[0x20];
4574 u8 reserved_at_60[0x18];
4575 u8 admin_state[0x4];
4580 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4581 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4582 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
4585 struct mlx5_ifc_arm_monitor_counter_in_bits {
4589 u8 reserved_at_20[0x10];
4592 u8 reserved_at_40[0x20];
4594 u8 reserved_at_60[0x20];
4597 struct mlx5_ifc_arm_monitor_counter_out_bits {
4599 u8 reserved_at_8[0x18];
4603 u8 reserved_at_40[0x40];
4607 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4608 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4611 enum mlx5_monitor_counter_ppcnt {
4612 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4613 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4614 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4615 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4616 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4617 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4621 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4624 struct mlx5_ifc_monitor_counter_output_bits {
4625 u8 reserved_at_0[0x4];
4627 u8 reserved_at_8[0x8];
4630 u8 counter_group_id[0x20];
4633 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4634 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4635 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4636 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4638 struct mlx5_ifc_set_monitor_counter_in_bits {
4642 u8 reserved_at_20[0x10];
4645 u8 reserved_at_40[0x10];
4646 u8 num_of_counters[0x10];
4648 u8 reserved_at_60[0x20];
4650 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4653 struct mlx5_ifc_set_monitor_counter_out_bits {
4655 u8 reserved_at_8[0x18];
4659 u8 reserved_at_40[0x40];
4662 struct mlx5_ifc_query_vport_state_in_bits {
4664 u8 reserved_at_10[0x10];
4666 u8 reserved_at_20[0x10];
4669 u8 other_vport[0x1];
4670 u8 reserved_at_41[0xf];
4671 u8 vport_number[0x10];
4673 u8 reserved_at_60[0x20];
4676 struct mlx5_ifc_query_vnic_env_out_bits {
4678 u8 reserved_at_8[0x18];
4682 u8 reserved_at_40[0x40];
4684 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4688 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4691 struct mlx5_ifc_query_vnic_env_in_bits {
4693 u8 reserved_at_10[0x10];
4695 u8 reserved_at_20[0x10];
4698 u8 other_vport[0x1];
4699 u8 reserved_at_41[0xf];
4700 u8 vport_number[0x10];
4702 u8 reserved_at_60[0x20];
4705 struct mlx5_ifc_query_vport_counter_out_bits {
4707 u8 reserved_at_8[0x18];
4711 u8 reserved_at_40[0x40];
4713 struct mlx5_ifc_traffic_counter_bits received_errors;
4715 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4717 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4719 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4721 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4723 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4725 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4727 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4729 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4731 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4733 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4735 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4737 u8 reserved_at_680[0xa00];
4741 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4744 struct mlx5_ifc_query_vport_counter_in_bits {
4746 u8 reserved_at_10[0x10];
4748 u8 reserved_at_20[0x10];
4751 u8 other_vport[0x1];
4752 u8 reserved_at_41[0xb];
4754 u8 vport_number[0x10];
4756 u8 reserved_at_60[0x60];
4759 u8 reserved_at_c1[0x1f];
4761 u8 reserved_at_e0[0x20];
4764 struct mlx5_ifc_query_tis_out_bits {
4766 u8 reserved_at_8[0x18];
4770 u8 reserved_at_40[0x40];
4772 struct mlx5_ifc_tisc_bits tis_context;
4775 struct mlx5_ifc_query_tis_in_bits {
4777 u8 reserved_at_10[0x10];
4779 u8 reserved_at_20[0x10];
4782 u8 reserved_at_40[0x8];
4785 u8 reserved_at_60[0x20];
4788 struct mlx5_ifc_query_tir_out_bits {
4790 u8 reserved_at_8[0x18];
4794 u8 reserved_at_40[0xc0];
4796 struct mlx5_ifc_tirc_bits tir_context;
4799 struct mlx5_ifc_query_tir_in_bits {
4801 u8 reserved_at_10[0x10];
4803 u8 reserved_at_20[0x10];
4806 u8 reserved_at_40[0x8];
4809 u8 reserved_at_60[0x20];
4812 struct mlx5_ifc_query_srq_out_bits {
4814 u8 reserved_at_8[0x18];
4818 u8 reserved_at_40[0x40];
4820 struct mlx5_ifc_srqc_bits srq_context_entry;
4822 u8 reserved_at_280[0x600];
4827 struct mlx5_ifc_query_srq_in_bits {
4829 u8 reserved_at_10[0x10];
4831 u8 reserved_at_20[0x10];
4834 u8 reserved_at_40[0x8];
4837 u8 reserved_at_60[0x20];
4840 struct mlx5_ifc_query_sq_out_bits {
4842 u8 reserved_at_8[0x18];
4846 u8 reserved_at_40[0xc0];
4848 struct mlx5_ifc_sqc_bits sq_context;
4851 struct mlx5_ifc_query_sq_in_bits {
4853 u8 reserved_at_10[0x10];
4855 u8 reserved_at_20[0x10];
4858 u8 reserved_at_40[0x8];
4861 u8 reserved_at_60[0x20];
4864 struct mlx5_ifc_query_special_contexts_out_bits {
4866 u8 reserved_at_8[0x18];
4870 u8 dump_fill_mkey[0x20];
4876 u8 reserved_at_a0[0x60];
4879 struct mlx5_ifc_query_special_contexts_in_bits {
4881 u8 reserved_at_10[0x10];
4883 u8 reserved_at_20[0x10];
4886 u8 reserved_at_40[0x40];
4889 struct mlx5_ifc_query_scheduling_element_out_bits {
4891 u8 reserved_at_10[0x10];
4893 u8 reserved_at_20[0x10];
4896 u8 reserved_at_40[0xc0];
4898 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4900 u8 reserved_at_300[0x100];
4904 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4905 SCHEDULING_HIERARCHY_NIC = 0x3,
4908 struct mlx5_ifc_query_scheduling_element_in_bits {
4910 u8 reserved_at_10[0x10];
4912 u8 reserved_at_20[0x10];
4915 u8 scheduling_hierarchy[0x8];
4916 u8 reserved_at_48[0x18];
4918 u8 scheduling_element_id[0x20];
4920 u8 reserved_at_80[0x180];
4923 struct mlx5_ifc_query_rqt_out_bits {
4925 u8 reserved_at_8[0x18];
4929 u8 reserved_at_40[0xc0];
4931 struct mlx5_ifc_rqtc_bits rqt_context;
4934 struct mlx5_ifc_query_rqt_in_bits {
4936 u8 reserved_at_10[0x10];
4938 u8 reserved_at_20[0x10];
4941 u8 reserved_at_40[0x8];
4944 u8 reserved_at_60[0x20];
4947 struct mlx5_ifc_query_rq_out_bits {
4949 u8 reserved_at_8[0x18];
4953 u8 reserved_at_40[0xc0];
4955 struct mlx5_ifc_rqc_bits rq_context;
4958 struct mlx5_ifc_query_rq_in_bits {
4960 u8 reserved_at_10[0x10];
4962 u8 reserved_at_20[0x10];
4965 u8 reserved_at_40[0x8];
4968 u8 reserved_at_60[0x20];
4971 struct mlx5_ifc_query_roce_address_out_bits {
4973 u8 reserved_at_8[0x18];
4977 u8 reserved_at_40[0x40];
4979 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4982 struct mlx5_ifc_query_roce_address_in_bits {
4984 u8 reserved_at_10[0x10];
4986 u8 reserved_at_20[0x10];
4989 u8 roce_address_index[0x10];
4990 u8 reserved_at_50[0xc];
4991 u8 vhca_port_num[0x4];
4993 u8 reserved_at_60[0x20];
4996 struct mlx5_ifc_query_rmp_out_bits {
4998 u8 reserved_at_8[0x18];
5002 u8 reserved_at_40[0xc0];
5004 struct mlx5_ifc_rmpc_bits rmp_context;
5007 struct mlx5_ifc_query_rmp_in_bits {
5009 u8 reserved_at_10[0x10];
5011 u8 reserved_at_20[0x10];
5014 u8 reserved_at_40[0x8];
5017 u8 reserved_at_60[0x20];
5020 struct mlx5_ifc_query_qp_out_bits {
5022 u8 reserved_at_8[0x18];
5026 u8 reserved_at_40[0x20];
5029 u8 opt_param_mask[0x20];
5031 u8 reserved_at_a0[0x20];
5033 struct mlx5_ifc_qpc_bits qpc;
5035 u8 reserved_at_800[0x80];
5040 struct mlx5_ifc_query_qp_in_bits {
5042 u8 reserved_at_10[0x10];
5044 u8 reserved_at_20[0x10];
5047 u8 reserved_at_40[0x8];
5050 u8 reserved_at_60[0x20];
5053 struct mlx5_ifc_query_q_counter_out_bits {
5055 u8 reserved_at_8[0x18];
5059 u8 reserved_at_40[0x40];
5061 u8 rx_write_requests[0x20];
5063 u8 reserved_at_a0[0x20];
5065 u8 rx_read_requests[0x20];
5067 u8 reserved_at_e0[0x20];
5069 u8 rx_atomic_requests[0x20];
5071 u8 reserved_at_120[0x20];
5073 u8 rx_dct_connect[0x20];
5075 u8 reserved_at_160[0x20];
5077 u8 out_of_buffer[0x20];
5079 u8 reserved_at_1a0[0x20];
5081 u8 out_of_sequence[0x20];
5083 u8 reserved_at_1e0[0x20];
5085 u8 duplicate_request[0x20];
5087 u8 reserved_at_220[0x20];
5089 u8 rnr_nak_retry_err[0x20];
5091 u8 reserved_at_260[0x20];
5093 u8 packet_seq_err[0x20];
5095 u8 reserved_at_2a0[0x20];
5097 u8 implied_nak_seq_err[0x20];
5099 u8 reserved_at_2e0[0x20];
5101 u8 local_ack_timeout_err[0x20];
5103 u8 reserved_at_320[0xa0];
5105 u8 resp_local_length_error[0x20];
5107 u8 req_local_length_error[0x20];
5109 u8 resp_local_qp_error[0x20];
5111 u8 local_operation_error[0x20];
5113 u8 resp_local_protection[0x20];
5115 u8 req_local_protection[0x20];
5117 u8 resp_cqe_error[0x20];
5119 u8 req_cqe_error[0x20];
5121 u8 req_mw_binding[0x20];
5123 u8 req_bad_response[0x20];
5125 u8 req_remote_invalid_request[0x20];
5127 u8 resp_remote_invalid_request[0x20];
5129 u8 req_remote_access_errors[0x20];
5131 u8 resp_remote_access_errors[0x20];
5133 u8 req_remote_operation_errors[0x20];
5135 u8 req_transport_retries_exceeded[0x20];
5137 u8 cq_overflow[0x20];
5139 u8 resp_cqe_flush_error[0x20];
5141 u8 req_cqe_flush_error[0x20];
5143 u8 reserved_at_620[0x20];
5145 u8 roce_adp_retrans[0x20];
5147 u8 roce_adp_retrans_to[0x20];
5149 u8 roce_slow_restart[0x20];
5151 u8 roce_slow_restart_cnps[0x20];
5153 u8 roce_slow_restart_trans[0x20];
5155 u8 reserved_at_6e0[0x120];
5158 struct mlx5_ifc_query_q_counter_in_bits {
5160 u8 reserved_at_10[0x10];
5162 u8 reserved_at_20[0x10];
5165 u8 reserved_at_40[0x80];
5168 u8 reserved_at_c1[0x1f];
5170 u8 reserved_at_e0[0x18];
5171 u8 counter_set_id[0x8];
5174 struct mlx5_ifc_query_pages_out_bits {
5176 u8 reserved_at_8[0x18];
5180 u8 embedded_cpu_function[0x1];
5181 u8 reserved_at_41[0xf];
5182 u8 function_id[0x10];
5188 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5189 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5190 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5193 struct mlx5_ifc_query_pages_in_bits {
5195 u8 reserved_at_10[0x10];
5197 u8 reserved_at_20[0x10];
5200 u8 embedded_cpu_function[0x1];
5201 u8 reserved_at_41[0xf];
5202 u8 function_id[0x10];
5204 u8 reserved_at_60[0x20];
5207 struct mlx5_ifc_query_nic_vport_context_out_bits {
5209 u8 reserved_at_8[0x18];
5213 u8 reserved_at_40[0x40];
5215 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5218 struct mlx5_ifc_query_nic_vport_context_in_bits {
5220 u8 reserved_at_10[0x10];
5222 u8 reserved_at_20[0x10];
5225 u8 other_vport[0x1];
5226 u8 reserved_at_41[0xf];
5227 u8 vport_number[0x10];
5229 u8 reserved_at_60[0x5];
5230 u8 allowed_list_type[0x3];
5231 u8 reserved_at_68[0x18];
5234 struct mlx5_ifc_query_mkey_out_bits {
5236 u8 reserved_at_8[0x18];
5240 u8 reserved_at_40[0x40];
5242 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5244 u8 reserved_at_280[0x600];
5246 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5248 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5251 struct mlx5_ifc_query_mkey_in_bits {
5253 u8 reserved_at_10[0x10];
5255 u8 reserved_at_20[0x10];
5258 u8 reserved_at_40[0x8];
5259 u8 mkey_index[0x18];
5262 u8 reserved_at_61[0x1f];
5265 struct mlx5_ifc_query_mad_demux_out_bits {
5267 u8 reserved_at_8[0x18];
5271 u8 reserved_at_40[0x40];
5273 u8 mad_dumux_parameters_block[0x20];
5276 struct mlx5_ifc_query_mad_demux_in_bits {
5278 u8 reserved_at_10[0x10];
5280 u8 reserved_at_20[0x10];
5283 u8 reserved_at_40[0x40];
5286 struct mlx5_ifc_query_l2_table_entry_out_bits {
5288 u8 reserved_at_8[0x18];
5292 u8 reserved_at_40[0xa0];
5294 u8 reserved_at_e0[0x13];
5298 struct mlx5_ifc_mac_address_layout_bits mac_address;
5300 u8 reserved_at_140[0xc0];
5303 struct mlx5_ifc_query_l2_table_entry_in_bits {
5305 u8 reserved_at_10[0x10];
5307 u8 reserved_at_20[0x10];
5310 u8 reserved_at_40[0x60];
5312 u8 reserved_at_a0[0x8];
5313 u8 table_index[0x18];
5315 u8 reserved_at_c0[0x140];
5318 struct mlx5_ifc_query_issi_out_bits {
5320 u8 reserved_at_8[0x18];
5324 u8 reserved_at_40[0x10];
5325 u8 current_issi[0x10];
5327 u8 reserved_at_60[0xa0];
5329 u8 reserved_at_100[76][0x8];
5330 u8 supported_issi_dw0[0x20];
5333 struct mlx5_ifc_query_issi_in_bits {
5335 u8 reserved_at_10[0x10];
5337 u8 reserved_at_20[0x10];
5340 u8 reserved_at_40[0x40];
5343 struct mlx5_ifc_set_driver_version_out_bits {
5345 u8 reserved_0[0x18];
5348 u8 reserved_1[0x40];
5351 struct mlx5_ifc_set_driver_version_in_bits {
5353 u8 reserved_0[0x10];
5355 u8 reserved_1[0x10];
5358 u8 reserved_2[0x40];
5359 u8 driver_version[64][0x8];
5362 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5364 u8 reserved_at_8[0x18];
5368 u8 reserved_at_40[0x40];
5370 struct mlx5_ifc_pkey_bits pkey[];
5373 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5375 u8 reserved_at_10[0x10];
5377 u8 reserved_at_20[0x10];
5380 u8 other_vport[0x1];
5381 u8 reserved_at_41[0xb];
5383 u8 vport_number[0x10];
5385 u8 reserved_at_60[0x10];
5386 u8 pkey_index[0x10];
5390 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5391 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5392 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5395 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5397 u8 reserved_at_8[0x18];
5401 u8 reserved_at_40[0x20];
5404 u8 reserved_at_70[0x10];
5406 struct mlx5_ifc_array128_auto_bits gid[];
5409 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5411 u8 reserved_at_10[0x10];
5413 u8 reserved_at_20[0x10];
5416 u8 other_vport[0x1];
5417 u8 reserved_at_41[0xb];
5419 u8 vport_number[0x10];
5421 u8 reserved_at_60[0x10];
5425 struct mlx5_ifc_query_hca_vport_context_out_bits {
5427 u8 reserved_at_8[0x18];
5431 u8 reserved_at_40[0x40];
5433 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5436 struct mlx5_ifc_query_hca_vport_context_in_bits {
5438 u8 reserved_at_10[0x10];
5440 u8 reserved_at_20[0x10];
5443 u8 other_vport[0x1];
5444 u8 reserved_at_41[0xb];
5446 u8 vport_number[0x10];
5448 u8 reserved_at_60[0x20];
5451 struct mlx5_ifc_query_hca_cap_out_bits {
5453 u8 reserved_at_8[0x18];
5457 u8 reserved_at_40[0x40];
5459 union mlx5_ifc_hca_cap_union_bits capability;
5462 struct mlx5_ifc_query_hca_cap_in_bits {
5464 u8 reserved_at_10[0x10];
5466 u8 reserved_at_20[0x10];
5469 u8 other_function[0x1];
5470 u8 reserved_at_41[0xf];
5471 u8 function_id[0x10];
5473 u8 reserved_at_60[0x20];
5476 struct mlx5_ifc_other_hca_cap_bits {
5478 u8 reserved_at_1[0x27f];
5481 struct mlx5_ifc_query_other_hca_cap_out_bits {
5483 u8 reserved_at_8[0x18];
5487 u8 reserved_at_40[0x40];
5489 struct mlx5_ifc_other_hca_cap_bits other_capability;
5492 struct mlx5_ifc_query_other_hca_cap_in_bits {
5494 u8 reserved_at_10[0x10];
5496 u8 reserved_at_20[0x10];
5499 u8 reserved_at_40[0x10];
5500 u8 function_id[0x10];
5502 u8 reserved_at_60[0x20];
5505 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5507 u8 reserved_at_8[0x18];
5511 u8 reserved_at_40[0x40];
5514 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5516 u8 reserved_at_10[0x10];
5518 u8 reserved_at_20[0x10];
5521 u8 reserved_at_40[0x10];
5522 u8 function_id[0x10];
5523 u8 field_select[0x20];
5525 struct mlx5_ifc_other_hca_cap_bits other_capability;
5528 struct mlx5_ifc_flow_table_context_bits {
5529 u8 reformat_en[0x1];
5532 u8 termination_table[0x1];
5533 u8 table_miss_action[0x4];
5535 u8 reserved_at_10[0x8];
5538 u8 reserved_at_20[0x8];
5539 u8 table_miss_id[0x18];
5541 u8 reserved_at_40[0x8];
5542 u8 lag_master_next_table_id[0x18];
5544 u8 reserved_at_60[0x60];
5546 u8 sw_owner_icm_root_1[0x40];
5548 u8 sw_owner_icm_root_0[0x40];
5552 struct mlx5_ifc_query_flow_table_out_bits {
5554 u8 reserved_at_8[0x18];
5558 u8 reserved_at_40[0x80];
5560 struct mlx5_ifc_flow_table_context_bits flow_table_context;
5563 struct mlx5_ifc_query_flow_table_in_bits {
5565 u8 reserved_at_10[0x10];
5567 u8 reserved_at_20[0x10];
5570 u8 reserved_at_40[0x40];
5573 u8 reserved_at_88[0x18];
5575 u8 reserved_at_a0[0x8];
5578 u8 reserved_at_c0[0x140];
5581 struct mlx5_ifc_query_fte_out_bits {
5583 u8 reserved_at_8[0x18];
5587 u8 reserved_at_40[0x1c0];
5589 struct mlx5_ifc_flow_context_bits flow_context;
5592 struct mlx5_ifc_query_fte_in_bits {
5594 u8 reserved_at_10[0x10];
5596 u8 reserved_at_20[0x10];
5599 u8 reserved_at_40[0x40];
5602 u8 reserved_at_88[0x18];
5604 u8 reserved_at_a0[0x8];
5607 u8 reserved_at_c0[0x40];
5609 u8 flow_index[0x20];
5611 u8 reserved_at_120[0xe0];
5615 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5616 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5617 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5618 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5619 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5620 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
5623 struct mlx5_ifc_query_flow_group_out_bits {
5625 u8 reserved_at_8[0x18];
5629 u8 reserved_at_40[0xa0];
5631 u8 start_flow_index[0x20];
5633 u8 reserved_at_100[0x20];
5635 u8 end_flow_index[0x20];
5637 u8 reserved_at_140[0xa0];
5639 u8 reserved_at_1e0[0x18];
5640 u8 match_criteria_enable[0x8];
5642 struct mlx5_ifc_fte_match_param_bits match_criteria;
5644 u8 reserved_at_1200[0xe00];
5647 struct mlx5_ifc_query_flow_group_in_bits {
5649 u8 reserved_at_10[0x10];
5651 u8 reserved_at_20[0x10];
5654 u8 reserved_at_40[0x40];
5657 u8 reserved_at_88[0x18];
5659 u8 reserved_at_a0[0x8];
5664 u8 reserved_at_e0[0x120];
5667 struct mlx5_ifc_query_flow_counter_out_bits {
5669 u8 reserved_at_8[0x18];
5673 u8 reserved_at_40[0x40];
5675 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
5678 struct mlx5_ifc_query_flow_counter_in_bits {
5680 u8 reserved_at_10[0x10];
5682 u8 reserved_at_20[0x10];
5685 u8 reserved_at_40[0x80];
5688 u8 reserved_at_c1[0xf];
5689 u8 num_of_counters[0x10];
5691 u8 flow_counter_id[0x20];
5694 struct mlx5_ifc_query_esw_vport_context_out_bits {
5696 u8 reserved_at_8[0x18];
5700 u8 reserved_at_40[0x40];
5702 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5705 struct mlx5_ifc_query_esw_vport_context_in_bits {
5707 u8 reserved_at_10[0x10];
5709 u8 reserved_at_20[0x10];
5712 u8 other_vport[0x1];
5713 u8 reserved_at_41[0xf];
5714 u8 vport_number[0x10];
5716 u8 reserved_at_60[0x20];
5719 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5721 u8 reserved_at_8[0x18];
5725 u8 reserved_at_40[0x40];
5728 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5729 u8 reserved_at_0[0x1b];
5730 u8 fdb_to_vport_reg_c_id[0x1];
5731 u8 vport_cvlan_insert[0x1];
5732 u8 vport_svlan_insert[0x1];
5733 u8 vport_cvlan_strip[0x1];
5734 u8 vport_svlan_strip[0x1];
5737 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5739 u8 reserved_at_10[0x10];
5741 u8 reserved_at_20[0x10];
5744 u8 other_vport[0x1];
5745 u8 reserved_at_41[0xf];
5746 u8 vport_number[0x10];
5748 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5750 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5753 struct mlx5_ifc_query_eq_out_bits {
5755 u8 reserved_at_8[0x18];
5759 u8 reserved_at_40[0x40];
5761 struct mlx5_ifc_eqc_bits eq_context_entry;
5763 u8 reserved_at_280[0x40];
5765 u8 event_bitmask[0x40];
5767 u8 reserved_at_300[0x580];
5772 struct mlx5_ifc_query_eq_in_bits {
5774 u8 reserved_at_10[0x10];
5776 u8 reserved_at_20[0x10];
5779 u8 reserved_at_40[0x18];
5782 u8 reserved_at_60[0x20];
5785 struct mlx5_ifc_packet_reformat_context_in_bits {
5786 u8 reserved_at_0[0x5];
5787 u8 reformat_type[0x3];
5788 u8 reserved_at_8[0xe];
5789 u8 reformat_data_size[0xa];
5791 u8 reserved_at_20[0x10];
5792 u8 reformat_data[2][0x8];
5794 u8 more_reformat_data[][0x8];
5797 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5799 u8 reserved_at_8[0x18];
5803 u8 reserved_at_40[0xa0];
5805 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
5808 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5810 u8 reserved_at_10[0x10];
5812 u8 reserved_at_20[0x10];
5815 u8 packet_reformat_id[0x20];
5817 u8 reserved_at_60[0xa0];
5820 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5822 u8 reserved_at_8[0x18];
5826 u8 packet_reformat_id[0x20];
5828 u8 reserved_at_60[0x20];
5831 enum mlx5_reformat_ctx_type {
5832 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5833 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5834 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5835 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5836 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5839 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5841 u8 reserved_at_10[0x10];
5843 u8 reserved_at_20[0x10];
5846 u8 reserved_at_40[0xa0];
5848 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5851 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5853 u8 reserved_at_8[0x18];
5857 u8 reserved_at_40[0x40];
5860 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5862 u8 reserved_at_10[0x10];
5864 u8 reserved_20[0x10];
5867 u8 packet_reformat_id[0x20];
5869 u8 reserved_60[0x20];
5872 struct mlx5_ifc_set_action_in_bits {
5873 u8 action_type[0x4];
5875 u8 reserved_at_10[0x3];
5877 u8 reserved_at_18[0x3];
5883 struct mlx5_ifc_add_action_in_bits {
5884 u8 action_type[0x4];
5886 u8 reserved_at_10[0x10];
5891 struct mlx5_ifc_copy_action_in_bits {
5892 u8 action_type[0x4];
5894 u8 reserved_at_10[0x3];
5896 u8 reserved_at_18[0x3];
5899 u8 reserved_at_20[0x4];
5901 u8 reserved_at_30[0x3];
5903 u8 reserved_at_38[0x8];
5906 union mlx5_ifc_set_add_copy_action_in_auto_bits {
5907 struct mlx5_ifc_set_action_in_bits set_action_in;
5908 struct mlx5_ifc_add_action_in_bits add_action_in;
5909 struct mlx5_ifc_copy_action_in_bits copy_action_in;
5910 u8 reserved_at_0[0x40];
5914 MLX5_ACTION_TYPE_SET = 0x1,
5915 MLX5_ACTION_TYPE_ADD = 0x2,
5916 MLX5_ACTION_TYPE_COPY = 0x3,
5920 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5921 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5922 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5923 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5924 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5925 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5926 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5927 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5928 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5929 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5930 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5931 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5932 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5933 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5934 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5935 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5936 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5937 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5938 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5939 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5940 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5941 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5942 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5943 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5944 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5945 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
5946 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5947 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5948 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5949 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5950 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5951 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5952 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
5953 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
5954 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5955 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
5956 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
5959 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5961 u8 reserved_at_8[0x18];
5965 u8 modify_header_id[0x20];
5967 u8 reserved_at_60[0x20];
5970 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5972 u8 reserved_at_10[0x10];
5974 u8 reserved_at_20[0x10];
5977 u8 reserved_at_40[0x20];
5980 u8 reserved_at_68[0x10];
5981 u8 num_of_actions[0x8];
5983 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
5986 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5988 u8 reserved_at_8[0x18];
5992 u8 reserved_at_40[0x40];
5995 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5997 u8 reserved_at_10[0x10];
5999 u8 reserved_at_20[0x10];
6002 u8 modify_header_id[0x20];
6004 u8 reserved_at_60[0x20];
6007 struct mlx5_ifc_query_modify_header_context_in_bits {
6011 u8 reserved_at_20[0x10];
6014 u8 modify_header_id[0x20];
6016 u8 reserved_at_60[0xa0];
6019 struct mlx5_ifc_query_dct_out_bits {
6021 u8 reserved_at_8[0x18];
6025 u8 reserved_at_40[0x40];
6027 struct mlx5_ifc_dctc_bits dct_context_entry;
6029 u8 reserved_at_280[0x180];
6032 struct mlx5_ifc_query_dct_in_bits {
6034 u8 reserved_at_10[0x10];
6036 u8 reserved_at_20[0x10];
6039 u8 reserved_at_40[0x8];
6042 u8 reserved_at_60[0x20];
6045 struct mlx5_ifc_query_cq_out_bits {
6047 u8 reserved_at_8[0x18];
6051 u8 reserved_at_40[0x40];
6053 struct mlx5_ifc_cqc_bits cq_context;
6055 u8 reserved_at_280[0x600];
6060 struct mlx5_ifc_query_cq_in_bits {
6062 u8 reserved_at_10[0x10];
6064 u8 reserved_at_20[0x10];
6067 u8 reserved_at_40[0x8];
6070 u8 reserved_at_60[0x20];
6073 struct mlx5_ifc_query_cong_status_out_bits {
6075 u8 reserved_at_8[0x18];
6079 u8 reserved_at_40[0x20];
6083 u8 reserved_at_62[0x1e];
6086 struct mlx5_ifc_query_cong_status_in_bits {
6088 u8 reserved_at_10[0x10];
6090 u8 reserved_at_20[0x10];
6093 u8 reserved_at_40[0x18];
6095 u8 cong_protocol[0x4];
6097 u8 reserved_at_60[0x20];
6100 struct mlx5_ifc_query_cong_statistics_out_bits {
6102 u8 reserved_at_8[0x18];
6106 u8 reserved_at_40[0x40];
6108 u8 rp_cur_flows[0x20];
6112 u8 rp_cnp_ignored_high[0x20];
6114 u8 rp_cnp_ignored_low[0x20];
6116 u8 rp_cnp_handled_high[0x20];
6118 u8 rp_cnp_handled_low[0x20];
6120 u8 reserved_at_140[0x100];
6122 u8 time_stamp_high[0x20];
6124 u8 time_stamp_low[0x20];
6126 u8 accumulators_period[0x20];
6128 u8 np_ecn_marked_roce_packets_high[0x20];
6130 u8 np_ecn_marked_roce_packets_low[0x20];
6132 u8 np_cnp_sent_high[0x20];
6134 u8 np_cnp_sent_low[0x20];
6136 u8 reserved_at_320[0x560];
6139 struct mlx5_ifc_query_cong_statistics_in_bits {
6141 u8 reserved_at_10[0x10];
6143 u8 reserved_at_20[0x10];
6147 u8 reserved_at_41[0x1f];
6149 u8 reserved_at_60[0x20];
6152 struct mlx5_ifc_query_cong_params_out_bits {
6154 u8 reserved_at_8[0x18];
6158 u8 reserved_at_40[0x40];
6160 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6163 struct mlx5_ifc_query_cong_params_in_bits {
6165 u8 reserved_at_10[0x10];
6167 u8 reserved_at_20[0x10];
6170 u8 reserved_at_40[0x1c];
6171 u8 cong_protocol[0x4];
6173 u8 reserved_at_60[0x20];
6176 struct mlx5_ifc_query_adapter_out_bits {
6178 u8 reserved_at_8[0x18];
6182 u8 reserved_at_40[0x40];
6184 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6187 struct mlx5_ifc_query_adapter_in_bits {
6189 u8 reserved_at_10[0x10];
6191 u8 reserved_at_20[0x10];
6194 u8 reserved_at_40[0x40];
6197 struct mlx5_ifc_qp_2rst_out_bits {
6199 u8 reserved_at_8[0x18];
6203 u8 reserved_at_40[0x40];
6206 struct mlx5_ifc_qp_2rst_in_bits {
6210 u8 reserved_at_20[0x10];
6213 u8 reserved_at_40[0x8];
6216 u8 reserved_at_60[0x20];
6219 struct mlx5_ifc_qp_2err_out_bits {
6221 u8 reserved_at_8[0x18];
6225 u8 reserved_at_40[0x40];
6228 struct mlx5_ifc_qp_2err_in_bits {
6232 u8 reserved_at_20[0x10];
6235 u8 reserved_at_40[0x8];
6238 u8 reserved_at_60[0x20];
6241 struct mlx5_ifc_page_fault_resume_out_bits {
6243 u8 reserved_at_8[0x18];
6247 u8 reserved_at_40[0x40];
6250 struct mlx5_ifc_page_fault_resume_in_bits {
6252 u8 reserved_at_10[0x10];
6254 u8 reserved_at_20[0x10];
6258 u8 reserved_at_41[0x4];
6259 u8 page_fault_type[0x3];
6262 u8 reserved_at_60[0x8];
6266 struct mlx5_ifc_nop_out_bits {
6268 u8 reserved_at_8[0x18];
6272 u8 reserved_at_40[0x40];
6275 struct mlx5_ifc_nop_in_bits {
6277 u8 reserved_at_10[0x10];
6279 u8 reserved_at_20[0x10];
6282 u8 reserved_at_40[0x40];
6285 struct mlx5_ifc_modify_vport_state_out_bits {
6287 u8 reserved_at_8[0x18];
6291 u8 reserved_at_40[0x40];
6294 struct mlx5_ifc_modify_vport_state_in_bits {
6296 u8 reserved_at_10[0x10];
6298 u8 reserved_at_20[0x10];
6301 u8 other_vport[0x1];
6302 u8 reserved_at_41[0xf];
6303 u8 vport_number[0x10];
6305 u8 reserved_at_60[0x18];
6306 u8 admin_state[0x4];
6307 u8 reserved_at_7c[0x4];
6310 struct mlx5_ifc_modify_tis_out_bits {
6312 u8 reserved_at_8[0x18];
6316 u8 reserved_at_40[0x40];
6319 struct mlx5_ifc_modify_tis_bitmask_bits {
6320 u8 reserved_at_0[0x20];
6322 u8 reserved_at_20[0x1d];
6323 u8 lag_tx_port_affinity[0x1];
6324 u8 strict_lag_tx_port_affinity[0x1];
6328 struct mlx5_ifc_modify_tis_in_bits {
6332 u8 reserved_at_20[0x10];
6335 u8 reserved_at_40[0x8];
6338 u8 reserved_at_60[0x20];
6340 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6342 u8 reserved_at_c0[0x40];
6344 struct mlx5_ifc_tisc_bits ctx;
6347 struct mlx5_ifc_modify_tir_bitmask_bits {
6348 u8 reserved_at_0[0x20];
6350 u8 reserved_at_20[0x1b];
6352 u8 reserved_at_3c[0x1];
6354 u8 reserved_at_3e[0x1];
6358 struct mlx5_ifc_modify_tir_out_bits {
6360 u8 reserved_at_8[0x18];
6364 u8 reserved_at_40[0x40];
6367 struct mlx5_ifc_modify_tir_in_bits {
6371 u8 reserved_at_20[0x10];
6374 u8 reserved_at_40[0x8];
6377 u8 reserved_at_60[0x20];
6379 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6381 u8 reserved_at_c0[0x40];
6383 struct mlx5_ifc_tirc_bits ctx;
6386 struct mlx5_ifc_modify_sq_out_bits {
6388 u8 reserved_at_8[0x18];
6392 u8 reserved_at_40[0x40];
6395 struct mlx5_ifc_modify_sq_in_bits {
6399 u8 reserved_at_20[0x10];
6403 u8 reserved_at_44[0x4];
6406 u8 reserved_at_60[0x20];
6408 u8 modify_bitmask[0x40];
6410 u8 reserved_at_c0[0x40];
6412 struct mlx5_ifc_sqc_bits ctx;
6415 struct mlx5_ifc_modify_scheduling_element_out_bits {
6417 u8 reserved_at_8[0x18];
6421 u8 reserved_at_40[0x1c0];
6425 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6426 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6429 struct mlx5_ifc_modify_scheduling_element_in_bits {
6431 u8 reserved_at_10[0x10];
6433 u8 reserved_at_20[0x10];
6436 u8 scheduling_hierarchy[0x8];
6437 u8 reserved_at_48[0x18];
6439 u8 scheduling_element_id[0x20];
6441 u8 reserved_at_80[0x20];
6443 u8 modify_bitmask[0x20];
6445 u8 reserved_at_c0[0x40];
6447 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6449 u8 reserved_at_300[0x100];
6452 struct mlx5_ifc_modify_rqt_out_bits {
6454 u8 reserved_at_8[0x18];
6458 u8 reserved_at_40[0x40];
6461 struct mlx5_ifc_rqt_bitmask_bits {
6462 u8 reserved_at_0[0x20];
6464 u8 reserved_at_20[0x1f];
6468 struct mlx5_ifc_modify_rqt_in_bits {
6472 u8 reserved_at_20[0x10];
6475 u8 reserved_at_40[0x8];
6478 u8 reserved_at_60[0x20];
6480 struct mlx5_ifc_rqt_bitmask_bits bitmask;
6482 u8 reserved_at_c0[0x40];
6484 struct mlx5_ifc_rqtc_bits ctx;
6487 struct mlx5_ifc_modify_rq_out_bits {
6489 u8 reserved_at_8[0x18];
6493 u8 reserved_at_40[0x40];
6497 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6498 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6499 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6502 struct mlx5_ifc_modify_rq_in_bits {
6506 u8 reserved_at_20[0x10];
6510 u8 reserved_at_44[0x4];
6513 u8 reserved_at_60[0x20];
6515 u8 modify_bitmask[0x40];
6517 u8 reserved_at_c0[0x40];
6519 struct mlx5_ifc_rqc_bits ctx;
6522 struct mlx5_ifc_modify_rmp_out_bits {
6524 u8 reserved_at_8[0x18];
6528 u8 reserved_at_40[0x40];
6531 struct mlx5_ifc_rmp_bitmask_bits {
6532 u8 reserved_at_0[0x20];
6534 u8 reserved_at_20[0x1f];
6538 struct mlx5_ifc_modify_rmp_in_bits {
6542 u8 reserved_at_20[0x10];
6546 u8 reserved_at_44[0x4];
6549 u8 reserved_at_60[0x20];
6551 struct mlx5_ifc_rmp_bitmask_bits bitmask;
6553 u8 reserved_at_c0[0x40];
6555 struct mlx5_ifc_rmpc_bits ctx;
6558 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6560 u8 reserved_at_8[0x18];
6564 u8 reserved_at_40[0x40];
6567 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6568 u8 reserved_at_0[0x12];
6569 u8 affiliation[0x1];
6570 u8 reserved_at_13[0x1];
6571 u8 disable_uc_local_lb[0x1];
6572 u8 disable_mc_local_lb[0x1];
6577 u8 change_event[0x1];
6579 u8 permanent_address[0x1];
6580 u8 addresses_list[0x1];
6582 u8 reserved_at_1f[0x1];
6585 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6587 u8 reserved_at_10[0x10];
6589 u8 reserved_at_20[0x10];
6592 u8 other_vport[0x1];
6593 u8 reserved_at_41[0xf];
6594 u8 vport_number[0x10];
6596 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6598 u8 reserved_at_80[0x780];
6600 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6603 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6605 u8 reserved_at_8[0x18];
6609 u8 reserved_at_40[0x40];
6612 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6614 u8 reserved_at_10[0x10];
6616 u8 reserved_at_20[0x10];
6619 u8 other_vport[0x1];
6620 u8 reserved_at_41[0xb];
6622 u8 vport_number[0x10];
6624 u8 reserved_at_60[0x20];
6626 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6629 struct mlx5_ifc_modify_cq_out_bits {
6631 u8 reserved_at_8[0x18];
6635 u8 reserved_at_40[0x40];
6639 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
6640 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6643 struct mlx5_ifc_modify_cq_in_bits {
6647 u8 reserved_at_20[0x10];
6650 u8 reserved_at_40[0x8];
6653 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6655 struct mlx5_ifc_cqc_bits cq_context;
6657 u8 reserved_at_280[0x60];
6659 u8 cq_umem_valid[0x1];
6660 u8 reserved_at_2e1[0x1f];
6662 u8 reserved_at_300[0x580];
6667 struct mlx5_ifc_modify_cong_status_out_bits {
6669 u8 reserved_at_8[0x18];
6673 u8 reserved_at_40[0x40];
6676 struct mlx5_ifc_modify_cong_status_in_bits {
6678 u8 reserved_at_10[0x10];
6680 u8 reserved_at_20[0x10];
6683 u8 reserved_at_40[0x18];
6685 u8 cong_protocol[0x4];
6689 u8 reserved_at_62[0x1e];
6692 struct mlx5_ifc_modify_cong_params_out_bits {
6694 u8 reserved_at_8[0x18];
6698 u8 reserved_at_40[0x40];
6701 struct mlx5_ifc_modify_cong_params_in_bits {
6703 u8 reserved_at_10[0x10];
6705 u8 reserved_at_20[0x10];
6708 u8 reserved_at_40[0x1c];
6709 u8 cong_protocol[0x4];
6711 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6713 u8 reserved_at_80[0x80];
6715 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6718 struct mlx5_ifc_manage_pages_out_bits {
6720 u8 reserved_at_8[0x18];
6724 u8 output_num_entries[0x20];
6726 u8 reserved_at_60[0x20];
6732 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6733 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6734 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6737 struct mlx5_ifc_manage_pages_in_bits {
6739 u8 reserved_at_10[0x10];
6741 u8 reserved_at_20[0x10];
6744 u8 embedded_cpu_function[0x1];
6745 u8 reserved_at_41[0xf];
6746 u8 function_id[0x10];
6748 u8 input_num_entries[0x20];
6753 struct mlx5_ifc_mad_ifc_out_bits {
6755 u8 reserved_at_8[0x18];
6759 u8 reserved_at_40[0x40];
6761 u8 response_mad_packet[256][0x8];
6764 struct mlx5_ifc_mad_ifc_in_bits {
6766 u8 reserved_at_10[0x10];
6768 u8 reserved_at_20[0x10];
6771 u8 remote_lid[0x10];
6772 u8 reserved_at_50[0x8];
6775 u8 reserved_at_60[0x20];
6780 struct mlx5_ifc_init_hca_out_bits {
6782 u8 reserved_at_8[0x18];
6786 u8 reserved_at_40[0x40];
6789 struct mlx5_ifc_init_hca_in_bits {
6791 u8 reserved_at_10[0x10];
6793 u8 reserved_at_20[0x10];
6796 u8 reserved_at_40[0x40];
6797 u8 sw_owner_id[4][0x20];
6800 struct mlx5_ifc_init2rtr_qp_out_bits {
6802 u8 reserved_at_8[0x18];
6806 u8 reserved_at_40[0x20];
6810 struct mlx5_ifc_init2rtr_qp_in_bits {
6814 u8 reserved_at_20[0x10];
6817 u8 reserved_at_40[0x8];
6820 u8 reserved_at_60[0x20];
6822 u8 opt_param_mask[0x20];
6826 struct mlx5_ifc_qpc_bits qpc;
6828 u8 reserved_at_800[0x80];
6831 struct mlx5_ifc_init2init_qp_out_bits {
6833 u8 reserved_at_8[0x18];
6837 u8 reserved_at_40[0x20];
6841 struct mlx5_ifc_init2init_qp_in_bits {
6845 u8 reserved_at_20[0x10];
6848 u8 reserved_at_40[0x8];
6851 u8 reserved_at_60[0x20];
6853 u8 opt_param_mask[0x20];
6857 struct mlx5_ifc_qpc_bits qpc;
6859 u8 reserved_at_800[0x80];
6862 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6864 u8 reserved_at_8[0x18];
6868 u8 reserved_at_40[0x40];
6870 u8 packet_headers_log[128][0x8];
6872 u8 packet_syndrome[64][0x8];
6875 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6877 u8 reserved_at_10[0x10];
6879 u8 reserved_at_20[0x10];
6882 u8 reserved_at_40[0x40];
6885 struct mlx5_ifc_gen_eqe_in_bits {
6887 u8 reserved_at_10[0x10];
6889 u8 reserved_at_20[0x10];
6892 u8 reserved_at_40[0x18];
6895 u8 reserved_at_60[0x20];
6900 struct mlx5_ifc_gen_eq_out_bits {
6902 u8 reserved_at_8[0x18];
6906 u8 reserved_at_40[0x40];
6909 struct mlx5_ifc_enable_hca_out_bits {
6911 u8 reserved_at_8[0x18];
6915 u8 reserved_at_40[0x20];
6918 struct mlx5_ifc_enable_hca_in_bits {
6920 u8 reserved_at_10[0x10];
6922 u8 reserved_at_20[0x10];
6925 u8 embedded_cpu_function[0x1];
6926 u8 reserved_at_41[0xf];
6927 u8 function_id[0x10];
6929 u8 reserved_at_60[0x20];
6932 struct mlx5_ifc_drain_dct_out_bits {
6934 u8 reserved_at_8[0x18];
6938 u8 reserved_at_40[0x40];
6941 struct mlx5_ifc_drain_dct_in_bits {
6945 u8 reserved_at_20[0x10];
6948 u8 reserved_at_40[0x8];
6951 u8 reserved_at_60[0x20];
6954 struct mlx5_ifc_disable_hca_out_bits {
6956 u8 reserved_at_8[0x18];
6960 u8 reserved_at_40[0x20];
6963 struct mlx5_ifc_disable_hca_in_bits {
6965 u8 reserved_at_10[0x10];
6967 u8 reserved_at_20[0x10];
6970 u8 embedded_cpu_function[0x1];
6971 u8 reserved_at_41[0xf];
6972 u8 function_id[0x10];
6974 u8 reserved_at_60[0x20];
6977 struct mlx5_ifc_detach_from_mcg_out_bits {
6979 u8 reserved_at_8[0x18];
6983 u8 reserved_at_40[0x40];
6986 struct mlx5_ifc_detach_from_mcg_in_bits {
6990 u8 reserved_at_20[0x10];
6993 u8 reserved_at_40[0x8];
6996 u8 reserved_at_60[0x20];
6998 u8 multicast_gid[16][0x8];
7001 struct mlx5_ifc_destroy_xrq_out_bits {
7003 u8 reserved_at_8[0x18];
7007 u8 reserved_at_40[0x40];
7010 struct mlx5_ifc_destroy_xrq_in_bits {
7014 u8 reserved_at_20[0x10];
7017 u8 reserved_at_40[0x8];
7020 u8 reserved_at_60[0x20];
7023 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7025 u8 reserved_at_8[0x18];
7029 u8 reserved_at_40[0x40];
7032 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7036 u8 reserved_at_20[0x10];
7039 u8 reserved_at_40[0x8];
7042 u8 reserved_at_60[0x20];
7045 struct mlx5_ifc_destroy_tis_out_bits {
7047 u8 reserved_at_8[0x18];
7051 u8 reserved_at_40[0x40];
7054 struct mlx5_ifc_destroy_tis_in_bits {
7058 u8 reserved_at_20[0x10];
7061 u8 reserved_at_40[0x8];
7064 u8 reserved_at_60[0x20];
7067 struct mlx5_ifc_destroy_tir_out_bits {
7069 u8 reserved_at_8[0x18];
7073 u8 reserved_at_40[0x40];
7076 struct mlx5_ifc_destroy_tir_in_bits {
7080 u8 reserved_at_20[0x10];
7083 u8 reserved_at_40[0x8];
7086 u8 reserved_at_60[0x20];
7089 struct mlx5_ifc_destroy_srq_out_bits {
7091 u8 reserved_at_8[0x18];
7095 u8 reserved_at_40[0x40];
7098 struct mlx5_ifc_destroy_srq_in_bits {
7102 u8 reserved_at_20[0x10];
7105 u8 reserved_at_40[0x8];
7108 u8 reserved_at_60[0x20];
7111 struct mlx5_ifc_destroy_sq_out_bits {
7113 u8 reserved_at_8[0x18];
7117 u8 reserved_at_40[0x40];
7120 struct mlx5_ifc_destroy_sq_in_bits {
7124 u8 reserved_at_20[0x10];
7127 u8 reserved_at_40[0x8];
7130 u8 reserved_at_60[0x20];
7133 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7135 u8 reserved_at_8[0x18];
7139 u8 reserved_at_40[0x1c0];
7142 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7144 u8 reserved_at_10[0x10];
7146 u8 reserved_at_20[0x10];
7149 u8 scheduling_hierarchy[0x8];
7150 u8 reserved_at_48[0x18];
7152 u8 scheduling_element_id[0x20];
7154 u8 reserved_at_80[0x180];
7157 struct mlx5_ifc_destroy_rqt_out_bits {
7159 u8 reserved_at_8[0x18];
7163 u8 reserved_at_40[0x40];
7166 struct mlx5_ifc_destroy_rqt_in_bits {
7170 u8 reserved_at_20[0x10];
7173 u8 reserved_at_40[0x8];
7176 u8 reserved_at_60[0x20];
7179 struct mlx5_ifc_destroy_rq_out_bits {
7181 u8 reserved_at_8[0x18];
7185 u8 reserved_at_40[0x40];
7188 struct mlx5_ifc_destroy_rq_in_bits {
7192 u8 reserved_at_20[0x10];
7195 u8 reserved_at_40[0x8];
7198 u8 reserved_at_60[0x20];
7201 struct mlx5_ifc_set_delay_drop_params_in_bits {
7203 u8 reserved_at_10[0x10];
7205 u8 reserved_at_20[0x10];
7208 u8 reserved_at_40[0x20];
7210 u8 reserved_at_60[0x10];
7211 u8 delay_drop_timeout[0x10];
7214 struct mlx5_ifc_set_delay_drop_params_out_bits {
7216 u8 reserved_at_8[0x18];
7220 u8 reserved_at_40[0x40];
7223 struct mlx5_ifc_destroy_rmp_out_bits {
7225 u8 reserved_at_8[0x18];
7229 u8 reserved_at_40[0x40];
7232 struct mlx5_ifc_destroy_rmp_in_bits {
7236 u8 reserved_at_20[0x10];
7239 u8 reserved_at_40[0x8];
7242 u8 reserved_at_60[0x20];
7245 struct mlx5_ifc_destroy_qp_out_bits {
7247 u8 reserved_at_8[0x18];
7251 u8 reserved_at_40[0x40];
7254 struct mlx5_ifc_destroy_qp_in_bits {
7258 u8 reserved_at_20[0x10];
7261 u8 reserved_at_40[0x8];
7264 u8 reserved_at_60[0x20];
7267 struct mlx5_ifc_destroy_psv_out_bits {
7269 u8 reserved_at_8[0x18];
7273 u8 reserved_at_40[0x40];
7276 struct mlx5_ifc_destroy_psv_in_bits {
7278 u8 reserved_at_10[0x10];
7280 u8 reserved_at_20[0x10];
7283 u8 reserved_at_40[0x8];
7286 u8 reserved_at_60[0x20];
7289 struct mlx5_ifc_destroy_mkey_out_bits {
7291 u8 reserved_at_8[0x18];
7295 u8 reserved_at_40[0x40];
7298 struct mlx5_ifc_destroy_mkey_in_bits {
7302 u8 reserved_at_20[0x10];
7305 u8 reserved_at_40[0x8];
7306 u8 mkey_index[0x18];
7308 u8 reserved_at_60[0x20];
7311 struct mlx5_ifc_destroy_flow_table_out_bits {
7313 u8 reserved_at_8[0x18];
7317 u8 reserved_at_40[0x40];
7320 struct mlx5_ifc_destroy_flow_table_in_bits {
7322 u8 reserved_at_10[0x10];
7324 u8 reserved_at_20[0x10];
7327 u8 other_vport[0x1];
7328 u8 reserved_at_41[0xf];
7329 u8 vport_number[0x10];
7331 u8 reserved_at_60[0x20];
7334 u8 reserved_at_88[0x18];
7336 u8 reserved_at_a0[0x8];
7339 u8 reserved_at_c0[0x140];
7342 struct mlx5_ifc_destroy_flow_group_out_bits {
7344 u8 reserved_at_8[0x18];
7348 u8 reserved_at_40[0x40];
7351 struct mlx5_ifc_destroy_flow_group_in_bits {
7353 u8 reserved_at_10[0x10];
7355 u8 reserved_at_20[0x10];
7358 u8 other_vport[0x1];
7359 u8 reserved_at_41[0xf];
7360 u8 vport_number[0x10];
7362 u8 reserved_at_60[0x20];
7365 u8 reserved_at_88[0x18];
7367 u8 reserved_at_a0[0x8];
7372 u8 reserved_at_e0[0x120];
7375 struct mlx5_ifc_destroy_eq_out_bits {
7377 u8 reserved_at_8[0x18];
7381 u8 reserved_at_40[0x40];
7384 struct mlx5_ifc_destroy_eq_in_bits {
7386 u8 reserved_at_10[0x10];
7388 u8 reserved_at_20[0x10];
7391 u8 reserved_at_40[0x18];
7394 u8 reserved_at_60[0x20];
7397 struct mlx5_ifc_destroy_dct_out_bits {
7399 u8 reserved_at_8[0x18];
7403 u8 reserved_at_40[0x40];
7406 struct mlx5_ifc_destroy_dct_in_bits {
7410 u8 reserved_at_20[0x10];
7413 u8 reserved_at_40[0x8];
7416 u8 reserved_at_60[0x20];
7419 struct mlx5_ifc_destroy_cq_out_bits {
7421 u8 reserved_at_8[0x18];
7425 u8 reserved_at_40[0x40];
7428 struct mlx5_ifc_destroy_cq_in_bits {
7432 u8 reserved_at_20[0x10];
7435 u8 reserved_at_40[0x8];
7438 u8 reserved_at_60[0x20];
7441 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7443 u8 reserved_at_8[0x18];
7447 u8 reserved_at_40[0x40];
7450 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7452 u8 reserved_at_10[0x10];
7454 u8 reserved_at_20[0x10];
7457 u8 reserved_at_40[0x20];
7459 u8 reserved_at_60[0x10];
7460 u8 vxlan_udp_port[0x10];
7463 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7465 u8 reserved_at_8[0x18];
7469 u8 reserved_at_40[0x40];
7472 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7474 u8 reserved_at_10[0x10];
7476 u8 reserved_at_20[0x10];
7479 u8 reserved_at_40[0x60];
7481 u8 reserved_at_a0[0x8];
7482 u8 table_index[0x18];
7484 u8 reserved_at_c0[0x140];
7487 struct mlx5_ifc_delete_fte_out_bits {
7489 u8 reserved_at_8[0x18];
7493 u8 reserved_at_40[0x40];
7496 struct mlx5_ifc_delete_fte_in_bits {
7498 u8 reserved_at_10[0x10];
7500 u8 reserved_at_20[0x10];
7503 u8 other_vport[0x1];
7504 u8 reserved_at_41[0xf];
7505 u8 vport_number[0x10];
7507 u8 reserved_at_60[0x20];
7510 u8 reserved_at_88[0x18];
7512 u8 reserved_at_a0[0x8];
7515 u8 reserved_at_c0[0x40];
7517 u8 flow_index[0x20];
7519 u8 reserved_at_120[0xe0];
7522 struct mlx5_ifc_dealloc_xrcd_out_bits {
7524 u8 reserved_at_8[0x18];
7528 u8 reserved_at_40[0x40];
7531 struct mlx5_ifc_dealloc_xrcd_in_bits {
7535 u8 reserved_at_20[0x10];
7538 u8 reserved_at_40[0x8];
7541 u8 reserved_at_60[0x20];
7544 struct mlx5_ifc_dealloc_uar_out_bits {
7546 u8 reserved_at_8[0x18];
7550 u8 reserved_at_40[0x40];
7553 struct mlx5_ifc_dealloc_uar_in_bits {
7555 u8 reserved_at_10[0x10];
7557 u8 reserved_at_20[0x10];
7560 u8 reserved_at_40[0x8];
7563 u8 reserved_at_60[0x20];
7566 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7568 u8 reserved_at_8[0x18];
7572 u8 reserved_at_40[0x40];
7575 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7579 u8 reserved_at_20[0x10];
7582 u8 reserved_at_40[0x8];
7583 u8 transport_domain[0x18];
7585 u8 reserved_at_60[0x20];
7588 struct mlx5_ifc_dealloc_q_counter_out_bits {
7590 u8 reserved_at_8[0x18];
7594 u8 reserved_at_40[0x40];
7597 struct mlx5_ifc_dealloc_q_counter_in_bits {
7599 u8 reserved_at_10[0x10];
7601 u8 reserved_at_20[0x10];
7604 u8 reserved_at_40[0x18];
7605 u8 counter_set_id[0x8];
7607 u8 reserved_at_60[0x20];
7610 struct mlx5_ifc_dealloc_pd_out_bits {
7612 u8 reserved_at_8[0x18];
7616 u8 reserved_at_40[0x40];
7619 struct mlx5_ifc_dealloc_pd_in_bits {
7623 u8 reserved_at_20[0x10];
7626 u8 reserved_at_40[0x8];
7629 u8 reserved_at_60[0x20];
7632 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7634 u8 reserved_at_8[0x18];
7638 u8 reserved_at_40[0x40];
7641 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7643 u8 reserved_at_10[0x10];
7645 u8 reserved_at_20[0x10];
7648 u8 flow_counter_id[0x20];
7650 u8 reserved_at_60[0x20];
7653 struct mlx5_ifc_create_xrq_out_bits {
7655 u8 reserved_at_8[0x18];
7659 u8 reserved_at_40[0x8];
7662 u8 reserved_at_60[0x20];
7665 struct mlx5_ifc_create_xrq_in_bits {
7669 u8 reserved_at_20[0x10];
7672 u8 reserved_at_40[0x40];
7674 struct mlx5_ifc_xrqc_bits xrq_context;
7677 struct mlx5_ifc_create_xrc_srq_out_bits {
7679 u8 reserved_at_8[0x18];
7683 u8 reserved_at_40[0x8];
7686 u8 reserved_at_60[0x20];
7689 struct mlx5_ifc_create_xrc_srq_in_bits {
7693 u8 reserved_at_20[0x10];
7696 u8 reserved_at_40[0x40];
7698 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7700 u8 reserved_at_280[0x60];
7702 u8 xrc_srq_umem_valid[0x1];
7703 u8 reserved_at_2e1[0x1f];
7705 u8 reserved_at_300[0x580];
7710 struct mlx5_ifc_create_tis_out_bits {
7712 u8 reserved_at_8[0x18];
7716 u8 reserved_at_40[0x8];
7719 u8 reserved_at_60[0x20];
7722 struct mlx5_ifc_create_tis_in_bits {
7726 u8 reserved_at_20[0x10];
7729 u8 reserved_at_40[0xc0];
7731 struct mlx5_ifc_tisc_bits ctx;
7734 struct mlx5_ifc_create_tir_out_bits {
7736 u8 icm_address_63_40[0x18];
7740 u8 icm_address_39_32[0x8];
7743 u8 icm_address_31_0[0x20];
7746 struct mlx5_ifc_create_tir_in_bits {
7750 u8 reserved_at_20[0x10];
7753 u8 reserved_at_40[0xc0];
7755 struct mlx5_ifc_tirc_bits ctx;
7758 struct mlx5_ifc_create_srq_out_bits {
7760 u8 reserved_at_8[0x18];
7764 u8 reserved_at_40[0x8];
7767 u8 reserved_at_60[0x20];
7770 struct mlx5_ifc_create_srq_in_bits {
7774 u8 reserved_at_20[0x10];
7777 u8 reserved_at_40[0x40];
7779 struct mlx5_ifc_srqc_bits srq_context_entry;
7781 u8 reserved_at_280[0x600];
7786 struct mlx5_ifc_create_sq_out_bits {
7788 u8 reserved_at_8[0x18];
7792 u8 reserved_at_40[0x8];
7795 u8 reserved_at_60[0x20];
7798 struct mlx5_ifc_create_sq_in_bits {
7802 u8 reserved_at_20[0x10];
7805 u8 reserved_at_40[0xc0];
7807 struct mlx5_ifc_sqc_bits ctx;
7810 struct mlx5_ifc_create_scheduling_element_out_bits {
7812 u8 reserved_at_8[0x18];
7816 u8 reserved_at_40[0x40];
7818 u8 scheduling_element_id[0x20];
7820 u8 reserved_at_a0[0x160];
7823 struct mlx5_ifc_create_scheduling_element_in_bits {
7825 u8 reserved_at_10[0x10];
7827 u8 reserved_at_20[0x10];
7830 u8 scheduling_hierarchy[0x8];
7831 u8 reserved_at_48[0x18];
7833 u8 reserved_at_60[0xa0];
7835 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7837 u8 reserved_at_300[0x100];
7840 struct mlx5_ifc_create_rqt_out_bits {
7842 u8 reserved_at_8[0x18];
7846 u8 reserved_at_40[0x8];
7849 u8 reserved_at_60[0x20];
7852 struct mlx5_ifc_create_rqt_in_bits {
7856 u8 reserved_at_20[0x10];
7859 u8 reserved_at_40[0xc0];
7861 struct mlx5_ifc_rqtc_bits rqt_context;
7864 struct mlx5_ifc_create_rq_out_bits {
7866 u8 reserved_at_8[0x18];
7870 u8 reserved_at_40[0x8];
7873 u8 reserved_at_60[0x20];
7876 struct mlx5_ifc_create_rq_in_bits {
7880 u8 reserved_at_20[0x10];
7883 u8 reserved_at_40[0xc0];
7885 struct mlx5_ifc_rqc_bits ctx;
7888 struct mlx5_ifc_create_rmp_out_bits {
7890 u8 reserved_at_8[0x18];
7894 u8 reserved_at_40[0x8];
7897 u8 reserved_at_60[0x20];
7900 struct mlx5_ifc_create_rmp_in_bits {
7904 u8 reserved_at_20[0x10];
7907 u8 reserved_at_40[0xc0];
7909 struct mlx5_ifc_rmpc_bits ctx;
7912 struct mlx5_ifc_create_qp_out_bits {
7914 u8 reserved_at_8[0x18];
7918 u8 reserved_at_40[0x8];
7924 struct mlx5_ifc_create_qp_in_bits {
7928 u8 reserved_at_20[0x10];
7931 u8 reserved_at_40[0x8];
7934 u8 reserved_at_60[0x20];
7935 u8 opt_param_mask[0x20];
7939 struct mlx5_ifc_qpc_bits qpc;
7941 u8 reserved_at_800[0x60];
7943 u8 wq_umem_valid[0x1];
7944 u8 reserved_at_861[0x1f];
7949 struct mlx5_ifc_create_psv_out_bits {
7951 u8 reserved_at_8[0x18];
7955 u8 reserved_at_40[0x40];
7957 u8 reserved_at_80[0x8];
7958 u8 psv0_index[0x18];
7960 u8 reserved_at_a0[0x8];
7961 u8 psv1_index[0x18];
7963 u8 reserved_at_c0[0x8];
7964 u8 psv2_index[0x18];
7966 u8 reserved_at_e0[0x8];
7967 u8 psv3_index[0x18];
7970 struct mlx5_ifc_create_psv_in_bits {
7972 u8 reserved_at_10[0x10];
7974 u8 reserved_at_20[0x10];
7978 u8 reserved_at_44[0x4];
7981 u8 reserved_at_60[0x20];
7984 struct mlx5_ifc_create_mkey_out_bits {
7986 u8 reserved_at_8[0x18];
7990 u8 reserved_at_40[0x8];
7991 u8 mkey_index[0x18];
7993 u8 reserved_at_60[0x20];
7996 struct mlx5_ifc_create_mkey_in_bits {
8000 u8 reserved_at_20[0x10];
8003 u8 reserved_at_40[0x20];
8006 u8 mkey_umem_valid[0x1];
8007 u8 reserved_at_62[0x1e];
8009 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8011 u8 reserved_at_280[0x80];
8013 u8 translations_octword_actual_size[0x20];
8015 u8 reserved_at_320[0x560];
8017 u8 klm_pas_mtt[][0x20];
8021 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
8022 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
8023 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
8024 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
8025 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
8026 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
8027 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
8030 struct mlx5_ifc_create_flow_table_out_bits {
8032 u8 icm_address_63_40[0x18];
8036 u8 icm_address_39_32[0x8];
8039 u8 icm_address_31_0[0x20];
8042 struct mlx5_ifc_create_flow_table_in_bits {
8044 u8 reserved_at_10[0x10];
8046 u8 reserved_at_20[0x10];
8049 u8 other_vport[0x1];
8050 u8 reserved_at_41[0xf];
8051 u8 vport_number[0x10];
8053 u8 reserved_at_60[0x20];
8056 u8 reserved_at_88[0x18];
8058 u8 reserved_at_a0[0x20];
8060 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8063 struct mlx5_ifc_create_flow_group_out_bits {
8065 u8 reserved_at_8[0x18];
8069 u8 reserved_at_40[0x8];
8072 u8 reserved_at_60[0x20];
8076 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
8077 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
8078 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
8079 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8082 struct mlx5_ifc_create_flow_group_in_bits {
8084 u8 reserved_at_10[0x10];
8086 u8 reserved_at_20[0x10];
8089 u8 other_vport[0x1];
8090 u8 reserved_at_41[0xf];
8091 u8 vport_number[0x10];
8093 u8 reserved_at_60[0x20];
8096 u8 reserved_at_88[0x18];
8098 u8 reserved_at_a0[0x8];
8101 u8 source_eswitch_owner_vhca_id_valid[0x1];
8103 u8 reserved_at_c1[0x1f];
8105 u8 start_flow_index[0x20];
8107 u8 reserved_at_100[0x20];
8109 u8 end_flow_index[0x20];
8111 u8 reserved_at_140[0xa0];
8113 u8 reserved_at_1e0[0x18];
8114 u8 match_criteria_enable[0x8];
8116 struct mlx5_ifc_fte_match_param_bits match_criteria;
8118 u8 reserved_at_1200[0xe00];
8121 struct mlx5_ifc_create_eq_out_bits {
8123 u8 reserved_at_8[0x18];
8127 u8 reserved_at_40[0x18];
8130 u8 reserved_at_60[0x20];
8133 struct mlx5_ifc_create_eq_in_bits {
8137 u8 reserved_at_20[0x10];
8140 u8 reserved_at_40[0x40];
8142 struct mlx5_ifc_eqc_bits eq_context_entry;
8144 u8 reserved_at_280[0x40];
8146 u8 event_bitmask[4][0x40];
8148 u8 reserved_at_3c0[0x4c0];
8153 struct mlx5_ifc_create_dct_out_bits {
8155 u8 reserved_at_8[0x18];
8159 u8 reserved_at_40[0x8];
8165 struct mlx5_ifc_create_dct_in_bits {
8169 u8 reserved_at_20[0x10];
8172 u8 reserved_at_40[0x40];
8174 struct mlx5_ifc_dctc_bits dct_context_entry;
8176 u8 reserved_at_280[0x180];
8179 struct mlx5_ifc_create_cq_out_bits {
8181 u8 reserved_at_8[0x18];
8185 u8 reserved_at_40[0x8];
8188 u8 reserved_at_60[0x20];
8191 struct mlx5_ifc_create_cq_in_bits {
8195 u8 reserved_at_20[0x10];
8198 u8 reserved_at_40[0x40];
8200 struct mlx5_ifc_cqc_bits cq_context;
8202 u8 reserved_at_280[0x60];
8204 u8 cq_umem_valid[0x1];
8205 u8 reserved_at_2e1[0x59f];
8210 struct mlx5_ifc_config_int_moderation_out_bits {
8212 u8 reserved_at_8[0x18];
8216 u8 reserved_at_40[0x4];
8218 u8 int_vector[0x10];
8220 u8 reserved_at_60[0x20];
8224 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8225 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8228 struct mlx5_ifc_config_int_moderation_in_bits {
8230 u8 reserved_at_10[0x10];
8232 u8 reserved_at_20[0x10];
8235 u8 reserved_at_40[0x4];
8237 u8 int_vector[0x10];
8239 u8 reserved_at_60[0x20];
8242 struct mlx5_ifc_attach_to_mcg_out_bits {
8244 u8 reserved_at_8[0x18];
8248 u8 reserved_at_40[0x40];
8251 struct mlx5_ifc_attach_to_mcg_in_bits {
8255 u8 reserved_at_20[0x10];
8258 u8 reserved_at_40[0x8];
8261 u8 reserved_at_60[0x20];
8263 u8 multicast_gid[16][0x8];
8266 struct mlx5_ifc_arm_xrq_out_bits {
8268 u8 reserved_at_8[0x18];
8272 u8 reserved_at_40[0x40];
8275 struct mlx5_ifc_arm_xrq_in_bits {
8277 u8 reserved_at_10[0x10];
8279 u8 reserved_at_20[0x10];
8282 u8 reserved_at_40[0x8];
8285 u8 reserved_at_60[0x10];
8289 struct mlx5_ifc_arm_xrc_srq_out_bits {
8291 u8 reserved_at_8[0x18];
8295 u8 reserved_at_40[0x40];
8299 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8302 struct mlx5_ifc_arm_xrc_srq_in_bits {
8306 u8 reserved_at_20[0x10];
8309 u8 reserved_at_40[0x8];
8312 u8 reserved_at_60[0x10];
8316 struct mlx5_ifc_arm_rq_out_bits {
8318 u8 reserved_at_8[0x18];
8322 u8 reserved_at_40[0x40];
8326 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8327 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8330 struct mlx5_ifc_arm_rq_in_bits {
8334 u8 reserved_at_20[0x10];
8337 u8 reserved_at_40[0x8];
8338 u8 srq_number[0x18];
8340 u8 reserved_at_60[0x10];
8344 struct mlx5_ifc_arm_dct_out_bits {
8346 u8 reserved_at_8[0x18];
8350 u8 reserved_at_40[0x40];
8353 struct mlx5_ifc_arm_dct_in_bits {
8355 u8 reserved_at_10[0x10];
8357 u8 reserved_at_20[0x10];
8360 u8 reserved_at_40[0x8];
8361 u8 dct_number[0x18];
8363 u8 reserved_at_60[0x20];
8366 struct mlx5_ifc_alloc_xrcd_out_bits {
8368 u8 reserved_at_8[0x18];
8372 u8 reserved_at_40[0x8];
8375 u8 reserved_at_60[0x20];
8378 struct mlx5_ifc_alloc_xrcd_in_bits {
8382 u8 reserved_at_20[0x10];
8385 u8 reserved_at_40[0x40];
8388 struct mlx5_ifc_alloc_uar_out_bits {
8390 u8 reserved_at_8[0x18];
8394 u8 reserved_at_40[0x8];
8397 u8 reserved_at_60[0x20];
8400 struct mlx5_ifc_alloc_uar_in_bits {
8402 u8 reserved_at_10[0x10];
8404 u8 reserved_at_20[0x10];
8407 u8 reserved_at_40[0x40];
8410 struct mlx5_ifc_alloc_transport_domain_out_bits {
8412 u8 reserved_at_8[0x18];
8416 u8 reserved_at_40[0x8];
8417 u8 transport_domain[0x18];
8419 u8 reserved_at_60[0x20];
8422 struct mlx5_ifc_alloc_transport_domain_in_bits {
8426 u8 reserved_at_20[0x10];
8429 u8 reserved_at_40[0x40];
8432 struct mlx5_ifc_alloc_q_counter_out_bits {
8434 u8 reserved_at_8[0x18];
8438 u8 reserved_at_40[0x18];
8439 u8 counter_set_id[0x8];
8441 u8 reserved_at_60[0x20];
8444 struct mlx5_ifc_alloc_q_counter_in_bits {
8448 u8 reserved_at_20[0x10];
8451 u8 reserved_at_40[0x40];
8454 struct mlx5_ifc_alloc_pd_out_bits {
8456 u8 reserved_at_8[0x18];
8460 u8 reserved_at_40[0x8];
8463 u8 reserved_at_60[0x20];
8466 struct mlx5_ifc_alloc_pd_in_bits {
8470 u8 reserved_at_20[0x10];
8473 u8 reserved_at_40[0x40];
8476 struct mlx5_ifc_alloc_flow_counter_out_bits {
8478 u8 reserved_at_8[0x18];
8482 u8 flow_counter_id[0x20];
8484 u8 reserved_at_60[0x20];
8487 struct mlx5_ifc_alloc_flow_counter_in_bits {
8489 u8 reserved_at_10[0x10];
8491 u8 reserved_at_20[0x10];
8494 u8 reserved_at_40[0x38];
8495 u8 flow_counter_bulk[0x8];
8498 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8500 u8 reserved_at_8[0x18];
8504 u8 reserved_at_40[0x40];
8507 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8509 u8 reserved_at_10[0x10];
8511 u8 reserved_at_20[0x10];
8514 u8 reserved_at_40[0x20];
8516 u8 reserved_at_60[0x10];
8517 u8 vxlan_udp_port[0x10];
8520 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8522 u8 reserved_at_8[0x18];
8526 u8 reserved_at_40[0x40];
8529 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8530 u8 rate_limit[0x20];
8532 u8 burst_upper_bound[0x20];
8534 u8 reserved_at_40[0x10];
8535 u8 typical_packet_size[0x10];
8537 u8 reserved_at_60[0x120];
8540 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8544 u8 reserved_at_20[0x10];
8547 u8 reserved_at_40[0x10];
8548 u8 rate_limit_index[0x10];
8550 u8 reserved_at_60[0x20];
8552 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8555 struct mlx5_ifc_access_register_out_bits {
8557 u8 reserved_at_8[0x18];
8561 u8 reserved_at_40[0x40];
8563 u8 register_data[][0x20];
8567 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8568 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8571 struct mlx5_ifc_access_register_in_bits {
8573 u8 reserved_at_10[0x10];
8575 u8 reserved_at_20[0x10];
8578 u8 reserved_at_40[0x10];
8579 u8 register_id[0x10];
8583 u8 register_data[][0x20];
8586 struct mlx5_ifc_sltp_reg_bits {
8591 u8 reserved_at_12[0x2];
8593 u8 reserved_at_18[0x8];
8595 u8 reserved_at_20[0x20];
8597 u8 reserved_at_40[0x7];
8603 u8 reserved_at_60[0xc];
8604 u8 ob_preemp_mode[0x4];
8608 u8 reserved_at_80[0x20];
8611 struct mlx5_ifc_slrg_reg_bits {
8616 u8 reserved_at_12[0x2];
8618 u8 reserved_at_18[0x8];
8620 u8 time_to_link_up[0x10];
8621 u8 reserved_at_30[0xc];
8622 u8 grade_lane_speed[0x4];
8624 u8 grade_version[0x8];
8627 u8 reserved_at_60[0x4];
8628 u8 height_grade_type[0x4];
8629 u8 height_grade[0x18];
8634 u8 reserved_at_a0[0x10];
8635 u8 height_sigma[0x10];
8637 u8 reserved_at_c0[0x20];
8639 u8 reserved_at_e0[0x4];
8640 u8 phase_grade_type[0x4];
8641 u8 phase_grade[0x18];
8643 u8 reserved_at_100[0x8];
8644 u8 phase_eo_pos[0x8];
8645 u8 reserved_at_110[0x8];
8646 u8 phase_eo_neg[0x8];
8648 u8 ffe_set_tested[0x10];
8649 u8 test_errors_per_lane[0x10];
8652 struct mlx5_ifc_pvlc_reg_bits {
8653 u8 reserved_at_0[0x8];
8655 u8 reserved_at_10[0x10];
8657 u8 reserved_at_20[0x1c];
8660 u8 reserved_at_40[0x1c];
8663 u8 reserved_at_60[0x1c];
8664 u8 vl_operational[0x4];
8667 struct mlx5_ifc_pude_reg_bits {
8670 u8 reserved_at_10[0x4];
8671 u8 admin_status[0x4];
8672 u8 reserved_at_18[0x4];
8673 u8 oper_status[0x4];
8675 u8 reserved_at_20[0x60];
8678 struct mlx5_ifc_ptys_reg_bits {
8679 u8 reserved_at_0[0x1];
8680 u8 an_disable_admin[0x1];
8681 u8 an_disable_cap[0x1];
8682 u8 reserved_at_3[0x5];
8684 u8 reserved_at_10[0xd];
8688 u8 reserved_at_24[0xc];
8689 u8 data_rate_oper[0x10];
8691 u8 ext_eth_proto_capability[0x20];
8693 u8 eth_proto_capability[0x20];
8695 u8 ib_link_width_capability[0x10];
8696 u8 ib_proto_capability[0x10];
8698 u8 ext_eth_proto_admin[0x20];
8700 u8 eth_proto_admin[0x20];
8702 u8 ib_link_width_admin[0x10];
8703 u8 ib_proto_admin[0x10];
8705 u8 ext_eth_proto_oper[0x20];
8707 u8 eth_proto_oper[0x20];
8709 u8 ib_link_width_oper[0x10];
8710 u8 ib_proto_oper[0x10];
8712 u8 reserved_at_160[0x1c];
8713 u8 connector_type[0x4];
8715 u8 eth_proto_lp_advertise[0x20];
8717 u8 reserved_at_1a0[0x60];
8720 struct mlx5_ifc_mlcr_reg_bits {
8721 u8 reserved_at_0[0x8];
8723 u8 reserved_at_10[0x20];
8725 u8 beacon_duration[0x10];
8726 u8 reserved_at_40[0x10];
8728 u8 beacon_remain[0x10];
8731 struct mlx5_ifc_ptas_reg_bits {
8732 u8 reserved_at_0[0x20];
8734 u8 algorithm_options[0x10];
8735 u8 reserved_at_30[0x4];
8736 u8 repetitions_mode[0x4];
8737 u8 num_of_repetitions[0x8];
8739 u8 grade_version[0x8];
8740 u8 height_grade_type[0x4];
8741 u8 phase_grade_type[0x4];
8742 u8 height_grade_weight[0x8];
8743 u8 phase_grade_weight[0x8];
8745 u8 gisim_measure_bits[0x10];
8746 u8 adaptive_tap_measure_bits[0x10];
8748 u8 ber_bath_high_error_threshold[0x10];
8749 u8 ber_bath_mid_error_threshold[0x10];
8751 u8 ber_bath_low_error_threshold[0x10];
8752 u8 one_ratio_high_threshold[0x10];
8754 u8 one_ratio_high_mid_threshold[0x10];
8755 u8 one_ratio_low_mid_threshold[0x10];
8757 u8 one_ratio_low_threshold[0x10];
8758 u8 ndeo_error_threshold[0x10];
8760 u8 mixer_offset_step_size[0x10];
8761 u8 reserved_at_110[0x8];
8762 u8 mix90_phase_for_voltage_bath[0x8];
8764 u8 mixer_offset_start[0x10];
8765 u8 mixer_offset_end[0x10];
8767 u8 reserved_at_140[0x15];
8768 u8 ber_test_time[0xb];
8771 struct mlx5_ifc_pspa_reg_bits {
8775 u8 reserved_at_18[0x8];
8777 u8 reserved_at_20[0x20];
8780 struct mlx5_ifc_pqdr_reg_bits {
8781 u8 reserved_at_0[0x8];
8783 u8 reserved_at_10[0x5];
8785 u8 reserved_at_18[0x6];
8788 u8 reserved_at_20[0x20];
8790 u8 reserved_at_40[0x10];
8791 u8 min_threshold[0x10];
8793 u8 reserved_at_60[0x10];
8794 u8 max_threshold[0x10];
8796 u8 reserved_at_80[0x10];
8797 u8 mark_probability_denominator[0x10];
8799 u8 reserved_at_a0[0x60];
8802 struct mlx5_ifc_ppsc_reg_bits {
8803 u8 reserved_at_0[0x8];
8805 u8 reserved_at_10[0x10];
8807 u8 reserved_at_20[0x60];
8809 u8 reserved_at_80[0x1c];
8812 u8 reserved_at_a0[0x1c];
8813 u8 wrps_status[0x4];
8815 u8 reserved_at_c0[0x8];
8816 u8 up_threshold[0x8];
8817 u8 reserved_at_d0[0x8];
8818 u8 down_threshold[0x8];
8820 u8 reserved_at_e0[0x20];
8822 u8 reserved_at_100[0x1c];
8825 u8 reserved_at_120[0x1c];
8826 u8 srps_status[0x4];
8828 u8 reserved_at_140[0x40];
8831 struct mlx5_ifc_pplr_reg_bits {
8832 u8 reserved_at_0[0x8];
8834 u8 reserved_at_10[0x10];
8836 u8 reserved_at_20[0x8];
8838 u8 reserved_at_30[0x8];
8842 struct mlx5_ifc_pplm_reg_bits {
8843 u8 reserved_at_0[0x8];
8845 u8 reserved_at_10[0x10];
8847 u8 reserved_at_20[0x20];
8849 u8 port_profile_mode[0x8];
8850 u8 static_port_profile[0x8];
8851 u8 active_port_profile[0x8];
8852 u8 reserved_at_58[0x8];
8854 u8 retransmission_active[0x8];
8855 u8 fec_mode_active[0x18];
8857 u8 rs_fec_correction_bypass_cap[0x4];
8858 u8 reserved_at_84[0x8];
8859 u8 fec_override_cap_56g[0x4];
8860 u8 fec_override_cap_100g[0x4];
8861 u8 fec_override_cap_50g[0x4];
8862 u8 fec_override_cap_25g[0x4];
8863 u8 fec_override_cap_10g_40g[0x4];
8865 u8 rs_fec_correction_bypass_admin[0x4];
8866 u8 reserved_at_a4[0x8];
8867 u8 fec_override_admin_56g[0x4];
8868 u8 fec_override_admin_100g[0x4];
8869 u8 fec_override_admin_50g[0x4];
8870 u8 fec_override_admin_25g[0x4];
8871 u8 fec_override_admin_10g_40g[0x4];
8873 u8 fec_override_cap_400g_8x[0x10];
8874 u8 fec_override_cap_200g_4x[0x10];
8876 u8 fec_override_cap_100g_2x[0x10];
8877 u8 fec_override_cap_50g_1x[0x10];
8879 u8 fec_override_admin_400g_8x[0x10];
8880 u8 fec_override_admin_200g_4x[0x10];
8882 u8 fec_override_admin_100g_2x[0x10];
8883 u8 fec_override_admin_50g_1x[0x10];
8885 u8 reserved_at_140[0x140];
8888 struct mlx5_ifc_ppcnt_reg_bits {
8892 u8 reserved_at_12[0x8];
8896 u8 reserved_at_21[0x1c];
8899 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8902 struct mlx5_ifc_mpein_reg_bits {
8903 u8 reserved_at_0[0x2];
8907 u8 reserved_at_18[0x8];
8909 u8 capability_mask[0x20];
8911 u8 reserved_at_40[0x8];
8912 u8 link_width_enabled[0x8];
8913 u8 link_speed_enabled[0x10];
8915 u8 lane0_physical_position[0x8];
8916 u8 link_width_active[0x8];
8917 u8 link_speed_active[0x10];
8919 u8 num_of_pfs[0x10];
8920 u8 num_of_vfs[0x10];
8923 u8 reserved_at_b0[0x10];
8925 u8 max_read_request_size[0x4];
8926 u8 max_payload_size[0x4];
8927 u8 reserved_at_c8[0x5];
8930 u8 reserved_at_d4[0xb];
8931 u8 lane_reversal[0x1];
8933 u8 reserved_at_e0[0x14];
8936 u8 reserved_at_100[0x20];
8938 u8 device_status[0x10];
8940 u8 reserved_at_138[0x8];
8942 u8 reserved_at_140[0x10];
8943 u8 receiver_detect_result[0x10];
8945 u8 reserved_at_160[0x20];
8948 struct mlx5_ifc_mpcnt_reg_bits {
8949 u8 reserved_at_0[0x8];
8951 u8 reserved_at_10[0xa];
8955 u8 reserved_at_21[0x1f];
8957 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8960 struct mlx5_ifc_ppad_reg_bits {
8961 u8 reserved_at_0[0x3];
8963 u8 reserved_at_4[0x4];
8969 u8 reserved_at_40[0x40];
8972 struct mlx5_ifc_pmtu_reg_bits {
8973 u8 reserved_at_0[0x8];
8975 u8 reserved_at_10[0x10];
8978 u8 reserved_at_30[0x10];
8981 u8 reserved_at_50[0x10];
8984 u8 reserved_at_70[0x10];
8987 struct mlx5_ifc_pmpr_reg_bits {
8988 u8 reserved_at_0[0x8];
8990 u8 reserved_at_10[0x10];
8992 u8 reserved_at_20[0x18];
8993 u8 attenuation_5g[0x8];
8995 u8 reserved_at_40[0x18];
8996 u8 attenuation_7g[0x8];
8998 u8 reserved_at_60[0x18];
8999 u8 attenuation_12g[0x8];
9002 struct mlx5_ifc_pmpe_reg_bits {
9003 u8 reserved_at_0[0x8];
9005 u8 reserved_at_10[0xc];
9006 u8 module_status[0x4];
9008 u8 reserved_at_20[0x60];
9011 struct mlx5_ifc_pmpc_reg_bits {
9012 u8 module_state_updated[32][0x8];
9015 struct mlx5_ifc_pmlpn_reg_bits {
9016 u8 reserved_at_0[0x4];
9017 u8 mlpn_status[0x4];
9019 u8 reserved_at_10[0x10];
9022 u8 reserved_at_21[0x1f];
9025 struct mlx5_ifc_pmlp_reg_bits {
9027 u8 reserved_at_1[0x7];
9029 u8 reserved_at_10[0x8];
9032 u8 lane0_module_mapping[0x20];
9034 u8 lane1_module_mapping[0x20];
9036 u8 lane2_module_mapping[0x20];
9038 u8 lane3_module_mapping[0x20];
9040 u8 reserved_at_a0[0x160];
9043 struct mlx5_ifc_pmaos_reg_bits {
9044 u8 reserved_at_0[0x8];
9046 u8 reserved_at_10[0x4];
9047 u8 admin_status[0x4];
9048 u8 reserved_at_18[0x4];
9049 u8 oper_status[0x4];
9053 u8 reserved_at_22[0x1c];
9056 u8 reserved_at_40[0x40];
9059 struct mlx5_ifc_plpc_reg_bits {
9060 u8 reserved_at_0[0x4];
9062 u8 reserved_at_10[0x4];
9064 u8 reserved_at_18[0x8];
9066 u8 reserved_at_20[0x10];
9067 u8 lane_speed[0x10];
9069 u8 reserved_at_40[0x17];
9071 u8 fec_mode_policy[0x8];
9073 u8 retransmission_capability[0x8];
9074 u8 fec_mode_capability[0x18];
9076 u8 retransmission_support_admin[0x8];
9077 u8 fec_mode_support_admin[0x18];
9079 u8 retransmission_request_admin[0x8];
9080 u8 fec_mode_request_admin[0x18];
9082 u8 reserved_at_c0[0x80];
9085 struct mlx5_ifc_plib_reg_bits {
9086 u8 reserved_at_0[0x8];
9088 u8 reserved_at_10[0x8];
9091 u8 reserved_at_20[0x60];
9094 struct mlx5_ifc_plbf_reg_bits {
9095 u8 reserved_at_0[0x8];
9097 u8 reserved_at_10[0xd];
9100 u8 reserved_at_20[0x20];
9103 struct mlx5_ifc_pipg_reg_bits {
9104 u8 reserved_at_0[0x8];
9106 u8 reserved_at_10[0x10];
9109 u8 reserved_at_21[0x19];
9111 u8 reserved_at_3e[0x2];
9114 struct mlx5_ifc_pifr_reg_bits {
9115 u8 reserved_at_0[0x8];
9117 u8 reserved_at_10[0x10];
9119 u8 reserved_at_20[0xe0];
9121 u8 port_filter[8][0x20];
9123 u8 port_filter_update_en[8][0x20];
9126 struct mlx5_ifc_pfcc_reg_bits {
9127 u8 reserved_at_0[0x8];
9129 u8 reserved_at_10[0xb];
9130 u8 ppan_mask_n[0x1];
9131 u8 minor_stall_mask[0x1];
9132 u8 critical_stall_mask[0x1];
9133 u8 reserved_at_1e[0x2];
9136 u8 reserved_at_24[0x4];
9137 u8 prio_mask_tx[0x8];
9138 u8 reserved_at_30[0x8];
9139 u8 prio_mask_rx[0x8];
9143 u8 pptx_mask_n[0x1];
9144 u8 reserved_at_43[0x5];
9146 u8 reserved_at_50[0x10];
9150 u8 pprx_mask_n[0x1];
9151 u8 reserved_at_63[0x5];
9153 u8 reserved_at_70[0x10];
9155 u8 device_stall_minor_watermark[0x10];
9156 u8 device_stall_critical_watermark[0x10];
9158 u8 reserved_at_a0[0x60];
9161 struct mlx5_ifc_pelc_reg_bits {
9163 u8 reserved_at_4[0x4];
9165 u8 reserved_at_10[0x10];
9168 u8 op_capability[0x8];
9174 u8 capability[0x40];
9180 u8 reserved_at_140[0x80];
9183 struct mlx5_ifc_peir_reg_bits {
9184 u8 reserved_at_0[0x8];
9186 u8 reserved_at_10[0x10];
9188 u8 reserved_at_20[0xc];
9189 u8 error_count[0x4];
9190 u8 reserved_at_30[0x10];
9192 u8 reserved_at_40[0xc];
9194 u8 reserved_at_50[0x8];
9198 struct mlx5_ifc_mpegc_reg_bits {
9199 u8 reserved_at_0[0x30];
9200 u8 field_select[0x10];
9202 u8 tx_overflow_sense[0x1];
9205 u8 reserved_at_43[0x1b];
9206 u8 tx_lossy_overflow_oper[0x2];
9208 u8 reserved_at_60[0x100];
9212 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1,
9213 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2,
9214 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3,
9217 struct mlx5_ifc_mtutc_reg_bits {
9218 u8 reserved_at_0[0x1c];
9221 u8 freq_adjustment[0x20];
9223 u8 reserved_at_40[0x40];
9227 u8 reserved_at_a0[0x2];
9230 u8 time_adjustment[0x20];
9233 struct mlx5_ifc_pcam_enhanced_features_bits {
9234 u8 reserved_at_0[0x68];
9235 u8 fec_50G_per_lane_in_pplm[0x1];
9236 u8 reserved_at_69[0x4];
9237 u8 rx_icrc_encapsulated_counter[0x1];
9238 u8 reserved_at_6e[0x4];
9239 u8 ptys_extended_ethernet[0x1];
9240 u8 reserved_at_73[0x3];
9242 u8 reserved_at_77[0x3];
9243 u8 per_lane_error_counters[0x1];
9244 u8 rx_buffer_fullness_counters[0x1];
9245 u8 ptys_connector_type[0x1];
9246 u8 reserved_at_7d[0x1];
9247 u8 ppcnt_discard_group[0x1];
9248 u8 ppcnt_statistical_group[0x1];
9251 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9252 u8 port_access_reg_cap_mask_127_to_96[0x20];
9253 u8 port_access_reg_cap_mask_95_to_64[0x20];
9255 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9257 u8 port_access_reg_cap_mask_34_to_32[0x3];
9259 u8 port_access_reg_cap_mask_31_to_13[0x13];
9262 u8 port_access_reg_cap_mask_10_to_09[0x2];
9264 u8 port_access_reg_cap_mask_07_to_00[0x8];
9267 struct mlx5_ifc_pcam_reg_bits {
9268 u8 reserved_at_0[0x8];
9269 u8 feature_group[0x8];
9270 u8 reserved_at_10[0x8];
9271 u8 access_reg_group[0x8];
9273 u8 reserved_at_20[0x20];
9276 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9277 u8 reserved_at_0[0x80];
9278 } port_access_reg_cap_mask;
9280 u8 reserved_at_c0[0x80];
9283 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9284 u8 reserved_at_0[0x80];
9287 u8 reserved_at_1c0[0xc0];
9290 struct mlx5_ifc_mcam_enhanced_features_bits {
9291 u8 reserved_at_0[0x6b];
9292 u8 ptpcyc2realtime_modify[0x1];
9293 u8 reserved_at_6c[0x2];
9294 u8 pci_status_and_power[0x1];
9295 u8 reserved_at_6f[0x5];
9296 u8 mark_tx_action_cnp[0x1];
9297 u8 mark_tx_action_cqe[0x1];
9298 u8 dynamic_tx_overflow[0x1];
9299 u8 reserved_at_77[0x4];
9300 u8 pcie_outbound_stalled[0x1];
9301 u8 tx_overflow_buffer_pkt[0x1];
9302 u8 mtpps_enh_out_per_adj[0x1];
9304 u8 pcie_performance_group[0x1];
9307 struct mlx5_ifc_mcam_access_reg_bits {
9308 u8 reserved_at_0[0x1c];
9314 u8 regs_95_to_87[0x9];
9317 u8 regs_84_to_68[0x11];
9318 u8 tracer_registers[0x4];
9320 u8 regs_63_to_32[0x20];
9321 u8 regs_31_to_0[0x20];
9324 struct mlx5_ifc_mcam_access_reg_bits1 {
9325 u8 regs_127_to_96[0x20];
9327 u8 regs_95_to_64[0x20];
9329 u8 regs_63_to_32[0x20];
9331 u8 regs_31_to_0[0x20];
9334 struct mlx5_ifc_mcam_access_reg_bits2 {
9335 u8 regs_127_to_99[0x1d];
9337 u8 regs_97_to_96[0x2];
9339 u8 regs_95_to_64[0x20];
9341 u8 regs_63_to_32[0x20];
9343 u8 regs_31_to_0[0x20];
9346 struct mlx5_ifc_mcam_reg_bits {
9347 u8 reserved_at_0[0x8];
9348 u8 feature_group[0x8];
9349 u8 reserved_at_10[0x8];
9350 u8 access_reg_group[0x8];
9352 u8 reserved_at_20[0x20];
9355 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9356 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9357 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9358 u8 reserved_at_0[0x80];
9359 } mng_access_reg_cap_mask;
9361 u8 reserved_at_c0[0x80];
9364 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9365 u8 reserved_at_0[0x80];
9366 } mng_feature_cap_mask;
9368 u8 reserved_at_1c0[0x80];
9371 struct mlx5_ifc_qcam_access_reg_cap_mask {
9372 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9374 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9378 u8 qcam_access_reg_cap_mask_0[0x1];
9381 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9382 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9383 u8 qpts_trust_both[0x1];
9386 struct mlx5_ifc_qcam_reg_bits {
9387 u8 reserved_at_0[0x8];
9388 u8 feature_group[0x8];
9389 u8 reserved_at_10[0x8];
9390 u8 access_reg_group[0x8];
9391 u8 reserved_at_20[0x20];
9394 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9395 u8 reserved_at_0[0x80];
9396 } qos_access_reg_cap_mask;
9398 u8 reserved_at_c0[0x80];
9401 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9402 u8 reserved_at_0[0x80];
9403 } qos_feature_cap_mask;
9405 u8 reserved_at_1c0[0x80];
9408 struct mlx5_ifc_core_dump_reg_bits {
9409 u8 reserved_at_0[0x18];
9410 u8 core_dump_type[0x8];
9412 u8 reserved_at_20[0x30];
9415 u8 reserved_at_60[0x8];
9417 u8 reserved_at_80[0x180];
9420 struct mlx5_ifc_pcap_reg_bits {
9421 u8 reserved_at_0[0x8];
9423 u8 reserved_at_10[0x10];
9425 u8 port_capability_mask[4][0x20];
9428 struct mlx5_ifc_paos_reg_bits {
9431 u8 reserved_at_10[0x4];
9432 u8 admin_status[0x4];
9433 u8 reserved_at_18[0x4];
9434 u8 oper_status[0x4];
9438 u8 reserved_at_22[0x1c];
9441 u8 reserved_at_40[0x40];
9444 struct mlx5_ifc_pamp_reg_bits {
9445 u8 reserved_at_0[0x8];
9446 u8 opamp_group[0x8];
9447 u8 reserved_at_10[0xc];
9448 u8 opamp_group_type[0x4];
9450 u8 start_index[0x10];
9451 u8 reserved_at_30[0x4];
9452 u8 num_of_indices[0xc];
9454 u8 index_data[18][0x10];
9457 struct mlx5_ifc_pcmr_reg_bits {
9458 u8 reserved_at_0[0x8];
9460 u8 reserved_at_10[0x10];
9461 u8 entropy_force_cap[0x1];
9462 u8 entropy_calc_cap[0x1];
9463 u8 entropy_gre_calc_cap[0x1];
9464 u8 reserved_at_23[0x1b];
9466 u8 reserved_at_3f[0x1];
9467 u8 entropy_force[0x1];
9468 u8 entropy_calc[0x1];
9469 u8 entropy_gre_calc[0x1];
9470 u8 reserved_at_43[0x1b];
9472 u8 reserved_at_5f[0x1];
9475 struct mlx5_ifc_lane_2_module_mapping_bits {
9476 u8 reserved_at_0[0x6];
9478 u8 reserved_at_8[0x6];
9480 u8 reserved_at_10[0x8];
9484 struct mlx5_ifc_bufferx_reg_bits {
9485 u8 reserved_at_0[0x6];
9488 u8 reserved_at_8[0xc];
9491 u8 xoff_threshold[0x10];
9492 u8 xon_threshold[0x10];
9495 struct mlx5_ifc_set_node_in_bits {
9496 u8 node_description[64][0x8];
9499 struct mlx5_ifc_register_power_settings_bits {
9500 u8 reserved_at_0[0x18];
9501 u8 power_settings_level[0x8];
9503 u8 reserved_at_20[0x60];
9506 struct mlx5_ifc_register_host_endianness_bits {
9508 u8 reserved_at_1[0x1f];
9510 u8 reserved_at_20[0x60];
9513 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9514 u8 reserved_at_0[0x20];
9518 u8 addressh_63_32[0x20];
9520 u8 addressl_31_0[0x20];
9523 struct mlx5_ifc_ud_adrs_vector_bits {
9527 u8 reserved_at_41[0x7];
9528 u8 destination_qp_dct[0x18];
9530 u8 static_rate[0x4];
9531 u8 sl_eth_prio[0x4];
9534 u8 rlid_udp_sport[0x10];
9536 u8 reserved_at_80[0x20];
9538 u8 rmac_47_16[0x20];
9544 u8 reserved_at_e0[0x1];
9546 u8 reserved_at_e2[0x2];
9547 u8 src_addr_index[0x8];
9548 u8 flow_label[0x14];
9550 u8 rgid_rip[16][0x8];
9553 struct mlx5_ifc_pages_req_event_bits {
9554 u8 reserved_at_0[0x10];
9555 u8 function_id[0x10];
9559 u8 reserved_at_40[0xa0];
9562 struct mlx5_ifc_eqe_bits {
9563 u8 reserved_at_0[0x8];
9565 u8 reserved_at_10[0x8];
9566 u8 event_sub_type[0x8];
9568 u8 reserved_at_20[0xe0];
9570 union mlx5_ifc_event_auto_bits event_data;
9572 u8 reserved_at_1e0[0x10];
9574 u8 reserved_at_1f8[0x7];
9579 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9582 struct mlx5_ifc_cmd_queue_entry_bits {
9584 u8 reserved_at_8[0x18];
9586 u8 input_length[0x20];
9588 u8 input_mailbox_pointer_63_32[0x20];
9590 u8 input_mailbox_pointer_31_9[0x17];
9591 u8 reserved_at_77[0x9];
9593 u8 command_input_inline_data[16][0x8];
9595 u8 command_output_inline_data[16][0x8];
9597 u8 output_mailbox_pointer_63_32[0x20];
9599 u8 output_mailbox_pointer_31_9[0x17];
9600 u8 reserved_at_1b7[0x9];
9602 u8 output_length[0x20];
9606 u8 reserved_at_1f0[0x8];
9611 struct mlx5_ifc_cmd_out_bits {
9613 u8 reserved_at_8[0x18];
9617 u8 command_output[0x20];
9620 struct mlx5_ifc_cmd_in_bits {
9622 u8 reserved_at_10[0x10];
9624 u8 reserved_at_20[0x10];
9630 struct mlx5_ifc_cmd_if_box_bits {
9631 u8 mailbox_data[512][0x8];
9633 u8 reserved_at_1000[0x180];
9635 u8 next_pointer_63_32[0x20];
9637 u8 next_pointer_31_10[0x16];
9638 u8 reserved_at_11b6[0xa];
9640 u8 block_number[0x20];
9642 u8 reserved_at_11e0[0x8];
9644 u8 ctrl_signature[0x8];
9648 struct mlx5_ifc_mtt_bits {
9649 u8 ptag_63_32[0x20];
9652 u8 reserved_at_38[0x6];
9657 struct mlx5_ifc_query_wol_rol_out_bits {
9659 u8 reserved_at_8[0x18];
9663 u8 reserved_at_40[0x10];
9667 u8 reserved_at_60[0x20];
9670 struct mlx5_ifc_query_wol_rol_in_bits {
9672 u8 reserved_at_10[0x10];
9674 u8 reserved_at_20[0x10];
9677 u8 reserved_at_40[0x40];
9680 struct mlx5_ifc_set_wol_rol_out_bits {
9682 u8 reserved_at_8[0x18];
9686 u8 reserved_at_40[0x40];
9689 struct mlx5_ifc_set_wol_rol_in_bits {
9691 u8 reserved_at_10[0x10];
9693 u8 reserved_at_20[0x10];
9696 u8 rol_mode_valid[0x1];
9697 u8 wol_mode_valid[0x1];
9698 u8 reserved_at_42[0xe];
9702 u8 reserved_at_60[0x20];
9706 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9707 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9708 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9712 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9713 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9714 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9718 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9719 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9720 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9721 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9722 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9723 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9724 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9725 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9726 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9727 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9728 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9731 struct mlx5_ifc_initial_seg_bits {
9732 u8 fw_rev_minor[0x10];
9733 u8 fw_rev_major[0x10];
9735 u8 cmd_interface_rev[0x10];
9736 u8 fw_rev_subminor[0x10];
9738 u8 reserved_at_40[0x40];
9740 u8 cmdq_phy_addr_63_32[0x20];
9742 u8 cmdq_phy_addr_31_12[0x14];
9743 u8 reserved_at_b4[0x2];
9744 u8 nic_interface[0x2];
9745 u8 log_cmdq_size[0x4];
9746 u8 log_cmdq_stride[0x4];
9748 u8 command_doorbell_vector[0x20];
9750 u8 reserved_at_e0[0xf00];
9752 u8 initializing[0x1];
9753 u8 reserved_at_fe1[0x4];
9754 u8 nic_interface_supported[0x3];
9755 u8 embedded_cpu[0x1];
9756 u8 reserved_at_fe9[0x17];
9758 struct mlx5_ifc_health_buffer_bits health_buffer;
9760 u8 no_dram_nic_offset[0x20];
9762 u8 reserved_at_1220[0x6e40];
9764 u8 reserved_at_8060[0x1f];
9767 u8 health_syndrome[0x8];
9768 u8 health_counter[0x18];
9770 u8 reserved_at_80a0[0x17fc0];
9773 struct mlx5_ifc_mtpps_reg_bits {
9774 u8 reserved_at_0[0xc];
9775 u8 cap_number_of_pps_pins[0x4];
9776 u8 reserved_at_10[0x4];
9777 u8 cap_max_num_of_pps_in_pins[0x4];
9778 u8 reserved_at_18[0x4];
9779 u8 cap_max_num_of_pps_out_pins[0x4];
9781 u8 reserved_at_20[0x24];
9782 u8 cap_pin_3_mode[0x4];
9783 u8 reserved_at_48[0x4];
9784 u8 cap_pin_2_mode[0x4];
9785 u8 reserved_at_50[0x4];
9786 u8 cap_pin_1_mode[0x4];
9787 u8 reserved_at_58[0x4];
9788 u8 cap_pin_0_mode[0x4];
9790 u8 reserved_at_60[0x4];
9791 u8 cap_pin_7_mode[0x4];
9792 u8 reserved_at_68[0x4];
9793 u8 cap_pin_6_mode[0x4];
9794 u8 reserved_at_70[0x4];
9795 u8 cap_pin_5_mode[0x4];
9796 u8 reserved_at_78[0x4];
9797 u8 cap_pin_4_mode[0x4];
9799 u8 field_select[0x20];
9800 u8 reserved_at_a0[0x60];
9803 u8 reserved_at_101[0xb];
9805 u8 reserved_at_110[0x4];
9809 u8 reserved_at_120[0x20];
9811 u8 time_stamp[0x40];
9813 u8 out_pulse_duration[0x10];
9814 u8 out_periodic_adjustment[0x10];
9815 u8 enhanced_out_periodic_adjustment[0x20];
9817 u8 reserved_at_1c0[0x20];
9820 struct mlx5_ifc_mtppse_reg_bits {
9821 u8 reserved_at_0[0x18];
9824 u8 reserved_at_21[0x1b];
9825 u8 event_generation_mode[0x4];
9826 u8 reserved_at_40[0x40];
9829 struct mlx5_ifc_mcqs_reg_bits {
9830 u8 last_index_flag[0x1];
9831 u8 reserved_at_1[0x7];
9833 u8 component_index[0x10];
9835 u8 reserved_at_20[0x10];
9836 u8 identifier[0x10];
9838 u8 reserved_at_40[0x17];
9839 u8 component_status[0x5];
9840 u8 component_update_state[0x4];
9842 u8 last_update_state_changer_type[0x4];
9843 u8 last_update_state_changer_host_id[0x4];
9844 u8 reserved_at_68[0x18];
9847 struct mlx5_ifc_mcqi_cap_bits {
9848 u8 supported_info_bitmask[0x20];
9850 u8 component_size[0x20];
9852 u8 max_component_size[0x20];
9854 u8 log_mcda_word_size[0x4];
9855 u8 reserved_at_64[0xc];
9856 u8 mcda_max_write_size[0x10];
9859 u8 reserved_at_81[0x1];
9860 u8 match_chip_id[0x1];
9862 u8 check_user_timestamp[0x1];
9863 u8 match_base_guid_mac[0x1];
9864 u8 reserved_at_86[0x1a];
9867 struct mlx5_ifc_mcqi_version_bits {
9868 u8 reserved_at_0[0x2];
9869 u8 build_time_valid[0x1];
9870 u8 user_defined_time_valid[0x1];
9871 u8 reserved_at_4[0x14];
9872 u8 version_string_length[0x8];
9876 u8 build_time[0x40];
9878 u8 user_defined_time[0x40];
9880 u8 build_tool_version[0x20];
9882 u8 reserved_at_e0[0x20];
9884 u8 version_string[92][0x8];
9887 struct mlx5_ifc_mcqi_activation_method_bits {
9888 u8 pending_server_ac_power_cycle[0x1];
9889 u8 pending_server_dc_power_cycle[0x1];
9890 u8 pending_server_reboot[0x1];
9891 u8 pending_fw_reset[0x1];
9892 u8 auto_activate[0x1];
9893 u8 all_hosts_sync[0x1];
9894 u8 device_hw_reset[0x1];
9895 u8 reserved_at_7[0x19];
9898 union mlx5_ifc_mcqi_reg_data_bits {
9899 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9900 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9901 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9904 struct mlx5_ifc_mcqi_reg_bits {
9905 u8 read_pending_component[0x1];
9906 u8 reserved_at_1[0xf];
9907 u8 component_index[0x10];
9909 u8 reserved_at_20[0x20];
9911 u8 reserved_at_40[0x1b];
9918 u8 reserved_at_a0[0x10];
9921 union mlx5_ifc_mcqi_reg_data_bits data[];
9924 struct mlx5_ifc_mcc_reg_bits {
9925 u8 reserved_at_0[0x4];
9926 u8 time_elapsed_since_last_cmd[0xc];
9927 u8 reserved_at_10[0x8];
9928 u8 instruction[0x8];
9930 u8 reserved_at_20[0x10];
9931 u8 component_index[0x10];
9933 u8 reserved_at_40[0x8];
9934 u8 update_handle[0x18];
9936 u8 handle_owner_type[0x4];
9937 u8 handle_owner_host_id[0x4];
9938 u8 reserved_at_68[0x1];
9939 u8 control_progress[0x7];
9941 u8 reserved_at_78[0x4];
9942 u8 control_state[0x4];
9944 u8 component_size[0x20];
9946 u8 reserved_at_a0[0x60];
9949 struct mlx5_ifc_mcda_reg_bits {
9950 u8 reserved_at_0[0x8];
9951 u8 update_handle[0x18];
9955 u8 reserved_at_40[0x10];
9958 u8 reserved_at_60[0x20];
9964 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
9965 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
9969 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
9970 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
9971 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
9974 struct mlx5_ifc_mfrl_reg_bits {
9975 u8 reserved_at_0[0x20];
9977 u8 reserved_at_20[0x2];
9978 u8 pci_sync_for_fw_update_start[0x1];
9979 u8 pci_sync_for_fw_update_resp[0x2];
9980 u8 rst_type_sel[0x3];
9981 u8 reserved_at_28[0x8];
9983 u8 reset_level[0x8];
9986 struct mlx5_ifc_mirc_reg_bits {
9987 u8 reserved_at_0[0x18];
9988 u8 status_code[0x8];
9990 u8 reserved_at_20[0x20];
9993 struct mlx5_ifc_pddr_monitor_opcode_bits {
9994 u8 reserved_at_0[0x10];
9995 u8 monitor_opcode[0x10];
9998 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
9999 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10000 u8 reserved_at_0[0x20];
10004 /* Monitor opcodes */
10005 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10008 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10009 u8 reserved_at_0[0x10];
10010 u8 group_opcode[0x10];
10012 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10014 u8 reserved_at_40[0x20];
10016 u8 status_message[59][0x20];
10019 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10020 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10021 u8 reserved_at_0[0x7c0];
10025 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1,
10028 struct mlx5_ifc_pddr_reg_bits {
10029 u8 reserved_at_0[0x8];
10030 u8 local_port[0x8];
10032 u8 reserved_at_12[0xe];
10034 u8 reserved_at_20[0x18];
10035 u8 page_select[0x8];
10037 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10040 union mlx5_ifc_ports_control_registers_document_bits {
10041 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10042 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10043 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10044 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10045 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10046 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10047 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10048 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10049 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10050 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10051 struct mlx5_ifc_pamp_reg_bits pamp_reg;
10052 struct mlx5_ifc_paos_reg_bits paos_reg;
10053 struct mlx5_ifc_pcap_reg_bits pcap_reg;
10054 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10055 struct mlx5_ifc_pddr_reg_bits pddr_reg;
10056 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10057 struct mlx5_ifc_peir_reg_bits peir_reg;
10058 struct mlx5_ifc_pelc_reg_bits pelc_reg;
10059 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10060 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10061 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10062 struct mlx5_ifc_pifr_reg_bits pifr_reg;
10063 struct mlx5_ifc_pipg_reg_bits pipg_reg;
10064 struct mlx5_ifc_plbf_reg_bits plbf_reg;
10065 struct mlx5_ifc_plib_reg_bits plib_reg;
10066 struct mlx5_ifc_plpc_reg_bits plpc_reg;
10067 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10068 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10069 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10070 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10071 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10072 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10073 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10074 struct mlx5_ifc_ppad_reg_bits ppad_reg;
10075 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10076 struct mlx5_ifc_mpein_reg_bits mpein_reg;
10077 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10078 struct mlx5_ifc_pplm_reg_bits pplm_reg;
10079 struct mlx5_ifc_pplr_reg_bits pplr_reg;
10080 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10081 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10082 struct mlx5_ifc_pspa_reg_bits pspa_reg;
10083 struct mlx5_ifc_ptas_reg_bits ptas_reg;
10084 struct mlx5_ifc_ptys_reg_bits ptys_reg;
10085 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10086 struct mlx5_ifc_pude_reg_bits pude_reg;
10087 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10088 struct mlx5_ifc_slrg_reg_bits slrg_reg;
10089 struct mlx5_ifc_sltp_reg_bits sltp_reg;
10090 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10091 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
10092 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
10093 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10094 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
10095 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10096 struct mlx5_ifc_mcc_reg_bits mcc_reg;
10097 struct mlx5_ifc_mcda_reg_bits mcda_reg;
10098 struct mlx5_ifc_mirc_reg_bits mirc_reg;
10099 struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
10100 struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
10101 u8 reserved_at_0[0x60e0];
10104 union mlx5_ifc_debug_enhancements_document_bits {
10105 struct mlx5_ifc_health_buffer_bits health_buffer;
10106 u8 reserved_at_0[0x200];
10109 union mlx5_ifc_uplink_pci_interface_document_bits {
10110 struct mlx5_ifc_initial_seg_bits initial_seg;
10111 u8 reserved_at_0[0x20060];
10114 struct mlx5_ifc_set_flow_table_root_out_bits {
10116 u8 reserved_at_8[0x18];
10120 u8 reserved_at_40[0x40];
10123 struct mlx5_ifc_set_flow_table_root_in_bits {
10125 u8 reserved_at_10[0x10];
10127 u8 reserved_at_20[0x10];
10130 u8 other_vport[0x1];
10131 u8 reserved_at_41[0xf];
10132 u8 vport_number[0x10];
10134 u8 reserved_at_60[0x20];
10136 u8 table_type[0x8];
10137 u8 reserved_at_88[0x7];
10138 u8 table_of_other_vport[0x1];
10139 u8 table_vport_number[0x10];
10141 u8 reserved_at_a0[0x8];
10144 u8 reserved_at_c0[0x8];
10145 u8 underlay_qpn[0x18];
10146 u8 table_eswitch_owner_vhca_id_valid[0x1];
10147 u8 reserved_at_e1[0xf];
10148 u8 table_eswitch_owner_vhca_id[0x10];
10149 u8 reserved_at_100[0x100];
10153 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
10154 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
10157 struct mlx5_ifc_modify_flow_table_out_bits {
10159 u8 reserved_at_8[0x18];
10163 u8 reserved_at_40[0x40];
10166 struct mlx5_ifc_modify_flow_table_in_bits {
10168 u8 reserved_at_10[0x10];
10170 u8 reserved_at_20[0x10];
10173 u8 other_vport[0x1];
10174 u8 reserved_at_41[0xf];
10175 u8 vport_number[0x10];
10177 u8 reserved_at_60[0x10];
10178 u8 modify_field_select[0x10];
10180 u8 table_type[0x8];
10181 u8 reserved_at_88[0x18];
10183 u8 reserved_at_a0[0x8];
10186 struct mlx5_ifc_flow_table_context_bits flow_table_context;
10189 struct mlx5_ifc_ets_tcn_config_reg_bits {
10193 u8 reserved_at_3[0x9];
10195 u8 reserved_at_10[0x9];
10196 u8 bw_allocation[0x7];
10198 u8 reserved_at_20[0xc];
10199 u8 max_bw_units[0x4];
10200 u8 reserved_at_30[0x8];
10201 u8 max_bw_value[0x8];
10204 struct mlx5_ifc_ets_global_config_reg_bits {
10205 u8 reserved_at_0[0x2];
10207 u8 reserved_at_3[0x1d];
10209 u8 reserved_at_20[0xc];
10210 u8 max_bw_units[0x4];
10211 u8 reserved_at_30[0x8];
10212 u8 max_bw_value[0x8];
10215 struct mlx5_ifc_qetc_reg_bits {
10216 u8 reserved_at_0[0x8];
10217 u8 port_number[0x8];
10218 u8 reserved_at_10[0x30];
10220 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
10221 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10224 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10226 u8 reserved_at_01[0x0b];
10230 struct mlx5_ifc_qpdpm_reg_bits {
10231 u8 reserved_at_0[0x8];
10232 u8 local_port[0x8];
10233 u8 reserved_at_10[0x10];
10234 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
10237 struct mlx5_ifc_qpts_reg_bits {
10238 u8 reserved_at_0[0x8];
10239 u8 local_port[0x8];
10240 u8 reserved_at_10[0x2d];
10241 u8 trust_state[0x3];
10244 struct mlx5_ifc_pptb_reg_bits {
10245 u8 reserved_at_0[0x2];
10247 u8 reserved_at_4[0x4];
10248 u8 local_port[0x8];
10249 u8 reserved_at_10[0x6];
10254 u8 prio_x_buff[0x20];
10257 u8 reserved_at_48[0x10];
10259 u8 untagged_buff[0x4];
10262 struct mlx5_ifc_sbcam_reg_bits {
10263 u8 reserved_at_0[0x8];
10264 u8 feature_group[0x8];
10265 u8 reserved_at_10[0x8];
10266 u8 access_reg_group[0x8];
10268 u8 reserved_at_20[0x20];
10270 u8 sb_access_reg_cap_mask[4][0x20];
10272 u8 reserved_at_c0[0x80];
10274 u8 sb_feature_cap_mask[4][0x20];
10276 u8 reserved_at_1c0[0x40];
10278 u8 cap_total_buffer_size[0x20];
10280 u8 cap_cell_size[0x10];
10281 u8 cap_max_pg_buffers[0x8];
10282 u8 cap_num_pool_supported[0x8];
10284 u8 reserved_at_240[0x8];
10285 u8 cap_sbsr_stat_size[0x8];
10286 u8 cap_max_tclass_data[0x8];
10287 u8 cap_max_cpu_ingress_tclass_sb[0x8];
10290 struct mlx5_ifc_pbmc_reg_bits {
10291 u8 reserved_at_0[0x8];
10292 u8 local_port[0x8];
10293 u8 reserved_at_10[0x10];
10295 u8 xoff_timer_value[0x10];
10296 u8 xoff_refresh[0x10];
10298 u8 reserved_at_40[0x9];
10299 u8 fullness_threshold[0x7];
10300 u8 port_buffer_size[0x10];
10302 struct mlx5_ifc_bufferx_reg_bits buffer[10];
10304 u8 reserved_at_2e0[0x80];
10307 struct mlx5_ifc_qtct_reg_bits {
10308 u8 reserved_at_0[0x8];
10309 u8 port_number[0x8];
10310 u8 reserved_at_10[0xd];
10313 u8 reserved_at_20[0x1d];
10317 struct mlx5_ifc_mcia_reg_bits {
10319 u8 reserved_at_1[0x7];
10321 u8 reserved_at_10[0x8];
10324 u8 i2c_device_address[0x8];
10325 u8 page_number[0x8];
10326 u8 device_address[0x10];
10328 u8 reserved_at_40[0x10];
10331 u8 reserved_at_60[0x20];
10347 struct mlx5_ifc_dcbx_param_bits {
10348 u8 dcbx_cee_cap[0x1];
10349 u8 dcbx_ieee_cap[0x1];
10350 u8 dcbx_standby_cap[0x1];
10351 u8 reserved_at_3[0x5];
10352 u8 port_number[0x8];
10353 u8 reserved_at_10[0xa];
10354 u8 max_application_table_size[6];
10355 u8 reserved_at_20[0x15];
10356 u8 version_oper[0x3];
10357 u8 reserved_at_38[5];
10358 u8 version_admin[0x3];
10359 u8 willing_admin[0x1];
10360 u8 reserved_at_41[0x3];
10361 u8 pfc_cap_oper[0x4];
10362 u8 reserved_at_48[0x4];
10363 u8 pfc_cap_admin[0x4];
10364 u8 reserved_at_50[0x4];
10365 u8 num_of_tc_oper[0x4];
10366 u8 reserved_at_58[0x4];
10367 u8 num_of_tc_admin[0x4];
10368 u8 remote_willing[0x1];
10369 u8 reserved_at_61[3];
10370 u8 remote_pfc_cap[4];
10371 u8 reserved_at_68[0x14];
10372 u8 remote_num_of_tc[0x4];
10373 u8 reserved_at_80[0x18];
10375 u8 reserved_at_a0[0x160];
10378 struct mlx5_ifc_lagc_bits {
10379 u8 fdb_selection_mode[0x1];
10380 u8 reserved_at_1[0x1c];
10383 u8 reserved_at_20[0x14];
10384 u8 tx_remap_affinity_2[0x4];
10385 u8 reserved_at_38[0x4];
10386 u8 tx_remap_affinity_1[0x4];
10389 struct mlx5_ifc_create_lag_out_bits {
10391 u8 reserved_at_8[0x18];
10395 u8 reserved_at_40[0x40];
10398 struct mlx5_ifc_create_lag_in_bits {
10400 u8 reserved_at_10[0x10];
10402 u8 reserved_at_20[0x10];
10405 struct mlx5_ifc_lagc_bits ctx;
10408 struct mlx5_ifc_modify_lag_out_bits {
10410 u8 reserved_at_8[0x18];
10414 u8 reserved_at_40[0x40];
10417 struct mlx5_ifc_modify_lag_in_bits {
10419 u8 reserved_at_10[0x10];
10421 u8 reserved_at_20[0x10];
10424 u8 reserved_at_40[0x20];
10425 u8 field_select[0x20];
10427 struct mlx5_ifc_lagc_bits ctx;
10430 struct mlx5_ifc_query_lag_out_bits {
10432 u8 reserved_at_8[0x18];
10436 struct mlx5_ifc_lagc_bits ctx;
10439 struct mlx5_ifc_query_lag_in_bits {
10441 u8 reserved_at_10[0x10];
10443 u8 reserved_at_20[0x10];
10446 u8 reserved_at_40[0x40];
10449 struct mlx5_ifc_destroy_lag_out_bits {
10451 u8 reserved_at_8[0x18];
10455 u8 reserved_at_40[0x40];
10458 struct mlx5_ifc_destroy_lag_in_bits {
10460 u8 reserved_at_10[0x10];
10462 u8 reserved_at_20[0x10];
10465 u8 reserved_at_40[0x40];
10468 struct mlx5_ifc_create_vport_lag_out_bits {
10470 u8 reserved_at_8[0x18];
10474 u8 reserved_at_40[0x40];
10477 struct mlx5_ifc_create_vport_lag_in_bits {
10479 u8 reserved_at_10[0x10];
10481 u8 reserved_at_20[0x10];
10484 u8 reserved_at_40[0x40];
10487 struct mlx5_ifc_destroy_vport_lag_out_bits {
10489 u8 reserved_at_8[0x18];
10493 u8 reserved_at_40[0x40];
10496 struct mlx5_ifc_destroy_vport_lag_in_bits {
10498 u8 reserved_at_10[0x10];
10500 u8 reserved_at_20[0x10];
10503 u8 reserved_at_40[0x40];
10507 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
10508 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
10511 struct mlx5_ifc_modify_memic_in_bits {
10515 u8 reserved_at_20[0x10];
10518 u8 reserved_at_40[0x20];
10520 u8 reserved_at_60[0x18];
10521 u8 memic_operation_type[0x8];
10523 u8 memic_start_addr[0x40];
10525 u8 reserved_at_c0[0x140];
10528 struct mlx5_ifc_modify_memic_out_bits {
10530 u8 reserved_at_8[0x18];
10534 u8 reserved_at_40[0x40];
10536 u8 memic_operation_addr[0x40];
10538 u8 reserved_at_c0[0x140];
10541 struct mlx5_ifc_alloc_memic_in_bits {
10543 u8 reserved_at_10[0x10];
10545 u8 reserved_at_20[0x10];
10548 u8 reserved_at_30[0x20];
10550 u8 reserved_at_40[0x18];
10551 u8 log_memic_addr_alignment[0x8];
10553 u8 range_start_addr[0x40];
10555 u8 range_size[0x20];
10557 u8 memic_size[0x20];
10560 struct mlx5_ifc_alloc_memic_out_bits {
10562 u8 reserved_at_8[0x18];
10566 u8 memic_start_addr[0x40];
10569 struct mlx5_ifc_dealloc_memic_in_bits {
10571 u8 reserved_at_10[0x10];
10573 u8 reserved_at_20[0x10];
10576 u8 reserved_at_40[0x40];
10578 u8 memic_start_addr[0x40];
10580 u8 memic_size[0x20];
10582 u8 reserved_at_e0[0x20];
10585 struct mlx5_ifc_dealloc_memic_out_bits {
10587 u8 reserved_at_8[0x18];
10591 u8 reserved_at_40[0x40];
10594 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10598 u8 vhca_tunnel_id[0x10];
10603 u8 reserved_at_60[0x20];
10606 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10608 u8 reserved_at_8[0x18];
10614 u8 reserved_at_60[0x20];
10617 struct mlx5_ifc_umem_bits {
10618 u8 reserved_at_0[0x80];
10620 u8 reserved_at_80[0x1b];
10621 u8 log_page_size[0x5];
10623 u8 page_offset[0x20];
10625 u8 num_of_mtt[0x40];
10627 struct mlx5_ifc_mtt_bits mtt[];
10630 struct mlx5_ifc_uctx_bits {
10633 u8 reserved_at_20[0x160];
10636 struct mlx5_ifc_sw_icm_bits {
10637 u8 modify_field_select[0x40];
10639 u8 reserved_at_40[0x18];
10640 u8 log_sw_icm_size[0x8];
10642 u8 reserved_at_60[0x20];
10644 u8 sw_icm_start_addr[0x40];
10646 u8 reserved_at_c0[0x140];
10649 struct mlx5_ifc_geneve_tlv_option_bits {
10650 u8 modify_field_select[0x40];
10652 u8 reserved_at_40[0x18];
10653 u8 geneve_option_fte_index[0x8];
10655 u8 option_class[0x10];
10656 u8 option_type[0x8];
10657 u8 reserved_at_78[0x3];
10658 u8 option_data_length[0x5];
10660 u8 reserved_at_80[0x180];
10663 struct mlx5_ifc_create_umem_in_bits {
10667 u8 reserved_at_20[0x10];
10670 u8 reserved_at_40[0x40];
10672 struct mlx5_ifc_umem_bits umem;
10675 struct mlx5_ifc_create_umem_out_bits {
10677 u8 reserved_at_8[0x18];
10681 u8 reserved_at_40[0x8];
10684 u8 reserved_at_60[0x20];
10687 struct mlx5_ifc_destroy_umem_in_bits {
10691 u8 reserved_at_20[0x10];
10694 u8 reserved_at_40[0x8];
10697 u8 reserved_at_60[0x20];
10700 struct mlx5_ifc_destroy_umem_out_bits {
10702 u8 reserved_at_8[0x18];
10706 u8 reserved_at_40[0x40];
10709 struct mlx5_ifc_create_uctx_in_bits {
10711 u8 reserved_at_10[0x10];
10713 u8 reserved_at_20[0x10];
10716 u8 reserved_at_40[0x40];
10718 struct mlx5_ifc_uctx_bits uctx;
10721 struct mlx5_ifc_create_uctx_out_bits {
10723 u8 reserved_at_8[0x18];
10727 u8 reserved_at_40[0x10];
10730 u8 reserved_at_60[0x20];
10733 struct mlx5_ifc_destroy_uctx_in_bits {
10735 u8 reserved_at_10[0x10];
10737 u8 reserved_at_20[0x10];
10740 u8 reserved_at_40[0x10];
10743 u8 reserved_at_60[0x20];
10746 struct mlx5_ifc_destroy_uctx_out_bits {
10748 u8 reserved_at_8[0x18];
10752 u8 reserved_at_40[0x40];
10755 struct mlx5_ifc_create_sw_icm_in_bits {
10756 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10757 struct mlx5_ifc_sw_icm_bits sw_icm;
10760 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10761 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10762 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
10765 struct mlx5_ifc_mtrc_string_db_param_bits {
10766 u8 string_db_base_address[0x20];
10768 u8 reserved_at_20[0x8];
10769 u8 string_db_size[0x18];
10772 struct mlx5_ifc_mtrc_cap_bits {
10773 u8 trace_owner[0x1];
10774 u8 trace_to_memory[0x1];
10775 u8 reserved_at_2[0x4];
10777 u8 reserved_at_8[0x14];
10778 u8 num_string_db[0x4];
10780 u8 first_string_trace[0x8];
10781 u8 num_string_trace[0x8];
10782 u8 reserved_at_30[0x28];
10784 u8 log_max_trace_buffer_size[0x8];
10786 u8 reserved_at_60[0x20];
10788 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10790 u8 reserved_at_280[0x180];
10793 struct mlx5_ifc_mtrc_conf_bits {
10794 u8 reserved_at_0[0x1c];
10795 u8 trace_mode[0x4];
10796 u8 reserved_at_20[0x18];
10797 u8 log_trace_buffer_size[0x8];
10798 u8 trace_mkey[0x20];
10799 u8 reserved_at_60[0x3a0];
10802 struct mlx5_ifc_mtrc_stdb_bits {
10803 u8 string_db_index[0x4];
10804 u8 reserved_at_4[0x4];
10805 u8 read_size[0x18];
10806 u8 start_offset[0x20];
10807 u8 string_db_data[];
10810 struct mlx5_ifc_mtrc_ctrl_bits {
10811 u8 trace_status[0x2];
10812 u8 reserved_at_2[0x2];
10814 u8 reserved_at_5[0xb];
10815 u8 modify_field_select[0x10];
10816 u8 reserved_at_20[0x2b];
10817 u8 current_timestamp52_32[0x15];
10818 u8 current_timestamp31_0[0x20];
10819 u8 reserved_at_80[0x180];
10822 struct mlx5_ifc_host_params_context_bits {
10823 u8 host_number[0x8];
10824 u8 reserved_at_8[0x7];
10825 u8 host_pf_disabled[0x1];
10826 u8 host_num_of_vfs[0x10];
10828 u8 host_total_vfs[0x10];
10829 u8 host_pci_bus[0x10];
10831 u8 reserved_at_40[0x10];
10832 u8 host_pci_device[0x10];
10834 u8 reserved_at_60[0x10];
10835 u8 host_pci_function[0x10];
10837 u8 reserved_at_80[0x180];
10840 struct mlx5_ifc_query_esw_functions_in_bits {
10842 u8 reserved_at_10[0x10];
10844 u8 reserved_at_20[0x10];
10847 u8 reserved_at_40[0x40];
10850 struct mlx5_ifc_query_esw_functions_out_bits {
10852 u8 reserved_at_8[0x18];
10856 u8 reserved_at_40[0x40];
10858 struct mlx5_ifc_host_params_context_bits host_params_context;
10860 u8 reserved_at_280[0x180];
10861 u8 host_sf_enable[][0x40];
10864 struct mlx5_ifc_sf_partition_bits {
10865 u8 reserved_at_0[0x10];
10866 u8 log_num_sf[0x8];
10867 u8 log_sf_bar_size[0x8];
10870 struct mlx5_ifc_query_sf_partitions_out_bits {
10872 u8 reserved_at_8[0x18];
10876 u8 reserved_at_40[0x18];
10877 u8 num_sf_partitions[0x8];
10879 u8 reserved_at_60[0x20];
10881 struct mlx5_ifc_sf_partition_bits sf_partition[];
10884 struct mlx5_ifc_query_sf_partitions_in_bits {
10886 u8 reserved_at_10[0x10];
10888 u8 reserved_at_20[0x10];
10891 u8 reserved_at_40[0x40];
10894 struct mlx5_ifc_dealloc_sf_out_bits {
10896 u8 reserved_at_8[0x18];
10900 u8 reserved_at_40[0x40];
10903 struct mlx5_ifc_dealloc_sf_in_bits {
10905 u8 reserved_at_10[0x10];
10907 u8 reserved_at_20[0x10];
10910 u8 reserved_at_40[0x10];
10911 u8 function_id[0x10];
10913 u8 reserved_at_60[0x20];
10916 struct mlx5_ifc_alloc_sf_out_bits {
10918 u8 reserved_at_8[0x18];
10922 u8 reserved_at_40[0x40];
10925 struct mlx5_ifc_alloc_sf_in_bits {
10927 u8 reserved_at_10[0x10];
10929 u8 reserved_at_20[0x10];
10932 u8 reserved_at_40[0x10];
10933 u8 function_id[0x10];
10935 u8 reserved_at_60[0x20];
10938 struct mlx5_ifc_affiliated_event_header_bits {
10939 u8 reserved_at_0[0x10];
10946 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
10947 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
10948 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
10952 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10953 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
10954 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
10958 MLX5_IPSEC_OBJECT_ICV_LEN_16B,
10959 MLX5_IPSEC_OBJECT_ICV_LEN_12B,
10960 MLX5_IPSEC_OBJECT_ICV_LEN_8B,
10963 struct mlx5_ifc_ipsec_obj_bits {
10964 u8 modify_field_select[0x40];
10965 u8 full_offload[0x1];
10966 u8 reserved_at_41[0x1];
10968 u8 esn_overlap[0x1];
10969 u8 reserved_at_44[0x2];
10970 u8 icv_length[0x2];
10971 u8 reserved_at_48[0x4];
10972 u8 aso_return_reg[0x4];
10973 u8 reserved_at_50[0x10];
10977 u8 reserved_at_80[0x8];
10982 u8 implicit_iv[0x40];
10984 u8 reserved_at_100[0x700];
10987 struct mlx5_ifc_create_ipsec_obj_in_bits {
10988 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10989 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10993 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
10994 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
10997 struct mlx5_ifc_query_ipsec_obj_out_bits {
10998 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
10999 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11002 struct mlx5_ifc_modify_ipsec_obj_in_bits {
11003 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11004 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11007 struct mlx5_ifc_encryption_key_obj_bits {
11008 u8 modify_field_select[0x40];
11010 u8 reserved_at_40[0x14];
11012 u8 reserved_at_58[0x4];
11015 u8 reserved_at_60[0x8];
11018 u8 reserved_at_80[0x180];
11021 u8 reserved_at_300[0x500];
11024 struct mlx5_ifc_create_encryption_key_in_bits {
11025 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11026 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11029 struct mlx5_ifc_sampler_obj_bits {
11030 u8 modify_field_select[0x40];
11032 u8 table_type[0x8];
11034 u8 reserved_at_50[0xf];
11035 u8 ignore_flow_level[0x1];
11037 u8 sample_ratio[0x20];
11039 u8 reserved_at_80[0x8];
11040 u8 sample_table_id[0x18];
11042 u8 reserved_at_a0[0x8];
11043 u8 default_table_id[0x18];
11045 u8 sw_steering_icm_address_rx[0x40];
11046 u8 sw_steering_icm_address_tx[0x40];
11048 u8 reserved_at_140[0xa0];
11051 struct mlx5_ifc_create_sampler_obj_in_bits {
11052 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11053 struct mlx5_ifc_sampler_obj_bits sampler_object;
11057 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11058 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11062 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11063 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
11066 struct mlx5_ifc_tls_static_params_bits {
11068 u8 tls_version[0x4];
11070 u8 reserved_at_8[0x14];
11071 u8 encryption_standard[0x4];
11073 u8 reserved_at_20[0x20];
11075 u8 initial_record_number[0x40];
11077 u8 resync_tcp_sn[0x20];
11081 u8 implicit_iv[0x40];
11083 u8 reserved_at_100[0x8];
11084 u8 dek_index[0x18];
11086 u8 reserved_at_120[0xe0];
11089 struct mlx5_ifc_tls_progress_params_bits {
11090 u8 next_record_tcp_sn[0x20];
11092 u8 hw_resync_tcp_sn[0x20];
11094 u8 record_tracker_state[0x2];
11095 u8 auth_state[0x2];
11096 u8 reserved_at_44[0x4];
11097 u8 hw_offset_record_number[0x18];
11101 MLX5_MTT_PERM_READ = 1 << 0,
11102 MLX5_MTT_PERM_WRITE = 1 << 1,
11103 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11106 #endif /* MLX5_IFC_H */